1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012 ARM Ltd. 4 * Author: Catalin Marinas <catalin.marinas@arm.com> 5 */ 6 7 #include <linux/gfp.h> 8 #include <linux/cache.h> 9 #include <linux/dma-map-ops.h> 10 #include <xen/xen.h> 11 12 #include <asm/cacheflush.h> 13 #include <asm/xen/xen-ops.h> 14 15 void arch_sync_dma_for_device(phys_addr_t paddr, size_t size, 16 enum dma_data_direction dir) 17 { 18 unsigned long start = (unsigned long)phys_to_virt(paddr); 19 20 dcache_clean_poc_nosync(start, start + size); 21 } 22 23 void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size, 24 enum dma_data_direction dir) 25 { 26 unsigned long start = (unsigned long)phys_to_virt(paddr); 27 28 if (dir == DMA_TO_DEVICE) 29 return; 30 31 dcache_inval_poc_nosync(start, start + size); 32 } 33 34 void arch_dma_prep_coherent(struct page *page, size_t size) 35 { 36 unsigned long start = (unsigned long)page_address(page); 37 38 dcache_clean_poc(start, start + size); 39 } 40 41 void arch_setup_dma_ops(struct device *dev, bool coherent) 42 { 43 int cls = cache_line_size_of_cpu(); 44 45 if (!coherent && !CLIDR_LOC(read_sysreg(clidr_el1))) { 46 dev_warn(dev, "CLIDR_EL1.LoC == 0, treating as coherent\n"); 47 coherent = true; 48 } 49 50 WARN_TAINT(!coherent && cls > ARCH_DMA_MINALIGN, 51 TAINT_CPU_OUT_OF_SPEC, 52 "%s %s: ARCH_DMA_MINALIGN smaller than CTR_EL0.CWG (%d < %d)", 53 dev_driver_string(dev), dev_name(dev), 54 ARCH_DMA_MINALIGN, cls); 55 56 dev_assign_dma_coherent(dev, coherent); 57 58 xen_setup_dma_ops(dev); 59 } 60