1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012 ARM Ltd. 4 * Author: Catalin Marinas <catalin.marinas@arm.com> 5 */ 6 7 #include <linux/gfp.h> 8 #include <linux/cache.h> 9 #include <linux/dma-noncoherent.h> 10 #include <linux/dma-iommu.h> 11 12 #include <asm/cacheflush.h> 13 14 pgprot_t arch_dma_mmap_pgprot(struct device *dev, pgprot_t prot, 15 unsigned long attrs) 16 { 17 return pgprot_writecombine(prot); 18 } 19 20 void arch_sync_dma_for_device(struct device *dev, phys_addr_t paddr, 21 size_t size, enum dma_data_direction dir) 22 { 23 __dma_map_area(phys_to_virt(paddr), size, dir); 24 } 25 26 void arch_sync_dma_for_cpu(struct device *dev, phys_addr_t paddr, 27 size_t size, enum dma_data_direction dir) 28 { 29 __dma_unmap_area(phys_to_virt(paddr), size, dir); 30 } 31 32 void arch_dma_prep_coherent(struct page *page, size_t size) 33 { 34 __dma_flush_area(page_address(page), size); 35 } 36 37 static int __init arm64_dma_init(void) 38 { 39 return dma_atomic_pool_init(GFP_DMA32, __pgprot(PROT_NORMAL_NC)); 40 } 41 arch_initcall(arm64_dma_init); 42 43 #ifdef CONFIG_IOMMU_DMA 44 void arch_teardown_dma_ops(struct device *dev) 45 { 46 dev->dma_ops = NULL; 47 } 48 #endif 49 50 void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, 51 const struct iommu_ops *iommu, bool coherent) 52 { 53 int cls = cache_line_size_of_cpu(); 54 55 WARN_TAINT(!coherent && cls > ARCH_DMA_MINALIGN, 56 TAINT_CPU_OUT_OF_SPEC, 57 "%s %s: ARCH_DMA_MINALIGN smaller than CTR_EL0.CWG (%d < %d)", 58 dev_driver_string(dev), dev_name(dev), 59 ARCH_DMA_MINALIGN, cls); 60 61 dev->dma_coherent = coherent; 62 if (iommu) 63 iommu_setup_dma_ops(dev, dma_base, size); 64 65 #ifdef CONFIG_XEN 66 if (xen_initial_domain()) 67 dev->dma_ops = xen_dma_ops; 68 #endif 69 } 70