xref: /linux/arch/arm64/lib/Makefile (revision fd639726bf15fca8ee1a00dce8e0096d0ad9bd18)
1# SPDX-License-Identifier: GPL-2.0
2lib-y		:= bitops.o clear_user.o delay.o copy_from_user.o	\
3		   copy_to_user.o copy_in_user.o copy_page.o		\
4		   clear_page.o memchr.o memcpy.o memmove.o memset.o	\
5		   memcmp.o strcmp.o strncmp.o strlen.o strnlen.o	\
6		   strchr.o strrchr.o tishift.o
7
8# Tell the compiler to treat all general purpose registers (with the
9# exception of the IP registers, which are already handled by the caller
10# in case of a PLT) as callee-saved, which allows for efficient runtime
11# patching of the bl instruction in the caller with an atomic instruction
12# when supported by the CPU. Result and argument registers are handled
13# correctly, based on the function prototype.
14lib-$(CONFIG_ARM64_LSE_ATOMICS) += atomic_ll_sc.o
15CFLAGS_atomic_ll_sc.o	:= -fcall-used-x0 -ffixed-x1 -ffixed-x2		\
16		   -ffixed-x3 -ffixed-x4 -ffixed-x5 -ffixed-x6		\
17		   -ffixed-x7 -fcall-saved-x8 -fcall-saved-x9		\
18		   -fcall-saved-x10 -fcall-saved-x11 -fcall-saved-x12	\
19		   -fcall-saved-x13 -fcall-saved-x14 -fcall-saved-x15	\
20		   -fcall-saved-x18
21
22lib-$(CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE) += uaccess_flushcache.o
23