1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2015, 2016 ARM Ltd. 4 */ 5 #ifndef __KVM_ARM_VGIC_NEW_H__ 6 #define __KVM_ARM_VGIC_NEW_H__ 7 8 #include <linux/irqchip/arm-gic-common.h> 9 #include <asm/kvm_mmu.h> 10 11 #define PRODUCT_ID_KVM 0x4b /* ASCII code K */ 12 #define IMPLEMENTER_ARM 0x43b 13 14 #define VGIC_ADDR_UNDEF (-1) 15 #define IS_VGIC_ADDR_UNDEF(_x) ((_x) == VGIC_ADDR_UNDEF) 16 17 #define INTERRUPT_ID_BITS_SPIS 10 18 #define INTERRUPT_ID_BITS_ITS 16 19 #define VGIC_LPI_MAX_INTID ((1 << INTERRUPT_ID_BITS_ITS) - 1) 20 #define VGIC_PRI_BITS 5 21 22 #define vgic_irq_is_sgi(intid) ((intid) < VGIC_NR_SGIS) 23 24 #define VGIC_AFFINITY_0_SHIFT 0 25 #define VGIC_AFFINITY_0_MASK (0xffUL << VGIC_AFFINITY_0_SHIFT) 26 #define VGIC_AFFINITY_1_SHIFT 8 27 #define VGIC_AFFINITY_1_MASK (0xffUL << VGIC_AFFINITY_1_SHIFT) 28 #define VGIC_AFFINITY_2_SHIFT 16 29 #define VGIC_AFFINITY_2_MASK (0xffUL << VGIC_AFFINITY_2_SHIFT) 30 #define VGIC_AFFINITY_3_SHIFT 24 31 #define VGIC_AFFINITY_3_MASK (0xffUL << VGIC_AFFINITY_3_SHIFT) 32 33 #define VGIC_AFFINITY_LEVEL(reg, level) \ 34 ((((reg) & VGIC_AFFINITY_## level ##_MASK) \ 35 >> VGIC_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level)) 36 37 /* 38 * The Userspace encodes the affinity differently from the MPIDR, 39 * Below macro converts vgic userspace format to MPIDR reg format. 40 */ 41 #define VGIC_TO_MPIDR(val) (VGIC_AFFINITY_LEVEL(val, 0) | \ 42 VGIC_AFFINITY_LEVEL(val, 1) | \ 43 VGIC_AFFINITY_LEVEL(val, 2) | \ 44 VGIC_AFFINITY_LEVEL(val, 3)) 45 46 /* 47 * As per Documentation/virt/kvm/devices/arm-vgic-v3.rst, 48 * below macros are defined for CPUREG encoding. 49 */ 50 #define KVM_REG_ARM_VGIC_SYSREG_OP0_MASK 0x000000000000c000 51 #define KVM_REG_ARM_VGIC_SYSREG_OP0_SHIFT 14 52 #define KVM_REG_ARM_VGIC_SYSREG_OP1_MASK 0x0000000000003800 53 #define KVM_REG_ARM_VGIC_SYSREG_OP1_SHIFT 11 54 #define KVM_REG_ARM_VGIC_SYSREG_CRN_MASK 0x0000000000000780 55 #define KVM_REG_ARM_VGIC_SYSREG_CRN_SHIFT 7 56 #define KVM_REG_ARM_VGIC_SYSREG_CRM_MASK 0x0000000000000078 57 #define KVM_REG_ARM_VGIC_SYSREG_CRM_SHIFT 3 58 #define KVM_REG_ARM_VGIC_SYSREG_OP2_MASK 0x0000000000000007 59 #define KVM_REG_ARM_VGIC_SYSREG_OP2_SHIFT 0 60 61 #define KVM_DEV_ARM_VGIC_SYSREG_MASK (KVM_REG_ARM_VGIC_SYSREG_OP0_MASK | \ 62 KVM_REG_ARM_VGIC_SYSREG_OP1_MASK | \ 63 KVM_REG_ARM_VGIC_SYSREG_CRN_MASK | \ 64 KVM_REG_ARM_VGIC_SYSREG_CRM_MASK | \ 65 KVM_REG_ARM_VGIC_SYSREG_OP2_MASK) 66 67 /* 68 * As per Documentation/virt/kvm/devices/arm-vgic-its.rst, 69 * below macros are defined for ITS table entry encoding. 70 */ 71 #define KVM_ITS_CTE_VALID_SHIFT 63 72 #define KVM_ITS_CTE_VALID_MASK BIT_ULL(63) 73 #define KVM_ITS_CTE_RDBASE_SHIFT 16 74 #define KVM_ITS_CTE_ICID_MASK GENMASK_ULL(15, 0) 75 #define KVM_ITS_ITE_NEXT_SHIFT 48 76 #define KVM_ITS_ITE_PINTID_SHIFT 16 77 #define KVM_ITS_ITE_PINTID_MASK GENMASK_ULL(47, 16) 78 #define KVM_ITS_ITE_ICID_MASK GENMASK_ULL(15, 0) 79 #define KVM_ITS_DTE_VALID_SHIFT 63 80 #define KVM_ITS_DTE_VALID_MASK BIT_ULL(63) 81 #define KVM_ITS_DTE_NEXT_SHIFT 49 82 #define KVM_ITS_DTE_NEXT_MASK GENMASK_ULL(62, 49) 83 #define KVM_ITS_DTE_ITTADDR_SHIFT 5 84 #define KVM_ITS_DTE_ITTADDR_MASK GENMASK_ULL(48, 5) 85 #define KVM_ITS_DTE_SIZE_MASK GENMASK_ULL(4, 0) 86 #define KVM_ITS_L1E_VALID_MASK BIT_ULL(63) 87 /* we only support 64 kB translation table page size */ 88 #define KVM_ITS_L1E_ADDR_MASK GENMASK_ULL(51, 16) 89 90 #define KVM_VGIC_V3_RDIST_INDEX_MASK GENMASK_ULL(11, 0) 91 #define KVM_VGIC_V3_RDIST_FLAGS_MASK GENMASK_ULL(15, 12) 92 #define KVM_VGIC_V3_RDIST_FLAGS_SHIFT 12 93 #define KVM_VGIC_V3_RDIST_BASE_MASK GENMASK_ULL(51, 16) 94 #define KVM_VGIC_V3_RDIST_COUNT_MASK GENMASK_ULL(63, 52) 95 #define KVM_VGIC_V3_RDIST_COUNT_SHIFT 52 96 97 #ifdef CONFIG_DEBUG_SPINLOCK 98 #define DEBUG_SPINLOCK_BUG_ON(p) BUG_ON(p) 99 #else 100 #define DEBUG_SPINLOCK_BUG_ON(p) 101 #endif 102 103 static inline u32 vgic_get_implementation_rev(struct kvm_vcpu *vcpu) 104 { 105 return vcpu->kvm->arch.vgic.implementation_rev; 106 } 107 108 /* Requires the irq_lock to be held by the caller. */ 109 static inline bool irq_is_pending(struct vgic_irq *irq) 110 { 111 if (irq->config == VGIC_CONFIG_EDGE) 112 return irq->pending_latch; 113 else 114 return irq->pending_latch || irq->line_level; 115 } 116 117 static inline bool vgic_irq_is_mapped_level(struct vgic_irq *irq) 118 { 119 return irq->config == VGIC_CONFIG_LEVEL && irq->hw; 120 } 121 122 static inline int vgic_irq_get_lr_count(struct vgic_irq *irq) 123 { 124 /* Account for the active state as an interrupt */ 125 if (vgic_irq_is_sgi(irq->intid) && irq->source) 126 return hweight8(irq->source) + irq->active; 127 128 return irq_is_pending(irq) || irq->active; 129 } 130 131 static inline bool vgic_irq_is_multi_sgi(struct vgic_irq *irq) 132 { 133 return vgic_irq_get_lr_count(irq) > 1; 134 } 135 136 static inline int vgic_write_guest_lock(struct kvm *kvm, gpa_t gpa, 137 const void *data, unsigned long len) 138 { 139 struct vgic_dist *dist = &kvm->arch.vgic; 140 int ret; 141 142 dist->table_write_in_progress = true; 143 ret = kvm_write_guest_lock(kvm, gpa, data, len); 144 dist->table_write_in_progress = false; 145 146 return ret; 147 } 148 149 static inline int vgic_its_read_entry_lock(struct vgic_its *its, gpa_t eaddr, 150 u64 *eval, unsigned long esize) 151 { 152 struct kvm *kvm = its->dev->kvm; 153 154 if (KVM_BUG_ON(esize != sizeof(*eval), kvm)) 155 return -EINVAL; 156 157 return kvm_read_guest_lock(kvm, eaddr, eval, esize); 158 159 } 160 161 static inline int vgic_its_write_entry_lock(struct vgic_its *its, gpa_t eaddr, 162 u64 eval, unsigned long esize) 163 { 164 struct kvm *kvm = its->dev->kvm; 165 166 if (KVM_BUG_ON(esize != sizeof(eval), kvm)) 167 return -EINVAL; 168 169 return vgic_write_guest_lock(kvm, eaddr, &eval, esize); 170 } 171 172 /* 173 * This struct provides an intermediate representation of the fields contained 174 * in the GICH_VMCR and ICH_VMCR registers, such that code exporting the GIC 175 * state to userspace can generate either GICv2 or GICv3 CPU interface 176 * registers regardless of the hardware backed GIC used. 177 */ 178 struct vgic_vmcr { 179 u32 grpen0; 180 u32 grpen1; 181 182 u32 ackctl; 183 u32 fiqen; 184 u32 cbpr; 185 u32 eoim; 186 187 u32 abpr; 188 u32 bpr; 189 u32 pmr; /* Priority mask field in the GICC_PMR and 190 * ICC_PMR_EL1 priority field format */ 191 }; 192 193 struct vgic_reg_attr { 194 struct kvm_vcpu *vcpu; 195 gpa_t addr; 196 }; 197 198 int vgic_v3_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr, 199 struct vgic_reg_attr *reg_attr); 200 int vgic_v2_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr, 201 struct vgic_reg_attr *reg_attr); 202 const struct vgic_register_region * 203 vgic_get_mmio_region(struct kvm_vcpu *vcpu, struct vgic_io_device *iodev, 204 gpa_t addr, int len); 205 struct vgic_irq *vgic_get_irq(struct kvm *kvm, struct kvm_vcpu *vcpu, 206 u32 intid); 207 void vgic_put_irq(struct kvm *kvm, struct vgic_irq *irq); 208 bool vgic_get_phys_line_level(struct vgic_irq *irq); 209 void vgic_irq_set_phys_pending(struct vgic_irq *irq, bool pending); 210 void vgic_irq_set_phys_active(struct vgic_irq *irq, bool active); 211 bool vgic_queue_irq_unlock(struct kvm *kvm, struct vgic_irq *irq, 212 unsigned long flags) __releases(&irq->irq_lock); 213 void vgic_kick_vcpus(struct kvm *kvm); 214 void vgic_irq_handle_resampling(struct vgic_irq *irq, 215 bool lr_deactivated, bool lr_pending); 216 217 int vgic_check_iorange(struct kvm *kvm, phys_addr_t ioaddr, 218 phys_addr_t addr, phys_addr_t alignment, 219 phys_addr_t size); 220 221 void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu); 222 void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr); 223 void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr); 224 void vgic_v2_set_underflow(struct kvm_vcpu *vcpu); 225 int vgic_v2_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr); 226 int vgic_v2_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write, 227 int offset, u32 *val); 228 int vgic_v2_cpuif_uaccess(struct kvm_vcpu *vcpu, bool is_write, 229 int offset, u32 *val); 230 void vgic_v2_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); 231 void vgic_v2_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); 232 void vgic_v2_enable(struct kvm_vcpu *vcpu); 233 int vgic_v2_probe(const struct gic_kvm_info *info); 234 int vgic_v2_map_resources(struct kvm *kvm); 235 int vgic_register_dist_iodev(struct kvm *kvm, gpa_t dist_base_address, 236 enum vgic_type); 237 238 void vgic_v2_init_lrs(void); 239 void vgic_v2_load(struct kvm_vcpu *vcpu); 240 void vgic_v2_put(struct kvm_vcpu *vcpu); 241 242 void vgic_v2_save_state(struct kvm_vcpu *vcpu); 243 void vgic_v2_restore_state(struct kvm_vcpu *vcpu); 244 245 static inline bool vgic_try_get_irq_kref(struct vgic_irq *irq) 246 { 247 if (!irq) 248 return false; 249 250 if (irq->intid < VGIC_MIN_LPI) 251 return true; 252 253 return kref_get_unless_zero(&irq->refcount); 254 } 255 256 static inline void vgic_get_irq_kref(struct vgic_irq *irq) 257 { 258 WARN_ON_ONCE(!vgic_try_get_irq_kref(irq)); 259 } 260 261 void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu); 262 void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr); 263 void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr); 264 void vgic_v3_set_underflow(struct kvm_vcpu *vcpu); 265 void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); 266 void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); 267 void vgic_v3_enable(struct kvm_vcpu *vcpu); 268 int vgic_v3_probe(const struct gic_kvm_info *info); 269 int vgic_v3_map_resources(struct kvm *kvm); 270 int vgic_v3_lpi_sync_pending_status(struct kvm *kvm, struct vgic_irq *irq); 271 int vgic_v3_save_pending_tables(struct kvm *kvm); 272 int vgic_v3_set_redist_base(struct kvm *kvm, u32 index, u64 addr, u32 count); 273 int vgic_register_redist_iodev(struct kvm_vcpu *vcpu); 274 void vgic_unregister_redist_iodev(struct kvm_vcpu *vcpu); 275 bool vgic_v3_check_base(struct kvm *kvm); 276 277 void vgic_v3_load(struct kvm_vcpu *vcpu); 278 void vgic_v3_put(struct kvm_vcpu *vcpu); 279 280 bool vgic_has_its(struct kvm *kvm); 281 int kvm_vgic_register_its_device(void); 282 void vgic_enable_lpis(struct kvm_vcpu *vcpu); 283 void vgic_flush_pending_lpis(struct kvm_vcpu *vcpu); 284 int vgic_its_inject_msi(struct kvm *kvm, struct kvm_msi *msi); 285 int vgic_v3_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr); 286 int vgic_v3_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write, 287 int offset, u32 *val); 288 int vgic_v3_redist_uaccess(struct kvm_vcpu *vcpu, bool is_write, 289 int offset, u32 *val); 290 int vgic_v3_cpu_sysregs_uaccess(struct kvm_vcpu *vcpu, 291 struct kvm_device_attr *attr, bool is_write); 292 int vgic_v3_has_cpu_sysregs_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr); 293 int vgic_v3_line_level_info_uaccess(struct kvm_vcpu *vcpu, bool is_write, 294 u32 intid, u32 *val); 295 int kvm_register_vgic_device(unsigned long type); 296 void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); 297 void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); 298 int vgic_lazy_init(struct kvm *kvm); 299 int vgic_init(struct kvm *kvm); 300 301 void vgic_debug_init(struct kvm *kvm); 302 void vgic_debug_destroy(struct kvm *kvm); 303 304 static inline int vgic_v3_max_apr_idx(struct kvm_vcpu *vcpu) 305 { 306 struct vgic_cpu *cpu_if = &vcpu->arch.vgic_cpu; 307 308 /* 309 * num_pri_bits are initialized with HW supported values. 310 * We can rely safely on num_pri_bits even if VM has not 311 * restored ICC_CTLR_EL1 before restoring APnR registers. 312 */ 313 switch (cpu_if->num_pri_bits) { 314 case 7: return 3; 315 case 6: return 1; 316 default: return 0; 317 } 318 } 319 320 static inline bool 321 vgic_v3_redist_region_full(struct vgic_redist_region *region) 322 { 323 if (!region->count) 324 return false; 325 326 return (region->free_index >= region->count); 327 } 328 329 struct vgic_redist_region *vgic_v3_rdist_free_slot(struct list_head *rdregs); 330 331 static inline size_t 332 vgic_v3_rd_region_size(struct kvm *kvm, struct vgic_redist_region *rdreg) 333 { 334 if (!rdreg->count) 335 return atomic_read(&kvm->online_vcpus) * KVM_VGIC_V3_REDIST_SIZE; 336 else 337 return rdreg->count * KVM_VGIC_V3_REDIST_SIZE; 338 } 339 340 struct vgic_redist_region *vgic_v3_rdist_region_from_index(struct kvm *kvm, 341 u32 index); 342 void vgic_v3_free_redist_region(struct kvm *kvm, struct vgic_redist_region *rdreg); 343 344 bool vgic_v3_rdist_overlap(struct kvm *kvm, gpa_t base, size_t size); 345 346 static inline bool vgic_dist_overlap(struct kvm *kvm, gpa_t base, size_t size) 347 { 348 struct vgic_dist *d = &kvm->arch.vgic; 349 350 return (base + size > d->vgic_dist_base) && 351 (base < d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE); 352 } 353 354 bool vgic_lpis_enabled(struct kvm_vcpu *vcpu); 355 int vgic_its_resolve_lpi(struct kvm *kvm, struct vgic_its *its, 356 u32 devid, u32 eventid, struct vgic_irq **irq); 357 struct vgic_its *vgic_msi_to_its(struct kvm *kvm, struct kvm_msi *msi); 358 int vgic_its_inject_cached_translation(struct kvm *kvm, struct kvm_msi *msi); 359 void vgic_its_invalidate_all_caches(struct kvm *kvm); 360 361 /* GICv4.1 MMIO interface */ 362 int vgic_its_inv_lpi(struct kvm *kvm, struct vgic_irq *irq); 363 int vgic_its_invall(struct kvm_vcpu *vcpu); 364 365 bool vgic_supports_direct_msis(struct kvm *kvm); 366 int vgic_v4_init(struct kvm *kvm); 367 void vgic_v4_teardown(struct kvm *kvm); 368 void vgic_v4_configure_vsgis(struct kvm *kvm); 369 void vgic_v4_get_vlpi_state(struct vgic_irq *irq, bool *val); 370 int vgic_v4_request_vpe_irq(struct kvm_vcpu *vcpu, int irq); 371 372 void vcpu_set_ich_hcr(struct kvm_vcpu *vcpu); 373 374 static inline bool kvm_has_gicv3(struct kvm *kvm) 375 { 376 return kvm_has_feat(kvm, ID_AA64PFR0_EL1, GIC, IMP); 377 } 378 379 #endif 380