1 // SPDX-License-Identifier: GPL-2.0-only 2 3 #include <linux/irqchip/arm-gic-v3.h> 4 #include <linux/irq.h> 5 #include <linux/irqdomain.h> 6 #include <linux/kvm.h> 7 #include <linux/kvm_host.h> 8 #include <kvm/arm_vgic.h> 9 #include <asm/kvm_hyp.h> 10 #include <asm/kvm_mmu.h> 11 #include <asm/kvm_asm.h> 12 13 #include "vgic.h" 14 15 static bool group0_trap; 16 static bool group1_trap; 17 static bool common_trap; 18 static bool gicv4_enable; 19 20 void vgic_v3_set_underflow(struct kvm_vcpu *vcpu) 21 { 22 struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3; 23 24 cpuif->vgic_hcr |= ICH_HCR_UIE; 25 } 26 27 static bool lr_signals_eoi_mi(u64 lr_val) 28 { 29 return !(lr_val & ICH_LR_STATE) && (lr_val & ICH_LR_EOI) && 30 !(lr_val & ICH_LR_HW); 31 } 32 33 void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu) 34 { 35 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; 36 struct vgic_v3_cpu_if *cpuif = &vgic_cpu->vgic_v3; 37 u32 model = vcpu->kvm->arch.vgic.vgic_model; 38 int lr; 39 40 DEBUG_SPINLOCK_BUG_ON(!irqs_disabled()); 41 42 cpuif->vgic_hcr &= ~ICH_HCR_UIE; 43 44 for (lr = 0; lr < cpuif->used_lrs; lr++) { 45 u64 val = cpuif->vgic_lr[lr]; 46 u32 intid, cpuid; 47 struct vgic_irq *irq; 48 bool is_v2_sgi = false; 49 50 cpuid = val & GICH_LR_PHYSID_CPUID; 51 cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT; 52 53 if (model == KVM_DEV_TYPE_ARM_VGIC_V3) { 54 intid = val & ICH_LR_VIRTUAL_ID_MASK; 55 } else { 56 intid = val & GICH_LR_VIRTUALID; 57 is_v2_sgi = vgic_irq_is_sgi(intid); 58 } 59 60 /* Notify fds when the guest EOI'ed a level-triggered IRQ */ 61 if (lr_signals_eoi_mi(val) && vgic_valid_spi(vcpu->kvm, intid)) 62 kvm_notify_acked_irq(vcpu->kvm, 0, 63 intid - VGIC_NR_PRIVATE_IRQS); 64 65 irq = vgic_get_irq(vcpu->kvm, vcpu, intid); 66 if (!irq) /* An LPI could have been unmapped. */ 67 continue; 68 69 raw_spin_lock(&irq->irq_lock); 70 71 /* Always preserve the active bit */ 72 irq->active = !!(val & ICH_LR_ACTIVE_BIT); 73 74 if (irq->active && is_v2_sgi) 75 irq->active_source = cpuid; 76 77 /* Edge is the only case where we preserve the pending bit */ 78 if (irq->config == VGIC_CONFIG_EDGE && 79 (val & ICH_LR_PENDING_BIT)) { 80 irq->pending_latch = true; 81 82 if (is_v2_sgi) 83 irq->source |= (1 << cpuid); 84 } 85 86 /* 87 * Clear soft pending state when level irqs have been acked. 88 */ 89 if (irq->config == VGIC_CONFIG_LEVEL && !(val & ICH_LR_STATE)) 90 irq->pending_latch = false; 91 92 /* 93 * Level-triggered mapped IRQs are special because we only 94 * observe rising edges as input to the VGIC. 95 * 96 * If the guest never acked the interrupt we have to sample 97 * the physical line and set the line level, because the 98 * device state could have changed or we simply need to 99 * process the still pending interrupt later. 100 * 101 * If this causes us to lower the level, we have to also clear 102 * the physical active state, since we will otherwise never be 103 * told when the interrupt becomes asserted again. 104 * 105 * Another case is when the interrupt requires a helping hand 106 * on deactivation (no HW deactivation, for example). 107 */ 108 if (vgic_irq_is_mapped_level(irq)) { 109 bool resample = false; 110 111 if (val & ICH_LR_PENDING_BIT) { 112 irq->line_level = vgic_get_phys_line_level(irq); 113 resample = !irq->line_level; 114 } else if (vgic_irq_needs_resampling(irq) && 115 !(irq->active || irq->pending_latch)) { 116 resample = true; 117 } 118 119 if (resample) 120 vgic_irq_set_phys_active(irq, false); 121 } 122 123 raw_spin_unlock(&irq->irq_lock); 124 vgic_put_irq(vcpu->kvm, irq); 125 } 126 127 cpuif->used_lrs = 0; 128 } 129 130 /* Requires the irq to be locked already */ 131 void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr) 132 { 133 u32 model = vcpu->kvm->arch.vgic.vgic_model; 134 u64 val = irq->intid; 135 bool allow_pending = true, is_v2_sgi; 136 137 is_v2_sgi = (vgic_irq_is_sgi(irq->intid) && 138 model == KVM_DEV_TYPE_ARM_VGIC_V2); 139 140 if (irq->active) { 141 val |= ICH_LR_ACTIVE_BIT; 142 if (is_v2_sgi) 143 val |= irq->active_source << GICH_LR_PHYSID_CPUID_SHIFT; 144 if (vgic_irq_is_multi_sgi(irq)) { 145 allow_pending = false; 146 val |= ICH_LR_EOI; 147 } 148 } 149 150 if (irq->hw && !vgic_irq_needs_resampling(irq)) { 151 val |= ICH_LR_HW; 152 val |= ((u64)irq->hwintid) << ICH_LR_PHYS_ID_SHIFT; 153 /* 154 * Never set pending+active on a HW interrupt, as the 155 * pending state is kept at the physical distributor 156 * level. 157 */ 158 if (irq->active) 159 allow_pending = false; 160 } else { 161 if (irq->config == VGIC_CONFIG_LEVEL) { 162 val |= ICH_LR_EOI; 163 164 /* 165 * Software resampling doesn't work very well 166 * if we allow P+A, so let's not do that. 167 */ 168 if (irq->active) 169 allow_pending = false; 170 } 171 } 172 173 if (allow_pending && irq_is_pending(irq)) { 174 val |= ICH_LR_PENDING_BIT; 175 176 if (irq->config == VGIC_CONFIG_EDGE) 177 irq->pending_latch = false; 178 179 if (vgic_irq_is_sgi(irq->intid) && 180 model == KVM_DEV_TYPE_ARM_VGIC_V2) { 181 u32 src = ffs(irq->source); 182 183 if (WARN_RATELIMIT(!src, "No SGI source for INTID %d\n", 184 irq->intid)) 185 return; 186 187 val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT; 188 irq->source &= ~(1 << (src - 1)); 189 if (irq->source) { 190 irq->pending_latch = true; 191 val |= ICH_LR_EOI; 192 } 193 } 194 } 195 196 /* 197 * Level-triggered mapped IRQs are special because we only observe 198 * rising edges as input to the VGIC. We therefore lower the line 199 * level here, so that we can take new virtual IRQs. See 200 * vgic_v3_fold_lr_state for more info. 201 */ 202 if (vgic_irq_is_mapped_level(irq) && (val & ICH_LR_PENDING_BIT)) 203 irq->line_level = false; 204 205 if (irq->group) 206 val |= ICH_LR_GROUP; 207 208 val |= (u64)irq->priority << ICH_LR_PRIORITY_SHIFT; 209 210 vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = val; 211 } 212 213 void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr) 214 { 215 vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = 0; 216 } 217 218 void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp) 219 { 220 struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3; 221 u32 model = vcpu->kvm->arch.vgic.vgic_model; 222 u32 vmcr; 223 224 if (model == KVM_DEV_TYPE_ARM_VGIC_V2) { 225 vmcr = (vmcrp->ackctl << ICH_VMCR_ACK_CTL_SHIFT) & 226 ICH_VMCR_ACK_CTL_MASK; 227 vmcr |= (vmcrp->fiqen << ICH_VMCR_FIQ_EN_SHIFT) & 228 ICH_VMCR_FIQ_EN_MASK; 229 } else { 230 /* 231 * When emulating GICv3 on GICv3 with SRE=1 on the 232 * VFIQEn bit is RES1 and the VAckCtl bit is RES0. 233 */ 234 vmcr = ICH_VMCR_FIQ_EN_MASK; 235 } 236 237 vmcr |= (vmcrp->cbpr << ICH_VMCR_CBPR_SHIFT) & ICH_VMCR_CBPR_MASK; 238 vmcr |= (vmcrp->eoim << ICH_VMCR_EOIM_SHIFT) & ICH_VMCR_EOIM_MASK; 239 vmcr |= (vmcrp->abpr << ICH_VMCR_BPR1_SHIFT) & ICH_VMCR_BPR1_MASK; 240 vmcr |= (vmcrp->bpr << ICH_VMCR_BPR0_SHIFT) & ICH_VMCR_BPR0_MASK; 241 vmcr |= (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK; 242 vmcr |= (vmcrp->grpen0 << ICH_VMCR_ENG0_SHIFT) & ICH_VMCR_ENG0_MASK; 243 vmcr |= (vmcrp->grpen1 << ICH_VMCR_ENG1_SHIFT) & ICH_VMCR_ENG1_MASK; 244 245 cpu_if->vgic_vmcr = vmcr; 246 } 247 248 void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp) 249 { 250 struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3; 251 u32 model = vcpu->kvm->arch.vgic.vgic_model; 252 u32 vmcr; 253 254 vmcr = cpu_if->vgic_vmcr; 255 256 if (model == KVM_DEV_TYPE_ARM_VGIC_V2) { 257 vmcrp->ackctl = (vmcr & ICH_VMCR_ACK_CTL_MASK) >> 258 ICH_VMCR_ACK_CTL_SHIFT; 259 vmcrp->fiqen = (vmcr & ICH_VMCR_FIQ_EN_MASK) >> 260 ICH_VMCR_FIQ_EN_SHIFT; 261 } else { 262 /* 263 * When emulating GICv3 on GICv3 with SRE=1 on the 264 * VFIQEn bit is RES1 and the VAckCtl bit is RES0. 265 */ 266 vmcrp->fiqen = 1; 267 vmcrp->ackctl = 0; 268 } 269 270 vmcrp->cbpr = (vmcr & ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT; 271 vmcrp->eoim = (vmcr & ICH_VMCR_EOIM_MASK) >> ICH_VMCR_EOIM_SHIFT; 272 vmcrp->abpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT; 273 vmcrp->bpr = (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT; 274 vmcrp->pmr = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT; 275 vmcrp->grpen0 = (vmcr & ICH_VMCR_ENG0_MASK) >> ICH_VMCR_ENG0_SHIFT; 276 vmcrp->grpen1 = (vmcr & ICH_VMCR_ENG1_MASK) >> ICH_VMCR_ENG1_SHIFT; 277 } 278 279 #define INITIAL_PENDBASER_VALUE \ 280 (GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWb) | \ 281 GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, SameAsInner) | \ 282 GIC_BASER_SHAREABILITY(GICR_PENDBASER, InnerShareable)) 283 284 void vgic_v3_enable(struct kvm_vcpu *vcpu) 285 { 286 struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3; 287 288 /* 289 * By forcing VMCR to zero, the GIC will restore the binary 290 * points to their reset values. Anything else resets to zero 291 * anyway. 292 */ 293 vgic_v3->vgic_vmcr = 0; 294 295 /* 296 * If we are emulating a GICv3, we do it in an non-GICv2-compatible 297 * way, so we force SRE to 1 to demonstrate this to the guest. 298 * Also, we don't support any form of IRQ/FIQ bypass. 299 * This goes with the spec allowing the value to be RAO/WI. 300 */ 301 if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) { 302 vgic_v3->vgic_sre = (ICC_SRE_EL1_DIB | 303 ICC_SRE_EL1_DFB | 304 ICC_SRE_EL1_SRE); 305 vcpu->arch.vgic_cpu.pendbaser = INITIAL_PENDBASER_VALUE; 306 } else { 307 vgic_v3->vgic_sre = 0; 308 } 309 310 vcpu->arch.vgic_cpu.num_id_bits = (kvm_vgic_global_state.ich_vtr_el2 & 311 ICH_VTR_ID_BITS_MASK) >> 312 ICH_VTR_ID_BITS_SHIFT; 313 vcpu->arch.vgic_cpu.num_pri_bits = ((kvm_vgic_global_state.ich_vtr_el2 & 314 ICH_VTR_PRI_BITS_MASK) >> 315 ICH_VTR_PRI_BITS_SHIFT) + 1; 316 317 /* Get the show on the road... */ 318 vgic_v3->vgic_hcr = ICH_HCR_EN; 319 if (group0_trap) 320 vgic_v3->vgic_hcr |= ICH_HCR_TALL0; 321 if (group1_trap) 322 vgic_v3->vgic_hcr |= ICH_HCR_TALL1; 323 if (common_trap) 324 vgic_v3->vgic_hcr |= ICH_HCR_TC; 325 } 326 327 int vgic_v3_lpi_sync_pending_status(struct kvm *kvm, struct vgic_irq *irq) 328 { 329 struct kvm_vcpu *vcpu; 330 int byte_offset, bit_nr; 331 gpa_t pendbase, ptr; 332 bool status; 333 u8 val; 334 int ret; 335 unsigned long flags; 336 337 retry: 338 vcpu = irq->target_vcpu; 339 if (!vcpu) 340 return 0; 341 342 pendbase = GICR_PENDBASER_ADDRESS(vcpu->arch.vgic_cpu.pendbaser); 343 344 byte_offset = irq->intid / BITS_PER_BYTE; 345 bit_nr = irq->intid % BITS_PER_BYTE; 346 ptr = pendbase + byte_offset; 347 348 ret = kvm_read_guest_lock(kvm, ptr, &val, 1); 349 if (ret) 350 return ret; 351 352 status = val & (1 << bit_nr); 353 354 raw_spin_lock_irqsave(&irq->irq_lock, flags); 355 if (irq->target_vcpu != vcpu) { 356 raw_spin_unlock_irqrestore(&irq->irq_lock, flags); 357 goto retry; 358 } 359 irq->pending_latch = status; 360 vgic_queue_irq_unlock(vcpu->kvm, irq, flags); 361 362 if (status) { 363 /* clear consumed data */ 364 val &= ~(1 << bit_nr); 365 ret = kvm_write_guest_lock(kvm, ptr, &val, 1); 366 if (ret) 367 return ret; 368 } 369 return 0; 370 } 371 372 /* 373 * The deactivation of the doorbell interrupt will trigger the 374 * unmapping of the associated vPE. 375 */ 376 static void unmap_all_vpes(struct vgic_dist *dist) 377 { 378 struct irq_desc *desc; 379 int i; 380 381 for (i = 0; i < dist->its_vm.nr_vpes; i++) { 382 desc = irq_to_desc(dist->its_vm.vpes[i]->irq); 383 irq_domain_deactivate_irq(irq_desc_get_irq_data(desc)); 384 } 385 } 386 387 static void map_all_vpes(struct vgic_dist *dist) 388 { 389 struct irq_desc *desc; 390 int i; 391 392 for (i = 0; i < dist->its_vm.nr_vpes; i++) { 393 desc = irq_to_desc(dist->its_vm.vpes[i]->irq); 394 irq_domain_activate_irq(irq_desc_get_irq_data(desc), false); 395 } 396 } 397 398 /** 399 * vgic_v3_save_pending_tables - Save the pending tables into guest RAM 400 * kvm lock and all vcpu lock must be held 401 */ 402 int vgic_v3_save_pending_tables(struct kvm *kvm) 403 { 404 struct vgic_dist *dist = &kvm->arch.vgic; 405 struct vgic_irq *irq; 406 gpa_t last_ptr = ~(gpa_t)0; 407 bool vlpi_avail = false; 408 int ret = 0; 409 u8 val; 410 411 if (unlikely(!vgic_initialized(kvm))) 412 return -ENXIO; 413 414 /* 415 * A preparation for getting any VLPI states. 416 * The above vgic initialized check also ensures that the allocation 417 * and enabling of the doorbells have already been done. 418 */ 419 if (kvm_vgic_global_state.has_gicv4_1) { 420 unmap_all_vpes(dist); 421 vlpi_avail = true; 422 } 423 424 list_for_each_entry(irq, &dist->lpi_list_head, lpi_list) { 425 int byte_offset, bit_nr; 426 struct kvm_vcpu *vcpu; 427 gpa_t pendbase, ptr; 428 bool is_pending; 429 bool stored; 430 431 vcpu = irq->target_vcpu; 432 if (!vcpu) 433 continue; 434 435 pendbase = GICR_PENDBASER_ADDRESS(vcpu->arch.vgic_cpu.pendbaser); 436 437 byte_offset = irq->intid / BITS_PER_BYTE; 438 bit_nr = irq->intid % BITS_PER_BYTE; 439 ptr = pendbase + byte_offset; 440 441 if (ptr != last_ptr) { 442 ret = kvm_read_guest_lock(kvm, ptr, &val, 1); 443 if (ret) 444 goto out; 445 last_ptr = ptr; 446 } 447 448 stored = val & (1U << bit_nr); 449 450 is_pending = irq->pending_latch; 451 452 if (irq->hw && vlpi_avail) 453 vgic_v4_get_vlpi_state(irq, &is_pending); 454 455 if (stored == is_pending) 456 continue; 457 458 if (is_pending) 459 val |= 1 << bit_nr; 460 else 461 val &= ~(1 << bit_nr); 462 463 ret = kvm_write_guest_lock(kvm, ptr, &val, 1); 464 if (ret) 465 goto out; 466 } 467 468 out: 469 if (vlpi_avail) 470 map_all_vpes(dist); 471 472 return ret; 473 } 474 475 /** 476 * vgic_v3_rdist_overlap - check if a region overlaps with any 477 * existing redistributor region 478 * 479 * @kvm: kvm handle 480 * @base: base of the region 481 * @size: size of region 482 * 483 * Return: true if there is an overlap 484 */ 485 bool vgic_v3_rdist_overlap(struct kvm *kvm, gpa_t base, size_t size) 486 { 487 struct vgic_dist *d = &kvm->arch.vgic; 488 struct vgic_redist_region *rdreg; 489 490 list_for_each_entry(rdreg, &d->rd_regions, list) { 491 if ((base + size > rdreg->base) && 492 (base < rdreg->base + vgic_v3_rd_region_size(kvm, rdreg))) 493 return true; 494 } 495 return false; 496 } 497 498 /* 499 * Check for overlapping regions and for regions crossing the end of memory 500 * for base addresses which have already been set. 501 */ 502 bool vgic_v3_check_base(struct kvm *kvm) 503 { 504 struct vgic_dist *d = &kvm->arch.vgic; 505 struct vgic_redist_region *rdreg; 506 507 if (!IS_VGIC_ADDR_UNDEF(d->vgic_dist_base) && 508 d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE < d->vgic_dist_base) 509 return false; 510 511 list_for_each_entry(rdreg, &d->rd_regions, list) { 512 if (rdreg->base + vgic_v3_rd_region_size(kvm, rdreg) < 513 rdreg->base) 514 return false; 515 } 516 517 if (IS_VGIC_ADDR_UNDEF(d->vgic_dist_base)) 518 return true; 519 520 return !vgic_v3_rdist_overlap(kvm, d->vgic_dist_base, 521 KVM_VGIC_V3_DIST_SIZE); 522 } 523 524 /** 525 * vgic_v3_rdist_free_slot - Look up registered rdist regions and identify one 526 * which has free space to put a new rdist region. 527 * 528 * @rd_regions: redistributor region list head 529 * 530 * A redistributor regions maps n redistributors, n = region size / (2 x 64kB). 531 * Stride between redistributors is 0 and regions are filled in the index order. 532 * 533 * Return: the redist region handle, if any, that has space to map a new rdist 534 * region. 535 */ 536 struct vgic_redist_region *vgic_v3_rdist_free_slot(struct list_head *rd_regions) 537 { 538 struct vgic_redist_region *rdreg; 539 540 list_for_each_entry(rdreg, rd_regions, list) { 541 if (!vgic_v3_redist_region_full(rdreg)) 542 return rdreg; 543 } 544 return NULL; 545 } 546 547 struct vgic_redist_region *vgic_v3_rdist_region_from_index(struct kvm *kvm, 548 u32 index) 549 { 550 struct list_head *rd_regions = &kvm->arch.vgic.rd_regions; 551 struct vgic_redist_region *rdreg; 552 553 list_for_each_entry(rdreg, rd_regions, list) { 554 if (rdreg->index == index) 555 return rdreg; 556 } 557 return NULL; 558 } 559 560 561 int vgic_v3_map_resources(struct kvm *kvm) 562 { 563 struct vgic_dist *dist = &kvm->arch.vgic; 564 struct kvm_vcpu *vcpu; 565 int ret = 0; 566 int c; 567 568 kvm_for_each_vcpu(c, vcpu, kvm) { 569 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; 570 571 if (IS_VGIC_ADDR_UNDEF(vgic_cpu->rd_iodev.base_addr)) { 572 kvm_debug("vcpu %d redistributor base not set\n", c); 573 return -ENXIO; 574 } 575 } 576 577 if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base)) { 578 kvm_err("Need to set vgic distributor addresses first\n"); 579 return -ENXIO; 580 } 581 582 if (!vgic_v3_check_base(kvm)) { 583 kvm_err("VGIC redist and dist frames overlap\n"); 584 return -EINVAL; 585 } 586 587 /* 588 * For a VGICv3 we require the userland to explicitly initialize 589 * the VGIC before we need to use it. 590 */ 591 if (!vgic_initialized(kvm)) { 592 return -EBUSY; 593 } 594 595 ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V3); 596 if (ret) { 597 kvm_err("Unable to register VGICv3 dist MMIO regions\n"); 598 return ret; 599 } 600 601 if (kvm_vgic_global_state.has_gicv4_1) 602 vgic_v4_configure_vsgis(kvm); 603 604 return 0; 605 } 606 607 DEFINE_STATIC_KEY_FALSE(vgic_v3_cpuif_trap); 608 609 static int __init early_group0_trap_cfg(char *buf) 610 { 611 return strtobool(buf, &group0_trap); 612 } 613 early_param("kvm-arm.vgic_v3_group0_trap", early_group0_trap_cfg); 614 615 static int __init early_group1_trap_cfg(char *buf) 616 { 617 return strtobool(buf, &group1_trap); 618 } 619 early_param("kvm-arm.vgic_v3_group1_trap", early_group1_trap_cfg); 620 621 static int __init early_common_trap_cfg(char *buf) 622 { 623 return strtobool(buf, &common_trap); 624 } 625 early_param("kvm-arm.vgic_v3_common_trap", early_common_trap_cfg); 626 627 static int __init early_gicv4_enable(char *buf) 628 { 629 return strtobool(buf, &gicv4_enable); 630 } 631 early_param("kvm-arm.vgic_v4_enable", early_gicv4_enable); 632 633 /** 634 * vgic_v3_probe - probe for a VGICv3 compatible interrupt controller 635 * @info: pointer to the GIC description 636 * 637 * Returns 0 if the VGICv3 has been probed successfully, returns an error code 638 * otherwise 639 */ 640 int vgic_v3_probe(const struct gic_kvm_info *info) 641 { 642 u64 ich_vtr_el2 = kvm_call_hyp_ret(__vgic_v3_get_gic_config); 643 bool has_v2; 644 int ret; 645 646 has_v2 = ich_vtr_el2 >> 63; 647 ich_vtr_el2 = (u32)ich_vtr_el2; 648 649 /* 650 * The ListRegs field is 5 bits, but there is an architectural 651 * maximum of 16 list registers. Just ignore bit 4... 652 */ 653 kvm_vgic_global_state.nr_lr = (ich_vtr_el2 & 0xf) + 1; 654 kvm_vgic_global_state.can_emulate_gicv2 = false; 655 kvm_vgic_global_state.ich_vtr_el2 = ich_vtr_el2; 656 657 /* GICv4 support? */ 658 if (info->has_v4) { 659 kvm_vgic_global_state.has_gicv4 = gicv4_enable; 660 kvm_vgic_global_state.has_gicv4_1 = info->has_v4_1 && gicv4_enable; 661 kvm_info("GICv4%s support %sabled\n", 662 kvm_vgic_global_state.has_gicv4_1 ? ".1" : "", 663 gicv4_enable ? "en" : "dis"); 664 } 665 666 kvm_vgic_global_state.vcpu_base = 0; 667 668 if (!info->vcpu.start) { 669 kvm_info("GICv3: no GICV resource entry\n"); 670 } else if (!has_v2) { 671 pr_warn(FW_BUG "CPU interface incapable of MMIO access\n"); 672 } else if (!PAGE_ALIGNED(info->vcpu.start)) { 673 pr_warn("GICV physical address 0x%llx not page aligned\n", 674 (unsigned long long)info->vcpu.start); 675 } else { 676 kvm_vgic_global_state.vcpu_base = info->vcpu.start; 677 kvm_vgic_global_state.can_emulate_gicv2 = true; 678 ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2); 679 if (ret) { 680 kvm_err("Cannot register GICv2 KVM device.\n"); 681 return ret; 682 } 683 kvm_info("vgic-v2@%llx\n", info->vcpu.start); 684 } 685 ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V3); 686 if (ret) { 687 kvm_err("Cannot register GICv3 KVM device.\n"); 688 kvm_unregister_device_ops(KVM_DEV_TYPE_ARM_VGIC_V2); 689 return ret; 690 } 691 692 if (kvm_vgic_global_state.vcpu_base == 0) 693 kvm_info("disabling GICv2 emulation\n"); 694 695 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_30115)) { 696 group0_trap = true; 697 group1_trap = true; 698 } 699 700 if (group0_trap || group1_trap || common_trap) { 701 kvm_info("GICv3 sysreg trapping enabled ([%s%s%s], reduced performance)\n", 702 group0_trap ? "G0" : "", 703 group1_trap ? "G1" : "", 704 common_trap ? "C" : ""); 705 static_branch_enable(&vgic_v3_cpuif_trap); 706 } 707 708 kvm_vgic_global_state.vctrl_base = NULL; 709 kvm_vgic_global_state.type = VGIC_V3; 710 kvm_vgic_global_state.max_gic_vcpus = VGIC_V3_MAX_CPUS; 711 712 return 0; 713 } 714 715 void vgic_v3_load(struct kvm_vcpu *vcpu) 716 { 717 struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3; 718 719 /* 720 * If dealing with a GICv2 emulation on GICv3, VMCR_EL2.VFIQen 721 * is dependent on ICC_SRE_EL1.SRE, and we have to perform the 722 * VMCR_EL2 save/restore in the world switch. 723 */ 724 if (likely(cpu_if->vgic_sre)) 725 kvm_call_hyp(__vgic_v3_write_vmcr, cpu_if->vgic_vmcr); 726 727 kvm_call_hyp(__vgic_v3_restore_aprs, cpu_if); 728 729 if (has_vhe()) 730 __vgic_v3_activate_traps(cpu_if); 731 732 WARN_ON(vgic_v4_load(vcpu)); 733 } 734 735 void vgic_v3_vmcr_sync(struct kvm_vcpu *vcpu) 736 { 737 struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3; 738 739 if (likely(cpu_if->vgic_sre)) 740 cpu_if->vgic_vmcr = kvm_call_hyp_ret(__vgic_v3_read_vmcr); 741 } 742 743 void vgic_v3_put(struct kvm_vcpu *vcpu) 744 { 745 struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3; 746 747 WARN_ON(vgic_v4_put(vcpu, false)); 748 749 vgic_v3_vmcr_sync(vcpu); 750 751 kvm_call_hyp(__vgic_v3_save_aprs, cpu_if); 752 753 if (has_vhe()) 754 __vgic_v3_deactivate_traps(cpu_if); 755 } 756