1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * VGICv3 MMIO handling functions 4 */ 5 6 #include <linux/bitfield.h> 7 #include <linux/irqchip/arm-gic-v3.h> 8 #include <linux/kvm.h> 9 #include <linux/kvm_host.h> 10 #include <linux/interrupt.h> 11 #include <kvm/iodev.h> 12 #include <kvm/arm_vgic.h> 13 14 #include <asm/kvm_emulate.h> 15 #include <asm/kvm_arm.h> 16 #include <asm/kvm_mmu.h> 17 18 #include "vgic.h" 19 #include "vgic-mmio.h" 20 21 /* extract @num bytes at @offset bytes offset in data */ 22 unsigned long extract_bytes(u64 data, unsigned int offset, 23 unsigned int num) 24 { 25 return (data >> (offset * 8)) & GENMASK_ULL(num * 8 - 1, 0); 26 } 27 28 /* allows updates of any half of a 64-bit register (or the whole thing) */ 29 u64 update_64bit_reg(u64 reg, unsigned int offset, unsigned int len, 30 unsigned long val) 31 { 32 int lower = (offset & 4) * 8; 33 int upper = lower + 8 * len - 1; 34 35 reg &= ~GENMASK_ULL(upper, lower); 36 val &= GENMASK_ULL(len * 8 - 1, 0); 37 38 return reg | ((u64)val << lower); 39 } 40 41 bool vgic_has_its(struct kvm *kvm) 42 { 43 struct vgic_dist *dist = &kvm->arch.vgic; 44 45 if (dist->vgic_model != KVM_DEV_TYPE_ARM_VGIC_V3) 46 return false; 47 48 return dist->has_its; 49 } 50 51 bool vgic_supports_direct_msis(struct kvm *kvm) 52 { 53 return kvm_vgic_global_state.has_gicv4 && vgic_has_its(kvm); 54 } 55 56 bool system_supports_direct_sgis(void) 57 { 58 return kvm_vgic_global_state.has_gicv4_1 && gic_cpuif_has_vsgi(); 59 } 60 61 bool vgic_supports_direct_sgis(struct kvm *kvm) 62 { 63 return kvm->arch.vgic.nassgicap; 64 } 65 66 /* 67 * The Revision field in the IIDR have the following meanings: 68 * 69 * Revision 2: Interrupt groups are guest-configurable and signaled using 70 * their configured groups. 71 */ 72 73 static unsigned long vgic_mmio_read_v3_misc(struct kvm_vcpu *vcpu, 74 gpa_t addr, unsigned int len) 75 { 76 struct vgic_dist *vgic = &vcpu->kvm->arch.vgic; 77 u32 value = 0; 78 79 switch (addr & 0x0c) { 80 case GICD_CTLR: 81 if (vgic->enabled) 82 value |= GICD_CTLR_ENABLE_SS_G1; 83 value |= GICD_CTLR_ARE_NS | GICD_CTLR_DS; 84 if (vgic->nassgireq) 85 value |= GICD_CTLR_nASSGIreq; 86 break; 87 case GICD_TYPER: 88 value = vgic->nr_spis + VGIC_NR_PRIVATE_IRQS; 89 value = (value >> 5) - 1; 90 if (vgic_has_its(vcpu->kvm)) { 91 value |= (INTERRUPT_ID_BITS_ITS - 1) << 19; 92 value |= GICD_TYPER_LPIS; 93 } else { 94 value |= (INTERRUPT_ID_BITS_SPIS - 1) << 19; 95 } 96 break; 97 case GICD_TYPER2: 98 if (vgic_supports_direct_sgis(vcpu->kvm)) 99 value = GICD_TYPER2_nASSGIcap; 100 break; 101 case GICD_IIDR: 102 value = (PRODUCT_ID_KVM << GICD_IIDR_PRODUCT_ID_SHIFT) | 103 (vgic->implementation_rev << GICD_IIDR_REVISION_SHIFT) | 104 (IMPLEMENTER_ARM << GICD_IIDR_IMPLEMENTER_SHIFT); 105 break; 106 default: 107 return 0; 108 } 109 110 return value; 111 } 112 113 static void vgic_mmio_write_v3_misc(struct kvm_vcpu *vcpu, 114 gpa_t addr, unsigned int len, 115 unsigned long val) 116 { 117 struct vgic_dist *dist = &vcpu->kvm->arch.vgic; 118 119 switch (addr & 0x0c) { 120 case GICD_CTLR: { 121 bool was_enabled, is_hwsgi; 122 123 mutex_lock(&vcpu->kvm->arch.config_lock); 124 125 was_enabled = dist->enabled; 126 is_hwsgi = dist->nassgireq; 127 128 dist->enabled = val & GICD_CTLR_ENABLE_SS_G1; 129 130 /* Not a GICv4.1? No HW SGIs */ 131 if (!vgic_supports_direct_sgis(vcpu->kvm)) 132 val &= ~GICD_CTLR_nASSGIreq; 133 134 /* Dist stays enabled? nASSGIreq is RO */ 135 if (was_enabled && dist->enabled) { 136 val &= ~GICD_CTLR_nASSGIreq; 137 val |= FIELD_PREP(GICD_CTLR_nASSGIreq, is_hwsgi); 138 } 139 140 /* Switching HW SGIs? */ 141 dist->nassgireq = val & GICD_CTLR_nASSGIreq; 142 if (is_hwsgi != dist->nassgireq) 143 vgic_v4_configure_vsgis(vcpu->kvm); 144 145 if (vgic_supports_direct_sgis(vcpu->kvm) && 146 was_enabled != dist->enabled) 147 kvm_make_all_cpus_request(vcpu->kvm, KVM_REQ_RELOAD_GICv4); 148 else if (!was_enabled && dist->enabled) 149 vgic_kick_vcpus(vcpu->kvm); 150 151 mutex_unlock(&vcpu->kvm->arch.config_lock); 152 break; 153 } 154 case GICD_TYPER: 155 case GICD_TYPER2: 156 case GICD_IIDR: 157 /* This is at best for documentation purposes... */ 158 return; 159 } 160 } 161 162 static int vgic_mmio_uaccess_write_v3_misc(struct kvm_vcpu *vcpu, 163 gpa_t addr, unsigned int len, 164 unsigned long val) 165 { 166 struct vgic_dist *dist = &vcpu->kvm->arch.vgic; 167 u32 reg; 168 169 switch (addr & 0x0c) { 170 case GICD_TYPER2: 171 reg = vgic_mmio_read_v3_misc(vcpu, addr, len); 172 173 if (reg == val) 174 return 0; 175 if (vgic_initialized(vcpu->kvm)) 176 return -EBUSY; 177 if ((reg ^ val) & ~GICD_TYPER2_nASSGIcap) 178 return -EINVAL; 179 if (!system_supports_direct_sgis() && val) 180 return -EINVAL; 181 182 dist->nassgicap = val & GICD_TYPER2_nASSGIcap; 183 return 0; 184 case GICD_IIDR: 185 reg = vgic_mmio_read_v3_misc(vcpu, addr, len); 186 if ((reg ^ val) & ~GICD_IIDR_REVISION_MASK) 187 return -EINVAL; 188 189 reg = FIELD_GET(GICD_IIDR_REVISION_MASK, reg); 190 switch (reg) { 191 case KVM_VGIC_IMP_REV_2: 192 case KVM_VGIC_IMP_REV_3: 193 dist->implementation_rev = reg; 194 return 0; 195 default: 196 return -EINVAL; 197 } 198 case GICD_CTLR: 199 /* Not a GICv4.1? No HW SGIs */ 200 if (!vgic_supports_direct_sgis(vcpu->kvm)) 201 val &= ~GICD_CTLR_nASSGIreq; 202 203 dist->enabled = val & GICD_CTLR_ENABLE_SS_G1; 204 dist->nassgireq = val & GICD_CTLR_nASSGIreq; 205 return 0; 206 } 207 208 vgic_mmio_write_v3_misc(vcpu, addr, len, val); 209 return 0; 210 } 211 212 static unsigned long vgic_mmio_read_irouter(struct kvm_vcpu *vcpu, 213 gpa_t addr, unsigned int len) 214 { 215 int intid = VGIC_ADDR_TO_INTID(addr, 64); 216 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, intid); 217 unsigned long ret = 0; 218 219 if (!irq) 220 return 0; 221 222 /* The upper word is RAZ for us. */ 223 if (!(addr & 4)) 224 ret = extract_bytes(READ_ONCE(irq->mpidr), addr & 7, len); 225 226 vgic_put_irq(vcpu->kvm, irq); 227 return ret; 228 } 229 230 static void vgic_mmio_write_irouter(struct kvm_vcpu *vcpu, 231 gpa_t addr, unsigned int len, 232 unsigned long val) 233 { 234 int intid = VGIC_ADDR_TO_INTID(addr, 64); 235 struct vgic_irq *irq; 236 unsigned long flags; 237 238 /* The upper word is WI for us since we don't implement Aff3. */ 239 if (addr & 4) 240 return; 241 242 irq = vgic_get_irq(vcpu->kvm, intid); 243 244 if (!irq) 245 return; 246 247 raw_spin_lock_irqsave(&irq->irq_lock, flags); 248 249 /* We only care about and preserve Aff0, Aff1 and Aff2. */ 250 irq->mpidr = val & GENMASK(23, 0); 251 irq->target_vcpu = kvm_mpidr_to_vcpu(vcpu->kvm, irq->mpidr); 252 253 raw_spin_unlock_irqrestore(&irq->irq_lock, flags); 254 vgic_put_irq(vcpu->kvm, irq); 255 } 256 257 bool vgic_lpis_enabled(struct kvm_vcpu *vcpu) 258 { 259 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; 260 261 return atomic_read(&vgic_cpu->ctlr) == GICR_CTLR_ENABLE_LPIS; 262 } 263 264 static unsigned long vgic_mmio_read_v3r_ctlr(struct kvm_vcpu *vcpu, 265 gpa_t addr, unsigned int len) 266 { 267 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; 268 unsigned long val; 269 270 val = atomic_read(&vgic_cpu->ctlr); 271 if (vgic_get_implementation_rev(vcpu) >= KVM_VGIC_IMP_REV_3) 272 val |= GICR_CTLR_IR | GICR_CTLR_CES; 273 274 return val; 275 } 276 277 static void vgic_mmio_write_v3r_ctlr(struct kvm_vcpu *vcpu, 278 gpa_t addr, unsigned int len, 279 unsigned long val) 280 { 281 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; 282 u32 ctlr; 283 284 if (!vgic_has_its(vcpu->kvm)) 285 return; 286 287 if (!(val & GICR_CTLR_ENABLE_LPIS)) { 288 /* 289 * Don't disable if RWP is set, as there already an 290 * ongoing disable. Funky guest... 291 */ 292 ctlr = atomic_cmpxchg_acquire(&vgic_cpu->ctlr, 293 GICR_CTLR_ENABLE_LPIS, 294 GICR_CTLR_RWP); 295 if (ctlr != GICR_CTLR_ENABLE_LPIS) 296 return; 297 298 vgic_flush_pending_lpis(vcpu); 299 vgic_its_invalidate_all_caches(vcpu->kvm); 300 atomic_set_release(&vgic_cpu->ctlr, 0); 301 } else { 302 ctlr = atomic_cmpxchg_acquire(&vgic_cpu->ctlr, 0, 303 GICR_CTLR_ENABLE_LPIS); 304 if (ctlr != 0) 305 return; 306 307 vgic_enable_lpis(vcpu); 308 } 309 } 310 311 static bool vgic_mmio_vcpu_rdist_is_last(struct kvm_vcpu *vcpu) 312 { 313 struct vgic_dist *vgic = &vcpu->kvm->arch.vgic; 314 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; 315 struct vgic_redist_region *iter, *rdreg = vgic_cpu->rdreg; 316 317 if (!rdreg) 318 return false; 319 320 if (vgic_cpu->rdreg_index < rdreg->free_index - 1) { 321 return false; 322 } else if (rdreg->count && vgic_cpu->rdreg_index == (rdreg->count - 1)) { 323 struct list_head *rd_regions = &vgic->rd_regions; 324 gpa_t end = rdreg->base + rdreg->count * KVM_VGIC_V3_REDIST_SIZE; 325 326 /* 327 * the rdist is the last one of the redist region, 328 * check whether there is no other contiguous rdist region 329 */ 330 list_for_each_entry(iter, rd_regions, list) { 331 if (iter->base == end && iter->free_index > 0) 332 return false; 333 } 334 } 335 return true; 336 } 337 338 static unsigned long vgic_mmio_read_v3r_typer(struct kvm_vcpu *vcpu, 339 gpa_t addr, unsigned int len) 340 { 341 unsigned long mpidr = kvm_vcpu_get_mpidr_aff(vcpu); 342 int target_vcpu_id = vcpu->vcpu_id; 343 u64 value; 344 345 value = (u64)(mpidr & GENMASK(23, 0)) << 32; 346 value |= ((target_vcpu_id & 0xffff) << 8); 347 348 if (vgic_has_its(vcpu->kvm)) 349 value |= GICR_TYPER_PLPIS; 350 351 if (vgic_mmio_vcpu_rdist_is_last(vcpu)) 352 value |= GICR_TYPER_LAST; 353 354 return extract_bytes(value, addr & 7, len); 355 } 356 357 static unsigned long vgic_mmio_read_v3r_iidr(struct kvm_vcpu *vcpu, 358 gpa_t addr, unsigned int len) 359 { 360 return (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0); 361 } 362 363 static unsigned long vgic_mmio_read_v3_idregs(struct kvm_vcpu *vcpu, 364 gpa_t addr, unsigned int len) 365 { 366 switch (addr & 0xffff) { 367 case GICD_PIDR2: 368 /* report a GICv3 compliant implementation */ 369 return 0x3b; 370 } 371 372 return 0; 373 } 374 375 static int vgic_v3_uaccess_write_pending(struct kvm_vcpu *vcpu, 376 gpa_t addr, unsigned int len, 377 unsigned long val) 378 { 379 int ret; 380 381 ret = vgic_uaccess_write_spending(vcpu, addr, len, val); 382 if (ret) 383 return ret; 384 385 return vgic_uaccess_write_cpending(vcpu, addr, len, ~val); 386 } 387 388 /* We want to avoid outer shareable. */ 389 u64 vgic_sanitise_shareability(u64 field) 390 { 391 switch (field) { 392 case GIC_BASER_OuterShareable: 393 return GIC_BASER_InnerShareable; 394 default: 395 return field; 396 } 397 } 398 399 /* Avoid any inner non-cacheable mapping. */ 400 u64 vgic_sanitise_inner_cacheability(u64 field) 401 { 402 switch (field) { 403 case GIC_BASER_CACHE_nCnB: 404 case GIC_BASER_CACHE_nC: 405 return GIC_BASER_CACHE_RaWb; 406 default: 407 return field; 408 } 409 } 410 411 /* Non-cacheable or same-as-inner are OK. */ 412 u64 vgic_sanitise_outer_cacheability(u64 field) 413 { 414 switch (field) { 415 case GIC_BASER_CACHE_SameAsInner: 416 case GIC_BASER_CACHE_nC: 417 return field; 418 default: 419 return GIC_BASER_CACHE_SameAsInner; 420 } 421 } 422 423 u64 vgic_sanitise_field(u64 reg, u64 field_mask, int field_shift, 424 u64 (*sanitise_fn)(u64)) 425 { 426 u64 field = (reg & field_mask) >> field_shift; 427 428 field = sanitise_fn(field) << field_shift; 429 return (reg & ~field_mask) | field; 430 } 431 432 #define PROPBASER_RES0_MASK \ 433 (GENMASK_ULL(63, 59) | GENMASK_ULL(55, 52) | GENMASK_ULL(6, 5)) 434 #define PENDBASER_RES0_MASK \ 435 (BIT_ULL(63) | GENMASK_ULL(61, 59) | GENMASK_ULL(55, 52) | \ 436 GENMASK_ULL(15, 12) | GENMASK_ULL(6, 0)) 437 438 static u64 vgic_sanitise_pendbaser(u64 reg) 439 { 440 reg = vgic_sanitise_field(reg, GICR_PENDBASER_SHAREABILITY_MASK, 441 GICR_PENDBASER_SHAREABILITY_SHIFT, 442 vgic_sanitise_shareability); 443 reg = vgic_sanitise_field(reg, GICR_PENDBASER_INNER_CACHEABILITY_MASK, 444 GICR_PENDBASER_INNER_CACHEABILITY_SHIFT, 445 vgic_sanitise_inner_cacheability); 446 reg = vgic_sanitise_field(reg, GICR_PENDBASER_OUTER_CACHEABILITY_MASK, 447 GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT, 448 vgic_sanitise_outer_cacheability); 449 450 reg &= ~PENDBASER_RES0_MASK; 451 452 return reg; 453 } 454 455 static u64 vgic_sanitise_propbaser(u64 reg) 456 { 457 reg = vgic_sanitise_field(reg, GICR_PROPBASER_SHAREABILITY_MASK, 458 GICR_PROPBASER_SHAREABILITY_SHIFT, 459 vgic_sanitise_shareability); 460 reg = vgic_sanitise_field(reg, GICR_PROPBASER_INNER_CACHEABILITY_MASK, 461 GICR_PROPBASER_INNER_CACHEABILITY_SHIFT, 462 vgic_sanitise_inner_cacheability); 463 reg = vgic_sanitise_field(reg, GICR_PROPBASER_OUTER_CACHEABILITY_MASK, 464 GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT, 465 vgic_sanitise_outer_cacheability); 466 467 reg &= ~PROPBASER_RES0_MASK; 468 return reg; 469 } 470 471 static unsigned long vgic_mmio_read_propbase(struct kvm_vcpu *vcpu, 472 gpa_t addr, unsigned int len) 473 { 474 struct vgic_dist *dist = &vcpu->kvm->arch.vgic; 475 476 return extract_bytes(dist->propbaser, addr & 7, len); 477 } 478 479 static void vgic_mmio_write_propbase(struct kvm_vcpu *vcpu, 480 gpa_t addr, unsigned int len, 481 unsigned long val) 482 { 483 struct vgic_dist *dist = &vcpu->kvm->arch.vgic; 484 u64 old_propbaser, propbaser; 485 486 /* Storing a value with LPIs already enabled is undefined */ 487 if (vgic_lpis_enabled(vcpu)) 488 return; 489 490 do { 491 old_propbaser = READ_ONCE(dist->propbaser); 492 propbaser = old_propbaser; 493 propbaser = update_64bit_reg(propbaser, addr & 4, len, val); 494 propbaser = vgic_sanitise_propbaser(propbaser); 495 } while (cmpxchg64(&dist->propbaser, old_propbaser, 496 propbaser) != old_propbaser); 497 } 498 499 static unsigned long vgic_mmio_read_pendbase(struct kvm_vcpu *vcpu, 500 gpa_t addr, unsigned int len) 501 { 502 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; 503 u64 value = vgic_cpu->pendbaser; 504 505 value &= ~GICR_PENDBASER_PTZ; 506 507 return extract_bytes(value, addr & 7, len); 508 } 509 510 static void vgic_mmio_write_pendbase(struct kvm_vcpu *vcpu, 511 gpa_t addr, unsigned int len, 512 unsigned long val) 513 { 514 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; 515 u64 old_pendbaser, pendbaser; 516 517 /* Storing a value with LPIs already enabled is undefined */ 518 if (vgic_lpis_enabled(vcpu)) 519 return; 520 521 do { 522 old_pendbaser = READ_ONCE(vgic_cpu->pendbaser); 523 pendbaser = old_pendbaser; 524 pendbaser = update_64bit_reg(pendbaser, addr & 4, len, val); 525 pendbaser = vgic_sanitise_pendbaser(pendbaser); 526 } while (cmpxchg64(&vgic_cpu->pendbaser, old_pendbaser, 527 pendbaser) != old_pendbaser); 528 } 529 530 static unsigned long vgic_mmio_read_sync(struct kvm_vcpu *vcpu, 531 gpa_t addr, unsigned int len) 532 { 533 return !!atomic_read(&vcpu->arch.vgic_cpu.syncr_busy); 534 } 535 536 static void vgic_set_rdist_busy(struct kvm_vcpu *vcpu, bool busy) 537 { 538 if (busy) { 539 atomic_inc(&vcpu->arch.vgic_cpu.syncr_busy); 540 smp_mb__after_atomic(); 541 } else { 542 smp_mb__before_atomic(); 543 atomic_dec(&vcpu->arch.vgic_cpu.syncr_busy); 544 } 545 } 546 547 static void vgic_mmio_write_invlpi(struct kvm_vcpu *vcpu, 548 gpa_t addr, unsigned int len, 549 unsigned long val) 550 { 551 struct vgic_irq *irq; 552 u32 intid; 553 554 /* 555 * If the guest wrote only to the upper 32bit part of the 556 * register, drop the write on the floor, as it is only for 557 * vPEs (which we don't support for obvious reasons). 558 * 559 * Also discard the access if LPIs are not enabled. 560 */ 561 if ((addr & 4) || !vgic_lpis_enabled(vcpu)) 562 return; 563 564 intid = lower_32_bits(val); 565 if (intid < VGIC_MIN_LPI) 566 return; 567 568 vgic_set_rdist_busy(vcpu, true); 569 570 irq = vgic_get_irq(vcpu->kvm, intid); 571 if (irq) { 572 vgic_its_inv_lpi(vcpu->kvm, irq); 573 vgic_put_irq(vcpu->kvm, irq); 574 } 575 576 vgic_set_rdist_busy(vcpu, false); 577 } 578 579 static void vgic_mmio_write_invall(struct kvm_vcpu *vcpu, 580 gpa_t addr, unsigned int len, 581 unsigned long val) 582 { 583 /* See vgic_mmio_write_invlpi() for the early return rationale */ 584 if ((addr & 4) || !vgic_lpis_enabled(vcpu)) 585 return; 586 587 vgic_set_rdist_busy(vcpu, true); 588 vgic_its_invall(vcpu); 589 vgic_set_rdist_busy(vcpu, false); 590 } 591 592 /* 593 * The GICv3 per-IRQ registers are split to control PPIs and SGIs in the 594 * redistributors, while SPIs are covered by registers in the distributor 595 * block. Trying to set private IRQs in this block gets ignored. 596 * We take some special care here to fix the calculation of the register 597 * offset. 598 */ 599 #define REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(off, rd, wr, ur, uw, bpi, acc) \ 600 { \ 601 .reg_offset = off, \ 602 .bits_per_irq = bpi, \ 603 .len = (bpi * VGIC_NR_PRIVATE_IRQS) / 8, \ 604 .access_flags = acc, \ 605 .read = vgic_mmio_read_raz, \ 606 .write = vgic_mmio_write_wi, \ 607 }, { \ 608 .reg_offset = off + (bpi * VGIC_NR_PRIVATE_IRQS) / 8, \ 609 .bits_per_irq = bpi, \ 610 .len = (bpi * (1024 - VGIC_NR_PRIVATE_IRQS)) / 8, \ 611 .access_flags = acc, \ 612 .read = rd, \ 613 .write = wr, \ 614 .uaccess_read = ur, \ 615 .uaccess_write = uw, \ 616 } 617 618 static const struct vgic_register_region vgic_v3_dist_registers[] = { 619 REGISTER_DESC_WITH_LENGTH_UACCESS(GICD_CTLR, 620 vgic_mmio_read_v3_misc, vgic_mmio_write_v3_misc, 621 NULL, vgic_mmio_uaccess_write_v3_misc, 622 16, VGIC_ACCESS_32bit), 623 REGISTER_DESC_WITH_LENGTH(GICD_STATUSR, 624 vgic_mmio_read_rao, vgic_mmio_write_wi, 4, 625 VGIC_ACCESS_32bit), 626 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGROUPR, 627 vgic_mmio_read_group, vgic_mmio_write_group, NULL, NULL, 1, 628 VGIC_ACCESS_32bit), 629 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISENABLER, 630 vgic_mmio_read_enable, vgic_mmio_write_senable, 631 NULL, vgic_uaccess_write_senable, 1, 632 VGIC_ACCESS_32bit), 633 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICENABLER, 634 vgic_mmio_read_enable, vgic_mmio_write_cenable, 635 NULL, vgic_uaccess_write_cenable, 1, 636 VGIC_ACCESS_32bit), 637 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISPENDR, 638 vgic_mmio_read_pending, vgic_mmio_write_spending, 639 vgic_uaccess_read_pending, vgic_v3_uaccess_write_pending, 1, 640 VGIC_ACCESS_32bit), 641 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICPENDR, 642 vgic_mmio_read_pending, vgic_mmio_write_cpending, 643 vgic_mmio_read_raz, vgic_mmio_uaccess_write_wi, 1, 644 VGIC_ACCESS_32bit), 645 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISACTIVER, 646 vgic_mmio_read_active, vgic_mmio_write_sactive, 647 vgic_uaccess_read_active, vgic_mmio_uaccess_write_sactive, 1, 648 VGIC_ACCESS_32bit), 649 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICACTIVER, 650 vgic_mmio_read_active, vgic_mmio_write_cactive, 651 vgic_uaccess_read_active, vgic_mmio_uaccess_write_cactive, 652 1, VGIC_ACCESS_32bit), 653 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IPRIORITYR, 654 vgic_mmio_read_priority, vgic_mmio_write_priority, NULL, NULL, 655 8, VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), 656 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ITARGETSR, 657 vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 8, 658 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), 659 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICFGR, 660 vgic_mmio_read_config, vgic_mmio_write_config, NULL, NULL, 2, 661 VGIC_ACCESS_32bit), 662 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGRPMODR, 663 vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 1, 664 VGIC_ACCESS_32bit), 665 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IROUTER, 666 vgic_mmio_read_irouter, vgic_mmio_write_irouter, NULL, NULL, 64, 667 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit), 668 REGISTER_DESC_WITH_LENGTH(GICD_IDREGS, 669 vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48, 670 VGIC_ACCESS_32bit), 671 }; 672 673 static const struct vgic_register_region vgic_v3_rd_registers[] = { 674 /* RD_base registers */ 675 REGISTER_DESC_WITH_LENGTH(GICR_CTLR, 676 vgic_mmio_read_v3r_ctlr, vgic_mmio_write_v3r_ctlr, 4, 677 VGIC_ACCESS_32bit), 678 REGISTER_DESC_WITH_LENGTH(GICR_STATUSR, 679 vgic_mmio_read_raz, vgic_mmio_write_wi, 4, 680 VGIC_ACCESS_32bit), 681 REGISTER_DESC_WITH_LENGTH(GICR_IIDR, 682 vgic_mmio_read_v3r_iidr, vgic_mmio_write_wi, 4, 683 VGIC_ACCESS_32bit), 684 REGISTER_DESC_WITH_LENGTH_UACCESS(GICR_TYPER, 685 vgic_mmio_read_v3r_typer, vgic_mmio_write_wi, 686 NULL, vgic_mmio_uaccess_write_wi, 8, 687 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit), 688 REGISTER_DESC_WITH_LENGTH(GICR_WAKER, 689 vgic_mmio_read_raz, vgic_mmio_write_wi, 4, 690 VGIC_ACCESS_32bit), 691 REGISTER_DESC_WITH_LENGTH(GICR_PROPBASER, 692 vgic_mmio_read_propbase, vgic_mmio_write_propbase, 8, 693 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit), 694 REGISTER_DESC_WITH_LENGTH(GICR_PENDBASER, 695 vgic_mmio_read_pendbase, vgic_mmio_write_pendbase, 8, 696 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit), 697 REGISTER_DESC_WITH_LENGTH(GICR_INVLPIR, 698 vgic_mmio_read_raz, vgic_mmio_write_invlpi, 8, 699 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit), 700 REGISTER_DESC_WITH_LENGTH(GICR_INVALLR, 701 vgic_mmio_read_raz, vgic_mmio_write_invall, 8, 702 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit), 703 REGISTER_DESC_WITH_LENGTH(GICR_SYNCR, 704 vgic_mmio_read_sync, vgic_mmio_write_wi, 4, 705 VGIC_ACCESS_32bit), 706 REGISTER_DESC_WITH_LENGTH(GICR_IDREGS, 707 vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48, 708 VGIC_ACCESS_32bit), 709 /* SGI_base registers */ 710 REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_IGROUPR0, 711 vgic_mmio_read_group, vgic_mmio_write_group, 4, 712 VGIC_ACCESS_32bit), 713 REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ISENABLER0, 714 vgic_mmio_read_enable, vgic_mmio_write_senable, 715 NULL, vgic_uaccess_write_senable, 4, 716 VGIC_ACCESS_32bit), 717 REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ICENABLER0, 718 vgic_mmio_read_enable, vgic_mmio_write_cenable, 719 NULL, vgic_uaccess_write_cenable, 4, 720 VGIC_ACCESS_32bit), 721 REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ISPENDR0, 722 vgic_mmio_read_pending, vgic_mmio_write_spending, 723 vgic_uaccess_read_pending, vgic_v3_uaccess_write_pending, 4, 724 VGIC_ACCESS_32bit), 725 REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ICPENDR0, 726 vgic_mmio_read_pending, vgic_mmio_write_cpending, 727 vgic_mmio_read_raz, vgic_mmio_uaccess_write_wi, 4, 728 VGIC_ACCESS_32bit), 729 REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ISACTIVER0, 730 vgic_mmio_read_active, vgic_mmio_write_sactive, 731 vgic_uaccess_read_active, vgic_mmio_uaccess_write_sactive, 4, 732 VGIC_ACCESS_32bit), 733 REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ICACTIVER0, 734 vgic_mmio_read_active, vgic_mmio_write_cactive, 735 vgic_uaccess_read_active, vgic_mmio_uaccess_write_cactive, 4, 736 VGIC_ACCESS_32bit), 737 REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_IPRIORITYR0, 738 vgic_mmio_read_priority, vgic_mmio_write_priority, 32, 739 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), 740 REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_ICFGR0, 741 vgic_mmio_read_config, vgic_mmio_write_config, 8, 742 VGIC_ACCESS_32bit), 743 REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_IGRPMODR0, 744 vgic_mmio_read_raz, vgic_mmio_write_wi, 4, 745 VGIC_ACCESS_32bit), 746 REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_NSACR, 747 vgic_mmio_read_raz, vgic_mmio_write_wi, 4, 748 VGIC_ACCESS_32bit), 749 }; 750 751 unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev) 752 { 753 dev->regions = vgic_v3_dist_registers; 754 dev->nr_regions = ARRAY_SIZE(vgic_v3_dist_registers); 755 756 kvm_iodevice_init(&dev->dev, &kvm_io_gic_ops); 757 758 return SZ_64K; 759 } 760 761 /** 762 * vgic_register_redist_iodev - register a single redist iodev 763 * @vcpu: The VCPU to which the redistributor belongs 764 * 765 * Register a KVM iodev for this VCPU's redistributor using the address 766 * provided. 767 * 768 * Return 0 on success, -ERRNO otherwise. 769 */ 770 int vgic_register_redist_iodev(struct kvm_vcpu *vcpu) 771 { 772 struct kvm *kvm = vcpu->kvm; 773 struct vgic_dist *vgic = &kvm->arch.vgic; 774 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; 775 struct vgic_io_device *rd_dev = &vcpu->arch.vgic_cpu.rd_iodev; 776 struct vgic_redist_region *rdreg; 777 gpa_t rd_base; 778 int ret = 0; 779 780 lockdep_assert_held(&kvm->slots_lock); 781 mutex_lock(&kvm->arch.config_lock); 782 783 if (!IS_VGIC_ADDR_UNDEF(vgic_cpu->rd_iodev.base_addr)) 784 goto out_unlock; 785 786 /* 787 * We may be creating VCPUs before having set the base address for the 788 * redistributor region, in which case we will come back to this 789 * function for all VCPUs when the base address is set. Just return 790 * without doing any work for now. 791 */ 792 rdreg = vgic_v3_rdist_free_slot(&vgic->rd_regions); 793 if (!rdreg) 794 goto out_unlock; 795 796 if (!vgic_v3_check_base(kvm)) { 797 ret = -EINVAL; 798 goto out_unlock; 799 } 800 801 vgic_cpu->rdreg = rdreg; 802 vgic_cpu->rdreg_index = rdreg->free_index; 803 804 rd_base = rdreg->base + rdreg->free_index * KVM_VGIC_V3_REDIST_SIZE; 805 806 kvm_iodevice_init(&rd_dev->dev, &kvm_io_gic_ops); 807 rd_dev->base_addr = rd_base; 808 rd_dev->iodev_type = IODEV_REDIST; 809 rd_dev->regions = vgic_v3_rd_registers; 810 rd_dev->nr_regions = ARRAY_SIZE(vgic_v3_rd_registers); 811 rd_dev->redist_vcpu = vcpu; 812 813 mutex_unlock(&kvm->arch.config_lock); 814 815 ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, rd_base, 816 2 * SZ_64K, &rd_dev->dev); 817 if (ret) 818 return ret; 819 820 /* Protected by slots_lock */ 821 rdreg->free_index++; 822 return 0; 823 824 out_unlock: 825 mutex_unlock(&kvm->arch.config_lock); 826 return ret; 827 } 828 829 void vgic_unregister_redist_iodev(struct kvm_vcpu *vcpu) 830 { 831 struct vgic_io_device *rd_dev = &vcpu->arch.vgic_cpu.rd_iodev; 832 833 kvm_io_bus_unregister_dev(vcpu->kvm, KVM_MMIO_BUS, &rd_dev->dev); 834 } 835 836 static int vgic_register_all_redist_iodevs(struct kvm *kvm) 837 { 838 struct kvm_vcpu *vcpu; 839 unsigned long c; 840 int ret = 0; 841 842 lockdep_assert_held(&kvm->slots_lock); 843 844 kvm_for_each_vcpu(c, vcpu, kvm) { 845 ret = vgic_register_redist_iodev(vcpu); 846 if (ret) 847 break; 848 } 849 850 if (ret) { 851 /* The current c failed, so iterate over the previous ones. */ 852 int i; 853 854 for (i = 0; i < c; i++) { 855 vcpu = kvm_get_vcpu(kvm, i); 856 vgic_unregister_redist_iodev(vcpu); 857 } 858 } 859 860 return ret; 861 } 862 863 /** 864 * vgic_v3_alloc_redist_region - Allocate a new redistributor region 865 * 866 * Performs various checks before inserting the rdist region in the list. 867 * Those tests depend on whether the size of the rdist region is known 868 * (ie. count != 0). The list is sorted by rdist region index. 869 * 870 * @kvm: kvm handle 871 * @index: redist region index 872 * @base: base of the new rdist region 873 * @count: number of redistributors the region is made of (0 in the old style 874 * single region, whose size is induced from the number of vcpus) 875 * 876 * Return 0 on success, < 0 otherwise 877 */ 878 static int vgic_v3_alloc_redist_region(struct kvm *kvm, uint32_t index, 879 gpa_t base, uint32_t count) 880 { 881 struct vgic_dist *d = &kvm->arch.vgic; 882 struct vgic_redist_region *rdreg; 883 struct list_head *rd_regions = &d->rd_regions; 884 int nr_vcpus = atomic_read(&kvm->online_vcpus); 885 size_t size = count ? count * KVM_VGIC_V3_REDIST_SIZE 886 : nr_vcpus * KVM_VGIC_V3_REDIST_SIZE; 887 int ret; 888 889 /* cross the end of memory ? */ 890 if (base + size < base) 891 return -EINVAL; 892 893 if (list_empty(rd_regions)) { 894 if (index != 0) 895 return -EINVAL; 896 } else { 897 rdreg = list_last_entry(rd_regions, 898 struct vgic_redist_region, list); 899 900 /* Don't mix single region and discrete redist regions */ 901 if (!count && rdreg->count) 902 return -EINVAL; 903 904 if (!count) 905 return -EEXIST; 906 907 if (index != rdreg->index + 1) 908 return -EINVAL; 909 } 910 911 /* 912 * For legacy single-region redistributor regions (!count), 913 * check that the redistributor region does not overlap with the 914 * distributor's address space. 915 */ 916 if (!count && !IS_VGIC_ADDR_UNDEF(d->vgic_dist_base) && 917 vgic_dist_overlap(kvm, base, size)) 918 return -EINVAL; 919 920 /* collision with any other rdist region? */ 921 if (vgic_v3_rdist_overlap(kvm, base, size)) 922 return -EINVAL; 923 924 rdreg = kzalloc(sizeof(*rdreg), GFP_KERNEL_ACCOUNT); 925 if (!rdreg) 926 return -ENOMEM; 927 928 rdreg->base = VGIC_ADDR_UNDEF; 929 930 ret = vgic_check_iorange(kvm, rdreg->base, base, SZ_64K, size); 931 if (ret) 932 goto free; 933 934 rdreg->base = base; 935 rdreg->count = count; 936 rdreg->free_index = 0; 937 rdreg->index = index; 938 939 list_add_tail(&rdreg->list, rd_regions); 940 return 0; 941 free: 942 kfree(rdreg); 943 return ret; 944 } 945 946 void vgic_v3_free_redist_region(struct kvm *kvm, struct vgic_redist_region *rdreg) 947 { 948 struct kvm_vcpu *vcpu; 949 unsigned long c; 950 951 lockdep_assert_held(&kvm->arch.config_lock); 952 953 /* Garbage collect the region */ 954 kvm_for_each_vcpu(c, vcpu, kvm) { 955 if (vcpu->arch.vgic_cpu.rdreg == rdreg) 956 vcpu->arch.vgic_cpu.rdreg = NULL; 957 } 958 959 list_del(&rdreg->list); 960 kfree(rdreg); 961 } 962 963 int vgic_v3_set_redist_base(struct kvm *kvm, u32 index, u64 addr, u32 count) 964 { 965 int ret; 966 967 mutex_lock(&kvm->arch.config_lock); 968 ret = vgic_v3_alloc_redist_region(kvm, index, addr, count); 969 mutex_unlock(&kvm->arch.config_lock); 970 if (ret) 971 return ret; 972 973 /* 974 * Register iodevs for each existing VCPU. Adding more VCPUs 975 * afterwards will register the iodevs when needed. 976 */ 977 ret = vgic_register_all_redist_iodevs(kvm); 978 if (ret) { 979 struct vgic_redist_region *rdreg; 980 981 mutex_lock(&kvm->arch.config_lock); 982 rdreg = vgic_v3_rdist_region_from_index(kvm, index); 983 vgic_v3_free_redist_region(kvm, rdreg); 984 mutex_unlock(&kvm->arch.config_lock); 985 return ret; 986 } 987 988 return 0; 989 } 990 991 int vgic_v3_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr) 992 { 993 const struct vgic_register_region *region; 994 struct vgic_io_device iodev; 995 struct vgic_reg_attr reg_attr; 996 struct kvm_vcpu *vcpu; 997 gpa_t addr; 998 int ret; 999 1000 ret = vgic_v3_parse_attr(dev, attr, ®_attr); 1001 if (ret) 1002 return ret; 1003 1004 vcpu = reg_attr.vcpu; 1005 addr = reg_attr.addr; 1006 1007 switch (attr->group) { 1008 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS: 1009 iodev.regions = vgic_v3_dist_registers; 1010 iodev.nr_regions = ARRAY_SIZE(vgic_v3_dist_registers); 1011 iodev.base_addr = 0; 1012 break; 1013 case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS:{ 1014 iodev.regions = vgic_v3_rd_registers; 1015 iodev.nr_regions = ARRAY_SIZE(vgic_v3_rd_registers); 1016 iodev.base_addr = 0; 1017 break; 1018 } 1019 case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS: 1020 return vgic_v3_has_cpu_sysregs_attr(vcpu, attr); 1021 default: 1022 return -ENXIO; 1023 } 1024 1025 /* We only support aligned 32-bit accesses. */ 1026 if (addr & 3) 1027 return -ENXIO; 1028 1029 region = vgic_get_mmio_region(vcpu, &iodev, addr, sizeof(u32)); 1030 if (!region) 1031 return -ENXIO; 1032 1033 return 0; 1034 } 1035 1036 /* 1037 * The ICC_SGI* registers encode the affinity differently from the MPIDR, 1038 * so provide a wrapper to use the existing defines to isolate a certain 1039 * affinity level. 1040 */ 1041 #define SGI_AFFINITY_LEVEL(reg, level) \ 1042 ((((reg) & ICC_SGI1R_AFFINITY_## level ##_MASK) \ 1043 >> ICC_SGI1R_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level)) 1044 1045 static void vgic_v3_queue_sgi(struct kvm_vcpu *vcpu, u32 sgi, bool allow_group1) 1046 { 1047 struct vgic_irq *irq = vgic_get_vcpu_irq(vcpu, sgi); 1048 unsigned long flags; 1049 1050 raw_spin_lock_irqsave(&irq->irq_lock, flags); 1051 1052 /* 1053 * An access targeting Group0 SGIs can only generate 1054 * those, while an access targeting Group1 SGIs can 1055 * generate interrupts of either group. 1056 */ 1057 if (!irq->group || allow_group1) { 1058 if (!irq->hw) { 1059 irq->pending_latch = true; 1060 vgic_queue_irq_unlock(vcpu->kvm, irq, flags); 1061 } else { 1062 /* HW SGI? Ask the GIC to inject it */ 1063 int err; 1064 err = irq_set_irqchip_state(irq->host_irq, 1065 IRQCHIP_STATE_PENDING, 1066 true); 1067 WARN_RATELIMIT(err, "IRQ %d", irq->host_irq); 1068 raw_spin_unlock_irqrestore(&irq->irq_lock, flags); 1069 } 1070 } else { 1071 raw_spin_unlock_irqrestore(&irq->irq_lock, flags); 1072 } 1073 1074 vgic_put_irq(vcpu->kvm, irq); 1075 } 1076 1077 /** 1078 * vgic_v3_dispatch_sgi - handle SGI requests from VCPUs 1079 * @vcpu: The VCPU requesting a SGI 1080 * @reg: The value written into ICC_{ASGI1,SGI0,SGI1}R by that VCPU 1081 * @allow_group1: Does the sysreg access allow generation of G1 SGIs 1082 * 1083 * With GICv3 (and ARE=1) CPUs trigger SGIs by writing to a system register. 1084 * This will trap in sys_regs.c and call this function. 1085 * This ICC_SGI1R_EL1 register contains the upper three affinity levels of the 1086 * target processors as well as a bitmask of 16 Aff0 CPUs. 1087 * 1088 * If the interrupt routing mode bit is not set, we iterate over the Aff0 1089 * bits and signal the VCPUs matching the provided Aff{3,2,1}. 1090 * 1091 * If this bit is set, we signal all, but not the calling VCPU. 1092 */ 1093 void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg, bool allow_group1) 1094 { 1095 struct kvm *kvm = vcpu->kvm; 1096 struct kvm_vcpu *c_vcpu; 1097 unsigned long target_cpus; 1098 u64 mpidr; 1099 u32 sgi, aff0; 1100 unsigned long c; 1101 1102 sgi = FIELD_GET(ICC_SGI1R_SGI_ID_MASK, reg); 1103 1104 /* Broadcast */ 1105 if (unlikely(reg & BIT_ULL(ICC_SGI1R_IRQ_ROUTING_MODE_BIT))) { 1106 kvm_for_each_vcpu(c, c_vcpu, kvm) { 1107 /* Don't signal the calling VCPU */ 1108 if (c_vcpu == vcpu) 1109 continue; 1110 1111 vgic_v3_queue_sgi(c_vcpu, sgi, allow_group1); 1112 } 1113 1114 return; 1115 } 1116 1117 /* We iterate over affinities to find the corresponding vcpus */ 1118 mpidr = SGI_AFFINITY_LEVEL(reg, 3); 1119 mpidr |= SGI_AFFINITY_LEVEL(reg, 2); 1120 mpidr |= SGI_AFFINITY_LEVEL(reg, 1); 1121 target_cpus = FIELD_GET(ICC_SGI1R_TARGET_LIST_MASK, reg); 1122 1123 for_each_set_bit(aff0, &target_cpus, hweight_long(ICC_SGI1R_TARGET_LIST_MASK)) { 1124 c_vcpu = kvm_mpidr_to_vcpu(kvm, mpidr | aff0); 1125 if (c_vcpu) 1126 vgic_v3_queue_sgi(c_vcpu, sgi, allow_group1); 1127 } 1128 } 1129 1130 int vgic_v3_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write, 1131 int offset, u32 *val) 1132 { 1133 struct vgic_io_device dev = { 1134 .regions = vgic_v3_dist_registers, 1135 .nr_regions = ARRAY_SIZE(vgic_v3_dist_registers), 1136 }; 1137 1138 return vgic_uaccess(vcpu, &dev, is_write, offset, val); 1139 } 1140 1141 int vgic_v3_redist_uaccess(struct kvm_vcpu *vcpu, bool is_write, 1142 int offset, u32 *val) 1143 { 1144 struct vgic_io_device rd_dev = { 1145 .regions = vgic_v3_rd_registers, 1146 .nr_regions = ARRAY_SIZE(vgic_v3_rd_registers), 1147 }; 1148 1149 return vgic_uaccess(vcpu, &rd_dev, is_write, offset, val); 1150 } 1151 1152 int vgic_v3_line_level_info_uaccess(struct kvm_vcpu *vcpu, bool is_write, 1153 u32 intid, u32 *val) 1154 { 1155 if (intid % 32) 1156 return -EINVAL; 1157 1158 if (is_write) 1159 vgic_write_irq_line_level_info(vcpu, intid, *val); 1160 else 1161 *val = vgic_read_irq_line_level_info(vcpu, intid); 1162 1163 return 0; 1164 } 1165