1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * VGIC: KVM DEVICE API 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 * Author: Marc Zyngier <marc.zyngier@arm.com> 7 */ 8 #include <linux/irqchip/arm-gic-v3.h> 9 #include <linux/kvm_host.h> 10 #include <kvm/arm_vgic.h> 11 #include <linux/uaccess.h> 12 #include <asm/kvm_mmu.h> 13 #include <asm/cputype.h> 14 #include "vgic.h" 15 16 /* common helpers */ 17 18 int vgic_check_iorange(struct kvm *kvm, phys_addr_t ioaddr, 19 phys_addr_t addr, phys_addr_t alignment, 20 phys_addr_t size) 21 { 22 if (!IS_VGIC_ADDR_UNDEF(ioaddr)) 23 return -EEXIST; 24 25 if (!IS_ALIGNED(addr, alignment) || !IS_ALIGNED(size, alignment)) 26 return -EINVAL; 27 28 if (addr + size < addr) 29 return -EINVAL; 30 31 if (addr & ~kvm_phys_mask(&kvm->arch.mmu) || 32 (addr + size) > kvm_phys_size(&kvm->arch.mmu)) 33 return -E2BIG; 34 35 return 0; 36 } 37 38 static int vgic_check_type(struct kvm *kvm, int type_needed) 39 { 40 if (kvm->arch.vgic.vgic_model != type_needed) 41 return -ENODEV; 42 else 43 return 0; 44 } 45 46 int kvm_set_legacy_vgic_v2_addr(struct kvm *kvm, struct kvm_arm_device_addr *dev_addr) 47 { 48 struct vgic_dist *vgic = &kvm->arch.vgic; 49 int r; 50 51 mutex_lock(&kvm->arch.config_lock); 52 switch (FIELD_GET(KVM_ARM_DEVICE_TYPE_MASK, dev_addr->id)) { 53 case KVM_VGIC_V2_ADDR_TYPE_DIST: 54 r = vgic_check_type(kvm, KVM_DEV_TYPE_ARM_VGIC_V2); 55 if (!r) 56 r = vgic_check_iorange(kvm, vgic->vgic_dist_base, dev_addr->addr, 57 SZ_4K, KVM_VGIC_V2_DIST_SIZE); 58 if (!r) 59 vgic->vgic_dist_base = dev_addr->addr; 60 break; 61 case KVM_VGIC_V2_ADDR_TYPE_CPU: 62 r = vgic_check_type(kvm, KVM_DEV_TYPE_ARM_VGIC_V2); 63 if (!r) 64 r = vgic_check_iorange(kvm, vgic->vgic_cpu_base, dev_addr->addr, 65 SZ_4K, KVM_VGIC_V2_CPU_SIZE); 66 if (!r) 67 vgic->vgic_cpu_base = dev_addr->addr; 68 break; 69 default: 70 r = -ENODEV; 71 } 72 73 mutex_unlock(&kvm->arch.config_lock); 74 75 return r; 76 } 77 78 /** 79 * kvm_vgic_addr - set or get vgic VM base addresses 80 * @kvm: pointer to the vm struct 81 * @attr: pointer to the attribute being retrieved/updated 82 * @write: if true set the address in the VM address space, if false read the 83 * address 84 * 85 * Set or get the vgic base addresses for the distributor and the virtual CPU 86 * interface in the VM physical address space. These addresses are properties 87 * of the emulated core/SoC and therefore user space initially knows this 88 * information. 89 * Check them for sanity (alignment, double assignment). We can't check for 90 * overlapping regions in case of a virtual GICv3 here, since we don't know 91 * the number of VCPUs yet, so we defer this check to map_resources(). 92 */ 93 static int kvm_vgic_addr(struct kvm *kvm, struct kvm_device_attr *attr, bool write) 94 { 95 u64 __user *uaddr = (u64 __user *)attr->addr; 96 struct vgic_dist *vgic = &kvm->arch.vgic; 97 phys_addr_t *addr_ptr, alignment, size; 98 u64 undef_value = VGIC_ADDR_UNDEF; 99 u64 addr; 100 int r; 101 102 /* Reading a redistributor region addr implies getting the index */ 103 if (write || attr->attr == KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION) 104 if (get_user(addr, uaddr)) 105 return -EFAULT; 106 107 /* 108 * Since we can't hold config_lock while registering the redistributor 109 * iodevs, take the slots_lock immediately. 110 */ 111 mutex_lock(&kvm->slots_lock); 112 switch (attr->attr) { 113 case KVM_VGIC_V2_ADDR_TYPE_DIST: 114 r = vgic_check_type(kvm, KVM_DEV_TYPE_ARM_VGIC_V2); 115 addr_ptr = &vgic->vgic_dist_base; 116 alignment = SZ_4K; 117 size = KVM_VGIC_V2_DIST_SIZE; 118 break; 119 case KVM_VGIC_V2_ADDR_TYPE_CPU: 120 r = vgic_check_type(kvm, KVM_DEV_TYPE_ARM_VGIC_V2); 121 addr_ptr = &vgic->vgic_cpu_base; 122 alignment = SZ_4K; 123 size = KVM_VGIC_V2_CPU_SIZE; 124 break; 125 case KVM_VGIC_V3_ADDR_TYPE_DIST: 126 r = vgic_check_type(kvm, KVM_DEV_TYPE_ARM_VGIC_V3); 127 addr_ptr = &vgic->vgic_dist_base; 128 alignment = SZ_64K; 129 size = KVM_VGIC_V3_DIST_SIZE; 130 break; 131 case KVM_VGIC_V3_ADDR_TYPE_REDIST: { 132 struct vgic_redist_region *rdreg; 133 134 r = vgic_check_type(kvm, KVM_DEV_TYPE_ARM_VGIC_V3); 135 if (r) 136 break; 137 if (write) { 138 r = vgic_v3_set_redist_base(kvm, 0, addr, 0); 139 goto out; 140 } 141 rdreg = list_first_entry_or_null(&vgic->rd_regions, 142 struct vgic_redist_region, list); 143 if (!rdreg) 144 addr_ptr = &undef_value; 145 else 146 addr_ptr = &rdreg->base; 147 break; 148 } 149 case KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION: 150 { 151 struct vgic_redist_region *rdreg; 152 u8 index; 153 154 r = vgic_check_type(kvm, KVM_DEV_TYPE_ARM_VGIC_V3); 155 if (r) 156 break; 157 158 index = addr & KVM_VGIC_V3_RDIST_INDEX_MASK; 159 160 if (write) { 161 gpa_t base = addr & KVM_VGIC_V3_RDIST_BASE_MASK; 162 u32 count = FIELD_GET(KVM_VGIC_V3_RDIST_COUNT_MASK, addr); 163 u8 flags = FIELD_GET(KVM_VGIC_V3_RDIST_FLAGS_MASK, addr); 164 165 if (!count || flags) 166 r = -EINVAL; 167 else 168 r = vgic_v3_set_redist_base(kvm, index, 169 base, count); 170 goto out; 171 } 172 173 rdreg = vgic_v3_rdist_region_from_index(kvm, index); 174 if (!rdreg) { 175 r = -ENOENT; 176 goto out; 177 } 178 179 addr = index; 180 addr |= rdreg->base; 181 addr |= (u64)rdreg->count << KVM_VGIC_V3_RDIST_COUNT_SHIFT; 182 goto out; 183 } 184 default: 185 r = -ENODEV; 186 } 187 188 if (r) 189 goto out; 190 191 mutex_lock(&kvm->arch.config_lock); 192 if (write) { 193 r = vgic_check_iorange(kvm, *addr_ptr, addr, alignment, size); 194 if (!r) 195 *addr_ptr = addr; 196 } else { 197 addr = *addr_ptr; 198 } 199 mutex_unlock(&kvm->arch.config_lock); 200 201 out: 202 mutex_unlock(&kvm->slots_lock); 203 204 if (!r && !write) 205 r = put_user(addr, uaddr); 206 207 return r; 208 } 209 210 static int vgic_set_common_attr(struct kvm_device *dev, 211 struct kvm_device_attr *attr) 212 { 213 int r; 214 215 switch (attr->group) { 216 case KVM_DEV_ARM_VGIC_GRP_ADDR: 217 r = kvm_vgic_addr(dev->kvm, attr, true); 218 return (r == -ENODEV) ? -ENXIO : r; 219 case KVM_DEV_ARM_VGIC_GRP_NR_IRQS: { 220 u32 __user *uaddr = (u32 __user *)(long)attr->addr; 221 u32 val; 222 int ret = 0; 223 224 if (get_user(val, uaddr)) 225 return -EFAULT; 226 227 /* 228 * We require: 229 * - at least 32 SPIs on top of the 16 SGIs and 16 PPIs 230 * - at most 1024 interrupts 231 * - a multiple of 32 interrupts 232 */ 233 if (val < (VGIC_NR_PRIVATE_IRQS + 32) || 234 val > VGIC_MAX_RESERVED || 235 (val & 31)) 236 return -EINVAL; 237 238 mutex_lock(&dev->kvm->arch.config_lock); 239 240 /* 241 * Either userspace has already configured NR_IRQS or 242 * the vgic has already been initialized and vgic_init() 243 * supplied a default amount of SPIs. 244 */ 245 if (dev->kvm->arch.vgic.nr_spis) 246 ret = -EBUSY; 247 else 248 dev->kvm->arch.vgic.nr_spis = 249 val - VGIC_NR_PRIVATE_IRQS; 250 251 mutex_unlock(&dev->kvm->arch.config_lock); 252 253 return ret; 254 } 255 case KVM_DEV_ARM_VGIC_GRP_CTRL: { 256 switch (attr->attr) { 257 case KVM_DEV_ARM_VGIC_CTRL_INIT: 258 mutex_lock(&dev->kvm->arch.config_lock); 259 r = vgic_init(dev->kvm); 260 mutex_unlock(&dev->kvm->arch.config_lock); 261 return r; 262 case KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES: 263 /* 264 * OK, this one isn't common at all, but we 265 * want to handle all control group attributes 266 * in a single place. 267 */ 268 if (vgic_check_type(dev->kvm, KVM_DEV_TYPE_ARM_VGIC_V3)) 269 return -ENXIO; 270 mutex_lock(&dev->kvm->lock); 271 272 if (kvm_trylock_all_vcpus(dev->kvm)) { 273 mutex_unlock(&dev->kvm->lock); 274 return -EBUSY; 275 } 276 277 mutex_lock(&dev->kvm->arch.config_lock); 278 r = vgic_v3_save_pending_tables(dev->kvm); 279 mutex_unlock(&dev->kvm->arch.config_lock); 280 kvm_unlock_all_vcpus(dev->kvm); 281 mutex_unlock(&dev->kvm->lock); 282 return r; 283 } 284 break; 285 } 286 } 287 288 return -ENXIO; 289 } 290 291 static int vgic_get_common_attr(struct kvm_device *dev, 292 struct kvm_device_attr *attr) 293 { 294 int r = -ENXIO; 295 296 switch (attr->group) { 297 case KVM_DEV_ARM_VGIC_GRP_ADDR: 298 r = kvm_vgic_addr(dev->kvm, attr, false); 299 return (r == -ENODEV) ? -ENXIO : r; 300 case KVM_DEV_ARM_VGIC_GRP_NR_IRQS: { 301 u32 __user *uaddr = (u32 __user *)(long)attr->addr; 302 303 r = put_user(dev->kvm->arch.vgic.nr_spis + 304 VGIC_NR_PRIVATE_IRQS, uaddr); 305 break; 306 } 307 } 308 309 return r; 310 } 311 312 static int vgic_create(struct kvm_device *dev, u32 type) 313 { 314 return kvm_vgic_create(dev->kvm, type); 315 } 316 317 static void vgic_destroy(struct kvm_device *dev) 318 { 319 kfree(dev); 320 } 321 322 int kvm_register_vgic_device(unsigned long type) 323 { 324 int ret = -ENODEV; 325 326 switch (type) { 327 case KVM_DEV_TYPE_ARM_VGIC_V2: 328 ret = kvm_register_device_ops(&kvm_arm_vgic_v2_ops, 329 KVM_DEV_TYPE_ARM_VGIC_V2); 330 break; 331 case KVM_DEV_TYPE_ARM_VGIC_V3: 332 ret = kvm_register_device_ops(&kvm_arm_vgic_v3_ops, 333 KVM_DEV_TYPE_ARM_VGIC_V3); 334 335 if (ret) 336 break; 337 ret = kvm_vgic_register_its_device(); 338 break; 339 case KVM_DEV_TYPE_ARM_VGIC_V5: 340 ret = kvm_register_device_ops(&kvm_arm_vgic_v5_ops, 341 KVM_DEV_TYPE_ARM_VGIC_V5); 342 break; 343 } 344 345 return ret; 346 } 347 348 int vgic_v2_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr, 349 struct vgic_reg_attr *reg_attr) 350 { 351 int cpuid = FIELD_GET(KVM_DEV_ARM_VGIC_CPUID_MASK, attr->attr); 352 353 reg_attr->addr = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK; 354 reg_attr->vcpu = kvm_get_vcpu_by_id(dev->kvm, cpuid); 355 if (!reg_attr->vcpu) 356 return -EINVAL; 357 358 return 0; 359 } 360 361 /** 362 * vgic_v2_attr_regs_access - allows user space to access VGIC v2 state 363 * 364 * @dev: kvm device handle 365 * @attr: kvm device attribute 366 * @is_write: true if userspace is writing a register 367 */ 368 static int vgic_v2_attr_regs_access(struct kvm_device *dev, 369 struct kvm_device_attr *attr, 370 bool is_write) 371 { 372 u32 __user *uaddr = (u32 __user *)(unsigned long)attr->addr; 373 struct vgic_reg_attr reg_attr; 374 gpa_t addr; 375 struct kvm_vcpu *vcpu; 376 int ret; 377 u32 val; 378 379 ret = vgic_v2_parse_attr(dev, attr, ®_attr); 380 if (ret) 381 return ret; 382 383 vcpu = reg_attr.vcpu; 384 addr = reg_attr.addr; 385 386 if (is_write) 387 if (get_user(val, uaddr)) 388 return -EFAULT; 389 390 mutex_lock(&dev->kvm->lock); 391 392 if (kvm_trylock_all_vcpus(dev->kvm)) { 393 mutex_unlock(&dev->kvm->lock); 394 return -EBUSY; 395 } 396 397 mutex_lock(&dev->kvm->arch.config_lock); 398 399 ret = vgic_init(dev->kvm); 400 if (ret) 401 goto out; 402 403 switch (attr->group) { 404 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: 405 ret = vgic_v2_cpuif_uaccess(vcpu, is_write, addr, &val); 406 break; 407 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS: 408 ret = vgic_v2_dist_uaccess(vcpu, is_write, addr, &val); 409 break; 410 default: 411 ret = -EINVAL; 412 break; 413 } 414 415 out: 416 mutex_unlock(&dev->kvm->arch.config_lock); 417 kvm_unlock_all_vcpus(dev->kvm); 418 mutex_unlock(&dev->kvm->lock); 419 420 if (!ret && !is_write) 421 ret = put_user(val, uaddr); 422 423 return ret; 424 } 425 426 static int vgic_v2_set_attr(struct kvm_device *dev, 427 struct kvm_device_attr *attr) 428 { 429 switch (attr->group) { 430 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS: 431 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: 432 return vgic_v2_attr_regs_access(dev, attr, true); 433 default: 434 return vgic_set_common_attr(dev, attr); 435 } 436 } 437 438 static int vgic_v2_get_attr(struct kvm_device *dev, 439 struct kvm_device_attr *attr) 440 { 441 switch (attr->group) { 442 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS: 443 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: 444 return vgic_v2_attr_regs_access(dev, attr, false); 445 default: 446 return vgic_get_common_attr(dev, attr); 447 } 448 } 449 450 static int vgic_v2_has_attr(struct kvm_device *dev, 451 struct kvm_device_attr *attr) 452 { 453 switch (attr->group) { 454 case KVM_DEV_ARM_VGIC_GRP_ADDR: 455 switch (attr->attr) { 456 case KVM_VGIC_V2_ADDR_TYPE_DIST: 457 case KVM_VGIC_V2_ADDR_TYPE_CPU: 458 return 0; 459 } 460 break; 461 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS: 462 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: 463 return vgic_v2_has_attr_regs(dev, attr); 464 case KVM_DEV_ARM_VGIC_GRP_NR_IRQS: 465 return 0; 466 case KVM_DEV_ARM_VGIC_GRP_CTRL: 467 switch (attr->attr) { 468 case KVM_DEV_ARM_VGIC_CTRL_INIT: 469 return 0; 470 } 471 } 472 return -ENXIO; 473 } 474 475 struct kvm_device_ops kvm_arm_vgic_v2_ops = { 476 .name = "kvm-arm-vgic-v2", 477 .create = vgic_create, 478 .destroy = vgic_destroy, 479 .set_attr = vgic_v2_set_attr, 480 .get_attr = vgic_v2_get_attr, 481 .has_attr = vgic_v2_has_attr, 482 }; 483 484 int vgic_v3_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr, 485 struct vgic_reg_attr *reg_attr) 486 { 487 unsigned long vgic_mpidr, mpidr_reg; 488 489 /* 490 * For KVM_DEV_ARM_VGIC_GRP_DIST_REGS group, 491 * attr might not hold MPIDR. Hence assume vcpu0. 492 */ 493 if (attr->group != KVM_DEV_ARM_VGIC_GRP_DIST_REGS) { 494 vgic_mpidr = (attr->attr & KVM_DEV_ARM_VGIC_V3_MPIDR_MASK) >> 495 KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT; 496 497 mpidr_reg = VGIC_TO_MPIDR(vgic_mpidr); 498 reg_attr->vcpu = kvm_mpidr_to_vcpu(dev->kvm, mpidr_reg); 499 } else { 500 reg_attr->vcpu = kvm_get_vcpu(dev->kvm, 0); 501 } 502 503 if (!reg_attr->vcpu) 504 return -EINVAL; 505 506 reg_attr->addr = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK; 507 508 return 0; 509 } 510 511 /* 512 * Allow access to certain ID-like registers prior to VGIC initialization, 513 * thereby allowing the VMM to provision the features / sizing of the VGIC. 514 */ 515 static bool reg_allowed_pre_init(struct kvm_device_attr *attr) 516 { 517 if (attr->group != KVM_DEV_ARM_VGIC_GRP_DIST_REGS) 518 return false; 519 520 switch (attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK) { 521 case GICD_IIDR: 522 case GICD_TYPER2: 523 return true; 524 default: 525 return false; 526 } 527 } 528 529 /* 530 * vgic_v3_attr_regs_access - allows user space to access VGIC v3 state 531 * 532 * @dev: kvm device handle 533 * @attr: kvm device attribute 534 * @is_write: true if userspace is writing a register 535 */ 536 static int vgic_v3_attr_regs_access(struct kvm_device *dev, 537 struct kvm_device_attr *attr, 538 bool is_write) 539 { 540 struct vgic_reg_attr reg_attr; 541 gpa_t addr; 542 struct kvm_vcpu *vcpu; 543 bool uaccess; 544 u32 val; 545 int ret; 546 547 ret = vgic_v3_parse_attr(dev, attr, ®_attr); 548 if (ret) 549 return ret; 550 551 vcpu = reg_attr.vcpu; 552 addr = reg_attr.addr; 553 554 switch (attr->group) { 555 case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS: 556 /* Sysregs uaccess is performed by the sysreg handling code */ 557 uaccess = false; 558 break; 559 default: 560 uaccess = true; 561 } 562 563 if (uaccess && is_write) { 564 u32 __user *uaddr = (u32 __user *)(unsigned long)attr->addr; 565 if (get_user(val, uaddr)) 566 return -EFAULT; 567 } 568 569 mutex_lock(&dev->kvm->lock); 570 571 if (kvm_trylock_all_vcpus(dev->kvm)) { 572 mutex_unlock(&dev->kvm->lock); 573 return -EBUSY; 574 } 575 576 mutex_lock(&dev->kvm->arch.config_lock); 577 578 if (!(vgic_initialized(dev->kvm) || reg_allowed_pre_init(attr))) { 579 ret = -EBUSY; 580 goto out; 581 } 582 583 switch (attr->group) { 584 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS: 585 ret = vgic_v3_dist_uaccess(vcpu, is_write, addr, &val); 586 break; 587 case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS: 588 ret = vgic_v3_redist_uaccess(vcpu, is_write, addr, &val); 589 break; 590 case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS: 591 ret = vgic_v3_cpu_sysregs_uaccess(vcpu, attr, is_write); 592 break; 593 case KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO: { 594 unsigned int info, intid; 595 596 info = (attr->attr & KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK) >> 597 KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT; 598 if (info == VGIC_LEVEL_INFO_LINE_LEVEL) { 599 intid = attr->attr & 600 KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK; 601 ret = vgic_v3_line_level_info_uaccess(vcpu, is_write, 602 intid, &val); 603 } else { 604 ret = -EINVAL; 605 } 606 break; 607 } 608 default: 609 ret = -EINVAL; 610 break; 611 } 612 613 out: 614 mutex_unlock(&dev->kvm->arch.config_lock); 615 kvm_unlock_all_vcpus(dev->kvm); 616 mutex_unlock(&dev->kvm->lock); 617 618 if (!ret && uaccess && !is_write) { 619 u32 __user *uaddr = (u32 __user *)(unsigned long)attr->addr; 620 ret = put_user(val, uaddr); 621 } 622 623 return ret; 624 } 625 626 static int vgic_v3_set_attr(struct kvm_device *dev, 627 struct kvm_device_attr *attr) 628 { 629 switch (attr->group) { 630 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS: 631 case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS: 632 case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS: 633 case KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO: 634 return vgic_v3_attr_regs_access(dev, attr, true); 635 case KVM_DEV_ARM_VGIC_GRP_MAINT_IRQ: { 636 u32 __user *uaddr = (u32 __user *)attr->addr; 637 u32 val; 638 639 if (get_user(val, uaddr)) 640 return -EFAULT; 641 642 guard(mutex)(&dev->kvm->arch.config_lock); 643 if (vgic_initialized(dev->kvm)) 644 return -EBUSY; 645 646 if (!irq_is_ppi(dev->kvm, val)) 647 return -EINVAL; 648 649 dev->kvm->arch.vgic.mi_intid = val; 650 return 0; 651 } 652 default: 653 return vgic_set_common_attr(dev, attr); 654 } 655 } 656 657 static int vgic_v3_get_attr(struct kvm_device *dev, 658 struct kvm_device_attr *attr) 659 { 660 switch (attr->group) { 661 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS: 662 case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS: 663 case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS: 664 case KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO: 665 return vgic_v3_attr_regs_access(dev, attr, false); 666 case KVM_DEV_ARM_VGIC_GRP_MAINT_IRQ: { 667 u32 __user *uaddr = (u32 __user *)(long)attr->addr; 668 669 guard(mutex)(&dev->kvm->arch.config_lock); 670 return put_user(dev->kvm->arch.vgic.mi_intid, uaddr); 671 } 672 default: 673 return vgic_get_common_attr(dev, attr); 674 } 675 } 676 677 static int vgic_v3_has_attr(struct kvm_device *dev, 678 struct kvm_device_attr *attr) 679 { 680 switch (attr->group) { 681 case KVM_DEV_ARM_VGIC_GRP_ADDR: 682 switch (attr->attr) { 683 case KVM_VGIC_V3_ADDR_TYPE_DIST: 684 case KVM_VGIC_V3_ADDR_TYPE_REDIST: 685 case KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION: 686 return 0; 687 } 688 break; 689 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS: 690 case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS: 691 case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS: 692 return vgic_v3_has_attr_regs(dev, attr); 693 case KVM_DEV_ARM_VGIC_GRP_NR_IRQS: 694 case KVM_DEV_ARM_VGIC_GRP_MAINT_IRQ: 695 return 0; 696 case KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO: { 697 if (((attr->attr & KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK) >> 698 KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT) == 699 VGIC_LEVEL_INFO_LINE_LEVEL) 700 return 0; 701 break; 702 } 703 case KVM_DEV_ARM_VGIC_GRP_CTRL: 704 switch (attr->attr) { 705 case KVM_DEV_ARM_VGIC_CTRL_INIT: 706 return 0; 707 case KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES: 708 return 0; 709 } 710 } 711 return -ENXIO; 712 } 713 714 struct kvm_device_ops kvm_arm_vgic_v3_ops = { 715 .name = "kvm-arm-vgic-v3", 716 .create = vgic_create, 717 .destroy = vgic_destroy, 718 .set_attr = vgic_v3_set_attr, 719 .get_attr = vgic_v3_get_attr, 720 .has_attr = vgic_v3_has_attr, 721 }; 722 723 static int vgic_v5_get_userspace_ppis(struct kvm_device *dev, 724 struct kvm_device_attr *attr) 725 { 726 struct vgic_v5_vm *gicv5_vm = &dev->kvm->arch.vgic.gicv5_vm; 727 u64 __user *uaddr = (u64 __user *)(long)attr->addr; 728 int ret; 729 730 guard(mutex)(&dev->kvm->arch.config_lock); 731 732 /* 733 * We either support 64 or 128 PPIs. In the former case, we need to 734 * return 0s for the second 64 bits as we have no storage backing those. 735 */ 736 ret = put_user(bitmap_read(gicv5_vm->userspace_ppis, 0, 64), uaddr); 737 if (ret) 738 return ret; 739 uaddr++; 740 741 if (VGIC_V5_NR_PRIVATE_IRQS == 128) 742 ret = put_user(bitmap_read(gicv5_vm->userspace_ppis, 64, 128), uaddr); 743 else 744 ret = put_user(0, uaddr); 745 746 return ret; 747 } 748 749 static int vgic_v5_set_attr(struct kvm_device *dev, 750 struct kvm_device_attr *attr) 751 { 752 switch (attr->group) { 753 case KVM_DEV_ARM_VGIC_GRP_ADDR: 754 case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS: 755 case KVM_DEV_ARM_VGIC_GRP_NR_IRQS: 756 return -ENXIO; 757 case KVM_DEV_ARM_VGIC_GRP_CTRL: 758 switch (attr->attr) { 759 case KVM_DEV_ARM_VGIC_CTRL_INIT: 760 return vgic_set_common_attr(dev, attr); 761 case KVM_DEV_ARM_VGIC_USERSPACE_PPIS: 762 default: 763 return -ENXIO; 764 } 765 default: 766 return -ENXIO; 767 } 768 769 } 770 771 static int vgic_v5_get_attr(struct kvm_device *dev, 772 struct kvm_device_attr *attr) 773 { 774 switch (attr->group) { 775 case KVM_DEV_ARM_VGIC_GRP_ADDR: 776 case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS: 777 case KVM_DEV_ARM_VGIC_GRP_NR_IRQS: 778 return -ENXIO; 779 case KVM_DEV_ARM_VGIC_GRP_CTRL: 780 switch (attr->attr) { 781 case KVM_DEV_ARM_VGIC_CTRL_INIT: 782 return vgic_get_common_attr(dev, attr); 783 case KVM_DEV_ARM_VGIC_USERSPACE_PPIS: 784 return vgic_v5_get_userspace_ppis(dev, attr); 785 default: 786 return -ENXIO; 787 } 788 default: 789 return -ENXIO; 790 } 791 } 792 793 static int vgic_v5_has_attr(struct kvm_device *dev, 794 struct kvm_device_attr *attr) 795 { 796 switch (attr->group) { 797 case KVM_DEV_ARM_VGIC_GRP_ADDR: 798 case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS: 799 case KVM_DEV_ARM_VGIC_GRP_NR_IRQS: 800 return -ENXIO; 801 case KVM_DEV_ARM_VGIC_GRP_CTRL: 802 switch (attr->attr) { 803 case KVM_DEV_ARM_VGIC_CTRL_INIT: 804 return 0; 805 case KVM_DEV_ARM_VGIC_USERSPACE_PPIS: 806 return 0; 807 default: 808 return -ENXIO; 809 } 810 default: 811 return -ENXIO; 812 } 813 } 814 815 struct kvm_device_ops kvm_arm_vgic_v5_ops = { 816 .name = "kvm-arm-vgic-v5", 817 .create = vgic_create, 818 .destroy = vgic_destroy, 819 .set_attr = vgic_v5_set_attr, 820 .get_attr = vgic_v5_get_attr, 821 .has_attr = vgic_v5_has_attr, 822 }; 823