1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/kvm/coproc.c: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Authors: Rusty Russell <rusty@rustcorp.com.au> 9 * Christoffer Dall <c.dall@virtualopensystems.com> 10 */ 11 12 #include <linux/bsearch.h> 13 #include <linux/kvm_host.h> 14 #include <linux/mm.h> 15 #include <linux/printk.h> 16 #include <linux/uaccess.h> 17 18 #include <asm/cacheflush.h> 19 #include <asm/cputype.h> 20 #include <asm/debug-monitors.h> 21 #include <asm/esr.h> 22 #include <asm/kvm_arm.h> 23 #include <asm/kvm_coproc.h> 24 #include <asm/kvm_emulate.h> 25 #include <asm/kvm_hyp.h> 26 #include <asm/kvm_mmu.h> 27 #include <asm/perf_event.h> 28 #include <asm/sysreg.h> 29 30 #include <trace/events/kvm.h> 31 32 #include "sys_regs.h" 33 34 #include "trace.h" 35 36 /* 37 * All of this file is extremely similar to the ARM coproc.c, but the 38 * types are different. My gut feeling is that it should be pretty 39 * easy to merge, but that would be an ABI breakage -- again. VFP 40 * would also need to be abstracted. 41 * 42 * For AArch32, we only take care of what is being trapped. Anything 43 * that has to do with init and userspace access has to go via the 44 * 64bit interface. 45 */ 46 47 static bool read_from_write_only(struct kvm_vcpu *vcpu, 48 struct sys_reg_params *params, 49 const struct sys_reg_desc *r) 50 { 51 WARN_ONCE(1, "Unexpected sys_reg read to write-only register\n"); 52 print_sys_reg_instr(params); 53 kvm_inject_undefined(vcpu); 54 return false; 55 } 56 57 static bool write_to_read_only(struct kvm_vcpu *vcpu, 58 struct sys_reg_params *params, 59 const struct sys_reg_desc *r) 60 { 61 WARN_ONCE(1, "Unexpected sys_reg write to read-only register\n"); 62 print_sys_reg_instr(params); 63 kvm_inject_undefined(vcpu); 64 return false; 65 } 66 67 static bool __vcpu_read_sys_reg_from_cpu(int reg, u64 *val) 68 { 69 /* 70 * System registers listed in the switch are not saved on every 71 * exit from the guest but are only saved on vcpu_put. 72 * 73 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but 74 * should never be listed below, because the guest cannot modify its 75 * own MPIDR_EL1 and MPIDR_EL1 is accessed for VCPU A from VCPU B's 76 * thread when emulating cross-VCPU communication. 77 */ 78 switch (reg) { 79 case CSSELR_EL1: *val = read_sysreg_s(SYS_CSSELR_EL1); break; 80 case SCTLR_EL1: *val = read_sysreg_s(SYS_SCTLR_EL12); break; 81 case CPACR_EL1: *val = read_sysreg_s(SYS_CPACR_EL12); break; 82 case TTBR0_EL1: *val = read_sysreg_s(SYS_TTBR0_EL12); break; 83 case TTBR1_EL1: *val = read_sysreg_s(SYS_TTBR1_EL12); break; 84 case TCR_EL1: *val = read_sysreg_s(SYS_TCR_EL12); break; 85 case ESR_EL1: *val = read_sysreg_s(SYS_ESR_EL12); break; 86 case AFSR0_EL1: *val = read_sysreg_s(SYS_AFSR0_EL12); break; 87 case AFSR1_EL1: *val = read_sysreg_s(SYS_AFSR1_EL12); break; 88 case FAR_EL1: *val = read_sysreg_s(SYS_FAR_EL12); break; 89 case MAIR_EL1: *val = read_sysreg_s(SYS_MAIR_EL12); break; 90 case VBAR_EL1: *val = read_sysreg_s(SYS_VBAR_EL12); break; 91 case CONTEXTIDR_EL1: *val = read_sysreg_s(SYS_CONTEXTIDR_EL12);break; 92 case TPIDR_EL0: *val = read_sysreg_s(SYS_TPIDR_EL0); break; 93 case TPIDRRO_EL0: *val = read_sysreg_s(SYS_TPIDRRO_EL0); break; 94 case TPIDR_EL1: *val = read_sysreg_s(SYS_TPIDR_EL1); break; 95 case AMAIR_EL1: *val = read_sysreg_s(SYS_AMAIR_EL12); break; 96 case CNTKCTL_EL1: *val = read_sysreg_s(SYS_CNTKCTL_EL12); break; 97 case ELR_EL1: *val = read_sysreg_s(SYS_ELR_EL12); break; 98 case PAR_EL1: *val = read_sysreg_par(); break; 99 case DACR32_EL2: *val = read_sysreg_s(SYS_DACR32_EL2); break; 100 case IFSR32_EL2: *val = read_sysreg_s(SYS_IFSR32_EL2); break; 101 case DBGVCR32_EL2: *val = read_sysreg_s(SYS_DBGVCR32_EL2); break; 102 default: return false; 103 } 104 105 return true; 106 } 107 108 static bool __vcpu_write_sys_reg_to_cpu(u64 val, int reg) 109 { 110 /* 111 * System registers listed in the switch are not restored on every 112 * entry to the guest but are only restored on vcpu_load. 113 * 114 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but 115 * should never be listed below, because the MPIDR should only be set 116 * once, before running the VCPU, and never changed later. 117 */ 118 switch (reg) { 119 case CSSELR_EL1: write_sysreg_s(val, SYS_CSSELR_EL1); break; 120 case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); break; 121 case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); break; 122 case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); break; 123 case TTBR1_EL1: write_sysreg_s(val, SYS_TTBR1_EL12); break; 124 case TCR_EL1: write_sysreg_s(val, SYS_TCR_EL12); break; 125 case ESR_EL1: write_sysreg_s(val, SYS_ESR_EL12); break; 126 case AFSR0_EL1: write_sysreg_s(val, SYS_AFSR0_EL12); break; 127 case AFSR1_EL1: write_sysreg_s(val, SYS_AFSR1_EL12); break; 128 case FAR_EL1: write_sysreg_s(val, SYS_FAR_EL12); break; 129 case MAIR_EL1: write_sysreg_s(val, SYS_MAIR_EL12); break; 130 case VBAR_EL1: write_sysreg_s(val, SYS_VBAR_EL12); break; 131 case CONTEXTIDR_EL1: write_sysreg_s(val, SYS_CONTEXTIDR_EL12);break; 132 case TPIDR_EL0: write_sysreg_s(val, SYS_TPIDR_EL0); break; 133 case TPIDRRO_EL0: write_sysreg_s(val, SYS_TPIDRRO_EL0); break; 134 case TPIDR_EL1: write_sysreg_s(val, SYS_TPIDR_EL1); break; 135 case AMAIR_EL1: write_sysreg_s(val, SYS_AMAIR_EL12); break; 136 case CNTKCTL_EL1: write_sysreg_s(val, SYS_CNTKCTL_EL12); break; 137 case ELR_EL1: write_sysreg_s(val, SYS_ELR_EL12); break; 138 case PAR_EL1: write_sysreg_s(val, SYS_PAR_EL1); break; 139 case DACR32_EL2: write_sysreg_s(val, SYS_DACR32_EL2); break; 140 case IFSR32_EL2: write_sysreg_s(val, SYS_IFSR32_EL2); break; 141 case DBGVCR32_EL2: write_sysreg_s(val, SYS_DBGVCR32_EL2); break; 142 default: return false; 143 } 144 145 return true; 146 } 147 148 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg) 149 { 150 u64 val = 0x8badf00d8badf00d; 151 152 if (vcpu->arch.sysregs_loaded_on_cpu && 153 __vcpu_read_sys_reg_from_cpu(reg, &val)) 154 return val; 155 156 return __vcpu_sys_reg(vcpu, reg); 157 } 158 159 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg) 160 { 161 if (vcpu->arch.sysregs_loaded_on_cpu && 162 __vcpu_write_sys_reg_to_cpu(val, reg)) 163 return; 164 165 __vcpu_sys_reg(vcpu, reg) = val; 166 } 167 168 /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */ 169 static u32 cache_levels; 170 171 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */ 172 #define CSSELR_MAX 12 173 174 /* Which cache CCSIDR represents depends on CSSELR value. */ 175 static u32 get_ccsidr(u32 csselr) 176 { 177 u32 ccsidr; 178 179 /* Make sure noone else changes CSSELR during this! */ 180 local_irq_disable(); 181 write_sysreg(csselr, csselr_el1); 182 isb(); 183 ccsidr = read_sysreg(ccsidr_el1); 184 local_irq_enable(); 185 186 return ccsidr; 187 } 188 189 /* 190 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized). 191 */ 192 static bool access_dcsw(struct kvm_vcpu *vcpu, 193 struct sys_reg_params *p, 194 const struct sys_reg_desc *r) 195 { 196 if (!p->is_write) 197 return read_from_write_only(vcpu, p, r); 198 199 /* 200 * Only track S/W ops if we don't have FWB. It still indicates 201 * that the guest is a bit broken (S/W operations should only 202 * be done by firmware, knowing that there is only a single 203 * CPU left in the system, and certainly not from non-secure 204 * software). 205 */ 206 if (!cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) 207 kvm_set_way_flush(vcpu); 208 209 return true; 210 } 211 212 /* 213 * Generic accessor for VM registers. Only called as long as HCR_TVM 214 * is set. If the guest enables the MMU, we stop trapping the VM 215 * sys_regs and leave it in complete control of the caches. 216 */ 217 static bool access_vm_reg(struct kvm_vcpu *vcpu, 218 struct sys_reg_params *p, 219 const struct sys_reg_desc *r) 220 { 221 bool was_enabled = vcpu_has_cache_enabled(vcpu); 222 u64 val; 223 int reg = r->reg; 224 225 BUG_ON(!p->is_write); 226 227 /* See the 32bit mapping in kvm_host.h */ 228 if (p->is_aarch32) 229 reg = r->reg / 2; 230 231 if (!p->is_aarch32 || !p->is_32bit) { 232 val = p->regval; 233 } else { 234 val = vcpu_read_sys_reg(vcpu, reg); 235 if (r->reg % 2) 236 val = (p->regval << 32) | (u64)lower_32_bits(val); 237 else 238 val = ((u64)upper_32_bits(val) << 32) | 239 lower_32_bits(p->regval); 240 } 241 vcpu_write_sys_reg(vcpu, val, reg); 242 243 kvm_toggle_cache(vcpu, was_enabled); 244 return true; 245 } 246 247 static bool access_actlr(struct kvm_vcpu *vcpu, 248 struct sys_reg_params *p, 249 const struct sys_reg_desc *r) 250 { 251 if (p->is_write) 252 return ignore_write(vcpu, p); 253 254 p->regval = vcpu_read_sys_reg(vcpu, ACTLR_EL1); 255 256 if (p->is_aarch32) { 257 if (r->Op2 & 2) 258 p->regval = upper_32_bits(p->regval); 259 else 260 p->regval = lower_32_bits(p->regval); 261 } 262 263 return true; 264 } 265 266 /* 267 * Trap handler for the GICv3 SGI generation system register. 268 * Forward the request to the VGIC emulation. 269 * The cp15_64 code makes sure this automatically works 270 * for both AArch64 and AArch32 accesses. 271 */ 272 static bool access_gic_sgi(struct kvm_vcpu *vcpu, 273 struct sys_reg_params *p, 274 const struct sys_reg_desc *r) 275 { 276 bool g1; 277 278 if (!p->is_write) 279 return read_from_write_only(vcpu, p, r); 280 281 /* 282 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates 283 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group, 284 * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively 285 * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure 286 * group. 287 */ 288 if (p->is_aarch32) { 289 switch (p->Op1) { 290 default: /* Keep GCC quiet */ 291 case 0: /* ICC_SGI1R */ 292 g1 = true; 293 break; 294 case 1: /* ICC_ASGI1R */ 295 case 2: /* ICC_SGI0R */ 296 g1 = false; 297 break; 298 } 299 } else { 300 switch (p->Op2) { 301 default: /* Keep GCC quiet */ 302 case 5: /* ICC_SGI1R_EL1 */ 303 g1 = true; 304 break; 305 case 6: /* ICC_ASGI1R_EL1 */ 306 case 7: /* ICC_SGI0R_EL1 */ 307 g1 = false; 308 break; 309 } 310 } 311 312 vgic_v3_dispatch_sgi(vcpu, p->regval, g1); 313 314 return true; 315 } 316 317 static bool access_gic_sre(struct kvm_vcpu *vcpu, 318 struct sys_reg_params *p, 319 const struct sys_reg_desc *r) 320 { 321 if (p->is_write) 322 return ignore_write(vcpu, p); 323 324 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre; 325 return true; 326 } 327 328 static bool trap_raz_wi(struct kvm_vcpu *vcpu, 329 struct sys_reg_params *p, 330 const struct sys_reg_desc *r) 331 { 332 if (p->is_write) 333 return ignore_write(vcpu, p); 334 else 335 return read_zero(vcpu, p); 336 } 337 338 /* 339 * ARMv8.1 mandates at least a trivial LORegion implementation, where all the 340 * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0 341 * system, these registers should UNDEF. LORID_EL1 being a RO register, we 342 * treat it separately. 343 */ 344 static bool trap_loregion(struct kvm_vcpu *vcpu, 345 struct sys_reg_params *p, 346 const struct sys_reg_desc *r) 347 { 348 u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 349 u32 sr = sys_reg((u32)r->Op0, (u32)r->Op1, 350 (u32)r->CRn, (u32)r->CRm, (u32)r->Op2); 351 352 if (!(val & (0xfUL << ID_AA64MMFR1_LOR_SHIFT))) { 353 kvm_inject_undefined(vcpu); 354 return false; 355 } 356 357 if (p->is_write && sr == SYS_LORID_EL1) 358 return write_to_read_only(vcpu, p, r); 359 360 return trap_raz_wi(vcpu, p, r); 361 } 362 363 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu, 364 struct sys_reg_params *p, 365 const struct sys_reg_desc *r) 366 { 367 if (p->is_write) { 368 return ignore_write(vcpu, p); 369 } else { 370 p->regval = (1 << 3); 371 return true; 372 } 373 } 374 375 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu, 376 struct sys_reg_params *p, 377 const struct sys_reg_desc *r) 378 { 379 if (p->is_write) { 380 return ignore_write(vcpu, p); 381 } else { 382 p->regval = read_sysreg(dbgauthstatus_el1); 383 return true; 384 } 385 } 386 387 /* 388 * We want to avoid world-switching all the DBG registers all the 389 * time: 390 * 391 * - If we've touched any debug register, it is likely that we're 392 * going to touch more of them. It then makes sense to disable the 393 * traps and start doing the save/restore dance 394 * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is 395 * then mandatory to save/restore the registers, as the guest 396 * depends on them. 397 * 398 * For this, we use a DIRTY bit, indicating the guest has modified the 399 * debug registers, used as follow: 400 * 401 * On guest entry: 402 * - If the dirty bit is set (because we're coming back from trapping), 403 * disable the traps, save host registers, restore guest registers. 404 * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), 405 * set the dirty bit, disable the traps, save host registers, 406 * restore guest registers. 407 * - Otherwise, enable the traps 408 * 409 * On guest exit: 410 * - If the dirty bit is set, save guest registers, restore host 411 * registers and clear the dirty bit. This ensure that the host can 412 * now use the debug registers. 413 */ 414 static bool trap_debug_regs(struct kvm_vcpu *vcpu, 415 struct sys_reg_params *p, 416 const struct sys_reg_desc *r) 417 { 418 if (p->is_write) { 419 vcpu_write_sys_reg(vcpu, p->regval, r->reg); 420 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY; 421 } else { 422 p->regval = vcpu_read_sys_reg(vcpu, r->reg); 423 } 424 425 trace_trap_reg(__func__, r->reg, p->is_write, p->regval); 426 427 return true; 428 } 429 430 /* 431 * reg_to_dbg/dbg_to_reg 432 * 433 * A 32 bit write to a debug register leave top bits alone 434 * A 32 bit read from a debug register only returns the bottom bits 435 * 436 * All writes will set the KVM_ARM64_DEBUG_DIRTY flag to ensure the 437 * hyp.S code switches between host and guest values in future. 438 */ 439 static void reg_to_dbg(struct kvm_vcpu *vcpu, 440 struct sys_reg_params *p, 441 u64 *dbg_reg) 442 { 443 u64 val = p->regval; 444 445 if (p->is_32bit) { 446 val &= 0xffffffffUL; 447 val |= ((*dbg_reg >> 32) << 32); 448 } 449 450 *dbg_reg = val; 451 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY; 452 } 453 454 static void dbg_to_reg(struct kvm_vcpu *vcpu, 455 struct sys_reg_params *p, 456 u64 *dbg_reg) 457 { 458 p->regval = *dbg_reg; 459 if (p->is_32bit) 460 p->regval &= 0xffffffffUL; 461 } 462 463 static bool trap_bvr(struct kvm_vcpu *vcpu, 464 struct sys_reg_params *p, 465 const struct sys_reg_desc *rd) 466 { 467 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg]; 468 469 if (p->is_write) 470 reg_to_dbg(vcpu, p, dbg_reg); 471 else 472 dbg_to_reg(vcpu, p, dbg_reg); 473 474 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg); 475 476 return true; 477 } 478 479 static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 480 const struct kvm_one_reg *reg, void __user *uaddr) 481 { 482 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg]; 483 484 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) 485 return -EFAULT; 486 return 0; 487 } 488 489 static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 490 const struct kvm_one_reg *reg, void __user *uaddr) 491 { 492 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg]; 493 494 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) 495 return -EFAULT; 496 return 0; 497 } 498 499 static void reset_bvr(struct kvm_vcpu *vcpu, 500 const struct sys_reg_desc *rd) 501 { 502 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg] = rd->val; 503 } 504 505 static bool trap_bcr(struct kvm_vcpu *vcpu, 506 struct sys_reg_params *p, 507 const struct sys_reg_desc *rd) 508 { 509 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg]; 510 511 if (p->is_write) 512 reg_to_dbg(vcpu, p, dbg_reg); 513 else 514 dbg_to_reg(vcpu, p, dbg_reg); 515 516 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg); 517 518 return true; 519 } 520 521 static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 522 const struct kvm_one_reg *reg, void __user *uaddr) 523 { 524 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg]; 525 526 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) 527 return -EFAULT; 528 529 return 0; 530 } 531 532 static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 533 const struct kvm_one_reg *reg, void __user *uaddr) 534 { 535 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg]; 536 537 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) 538 return -EFAULT; 539 return 0; 540 } 541 542 static void reset_bcr(struct kvm_vcpu *vcpu, 543 const struct sys_reg_desc *rd) 544 { 545 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg] = rd->val; 546 } 547 548 static bool trap_wvr(struct kvm_vcpu *vcpu, 549 struct sys_reg_params *p, 550 const struct sys_reg_desc *rd) 551 { 552 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]; 553 554 if (p->is_write) 555 reg_to_dbg(vcpu, p, dbg_reg); 556 else 557 dbg_to_reg(vcpu, p, dbg_reg); 558 559 trace_trap_reg(__func__, rd->reg, p->is_write, 560 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]); 561 562 return true; 563 } 564 565 static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 566 const struct kvm_one_reg *reg, void __user *uaddr) 567 { 568 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]; 569 570 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) 571 return -EFAULT; 572 return 0; 573 } 574 575 static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 576 const struct kvm_one_reg *reg, void __user *uaddr) 577 { 578 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]; 579 580 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) 581 return -EFAULT; 582 return 0; 583 } 584 585 static void reset_wvr(struct kvm_vcpu *vcpu, 586 const struct sys_reg_desc *rd) 587 { 588 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg] = rd->val; 589 } 590 591 static bool trap_wcr(struct kvm_vcpu *vcpu, 592 struct sys_reg_params *p, 593 const struct sys_reg_desc *rd) 594 { 595 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg]; 596 597 if (p->is_write) 598 reg_to_dbg(vcpu, p, dbg_reg); 599 else 600 dbg_to_reg(vcpu, p, dbg_reg); 601 602 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg); 603 604 return true; 605 } 606 607 static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 608 const struct kvm_one_reg *reg, void __user *uaddr) 609 { 610 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg]; 611 612 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) 613 return -EFAULT; 614 return 0; 615 } 616 617 static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 618 const struct kvm_one_reg *reg, void __user *uaddr) 619 { 620 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg]; 621 622 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) 623 return -EFAULT; 624 return 0; 625 } 626 627 static void reset_wcr(struct kvm_vcpu *vcpu, 628 const struct sys_reg_desc *rd) 629 { 630 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg] = rd->val; 631 } 632 633 static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 634 { 635 u64 amair = read_sysreg(amair_el1); 636 vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1); 637 } 638 639 static void reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 640 { 641 u64 actlr = read_sysreg(actlr_el1); 642 vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1); 643 } 644 645 static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 646 { 647 u64 mpidr; 648 649 /* 650 * Map the vcpu_id into the first three affinity level fields of 651 * the MPIDR. We limit the number of VCPUs in level 0 due to a 652 * limitation to 16 CPUs in that level in the ICC_SGIxR registers 653 * of the GICv3 to be able to address each CPU directly when 654 * sending IPIs. 655 */ 656 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0); 657 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1); 658 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2); 659 vcpu_write_sys_reg(vcpu, (1ULL << 31) | mpidr, MPIDR_EL1); 660 } 661 662 static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 663 { 664 u64 pmcr, val; 665 666 pmcr = read_sysreg(pmcr_el0); 667 /* 668 * Writable bits of PMCR_EL0 (ARMV8_PMU_PMCR_MASK) are reset to UNKNOWN 669 * except PMCR.E resetting to zero. 670 */ 671 val = ((pmcr & ~ARMV8_PMU_PMCR_MASK) 672 | (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E); 673 if (!system_supports_32bit_el0()) 674 val |= ARMV8_PMU_PMCR_LC; 675 __vcpu_sys_reg(vcpu, r->reg) = val; 676 } 677 678 static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags) 679 { 680 u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0); 681 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu); 682 683 if (!enabled) 684 kvm_inject_undefined(vcpu); 685 686 return !enabled; 687 } 688 689 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu) 690 { 691 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN); 692 } 693 694 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu) 695 { 696 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN); 697 } 698 699 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu) 700 { 701 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN); 702 } 703 704 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu) 705 { 706 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN); 707 } 708 709 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 710 const struct sys_reg_desc *r) 711 { 712 u64 val; 713 714 if (!kvm_arm_pmu_v3_ready(vcpu)) 715 return trap_raz_wi(vcpu, p, r); 716 717 if (pmu_access_el0_disabled(vcpu)) 718 return false; 719 720 if (p->is_write) { 721 /* Only update writeable bits of PMCR */ 722 val = __vcpu_sys_reg(vcpu, PMCR_EL0); 723 val &= ~ARMV8_PMU_PMCR_MASK; 724 val |= p->regval & ARMV8_PMU_PMCR_MASK; 725 if (!system_supports_32bit_el0()) 726 val |= ARMV8_PMU_PMCR_LC; 727 __vcpu_sys_reg(vcpu, PMCR_EL0) = val; 728 kvm_pmu_handle_pmcr(vcpu, val); 729 kvm_vcpu_pmu_restore_guest(vcpu); 730 } else { 731 /* PMCR.P & PMCR.C are RAZ */ 732 val = __vcpu_sys_reg(vcpu, PMCR_EL0) 733 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C); 734 p->regval = val; 735 } 736 737 return true; 738 } 739 740 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 741 const struct sys_reg_desc *r) 742 { 743 if (!kvm_arm_pmu_v3_ready(vcpu)) 744 return trap_raz_wi(vcpu, p, r); 745 746 if (pmu_access_event_counter_el0_disabled(vcpu)) 747 return false; 748 749 if (p->is_write) 750 __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval; 751 else 752 /* return PMSELR.SEL field */ 753 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0) 754 & ARMV8_PMU_COUNTER_MASK; 755 756 return true; 757 } 758 759 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 760 const struct sys_reg_desc *r) 761 { 762 u64 pmceid; 763 764 if (!kvm_arm_pmu_v3_ready(vcpu)) 765 return trap_raz_wi(vcpu, p, r); 766 767 BUG_ON(p->is_write); 768 769 if (pmu_access_el0_disabled(vcpu)) 770 return false; 771 772 pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1)); 773 774 p->regval = pmceid; 775 776 return true; 777 } 778 779 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx) 780 { 781 u64 pmcr, val; 782 783 pmcr = __vcpu_sys_reg(vcpu, PMCR_EL0); 784 val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK; 785 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) { 786 kvm_inject_undefined(vcpu); 787 return false; 788 } 789 790 return true; 791 } 792 793 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu, 794 struct sys_reg_params *p, 795 const struct sys_reg_desc *r) 796 { 797 u64 idx; 798 799 if (!kvm_arm_pmu_v3_ready(vcpu)) 800 return trap_raz_wi(vcpu, p, r); 801 802 if (r->CRn == 9 && r->CRm == 13) { 803 if (r->Op2 == 2) { 804 /* PMXEVCNTR_EL0 */ 805 if (pmu_access_event_counter_el0_disabled(vcpu)) 806 return false; 807 808 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) 809 & ARMV8_PMU_COUNTER_MASK; 810 } else if (r->Op2 == 0) { 811 /* PMCCNTR_EL0 */ 812 if (pmu_access_cycle_counter_el0_disabled(vcpu)) 813 return false; 814 815 idx = ARMV8_PMU_CYCLE_IDX; 816 } else { 817 return false; 818 } 819 } else if (r->CRn == 0 && r->CRm == 9) { 820 /* PMCCNTR */ 821 if (pmu_access_event_counter_el0_disabled(vcpu)) 822 return false; 823 824 idx = ARMV8_PMU_CYCLE_IDX; 825 } else if (r->CRn == 14 && (r->CRm & 12) == 8) { 826 /* PMEVCNTRn_EL0 */ 827 if (pmu_access_event_counter_el0_disabled(vcpu)) 828 return false; 829 830 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 831 } else { 832 return false; 833 } 834 835 if (!pmu_counter_idx_valid(vcpu, idx)) 836 return false; 837 838 if (p->is_write) { 839 if (pmu_access_el0_disabled(vcpu)) 840 return false; 841 842 kvm_pmu_set_counter_value(vcpu, idx, p->regval); 843 } else { 844 p->regval = kvm_pmu_get_counter_value(vcpu, idx); 845 } 846 847 return true; 848 } 849 850 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 851 const struct sys_reg_desc *r) 852 { 853 u64 idx, reg; 854 855 if (!kvm_arm_pmu_v3_ready(vcpu)) 856 return trap_raz_wi(vcpu, p, r); 857 858 if (pmu_access_el0_disabled(vcpu)) 859 return false; 860 861 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) { 862 /* PMXEVTYPER_EL0 */ 863 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK; 864 reg = PMEVTYPER0_EL0 + idx; 865 } else if (r->CRn == 14 && (r->CRm & 12) == 12) { 866 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 867 if (idx == ARMV8_PMU_CYCLE_IDX) 868 reg = PMCCFILTR_EL0; 869 else 870 /* PMEVTYPERn_EL0 */ 871 reg = PMEVTYPER0_EL0 + idx; 872 } else { 873 BUG(); 874 } 875 876 if (!pmu_counter_idx_valid(vcpu, idx)) 877 return false; 878 879 if (p->is_write) { 880 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx); 881 __vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK; 882 kvm_vcpu_pmu_restore_guest(vcpu); 883 } else { 884 p->regval = __vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK; 885 } 886 887 return true; 888 } 889 890 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 891 const struct sys_reg_desc *r) 892 { 893 u64 val, mask; 894 895 if (!kvm_arm_pmu_v3_ready(vcpu)) 896 return trap_raz_wi(vcpu, p, r); 897 898 if (pmu_access_el0_disabled(vcpu)) 899 return false; 900 901 mask = kvm_pmu_valid_counter_mask(vcpu); 902 if (p->is_write) { 903 val = p->regval & mask; 904 if (r->Op2 & 0x1) { 905 /* accessing PMCNTENSET_EL0 */ 906 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val; 907 kvm_pmu_enable_counter_mask(vcpu, val); 908 kvm_vcpu_pmu_restore_guest(vcpu); 909 } else { 910 /* accessing PMCNTENCLR_EL0 */ 911 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val; 912 kvm_pmu_disable_counter_mask(vcpu, val); 913 } 914 } else { 915 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask; 916 } 917 918 return true; 919 } 920 921 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 922 const struct sys_reg_desc *r) 923 { 924 u64 mask = kvm_pmu_valid_counter_mask(vcpu); 925 926 if (!kvm_arm_pmu_v3_ready(vcpu)) 927 return trap_raz_wi(vcpu, p, r); 928 929 if (!vcpu_mode_priv(vcpu)) { 930 kvm_inject_undefined(vcpu); 931 return false; 932 } 933 934 if (p->is_write) { 935 u64 val = p->regval & mask; 936 937 if (r->Op2 & 0x1) 938 /* accessing PMINTENSET_EL1 */ 939 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val; 940 else 941 /* accessing PMINTENCLR_EL1 */ 942 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val; 943 } else { 944 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1) & mask; 945 } 946 947 return true; 948 } 949 950 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 951 const struct sys_reg_desc *r) 952 { 953 u64 mask = kvm_pmu_valid_counter_mask(vcpu); 954 955 if (!kvm_arm_pmu_v3_ready(vcpu)) 956 return trap_raz_wi(vcpu, p, r); 957 958 if (pmu_access_el0_disabled(vcpu)) 959 return false; 960 961 if (p->is_write) { 962 if (r->CRm & 0x2) 963 /* accessing PMOVSSET_EL0 */ 964 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask); 965 else 966 /* accessing PMOVSCLR_EL0 */ 967 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask); 968 } else { 969 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0) & mask; 970 } 971 972 return true; 973 } 974 975 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 976 const struct sys_reg_desc *r) 977 { 978 u64 mask; 979 980 if (!kvm_arm_pmu_v3_ready(vcpu)) 981 return trap_raz_wi(vcpu, p, r); 982 983 if (!p->is_write) 984 return read_from_write_only(vcpu, p, r); 985 986 if (pmu_write_swinc_el0_disabled(vcpu)) 987 return false; 988 989 mask = kvm_pmu_valid_counter_mask(vcpu); 990 kvm_pmu_software_increment(vcpu, p->regval & mask); 991 return true; 992 } 993 994 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 995 const struct sys_reg_desc *r) 996 { 997 if (!kvm_arm_pmu_v3_ready(vcpu)) 998 return trap_raz_wi(vcpu, p, r); 999 1000 if (p->is_write) { 1001 if (!vcpu_mode_priv(vcpu)) { 1002 kvm_inject_undefined(vcpu); 1003 return false; 1004 } 1005 1006 __vcpu_sys_reg(vcpu, PMUSERENR_EL0) = 1007 p->regval & ARMV8_PMU_USERENR_MASK; 1008 } else { 1009 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0) 1010 & ARMV8_PMU_USERENR_MASK; 1011 } 1012 1013 return true; 1014 } 1015 1016 #define reg_to_encoding(x) \ 1017 sys_reg((u32)(x)->Op0, (u32)(x)->Op1, \ 1018 (u32)(x)->CRn, (u32)(x)->CRm, (u32)(x)->Op2); 1019 1020 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */ 1021 #define DBG_BCR_BVR_WCR_WVR_EL1(n) \ 1022 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \ 1023 trap_bvr, reset_bvr, 0, 0, get_bvr, set_bvr }, \ 1024 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \ 1025 trap_bcr, reset_bcr, 0, 0, get_bcr, set_bcr }, \ 1026 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \ 1027 trap_wvr, reset_wvr, 0, 0, get_wvr, set_wvr }, \ 1028 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \ 1029 trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr } 1030 1031 /* Macro to expand the PMEVCNTRn_EL0 register */ 1032 #define PMU_PMEVCNTR_EL0(n) \ 1033 { SYS_DESC(SYS_PMEVCNTRn_EL0(n)), \ 1034 access_pmu_evcntr, reset_unknown, (PMEVCNTR0_EL0 + n), } 1035 1036 /* Macro to expand the PMEVTYPERn_EL0 register */ 1037 #define PMU_PMEVTYPER_EL0(n) \ 1038 { SYS_DESC(SYS_PMEVTYPERn_EL0(n)), \ 1039 access_pmu_evtyper, reset_unknown, (PMEVTYPER0_EL0 + n), } 1040 1041 static bool access_amu(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1042 const struct sys_reg_desc *r) 1043 { 1044 kvm_inject_undefined(vcpu); 1045 1046 return false; 1047 } 1048 1049 /* Macro to expand the AMU counter and type registers*/ 1050 #define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), access_amu } 1051 #define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), access_amu } 1052 #define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), access_amu } 1053 #define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), access_amu } 1054 1055 static bool trap_ptrauth(struct kvm_vcpu *vcpu, 1056 struct sys_reg_params *p, 1057 const struct sys_reg_desc *rd) 1058 { 1059 /* 1060 * If we land here, that is because we didn't fixup the access on exit 1061 * by allowing the PtrAuth sysregs. The only way this happens is when 1062 * the guest does not have PtrAuth support enabled. 1063 */ 1064 kvm_inject_undefined(vcpu); 1065 1066 return false; 1067 } 1068 1069 static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu, 1070 const struct sys_reg_desc *rd) 1071 { 1072 return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN; 1073 } 1074 1075 #define __PTRAUTH_KEY(k) \ 1076 { SYS_DESC(SYS_## k), trap_ptrauth, reset_unknown, k, \ 1077 .visibility = ptrauth_visibility} 1078 1079 #define PTRAUTH_KEY(k) \ 1080 __PTRAUTH_KEY(k ## KEYLO_EL1), \ 1081 __PTRAUTH_KEY(k ## KEYHI_EL1) 1082 1083 static bool access_arch_timer(struct kvm_vcpu *vcpu, 1084 struct sys_reg_params *p, 1085 const struct sys_reg_desc *r) 1086 { 1087 enum kvm_arch_timers tmr; 1088 enum kvm_arch_timer_regs treg; 1089 u64 reg = reg_to_encoding(r); 1090 1091 switch (reg) { 1092 case SYS_CNTP_TVAL_EL0: 1093 case SYS_AARCH32_CNTP_TVAL: 1094 tmr = TIMER_PTIMER; 1095 treg = TIMER_REG_TVAL; 1096 break; 1097 case SYS_CNTP_CTL_EL0: 1098 case SYS_AARCH32_CNTP_CTL: 1099 tmr = TIMER_PTIMER; 1100 treg = TIMER_REG_CTL; 1101 break; 1102 case SYS_CNTP_CVAL_EL0: 1103 case SYS_AARCH32_CNTP_CVAL: 1104 tmr = TIMER_PTIMER; 1105 treg = TIMER_REG_CVAL; 1106 break; 1107 default: 1108 BUG(); 1109 } 1110 1111 if (p->is_write) 1112 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval); 1113 else 1114 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg); 1115 1116 return true; 1117 } 1118 1119 /* Read a sanitised cpufeature ID register by sys_reg_desc */ 1120 static u64 read_id_reg(const struct kvm_vcpu *vcpu, 1121 struct sys_reg_desc const *r, bool raz) 1122 { 1123 u32 id = sys_reg((u32)r->Op0, (u32)r->Op1, 1124 (u32)r->CRn, (u32)r->CRm, (u32)r->Op2); 1125 u64 val = raz ? 0 : read_sanitised_ftr_reg(id); 1126 1127 if (id == SYS_ID_AA64PFR0_EL1) { 1128 if (!vcpu_has_sve(vcpu)) 1129 val &= ~(0xfUL << ID_AA64PFR0_SVE_SHIFT); 1130 val &= ~(0xfUL << ID_AA64PFR0_AMU_SHIFT); 1131 if (!(val & (0xfUL << ID_AA64PFR0_CSV2_SHIFT)) && 1132 arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED) 1133 val |= (1UL << ID_AA64PFR0_CSV2_SHIFT); 1134 } else if (id == SYS_ID_AA64PFR1_EL1) { 1135 val &= ~(0xfUL << ID_AA64PFR1_MTE_SHIFT); 1136 } else if (id == SYS_ID_AA64ISAR1_EL1 && !vcpu_has_ptrauth(vcpu)) { 1137 val &= ~((0xfUL << ID_AA64ISAR1_APA_SHIFT) | 1138 (0xfUL << ID_AA64ISAR1_API_SHIFT) | 1139 (0xfUL << ID_AA64ISAR1_GPA_SHIFT) | 1140 (0xfUL << ID_AA64ISAR1_GPI_SHIFT)); 1141 } else if (id == SYS_ID_AA64DFR0_EL1) { 1142 /* Limit guests to PMUv3 for ARMv8.1 */ 1143 val = cpuid_feature_cap_perfmon_field(val, 1144 ID_AA64DFR0_PMUVER_SHIFT, 1145 ID_AA64DFR0_PMUVER_8_1); 1146 } else if (id == SYS_ID_DFR0_EL1) { 1147 /* Limit guests to PMUv3 for ARMv8.1 */ 1148 val = cpuid_feature_cap_perfmon_field(val, 1149 ID_DFR0_PERFMON_SHIFT, 1150 ID_DFR0_PERFMON_8_1); 1151 } 1152 1153 return val; 1154 } 1155 1156 static unsigned int id_visibility(const struct kvm_vcpu *vcpu, 1157 const struct sys_reg_desc *r) 1158 { 1159 u32 id = sys_reg((u32)r->Op0, (u32)r->Op1, 1160 (u32)r->CRn, (u32)r->CRm, (u32)r->Op2); 1161 1162 switch (id) { 1163 case SYS_ID_AA64ZFR0_EL1: 1164 if (!vcpu_has_sve(vcpu)) 1165 return REG_RAZ; 1166 break; 1167 } 1168 1169 return 0; 1170 } 1171 1172 /* cpufeature ID register access trap handlers */ 1173 1174 static bool __access_id_reg(struct kvm_vcpu *vcpu, 1175 struct sys_reg_params *p, 1176 const struct sys_reg_desc *r, 1177 bool raz) 1178 { 1179 if (p->is_write) 1180 return write_to_read_only(vcpu, p, r); 1181 1182 p->regval = read_id_reg(vcpu, r, raz); 1183 return true; 1184 } 1185 1186 static bool access_id_reg(struct kvm_vcpu *vcpu, 1187 struct sys_reg_params *p, 1188 const struct sys_reg_desc *r) 1189 { 1190 bool raz = sysreg_visible_as_raz(vcpu, r); 1191 1192 return __access_id_reg(vcpu, p, r, raz); 1193 } 1194 1195 static bool access_raz_id_reg(struct kvm_vcpu *vcpu, 1196 struct sys_reg_params *p, 1197 const struct sys_reg_desc *r) 1198 { 1199 return __access_id_reg(vcpu, p, r, true); 1200 } 1201 1202 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id); 1203 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id); 1204 static u64 sys_reg_to_index(const struct sys_reg_desc *reg); 1205 1206 /* Visibility overrides for SVE-specific control registers */ 1207 static unsigned int sve_visibility(const struct kvm_vcpu *vcpu, 1208 const struct sys_reg_desc *rd) 1209 { 1210 if (vcpu_has_sve(vcpu)) 1211 return 0; 1212 1213 return REG_HIDDEN; 1214 } 1215 1216 /* 1217 * cpufeature ID register user accessors 1218 * 1219 * For now, these registers are immutable for userspace, so no values 1220 * are stored, and for set_id_reg() we don't allow the effective value 1221 * to be changed. 1222 */ 1223 static int __get_id_reg(const struct kvm_vcpu *vcpu, 1224 const struct sys_reg_desc *rd, void __user *uaddr, 1225 bool raz) 1226 { 1227 const u64 id = sys_reg_to_index(rd); 1228 const u64 val = read_id_reg(vcpu, rd, raz); 1229 1230 return reg_to_user(uaddr, &val, id); 1231 } 1232 1233 static int __set_id_reg(const struct kvm_vcpu *vcpu, 1234 const struct sys_reg_desc *rd, void __user *uaddr, 1235 bool raz) 1236 { 1237 const u64 id = sys_reg_to_index(rd); 1238 int err; 1239 u64 val; 1240 1241 err = reg_from_user(&val, uaddr, id); 1242 if (err) 1243 return err; 1244 1245 /* This is what we mean by invariant: you can't change it. */ 1246 if (val != read_id_reg(vcpu, rd, raz)) 1247 return -EINVAL; 1248 1249 return 0; 1250 } 1251 1252 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1253 const struct kvm_one_reg *reg, void __user *uaddr) 1254 { 1255 bool raz = sysreg_visible_as_raz(vcpu, rd); 1256 1257 return __get_id_reg(vcpu, rd, uaddr, raz); 1258 } 1259 1260 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1261 const struct kvm_one_reg *reg, void __user *uaddr) 1262 { 1263 bool raz = sysreg_visible_as_raz(vcpu, rd); 1264 1265 return __set_id_reg(vcpu, rd, uaddr, raz); 1266 } 1267 1268 static int get_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1269 const struct kvm_one_reg *reg, void __user *uaddr) 1270 { 1271 return __get_id_reg(vcpu, rd, uaddr, true); 1272 } 1273 1274 static int set_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1275 const struct kvm_one_reg *reg, void __user *uaddr) 1276 { 1277 return __set_id_reg(vcpu, rd, uaddr, true); 1278 } 1279 1280 static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1281 const struct sys_reg_desc *r) 1282 { 1283 if (p->is_write) 1284 return write_to_read_only(vcpu, p, r); 1285 1286 p->regval = read_sanitised_ftr_reg(SYS_CTR_EL0); 1287 return true; 1288 } 1289 1290 static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1291 const struct sys_reg_desc *r) 1292 { 1293 if (p->is_write) 1294 return write_to_read_only(vcpu, p, r); 1295 1296 p->regval = read_sysreg(clidr_el1); 1297 return true; 1298 } 1299 1300 static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1301 const struct sys_reg_desc *r) 1302 { 1303 int reg = r->reg; 1304 1305 /* See the 32bit mapping in kvm_host.h */ 1306 if (p->is_aarch32) 1307 reg = r->reg / 2; 1308 1309 if (p->is_write) 1310 vcpu_write_sys_reg(vcpu, p->regval, reg); 1311 else 1312 p->regval = vcpu_read_sys_reg(vcpu, reg); 1313 return true; 1314 } 1315 1316 static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1317 const struct sys_reg_desc *r) 1318 { 1319 u32 csselr; 1320 1321 if (p->is_write) 1322 return write_to_read_only(vcpu, p, r); 1323 1324 csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1); 1325 p->regval = get_ccsidr(csselr); 1326 1327 /* 1328 * Guests should not be doing cache operations by set/way at all, and 1329 * for this reason, we trap them and attempt to infer the intent, so 1330 * that we can flush the entire guest's address space at the appropriate 1331 * time. 1332 * To prevent this trapping from causing performance problems, let's 1333 * expose the geometry of all data and unified caches (which are 1334 * guaranteed to be PIPT and thus non-aliasing) as 1 set and 1 way. 1335 * [If guests should attempt to infer aliasing properties from the 1336 * geometry (which is not permitted by the architecture), they would 1337 * only do so for virtually indexed caches.] 1338 */ 1339 if (!(csselr & 1)) // data or unified cache 1340 p->regval &= ~GENMASK(27, 3); 1341 return true; 1342 } 1343 1344 static bool access_mte_regs(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1345 const struct sys_reg_desc *r) 1346 { 1347 kvm_inject_undefined(vcpu); 1348 return false; 1349 } 1350 1351 /* sys_reg_desc initialiser for known cpufeature ID registers */ 1352 #define ID_SANITISED(name) { \ 1353 SYS_DESC(SYS_##name), \ 1354 .access = access_id_reg, \ 1355 .get_user = get_id_reg, \ 1356 .set_user = set_id_reg, \ 1357 .visibility = id_visibility, \ 1358 } 1359 1360 /* 1361 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID 1362 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2 1363 * (1 <= crm < 8, 0 <= Op2 < 8). 1364 */ 1365 #define ID_UNALLOCATED(crm, op2) { \ 1366 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \ 1367 .access = access_raz_id_reg, \ 1368 .get_user = get_raz_id_reg, \ 1369 .set_user = set_raz_id_reg, \ 1370 } 1371 1372 /* 1373 * sys_reg_desc initialiser for known ID registers that we hide from guests. 1374 * For now, these are exposed just like unallocated ID regs: they appear 1375 * RAZ for the guest. 1376 */ 1377 #define ID_HIDDEN(name) { \ 1378 SYS_DESC(SYS_##name), \ 1379 .access = access_raz_id_reg, \ 1380 .get_user = get_raz_id_reg, \ 1381 .set_user = set_raz_id_reg, \ 1382 } 1383 1384 /* 1385 * Architected system registers. 1386 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2 1387 * 1388 * Debug handling: We do trap most, if not all debug related system 1389 * registers. The implementation is good enough to ensure that a guest 1390 * can use these with minimal performance degradation. The drawback is 1391 * that we don't implement any of the external debug, none of the 1392 * OSlock protocol. This should be revisited if we ever encounter a 1393 * more demanding guest... 1394 */ 1395 static const struct sys_reg_desc sys_reg_descs[] = { 1396 { SYS_DESC(SYS_DC_ISW), access_dcsw }, 1397 { SYS_DESC(SYS_DC_CSW), access_dcsw }, 1398 { SYS_DESC(SYS_DC_CISW), access_dcsw }, 1399 1400 DBG_BCR_BVR_WCR_WVR_EL1(0), 1401 DBG_BCR_BVR_WCR_WVR_EL1(1), 1402 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 }, 1403 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 }, 1404 DBG_BCR_BVR_WCR_WVR_EL1(2), 1405 DBG_BCR_BVR_WCR_WVR_EL1(3), 1406 DBG_BCR_BVR_WCR_WVR_EL1(4), 1407 DBG_BCR_BVR_WCR_WVR_EL1(5), 1408 DBG_BCR_BVR_WCR_WVR_EL1(6), 1409 DBG_BCR_BVR_WCR_WVR_EL1(7), 1410 DBG_BCR_BVR_WCR_WVR_EL1(8), 1411 DBG_BCR_BVR_WCR_WVR_EL1(9), 1412 DBG_BCR_BVR_WCR_WVR_EL1(10), 1413 DBG_BCR_BVR_WCR_WVR_EL1(11), 1414 DBG_BCR_BVR_WCR_WVR_EL1(12), 1415 DBG_BCR_BVR_WCR_WVR_EL1(13), 1416 DBG_BCR_BVR_WCR_WVR_EL1(14), 1417 DBG_BCR_BVR_WCR_WVR_EL1(15), 1418 1419 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi }, 1420 { SYS_DESC(SYS_OSLAR_EL1), trap_raz_wi }, 1421 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1 }, 1422 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi }, 1423 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi }, 1424 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi }, 1425 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi }, 1426 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 }, 1427 1428 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi }, 1429 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi }, 1430 // DBGDTR[TR]X_EL0 share the same encoding 1431 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi }, 1432 1433 { SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 }, 1434 1435 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 }, 1436 1437 /* 1438 * ID regs: all ID_SANITISED() entries here must have corresponding 1439 * entries in arm64_ftr_regs[]. 1440 */ 1441 1442 /* AArch64 mappings of the AArch32 ID registers */ 1443 /* CRm=1 */ 1444 ID_SANITISED(ID_PFR0_EL1), 1445 ID_SANITISED(ID_PFR1_EL1), 1446 ID_SANITISED(ID_DFR0_EL1), 1447 ID_HIDDEN(ID_AFR0_EL1), 1448 ID_SANITISED(ID_MMFR0_EL1), 1449 ID_SANITISED(ID_MMFR1_EL1), 1450 ID_SANITISED(ID_MMFR2_EL1), 1451 ID_SANITISED(ID_MMFR3_EL1), 1452 1453 /* CRm=2 */ 1454 ID_SANITISED(ID_ISAR0_EL1), 1455 ID_SANITISED(ID_ISAR1_EL1), 1456 ID_SANITISED(ID_ISAR2_EL1), 1457 ID_SANITISED(ID_ISAR3_EL1), 1458 ID_SANITISED(ID_ISAR4_EL1), 1459 ID_SANITISED(ID_ISAR5_EL1), 1460 ID_SANITISED(ID_MMFR4_EL1), 1461 ID_SANITISED(ID_ISAR6_EL1), 1462 1463 /* CRm=3 */ 1464 ID_SANITISED(MVFR0_EL1), 1465 ID_SANITISED(MVFR1_EL1), 1466 ID_SANITISED(MVFR2_EL1), 1467 ID_UNALLOCATED(3,3), 1468 ID_SANITISED(ID_PFR2_EL1), 1469 ID_HIDDEN(ID_DFR1_EL1), 1470 ID_SANITISED(ID_MMFR5_EL1), 1471 ID_UNALLOCATED(3,7), 1472 1473 /* AArch64 ID registers */ 1474 /* CRm=4 */ 1475 ID_SANITISED(ID_AA64PFR0_EL1), 1476 ID_SANITISED(ID_AA64PFR1_EL1), 1477 ID_UNALLOCATED(4,2), 1478 ID_UNALLOCATED(4,3), 1479 ID_SANITISED(ID_AA64ZFR0_EL1), 1480 ID_UNALLOCATED(4,5), 1481 ID_UNALLOCATED(4,6), 1482 ID_UNALLOCATED(4,7), 1483 1484 /* CRm=5 */ 1485 ID_SANITISED(ID_AA64DFR0_EL1), 1486 ID_SANITISED(ID_AA64DFR1_EL1), 1487 ID_UNALLOCATED(5,2), 1488 ID_UNALLOCATED(5,3), 1489 ID_HIDDEN(ID_AA64AFR0_EL1), 1490 ID_HIDDEN(ID_AA64AFR1_EL1), 1491 ID_UNALLOCATED(5,6), 1492 ID_UNALLOCATED(5,7), 1493 1494 /* CRm=6 */ 1495 ID_SANITISED(ID_AA64ISAR0_EL1), 1496 ID_SANITISED(ID_AA64ISAR1_EL1), 1497 ID_UNALLOCATED(6,2), 1498 ID_UNALLOCATED(6,3), 1499 ID_UNALLOCATED(6,4), 1500 ID_UNALLOCATED(6,5), 1501 ID_UNALLOCATED(6,6), 1502 ID_UNALLOCATED(6,7), 1503 1504 /* CRm=7 */ 1505 ID_SANITISED(ID_AA64MMFR0_EL1), 1506 ID_SANITISED(ID_AA64MMFR1_EL1), 1507 ID_SANITISED(ID_AA64MMFR2_EL1), 1508 ID_UNALLOCATED(7,3), 1509 ID_UNALLOCATED(7,4), 1510 ID_UNALLOCATED(7,5), 1511 ID_UNALLOCATED(7,6), 1512 ID_UNALLOCATED(7,7), 1513 1514 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 }, 1515 { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 }, 1516 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 }, 1517 1518 { SYS_DESC(SYS_RGSR_EL1), access_mte_regs }, 1519 { SYS_DESC(SYS_GCR_EL1), access_mte_regs }, 1520 1521 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility }, 1522 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 }, 1523 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 }, 1524 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 }, 1525 1526 PTRAUTH_KEY(APIA), 1527 PTRAUTH_KEY(APIB), 1528 PTRAUTH_KEY(APDA), 1529 PTRAUTH_KEY(APDB), 1530 PTRAUTH_KEY(APGA), 1531 1532 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 }, 1533 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 }, 1534 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 }, 1535 1536 { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi }, 1537 { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi }, 1538 { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi }, 1539 { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi }, 1540 { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi }, 1541 { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi }, 1542 { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi }, 1543 { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi }, 1544 1545 { SYS_DESC(SYS_TFSR_EL1), access_mte_regs }, 1546 { SYS_DESC(SYS_TFSRE0_EL1), access_mte_regs }, 1547 1548 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 }, 1549 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 }, 1550 1551 { SYS_DESC(SYS_PMINTENSET_EL1), access_pminten, reset_unknown, PMINTENSET_EL1 }, 1552 { SYS_DESC(SYS_PMINTENCLR_EL1), access_pminten, reset_unknown, PMINTENSET_EL1 }, 1553 1554 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 }, 1555 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 }, 1556 1557 { SYS_DESC(SYS_LORSA_EL1), trap_loregion }, 1558 { SYS_DESC(SYS_LOREA_EL1), trap_loregion }, 1559 { SYS_DESC(SYS_LORN_EL1), trap_loregion }, 1560 { SYS_DESC(SYS_LORC_EL1), trap_loregion }, 1561 { SYS_DESC(SYS_LORID_EL1), trap_loregion }, 1562 1563 { SYS_DESC(SYS_VBAR_EL1), NULL, reset_val, VBAR_EL1, 0 }, 1564 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 }, 1565 1566 { SYS_DESC(SYS_ICC_IAR0_EL1), write_to_read_only }, 1567 { SYS_DESC(SYS_ICC_EOIR0_EL1), read_from_write_only }, 1568 { SYS_DESC(SYS_ICC_HPPIR0_EL1), write_to_read_only }, 1569 { SYS_DESC(SYS_ICC_DIR_EL1), read_from_write_only }, 1570 { SYS_DESC(SYS_ICC_RPR_EL1), write_to_read_only }, 1571 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi }, 1572 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi }, 1573 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi }, 1574 { SYS_DESC(SYS_ICC_IAR1_EL1), write_to_read_only }, 1575 { SYS_DESC(SYS_ICC_EOIR1_EL1), read_from_write_only }, 1576 { SYS_DESC(SYS_ICC_HPPIR1_EL1), write_to_read_only }, 1577 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre }, 1578 1579 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 }, 1580 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 }, 1581 1582 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0}, 1583 1584 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr }, 1585 { SYS_DESC(SYS_CLIDR_EL1), access_clidr }, 1586 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, 1587 { SYS_DESC(SYS_CTR_EL0), access_ctr }, 1588 1589 { SYS_DESC(SYS_PMCR_EL0), access_pmcr, reset_pmcr, PMCR_EL0 }, 1590 { SYS_DESC(SYS_PMCNTENSET_EL0), access_pmcnten, reset_unknown, PMCNTENSET_EL0 }, 1591 { SYS_DESC(SYS_PMCNTENCLR_EL0), access_pmcnten, reset_unknown, PMCNTENSET_EL0 }, 1592 { SYS_DESC(SYS_PMOVSCLR_EL0), access_pmovs, reset_unknown, PMOVSSET_EL0 }, 1593 { SYS_DESC(SYS_PMSWINC_EL0), access_pmswinc, reset_unknown, PMSWINC_EL0 }, 1594 { SYS_DESC(SYS_PMSELR_EL0), access_pmselr, reset_unknown, PMSELR_EL0 }, 1595 { SYS_DESC(SYS_PMCEID0_EL0), access_pmceid }, 1596 { SYS_DESC(SYS_PMCEID1_EL0), access_pmceid }, 1597 { SYS_DESC(SYS_PMCCNTR_EL0), access_pmu_evcntr, reset_unknown, PMCCNTR_EL0 }, 1598 { SYS_DESC(SYS_PMXEVTYPER_EL0), access_pmu_evtyper }, 1599 { SYS_DESC(SYS_PMXEVCNTR_EL0), access_pmu_evcntr }, 1600 /* 1601 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero 1602 * in 32bit mode. Here we choose to reset it as zero for consistency. 1603 */ 1604 { SYS_DESC(SYS_PMUSERENR_EL0), access_pmuserenr, reset_val, PMUSERENR_EL0, 0 }, 1605 { SYS_DESC(SYS_PMOVSSET_EL0), access_pmovs, reset_unknown, PMOVSSET_EL0 }, 1606 1607 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 }, 1608 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 }, 1609 1610 { SYS_DESC(SYS_AMCR_EL0), access_amu }, 1611 { SYS_DESC(SYS_AMCFGR_EL0), access_amu }, 1612 { SYS_DESC(SYS_AMCGCR_EL0), access_amu }, 1613 { SYS_DESC(SYS_AMUSERENR_EL0), access_amu }, 1614 { SYS_DESC(SYS_AMCNTENCLR0_EL0), access_amu }, 1615 { SYS_DESC(SYS_AMCNTENSET0_EL0), access_amu }, 1616 { SYS_DESC(SYS_AMCNTENCLR1_EL0), access_amu }, 1617 { SYS_DESC(SYS_AMCNTENSET1_EL0), access_amu }, 1618 AMU_AMEVCNTR0_EL0(0), 1619 AMU_AMEVCNTR0_EL0(1), 1620 AMU_AMEVCNTR0_EL0(2), 1621 AMU_AMEVCNTR0_EL0(3), 1622 AMU_AMEVCNTR0_EL0(4), 1623 AMU_AMEVCNTR0_EL0(5), 1624 AMU_AMEVCNTR0_EL0(6), 1625 AMU_AMEVCNTR0_EL0(7), 1626 AMU_AMEVCNTR0_EL0(8), 1627 AMU_AMEVCNTR0_EL0(9), 1628 AMU_AMEVCNTR0_EL0(10), 1629 AMU_AMEVCNTR0_EL0(11), 1630 AMU_AMEVCNTR0_EL0(12), 1631 AMU_AMEVCNTR0_EL0(13), 1632 AMU_AMEVCNTR0_EL0(14), 1633 AMU_AMEVCNTR0_EL0(15), 1634 AMU_AMEVTYPER0_EL0(0), 1635 AMU_AMEVTYPER0_EL0(1), 1636 AMU_AMEVTYPER0_EL0(2), 1637 AMU_AMEVTYPER0_EL0(3), 1638 AMU_AMEVTYPER0_EL0(4), 1639 AMU_AMEVTYPER0_EL0(5), 1640 AMU_AMEVTYPER0_EL0(6), 1641 AMU_AMEVTYPER0_EL0(7), 1642 AMU_AMEVTYPER0_EL0(8), 1643 AMU_AMEVTYPER0_EL0(9), 1644 AMU_AMEVTYPER0_EL0(10), 1645 AMU_AMEVTYPER0_EL0(11), 1646 AMU_AMEVTYPER0_EL0(12), 1647 AMU_AMEVTYPER0_EL0(13), 1648 AMU_AMEVTYPER0_EL0(14), 1649 AMU_AMEVTYPER0_EL0(15), 1650 AMU_AMEVCNTR1_EL0(0), 1651 AMU_AMEVCNTR1_EL0(1), 1652 AMU_AMEVCNTR1_EL0(2), 1653 AMU_AMEVCNTR1_EL0(3), 1654 AMU_AMEVCNTR1_EL0(4), 1655 AMU_AMEVCNTR1_EL0(5), 1656 AMU_AMEVCNTR1_EL0(6), 1657 AMU_AMEVCNTR1_EL0(7), 1658 AMU_AMEVCNTR1_EL0(8), 1659 AMU_AMEVCNTR1_EL0(9), 1660 AMU_AMEVCNTR1_EL0(10), 1661 AMU_AMEVCNTR1_EL0(11), 1662 AMU_AMEVCNTR1_EL0(12), 1663 AMU_AMEVCNTR1_EL0(13), 1664 AMU_AMEVCNTR1_EL0(14), 1665 AMU_AMEVCNTR1_EL0(15), 1666 AMU_AMEVTYPER1_EL0(0), 1667 AMU_AMEVTYPER1_EL0(1), 1668 AMU_AMEVTYPER1_EL0(2), 1669 AMU_AMEVTYPER1_EL0(3), 1670 AMU_AMEVTYPER1_EL0(4), 1671 AMU_AMEVTYPER1_EL0(5), 1672 AMU_AMEVTYPER1_EL0(6), 1673 AMU_AMEVTYPER1_EL0(7), 1674 AMU_AMEVTYPER1_EL0(8), 1675 AMU_AMEVTYPER1_EL0(9), 1676 AMU_AMEVTYPER1_EL0(10), 1677 AMU_AMEVTYPER1_EL0(11), 1678 AMU_AMEVTYPER1_EL0(12), 1679 AMU_AMEVTYPER1_EL0(13), 1680 AMU_AMEVTYPER1_EL0(14), 1681 AMU_AMEVTYPER1_EL0(15), 1682 1683 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer }, 1684 { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer }, 1685 { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer }, 1686 1687 /* PMEVCNTRn_EL0 */ 1688 PMU_PMEVCNTR_EL0(0), 1689 PMU_PMEVCNTR_EL0(1), 1690 PMU_PMEVCNTR_EL0(2), 1691 PMU_PMEVCNTR_EL0(3), 1692 PMU_PMEVCNTR_EL0(4), 1693 PMU_PMEVCNTR_EL0(5), 1694 PMU_PMEVCNTR_EL0(6), 1695 PMU_PMEVCNTR_EL0(7), 1696 PMU_PMEVCNTR_EL0(8), 1697 PMU_PMEVCNTR_EL0(9), 1698 PMU_PMEVCNTR_EL0(10), 1699 PMU_PMEVCNTR_EL0(11), 1700 PMU_PMEVCNTR_EL0(12), 1701 PMU_PMEVCNTR_EL0(13), 1702 PMU_PMEVCNTR_EL0(14), 1703 PMU_PMEVCNTR_EL0(15), 1704 PMU_PMEVCNTR_EL0(16), 1705 PMU_PMEVCNTR_EL0(17), 1706 PMU_PMEVCNTR_EL0(18), 1707 PMU_PMEVCNTR_EL0(19), 1708 PMU_PMEVCNTR_EL0(20), 1709 PMU_PMEVCNTR_EL0(21), 1710 PMU_PMEVCNTR_EL0(22), 1711 PMU_PMEVCNTR_EL0(23), 1712 PMU_PMEVCNTR_EL0(24), 1713 PMU_PMEVCNTR_EL0(25), 1714 PMU_PMEVCNTR_EL0(26), 1715 PMU_PMEVCNTR_EL0(27), 1716 PMU_PMEVCNTR_EL0(28), 1717 PMU_PMEVCNTR_EL0(29), 1718 PMU_PMEVCNTR_EL0(30), 1719 /* PMEVTYPERn_EL0 */ 1720 PMU_PMEVTYPER_EL0(0), 1721 PMU_PMEVTYPER_EL0(1), 1722 PMU_PMEVTYPER_EL0(2), 1723 PMU_PMEVTYPER_EL0(3), 1724 PMU_PMEVTYPER_EL0(4), 1725 PMU_PMEVTYPER_EL0(5), 1726 PMU_PMEVTYPER_EL0(6), 1727 PMU_PMEVTYPER_EL0(7), 1728 PMU_PMEVTYPER_EL0(8), 1729 PMU_PMEVTYPER_EL0(9), 1730 PMU_PMEVTYPER_EL0(10), 1731 PMU_PMEVTYPER_EL0(11), 1732 PMU_PMEVTYPER_EL0(12), 1733 PMU_PMEVTYPER_EL0(13), 1734 PMU_PMEVTYPER_EL0(14), 1735 PMU_PMEVTYPER_EL0(15), 1736 PMU_PMEVTYPER_EL0(16), 1737 PMU_PMEVTYPER_EL0(17), 1738 PMU_PMEVTYPER_EL0(18), 1739 PMU_PMEVTYPER_EL0(19), 1740 PMU_PMEVTYPER_EL0(20), 1741 PMU_PMEVTYPER_EL0(21), 1742 PMU_PMEVTYPER_EL0(22), 1743 PMU_PMEVTYPER_EL0(23), 1744 PMU_PMEVTYPER_EL0(24), 1745 PMU_PMEVTYPER_EL0(25), 1746 PMU_PMEVTYPER_EL0(26), 1747 PMU_PMEVTYPER_EL0(27), 1748 PMU_PMEVTYPER_EL0(28), 1749 PMU_PMEVTYPER_EL0(29), 1750 PMU_PMEVTYPER_EL0(30), 1751 /* 1752 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero 1753 * in 32bit mode. Here we choose to reset it as zero for consistency. 1754 */ 1755 { SYS_DESC(SYS_PMCCFILTR_EL0), access_pmu_evtyper, reset_val, PMCCFILTR_EL0, 0 }, 1756 1757 { SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 }, 1758 { SYS_DESC(SYS_IFSR32_EL2), NULL, reset_unknown, IFSR32_EL2 }, 1759 { SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x700 }, 1760 }; 1761 1762 static bool trap_dbgidr(struct kvm_vcpu *vcpu, 1763 struct sys_reg_params *p, 1764 const struct sys_reg_desc *r) 1765 { 1766 if (p->is_write) { 1767 return ignore_write(vcpu, p); 1768 } else { 1769 u64 dfr = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); 1770 u64 pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1771 u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL3_SHIFT); 1772 1773 p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) | 1774 (((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) | 1775 (((dfr >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) << 20) 1776 | (6 << 16) | (el3 << 14) | (el3 << 12)); 1777 return true; 1778 } 1779 } 1780 1781 static bool trap_debug32(struct kvm_vcpu *vcpu, 1782 struct sys_reg_params *p, 1783 const struct sys_reg_desc *r) 1784 { 1785 if (p->is_write) { 1786 vcpu_cp14(vcpu, r->reg) = p->regval; 1787 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY; 1788 } else { 1789 p->regval = vcpu_cp14(vcpu, r->reg); 1790 } 1791 1792 return true; 1793 } 1794 1795 /* AArch32 debug register mappings 1796 * 1797 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0] 1798 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32] 1799 * 1800 * All control registers and watchpoint value registers are mapped to 1801 * the lower 32 bits of their AArch64 equivalents. We share the trap 1802 * handlers with the above AArch64 code which checks what mode the 1803 * system is in. 1804 */ 1805 1806 static bool trap_xvr(struct kvm_vcpu *vcpu, 1807 struct sys_reg_params *p, 1808 const struct sys_reg_desc *rd) 1809 { 1810 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg]; 1811 1812 if (p->is_write) { 1813 u64 val = *dbg_reg; 1814 1815 val &= 0xffffffffUL; 1816 val |= p->regval << 32; 1817 *dbg_reg = val; 1818 1819 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY; 1820 } else { 1821 p->regval = *dbg_reg >> 32; 1822 } 1823 1824 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg); 1825 1826 return true; 1827 } 1828 1829 #define DBG_BCR_BVR_WCR_WVR(n) \ 1830 /* DBGBVRn */ \ 1831 { Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \ 1832 /* DBGBCRn */ \ 1833 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \ 1834 /* DBGWVRn */ \ 1835 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \ 1836 /* DBGWCRn */ \ 1837 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n } 1838 1839 #define DBGBXVR(n) \ 1840 { Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_xvr, NULL, n } 1841 1842 /* 1843 * Trapped cp14 registers. We generally ignore most of the external 1844 * debug, on the principle that they don't really make sense to a 1845 * guest. Revisit this one day, would this principle change. 1846 */ 1847 static const struct sys_reg_desc cp14_regs[] = { 1848 /* DBGIDR */ 1849 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgidr }, 1850 /* DBGDTRRXext */ 1851 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi }, 1852 1853 DBG_BCR_BVR_WCR_WVR(0), 1854 /* DBGDSCRint */ 1855 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi }, 1856 DBG_BCR_BVR_WCR_WVR(1), 1857 /* DBGDCCINT */ 1858 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug32, NULL, cp14_DBGDCCINT }, 1859 /* DBGDSCRext */ 1860 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug32, NULL, cp14_DBGDSCRext }, 1861 DBG_BCR_BVR_WCR_WVR(2), 1862 /* DBGDTR[RT]Xint */ 1863 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi }, 1864 /* DBGDTR[RT]Xext */ 1865 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi }, 1866 DBG_BCR_BVR_WCR_WVR(3), 1867 DBG_BCR_BVR_WCR_WVR(4), 1868 DBG_BCR_BVR_WCR_WVR(5), 1869 /* DBGWFAR */ 1870 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi }, 1871 /* DBGOSECCR */ 1872 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi }, 1873 DBG_BCR_BVR_WCR_WVR(6), 1874 /* DBGVCR */ 1875 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug32, NULL, cp14_DBGVCR }, 1876 DBG_BCR_BVR_WCR_WVR(7), 1877 DBG_BCR_BVR_WCR_WVR(8), 1878 DBG_BCR_BVR_WCR_WVR(9), 1879 DBG_BCR_BVR_WCR_WVR(10), 1880 DBG_BCR_BVR_WCR_WVR(11), 1881 DBG_BCR_BVR_WCR_WVR(12), 1882 DBG_BCR_BVR_WCR_WVR(13), 1883 DBG_BCR_BVR_WCR_WVR(14), 1884 DBG_BCR_BVR_WCR_WVR(15), 1885 1886 /* DBGDRAR (32bit) */ 1887 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi }, 1888 1889 DBGBXVR(0), 1890 /* DBGOSLAR */ 1891 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi }, 1892 DBGBXVR(1), 1893 /* DBGOSLSR */ 1894 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 }, 1895 DBGBXVR(2), 1896 DBGBXVR(3), 1897 /* DBGOSDLR */ 1898 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi }, 1899 DBGBXVR(4), 1900 /* DBGPRCR */ 1901 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi }, 1902 DBGBXVR(5), 1903 DBGBXVR(6), 1904 DBGBXVR(7), 1905 DBGBXVR(8), 1906 DBGBXVR(9), 1907 DBGBXVR(10), 1908 DBGBXVR(11), 1909 DBGBXVR(12), 1910 DBGBXVR(13), 1911 DBGBXVR(14), 1912 DBGBXVR(15), 1913 1914 /* DBGDSAR (32bit) */ 1915 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi }, 1916 1917 /* DBGDEVID2 */ 1918 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi }, 1919 /* DBGDEVID1 */ 1920 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi }, 1921 /* DBGDEVID */ 1922 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi }, 1923 /* DBGCLAIMSET */ 1924 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi }, 1925 /* DBGCLAIMCLR */ 1926 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi }, 1927 /* DBGAUTHSTATUS */ 1928 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 }, 1929 }; 1930 1931 /* Trapped cp14 64bit registers */ 1932 static const struct sys_reg_desc cp14_64_regs[] = { 1933 /* DBGDRAR (64bit) */ 1934 { Op1( 0), CRm( 1), .access = trap_raz_wi }, 1935 1936 /* DBGDSAR (64bit) */ 1937 { Op1( 0), CRm( 2), .access = trap_raz_wi }, 1938 }; 1939 1940 /* Macro to expand the PMEVCNTRn register */ 1941 #define PMU_PMEVCNTR(n) \ 1942 /* PMEVCNTRn */ \ 1943 { Op1(0), CRn(0b1110), \ 1944 CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \ 1945 access_pmu_evcntr } 1946 1947 /* Macro to expand the PMEVTYPERn register */ 1948 #define PMU_PMEVTYPER(n) \ 1949 /* PMEVTYPERn */ \ 1950 { Op1(0), CRn(0b1110), \ 1951 CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \ 1952 access_pmu_evtyper } 1953 1954 /* 1955 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding, 1956 * depending on the way they are accessed (as a 32bit or a 64bit 1957 * register). 1958 */ 1959 static const struct sys_reg_desc cp15_regs[] = { 1960 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr }, 1961 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, c1_SCTLR }, 1962 { Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr }, 1963 { Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr }, 1964 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 }, 1965 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 }, 1966 { Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR }, 1967 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, c3_DACR }, 1968 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, c5_DFSR }, 1969 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, c5_IFSR }, 1970 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, c5_ADFSR }, 1971 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, c5_AIFSR }, 1972 { Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, c6_DFAR }, 1973 { Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, c6_IFAR }, 1974 1975 /* 1976 * DC{C,I,CI}SW operations: 1977 */ 1978 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw }, 1979 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw }, 1980 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw }, 1981 1982 /* PMU */ 1983 { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr }, 1984 { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcnten }, 1985 { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcnten }, 1986 { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs }, 1987 { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc }, 1988 { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr }, 1989 { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid }, 1990 { Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid }, 1991 { Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_evcntr }, 1992 { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper }, 1993 { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr }, 1994 { Op1( 0), CRn( 9), CRm(14), Op2( 0), access_pmuserenr }, 1995 { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pminten }, 1996 { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pminten }, 1997 { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovs }, 1998 1999 { Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR }, 2000 { Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR }, 2001 { Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, c10_AMAIR0 }, 2002 { Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 }, 2003 2004 /* ICC_SRE */ 2005 { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre }, 2006 2007 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID }, 2008 2009 /* Arch Tmers */ 2010 { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer }, 2011 { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer }, 2012 2013 /* PMEVCNTRn */ 2014 PMU_PMEVCNTR(0), 2015 PMU_PMEVCNTR(1), 2016 PMU_PMEVCNTR(2), 2017 PMU_PMEVCNTR(3), 2018 PMU_PMEVCNTR(4), 2019 PMU_PMEVCNTR(5), 2020 PMU_PMEVCNTR(6), 2021 PMU_PMEVCNTR(7), 2022 PMU_PMEVCNTR(8), 2023 PMU_PMEVCNTR(9), 2024 PMU_PMEVCNTR(10), 2025 PMU_PMEVCNTR(11), 2026 PMU_PMEVCNTR(12), 2027 PMU_PMEVCNTR(13), 2028 PMU_PMEVCNTR(14), 2029 PMU_PMEVCNTR(15), 2030 PMU_PMEVCNTR(16), 2031 PMU_PMEVCNTR(17), 2032 PMU_PMEVCNTR(18), 2033 PMU_PMEVCNTR(19), 2034 PMU_PMEVCNTR(20), 2035 PMU_PMEVCNTR(21), 2036 PMU_PMEVCNTR(22), 2037 PMU_PMEVCNTR(23), 2038 PMU_PMEVCNTR(24), 2039 PMU_PMEVCNTR(25), 2040 PMU_PMEVCNTR(26), 2041 PMU_PMEVCNTR(27), 2042 PMU_PMEVCNTR(28), 2043 PMU_PMEVCNTR(29), 2044 PMU_PMEVCNTR(30), 2045 /* PMEVTYPERn */ 2046 PMU_PMEVTYPER(0), 2047 PMU_PMEVTYPER(1), 2048 PMU_PMEVTYPER(2), 2049 PMU_PMEVTYPER(3), 2050 PMU_PMEVTYPER(4), 2051 PMU_PMEVTYPER(5), 2052 PMU_PMEVTYPER(6), 2053 PMU_PMEVTYPER(7), 2054 PMU_PMEVTYPER(8), 2055 PMU_PMEVTYPER(9), 2056 PMU_PMEVTYPER(10), 2057 PMU_PMEVTYPER(11), 2058 PMU_PMEVTYPER(12), 2059 PMU_PMEVTYPER(13), 2060 PMU_PMEVTYPER(14), 2061 PMU_PMEVTYPER(15), 2062 PMU_PMEVTYPER(16), 2063 PMU_PMEVTYPER(17), 2064 PMU_PMEVTYPER(18), 2065 PMU_PMEVTYPER(19), 2066 PMU_PMEVTYPER(20), 2067 PMU_PMEVTYPER(21), 2068 PMU_PMEVTYPER(22), 2069 PMU_PMEVTYPER(23), 2070 PMU_PMEVTYPER(24), 2071 PMU_PMEVTYPER(25), 2072 PMU_PMEVTYPER(26), 2073 PMU_PMEVTYPER(27), 2074 PMU_PMEVTYPER(28), 2075 PMU_PMEVTYPER(29), 2076 PMU_PMEVTYPER(30), 2077 /* PMCCFILTR */ 2078 { Op1(0), CRn(14), CRm(15), Op2(7), access_pmu_evtyper }, 2079 2080 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr }, 2081 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr }, 2082 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, c0_CSSELR }, 2083 }; 2084 2085 static const struct sys_reg_desc cp15_64_regs[] = { 2086 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR0 }, 2087 { Op1( 0), CRn( 0), CRm( 9), Op2( 0), access_pmu_evcntr }, 2088 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */ 2089 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 }, 2090 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */ 2091 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */ 2092 { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer }, 2093 }; 2094 2095 static int check_sysreg_table(const struct sys_reg_desc *table, unsigned int n, 2096 bool is_32) 2097 { 2098 unsigned int i; 2099 2100 for (i = 0; i < n; i++) { 2101 if (!is_32 && table[i].reg && !table[i].reset) { 2102 kvm_err("sys_reg table %p entry %d has lacks reset\n", 2103 table, i); 2104 return 1; 2105 } 2106 2107 if (i && cmp_sys_reg(&table[i-1], &table[i]) >= 0) { 2108 kvm_err("sys_reg table %p out of order (%d)\n", table, i - 1); 2109 return 1; 2110 } 2111 } 2112 2113 return 0; 2114 } 2115 2116 static int match_sys_reg(const void *key, const void *elt) 2117 { 2118 const unsigned long pval = (unsigned long)key; 2119 const struct sys_reg_desc *r = elt; 2120 2121 return pval - reg_to_encoding(r); 2122 } 2123 2124 static const struct sys_reg_desc *find_reg(const struct sys_reg_params *params, 2125 const struct sys_reg_desc table[], 2126 unsigned int num) 2127 { 2128 unsigned long pval = reg_to_encoding(params); 2129 2130 return bsearch((void *)pval, table, num, sizeof(table[0]), match_sys_reg); 2131 } 2132 2133 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu) 2134 { 2135 kvm_inject_undefined(vcpu); 2136 return 1; 2137 } 2138 2139 static void perform_access(struct kvm_vcpu *vcpu, 2140 struct sys_reg_params *params, 2141 const struct sys_reg_desc *r) 2142 { 2143 trace_kvm_sys_access(*vcpu_pc(vcpu), params, r); 2144 2145 /* Check for regs disabled by runtime config */ 2146 if (sysreg_hidden(vcpu, r)) { 2147 kvm_inject_undefined(vcpu); 2148 return; 2149 } 2150 2151 /* 2152 * Not having an accessor means that we have configured a trap 2153 * that we don't know how to handle. This certainly qualifies 2154 * as a gross bug that should be fixed right away. 2155 */ 2156 BUG_ON(!r->access); 2157 2158 /* Skip instruction if instructed so */ 2159 if (likely(r->access(vcpu, params, r))) 2160 kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu)); 2161 } 2162 2163 /* 2164 * emulate_cp -- tries to match a sys_reg access in a handling table, and 2165 * call the corresponding trap handler. 2166 * 2167 * @params: pointer to the descriptor of the access 2168 * @table: array of trap descriptors 2169 * @num: size of the trap descriptor array 2170 * 2171 * Return 0 if the access has been handled, and -1 if not. 2172 */ 2173 static int emulate_cp(struct kvm_vcpu *vcpu, 2174 struct sys_reg_params *params, 2175 const struct sys_reg_desc *table, 2176 size_t num) 2177 { 2178 const struct sys_reg_desc *r; 2179 2180 if (!table) 2181 return -1; /* Not handled */ 2182 2183 r = find_reg(params, table, num); 2184 2185 if (r) { 2186 perform_access(vcpu, params, r); 2187 return 0; 2188 } 2189 2190 /* Not handled */ 2191 return -1; 2192 } 2193 2194 static void unhandled_cp_access(struct kvm_vcpu *vcpu, 2195 struct sys_reg_params *params) 2196 { 2197 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu); 2198 int cp = -1; 2199 2200 switch (esr_ec) { 2201 case ESR_ELx_EC_CP15_32: 2202 case ESR_ELx_EC_CP15_64: 2203 cp = 15; 2204 break; 2205 case ESR_ELx_EC_CP14_MR: 2206 case ESR_ELx_EC_CP14_64: 2207 cp = 14; 2208 break; 2209 default: 2210 WARN_ON(1); 2211 } 2212 2213 print_sys_reg_msg(params, 2214 "Unsupported guest CP%d access at: %08lx [%08lx]\n", 2215 cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 2216 kvm_inject_undefined(vcpu); 2217 } 2218 2219 /** 2220 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access 2221 * @vcpu: The VCPU pointer 2222 * @run: The kvm_run struct 2223 */ 2224 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu, 2225 const struct sys_reg_desc *global, 2226 size_t nr_global) 2227 { 2228 struct sys_reg_params params; 2229 u32 esr = kvm_vcpu_get_esr(vcpu); 2230 int Rt = kvm_vcpu_sys_get_rt(vcpu); 2231 int Rt2 = (esr >> 10) & 0x1f; 2232 2233 params.is_aarch32 = true; 2234 params.is_32bit = false; 2235 params.CRm = (esr >> 1) & 0xf; 2236 params.is_write = ((esr & 1) == 0); 2237 2238 params.Op0 = 0; 2239 params.Op1 = (esr >> 16) & 0xf; 2240 params.Op2 = 0; 2241 params.CRn = 0; 2242 2243 /* 2244 * Make a 64-bit value out of Rt and Rt2. As we use the same trap 2245 * backends between AArch32 and AArch64, we get away with it. 2246 */ 2247 if (params.is_write) { 2248 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff; 2249 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32; 2250 } 2251 2252 /* 2253 * If the table contains a handler, handle the 2254 * potential register operation in the case of a read and return 2255 * with success. 2256 */ 2257 if (!emulate_cp(vcpu, ¶ms, global, nr_global)) { 2258 /* Split up the value between registers for the read side */ 2259 if (!params.is_write) { 2260 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval)); 2261 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval)); 2262 } 2263 2264 return 1; 2265 } 2266 2267 unhandled_cp_access(vcpu, ¶ms); 2268 return 1; 2269 } 2270 2271 /** 2272 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access 2273 * @vcpu: The VCPU pointer 2274 * @run: The kvm_run struct 2275 */ 2276 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu, 2277 const struct sys_reg_desc *global, 2278 size_t nr_global) 2279 { 2280 struct sys_reg_params params; 2281 u32 esr = kvm_vcpu_get_esr(vcpu); 2282 int Rt = kvm_vcpu_sys_get_rt(vcpu); 2283 2284 params.is_aarch32 = true; 2285 params.is_32bit = true; 2286 params.CRm = (esr >> 1) & 0xf; 2287 params.regval = vcpu_get_reg(vcpu, Rt); 2288 params.is_write = ((esr & 1) == 0); 2289 params.CRn = (esr >> 10) & 0xf; 2290 params.Op0 = 0; 2291 params.Op1 = (esr >> 14) & 0x7; 2292 params.Op2 = (esr >> 17) & 0x7; 2293 2294 if (!emulate_cp(vcpu, ¶ms, global, nr_global)) { 2295 if (!params.is_write) 2296 vcpu_set_reg(vcpu, Rt, params.regval); 2297 return 1; 2298 } 2299 2300 unhandled_cp_access(vcpu, ¶ms); 2301 return 1; 2302 } 2303 2304 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu) 2305 { 2306 return kvm_handle_cp_64(vcpu, cp15_64_regs, ARRAY_SIZE(cp15_64_regs)); 2307 } 2308 2309 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu) 2310 { 2311 return kvm_handle_cp_32(vcpu, cp15_regs, ARRAY_SIZE(cp15_regs)); 2312 } 2313 2314 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu) 2315 { 2316 return kvm_handle_cp_64(vcpu, cp14_64_regs, ARRAY_SIZE(cp14_64_regs)); 2317 } 2318 2319 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu) 2320 { 2321 return kvm_handle_cp_32(vcpu, cp14_regs, ARRAY_SIZE(cp14_regs)); 2322 } 2323 2324 static bool is_imp_def_sys_reg(struct sys_reg_params *params) 2325 { 2326 // See ARM DDI 0487E.a, section D12.3.2 2327 return params->Op0 == 3 && (params->CRn & 0b1011) == 0b1011; 2328 } 2329 2330 static int emulate_sys_reg(struct kvm_vcpu *vcpu, 2331 struct sys_reg_params *params) 2332 { 2333 const struct sys_reg_desc *r; 2334 2335 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 2336 2337 if (likely(r)) { 2338 perform_access(vcpu, params, r); 2339 } else if (is_imp_def_sys_reg(params)) { 2340 kvm_inject_undefined(vcpu); 2341 } else { 2342 print_sys_reg_msg(params, 2343 "Unsupported guest sys_reg access at: %lx [%08lx]\n", 2344 *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 2345 kvm_inject_undefined(vcpu); 2346 } 2347 return 1; 2348 } 2349 2350 /** 2351 * kvm_reset_sys_regs - sets system registers to reset value 2352 * @vcpu: The VCPU pointer 2353 * 2354 * This function finds the right table above and sets the registers on the 2355 * virtual CPU struct to their architecturally defined reset values. 2356 */ 2357 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu) 2358 { 2359 unsigned long i; 2360 2361 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) 2362 if (sys_reg_descs[i].reset) 2363 sys_reg_descs[i].reset(vcpu, &sys_reg_descs[i]); 2364 } 2365 2366 /** 2367 * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access 2368 * @vcpu: The VCPU pointer 2369 */ 2370 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu) 2371 { 2372 struct sys_reg_params params; 2373 unsigned long esr = kvm_vcpu_get_esr(vcpu); 2374 int Rt = kvm_vcpu_sys_get_rt(vcpu); 2375 int ret; 2376 2377 trace_kvm_handle_sys_reg(esr); 2378 2379 params.is_aarch32 = false; 2380 params.is_32bit = false; 2381 params.Op0 = (esr >> 20) & 3; 2382 params.Op1 = (esr >> 14) & 0x7; 2383 params.CRn = (esr >> 10) & 0xf; 2384 params.CRm = (esr >> 1) & 0xf; 2385 params.Op2 = (esr >> 17) & 0x7; 2386 params.regval = vcpu_get_reg(vcpu, Rt); 2387 params.is_write = !(esr & 1); 2388 2389 ret = emulate_sys_reg(vcpu, ¶ms); 2390 2391 if (!params.is_write) 2392 vcpu_set_reg(vcpu, Rt, params.regval); 2393 return ret; 2394 } 2395 2396 /****************************************************************************** 2397 * Userspace API 2398 *****************************************************************************/ 2399 2400 static bool index_to_params(u64 id, struct sys_reg_params *params) 2401 { 2402 switch (id & KVM_REG_SIZE_MASK) { 2403 case KVM_REG_SIZE_U64: 2404 /* Any unused index bits means it's not valid. */ 2405 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK 2406 | KVM_REG_ARM_COPROC_MASK 2407 | KVM_REG_ARM64_SYSREG_OP0_MASK 2408 | KVM_REG_ARM64_SYSREG_OP1_MASK 2409 | KVM_REG_ARM64_SYSREG_CRN_MASK 2410 | KVM_REG_ARM64_SYSREG_CRM_MASK 2411 | KVM_REG_ARM64_SYSREG_OP2_MASK)) 2412 return false; 2413 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK) 2414 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT); 2415 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK) 2416 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT); 2417 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK) 2418 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT); 2419 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK) 2420 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT); 2421 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK) 2422 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT); 2423 return true; 2424 default: 2425 return false; 2426 } 2427 } 2428 2429 const struct sys_reg_desc *find_reg_by_id(u64 id, 2430 struct sys_reg_params *params, 2431 const struct sys_reg_desc table[], 2432 unsigned int num) 2433 { 2434 if (!index_to_params(id, params)) 2435 return NULL; 2436 2437 return find_reg(params, table, num); 2438 } 2439 2440 /* Decode an index value, and find the sys_reg_desc entry. */ 2441 static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu, 2442 u64 id) 2443 { 2444 const struct sys_reg_desc *r; 2445 struct sys_reg_params params; 2446 2447 /* We only do sys_reg for now. */ 2448 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG) 2449 return NULL; 2450 2451 if (!index_to_params(id, ¶ms)) 2452 return NULL; 2453 2454 r = find_reg(¶ms, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 2455 2456 /* Not saved in the sys_reg array and not otherwise accessible? */ 2457 if (r && !(r->reg || r->get_user)) 2458 r = NULL; 2459 2460 return r; 2461 } 2462 2463 /* 2464 * These are the invariant sys_reg registers: we let the guest see the 2465 * host versions of these, so they're part of the guest state. 2466 * 2467 * A future CPU may provide a mechanism to present different values to 2468 * the guest, or a future kvm may trap them. 2469 */ 2470 2471 #define FUNCTION_INVARIANT(reg) \ 2472 static void get_##reg(struct kvm_vcpu *v, \ 2473 const struct sys_reg_desc *r) \ 2474 { \ 2475 ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \ 2476 } 2477 2478 FUNCTION_INVARIANT(midr_el1) 2479 FUNCTION_INVARIANT(revidr_el1) 2480 FUNCTION_INVARIANT(clidr_el1) 2481 FUNCTION_INVARIANT(aidr_el1) 2482 2483 static void get_ctr_el0(struct kvm_vcpu *v, const struct sys_reg_desc *r) 2484 { 2485 ((struct sys_reg_desc *)r)->val = read_sanitised_ftr_reg(SYS_CTR_EL0); 2486 } 2487 2488 /* ->val is filled in by kvm_sys_reg_table_init() */ 2489 static struct sys_reg_desc invariant_sys_regs[] = { 2490 { SYS_DESC(SYS_MIDR_EL1), NULL, get_midr_el1 }, 2491 { SYS_DESC(SYS_REVIDR_EL1), NULL, get_revidr_el1 }, 2492 { SYS_DESC(SYS_CLIDR_EL1), NULL, get_clidr_el1 }, 2493 { SYS_DESC(SYS_AIDR_EL1), NULL, get_aidr_el1 }, 2494 { SYS_DESC(SYS_CTR_EL0), NULL, get_ctr_el0 }, 2495 }; 2496 2497 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id) 2498 { 2499 if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0) 2500 return -EFAULT; 2501 return 0; 2502 } 2503 2504 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id) 2505 { 2506 if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0) 2507 return -EFAULT; 2508 return 0; 2509 } 2510 2511 static int get_invariant_sys_reg(u64 id, void __user *uaddr) 2512 { 2513 struct sys_reg_params params; 2514 const struct sys_reg_desc *r; 2515 2516 r = find_reg_by_id(id, ¶ms, invariant_sys_regs, 2517 ARRAY_SIZE(invariant_sys_regs)); 2518 if (!r) 2519 return -ENOENT; 2520 2521 return reg_to_user(uaddr, &r->val, id); 2522 } 2523 2524 static int set_invariant_sys_reg(u64 id, void __user *uaddr) 2525 { 2526 struct sys_reg_params params; 2527 const struct sys_reg_desc *r; 2528 int err; 2529 u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */ 2530 2531 r = find_reg_by_id(id, ¶ms, invariant_sys_regs, 2532 ARRAY_SIZE(invariant_sys_regs)); 2533 if (!r) 2534 return -ENOENT; 2535 2536 err = reg_from_user(&val, uaddr, id); 2537 if (err) 2538 return err; 2539 2540 /* This is what we mean by invariant: you can't change it. */ 2541 if (r->val != val) 2542 return -EINVAL; 2543 2544 return 0; 2545 } 2546 2547 static bool is_valid_cache(u32 val) 2548 { 2549 u32 level, ctype; 2550 2551 if (val >= CSSELR_MAX) 2552 return false; 2553 2554 /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */ 2555 level = (val >> 1); 2556 ctype = (cache_levels >> (level * 3)) & 7; 2557 2558 switch (ctype) { 2559 case 0: /* No cache */ 2560 return false; 2561 case 1: /* Instruction cache only */ 2562 return (val & 1); 2563 case 2: /* Data cache only */ 2564 case 4: /* Unified cache */ 2565 return !(val & 1); 2566 case 3: /* Separate instruction and data caches */ 2567 return true; 2568 default: /* Reserved: we can't know instruction or data. */ 2569 return false; 2570 } 2571 } 2572 2573 static int demux_c15_get(u64 id, void __user *uaddr) 2574 { 2575 u32 val; 2576 u32 __user *uval = uaddr; 2577 2578 /* Fail if we have unknown bits set. */ 2579 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 2580 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 2581 return -ENOENT; 2582 2583 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 2584 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 2585 if (KVM_REG_SIZE(id) != 4) 2586 return -ENOENT; 2587 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 2588 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 2589 if (!is_valid_cache(val)) 2590 return -ENOENT; 2591 2592 return put_user(get_ccsidr(val), uval); 2593 default: 2594 return -ENOENT; 2595 } 2596 } 2597 2598 static int demux_c15_set(u64 id, void __user *uaddr) 2599 { 2600 u32 val, newval; 2601 u32 __user *uval = uaddr; 2602 2603 /* Fail if we have unknown bits set. */ 2604 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 2605 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 2606 return -ENOENT; 2607 2608 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 2609 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 2610 if (KVM_REG_SIZE(id) != 4) 2611 return -ENOENT; 2612 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 2613 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 2614 if (!is_valid_cache(val)) 2615 return -ENOENT; 2616 2617 if (get_user(newval, uval)) 2618 return -EFAULT; 2619 2620 /* This is also invariant: you can't change it. */ 2621 if (newval != get_ccsidr(val)) 2622 return -EINVAL; 2623 return 0; 2624 default: 2625 return -ENOENT; 2626 } 2627 } 2628 2629 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 2630 { 2631 const struct sys_reg_desc *r; 2632 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 2633 2634 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 2635 return demux_c15_get(reg->id, uaddr); 2636 2637 if (KVM_REG_SIZE(reg->id) != sizeof(__u64)) 2638 return -ENOENT; 2639 2640 r = index_to_sys_reg_desc(vcpu, reg->id); 2641 if (!r) 2642 return get_invariant_sys_reg(reg->id, uaddr); 2643 2644 /* Check for regs disabled by runtime config */ 2645 if (sysreg_hidden(vcpu, r)) 2646 return -ENOENT; 2647 2648 if (r->get_user) 2649 return (r->get_user)(vcpu, r, reg, uaddr); 2650 2651 return reg_to_user(uaddr, &__vcpu_sys_reg(vcpu, r->reg), reg->id); 2652 } 2653 2654 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 2655 { 2656 const struct sys_reg_desc *r; 2657 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 2658 2659 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 2660 return demux_c15_set(reg->id, uaddr); 2661 2662 if (KVM_REG_SIZE(reg->id) != sizeof(__u64)) 2663 return -ENOENT; 2664 2665 r = index_to_sys_reg_desc(vcpu, reg->id); 2666 if (!r) 2667 return set_invariant_sys_reg(reg->id, uaddr); 2668 2669 /* Check for regs disabled by runtime config */ 2670 if (sysreg_hidden(vcpu, r)) 2671 return -ENOENT; 2672 2673 if (r->set_user) 2674 return (r->set_user)(vcpu, r, reg, uaddr); 2675 2676 return reg_from_user(&__vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id); 2677 } 2678 2679 static unsigned int num_demux_regs(void) 2680 { 2681 unsigned int i, count = 0; 2682 2683 for (i = 0; i < CSSELR_MAX; i++) 2684 if (is_valid_cache(i)) 2685 count++; 2686 2687 return count; 2688 } 2689 2690 static int write_demux_regids(u64 __user *uindices) 2691 { 2692 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX; 2693 unsigned int i; 2694 2695 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR; 2696 for (i = 0; i < CSSELR_MAX; i++) { 2697 if (!is_valid_cache(i)) 2698 continue; 2699 if (put_user(val | i, uindices)) 2700 return -EFAULT; 2701 uindices++; 2702 } 2703 return 0; 2704 } 2705 2706 static u64 sys_reg_to_index(const struct sys_reg_desc *reg) 2707 { 2708 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | 2709 KVM_REG_ARM64_SYSREG | 2710 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) | 2711 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) | 2712 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) | 2713 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) | 2714 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT)); 2715 } 2716 2717 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind) 2718 { 2719 if (!*uind) 2720 return true; 2721 2722 if (put_user(sys_reg_to_index(reg), *uind)) 2723 return false; 2724 2725 (*uind)++; 2726 return true; 2727 } 2728 2729 static int walk_one_sys_reg(const struct kvm_vcpu *vcpu, 2730 const struct sys_reg_desc *rd, 2731 u64 __user **uind, 2732 unsigned int *total) 2733 { 2734 /* 2735 * Ignore registers we trap but don't save, 2736 * and for which no custom user accessor is provided. 2737 */ 2738 if (!(rd->reg || rd->get_user)) 2739 return 0; 2740 2741 if (sysreg_hidden(vcpu, rd)) 2742 return 0; 2743 2744 if (!copy_reg_to_user(rd, uind)) 2745 return -EFAULT; 2746 2747 (*total)++; 2748 return 0; 2749 } 2750 2751 /* Assumed ordered tables, see kvm_sys_reg_table_init. */ 2752 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind) 2753 { 2754 const struct sys_reg_desc *i2, *end2; 2755 unsigned int total = 0; 2756 int err; 2757 2758 i2 = sys_reg_descs; 2759 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs); 2760 2761 while (i2 != end2) { 2762 err = walk_one_sys_reg(vcpu, i2++, &uind, &total); 2763 if (err) 2764 return err; 2765 } 2766 return total; 2767 } 2768 2769 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu) 2770 { 2771 return ARRAY_SIZE(invariant_sys_regs) 2772 + num_demux_regs() 2773 + walk_sys_regs(vcpu, (u64 __user *)NULL); 2774 } 2775 2776 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) 2777 { 2778 unsigned int i; 2779 int err; 2780 2781 /* Then give them all the invariant registers' indices. */ 2782 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) { 2783 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices)) 2784 return -EFAULT; 2785 uindices++; 2786 } 2787 2788 err = walk_sys_regs(vcpu, uindices); 2789 if (err < 0) 2790 return err; 2791 uindices += err; 2792 2793 return write_demux_regids(uindices); 2794 } 2795 2796 void kvm_sys_reg_table_init(void) 2797 { 2798 unsigned int i; 2799 struct sys_reg_desc clidr; 2800 2801 /* Make sure tables are unique and in order. */ 2802 BUG_ON(check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), false)); 2803 BUG_ON(check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), true)); 2804 BUG_ON(check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), true)); 2805 BUG_ON(check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), true)); 2806 BUG_ON(check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), true)); 2807 BUG_ON(check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs), false)); 2808 2809 /* We abuse the reset function to overwrite the table itself. */ 2810 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) 2811 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]); 2812 2813 /* 2814 * CLIDR format is awkward, so clean it up. See ARM B4.1.20: 2815 * 2816 * If software reads the Cache Type fields from Ctype1 2817 * upwards, once it has seen a value of 0b000, no caches 2818 * exist at further-out levels of the hierarchy. So, for 2819 * example, if Ctype3 is the first Cache Type field with a 2820 * value of 0b000, the values of Ctype4 to Ctype7 must be 2821 * ignored. 2822 */ 2823 get_clidr_el1(NULL, &clidr); /* Ugly... */ 2824 cache_levels = clidr.val; 2825 for (i = 0; i < 7; i++) 2826 if (((cache_levels >> (i*3)) & 7) == 0) 2827 break; 2828 /* Clear all higher bits. */ 2829 cache_levels &= (1 << (i*3))-1; 2830 } 2831