1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/kvm/coproc.c: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Authors: Rusty Russell <rusty@rustcorp.com.au> 9 * Christoffer Dall <c.dall@virtualopensystems.com> 10 */ 11 12 #include <linux/bitfield.h> 13 #include <linux/bsearch.h> 14 #include <linux/cacheinfo.h> 15 #include <linux/debugfs.h> 16 #include <linux/kvm_host.h> 17 #include <linux/mm.h> 18 #include <linux/printk.h> 19 #include <linux/uaccess.h> 20 21 #include <asm/arm_pmuv3.h> 22 #include <asm/cacheflush.h> 23 #include <asm/cputype.h> 24 #include <asm/debug-monitors.h> 25 #include <asm/esr.h> 26 #include <asm/kvm_arm.h> 27 #include <asm/kvm_emulate.h> 28 #include <asm/kvm_hyp.h> 29 #include <asm/kvm_mmu.h> 30 #include <asm/kvm_nested.h> 31 #include <asm/perf_event.h> 32 #include <asm/sysreg.h> 33 34 #include <trace/events/kvm.h> 35 36 #include "sys_regs.h" 37 #include "vgic/vgic.h" 38 39 #include "trace.h" 40 41 /* 42 * For AArch32, we only take care of what is being trapped. Anything 43 * that has to do with init and userspace access has to go via the 44 * 64bit interface. 45 */ 46 47 static u64 sys_reg_to_index(const struct sys_reg_desc *reg); 48 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 49 u64 val); 50 51 static bool undef_access(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 52 const struct sys_reg_desc *r) 53 { 54 kvm_inject_undefined(vcpu); 55 return false; 56 } 57 58 static bool bad_trap(struct kvm_vcpu *vcpu, 59 struct sys_reg_params *params, 60 const struct sys_reg_desc *r, 61 const char *msg) 62 { 63 WARN_ONCE(1, "Unexpected %s\n", msg); 64 print_sys_reg_instr(params); 65 return undef_access(vcpu, params, r); 66 } 67 68 static bool read_from_write_only(struct kvm_vcpu *vcpu, 69 struct sys_reg_params *params, 70 const struct sys_reg_desc *r) 71 { 72 return bad_trap(vcpu, params, r, 73 "sys_reg read to write-only register"); 74 } 75 76 static bool write_to_read_only(struct kvm_vcpu *vcpu, 77 struct sys_reg_params *params, 78 const struct sys_reg_desc *r) 79 { 80 return bad_trap(vcpu, params, r, 81 "sys_reg write to read-only register"); 82 } 83 84 #define PURE_EL2_SYSREG(el2) \ 85 case el2: { \ 86 *el1r = el2; \ 87 return true; \ 88 } 89 90 #define MAPPED_EL2_SYSREG(el2, el1, fn) \ 91 case el2: { \ 92 *xlate = fn; \ 93 *el1r = el1; \ 94 return true; \ 95 } 96 97 static bool get_el2_to_el1_mapping(unsigned int reg, 98 unsigned int *el1r, u64 (**xlate)(u64)) 99 { 100 switch (reg) { 101 PURE_EL2_SYSREG( VPIDR_EL2 ); 102 PURE_EL2_SYSREG( VMPIDR_EL2 ); 103 PURE_EL2_SYSREG( ACTLR_EL2 ); 104 PURE_EL2_SYSREG( HCR_EL2 ); 105 PURE_EL2_SYSREG( MDCR_EL2 ); 106 PURE_EL2_SYSREG( HSTR_EL2 ); 107 PURE_EL2_SYSREG( HACR_EL2 ); 108 PURE_EL2_SYSREG( VTTBR_EL2 ); 109 PURE_EL2_SYSREG( VTCR_EL2 ); 110 PURE_EL2_SYSREG( RVBAR_EL2 ); 111 PURE_EL2_SYSREG( TPIDR_EL2 ); 112 PURE_EL2_SYSREG( HPFAR_EL2 ); 113 PURE_EL2_SYSREG( HCRX_EL2 ); 114 PURE_EL2_SYSREG( HFGRTR_EL2 ); 115 PURE_EL2_SYSREG( HFGWTR_EL2 ); 116 PURE_EL2_SYSREG( HFGITR_EL2 ); 117 PURE_EL2_SYSREG( HDFGRTR_EL2 ); 118 PURE_EL2_SYSREG( HDFGWTR_EL2 ); 119 PURE_EL2_SYSREG( HAFGRTR_EL2 ); 120 PURE_EL2_SYSREG( CNTVOFF_EL2 ); 121 PURE_EL2_SYSREG( CNTHCTL_EL2 ); 122 MAPPED_EL2_SYSREG(SCTLR_EL2, SCTLR_EL1, 123 translate_sctlr_el2_to_sctlr_el1 ); 124 MAPPED_EL2_SYSREG(CPTR_EL2, CPACR_EL1, 125 translate_cptr_el2_to_cpacr_el1 ); 126 MAPPED_EL2_SYSREG(TTBR0_EL2, TTBR0_EL1, 127 translate_ttbr0_el2_to_ttbr0_el1 ); 128 MAPPED_EL2_SYSREG(TTBR1_EL2, TTBR1_EL1, NULL ); 129 MAPPED_EL2_SYSREG(TCR_EL2, TCR_EL1, 130 translate_tcr_el2_to_tcr_el1 ); 131 MAPPED_EL2_SYSREG(VBAR_EL2, VBAR_EL1, NULL ); 132 MAPPED_EL2_SYSREG(AFSR0_EL2, AFSR0_EL1, NULL ); 133 MAPPED_EL2_SYSREG(AFSR1_EL2, AFSR1_EL1, NULL ); 134 MAPPED_EL2_SYSREG(ESR_EL2, ESR_EL1, NULL ); 135 MAPPED_EL2_SYSREG(FAR_EL2, FAR_EL1, NULL ); 136 MAPPED_EL2_SYSREG(MAIR_EL2, MAIR_EL1, NULL ); 137 MAPPED_EL2_SYSREG(TCR2_EL2, TCR2_EL1, NULL ); 138 MAPPED_EL2_SYSREG(PIR_EL2, PIR_EL1, NULL ); 139 MAPPED_EL2_SYSREG(PIRE0_EL2, PIRE0_EL1, NULL ); 140 MAPPED_EL2_SYSREG(POR_EL2, POR_EL1, NULL ); 141 MAPPED_EL2_SYSREG(AMAIR_EL2, AMAIR_EL1, NULL ); 142 MAPPED_EL2_SYSREG(ELR_EL2, ELR_EL1, NULL ); 143 MAPPED_EL2_SYSREG(SPSR_EL2, SPSR_EL1, NULL ); 144 MAPPED_EL2_SYSREG(ZCR_EL2, ZCR_EL1, NULL ); 145 MAPPED_EL2_SYSREG(CONTEXTIDR_EL2, CONTEXTIDR_EL1, NULL ); 146 default: 147 return false; 148 } 149 } 150 151 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg) 152 { 153 u64 val = 0x8badf00d8badf00d; 154 u64 (*xlate)(u64) = NULL; 155 unsigned int el1r; 156 157 if (!vcpu_get_flag(vcpu, SYSREGS_ON_CPU)) 158 goto memory_read; 159 160 if (unlikely(get_el2_to_el1_mapping(reg, &el1r, &xlate))) { 161 if (!is_hyp_ctxt(vcpu)) 162 goto memory_read; 163 164 /* 165 * CNTHCTL_EL2 requires some special treatment to 166 * account for the bits that can be set via CNTKCTL_EL1. 167 */ 168 switch (reg) { 169 case CNTHCTL_EL2: 170 if (vcpu_el2_e2h_is_set(vcpu)) { 171 val = read_sysreg_el1(SYS_CNTKCTL); 172 val &= CNTKCTL_VALID_BITS; 173 val |= __vcpu_sys_reg(vcpu, reg) & ~CNTKCTL_VALID_BITS; 174 return val; 175 } 176 break; 177 } 178 179 /* 180 * If this register does not have an EL1 counterpart, 181 * then read the stored EL2 version. 182 */ 183 if (reg == el1r) 184 goto memory_read; 185 186 /* 187 * If we have a non-VHE guest and that the sysreg 188 * requires translation to be used at EL1, use the 189 * in-memory copy instead. 190 */ 191 if (!vcpu_el2_e2h_is_set(vcpu) && xlate) 192 goto memory_read; 193 194 /* Get the current version of the EL1 counterpart. */ 195 WARN_ON(!__vcpu_read_sys_reg_from_cpu(el1r, &val)); 196 if (reg >= __SANITISED_REG_START__) 197 val = kvm_vcpu_apply_reg_masks(vcpu, reg, val); 198 199 return val; 200 } 201 202 /* EL1 register can't be on the CPU if the guest is in vEL2. */ 203 if (unlikely(is_hyp_ctxt(vcpu))) 204 goto memory_read; 205 206 if (__vcpu_read_sys_reg_from_cpu(reg, &val)) 207 return val; 208 209 memory_read: 210 return __vcpu_sys_reg(vcpu, reg); 211 } 212 213 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg) 214 { 215 u64 (*xlate)(u64) = NULL; 216 unsigned int el1r; 217 218 if (!vcpu_get_flag(vcpu, SYSREGS_ON_CPU)) 219 goto memory_write; 220 221 if (unlikely(get_el2_to_el1_mapping(reg, &el1r, &xlate))) { 222 if (!is_hyp_ctxt(vcpu)) 223 goto memory_write; 224 225 /* 226 * Always store a copy of the write to memory to avoid having 227 * to reverse-translate virtual EL2 system registers for a 228 * non-VHE guest hypervisor. 229 */ 230 __vcpu_sys_reg(vcpu, reg) = val; 231 232 switch (reg) { 233 case CNTHCTL_EL2: 234 /* 235 * If E2H=0, CNHTCTL_EL2 is a pure shadow register. 236 * Otherwise, some of the bits are backed by 237 * CNTKCTL_EL1, while the rest is kept in memory. 238 * Yes, this is fun stuff. 239 */ 240 if (vcpu_el2_e2h_is_set(vcpu)) 241 write_sysreg_el1(val, SYS_CNTKCTL); 242 return; 243 } 244 245 /* No EL1 counterpart? We're done here.? */ 246 if (reg == el1r) 247 return; 248 249 if (!vcpu_el2_e2h_is_set(vcpu) && xlate) 250 val = xlate(val); 251 252 /* Redirect this to the EL1 version of the register. */ 253 WARN_ON(!__vcpu_write_sys_reg_to_cpu(val, el1r)); 254 return; 255 } 256 257 /* EL1 register can't be on the CPU if the guest is in vEL2. */ 258 if (unlikely(is_hyp_ctxt(vcpu))) 259 goto memory_write; 260 261 if (__vcpu_write_sys_reg_to_cpu(val, reg)) 262 return; 263 264 memory_write: 265 __vcpu_sys_reg(vcpu, reg) = val; 266 } 267 268 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */ 269 #define CSSELR_MAX 14 270 271 /* 272 * Returns the minimum line size for the selected cache, expressed as 273 * Log2(bytes). 274 */ 275 static u8 get_min_cache_line_size(bool icache) 276 { 277 u64 ctr = read_sanitised_ftr_reg(SYS_CTR_EL0); 278 u8 field; 279 280 if (icache) 281 field = SYS_FIELD_GET(CTR_EL0, IminLine, ctr); 282 else 283 field = SYS_FIELD_GET(CTR_EL0, DminLine, ctr); 284 285 /* 286 * Cache line size is represented as Log2(words) in CTR_EL0. 287 * Log2(bytes) can be derived with the following: 288 * 289 * Log2(words) + 2 = Log2(bytes / 4) + 2 290 * = Log2(bytes) - 2 + 2 291 * = Log2(bytes) 292 */ 293 return field + 2; 294 } 295 296 /* Which cache CCSIDR represents depends on CSSELR value. */ 297 static u32 get_ccsidr(struct kvm_vcpu *vcpu, u32 csselr) 298 { 299 u8 line_size; 300 301 if (vcpu->arch.ccsidr) 302 return vcpu->arch.ccsidr[csselr]; 303 304 line_size = get_min_cache_line_size(csselr & CSSELR_EL1_InD); 305 306 /* 307 * Fabricate a CCSIDR value as the overriding value does not exist. 308 * The real CCSIDR value will not be used as it can vary by the 309 * physical CPU which the vcpu currently resides in. 310 * 311 * The line size is determined with get_min_cache_line_size(), which 312 * should be valid for all CPUs even if they have different cache 313 * configuration. 314 * 315 * The associativity bits are cleared, meaning the geometry of all data 316 * and unified caches (which are guaranteed to be PIPT and thus 317 * non-aliasing) are 1 set and 1 way. 318 * Guests should not be doing cache operations by set/way at all, and 319 * for this reason, we trap them and attempt to infer the intent, so 320 * that we can flush the entire guest's address space at the appropriate 321 * time. The exposed geometry minimizes the number of the traps. 322 * [If guests should attempt to infer aliasing properties from the 323 * geometry (which is not permitted by the architecture), they would 324 * only do so for virtually indexed caches.] 325 * 326 * We don't check if the cache level exists as it is allowed to return 327 * an UNKNOWN value if not. 328 */ 329 return SYS_FIELD_PREP(CCSIDR_EL1, LineSize, line_size - 4); 330 } 331 332 static int set_ccsidr(struct kvm_vcpu *vcpu, u32 csselr, u32 val) 333 { 334 u8 line_size = FIELD_GET(CCSIDR_EL1_LineSize, val) + 4; 335 u32 *ccsidr = vcpu->arch.ccsidr; 336 u32 i; 337 338 if ((val & CCSIDR_EL1_RES0) || 339 line_size < get_min_cache_line_size(csselr & CSSELR_EL1_InD)) 340 return -EINVAL; 341 342 if (!ccsidr) { 343 if (val == get_ccsidr(vcpu, csselr)) 344 return 0; 345 346 ccsidr = kmalloc_array(CSSELR_MAX, sizeof(u32), GFP_KERNEL_ACCOUNT); 347 if (!ccsidr) 348 return -ENOMEM; 349 350 for (i = 0; i < CSSELR_MAX; i++) 351 ccsidr[i] = get_ccsidr(vcpu, i); 352 353 vcpu->arch.ccsidr = ccsidr; 354 } 355 356 ccsidr[csselr] = val; 357 358 return 0; 359 } 360 361 static bool access_rw(struct kvm_vcpu *vcpu, 362 struct sys_reg_params *p, 363 const struct sys_reg_desc *r) 364 { 365 if (p->is_write) 366 vcpu_write_sys_reg(vcpu, p->regval, r->reg); 367 else 368 p->regval = vcpu_read_sys_reg(vcpu, r->reg); 369 370 return true; 371 } 372 373 /* 374 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized). 375 */ 376 static bool access_dcsw(struct kvm_vcpu *vcpu, 377 struct sys_reg_params *p, 378 const struct sys_reg_desc *r) 379 { 380 if (!p->is_write) 381 return read_from_write_only(vcpu, p, r); 382 383 /* 384 * Only track S/W ops if we don't have FWB. It still indicates 385 * that the guest is a bit broken (S/W operations should only 386 * be done by firmware, knowing that there is only a single 387 * CPU left in the system, and certainly not from non-secure 388 * software). 389 */ 390 if (!cpus_have_final_cap(ARM64_HAS_STAGE2_FWB)) 391 kvm_set_way_flush(vcpu); 392 393 return true; 394 } 395 396 static bool access_dcgsw(struct kvm_vcpu *vcpu, 397 struct sys_reg_params *p, 398 const struct sys_reg_desc *r) 399 { 400 if (!kvm_has_mte(vcpu->kvm)) 401 return undef_access(vcpu, p, r); 402 403 /* Treat MTE S/W ops as we treat the classic ones: with contempt */ 404 return access_dcsw(vcpu, p, r); 405 } 406 407 static void get_access_mask(const struct sys_reg_desc *r, u64 *mask, u64 *shift) 408 { 409 switch (r->aarch32_map) { 410 case AA32_LO: 411 *mask = GENMASK_ULL(31, 0); 412 *shift = 0; 413 break; 414 case AA32_HI: 415 *mask = GENMASK_ULL(63, 32); 416 *shift = 32; 417 break; 418 default: 419 *mask = GENMASK_ULL(63, 0); 420 *shift = 0; 421 break; 422 } 423 } 424 425 /* 426 * Generic accessor for VM registers. Only called as long as HCR_TVM 427 * is set. If the guest enables the MMU, we stop trapping the VM 428 * sys_regs and leave it in complete control of the caches. 429 */ 430 static bool access_vm_reg(struct kvm_vcpu *vcpu, 431 struct sys_reg_params *p, 432 const struct sys_reg_desc *r) 433 { 434 bool was_enabled = vcpu_has_cache_enabled(vcpu); 435 u64 val, mask, shift; 436 437 BUG_ON(!p->is_write); 438 439 get_access_mask(r, &mask, &shift); 440 441 if (~mask) { 442 val = vcpu_read_sys_reg(vcpu, r->reg); 443 val &= ~mask; 444 } else { 445 val = 0; 446 } 447 448 val |= (p->regval & (mask >> shift)) << shift; 449 vcpu_write_sys_reg(vcpu, val, r->reg); 450 451 kvm_toggle_cache(vcpu, was_enabled); 452 return true; 453 } 454 455 static bool access_actlr(struct kvm_vcpu *vcpu, 456 struct sys_reg_params *p, 457 const struct sys_reg_desc *r) 458 { 459 u64 mask, shift; 460 461 if (p->is_write) 462 return ignore_write(vcpu, p); 463 464 get_access_mask(r, &mask, &shift); 465 p->regval = (vcpu_read_sys_reg(vcpu, r->reg) & mask) >> shift; 466 467 return true; 468 } 469 470 /* 471 * Trap handler for the GICv3 SGI generation system register. 472 * Forward the request to the VGIC emulation. 473 * The cp15_64 code makes sure this automatically works 474 * for both AArch64 and AArch32 accesses. 475 */ 476 static bool access_gic_sgi(struct kvm_vcpu *vcpu, 477 struct sys_reg_params *p, 478 const struct sys_reg_desc *r) 479 { 480 bool g1; 481 482 if (!kvm_has_gicv3(vcpu->kvm)) 483 return undef_access(vcpu, p, r); 484 485 if (!p->is_write) 486 return read_from_write_only(vcpu, p, r); 487 488 /* 489 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates 490 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group, 491 * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively 492 * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure 493 * group. 494 */ 495 if (p->Op0 == 0) { /* AArch32 */ 496 switch (p->Op1) { 497 default: /* Keep GCC quiet */ 498 case 0: /* ICC_SGI1R */ 499 g1 = true; 500 break; 501 case 1: /* ICC_ASGI1R */ 502 case 2: /* ICC_SGI0R */ 503 g1 = false; 504 break; 505 } 506 } else { /* AArch64 */ 507 switch (p->Op2) { 508 default: /* Keep GCC quiet */ 509 case 5: /* ICC_SGI1R_EL1 */ 510 g1 = true; 511 break; 512 case 6: /* ICC_ASGI1R_EL1 */ 513 case 7: /* ICC_SGI0R_EL1 */ 514 g1 = false; 515 break; 516 } 517 } 518 519 vgic_v3_dispatch_sgi(vcpu, p->regval, g1); 520 521 return true; 522 } 523 524 static bool access_gic_sre(struct kvm_vcpu *vcpu, 525 struct sys_reg_params *p, 526 const struct sys_reg_desc *r) 527 { 528 if (!kvm_has_gicv3(vcpu->kvm)) 529 return undef_access(vcpu, p, r); 530 531 if (p->is_write) 532 return ignore_write(vcpu, p); 533 534 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre; 535 return true; 536 } 537 538 static bool trap_raz_wi(struct kvm_vcpu *vcpu, 539 struct sys_reg_params *p, 540 const struct sys_reg_desc *r) 541 { 542 if (p->is_write) 543 return ignore_write(vcpu, p); 544 else 545 return read_zero(vcpu, p); 546 } 547 548 /* 549 * ARMv8.1 mandates at least a trivial LORegion implementation, where all the 550 * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0 551 * system, these registers should UNDEF. LORID_EL1 being a RO register, we 552 * treat it separately. 553 */ 554 static bool trap_loregion(struct kvm_vcpu *vcpu, 555 struct sys_reg_params *p, 556 const struct sys_reg_desc *r) 557 { 558 u32 sr = reg_to_encoding(r); 559 560 if (!kvm_has_feat(vcpu->kvm, ID_AA64MMFR1_EL1, LO, IMP)) 561 return undef_access(vcpu, p, r); 562 563 if (p->is_write && sr == SYS_LORID_EL1) 564 return write_to_read_only(vcpu, p, r); 565 566 return trap_raz_wi(vcpu, p, r); 567 } 568 569 static bool trap_oslar_el1(struct kvm_vcpu *vcpu, 570 struct sys_reg_params *p, 571 const struct sys_reg_desc *r) 572 { 573 u64 oslsr; 574 575 if (!p->is_write) 576 return read_from_write_only(vcpu, p, r); 577 578 /* Forward the OSLK bit to OSLSR */ 579 oslsr = __vcpu_sys_reg(vcpu, OSLSR_EL1) & ~OSLSR_EL1_OSLK; 580 if (p->regval & OSLAR_EL1_OSLK) 581 oslsr |= OSLSR_EL1_OSLK; 582 583 __vcpu_sys_reg(vcpu, OSLSR_EL1) = oslsr; 584 return true; 585 } 586 587 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu, 588 struct sys_reg_params *p, 589 const struct sys_reg_desc *r) 590 { 591 if (p->is_write) 592 return write_to_read_only(vcpu, p, r); 593 594 p->regval = __vcpu_sys_reg(vcpu, r->reg); 595 return true; 596 } 597 598 static int set_oslsr_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 599 u64 val) 600 { 601 /* 602 * The only modifiable bit is the OSLK bit. Refuse the write if 603 * userspace attempts to change any other bit in the register. 604 */ 605 if ((val ^ rd->val) & ~OSLSR_EL1_OSLK) 606 return -EINVAL; 607 608 __vcpu_sys_reg(vcpu, rd->reg) = val; 609 return 0; 610 } 611 612 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu, 613 struct sys_reg_params *p, 614 const struct sys_reg_desc *r) 615 { 616 if (p->is_write) { 617 return ignore_write(vcpu, p); 618 } else { 619 p->regval = read_sysreg(dbgauthstatus_el1); 620 return true; 621 } 622 } 623 624 /* 625 * We want to avoid world-switching all the DBG registers all the 626 * time: 627 * 628 * - If we've touched any debug register, it is likely that we're 629 * going to touch more of them. It then makes sense to disable the 630 * traps and start doing the save/restore dance 631 * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is 632 * then mandatory to save/restore the registers, as the guest 633 * depends on them. 634 * 635 * For this, we use a DIRTY bit, indicating the guest has modified the 636 * debug registers, used as follow: 637 * 638 * On guest entry: 639 * - If the dirty bit is set (because we're coming back from trapping), 640 * disable the traps, save host registers, restore guest registers. 641 * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), 642 * set the dirty bit, disable the traps, save host registers, 643 * restore guest registers. 644 * - Otherwise, enable the traps 645 * 646 * On guest exit: 647 * - If the dirty bit is set, save guest registers, restore host 648 * registers and clear the dirty bit. This ensure that the host can 649 * now use the debug registers. 650 */ 651 static bool trap_debug_regs(struct kvm_vcpu *vcpu, 652 struct sys_reg_params *p, 653 const struct sys_reg_desc *r) 654 { 655 access_rw(vcpu, p, r); 656 if (p->is_write) 657 vcpu_set_flag(vcpu, DEBUG_DIRTY); 658 659 trace_trap_reg(__func__, r->reg, p->is_write, p->regval); 660 661 return true; 662 } 663 664 /* 665 * reg_to_dbg/dbg_to_reg 666 * 667 * A 32 bit write to a debug register leave top bits alone 668 * A 32 bit read from a debug register only returns the bottom bits 669 * 670 * All writes will set the DEBUG_DIRTY flag to ensure the hyp code 671 * switches between host and guest values in future. 672 */ 673 static void reg_to_dbg(struct kvm_vcpu *vcpu, 674 struct sys_reg_params *p, 675 const struct sys_reg_desc *rd, 676 u64 *dbg_reg) 677 { 678 u64 mask, shift, val; 679 680 get_access_mask(rd, &mask, &shift); 681 682 val = *dbg_reg; 683 val &= ~mask; 684 val |= (p->regval & (mask >> shift)) << shift; 685 *dbg_reg = val; 686 687 vcpu_set_flag(vcpu, DEBUG_DIRTY); 688 } 689 690 static void dbg_to_reg(struct kvm_vcpu *vcpu, 691 struct sys_reg_params *p, 692 const struct sys_reg_desc *rd, 693 u64 *dbg_reg) 694 { 695 u64 mask, shift; 696 697 get_access_mask(rd, &mask, &shift); 698 p->regval = (*dbg_reg & mask) >> shift; 699 } 700 701 static bool trap_bvr(struct kvm_vcpu *vcpu, 702 struct sys_reg_params *p, 703 const struct sys_reg_desc *rd) 704 { 705 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm]; 706 707 if (p->is_write) 708 reg_to_dbg(vcpu, p, rd, dbg_reg); 709 else 710 dbg_to_reg(vcpu, p, rd, dbg_reg); 711 712 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); 713 714 return true; 715 } 716 717 static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 718 u64 val) 719 { 720 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = val; 721 return 0; 722 } 723 724 static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 725 u64 *val) 726 { 727 *val = vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm]; 728 return 0; 729 } 730 731 static u64 reset_bvr(struct kvm_vcpu *vcpu, 732 const struct sys_reg_desc *rd) 733 { 734 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = rd->val; 735 return rd->val; 736 } 737 738 static bool trap_bcr(struct kvm_vcpu *vcpu, 739 struct sys_reg_params *p, 740 const struct sys_reg_desc *rd) 741 { 742 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm]; 743 744 if (p->is_write) 745 reg_to_dbg(vcpu, p, rd, dbg_reg); 746 else 747 dbg_to_reg(vcpu, p, rd, dbg_reg); 748 749 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); 750 751 return true; 752 } 753 754 static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 755 u64 val) 756 { 757 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = val; 758 return 0; 759 } 760 761 static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 762 u64 *val) 763 { 764 *val = vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm]; 765 return 0; 766 } 767 768 static u64 reset_bcr(struct kvm_vcpu *vcpu, 769 const struct sys_reg_desc *rd) 770 { 771 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = rd->val; 772 return rd->val; 773 } 774 775 static bool trap_wvr(struct kvm_vcpu *vcpu, 776 struct sys_reg_params *p, 777 const struct sys_reg_desc *rd) 778 { 779 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]; 780 781 if (p->is_write) 782 reg_to_dbg(vcpu, p, rd, dbg_reg); 783 else 784 dbg_to_reg(vcpu, p, rd, dbg_reg); 785 786 trace_trap_reg(__func__, rd->CRm, p->is_write, 787 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]); 788 789 return true; 790 } 791 792 static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 793 u64 val) 794 { 795 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = val; 796 return 0; 797 } 798 799 static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 800 u64 *val) 801 { 802 *val = vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]; 803 return 0; 804 } 805 806 static u64 reset_wvr(struct kvm_vcpu *vcpu, 807 const struct sys_reg_desc *rd) 808 { 809 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = rd->val; 810 return rd->val; 811 } 812 813 static bool trap_wcr(struct kvm_vcpu *vcpu, 814 struct sys_reg_params *p, 815 const struct sys_reg_desc *rd) 816 { 817 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm]; 818 819 if (p->is_write) 820 reg_to_dbg(vcpu, p, rd, dbg_reg); 821 else 822 dbg_to_reg(vcpu, p, rd, dbg_reg); 823 824 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); 825 826 return true; 827 } 828 829 static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 830 u64 val) 831 { 832 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = val; 833 return 0; 834 } 835 836 static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 837 u64 *val) 838 { 839 *val = vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm]; 840 return 0; 841 } 842 843 static u64 reset_wcr(struct kvm_vcpu *vcpu, 844 const struct sys_reg_desc *rd) 845 { 846 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = rd->val; 847 return rd->val; 848 } 849 850 static u64 reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 851 { 852 u64 amair = read_sysreg(amair_el1); 853 vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1); 854 return amair; 855 } 856 857 static u64 reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 858 { 859 u64 actlr = read_sysreg(actlr_el1); 860 vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1); 861 return actlr; 862 } 863 864 static u64 reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 865 { 866 u64 mpidr; 867 868 /* 869 * Map the vcpu_id into the first three affinity level fields of 870 * the MPIDR. We limit the number of VCPUs in level 0 due to a 871 * limitation to 16 CPUs in that level in the ICC_SGIxR registers 872 * of the GICv3 to be able to address each CPU directly when 873 * sending IPIs. 874 */ 875 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0); 876 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1); 877 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2); 878 mpidr |= (1ULL << 31); 879 vcpu_write_sys_reg(vcpu, mpidr, MPIDR_EL1); 880 881 return mpidr; 882 } 883 884 static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu, 885 const struct sys_reg_desc *r) 886 { 887 if (kvm_vcpu_has_pmu(vcpu)) 888 return 0; 889 890 return REG_HIDDEN; 891 } 892 893 static u64 reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 894 { 895 u64 mask = BIT(ARMV8_PMU_CYCLE_IDX); 896 u8 n = vcpu->kvm->arch.pmcr_n; 897 898 if (n) 899 mask |= GENMASK(n - 1, 0); 900 901 reset_unknown(vcpu, r); 902 __vcpu_sys_reg(vcpu, r->reg) &= mask; 903 904 return __vcpu_sys_reg(vcpu, r->reg); 905 } 906 907 static u64 reset_pmevcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 908 { 909 reset_unknown(vcpu, r); 910 __vcpu_sys_reg(vcpu, r->reg) &= GENMASK(31, 0); 911 912 return __vcpu_sys_reg(vcpu, r->reg); 913 } 914 915 static u64 reset_pmevtyper(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 916 { 917 /* This thing will UNDEF, who cares about the reset value? */ 918 if (!kvm_vcpu_has_pmu(vcpu)) 919 return 0; 920 921 reset_unknown(vcpu, r); 922 __vcpu_sys_reg(vcpu, r->reg) &= kvm_pmu_evtyper_mask(vcpu->kvm); 923 924 return __vcpu_sys_reg(vcpu, r->reg); 925 } 926 927 static u64 reset_pmselr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 928 { 929 reset_unknown(vcpu, r); 930 __vcpu_sys_reg(vcpu, r->reg) &= PMSELR_EL0_SEL_MASK; 931 932 return __vcpu_sys_reg(vcpu, r->reg); 933 } 934 935 static u64 reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 936 { 937 u64 pmcr = 0; 938 939 if (!kvm_supports_32bit_el0()) 940 pmcr |= ARMV8_PMU_PMCR_LC; 941 942 /* 943 * The value of PMCR.N field is included when the 944 * vCPU register is read via kvm_vcpu_read_pmcr(). 945 */ 946 __vcpu_sys_reg(vcpu, r->reg) = pmcr; 947 948 return __vcpu_sys_reg(vcpu, r->reg); 949 } 950 951 static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags) 952 { 953 u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0); 954 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu); 955 956 if (!enabled) 957 kvm_inject_undefined(vcpu); 958 959 return !enabled; 960 } 961 962 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu) 963 { 964 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN); 965 } 966 967 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu) 968 { 969 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN); 970 } 971 972 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu) 973 { 974 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN); 975 } 976 977 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu) 978 { 979 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN); 980 } 981 982 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 983 const struct sys_reg_desc *r) 984 { 985 u64 val; 986 987 if (pmu_access_el0_disabled(vcpu)) 988 return false; 989 990 if (p->is_write) { 991 /* 992 * Only update writeable bits of PMCR (continuing into 993 * kvm_pmu_handle_pmcr() as well) 994 */ 995 val = kvm_vcpu_read_pmcr(vcpu); 996 val &= ~ARMV8_PMU_PMCR_MASK; 997 val |= p->regval & ARMV8_PMU_PMCR_MASK; 998 if (!kvm_supports_32bit_el0()) 999 val |= ARMV8_PMU_PMCR_LC; 1000 kvm_pmu_handle_pmcr(vcpu, val); 1001 } else { 1002 /* PMCR.P & PMCR.C are RAZ */ 1003 val = kvm_vcpu_read_pmcr(vcpu) 1004 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C); 1005 p->regval = val; 1006 } 1007 1008 return true; 1009 } 1010 1011 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1012 const struct sys_reg_desc *r) 1013 { 1014 if (pmu_access_event_counter_el0_disabled(vcpu)) 1015 return false; 1016 1017 if (p->is_write) 1018 __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval; 1019 else 1020 /* return PMSELR.SEL field */ 1021 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0) 1022 & PMSELR_EL0_SEL_MASK; 1023 1024 return true; 1025 } 1026 1027 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1028 const struct sys_reg_desc *r) 1029 { 1030 u64 pmceid, mask, shift; 1031 1032 BUG_ON(p->is_write); 1033 1034 if (pmu_access_el0_disabled(vcpu)) 1035 return false; 1036 1037 get_access_mask(r, &mask, &shift); 1038 1039 pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1)); 1040 pmceid &= mask; 1041 pmceid >>= shift; 1042 1043 p->regval = pmceid; 1044 1045 return true; 1046 } 1047 1048 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx) 1049 { 1050 u64 pmcr, val; 1051 1052 pmcr = kvm_vcpu_read_pmcr(vcpu); 1053 val = FIELD_GET(ARMV8_PMU_PMCR_N, pmcr); 1054 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) { 1055 kvm_inject_undefined(vcpu); 1056 return false; 1057 } 1058 1059 return true; 1060 } 1061 1062 static int get_pmu_evcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 1063 u64 *val) 1064 { 1065 u64 idx; 1066 1067 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 0) 1068 /* PMCCNTR_EL0 */ 1069 idx = ARMV8_PMU_CYCLE_IDX; 1070 else 1071 /* PMEVCNTRn_EL0 */ 1072 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 1073 1074 *val = kvm_pmu_get_counter_value(vcpu, idx); 1075 return 0; 1076 } 1077 1078 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu, 1079 struct sys_reg_params *p, 1080 const struct sys_reg_desc *r) 1081 { 1082 u64 idx = ~0UL; 1083 1084 if (r->CRn == 9 && r->CRm == 13) { 1085 if (r->Op2 == 2) { 1086 /* PMXEVCNTR_EL0 */ 1087 if (pmu_access_event_counter_el0_disabled(vcpu)) 1088 return false; 1089 1090 idx = SYS_FIELD_GET(PMSELR_EL0, SEL, 1091 __vcpu_sys_reg(vcpu, PMSELR_EL0)); 1092 } else if (r->Op2 == 0) { 1093 /* PMCCNTR_EL0 */ 1094 if (pmu_access_cycle_counter_el0_disabled(vcpu)) 1095 return false; 1096 1097 idx = ARMV8_PMU_CYCLE_IDX; 1098 } 1099 } else if (r->CRn == 0 && r->CRm == 9) { 1100 /* PMCCNTR */ 1101 if (pmu_access_event_counter_el0_disabled(vcpu)) 1102 return false; 1103 1104 idx = ARMV8_PMU_CYCLE_IDX; 1105 } else if (r->CRn == 14 && (r->CRm & 12) == 8) { 1106 /* PMEVCNTRn_EL0 */ 1107 if (pmu_access_event_counter_el0_disabled(vcpu)) 1108 return false; 1109 1110 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 1111 } 1112 1113 /* Catch any decoding mistake */ 1114 WARN_ON(idx == ~0UL); 1115 1116 if (!pmu_counter_idx_valid(vcpu, idx)) 1117 return false; 1118 1119 if (p->is_write) { 1120 if (pmu_access_el0_disabled(vcpu)) 1121 return false; 1122 1123 kvm_pmu_set_counter_value(vcpu, idx, p->regval); 1124 } else { 1125 p->regval = kvm_pmu_get_counter_value(vcpu, idx); 1126 } 1127 1128 return true; 1129 } 1130 1131 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1132 const struct sys_reg_desc *r) 1133 { 1134 u64 idx, reg; 1135 1136 if (pmu_access_el0_disabled(vcpu)) 1137 return false; 1138 1139 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) { 1140 /* PMXEVTYPER_EL0 */ 1141 idx = SYS_FIELD_GET(PMSELR_EL0, SEL, __vcpu_sys_reg(vcpu, PMSELR_EL0)); 1142 reg = PMEVTYPER0_EL0 + idx; 1143 } else if (r->CRn == 14 && (r->CRm & 12) == 12) { 1144 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 1145 if (idx == ARMV8_PMU_CYCLE_IDX) 1146 reg = PMCCFILTR_EL0; 1147 else 1148 /* PMEVTYPERn_EL0 */ 1149 reg = PMEVTYPER0_EL0 + idx; 1150 } else { 1151 BUG(); 1152 } 1153 1154 if (!pmu_counter_idx_valid(vcpu, idx)) 1155 return false; 1156 1157 if (p->is_write) { 1158 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx); 1159 kvm_vcpu_pmu_restore_guest(vcpu); 1160 } else { 1161 p->regval = __vcpu_sys_reg(vcpu, reg); 1162 } 1163 1164 return true; 1165 } 1166 1167 static int set_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 val) 1168 { 1169 bool set; 1170 1171 val &= kvm_pmu_accessible_counter_mask(vcpu); 1172 1173 switch (r->reg) { 1174 case PMOVSSET_EL0: 1175 /* CRm[1] being set indicates a SET register, and CLR otherwise */ 1176 set = r->CRm & 2; 1177 break; 1178 default: 1179 /* Op2[0] being set indicates a SET register, and CLR otherwise */ 1180 set = r->Op2 & 1; 1181 break; 1182 } 1183 1184 if (set) 1185 __vcpu_sys_reg(vcpu, r->reg) |= val; 1186 else 1187 __vcpu_sys_reg(vcpu, r->reg) &= ~val; 1188 1189 return 0; 1190 } 1191 1192 static int get_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 *val) 1193 { 1194 u64 mask = kvm_pmu_accessible_counter_mask(vcpu); 1195 1196 *val = __vcpu_sys_reg(vcpu, r->reg) & mask; 1197 return 0; 1198 } 1199 1200 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1201 const struct sys_reg_desc *r) 1202 { 1203 u64 val, mask; 1204 1205 if (pmu_access_el0_disabled(vcpu)) 1206 return false; 1207 1208 mask = kvm_pmu_accessible_counter_mask(vcpu); 1209 if (p->is_write) { 1210 val = p->regval & mask; 1211 if (r->Op2 & 0x1) 1212 /* accessing PMCNTENSET_EL0 */ 1213 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val; 1214 else 1215 /* accessing PMCNTENCLR_EL0 */ 1216 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val; 1217 1218 kvm_pmu_reprogram_counter_mask(vcpu, val); 1219 } else { 1220 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0); 1221 } 1222 1223 return true; 1224 } 1225 1226 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1227 const struct sys_reg_desc *r) 1228 { 1229 u64 mask = kvm_pmu_accessible_counter_mask(vcpu); 1230 1231 if (check_pmu_access_disabled(vcpu, 0)) 1232 return false; 1233 1234 if (p->is_write) { 1235 u64 val = p->regval & mask; 1236 1237 if (r->Op2 & 0x1) 1238 /* accessing PMINTENSET_EL1 */ 1239 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val; 1240 else 1241 /* accessing PMINTENCLR_EL1 */ 1242 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val; 1243 } else { 1244 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1); 1245 } 1246 1247 return true; 1248 } 1249 1250 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1251 const struct sys_reg_desc *r) 1252 { 1253 u64 mask = kvm_pmu_accessible_counter_mask(vcpu); 1254 1255 if (pmu_access_el0_disabled(vcpu)) 1256 return false; 1257 1258 if (p->is_write) { 1259 if (r->CRm & 0x2) 1260 /* accessing PMOVSSET_EL0 */ 1261 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask); 1262 else 1263 /* accessing PMOVSCLR_EL0 */ 1264 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask); 1265 } else { 1266 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0); 1267 } 1268 1269 return true; 1270 } 1271 1272 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1273 const struct sys_reg_desc *r) 1274 { 1275 u64 mask; 1276 1277 if (!p->is_write) 1278 return read_from_write_only(vcpu, p, r); 1279 1280 if (pmu_write_swinc_el0_disabled(vcpu)) 1281 return false; 1282 1283 mask = kvm_pmu_accessible_counter_mask(vcpu); 1284 kvm_pmu_software_increment(vcpu, p->regval & mask); 1285 return true; 1286 } 1287 1288 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1289 const struct sys_reg_desc *r) 1290 { 1291 if (p->is_write) { 1292 if (!vcpu_mode_priv(vcpu)) 1293 return undef_access(vcpu, p, r); 1294 1295 __vcpu_sys_reg(vcpu, PMUSERENR_EL0) = 1296 p->regval & ARMV8_PMU_USERENR_MASK; 1297 } else { 1298 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0) 1299 & ARMV8_PMU_USERENR_MASK; 1300 } 1301 1302 return true; 1303 } 1304 1305 static int get_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 1306 u64 *val) 1307 { 1308 *val = kvm_vcpu_read_pmcr(vcpu); 1309 return 0; 1310 } 1311 1312 static int set_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 1313 u64 val) 1314 { 1315 u8 new_n = FIELD_GET(ARMV8_PMU_PMCR_N, val); 1316 struct kvm *kvm = vcpu->kvm; 1317 1318 mutex_lock(&kvm->arch.config_lock); 1319 1320 /* 1321 * The vCPU can't have more counters than the PMU hardware 1322 * implements. Ignore this error to maintain compatibility 1323 * with the existing KVM behavior. 1324 */ 1325 if (!kvm_vm_has_ran_once(kvm) && 1326 new_n <= kvm_arm_pmu_get_max_counters(kvm)) 1327 kvm->arch.pmcr_n = new_n; 1328 1329 mutex_unlock(&kvm->arch.config_lock); 1330 1331 /* 1332 * Ignore writes to RES0 bits, read only bits that are cleared on 1333 * vCPU reset, and writable bits that KVM doesn't support yet. 1334 * (i.e. only PMCR.N and bits [7:0] are mutable from userspace) 1335 * The LP bit is RES0 when FEAT_PMUv3p5 is not supported on the vCPU. 1336 * But, we leave the bit as it is here, as the vCPU's PMUver might 1337 * be changed later (NOTE: the bit will be cleared on first vCPU run 1338 * if necessary). 1339 */ 1340 val &= ARMV8_PMU_PMCR_MASK; 1341 1342 /* The LC bit is RES1 when AArch32 is not supported */ 1343 if (!kvm_supports_32bit_el0()) 1344 val |= ARMV8_PMU_PMCR_LC; 1345 1346 __vcpu_sys_reg(vcpu, r->reg) = val; 1347 return 0; 1348 } 1349 1350 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */ 1351 #define DBG_BCR_BVR_WCR_WVR_EL1(n) \ 1352 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \ 1353 trap_bvr, reset_bvr, 0, 0, get_bvr, set_bvr }, \ 1354 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \ 1355 trap_bcr, reset_bcr, 0, 0, get_bcr, set_bcr }, \ 1356 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \ 1357 trap_wvr, reset_wvr, 0, 0, get_wvr, set_wvr }, \ 1358 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \ 1359 trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr } 1360 1361 #define PMU_SYS_REG(name) \ 1362 SYS_DESC(SYS_##name), .reset = reset_pmu_reg, \ 1363 .visibility = pmu_visibility 1364 1365 /* Macro to expand the PMEVCNTRn_EL0 register */ 1366 #define PMU_PMEVCNTR_EL0(n) \ 1367 { PMU_SYS_REG(PMEVCNTRn_EL0(n)), \ 1368 .reset = reset_pmevcntr, .get_user = get_pmu_evcntr, \ 1369 .access = access_pmu_evcntr, .reg = (PMEVCNTR0_EL0 + n), } 1370 1371 /* Macro to expand the PMEVTYPERn_EL0 register */ 1372 #define PMU_PMEVTYPER_EL0(n) \ 1373 { PMU_SYS_REG(PMEVTYPERn_EL0(n)), \ 1374 .reset = reset_pmevtyper, \ 1375 .access = access_pmu_evtyper, .reg = (PMEVTYPER0_EL0 + n), } 1376 1377 /* Macro to expand the AMU counter and type registers*/ 1378 #define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), undef_access } 1379 #define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), undef_access } 1380 #define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), undef_access } 1381 #define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), undef_access } 1382 1383 static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu, 1384 const struct sys_reg_desc *rd) 1385 { 1386 return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN; 1387 } 1388 1389 /* 1390 * If we land here on a PtrAuth access, that is because we didn't 1391 * fixup the access on exit by allowing the PtrAuth sysregs. The only 1392 * way this happens is when the guest does not have PtrAuth support 1393 * enabled. 1394 */ 1395 #define __PTRAUTH_KEY(k) \ 1396 { SYS_DESC(SYS_## k), undef_access, reset_unknown, k, \ 1397 .visibility = ptrauth_visibility} 1398 1399 #define PTRAUTH_KEY(k) \ 1400 __PTRAUTH_KEY(k ## KEYLO_EL1), \ 1401 __PTRAUTH_KEY(k ## KEYHI_EL1) 1402 1403 static bool access_arch_timer(struct kvm_vcpu *vcpu, 1404 struct sys_reg_params *p, 1405 const struct sys_reg_desc *r) 1406 { 1407 enum kvm_arch_timers tmr; 1408 enum kvm_arch_timer_regs treg; 1409 u64 reg = reg_to_encoding(r); 1410 1411 switch (reg) { 1412 case SYS_CNTP_TVAL_EL0: 1413 case SYS_AARCH32_CNTP_TVAL: 1414 tmr = TIMER_PTIMER; 1415 treg = TIMER_REG_TVAL; 1416 break; 1417 case SYS_CNTP_CTL_EL0: 1418 case SYS_AARCH32_CNTP_CTL: 1419 tmr = TIMER_PTIMER; 1420 treg = TIMER_REG_CTL; 1421 break; 1422 case SYS_CNTP_CVAL_EL0: 1423 case SYS_AARCH32_CNTP_CVAL: 1424 tmr = TIMER_PTIMER; 1425 treg = TIMER_REG_CVAL; 1426 break; 1427 case SYS_CNTPCT_EL0: 1428 case SYS_CNTPCTSS_EL0: 1429 case SYS_AARCH32_CNTPCT: 1430 tmr = TIMER_PTIMER; 1431 treg = TIMER_REG_CNT; 1432 break; 1433 default: 1434 print_sys_reg_msg(p, "%s", "Unhandled trapped timer register"); 1435 return undef_access(vcpu, p, r); 1436 } 1437 1438 if (p->is_write) 1439 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval); 1440 else 1441 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg); 1442 1443 return true; 1444 } 1445 1446 static s64 kvm_arm64_ftr_safe_value(u32 id, const struct arm64_ftr_bits *ftrp, 1447 s64 new, s64 cur) 1448 { 1449 struct arm64_ftr_bits kvm_ftr = *ftrp; 1450 1451 /* Some features have different safe value type in KVM than host features */ 1452 switch (id) { 1453 case SYS_ID_AA64DFR0_EL1: 1454 switch (kvm_ftr.shift) { 1455 case ID_AA64DFR0_EL1_PMUVer_SHIFT: 1456 kvm_ftr.type = FTR_LOWER_SAFE; 1457 break; 1458 case ID_AA64DFR0_EL1_DebugVer_SHIFT: 1459 kvm_ftr.type = FTR_LOWER_SAFE; 1460 break; 1461 } 1462 break; 1463 case SYS_ID_DFR0_EL1: 1464 if (kvm_ftr.shift == ID_DFR0_EL1_PerfMon_SHIFT) 1465 kvm_ftr.type = FTR_LOWER_SAFE; 1466 break; 1467 } 1468 1469 return arm64_ftr_safe_value(&kvm_ftr, new, cur); 1470 } 1471 1472 /* 1473 * arm64_check_features() - Check if a feature register value constitutes 1474 * a subset of features indicated by the idreg's KVM sanitised limit. 1475 * 1476 * This function will check if each feature field of @val is the "safe" value 1477 * against idreg's KVM sanitised limit return from reset() callback. 1478 * If a field value in @val is the same as the one in limit, it is always 1479 * considered the safe value regardless For register fields that are not in 1480 * writable, only the value in limit is considered the safe value. 1481 * 1482 * Return: 0 if all the fields are safe. Otherwise, return negative errno. 1483 */ 1484 static int arm64_check_features(struct kvm_vcpu *vcpu, 1485 const struct sys_reg_desc *rd, 1486 u64 val) 1487 { 1488 const struct arm64_ftr_reg *ftr_reg; 1489 const struct arm64_ftr_bits *ftrp = NULL; 1490 u32 id = reg_to_encoding(rd); 1491 u64 writable_mask = rd->val; 1492 u64 limit = rd->reset(vcpu, rd); 1493 u64 mask = 0; 1494 1495 /* 1496 * Hidden and unallocated ID registers may not have a corresponding 1497 * struct arm64_ftr_reg. Of course, if the register is RAZ we know the 1498 * only safe value is 0. 1499 */ 1500 if (sysreg_visible_as_raz(vcpu, rd)) 1501 return val ? -E2BIG : 0; 1502 1503 ftr_reg = get_arm64_ftr_reg(id); 1504 if (!ftr_reg) 1505 return -EINVAL; 1506 1507 ftrp = ftr_reg->ftr_bits; 1508 1509 for (; ftrp && ftrp->width; ftrp++) { 1510 s64 f_val, f_lim, safe_val; 1511 u64 ftr_mask; 1512 1513 ftr_mask = arm64_ftr_mask(ftrp); 1514 if ((ftr_mask & writable_mask) != ftr_mask) 1515 continue; 1516 1517 f_val = arm64_ftr_value(ftrp, val); 1518 f_lim = arm64_ftr_value(ftrp, limit); 1519 mask |= ftr_mask; 1520 1521 if (f_val == f_lim) 1522 safe_val = f_val; 1523 else 1524 safe_val = kvm_arm64_ftr_safe_value(id, ftrp, f_val, f_lim); 1525 1526 if (safe_val != f_val) 1527 return -E2BIG; 1528 } 1529 1530 /* For fields that are not writable, values in limit are the safe values. */ 1531 if ((val & ~mask) != (limit & ~mask)) 1532 return -E2BIG; 1533 1534 return 0; 1535 } 1536 1537 static u8 pmuver_to_perfmon(u8 pmuver) 1538 { 1539 switch (pmuver) { 1540 case ID_AA64DFR0_EL1_PMUVer_IMP: 1541 return ID_DFR0_EL1_PerfMon_PMUv3; 1542 case ID_AA64DFR0_EL1_PMUVer_IMP_DEF: 1543 return ID_DFR0_EL1_PerfMon_IMPDEF; 1544 default: 1545 /* Anything ARMv8.1+ and NI have the same value. For now. */ 1546 return pmuver; 1547 } 1548 } 1549 1550 static u64 sanitise_id_aa64pfr0_el1(const struct kvm_vcpu *vcpu, u64 val); 1551 static u64 sanitise_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, u64 val); 1552 1553 /* Read a sanitised cpufeature ID register by sys_reg_desc */ 1554 static u64 __kvm_read_sanitised_id_reg(const struct kvm_vcpu *vcpu, 1555 const struct sys_reg_desc *r) 1556 { 1557 u32 id = reg_to_encoding(r); 1558 u64 val; 1559 1560 if (sysreg_visible_as_raz(vcpu, r)) 1561 return 0; 1562 1563 val = read_sanitised_ftr_reg(id); 1564 1565 switch (id) { 1566 case SYS_ID_AA64DFR0_EL1: 1567 val = sanitise_id_aa64dfr0_el1(vcpu, val); 1568 break; 1569 case SYS_ID_AA64PFR0_EL1: 1570 val = sanitise_id_aa64pfr0_el1(vcpu, val); 1571 break; 1572 case SYS_ID_AA64PFR1_EL1: 1573 if (!kvm_has_mte(vcpu->kvm)) 1574 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE); 1575 1576 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_SME); 1577 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_RNDR_trap); 1578 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_NMI); 1579 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE_frac); 1580 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_GCS); 1581 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_THE); 1582 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTEX); 1583 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_DF2); 1584 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_PFAR); 1585 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MPAM_frac); 1586 break; 1587 case SYS_ID_AA64PFR2_EL1: 1588 /* We only expose FPMR */ 1589 val &= ID_AA64PFR2_EL1_FPMR; 1590 break; 1591 case SYS_ID_AA64ISAR1_EL1: 1592 if (!vcpu_has_ptrauth(vcpu)) 1593 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) | 1594 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) | 1595 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) | 1596 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI)); 1597 break; 1598 case SYS_ID_AA64ISAR2_EL1: 1599 if (!vcpu_has_ptrauth(vcpu)) 1600 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) | 1601 ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3)); 1602 if (!cpus_have_final_cap(ARM64_HAS_WFXT)) 1603 val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT); 1604 break; 1605 case SYS_ID_AA64ISAR3_EL1: 1606 val &= ID_AA64ISAR3_EL1_FPRCVT | ID_AA64ISAR3_EL1_FAMINMAX; 1607 break; 1608 case SYS_ID_AA64MMFR2_EL1: 1609 val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK; 1610 break; 1611 case SYS_ID_AA64MMFR3_EL1: 1612 val &= ID_AA64MMFR3_EL1_TCRX | ID_AA64MMFR3_EL1_S1POE | 1613 ID_AA64MMFR3_EL1_S1PIE; 1614 break; 1615 case SYS_ID_MMFR4_EL1: 1616 val &= ~ARM64_FEATURE_MASK(ID_MMFR4_EL1_CCIDX); 1617 break; 1618 } 1619 1620 return val; 1621 } 1622 1623 static u64 kvm_read_sanitised_id_reg(struct kvm_vcpu *vcpu, 1624 const struct sys_reg_desc *r) 1625 { 1626 return __kvm_read_sanitised_id_reg(vcpu, r); 1627 } 1628 1629 static u64 read_id_reg(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 1630 { 1631 return kvm_read_vm_id_reg(vcpu->kvm, reg_to_encoding(r)); 1632 } 1633 1634 static bool is_feature_id_reg(u32 encoding) 1635 { 1636 return (sys_reg_Op0(encoding) == 3 && 1637 (sys_reg_Op1(encoding) < 2 || sys_reg_Op1(encoding) == 3) && 1638 sys_reg_CRn(encoding) == 0 && 1639 sys_reg_CRm(encoding) <= 7); 1640 } 1641 1642 /* 1643 * Return true if the register's (Op0, Op1, CRn, CRm, Op2) is 1644 * (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8, which is the range of ID 1645 * registers KVM maintains on a per-VM basis. 1646 */ 1647 static inline bool is_vm_ftr_id_reg(u32 id) 1648 { 1649 if (id == SYS_CTR_EL0) 1650 return true; 1651 1652 return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 && 1653 sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 && 1654 sys_reg_CRm(id) < 8); 1655 } 1656 1657 static inline bool is_vcpu_ftr_id_reg(u32 id) 1658 { 1659 return is_feature_id_reg(id) && !is_vm_ftr_id_reg(id); 1660 } 1661 1662 static inline bool is_aa32_id_reg(u32 id) 1663 { 1664 return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 && 1665 sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 && 1666 sys_reg_CRm(id) <= 3); 1667 } 1668 1669 static unsigned int id_visibility(const struct kvm_vcpu *vcpu, 1670 const struct sys_reg_desc *r) 1671 { 1672 u32 id = reg_to_encoding(r); 1673 1674 switch (id) { 1675 case SYS_ID_AA64ZFR0_EL1: 1676 if (!vcpu_has_sve(vcpu)) 1677 return REG_RAZ; 1678 break; 1679 } 1680 1681 return 0; 1682 } 1683 1684 static unsigned int aa32_id_visibility(const struct kvm_vcpu *vcpu, 1685 const struct sys_reg_desc *r) 1686 { 1687 /* 1688 * AArch32 ID registers are UNKNOWN if AArch32 isn't implemented at any 1689 * EL. Promote to RAZ/WI in order to guarantee consistency between 1690 * systems. 1691 */ 1692 if (!kvm_supports_32bit_el0()) 1693 return REG_RAZ | REG_USER_WI; 1694 1695 return id_visibility(vcpu, r); 1696 } 1697 1698 static unsigned int raz_visibility(const struct kvm_vcpu *vcpu, 1699 const struct sys_reg_desc *r) 1700 { 1701 return REG_RAZ; 1702 } 1703 1704 /* cpufeature ID register access trap handlers */ 1705 1706 static bool access_id_reg(struct kvm_vcpu *vcpu, 1707 struct sys_reg_params *p, 1708 const struct sys_reg_desc *r) 1709 { 1710 if (p->is_write) 1711 return write_to_read_only(vcpu, p, r); 1712 1713 p->regval = read_id_reg(vcpu, r); 1714 1715 return true; 1716 } 1717 1718 /* Visibility overrides for SVE-specific control registers */ 1719 static unsigned int sve_visibility(const struct kvm_vcpu *vcpu, 1720 const struct sys_reg_desc *rd) 1721 { 1722 if (vcpu_has_sve(vcpu)) 1723 return 0; 1724 1725 return REG_HIDDEN; 1726 } 1727 1728 static unsigned int sme_visibility(const struct kvm_vcpu *vcpu, 1729 const struct sys_reg_desc *rd) 1730 { 1731 if (kvm_has_feat(vcpu->kvm, ID_AA64PFR1_EL1, SME, IMP)) 1732 return 0; 1733 1734 return REG_HIDDEN; 1735 } 1736 1737 static unsigned int fp8_visibility(const struct kvm_vcpu *vcpu, 1738 const struct sys_reg_desc *rd) 1739 { 1740 if (kvm_has_fpmr(vcpu->kvm)) 1741 return 0; 1742 1743 return REG_HIDDEN; 1744 } 1745 1746 static u64 sanitise_id_aa64pfr0_el1(const struct kvm_vcpu *vcpu, u64 val) 1747 { 1748 if (!vcpu_has_sve(vcpu)) 1749 val &= ~ID_AA64PFR0_EL1_SVE_MASK; 1750 1751 /* 1752 * The default is to expose CSV2 == 1 if the HW isn't affected. 1753 * Although this is a per-CPU feature, we make it global because 1754 * asymmetric systems are just a nuisance. 1755 * 1756 * Userspace can override this as long as it doesn't promise 1757 * the impossible. 1758 */ 1759 if (arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED) { 1760 val &= ~ID_AA64PFR0_EL1_CSV2_MASK; 1761 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV2, IMP); 1762 } 1763 if (arm64_get_meltdown_state() == SPECTRE_UNAFFECTED) { 1764 val &= ~ID_AA64PFR0_EL1_CSV3_MASK; 1765 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV3, IMP); 1766 } 1767 1768 if (kvm_vgic_global_state.type == VGIC_V3) { 1769 val &= ~ID_AA64PFR0_EL1_GIC_MASK; 1770 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, GIC, IMP); 1771 } 1772 1773 val &= ~ID_AA64PFR0_EL1_AMU_MASK; 1774 1775 /* 1776 * MPAM is disabled by default as KVM also needs a set of PARTID to 1777 * program the MPAMVPMx_EL2 PARTID remapping registers with. But some 1778 * older kernels let the guest see the ID bit. 1779 */ 1780 val &= ~ID_AA64PFR0_EL1_MPAM_MASK; 1781 1782 return val; 1783 } 1784 1785 #define ID_REG_LIMIT_FIELD_ENUM(val, reg, field, limit) \ 1786 ({ \ 1787 u64 __f_val = FIELD_GET(reg##_##field##_MASK, val); \ 1788 (val) &= ~reg##_##field##_MASK; \ 1789 (val) |= FIELD_PREP(reg##_##field##_MASK, \ 1790 min(__f_val, \ 1791 (u64)SYS_FIELD_VALUE(reg, field, limit))); \ 1792 (val); \ 1793 }) 1794 1795 static u64 sanitise_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, u64 val) 1796 { 1797 val = ID_REG_LIMIT_FIELD_ENUM(val, ID_AA64DFR0_EL1, DebugVer, V8P8); 1798 1799 /* 1800 * Only initialize the PMU version if the vCPU was configured with one. 1801 */ 1802 val &= ~ID_AA64DFR0_EL1_PMUVer_MASK; 1803 if (kvm_vcpu_has_pmu(vcpu)) 1804 val |= SYS_FIELD_PREP(ID_AA64DFR0_EL1, PMUVer, 1805 kvm_arm_pmu_get_pmuver_limit()); 1806 1807 /* Hide SPE from guests */ 1808 val &= ~ID_AA64DFR0_EL1_PMSVer_MASK; 1809 1810 return val; 1811 } 1812 1813 static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, 1814 const struct sys_reg_desc *rd, 1815 u64 val) 1816 { 1817 u8 debugver = SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, val); 1818 u8 pmuver = SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, val); 1819 1820 /* 1821 * Prior to commit 3d0dba5764b9 ("KVM: arm64: PMU: Move the 1822 * ID_AA64DFR0_EL1.PMUver limit to VM creation"), KVM erroneously 1823 * exposed an IMP_DEF PMU to userspace and the guest on systems w/ 1824 * non-architectural PMUs. Of course, PMUv3 is the only game in town for 1825 * PMU virtualization, so the IMP_DEF value was rather user-hostile. 1826 * 1827 * At minimum, we're on the hook to allow values that were given to 1828 * userspace by KVM. Cover our tracks here and replace the IMP_DEF value 1829 * with a more sensible NI. The value of an ID register changing under 1830 * the nose of the guest is unfortunate, but is certainly no more 1831 * surprising than an ill-guided PMU driver poking at impdef system 1832 * registers that end in an UNDEF... 1833 */ 1834 if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF) 1835 val &= ~ID_AA64DFR0_EL1_PMUVer_MASK; 1836 1837 /* 1838 * ID_AA64DFR0_EL1.DebugVer is one of those awkward fields with a 1839 * nonzero minimum safe value. 1840 */ 1841 if (debugver < ID_AA64DFR0_EL1_DebugVer_IMP) 1842 return -EINVAL; 1843 1844 return set_id_reg(vcpu, rd, val); 1845 } 1846 1847 static u64 read_sanitised_id_dfr0_el1(struct kvm_vcpu *vcpu, 1848 const struct sys_reg_desc *rd) 1849 { 1850 u8 perfmon = pmuver_to_perfmon(kvm_arm_pmu_get_pmuver_limit()); 1851 u64 val = read_sanitised_ftr_reg(SYS_ID_DFR0_EL1); 1852 1853 val &= ~ID_DFR0_EL1_PerfMon_MASK; 1854 if (kvm_vcpu_has_pmu(vcpu)) 1855 val |= SYS_FIELD_PREP(ID_DFR0_EL1, PerfMon, perfmon); 1856 1857 val = ID_REG_LIMIT_FIELD_ENUM(val, ID_DFR0_EL1, CopDbg, Debugv8p8); 1858 1859 return val; 1860 } 1861 1862 static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, 1863 const struct sys_reg_desc *rd, 1864 u64 val) 1865 { 1866 u8 perfmon = SYS_FIELD_GET(ID_DFR0_EL1, PerfMon, val); 1867 u8 copdbg = SYS_FIELD_GET(ID_DFR0_EL1, CopDbg, val); 1868 1869 if (perfmon == ID_DFR0_EL1_PerfMon_IMPDEF) { 1870 val &= ~ID_DFR0_EL1_PerfMon_MASK; 1871 perfmon = 0; 1872 } 1873 1874 /* 1875 * Allow DFR0_EL1.PerfMon to be set from userspace as long as 1876 * it doesn't promise more than what the HW gives us on the 1877 * AArch64 side (as everything is emulated with that), and 1878 * that this is a PMUv3. 1879 */ 1880 if (perfmon != 0 && perfmon < ID_DFR0_EL1_PerfMon_PMUv3) 1881 return -EINVAL; 1882 1883 if (copdbg < ID_DFR0_EL1_CopDbg_Armv8) 1884 return -EINVAL; 1885 1886 return set_id_reg(vcpu, rd, val); 1887 } 1888 1889 static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, 1890 const struct sys_reg_desc *rd, u64 user_val) 1891 { 1892 u64 hw_val = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1893 u64 mpam_mask = ID_AA64PFR0_EL1_MPAM_MASK; 1894 1895 /* 1896 * Commit 011e5f5bf529f ("arm64/cpufeature: Add remaining feature bits 1897 * in ID_AA64PFR0 register") exposed the MPAM field of AA64PFR0_EL1 to 1898 * guests, but didn't add trap handling. KVM doesn't support MPAM and 1899 * always returns an UNDEF for these registers. The guest must see 0 1900 * for this field. 1901 * 1902 * But KVM must also accept values from user-space that were provided 1903 * by KVM. On CPUs that support MPAM, permit user-space to write 1904 * the sanitizied value to ID_AA64PFR0_EL1.MPAM, but ignore this field. 1905 */ 1906 if ((hw_val & mpam_mask) == (user_val & mpam_mask)) 1907 user_val &= ~ID_AA64PFR0_EL1_MPAM_MASK; 1908 1909 return set_id_reg(vcpu, rd, user_val); 1910 } 1911 1912 static int set_id_aa64pfr1_el1(struct kvm_vcpu *vcpu, 1913 const struct sys_reg_desc *rd, u64 user_val) 1914 { 1915 u64 hw_val = read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1); 1916 u64 mpam_mask = ID_AA64PFR1_EL1_MPAM_frac_MASK; 1917 1918 /* See set_id_aa64pfr0_el1 for comment about MPAM */ 1919 if ((hw_val & mpam_mask) == (user_val & mpam_mask)) 1920 user_val &= ~ID_AA64PFR1_EL1_MPAM_frac_MASK; 1921 1922 return set_id_reg(vcpu, rd, user_val); 1923 } 1924 1925 static int set_ctr_el0(struct kvm_vcpu *vcpu, 1926 const struct sys_reg_desc *rd, u64 user_val) 1927 { 1928 u8 user_L1Ip = SYS_FIELD_GET(CTR_EL0, L1Ip, user_val); 1929 1930 /* 1931 * Both AIVIVT (0b01) and VPIPT (0b00) are documented as reserved. 1932 * Hence only allow to set VIPT(0b10) or PIPT(0b11) for L1Ip based 1933 * on what hardware reports. 1934 * 1935 * Using a VIPT software model on PIPT will lead to over invalidation, 1936 * but still correct. Hence, we can allow downgrading PIPT to VIPT, 1937 * but not the other way around. This is handled via arm64_ftr_safe_value() 1938 * as CTR_EL0 ftr_bits has L1Ip field with type FTR_EXACT and safe value 1939 * set as VIPT. 1940 */ 1941 switch (user_L1Ip) { 1942 case CTR_EL0_L1Ip_RESERVED_VPIPT: 1943 case CTR_EL0_L1Ip_RESERVED_AIVIVT: 1944 return -EINVAL; 1945 case CTR_EL0_L1Ip_VIPT: 1946 case CTR_EL0_L1Ip_PIPT: 1947 return set_id_reg(vcpu, rd, user_val); 1948 default: 1949 return -ENOENT; 1950 } 1951 } 1952 1953 /* 1954 * cpufeature ID register user accessors 1955 * 1956 * For now, these registers are immutable for userspace, so no values 1957 * are stored, and for set_id_reg() we don't allow the effective value 1958 * to be changed. 1959 */ 1960 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1961 u64 *val) 1962 { 1963 /* 1964 * Avoid locking if the VM has already started, as the ID registers are 1965 * guaranteed to be invariant at that point. 1966 */ 1967 if (kvm_vm_has_ran_once(vcpu->kvm)) { 1968 *val = read_id_reg(vcpu, rd); 1969 return 0; 1970 } 1971 1972 mutex_lock(&vcpu->kvm->arch.config_lock); 1973 *val = read_id_reg(vcpu, rd); 1974 mutex_unlock(&vcpu->kvm->arch.config_lock); 1975 1976 return 0; 1977 } 1978 1979 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1980 u64 val) 1981 { 1982 u32 id = reg_to_encoding(rd); 1983 int ret; 1984 1985 mutex_lock(&vcpu->kvm->arch.config_lock); 1986 1987 /* 1988 * Once the VM has started the ID registers are immutable. Reject any 1989 * write that does not match the final register value. 1990 */ 1991 if (kvm_vm_has_ran_once(vcpu->kvm)) { 1992 if (val != read_id_reg(vcpu, rd)) 1993 ret = -EBUSY; 1994 else 1995 ret = 0; 1996 1997 mutex_unlock(&vcpu->kvm->arch.config_lock); 1998 return ret; 1999 } 2000 2001 ret = arm64_check_features(vcpu, rd, val); 2002 if (!ret) 2003 kvm_set_vm_id_reg(vcpu->kvm, id, val); 2004 2005 mutex_unlock(&vcpu->kvm->arch.config_lock); 2006 2007 /* 2008 * arm64_check_features() returns -E2BIG to indicate the register's 2009 * feature set is a superset of the maximally-allowed register value. 2010 * While it would be nice to precisely describe this to userspace, the 2011 * existing UAPI for KVM_SET_ONE_REG has it that invalid register 2012 * writes return -EINVAL. 2013 */ 2014 if (ret == -E2BIG) 2015 ret = -EINVAL; 2016 return ret; 2017 } 2018 2019 void kvm_set_vm_id_reg(struct kvm *kvm, u32 reg, u64 val) 2020 { 2021 u64 *p = __vm_id_reg(&kvm->arch, reg); 2022 2023 lockdep_assert_held(&kvm->arch.config_lock); 2024 2025 if (KVM_BUG_ON(kvm_vm_has_ran_once(kvm) || !p, kvm)) 2026 return; 2027 2028 *p = val; 2029 } 2030 2031 static int get_raz_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 2032 u64 *val) 2033 { 2034 *val = 0; 2035 return 0; 2036 } 2037 2038 static int set_wi_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 2039 u64 val) 2040 { 2041 return 0; 2042 } 2043 2044 static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2045 const struct sys_reg_desc *r) 2046 { 2047 if (p->is_write) 2048 return write_to_read_only(vcpu, p, r); 2049 2050 p->regval = kvm_read_vm_id_reg(vcpu->kvm, SYS_CTR_EL0); 2051 return true; 2052 } 2053 2054 static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2055 const struct sys_reg_desc *r) 2056 { 2057 if (p->is_write) 2058 return write_to_read_only(vcpu, p, r); 2059 2060 p->regval = __vcpu_sys_reg(vcpu, r->reg); 2061 return true; 2062 } 2063 2064 /* 2065 * Fabricate a CLIDR_EL1 value instead of using the real value, which can vary 2066 * by the physical CPU which the vcpu currently resides in. 2067 */ 2068 static u64 reset_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 2069 { 2070 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0); 2071 u64 clidr; 2072 u8 loc; 2073 2074 if ((ctr_el0 & CTR_EL0_IDC)) { 2075 /* 2076 * Data cache clean to the PoU is not required so LoUU and LoUIS 2077 * will not be set and a unified cache, which will be marked as 2078 * LoC, will be added. 2079 * 2080 * If not DIC, let the unified cache L2 so that an instruction 2081 * cache can be added as L1 later. 2082 */ 2083 loc = (ctr_el0 & CTR_EL0_DIC) ? 1 : 2; 2084 clidr = CACHE_TYPE_UNIFIED << CLIDR_CTYPE_SHIFT(loc); 2085 } else { 2086 /* 2087 * Data cache clean to the PoU is required so let L1 have a data 2088 * cache and mark it as LoUU and LoUIS. As L1 has a data cache, 2089 * it can be marked as LoC too. 2090 */ 2091 loc = 1; 2092 clidr = 1 << CLIDR_LOUU_SHIFT; 2093 clidr |= 1 << CLIDR_LOUIS_SHIFT; 2094 clidr |= CACHE_TYPE_DATA << CLIDR_CTYPE_SHIFT(1); 2095 } 2096 2097 /* 2098 * Instruction cache invalidation to the PoU is required so let L1 have 2099 * an instruction cache. If L1 already has a data cache, it will be 2100 * CACHE_TYPE_SEPARATE. 2101 */ 2102 if (!(ctr_el0 & CTR_EL0_DIC)) 2103 clidr |= CACHE_TYPE_INST << CLIDR_CTYPE_SHIFT(1); 2104 2105 clidr |= loc << CLIDR_LOC_SHIFT; 2106 2107 /* 2108 * Add tag cache unified to data cache. Allocation tags and data are 2109 * unified in a cache line so that it looks valid even if there is only 2110 * one cache line. 2111 */ 2112 if (kvm_has_mte(vcpu->kvm)) 2113 clidr |= 2ULL << CLIDR_TTYPE_SHIFT(loc); 2114 2115 __vcpu_sys_reg(vcpu, r->reg) = clidr; 2116 2117 return __vcpu_sys_reg(vcpu, r->reg); 2118 } 2119 2120 static int set_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 2121 u64 val) 2122 { 2123 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0); 2124 u64 idc = !CLIDR_LOC(val) || (!CLIDR_LOUIS(val) && !CLIDR_LOUU(val)); 2125 2126 if ((val & CLIDR_EL1_RES0) || (!(ctr_el0 & CTR_EL0_IDC) && idc)) 2127 return -EINVAL; 2128 2129 __vcpu_sys_reg(vcpu, rd->reg) = val; 2130 2131 return 0; 2132 } 2133 2134 static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2135 const struct sys_reg_desc *r) 2136 { 2137 int reg = r->reg; 2138 2139 if (p->is_write) 2140 vcpu_write_sys_reg(vcpu, p->regval, reg); 2141 else 2142 p->regval = vcpu_read_sys_reg(vcpu, reg); 2143 return true; 2144 } 2145 2146 static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2147 const struct sys_reg_desc *r) 2148 { 2149 u32 csselr; 2150 2151 if (p->is_write) 2152 return write_to_read_only(vcpu, p, r); 2153 2154 csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1); 2155 csselr &= CSSELR_EL1_Level | CSSELR_EL1_InD; 2156 if (csselr < CSSELR_MAX) 2157 p->regval = get_ccsidr(vcpu, csselr); 2158 2159 return true; 2160 } 2161 2162 static unsigned int mte_visibility(const struct kvm_vcpu *vcpu, 2163 const struct sys_reg_desc *rd) 2164 { 2165 if (kvm_has_mte(vcpu->kvm)) 2166 return 0; 2167 2168 return REG_HIDDEN; 2169 } 2170 2171 #define MTE_REG(name) { \ 2172 SYS_DESC(SYS_##name), \ 2173 .access = undef_access, \ 2174 .reset = reset_unknown, \ 2175 .reg = name, \ 2176 .visibility = mte_visibility, \ 2177 } 2178 2179 static unsigned int el2_visibility(const struct kvm_vcpu *vcpu, 2180 const struct sys_reg_desc *rd) 2181 { 2182 if (vcpu_has_nv(vcpu)) 2183 return 0; 2184 2185 return REG_HIDDEN; 2186 } 2187 2188 static bool bad_vncr_trap(struct kvm_vcpu *vcpu, 2189 struct sys_reg_params *p, 2190 const struct sys_reg_desc *r) 2191 { 2192 /* 2193 * We really shouldn't be here, and this is likely the result 2194 * of a misconfigured trap, as this register should target the 2195 * VNCR page, and nothing else. 2196 */ 2197 return bad_trap(vcpu, p, r, 2198 "trap of VNCR-backed register"); 2199 } 2200 2201 static bool bad_redir_trap(struct kvm_vcpu *vcpu, 2202 struct sys_reg_params *p, 2203 const struct sys_reg_desc *r) 2204 { 2205 /* 2206 * We really shouldn't be here, and this is likely the result 2207 * of a misconfigured trap, as this register should target the 2208 * corresponding EL1, and nothing else. 2209 */ 2210 return bad_trap(vcpu, p, r, 2211 "trap of EL2 register redirected to EL1"); 2212 } 2213 2214 #define EL2_REG(name, acc, rst, v) { \ 2215 SYS_DESC(SYS_##name), \ 2216 .access = acc, \ 2217 .reset = rst, \ 2218 .reg = name, \ 2219 .visibility = el2_visibility, \ 2220 .val = v, \ 2221 } 2222 2223 #define EL2_REG_FILTERED(name, acc, rst, v, filter) { \ 2224 SYS_DESC(SYS_##name), \ 2225 .access = acc, \ 2226 .reset = rst, \ 2227 .reg = name, \ 2228 .visibility = filter, \ 2229 .val = v, \ 2230 } 2231 2232 #define EL2_REG_VNCR(name, rst, v) EL2_REG(name, bad_vncr_trap, rst, v) 2233 #define EL2_REG_REDIR(name, rst, v) EL2_REG(name, bad_redir_trap, rst, v) 2234 2235 /* 2236 * Since reset() callback and field val are not used for idregs, they will be 2237 * used for specific purposes for idregs. 2238 * The reset() would return KVM sanitised register value. The value would be the 2239 * same as the host kernel sanitised value if there is no KVM sanitisation. 2240 * The val would be used as a mask indicating writable fields for the idreg. 2241 * Only bits with 1 are writable from userspace. This mask might not be 2242 * necessary in the future whenever all ID registers are enabled as writable 2243 * from userspace. 2244 */ 2245 2246 #define ID_DESC(name) \ 2247 SYS_DESC(SYS_##name), \ 2248 .access = access_id_reg, \ 2249 .get_user = get_id_reg \ 2250 2251 /* sys_reg_desc initialiser for known cpufeature ID registers */ 2252 #define ID_SANITISED(name) { \ 2253 ID_DESC(name), \ 2254 .set_user = set_id_reg, \ 2255 .visibility = id_visibility, \ 2256 .reset = kvm_read_sanitised_id_reg, \ 2257 .val = 0, \ 2258 } 2259 2260 /* sys_reg_desc initialiser for known cpufeature ID registers */ 2261 #define AA32_ID_SANITISED(name) { \ 2262 ID_DESC(name), \ 2263 .set_user = set_id_reg, \ 2264 .visibility = aa32_id_visibility, \ 2265 .reset = kvm_read_sanitised_id_reg, \ 2266 .val = 0, \ 2267 } 2268 2269 /* sys_reg_desc initialiser for writable ID registers */ 2270 #define ID_WRITABLE(name, mask) { \ 2271 ID_DESC(name), \ 2272 .set_user = set_id_reg, \ 2273 .visibility = id_visibility, \ 2274 .reset = kvm_read_sanitised_id_reg, \ 2275 .val = mask, \ 2276 } 2277 2278 /* sys_reg_desc initialiser for cpufeature ID registers that need filtering */ 2279 #define ID_FILTERED(sysreg, name, mask) { \ 2280 ID_DESC(sysreg), \ 2281 .set_user = set_##name, \ 2282 .visibility = id_visibility, \ 2283 .reset = kvm_read_sanitised_id_reg, \ 2284 .val = (mask), \ 2285 } 2286 2287 /* 2288 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID 2289 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2 2290 * (1 <= crm < 8, 0 <= Op2 < 8). 2291 */ 2292 #define ID_UNALLOCATED(crm, op2) { \ 2293 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \ 2294 .access = access_id_reg, \ 2295 .get_user = get_id_reg, \ 2296 .set_user = set_id_reg, \ 2297 .visibility = raz_visibility, \ 2298 .reset = kvm_read_sanitised_id_reg, \ 2299 .val = 0, \ 2300 } 2301 2302 /* 2303 * sys_reg_desc initialiser for known ID registers that we hide from guests. 2304 * For now, these are exposed just like unallocated ID regs: they appear 2305 * RAZ for the guest. 2306 */ 2307 #define ID_HIDDEN(name) { \ 2308 ID_DESC(name), \ 2309 .set_user = set_id_reg, \ 2310 .visibility = raz_visibility, \ 2311 .reset = kvm_read_sanitised_id_reg, \ 2312 .val = 0, \ 2313 } 2314 2315 static bool access_sp_el1(struct kvm_vcpu *vcpu, 2316 struct sys_reg_params *p, 2317 const struct sys_reg_desc *r) 2318 { 2319 if (p->is_write) 2320 __vcpu_sys_reg(vcpu, SP_EL1) = p->regval; 2321 else 2322 p->regval = __vcpu_sys_reg(vcpu, SP_EL1); 2323 2324 return true; 2325 } 2326 2327 static bool access_elr(struct kvm_vcpu *vcpu, 2328 struct sys_reg_params *p, 2329 const struct sys_reg_desc *r) 2330 { 2331 if (p->is_write) 2332 vcpu_write_sys_reg(vcpu, p->regval, ELR_EL1); 2333 else 2334 p->regval = vcpu_read_sys_reg(vcpu, ELR_EL1); 2335 2336 return true; 2337 } 2338 2339 static bool access_spsr(struct kvm_vcpu *vcpu, 2340 struct sys_reg_params *p, 2341 const struct sys_reg_desc *r) 2342 { 2343 if (p->is_write) 2344 __vcpu_sys_reg(vcpu, SPSR_EL1) = p->regval; 2345 else 2346 p->regval = __vcpu_sys_reg(vcpu, SPSR_EL1); 2347 2348 return true; 2349 } 2350 2351 static bool access_cntkctl_el12(struct kvm_vcpu *vcpu, 2352 struct sys_reg_params *p, 2353 const struct sys_reg_desc *r) 2354 { 2355 if (p->is_write) 2356 __vcpu_sys_reg(vcpu, CNTKCTL_EL1) = p->regval; 2357 else 2358 p->regval = __vcpu_sys_reg(vcpu, CNTKCTL_EL1); 2359 2360 return true; 2361 } 2362 2363 static u64 reset_hcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 2364 { 2365 u64 val = r->val; 2366 2367 if (!cpus_have_final_cap(ARM64_HAS_HCR_NV1)) 2368 val |= HCR_E2H; 2369 2370 return __vcpu_sys_reg(vcpu, r->reg) = val; 2371 } 2372 2373 static unsigned int __el2_visibility(const struct kvm_vcpu *vcpu, 2374 const struct sys_reg_desc *rd, 2375 unsigned int (*fn)(const struct kvm_vcpu *, 2376 const struct sys_reg_desc *)) 2377 { 2378 return el2_visibility(vcpu, rd) ?: fn(vcpu, rd); 2379 } 2380 2381 static unsigned int sve_el2_visibility(const struct kvm_vcpu *vcpu, 2382 const struct sys_reg_desc *rd) 2383 { 2384 return __el2_visibility(vcpu, rd, sve_visibility); 2385 } 2386 2387 static bool access_zcr_el2(struct kvm_vcpu *vcpu, 2388 struct sys_reg_params *p, 2389 const struct sys_reg_desc *r) 2390 { 2391 unsigned int vq; 2392 2393 if (guest_hyp_sve_traps_enabled(vcpu)) { 2394 kvm_inject_nested_sve_trap(vcpu); 2395 return true; 2396 } 2397 2398 if (!p->is_write) { 2399 p->regval = vcpu_read_sys_reg(vcpu, ZCR_EL2); 2400 return true; 2401 } 2402 2403 vq = SYS_FIELD_GET(ZCR_ELx, LEN, p->regval) + 1; 2404 vq = min(vq, vcpu_sve_max_vq(vcpu)); 2405 vcpu_write_sys_reg(vcpu, vq - 1, ZCR_EL2); 2406 return true; 2407 } 2408 2409 static unsigned int s1poe_visibility(const struct kvm_vcpu *vcpu, 2410 const struct sys_reg_desc *rd) 2411 { 2412 if (kvm_has_s1poe(vcpu->kvm)) 2413 return 0; 2414 2415 return REG_HIDDEN; 2416 } 2417 2418 static unsigned int s1poe_el2_visibility(const struct kvm_vcpu *vcpu, 2419 const struct sys_reg_desc *rd) 2420 { 2421 return __el2_visibility(vcpu, rd, s1poe_visibility); 2422 } 2423 2424 static unsigned int tcr2_visibility(const struct kvm_vcpu *vcpu, 2425 const struct sys_reg_desc *rd) 2426 { 2427 if (kvm_has_tcr2(vcpu->kvm)) 2428 return 0; 2429 2430 return REG_HIDDEN; 2431 } 2432 2433 static unsigned int tcr2_el2_visibility(const struct kvm_vcpu *vcpu, 2434 const struct sys_reg_desc *rd) 2435 { 2436 return __el2_visibility(vcpu, rd, tcr2_visibility); 2437 } 2438 2439 static unsigned int s1pie_visibility(const struct kvm_vcpu *vcpu, 2440 const struct sys_reg_desc *rd) 2441 { 2442 if (kvm_has_s1pie(vcpu->kvm)) 2443 return 0; 2444 2445 return REG_HIDDEN; 2446 } 2447 2448 static unsigned int s1pie_el2_visibility(const struct kvm_vcpu *vcpu, 2449 const struct sys_reg_desc *rd) 2450 { 2451 return __el2_visibility(vcpu, rd, s1pie_visibility); 2452 } 2453 2454 static bool access_mdcr(struct kvm_vcpu *vcpu, 2455 struct sys_reg_params *p, 2456 const struct sys_reg_desc *r) 2457 { 2458 u64 old = __vcpu_sys_reg(vcpu, MDCR_EL2); 2459 2460 if (!access_rw(vcpu, p, r)) 2461 return false; 2462 2463 /* 2464 * Request a reload of the PMU to enable/disable the counters affected 2465 * by HPME. 2466 */ 2467 if ((old ^ __vcpu_sys_reg(vcpu, MDCR_EL2)) & MDCR_EL2_HPME) 2468 kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu); 2469 2470 return true; 2471 } 2472 2473 2474 /* 2475 * Architected system registers. 2476 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2 2477 * 2478 * Debug handling: We do trap most, if not all debug related system 2479 * registers. The implementation is good enough to ensure that a guest 2480 * can use these with minimal performance degradation. The drawback is 2481 * that we don't implement any of the external debug architecture. 2482 * This should be revisited if we ever encounter a more demanding 2483 * guest... 2484 */ 2485 static const struct sys_reg_desc sys_reg_descs[] = { 2486 DBG_BCR_BVR_WCR_WVR_EL1(0), 2487 DBG_BCR_BVR_WCR_WVR_EL1(1), 2488 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 }, 2489 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 }, 2490 DBG_BCR_BVR_WCR_WVR_EL1(2), 2491 DBG_BCR_BVR_WCR_WVR_EL1(3), 2492 DBG_BCR_BVR_WCR_WVR_EL1(4), 2493 DBG_BCR_BVR_WCR_WVR_EL1(5), 2494 DBG_BCR_BVR_WCR_WVR_EL1(6), 2495 DBG_BCR_BVR_WCR_WVR_EL1(7), 2496 DBG_BCR_BVR_WCR_WVR_EL1(8), 2497 DBG_BCR_BVR_WCR_WVR_EL1(9), 2498 DBG_BCR_BVR_WCR_WVR_EL1(10), 2499 DBG_BCR_BVR_WCR_WVR_EL1(11), 2500 DBG_BCR_BVR_WCR_WVR_EL1(12), 2501 DBG_BCR_BVR_WCR_WVR_EL1(13), 2502 DBG_BCR_BVR_WCR_WVR_EL1(14), 2503 DBG_BCR_BVR_WCR_WVR_EL1(15), 2504 2505 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi }, 2506 { SYS_DESC(SYS_OSLAR_EL1), trap_oslar_el1 }, 2507 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1, 2508 OSLSR_EL1_OSLM_IMPLEMENTED, .set_user = set_oslsr_el1, }, 2509 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi }, 2510 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi }, 2511 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi }, 2512 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi }, 2513 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 }, 2514 2515 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi }, 2516 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi }, 2517 // DBGDTR[TR]X_EL0 share the same encoding 2518 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi }, 2519 2520 { SYS_DESC(SYS_DBGVCR32_EL2), undef_access, reset_val, DBGVCR32_EL2, 0 }, 2521 2522 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 }, 2523 2524 /* 2525 * ID regs: all ID_SANITISED() entries here must have corresponding 2526 * entries in arm64_ftr_regs[]. 2527 */ 2528 2529 /* AArch64 mappings of the AArch32 ID registers */ 2530 /* CRm=1 */ 2531 AA32_ID_SANITISED(ID_PFR0_EL1), 2532 AA32_ID_SANITISED(ID_PFR1_EL1), 2533 { SYS_DESC(SYS_ID_DFR0_EL1), 2534 .access = access_id_reg, 2535 .get_user = get_id_reg, 2536 .set_user = set_id_dfr0_el1, 2537 .visibility = aa32_id_visibility, 2538 .reset = read_sanitised_id_dfr0_el1, 2539 .val = ID_DFR0_EL1_PerfMon_MASK | 2540 ID_DFR0_EL1_CopDbg_MASK, }, 2541 ID_HIDDEN(ID_AFR0_EL1), 2542 AA32_ID_SANITISED(ID_MMFR0_EL1), 2543 AA32_ID_SANITISED(ID_MMFR1_EL1), 2544 AA32_ID_SANITISED(ID_MMFR2_EL1), 2545 AA32_ID_SANITISED(ID_MMFR3_EL1), 2546 2547 /* CRm=2 */ 2548 AA32_ID_SANITISED(ID_ISAR0_EL1), 2549 AA32_ID_SANITISED(ID_ISAR1_EL1), 2550 AA32_ID_SANITISED(ID_ISAR2_EL1), 2551 AA32_ID_SANITISED(ID_ISAR3_EL1), 2552 AA32_ID_SANITISED(ID_ISAR4_EL1), 2553 AA32_ID_SANITISED(ID_ISAR5_EL1), 2554 AA32_ID_SANITISED(ID_MMFR4_EL1), 2555 AA32_ID_SANITISED(ID_ISAR6_EL1), 2556 2557 /* CRm=3 */ 2558 AA32_ID_SANITISED(MVFR0_EL1), 2559 AA32_ID_SANITISED(MVFR1_EL1), 2560 AA32_ID_SANITISED(MVFR2_EL1), 2561 ID_UNALLOCATED(3,3), 2562 AA32_ID_SANITISED(ID_PFR2_EL1), 2563 ID_HIDDEN(ID_DFR1_EL1), 2564 AA32_ID_SANITISED(ID_MMFR5_EL1), 2565 ID_UNALLOCATED(3,7), 2566 2567 /* AArch64 ID registers */ 2568 /* CRm=4 */ 2569 ID_FILTERED(ID_AA64PFR0_EL1, id_aa64pfr0_el1, 2570 ~(ID_AA64PFR0_EL1_AMU | 2571 ID_AA64PFR0_EL1_MPAM | 2572 ID_AA64PFR0_EL1_SVE | 2573 ID_AA64PFR0_EL1_RAS | 2574 ID_AA64PFR0_EL1_AdvSIMD | 2575 ID_AA64PFR0_EL1_FP)), 2576 ID_FILTERED(ID_AA64PFR1_EL1, id_aa64pfr1_el1, 2577 ~(ID_AA64PFR1_EL1_PFAR | 2578 ID_AA64PFR1_EL1_DF2 | 2579 ID_AA64PFR1_EL1_MTEX | 2580 ID_AA64PFR1_EL1_THE | 2581 ID_AA64PFR1_EL1_GCS | 2582 ID_AA64PFR1_EL1_MTE_frac | 2583 ID_AA64PFR1_EL1_NMI | 2584 ID_AA64PFR1_EL1_RNDR_trap | 2585 ID_AA64PFR1_EL1_SME | 2586 ID_AA64PFR1_EL1_RES0 | 2587 ID_AA64PFR1_EL1_MPAM_frac | 2588 ID_AA64PFR1_EL1_RAS_frac | 2589 ID_AA64PFR1_EL1_MTE)), 2590 ID_WRITABLE(ID_AA64PFR2_EL1, ID_AA64PFR2_EL1_FPMR), 2591 ID_UNALLOCATED(4,3), 2592 ID_WRITABLE(ID_AA64ZFR0_EL1, ~ID_AA64ZFR0_EL1_RES0), 2593 ID_HIDDEN(ID_AA64SMFR0_EL1), 2594 ID_UNALLOCATED(4,6), 2595 ID_WRITABLE(ID_AA64FPFR0_EL1, ~ID_AA64FPFR0_EL1_RES0), 2596 2597 /* CRm=5 */ 2598 /* 2599 * Prior to FEAT_Debugv8.9, the architecture defines context-aware 2600 * breakpoints (CTX_CMPs) as the highest numbered breakpoints (BRPs). 2601 * KVM does not trap + emulate the breakpoint registers, and as such 2602 * cannot support a layout that misaligns with the underlying hardware. 2603 * While it may be possible to describe a subset that aligns with 2604 * hardware, just prevent changes to BRPs and CTX_CMPs altogether for 2605 * simplicity. 2606 * 2607 * See DDI0487K.a, section D2.8.3 Breakpoint types and linking 2608 * of breakpoints for more details. 2609 */ 2610 ID_FILTERED(ID_AA64DFR0_EL1, id_aa64dfr0_el1, 2611 ID_AA64DFR0_EL1_DoubleLock_MASK | 2612 ID_AA64DFR0_EL1_WRPs_MASK | 2613 ID_AA64DFR0_EL1_PMUVer_MASK | 2614 ID_AA64DFR0_EL1_DebugVer_MASK), 2615 ID_SANITISED(ID_AA64DFR1_EL1), 2616 ID_UNALLOCATED(5,2), 2617 ID_UNALLOCATED(5,3), 2618 ID_HIDDEN(ID_AA64AFR0_EL1), 2619 ID_HIDDEN(ID_AA64AFR1_EL1), 2620 ID_UNALLOCATED(5,6), 2621 ID_UNALLOCATED(5,7), 2622 2623 /* CRm=6 */ 2624 ID_WRITABLE(ID_AA64ISAR0_EL1, ~ID_AA64ISAR0_EL1_RES0), 2625 ID_WRITABLE(ID_AA64ISAR1_EL1, ~(ID_AA64ISAR1_EL1_GPI | 2626 ID_AA64ISAR1_EL1_GPA | 2627 ID_AA64ISAR1_EL1_API | 2628 ID_AA64ISAR1_EL1_APA)), 2629 ID_WRITABLE(ID_AA64ISAR2_EL1, ~(ID_AA64ISAR2_EL1_RES0 | 2630 ID_AA64ISAR2_EL1_APA3 | 2631 ID_AA64ISAR2_EL1_GPA3)), 2632 ID_WRITABLE(ID_AA64ISAR3_EL1, (ID_AA64ISAR3_EL1_FPRCVT | 2633 ID_AA64ISAR3_EL1_FAMINMAX)), 2634 ID_UNALLOCATED(6,4), 2635 ID_UNALLOCATED(6,5), 2636 ID_UNALLOCATED(6,6), 2637 ID_UNALLOCATED(6,7), 2638 2639 /* CRm=7 */ 2640 ID_WRITABLE(ID_AA64MMFR0_EL1, ~(ID_AA64MMFR0_EL1_RES0 | 2641 ID_AA64MMFR0_EL1_TGRAN4_2 | 2642 ID_AA64MMFR0_EL1_TGRAN64_2 | 2643 ID_AA64MMFR0_EL1_TGRAN16_2 | 2644 ID_AA64MMFR0_EL1_ASIDBITS)), 2645 ID_WRITABLE(ID_AA64MMFR1_EL1, ~(ID_AA64MMFR1_EL1_RES0 | 2646 ID_AA64MMFR1_EL1_HCX | 2647 ID_AA64MMFR1_EL1_TWED | 2648 ID_AA64MMFR1_EL1_XNX | 2649 ID_AA64MMFR1_EL1_VH | 2650 ID_AA64MMFR1_EL1_VMIDBits)), 2651 ID_WRITABLE(ID_AA64MMFR2_EL1, ~(ID_AA64MMFR2_EL1_RES0 | 2652 ID_AA64MMFR2_EL1_EVT | 2653 ID_AA64MMFR2_EL1_FWB | 2654 ID_AA64MMFR2_EL1_IDS | 2655 ID_AA64MMFR2_EL1_NV | 2656 ID_AA64MMFR2_EL1_CCIDX)), 2657 ID_WRITABLE(ID_AA64MMFR3_EL1, (ID_AA64MMFR3_EL1_TCRX | 2658 ID_AA64MMFR3_EL1_S1PIE | 2659 ID_AA64MMFR3_EL1_S1POE)), 2660 ID_SANITISED(ID_AA64MMFR4_EL1), 2661 ID_UNALLOCATED(7,5), 2662 ID_UNALLOCATED(7,6), 2663 ID_UNALLOCATED(7,7), 2664 2665 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 }, 2666 { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 }, 2667 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 }, 2668 2669 MTE_REG(RGSR_EL1), 2670 MTE_REG(GCR_EL1), 2671 2672 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility }, 2673 { SYS_DESC(SYS_TRFCR_EL1), undef_access }, 2674 { SYS_DESC(SYS_SMPRI_EL1), undef_access }, 2675 { SYS_DESC(SYS_SMCR_EL1), undef_access }, 2676 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 }, 2677 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 }, 2678 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 }, 2679 { SYS_DESC(SYS_TCR2_EL1), access_vm_reg, reset_val, TCR2_EL1, 0, 2680 .visibility = tcr2_visibility }, 2681 2682 PTRAUTH_KEY(APIA), 2683 PTRAUTH_KEY(APIB), 2684 PTRAUTH_KEY(APDA), 2685 PTRAUTH_KEY(APDB), 2686 PTRAUTH_KEY(APGA), 2687 2688 { SYS_DESC(SYS_SPSR_EL1), access_spsr}, 2689 { SYS_DESC(SYS_ELR_EL1), access_elr}, 2690 2691 { SYS_DESC(SYS_ICC_PMR_EL1), undef_access }, 2692 2693 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 }, 2694 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 }, 2695 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 }, 2696 2697 { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi }, 2698 { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi }, 2699 { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi }, 2700 { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi }, 2701 { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi }, 2702 { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi }, 2703 { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi }, 2704 { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi }, 2705 2706 MTE_REG(TFSR_EL1), 2707 MTE_REG(TFSRE0_EL1), 2708 2709 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 }, 2710 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 }, 2711 2712 { SYS_DESC(SYS_PMSCR_EL1), undef_access }, 2713 { SYS_DESC(SYS_PMSNEVFR_EL1), undef_access }, 2714 { SYS_DESC(SYS_PMSICR_EL1), undef_access }, 2715 { SYS_DESC(SYS_PMSIRR_EL1), undef_access }, 2716 { SYS_DESC(SYS_PMSFCR_EL1), undef_access }, 2717 { SYS_DESC(SYS_PMSEVFR_EL1), undef_access }, 2718 { SYS_DESC(SYS_PMSLATFR_EL1), undef_access }, 2719 { SYS_DESC(SYS_PMSIDR_EL1), undef_access }, 2720 { SYS_DESC(SYS_PMBLIMITR_EL1), undef_access }, 2721 { SYS_DESC(SYS_PMBPTR_EL1), undef_access }, 2722 { SYS_DESC(SYS_PMBSR_EL1), undef_access }, 2723 /* PMBIDR_EL1 is not trapped */ 2724 2725 { PMU_SYS_REG(PMINTENSET_EL1), 2726 .access = access_pminten, .reg = PMINTENSET_EL1, 2727 .get_user = get_pmreg, .set_user = set_pmreg }, 2728 { PMU_SYS_REG(PMINTENCLR_EL1), 2729 .access = access_pminten, .reg = PMINTENSET_EL1, 2730 .get_user = get_pmreg, .set_user = set_pmreg }, 2731 { SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi }, 2732 2733 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 }, 2734 { SYS_DESC(SYS_PIRE0_EL1), NULL, reset_unknown, PIRE0_EL1, 2735 .visibility = s1pie_visibility }, 2736 { SYS_DESC(SYS_PIR_EL1), NULL, reset_unknown, PIR_EL1, 2737 .visibility = s1pie_visibility }, 2738 { SYS_DESC(SYS_POR_EL1), NULL, reset_unknown, POR_EL1, 2739 .visibility = s1poe_visibility }, 2740 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 }, 2741 2742 { SYS_DESC(SYS_LORSA_EL1), trap_loregion }, 2743 { SYS_DESC(SYS_LOREA_EL1), trap_loregion }, 2744 { SYS_DESC(SYS_LORN_EL1), trap_loregion }, 2745 { SYS_DESC(SYS_LORC_EL1), trap_loregion }, 2746 { SYS_DESC(SYS_MPAMIDR_EL1), undef_access }, 2747 { SYS_DESC(SYS_LORID_EL1), trap_loregion }, 2748 2749 { SYS_DESC(SYS_MPAM1_EL1), undef_access }, 2750 { SYS_DESC(SYS_MPAM0_EL1), undef_access }, 2751 { SYS_DESC(SYS_VBAR_EL1), access_rw, reset_val, VBAR_EL1, 0 }, 2752 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 }, 2753 2754 { SYS_DESC(SYS_ICC_IAR0_EL1), undef_access }, 2755 { SYS_DESC(SYS_ICC_EOIR0_EL1), undef_access }, 2756 { SYS_DESC(SYS_ICC_HPPIR0_EL1), undef_access }, 2757 { SYS_DESC(SYS_ICC_BPR0_EL1), undef_access }, 2758 { SYS_DESC(SYS_ICC_AP0R0_EL1), undef_access }, 2759 { SYS_DESC(SYS_ICC_AP0R1_EL1), undef_access }, 2760 { SYS_DESC(SYS_ICC_AP0R2_EL1), undef_access }, 2761 { SYS_DESC(SYS_ICC_AP0R3_EL1), undef_access }, 2762 { SYS_DESC(SYS_ICC_AP1R0_EL1), undef_access }, 2763 { SYS_DESC(SYS_ICC_AP1R1_EL1), undef_access }, 2764 { SYS_DESC(SYS_ICC_AP1R2_EL1), undef_access }, 2765 { SYS_DESC(SYS_ICC_AP1R3_EL1), undef_access }, 2766 { SYS_DESC(SYS_ICC_DIR_EL1), undef_access }, 2767 { SYS_DESC(SYS_ICC_RPR_EL1), undef_access }, 2768 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi }, 2769 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi }, 2770 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi }, 2771 { SYS_DESC(SYS_ICC_IAR1_EL1), undef_access }, 2772 { SYS_DESC(SYS_ICC_EOIR1_EL1), undef_access }, 2773 { SYS_DESC(SYS_ICC_HPPIR1_EL1), undef_access }, 2774 { SYS_DESC(SYS_ICC_BPR1_EL1), undef_access }, 2775 { SYS_DESC(SYS_ICC_CTLR_EL1), undef_access }, 2776 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre }, 2777 { SYS_DESC(SYS_ICC_IGRPEN0_EL1), undef_access }, 2778 { SYS_DESC(SYS_ICC_IGRPEN1_EL1), undef_access }, 2779 2780 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 }, 2781 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 }, 2782 2783 { SYS_DESC(SYS_ACCDATA_EL1), undef_access }, 2784 2785 { SYS_DESC(SYS_SCXTNUM_EL1), undef_access }, 2786 2787 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0}, 2788 2789 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr }, 2790 { SYS_DESC(SYS_CLIDR_EL1), access_clidr, reset_clidr, CLIDR_EL1, 2791 .set_user = set_clidr, .val = ~CLIDR_EL1_RES0 }, 2792 { SYS_DESC(SYS_CCSIDR2_EL1), undef_access }, 2793 { SYS_DESC(SYS_SMIDR_EL1), undef_access }, 2794 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, 2795 ID_FILTERED(CTR_EL0, ctr_el0, 2796 CTR_EL0_DIC_MASK | 2797 CTR_EL0_IDC_MASK | 2798 CTR_EL0_DminLine_MASK | 2799 CTR_EL0_L1Ip_MASK | 2800 CTR_EL0_IminLine_MASK), 2801 { SYS_DESC(SYS_SVCR), undef_access, reset_val, SVCR, 0, .visibility = sme_visibility }, 2802 { SYS_DESC(SYS_FPMR), undef_access, reset_val, FPMR, 0, .visibility = fp8_visibility }, 2803 2804 { PMU_SYS_REG(PMCR_EL0), .access = access_pmcr, .reset = reset_pmcr, 2805 .reg = PMCR_EL0, .get_user = get_pmcr, .set_user = set_pmcr }, 2806 { PMU_SYS_REG(PMCNTENSET_EL0), 2807 .access = access_pmcnten, .reg = PMCNTENSET_EL0, 2808 .get_user = get_pmreg, .set_user = set_pmreg }, 2809 { PMU_SYS_REG(PMCNTENCLR_EL0), 2810 .access = access_pmcnten, .reg = PMCNTENSET_EL0, 2811 .get_user = get_pmreg, .set_user = set_pmreg }, 2812 { PMU_SYS_REG(PMOVSCLR_EL0), 2813 .access = access_pmovs, .reg = PMOVSSET_EL0, 2814 .get_user = get_pmreg, .set_user = set_pmreg }, 2815 /* 2816 * PM_SWINC_EL0 is exposed to userspace as RAZ/WI, as it was 2817 * previously (and pointlessly) advertised in the past... 2818 */ 2819 { PMU_SYS_REG(PMSWINC_EL0), 2820 .get_user = get_raz_reg, .set_user = set_wi_reg, 2821 .access = access_pmswinc, .reset = NULL }, 2822 { PMU_SYS_REG(PMSELR_EL0), 2823 .access = access_pmselr, .reset = reset_pmselr, .reg = PMSELR_EL0 }, 2824 { PMU_SYS_REG(PMCEID0_EL0), 2825 .access = access_pmceid, .reset = NULL }, 2826 { PMU_SYS_REG(PMCEID1_EL0), 2827 .access = access_pmceid, .reset = NULL }, 2828 { PMU_SYS_REG(PMCCNTR_EL0), 2829 .access = access_pmu_evcntr, .reset = reset_unknown, 2830 .reg = PMCCNTR_EL0, .get_user = get_pmu_evcntr}, 2831 { PMU_SYS_REG(PMXEVTYPER_EL0), 2832 .access = access_pmu_evtyper, .reset = NULL }, 2833 { PMU_SYS_REG(PMXEVCNTR_EL0), 2834 .access = access_pmu_evcntr, .reset = NULL }, 2835 /* 2836 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero 2837 * in 32bit mode. Here we choose to reset it as zero for consistency. 2838 */ 2839 { PMU_SYS_REG(PMUSERENR_EL0), .access = access_pmuserenr, 2840 .reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 }, 2841 { PMU_SYS_REG(PMOVSSET_EL0), 2842 .access = access_pmovs, .reg = PMOVSSET_EL0, 2843 .get_user = get_pmreg, .set_user = set_pmreg }, 2844 2845 { SYS_DESC(SYS_POR_EL0), NULL, reset_unknown, POR_EL0, 2846 .visibility = s1poe_visibility }, 2847 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 }, 2848 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 }, 2849 { SYS_DESC(SYS_TPIDR2_EL0), undef_access }, 2850 2851 { SYS_DESC(SYS_SCXTNUM_EL0), undef_access }, 2852 2853 { SYS_DESC(SYS_AMCR_EL0), undef_access }, 2854 { SYS_DESC(SYS_AMCFGR_EL0), undef_access }, 2855 { SYS_DESC(SYS_AMCGCR_EL0), undef_access }, 2856 { SYS_DESC(SYS_AMUSERENR_EL0), undef_access }, 2857 { SYS_DESC(SYS_AMCNTENCLR0_EL0), undef_access }, 2858 { SYS_DESC(SYS_AMCNTENSET0_EL0), undef_access }, 2859 { SYS_DESC(SYS_AMCNTENCLR1_EL0), undef_access }, 2860 { SYS_DESC(SYS_AMCNTENSET1_EL0), undef_access }, 2861 AMU_AMEVCNTR0_EL0(0), 2862 AMU_AMEVCNTR0_EL0(1), 2863 AMU_AMEVCNTR0_EL0(2), 2864 AMU_AMEVCNTR0_EL0(3), 2865 AMU_AMEVCNTR0_EL0(4), 2866 AMU_AMEVCNTR0_EL0(5), 2867 AMU_AMEVCNTR0_EL0(6), 2868 AMU_AMEVCNTR0_EL0(7), 2869 AMU_AMEVCNTR0_EL0(8), 2870 AMU_AMEVCNTR0_EL0(9), 2871 AMU_AMEVCNTR0_EL0(10), 2872 AMU_AMEVCNTR0_EL0(11), 2873 AMU_AMEVCNTR0_EL0(12), 2874 AMU_AMEVCNTR0_EL0(13), 2875 AMU_AMEVCNTR0_EL0(14), 2876 AMU_AMEVCNTR0_EL0(15), 2877 AMU_AMEVTYPER0_EL0(0), 2878 AMU_AMEVTYPER0_EL0(1), 2879 AMU_AMEVTYPER0_EL0(2), 2880 AMU_AMEVTYPER0_EL0(3), 2881 AMU_AMEVTYPER0_EL0(4), 2882 AMU_AMEVTYPER0_EL0(5), 2883 AMU_AMEVTYPER0_EL0(6), 2884 AMU_AMEVTYPER0_EL0(7), 2885 AMU_AMEVTYPER0_EL0(8), 2886 AMU_AMEVTYPER0_EL0(9), 2887 AMU_AMEVTYPER0_EL0(10), 2888 AMU_AMEVTYPER0_EL0(11), 2889 AMU_AMEVTYPER0_EL0(12), 2890 AMU_AMEVTYPER0_EL0(13), 2891 AMU_AMEVTYPER0_EL0(14), 2892 AMU_AMEVTYPER0_EL0(15), 2893 AMU_AMEVCNTR1_EL0(0), 2894 AMU_AMEVCNTR1_EL0(1), 2895 AMU_AMEVCNTR1_EL0(2), 2896 AMU_AMEVCNTR1_EL0(3), 2897 AMU_AMEVCNTR1_EL0(4), 2898 AMU_AMEVCNTR1_EL0(5), 2899 AMU_AMEVCNTR1_EL0(6), 2900 AMU_AMEVCNTR1_EL0(7), 2901 AMU_AMEVCNTR1_EL0(8), 2902 AMU_AMEVCNTR1_EL0(9), 2903 AMU_AMEVCNTR1_EL0(10), 2904 AMU_AMEVCNTR1_EL0(11), 2905 AMU_AMEVCNTR1_EL0(12), 2906 AMU_AMEVCNTR1_EL0(13), 2907 AMU_AMEVCNTR1_EL0(14), 2908 AMU_AMEVCNTR1_EL0(15), 2909 AMU_AMEVTYPER1_EL0(0), 2910 AMU_AMEVTYPER1_EL0(1), 2911 AMU_AMEVTYPER1_EL0(2), 2912 AMU_AMEVTYPER1_EL0(3), 2913 AMU_AMEVTYPER1_EL0(4), 2914 AMU_AMEVTYPER1_EL0(5), 2915 AMU_AMEVTYPER1_EL0(6), 2916 AMU_AMEVTYPER1_EL0(7), 2917 AMU_AMEVTYPER1_EL0(8), 2918 AMU_AMEVTYPER1_EL0(9), 2919 AMU_AMEVTYPER1_EL0(10), 2920 AMU_AMEVTYPER1_EL0(11), 2921 AMU_AMEVTYPER1_EL0(12), 2922 AMU_AMEVTYPER1_EL0(13), 2923 AMU_AMEVTYPER1_EL0(14), 2924 AMU_AMEVTYPER1_EL0(15), 2925 2926 { SYS_DESC(SYS_CNTPCT_EL0), access_arch_timer }, 2927 { SYS_DESC(SYS_CNTPCTSS_EL0), access_arch_timer }, 2928 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer }, 2929 { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer }, 2930 { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer }, 2931 2932 /* PMEVCNTRn_EL0 */ 2933 PMU_PMEVCNTR_EL0(0), 2934 PMU_PMEVCNTR_EL0(1), 2935 PMU_PMEVCNTR_EL0(2), 2936 PMU_PMEVCNTR_EL0(3), 2937 PMU_PMEVCNTR_EL0(4), 2938 PMU_PMEVCNTR_EL0(5), 2939 PMU_PMEVCNTR_EL0(6), 2940 PMU_PMEVCNTR_EL0(7), 2941 PMU_PMEVCNTR_EL0(8), 2942 PMU_PMEVCNTR_EL0(9), 2943 PMU_PMEVCNTR_EL0(10), 2944 PMU_PMEVCNTR_EL0(11), 2945 PMU_PMEVCNTR_EL0(12), 2946 PMU_PMEVCNTR_EL0(13), 2947 PMU_PMEVCNTR_EL0(14), 2948 PMU_PMEVCNTR_EL0(15), 2949 PMU_PMEVCNTR_EL0(16), 2950 PMU_PMEVCNTR_EL0(17), 2951 PMU_PMEVCNTR_EL0(18), 2952 PMU_PMEVCNTR_EL0(19), 2953 PMU_PMEVCNTR_EL0(20), 2954 PMU_PMEVCNTR_EL0(21), 2955 PMU_PMEVCNTR_EL0(22), 2956 PMU_PMEVCNTR_EL0(23), 2957 PMU_PMEVCNTR_EL0(24), 2958 PMU_PMEVCNTR_EL0(25), 2959 PMU_PMEVCNTR_EL0(26), 2960 PMU_PMEVCNTR_EL0(27), 2961 PMU_PMEVCNTR_EL0(28), 2962 PMU_PMEVCNTR_EL0(29), 2963 PMU_PMEVCNTR_EL0(30), 2964 /* PMEVTYPERn_EL0 */ 2965 PMU_PMEVTYPER_EL0(0), 2966 PMU_PMEVTYPER_EL0(1), 2967 PMU_PMEVTYPER_EL0(2), 2968 PMU_PMEVTYPER_EL0(3), 2969 PMU_PMEVTYPER_EL0(4), 2970 PMU_PMEVTYPER_EL0(5), 2971 PMU_PMEVTYPER_EL0(6), 2972 PMU_PMEVTYPER_EL0(7), 2973 PMU_PMEVTYPER_EL0(8), 2974 PMU_PMEVTYPER_EL0(9), 2975 PMU_PMEVTYPER_EL0(10), 2976 PMU_PMEVTYPER_EL0(11), 2977 PMU_PMEVTYPER_EL0(12), 2978 PMU_PMEVTYPER_EL0(13), 2979 PMU_PMEVTYPER_EL0(14), 2980 PMU_PMEVTYPER_EL0(15), 2981 PMU_PMEVTYPER_EL0(16), 2982 PMU_PMEVTYPER_EL0(17), 2983 PMU_PMEVTYPER_EL0(18), 2984 PMU_PMEVTYPER_EL0(19), 2985 PMU_PMEVTYPER_EL0(20), 2986 PMU_PMEVTYPER_EL0(21), 2987 PMU_PMEVTYPER_EL0(22), 2988 PMU_PMEVTYPER_EL0(23), 2989 PMU_PMEVTYPER_EL0(24), 2990 PMU_PMEVTYPER_EL0(25), 2991 PMU_PMEVTYPER_EL0(26), 2992 PMU_PMEVTYPER_EL0(27), 2993 PMU_PMEVTYPER_EL0(28), 2994 PMU_PMEVTYPER_EL0(29), 2995 PMU_PMEVTYPER_EL0(30), 2996 /* 2997 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero 2998 * in 32bit mode. Here we choose to reset it as zero for consistency. 2999 */ 3000 { PMU_SYS_REG(PMCCFILTR_EL0), .access = access_pmu_evtyper, 3001 .reset = reset_val, .reg = PMCCFILTR_EL0, .val = 0 }, 3002 3003 EL2_REG_VNCR(VPIDR_EL2, reset_unknown, 0), 3004 EL2_REG_VNCR(VMPIDR_EL2, reset_unknown, 0), 3005 EL2_REG(SCTLR_EL2, access_rw, reset_val, SCTLR_EL2_RES1), 3006 EL2_REG(ACTLR_EL2, access_rw, reset_val, 0), 3007 EL2_REG_VNCR(HCR_EL2, reset_hcr, 0), 3008 EL2_REG(MDCR_EL2, access_mdcr, reset_val, 0), 3009 EL2_REG(CPTR_EL2, access_rw, reset_val, CPTR_NVHE_EL2_RES1), 3010 EL2_REG_VNCR(HSTR_EL2, reset_val, 0), 3011 EL2_REG_VNCR(HFGRTR_EL2, reset_val, 0), 3012 EL2_REG_VNCR(HFGWTR_EL2, reset_val, 0), 3013 EL2_REG_VNCR(HFGITR_EL2, reset_val, 0), 3014 EL2_REG_VNCR(HACR_EL2, reset_val, 0), 3015 3016 EL2_REG_FILTERED(ZCR_EL2, access_zcr_el2, reset_val, 0, 3017 sve_el2_visibility), 3018 3019 EL2_REG_VNCR(HCRX_EL2, reset_val, 0), 3020 3021 EL2_REG(TTBR0_EL2, access_rw, reset_val, 0), 3022 EL2_REG(TTBR1_EL2, access_rw, reset_val, 0), 3023 EL2_REG(TCR_EL2, access_rw, reset_val, TCR_EL2_RES1), 3024 EL2_REG_FILTERED(TCR2_EL2, access_rw, reset_val, TCR2_EL2_RES1, 3025 tcr2_el2_visibility), 3026 EL2_REG_VNCR(VTTBR_EL2, reset_val, 0), 3027 EL2_REG_VNCR(VTCR_EL2, reset_val, 0), 3028 3029 { SYS_DESC(SYS_DACR32_EL2), undef_access, reset_unknown, DACR32_EL2 }, 3030 EL2_REG_VNCR(HDFGRTR_EL2, reset_val, 0), 3031 EL2_REG_VNCR(HDFGWTR_EL2, reset_val, 0), 3032 EL2_REG_VNCR(HAFGRTR_EL2, reset_val, 0), 3033 EL2_REG_REDIR(SPSR_EL2, reset_val, 0), 3034 EL2_REG_REDIR(ELR_EL2, reset_val, 0), 3035 { SYS_DESC(SYS_SP_EL1), access_sp_el1}, 3036 3037 /* AArch32 SPSR_* are RES0 if trapped from a NV guest */ 3038 { SYS_DESC(SYS_SPSR_irq), .access = trap_raz_wi }, 3039 { SYS_DESC(SYS_SPSR_abt), .access = trap_raz_wi }, 3040 { SYS_DESC(SYS_SPSR_und), .access = trap_raz_wi }, 3041 { SYS_DESC(SYS_SPSR_fiq), .access = trap_raz_wi }, 3042 3043 { SYS_DESC(SYS_IFSR32_EL2), undef_access, reset_unknown, IFSR32_EL2 }, 3044 EL2_REG(AFSR0_EL2, access_rw, reset_val, 0), 3045 EL2_REG(AFSR1_EL2, access_rw, reset_val, 0), 3046 EL2_REG_REDIR(ESR_EL2, reset_val, 0), 3047 { SYS_DESC(SYS_FPEXC32_EL2), undef_access, reset_val, FPEXC32_EL2, 0x700 }, 3048 3049 EL2_REG_REDIR(FAR_EL2, reset_val, 0), 3050 EL2_REG(HPFAR_EL2, access_rw, reset_val, 0), 3051 3052 EL2_REG(MAIR_EL2, access_rw, reset_val, 0), 3053 EL2_REG_FILTERED(PIRE0_EL2, access_rw, reset_val, 0, 3054 s1pie_el2_visibility), 3055 EL2_REG_FILTERED(PIR_EL2, access_rw, reset_val, 0, 3056 s1pie_el2_visibility), 3057 EL2_REG_FILTERED(POR_EL2, access_rw, reset_val, 0, 3058 s1poe_el2_visibility), 3059 EL2_REG(AMAIR_EL2, access_rw, reset_val, 0), 3060 { SYS_DESC(SYS_MPAMHCR_EL2), undef_access }, 3061 { SYS_DESC(SYS_MPAMVPMV_EL2), undef_access }, 3062 { SYS_DESC(SYS_MPAM2_EL2), undef_access }, 3063 { SYS_DESC(SYS_MPAMVPM0_EL2), undef_access }, 3064 { SYS_DESC(SYS_MPAMVPM1_EL2), undef_access }, 3065 { SYS_DESC(SYS_MPAMVPM2_EL2), undef_access }, 3066 { SYS_DESC(SYS_MPAMVPM3_EL2), undef_access }, 3067 { SYS_DESC(SYS_MPAMVPM4_EL2), undef_access }, 3068 { SYS_DESC(SYS_MPAMVPM5_EL2), undef_access }, 3069 { SYS_DESC(SYS_MPAMVPM6_EL2), undef_access }, 3070 { SYS_DESC(SYS_MPAMVPM7_EL2), undef_access }, 3071 3072 EL2_REG(VBAR_EL2, access_rw, reset_val, 0), 3073 EL2_REG(RVBAR_EL2, access_rw, reset_val, 0), 3074 { SYS_DESC(SYS_RMR_EL2), undef_access }, 3075 3076 EL2_REG_VNCR(ICH_HCR_EL2, reset_val, 0), 3077 3078 EL2_REG(CONTEXTIDR_EL2, access_rw, reset_val, 0), 3079 EL2_REG(TPIDR_EL2, access_rw, reset_val, 0), 3080 3081 EL2_REG_VNCR(CNTVOFF_EL2, reset_val, 0), 3082 EL2_REG(CNTHCTL_EL2, access_rw, reset_val, 0), 3083 3084 { SYS_DESC(SYS_CNTKCTL_EL12), access_cntkctl_el12 }, 3085 3086 EL2_REG(SP_EL2, NULL, reset_unknown, 0), 3087 }; 3088 3089 static bool handle_at_s1e01(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3090 const struct sys_reg_desc *r) 3091 { 3092 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3093 3094 __kvm_at_s1e01(vcpu, op, p->regval); 3095 3096 return true; 3097 } 3098 3099 static bool handle_at_s1e2(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3100 const struct sys_reg_desc *r) 3101 { 3102 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3103 3104 /* There is no FGT associated with AT S1E2A :-( */ 3105 if (op == OP_AT_S1E2A && 3106 !kvm_has_feat(vcpu->kvm, ID_AA64ISAR2_EL1, ATS1A, IMP)) { 3107 kvm_inject_undefined(vcpu); 3108 return false; 3109 } 3110 3111 __kvm_at_s1e2(vcpu, op, p->regval); 3112 3113 return true; 3114 } 3115 3116 static bool handle_at_s12(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3117 const struct sys_reg_desc *r) 3118 { 3119 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3120 3121 __kvm_at_s12(vcpu, op, p->regval); 3122 3123 return true; 3124 } 3125 3126 static bool kvm_supported_tlbi_s12_op(struct kvm_vcpu *vpcu, u32 instr) 3127 { 3128 struct kvm *kvm = vpcu->kvm; 3129 u8 CRm = sys_reg_CRm(instr); 3130 3131 if (sys_reg_CRn(instr) == TLBI_CRn_nXS && 3132 !kvm_has_feat(kvm, ID_AA64ISAR1_EL1, XS, IMP)) 3133 return false; 3134 3135 if (CRm == TLBI_CRm_nROS && 3136 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 3137 return false; 3138 3139 return true; 3140 } 3141 3142 static bool handle_alle1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3143 const struct sys_reg_desc *r) 3144 { 3145 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3146 3147 if (!kvm_supported_tlbi_s12_op(vcpu, sys_encoding)) 3148 return undef_access(vcpu, p, r); 3149 3150 write_lock(&vcpu->kvm->mmu_lock); 3151 3152 /* 3153 * Drop all shadow S2s, resulting in S1/S2 TLBIs for each of the 3154 * corresponding VMIDs. 3155 */ 3156 kvm_nested_s2_unmap(vcpu->kvm, true); 3157 3158 write_unlock(&vcpu->kvm->mmu_lock); 3159 3160 return true; 3161 } 3162 3163 static bool kvm_supported_tlbi_ipas2_op(struct kvm_vcpu *vpcu, u32 instr) 3164 { 3165 struct kvm *kvm = vpcu->kvm; 3166 u8 CRm = sys_reg_CRm(instr); 3167 u8 Op2 = sys_reg_Op2(instr); 3168 3169 if (sys_reg_CRn(instr) == TLBI_CRn_nXS && 3170 !kvm_has_feat(kvm, ID_AA64ISAR1_EL1, XS, IMP)) 3171 return false; 3172 3173 if (CRm == TLBI_CRm_IPAIS && (Op2 == 2 || Op2 == 6) && 3174 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE)) 3175 return false; 3176 3177 if (CRm == TLBI_CRm_IPAONS && (Op2 == 0 || Op2 == 4) && 3178 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 3179 return false; 3180 3181 if (CRm == TLBI_CRm_IPAONS && (Op2 == 3 || Op2 == 7) && 3182 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE)) 3183 return false; 3184 3185 return true; 3186 } 3187 3188 /* Only defined here as this is an internal "abstraction" */ 3189 union tlbi_info { 3190 struct { 3191 u64 start; 3192 u64 size; 3193 } range; 3194 3195 struct { 3196 u64 addr; 3197 } ipa; 3198 3199 struct { 3200 u64 addr; 3201 u32 encoding; 3202 } va; 3203 }; 3204 3205 static void s2_mmu_unmap_range(struct kvm_s2_mmu *mmu, 3206 const union tlbi_info *info) 3207 { 3208 /* 3209 * The unmap operation is allowed to drop the MMU lock and block, which 3210 * means that @mmu could be used for a different context than the one 3211 * currently being invalidated. 3212 * 3213 * This behavior is still safe, as: 3214 * 3215 * 1) The vCPU(s) that recycled the MMU are responsible for invalidating 3216 * the entire MMU before reusing it, which still honors the intent 3217 * of a TLBI. 3218 * 3219 * 2) Until the guest TLBI instruction is 'retired' (i.e. increment PC 3220 * and ERET to the guest), other vCPUs are allowed to use stale 3221 * translations. 3222 * 3223 * 3) Accidentally unmapping an unrelated MMU context is nonfatal, and 3224 * at worst may cause more aborts for shadow stage-2 fills. 3225 * 3226 * Dropping the MMU lock also implies that shadow stage-2 fills could 3227 * happen behind the back of the TLBI. This is still safe, though, as 3228 * the L1 needs to put its stage-2 in a consistent state before doing 3229 * the TLBI. 3230 */ 3231 kvm_stage2_unmap_range(mmu, info->range.start, info->range.size, true); 3232 } 3233 3234 static bool handle_vmalls12e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3235 const struct sys_reg_desc *r) 3236 { 3237 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3238 u64 limit, vttbr; 3239 3240 if (!kvm_supported_tlbi_s12_op(vcpu, sys_encoding)) 3241 return undef_access(vcpu, p, r); 3242 3243 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 3244 limit = BIT_ULL(kvm_get_pa_bits(vcpu->kvm)); 3245 3246 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 3247 &(union tlbi_info) { 3248 .range = { 3249 .start = 0, 3250 .size = limit, 3251 }, 3252 }, 3253 s2_mmu_unmap_range); 3254 3255 return true; 3256 } 3257 3258 static bool handle_ripas2e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3259 const struct sys_reg_desc *r) 3260 { 3261 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3262 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 3263 u64 base, range, tg, num, scale; 3264 int shift; 3265 3266 if (!kvm_supported_tlbi_ipas2_op(vcpu, sys_encoding)) 3267 return undef_access(vcpu, p, r); 3268 3269 /* 3270 * Because the shadow S2 structure doesn't necessarily reflect that 3271 * of the guest's S2 (different base granule size, for example), we 3272 * decide to ignore TTL and only use the described range. 3273 */ 3274 tg = FIELD_GET(GENMASK(47, 46), p->regval); 3275 scale = FIELD_GET(GENMASK(45, 44), p->regval); 3276 num = FIELD_GET(GENMASK(43, 39), p->regval); 3277 base = p->regval & GENMASK(36, 0); 3278 3279 switch(tg) { 3280 case 1: 3281 shift = 12; 3282 break; 3283 case 2: 3284 shift = 14; 3285 break; 3286 case 3: 3287 default: /* IMPDEF: handle tg==0 as 64k */ 3288 shift = 16; 3289 break; 3290 } 3291 3292 base <<= shift; 3293 range = __TLBI_RANGE_PAGES(num, scale) << shift; 3294 3295 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 3296 &(union tlbi_info) { 3297 .range = { 3298 .start = base, 3299 .size = range, 3300 }, 3301 }, 3302 s2_mmu_unmap_range); 3303 3304 return true; 3305 } 3306 3307 static void s2_mmu_unmap_ipa(struct kvm_s2_mmu *mmu, 3308 const union tlbi_info *info) 3309 { 3310 unsigned long max_size; 3311 u64 base_addr; 3312 3313 /* 3314 * We drop a number of things from the supplied value: 3315 * 3316 * - NS bit: we're non-secure only. 3317 * 3318 * - IPA[51:48]: We don't support 52bit IPA just yet... 3319 * 3320 * And of course, adjust the IPA to be on an actual address. 3321 */ 3322 base_addr = (info->ipa.addr & GENMASK_ULL(35, 0)) << 12; 3323 max_size = compute_tlb_inval_range(mmu, info->ipa.addr); 3324 base_addr &= ~(max_size - 1); 3325 3326 /* 3327 * See comment in s2_mmu_unmap_range() for why this is allowed to 3328 * reschedule. 3329 */ 3330 kvm_stage2_unmap_range(mmu, base_addr, max_size, true); 3331 } 3332 3333 static bool handle_ipas2e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3334 const struct sys_reg_desc *r) 3335 { 3336 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3337 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 3338 3339 if (!kvm_supported_tlbi_ipas2_op(vcpu, sys_encoding)) 3340 return undef_access(vcpu, p, r); 3341 3342 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 3343 &(union tlbi_info) { 3344 .ipa = { 3345 .addr = p->regval, 3346 }, 3347 }, 3348 s2_mmu_unmap_ipa); 3349 3350 return true; 3351 } 3352 3353 static void s2_mmu_tlbi_s1e1(struct kvm_s2_mmu *mmu, 3354 const union tlbi_info *info) 3355 { 3356 WARN_ON(__kvm_tlbi_s1e2(mmu, info->va.addr, info->va.encoding)); 3357 } 3358 3359 static bool handle_tlbi_el1(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3360 const struct sys_reg_desc *r) 3361 { 3362 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3363 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 3364 3365 /* 3366 * If we're here, this is because we've trapped on a EL1 TLBI 3367 * instruction that affects the EL1 translation regime while 3368 * we're running in a context that doesn't allow us to let the 3369 * HW do its thing (aka vEL2): 3370 * 3371 * - HCR_EL2.E2H == 0 : a non-VHE guest 3372 * - HCR_EL2.{E2H,TGE} == { 1, 0 } : a VHE guest in guest mode 3373 * 3374 * We don't expect these helpers to ever be called when running 3375 * in a vEL1 context. 3376 */ 3377 3378 WARN_ON(!vcpu_is_el2(vcpu)); 3379 3380 if (!kvm_supported_tlbi_s1e1_op(vcpu, sys_encoding)) 3381 return undef_access(vcpu, p, r); 3382 3383 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 3384 &(union tlbi_info) { 3385 .va = { 3386 .addr = p->regval, 3387 .encoding = sys_encoding, 3388 }, 3389 }, 3390 s2_mmu_tlbi_s1e1); 3391 3392 return true; 3393 } 3394 3395 #define SYS_INSN(insn, access_fn) \ 3396 { \ 3397 SYS_DESC(OP_##insn), \ 3398 .access = (access_fn), \ 3399 } 3400 3401 static struct sys_reg_desc sys_insn_descs[] = { 3402 { SYS_DESC(SYS_DC_ISW), access_dcsw }, 3403 { SYS_DESC(SYS_DC_IGSW), access_dcgsw }, 3404 { SYS_DESC(SYS_DC_IGDSW), access_dcgsw }, 3405 3406 SYS_INSN(AT_S1E1R, handle_at_s1e01), 3407 SYS_INSN(AT_S1E1W, handle_at_s1e01), 3408 SYS_INSN(AT_S1E0R, handle_at_s1e01), 3409 SYS_INSN(AT_S1E0W, handle_at_s1e01), 3410 SYS_INSN(AT_S1E1RP, handle_at_s1e01), 3411 SYS_INSN(AT_S1E1WP, handle_at_s1e01), 3412 3413 { SYS_DESC(SYS_DC_CSW), access_dcsw }, 3414 { SYS_DESC(SYS_DC_CGSW), access_dcgsw }, 3415 { SYS_DESC(SYS_DC_CGDSW), access_dcgsw }, 3416 { SYS_DESC(SYS_DC_CISW), access_dcsw }, 3417 { SYS_DESC(SYS_DC_CIGSW), access_dcgsw }, 3418 { SYS_DESC(SYS_DC_CIGDSW), access_dcgsw }, 3419 3420 SYS_INSN(TLBI_VMALLE1OS, handle_tlbi_el1), 3421 SYS_INSN(TLBI_VAE1OS, handle_tlbi_el1), 3422 SYS_INSN(TLBI_ASIDE1OS, handle_tlbi_el1), 3423 SYS_INSN(TLBI_VAAE1OS, handle_tlbi_el1), 3424 SYS_INSN(TLBI_VALE1OS, handle_tlbi_el1), 3425 SYS_INSN(TLBI_VAALE1OS, handle_tlbi_el1), 3426 3427 SYS_INSN(TLBI_RVAE1IS, handle_tlbi_el1), 3428 SYS_INSN(TLBI_RVAAE1IS, handle_tlbi_el1), 3429 SYS_INSN(TLBI_RVALE1IS, handle_tlbi_el1), 3430 SYS_INSN(TLBI_RVAALE1IS, handle_tlbi_el1), 3431 3432 SYS_INSN(TLBI_VMALLE1IS, handle_tlbi_el1), 3433 SYS_INSN(TLBI_VAE1IS, handle_tlbi_el1), 3434 SYS_INSN(TLBI_ASIDE1IS, handle_tlbi_el1), 3435 SYS_INSN(TLBI_VAAE1IS, handle_tlbi_el1), 3436 SYS_INSN(TLBI_VALE1IS, handle_tlbi_el1), 3437 SYS_INSN(TLBI_VAALE1IS, handle_tlbi_el1), 3438 3439 SYS_INSN(TLBI_RVAE1OS, handle_tlbi_el1), 3440 SYS_INSN(TLBI_RVAAE1OS, handle_tlbi_el1), 3441 SYS_INSN(TLBI_RVALE1OS, handle_tlbi_el1), 3442 SYS_INSN(TLBI_RVAALE1OS, handle_tlbi_el1), 3443 3444 SYS_INSN(TLBI_RVAE1, handle_tlbi_el1), 3445 SYS_INSN(TLBI_RVAAE1, handle_tlbi_el1), 3446 SYS_INSN(TLBI_RVALE1, handle_tlbi_el1), 3447 SYS_INSN(TLBI_RVAALE1, handle_tlbi_el1), 3448 3449 SYS_INSN(TLBI_VMALLE1, handle_tlbi_el1), 3450 SYS_INSN(TLBI_VAE1, handle_tlbi_el1), 3451 SYS_INSN(TLBI_ASIDE1, handle_tlbi_el1), 3452 SYS_INSN(TLBI_VAAE1, handle_tlbi_el1), 3453 SYS_INSN(TLBI_VALE1, handle_tlbi_el1), 3454 SYS_INSN(TLBI_VAALE1, handle_tlbi_el1), 3455 3456 SYS_INSN(TLBI_VMALLE1OSNXS, handle_tlbi_el1), 3457 SYS_INSN(TLBI_VAE1OSNXS, handle_tlbi_el1), 3458 SYS_INSN(TLBI_ASIDE1OSNXS, handle_tlbi_el1), 3459 SYS_INSN(TLBI_VAAE1OSNXS, handle_tlbi_el1), 3460 SYS_INSN(TLBI_VALE1OSNXS, handle_tlbi_el1), 3461 SYS_INSN(TLBI_VAALE1OSNXS, handle_tlbi_el1), 3462 3463 SYS_INSN(TLBI_RVAE1ISNXS, handle_tlbi_el1), 3464 SYS_INSN(TLBI_RVAAE1ISNXS, handle_tlbi_el1), 3465 SYS_INSN(TLBI_RVALE1ISNXS, handle_tlbi_el1), 3466 SYS_INSN(TLBI_RVAALE1ISNXS, handle_tlbi_el1), 3467 3468 SYS_INSN(TLBI_VMALLE1ISNXS, handle_tlbi_el1), 3469 SYS_INSN(TLBI_VAE1ISNXS, handle_tlbi_el1), 3470 SYS_INSN(TLBI_ASIDE1ISNXS, handle_tlbi_el1), 3471 SYS_INSN(TLBI_VAAE1ISNXS, handle_tlbi_el1), 3472 SYS_INSN(TLBI_VALE1ISNXS, handle_tlbi_el1), 3473 SYS_INSN(TLBI_VAALE1ISNXS, handle_tlbi_el1), 3474 3475 SYS_INSN(TLBI_RVAE1OSNXS, handle_tlbi_el1), 3476 SYS_INSN(TLBI_RVAAE1OSNXS, handle_tlbi_el1), 3477 SYS_INSN(TLBI_RVALE1OSNXS, handle_tlbi_el1), 3478 SYS_INSN(TLBI_RVAALE1OSNXS, handle_tlbi_el1), 3479 3480 SYS_INSN(TLBI_RVAE1NXS, handle_tlbi_el1), 3481 SYS_INSN(TLBI_RVAAE1NXS, handle_tlbi_el1), 3482 SYS_INSN(TLBI_RVALE1NXS, handle_tlbi_el1), 3483 SYS_INSN(TLBI_RVAALE1NXS, handle_tlbi_el1), 3484 3485 SYS_INSN(TLBI_VMALLE1NXS, handle_tlbi_el1), 3486 SYS_INSN(TLBI_VAE1NXS, handle_tlbi_el1), 3487 SYS_INSN(TLBI_ASIDE1NXS, handle_tlbi_el1), 3488 SYS_INSN(TLBI_VAAE1NXS, handle_tlbi_el1), 3489 SYS_INSN(TLBI_VALE1NXS, handle_tlbi_el1), 3490 SYS_INSN(TLBI_VAALE1NXS, handle_tlbi_el1), 3491 3492 SYS_INSN(AT_S1E2R, handle_at_s1e2), 3493 SYS_INSN(AT_S1E2W, handle_at_s1e2), 3494 SYS_INSN(AT_S12E1R, handle_at_s12), 3495 SYS_INSN(AT_S12E1W, handle_at_s12), 3496 SYS_INSN(AT_S12E0R, handle_at_s12), 3497 SYS_INSN(AT_S12E0W, handle_at_s12), 3498 SYS_INSN(AT_S1E2A, handle_at_s1e2), 3499 3500 SYS_INSN(TLBI_IPAS2E1IS, handle_ipas2e1is), 3501 SYS_INSN(TLBI_RIPAS2E1IS, handle_ripas2e1is), 3502 SYS_INSN(TLBI_IPAS2LE1IS, handle_ipas2e1is), 3503 SYS_INSN(TLBI_RIPAS2LE1IS, handle_ripas2e1is), 3504 3505 SYS_INSN(TLBI_ALLE2OS, undef_access), 3506 SYS_INSN(TLBI_VAE2OS, undef_access), 3507 SYS_INSN(TLBI_ALLE1OS, handle_alle1is), 3508 SYS_INSN(TLBI_VALE2OS, undef_access), 3509 SYS_INSN(TLBI_VMALLS12E1OS, handle_vmalls12e1is), 3510 3511 SYS_INSN(TLBI_RVAE2IS, undef_access), 3512 SYS_INSN(TLBI_RVALE2IS, undef_access), 3513 3514 SYS_INSN(TLBI_ALLE1IS, handle_alle1is), 3515 SYS_INSN(TLBI_VMALLS12E1IS, handle_vmalls12e1is), 3516 SYS_INSN(TLBI_IPAS2E1OS, handle_ipas2e1is), 3517 SYS_INSN(TLBI_IPAS2E1, handle_ipas2e1is), 3518 SYS_INSN(TLBI_RIPAS2E1, handle_ripas2e1is), 3519 SYS_INSN(TLBI_RIPAS2E1OS, handle_ripas2e1is), 3520 SYS_INSN(TLBI_IPAS2LE1OS, handle_ipas2e1is), 3521 SYS_INSN(TLBI_IPAS2LE1, handle_ipas2e1is), 3522 SYS_INSN(TLBI_RIPAS2LE1, handle_ripas2e1is), 3523 SYS_INSN(TLBI_RIPAS2LE1OS, handle_ripas2e1is), 3524 SYS_INSN(TLBI_RVAE2OS, undef_access), 3525 SYS_INSN(TLBI_RVALE2OS, undef_access), 3526 SYS_INSN(TLBI_RVAE2, undef_access), 3527 SYS_INSN(TLBI_RVALE2, undef_access), 3528 SYS_INSN(TLBI_ALLE1, handle_alle1is), 3529 SYS_INSN(TLBI_VMALLS12E1, handle_vmalls12e1is), 3530 3531 SYS_INSN(TLBI_IPAS2E1ISNXS, handle_ipas2e1is), 3532 SYS_INSN(TLBI_RIPAS2E1ISNXS, handle_ripas2e1is), 3533 SYS_INSN(TLBI_IPAS2LE1ISNXS, handle_ipas2e1is), 3534 SYS_INSN(TLBI_RIPAS2LE1ISNXS, handle_ripas2e1is), 3535 3536 SYS_INSN(TLBI_ALLE2OSNXS, undef_access), 3537 SYS_INSN(TLBI_VAE2OSNXS, undef_access), 3538 SYS_INSN(TLBI_ALLE1OSNXS, handle_alle1is), 3539 SYS_INSN(TLBI_VALE2OSNXS, undef_access), 3540 SYS_INSN(TLBI_VMALLS12E1OSNXS, handle_vmalls12e1is), 3541 3542 SYS_INSN(TLBI_RVAE2ISNXS, undef_access), 3543 SYS_INSN(TLBI_RVALE2ISNXS, undef_access), 3544 SYS_INSN(TLBI_ALLE2ISNXS, undef_access), 3545 SYS_INSN(TLBI_VAE2ISNXS, undef_access), 3546 3547 SYS_INSN(TLBI_ALLE1ISNXS, handle_alle1is), 3548 SYS_INSN(TLBI_VALE2ISNXS, undef_access), 3549 SYS_INSN(TLBI_VMALLS12E1ISNXS, handle_vmalls12e1is), 3550 SYS_INSN(TLBI_IPAS2E1OSNXS, handle_ipas2e1is), 3551 SYS_INSN(TLBI_IPAS2E1NXS, handle_ipas2e1is), 3552 SYS_INSN(TLBI_RIPAS2E1NXS, handle_ripas2e1is), 3553 SYS_INSN(TLBI_RIPAS2E1OSNXS, handle_ripas2e1is), 3554 SYS_INSN(TLBI_IPAS2LE1OSNXS, handle_ipas2e1is), 3555 SYS_INSN(TLBI_IPAS2LE1NXS, handle_ipas2e1is), 3556 SYS_INSN(TLBI_RIPAS2LE1NXS, handle_ripas2e1is), 3557 SYS_INSN(TLBI_RIPAS2LE1OSNXS, handle_ripas2e1is), 3558 SYS_INSN(TLBI_RVAE2OSNXS, undef_access), 3559 SYS_INSN(TLBI_RVALE2OSNXS, undef_access), 3560 SYS_INSN(TLBI_RVAE2NXS, undef_access), 3561 SYS_INSN(TLBI_RVALE2NXS, undef_access), 3562 SYS_INSN(TLBI_ALLE2NXS, undef_access), 3563 SYS_INSN(TLBI_VAE2NXS, undef_access), 3564 SYS_INSN(TLBI_ALLE1NXS, handle_alle1is), 3565 SYS_INSN(TLBI_VALE2NXS, undef_access), 3566 SYS_INSN(TLBI_VMALLS12E1NXS, handle_vmalls12e1is), 3567 }; 3568 3569 static bool trap_dbgdidr(struct kvm_vcpu *vcpu, 3570 struct sys_reg_params *p, 3571 const struct sys_reg_desc *r) 3572 { 3573 if (p->is_write) { 3574 return ignore_write(vcpu, p); 3575 } else { 3576 u64 dfr = kvm_read_vm_id_reg(vcpu->kvm, SYS_ID_AA64DFR0_EL1); 3577 u32 el3 = kvm_has_feat(vcpu->kvm, ID_AA64PFR0_EL1, EL3, IMP); 3578 3579 p->regval = ((SYS_FIELD_GET(ID_AA64DFR0_EL1, WRPs, dfr) << 28) | 3580 (SYS_FIELD_GET(ID_AA64DFR0_EL1, BRPs, dfr) << 24) | 3581 (SYS_FIELD_GET(ID_AA64DFR0_EL1, CTX_CMPs, dfr) << 20) | 3582 (SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, dfr) << 16) | 3583 (1 << 15) | (el3 << 14) | (el3 << 12)); 3584 return true; 3585 } 3586 } 3587 3588 /* 3589 * AArch32 debug register mappings 3590 * 3591 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0] 3592 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32] 3593 * 3594 * None of the other registers share their location, so treat them as 3595 * if they were 64bit. 3596 */ 3597 #define DBG_BCR_BVR_WCR_WVR(n) \ 3598 /* DBGBVRn */ \ 3599 { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \ 3600 /* DBGBCRn */ \ 3601 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \ 3602 /* DBGWVRn */ \ 3603 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \ 3604 /* DBGWCRn */ \ 3605 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n } 3606 3607 #define DBGBXVR(n) \ 3608 { AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_bvr, NULL, n } 3609 3610 /* 3611 * Trapped cp14 registers. We generally ignore most of the external 3612 * debug, on the principle that they don't really make sense to a 3613 * guest. Revisit this one day, would this principle change. 3614 */ 3615 static const struct sys_reg_desc cp14_regs[] = { 3616 /* DBGDIDR */ 3617 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgdidr }, 3618 /* DBGDTRRXext */ 3619 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi }, 3620 3621 DBG_BCR_BVR_WCR_WVR(0), 3622 /* DBGDSCRint */ 3623 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi }, 3624 DBG_BCR_BVR_WCR_WVR(1), 3625 /* DBGDCCINT */ 3626 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug_regs, NULL, MDCCINT_EL1 }, 3627 /* DBGDSCRext */ 3628 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug_regs, NULL, MDSCR_EL1 }, 3629 DBG_BCR_BVR_WCR_WVR(2), 3630 /* DBGDTR[RT]Xint */ 3631 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi }, 3632 /* DBGDTR[RT]Xext */ 3633 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi }, 3634 DBG_BCR_BVR_WCR_WVR(3), 3635 DBG_BCR_BVR_WCR_WVR(4), 3636 DBG_BCR_BVR_WCR_WVR(5), 3637 /* DBGWFAR */ 3638 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi }, 3639 /* DBGOSECCR */ 3640 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi }, 3641 DBG_BCR_BVR_WCR_WVR(6), 3642 /* DBGVCR */ 3643 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug_regs, NULL, DBGVCR32_EL2 }, 3644 DBG_BCR_BVR_WCR_WVR(7), 3645 DBG_BCR_BVR_WCR_WVR(8), 3646 DBG_BCR_BVR_WCR_WVR(9), 3647 DBG_BCR_BVR_WCR_WVR(10), 3648 DBG_BCR_BVR_WCR_WVR(11), 3649 DBG_BCR_BVR_WCR_WVR(12), 3650 DBG_BCR_BVR_WCR_WVR(13), 3651 DBG_BCR_BVR_WCR_WVR(14), 3652 DBG_BCR_BVR_WCR_WVR(15), 3653 3654 /* DBGDRAR (32bit) */ 3655 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi }, 3656 3657 DBGBXVR(0), 3658 /* DBGOSLAR */ 3659 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_oslar_el1 }, 3660 DBGBXVR(1), 3661 /* DBGOSLSR */ 3662 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1, NULL, OSLSR_EL1 }, 3663 DBGBXVR(2), 3664 DBGBXVR(3), 3665 /* DBGOSDLR */ 3666 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi }, 3667 DBGBXVR(4), 3668 /* DBGPRCR */ 3669 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi }, 3670 DBGBXVR(5), 3671 DBGBXVR(6), 3672 DBGBXVR(7), 3673 DBGBXVR(8), 3674 DBGBXVR(9), 3675 DBGBXVR(10), 3676 DBGBXVR(11), 3677 DBGBXVR(12), 3678 DBGBXVR(13), 3679 DBGBXVR(14), 3680 DBGBXVR(15), 3681 3682 /* DBGDSAR (32bit) */ 3683 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi }, 3684 3685 /* DBGDEVID2 */ 3686 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi }, 3687 /* DBGDEVID1 */ 3688 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi }, 3689 /* DBGDEVID */ 3690 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi }, 3691 /* DBGCLAIMSET */ 3692 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi }, 3693 /* DBGCLAIMCLR */ 3694 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi }, 3695 /* DBGAUTHSTATUS */ 3696 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 }, 3697 }; 3698 3699 /* Trapped cp14 64bit registers */ 3700 static const struct sys_reg_desc cp14_64_regs[] = { 3701 /* DBGDRAR (64bit) */ 3702 { Op1( 0), CRm( 1), .access = trap_raz_wi }, 3703 3704 /* DBGDSAR (64bit) */ 3705 { Op1( 0), CRm( 2), .access = trap_raz_wi }, 3706 }; 3707 3708 #define CP15_PMU_SYS_REG(_map, _Op1, _CRn, _CRm, _Op2) \ 3709 AA32(_map), \ 3710 Op1(_Op1), CRn(_CRn), CRm(_CRm), Op2(_Op2), \ 3711 .visibility = pmu_visibility 3712 3713 /* Macro to expand the PMEVCNTRn register */ 3714 #define PMU_PMEVCNTR(n) \ 3715 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \ 3716 (0b1000 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \ 3717 .access = access_pmu_evcntr } 3718 3719 /* Macro to expand the PMEVTYPERn register */ 3720 #define PMU_PMEVTYPER(n) \ 3721 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \ 3722 (0b1100 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \ 3723 .access = access_pmu_evtyper } 3724 /* 3725 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding, 3726 * depending on the way they are accessed (as a 32bit or a 64bit 3727 * register). 3728 */ 3729 static const struct sys_reg_desc cp15_regs[] = { 3730 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr }, 3731 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, SCTLR_EL1 }, 3732 /* ACTLR */ 3733 { AA32(LO), Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr, NULL, ACTLR_EL1 }, 3734 /* ACTLR2 */ 3735 { AA32(HI), Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr, NULL, ACTLR_EL1 }, 3736 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, 3737 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, TTBR1_EL1 }, 3738 /* TTBCR */ 3739 { AA32(LO), Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 }, 3740 /* TTBCR2 */ 3741 { AA32(HI), Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, TCR_EL1 }, 3742 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, DACR32_EL2 }, 3743 { CP15_SYS_DESC(SYS_ICC_PMR_EL1), undef_access }, 3744 /* DFSR */ 3745 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, ESR_EL1 }, 3746 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, IFSR32_EL2 }, 3747 /* ADFSR */ 3748 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, AFSR0_EL1 }, 3749 /* AIFSR */ 3750 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, AFSR1_EL1 }, 3751 /* DFAR */ 3752 { AA32(LO), Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, FAR_EL1 }, 3753 /* IFAR */ 3754 { AA32(HI), Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, FAR_EL1 }, 3755 3756 /* 3757 * DC{C,I,CI}SW operations: 3758 */ 3759 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw }, 3760 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw }, 3761 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw }, 3762 3763 /* PMU */ 3764 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 0), .access = access_pmcr }, 3765 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 1), .access = access_pmcnten }, 3766 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 2), .access = access_pmcnten }, 3767 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 3), .access = access_pmovs }, 3768 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 4), .access = access_pmswinc }, 3769 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 5), .access = access_pmselr }, 3770 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 6), .access = access_pmceid }, 3771 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 7), .access = access_pmceid }, 3772 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 0), .access = access_pmu_evcntr }, 3773 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 1), .access = access_pmu_evtyper }, 3774 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 2), .access = access_pmu_evcntr }, 3775 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 0), .access = access_pmuserenr }, 3776 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 1), .access = access_pminten }, 3777 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 2), .access = access_pminten }, 3778 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 3), .access = access_pmovs }, 3779 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 4), .access = access_pmceid }, 3780 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 5), .access = access_pmceid }, 3781 /* PMMIR */ 3782 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 6), .access = trap_raz_wi }, 3783 3784 /* PRRR/MAIR0 */ 3785 { AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 }, 3786 /* NMRR/MAIR1 */ 3787 { AA32(HI), Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, MAIR_EL1 }, 3788 /* AMAIR0 */ 3789 { AA32(LO), Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, AMAIR_EL1 }, 3790 /* AMAIR1 */ 3791 { AA32(HI), Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, AMAIR_EL1 }, 3792 3793 { CP15_SYS_DESC(SYS_ICC_IAR0_EL1), undef_access }, 3794 { CP15_SYS_DESC(SYS_ICC_EOIR0_EL1), undef_access }, 3795 { CP15_SYS_DESC(SYS_ICC_HPPIR0_EL1), undef_access }, 3796 { CP15_SYS_DESC(SYS_ICC_BPR0_EL1), undef_access }, 3797 { CP15_SYS_DESC(SYS_ICC_AP0R0_EL1), undef_access }, 3798 { CP15_SYS_DESC(SYS_ICC_AP0R1_EL1), undef_access }, 3799 { CP15_SYS_DESC(SYS_ICC_AP0R2_EL1), undef_access }, 3800 { CP15_SYS_DESC(SYS_ICC_AP0R3_EL1), undef_access }, 3801 { CP15_SYS_DESC(SYS_ICC_AP1R0_EL1), undef_access }, 3802 { CP15_SYS_DESC(SYS_ICC_AP1R1_EL1), undef_access }, 3803 { CP15_SYS_DESC(SYS_ICC_AP1R2_EL1), undef_access }, 3804 { CP15_SYS_DESC(SYS_ICC_AP1R3_EL1), undef_access }, 3805 { CP15_SYS_DESC(SYS_ICC_DIR_EL1), undef_access }, 3806 { CP15_SYS_DESC(SYS_ICC_RPR_EL1), undef_access }, 3807 { CP15_SYS_DESC(SYS_ICC_IAR1_EL1), undef_access }, 3808 { CP15_SYS_DESC(SYS_ICC_EOIR1_EL1), undef_access }, 3809 { CP15_SYS_DESC(SYS_ICC_HPPIR1_EL1), undef_access }, 3810 { CP15_SYS_DESC(SYS_ICC_BPR1_EL1), undef_access }, 3811 { CP15_SYS_DESC(SYS_ICC_CTLR_EL1), undef_access }, 3812 { CP15_SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre }, 3813 { CP15_SYS_DESC(SYS_ICC_IGRPEN0_EL1), undef_access }, 3814 { CP15_SYS_DESC(SYS_ICC_IGRPEN1_EL1), undef_access }, 3815 3816 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, CONTEXTIDR_EL1 }, 3817 3818 /* Arch Tmers */ 3819 { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer }, 3820 { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer }, 3821 3822 /* PMEVCNTRn */ 3823 PMU_PMEVCNTR(0), 3824 PMU_PMEVCNTR(1), 3825 PMU_PMEVCNTR(2), 3826 PMU_PMEVCNTR(3), 3827 PMU_PMEVCNTR(4), 3828 PMU_PMEVCNTR(5), 3829 PMU_PMEVCNTR(6), 3830 PMU_PMEVCNTR(7), 3831 PMU_PMEVCNTR(8), 3832 PMU_PMEVCNTR(9), 3833 PMU_PMEVCNTR(10), 3834 PMU_PMEVCNTR(11), 3835 PMU_PMEVCNTR(12), 3836 PMU_PMEVCNTR(13), 3837 PMU_PMEVCNTR(14), 3838 PMU_PMEVCNTR(15), 3839 PMU_PMEVCNTR(16), 3840 PMU_PMEVCNTR(17), 3841 PMU_PMEVCNTR(18), 3842 PMU_PMEVCNTR(19), 3843 PMU_PMEVCNTR(20), 3844 PMU_PMEVCNTR(21), 3845 PMU_PMEVCNTR(22), 3846 PMU_PMEVCNTR(23), 3847 PMU_PMEVCNTR(24), 3848 PMU_PMEVCNTR(25), 3849 PMU_PMEVCNTR(26), 3850 PMU_PMEVCNTR(27), 3851 PMU_PMEVCNTR(28), 3852 PMU_PMEVCNTR(29), 3853 PMU_PMEVCNTR(30), 3854 /* PMEVTYPERn */ 3855 PMU_PMEVTYPER(0), 3856 PMU_PMEVTYPER(1), 3857 PMU_PMEVTYPER(2), 3858 PMU_PMEVTYPER(3), 3859 PMU_PMEVTYPER(4), 3860 PMU_PMEVTYPER(5), 3861 PMU_PMEVTYPER(6), 3862 PMU_PMEVTYPER(7), 3863 PMU_PMEVTYPER(8), 3864 PMU_PMEVTYPER(9), 3865 PMU_PMEVTYPER(10), 3866 PMU_PMEVTYPER(11), 3867 PMU_PMEVTYPER(12), 3868 PMU_PMEVTYPER(13), 3869 PMU_PMEVTYPER(14), 3870 PMU_PMEVTYPER(15), 3871 PMU_PMEVTYPER(16), 3872 PMU_PMEVTYPER(17), 3873 PMU_PMEVTYPER(18), 3874 PMU_PMEVTYPER(19), 3875 PMU_PMEVTYPER(20), 3876 PMU_PMEVTYPER(21), 3877 PMU_PMEVTYPER(22), 3878 PMU_PMEVTYPER(23), 3879 PMU_PMEVTYPER(24), 3880 PMU_PMEVTYPER(25), 3881 PMU_PMEVTYPER(26), 3882 PMU_PMEVTYPER(27), 3883 PMU_PMEVTYPER(28), 3884 PMU_PMEVTYPER(29), 3885 PMU_PMEVTYPER(30), 3886 /* PMCCFILTR */ 3887 { CP15_PMU_SYS_REG(DIRECT, 0, 14, 15, 7), .access = access_pmu_evtyper }, 3888 3889 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr }, 3890 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr }, 3891 3892 /* CCSIDR2 */ 3893 { Op1(1), CRn( 0), CRm( 0), Op2(2), undef_access }, 3894 3895 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 }, 3896 }; 3897 3898 static const struct sys_reg_desc cp15_64_regs[] = { 3899 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, 3900 { CP15_PMU_SYS_REG(DIRECT, 0, 0, 9, 0), .access = access_pmu_evcntr }, 3901 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */ 3902 { SYS_DESC(SYS_AARCH32_CNTPCT), access_arch_timer }, 3903 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 }, 3904 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */ 3905 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */ 3906 { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer }, 3907 { SYS_DESC(SYS_AARCH32_CNTPCTSS), access_arch_timer }, 3908 }; 3909 3910 static bool check_sysreg_table(const struct sys_reg_desc *table, unsigned int n, 3911 bool is_32) 3912 { 3913 unsigned int i; 3914 3915 for (i = 0; i < n; i++) { 3916 if (!is_32 && table[i].reg && !table[i].reset) { 3917 kvm_err("sys_reg table %pS entry %d (%s) lacks reset\n", 3918 &table[i], i, table[i].name); 3919 return false; 3920 } 3921 3922 if (i && cmp_sys_reg(&table[i-1], &table[i]) >= 0) { 3923 kvm_err("sys_reg table %pS entry %d (%s -> %s) out of order\n", 3924 &table[i], i, table[i - 1].name, table[i].name); 3925 return false; 3926 } 3927 } 3928 3929 return true; 3930 } 3931 3932 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu) 3933 { 3934 kvm_inject_undefined(vcpu); 3935 return 1; 3936 } 3937 3938 static void perform_access(struct kvm_vcpu *vcpu, 3939 struct sys_reg_params *params, 3940 const struct sys_reg_desc *r) 3941 { 3942 trace_kvm_sys_access(*vcpu_pc(vcpu), params, r); 3943 3944 /* Check for regs disabled by runtime config */ 3945 if (sysreg_hidden(vcpu, r)) { 3946 kvm_inject_undefined(vcpu); 3947 return; 3948 } 3949 3950 /* 3951 * Not having an accessor means that we have configured a trap 3952 * that we don't know how to handle. This certainly qualifies 3953 * as a gross bug that should be fixed right away. 3954 */ 3955 BUG_ON(!r->access); 3956 3957 /* Skip instruction if instructed so */ 3958 if (likely(r->access(vcpu, params, r))) 3959 kvm_incr_pc(vcpu); 3960 } 3961 3962 /* 3963 * emulate_cp -- tries to match a sys_reg access in a handling table, and 3964 * call the corresponding trap handler. 3965 * 3966 * @params: pointer to the descriptor of the access 3967 * @table: array of trap descriptors 3968 * @num: size of the trap descriptor array 3969 * 3970 * Return true if the access has been handled, false if not. 3971 */ 3972 static bool emulate_cp(struct kvm_vcpu *vcpu, 3973 struct sys_reg_params *params, 3974 const struct sys_reg_desc *table, 3975 size_t num) 3976 { 3977 const struct sys_reg_desc *r; 3978 3979 if (!table) 3980 return false; /* Not handled */ 3981 3982 r = find_reg(params, table, num); 3983 3984 if (r) { 3985 perform_access(vcpu, params, r); 3986 return true; 3987 } 3988 3989 /* Not handled */ 3990 return false; 3991 } 3992 3993 static void unhandled_cp_access(struct kvm_vcpu *vcpu, 3994 struct sys_reg_params *params) 3995 { 3996 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu); 3997 int cp = -1; 3998 3999 switch (esr_ec) { 4000 case ESR_ELx_EC_CP15_32: 4001 case ESR_ELx_EC_CP15_64: 4002 cp = 15; 4003 break; 4004 case ESR_ELx_EC_CP14_MR: 4005 case ESR_ELx_EC_CP14_64: 4006 cp = 14; 4007 break; 4008 default: 4009 WARN_ON(1); 4010 } 4011 4012 print_sys_reg_msg(params, 4013 "Unsupported guest CP%d access at: %08lx [%08lx]\n", 4014 cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 4015 kvm_inject_undefined(vcpu); 4016 } 4017 4018 /** 4019 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access 4020 * @vcpu: The VCPU pointer 4021 * @global: &struct sys_reg_desc 4022 * @nr_global: size of the @global array 4023 */ 4024 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu, 4025 const struct sys_reg_desc *global, 4026 size_t nr_global) 4027 { 4028 struct sys_reg_params params; 4029 u64 esr = kvm_vcpu_get_esr(vcpu); 4030 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4031 int Rt2 = (esr >> 10) & 0x1f; 4032 4033 params.CRm = (esr >> 1) & 0xf; 4034 params.is_write = ((esr & 1) == 0); 4035 4036 params.Op0 = 0; 4037 params.Op1 = (esr >> 16) & 0xf; 4038 params.Op2 = 0; 4039 params.CRn = 0; 4040 4041 /* 4042 * Make a 64-bit value out of Rt and Rt2. As we use the same trap 4043 * backends between AArch32 and AArch64, we get away with it. 4044 */ 4045 if (params.is_write) { 4046 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff; 4047 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32; 4048 } 4049 4050 /* 4051 * If the table contains a handler, handle the 4052 * potential register operation in the case of a read and return 4053 * with success. 4054 */ 4055 if (emulate_cp(vcpu, ¶ms, global, nr_global)) { 4056 /* Split up the value between registers for the read side */ 4057 if (!params.is_write) { 4058 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval)); 4059 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval)); 4060 } 4061 4062 return 1; 4063 } 4064 4065 unhandled_cp_access(vcpu, ¶ms); 4066 return 1; 4067 } 4068 4069 static bool emulate_sys_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *params); 4070 4071 /* 4072 * The CP10 ID registers are architecturally mapped to AArch64 feature 4073 * registers. Abuse that fact so we can rely on the AArch64 handler for accesses 4074 * from AArch32. 4075 */ 4076 static bool kvm_esr_cp10_id_to_sys64(u64 esr, struct sys_reg_params *params) 4077 { 4078 u8 reg_id = (esr >> 10) & 0xf; 4079 bool valid; 4080 4081 params->is_write = ((esr & 1) == 0); 4082 params->Op0 = 3; 4083 params->Op1 = 0; 4084 params->CRn = 0; 4085 params->CRm = 3; 4086 4087 /* CP10 ID registers are read-only */ 4088 valid = !params->is_write; 4089 4090 switch (reg_id) { 4091 /* MVFR0 */ 4092 case 0b0111: 4093 params->Op2 = 0; 4094 break; 4095 /* MVFR1 */ 4096 case 0b0110: 4097 params->Op2 = 1; 4098 break; 4099 /* MVFR2 */ 4100 case 0b0101: 4101 params->Op2 = 2; 4102 break; 4103 default: 4104 valid = false; 4105 } 4106 4107 if (valid) 4108 return true; 4109 4110 kvm_pr_unimpl("Unhandled cp10 register %s: %u\n", 4111 params->is_write ? "write" : "read", reg_id); 4112 return false; 4113 } 4114 4115 /** 4116 * kvm_handle_cp10_id() - Handles a VMRS trap on guest access to a 'Media and 4117 * VFP Register' from AArch32. 4118 * @vcpu: The vCPU pointer 4119 * 4120 * MVFR{0-2} are architecturally mapped to the AArch64 MVFR{0-2}_EL1 registers. 4121 * Work out the correct AArch64 system register encoding and reroute to the 4122 * AArch64 system register emulation. 4123 */ 4124 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu) 4125 { 4126 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4127 u64 esr = kvm_vcpu_get_esr(vcpu); 4128 struct sys_reg_params params; 4129 4130 /* UNDEF on any unhandled register access */ 4131 if (!kvm_esr_cp10_id_to_sys64(esr, ¶ms)) { 4132 kvm_inject_undefined(vcpu); 4133 return 1; 4134 } 4135 4136 if (emulate_sys_reg(vcpu, ¶ms)) 4137 vcpu_set_reg(vcpu, Rt, params.regval); 4138 4139 return 1; 4140 } 4141 4142 /** 4143 * kvm_emulate_cp15_id_reg() - Handles an MRC trap on a guest CP15 access where 4144 * CRn=0, which corresponds to the AArch32 feature 4145 * registers. 4146 * @vcpu: the vCPU pointer 4147 * @params: the system register access parameters. 4148 * 4149 * Our cp15 system register tables do not enumerate the AArch32 feature 4150 * registers. Conveniently, our AArch64 table does, and the AArch32 system 4151 * register encoding can be trivially remapped into the AArch64 for the feature 4152 * registers: Append op0=3, leaving op1, CRn, CRm, and op2 the same. 4153 * 4154 * According to DDI0487G.b G7.3.1, paragraph "Behavior of VMSAv8-32 32-bit 4155 * System registers with (coproc=0b1111, CRn==c0)", read accesses from this 4156 * range are either UNKNOWN or RES0. Rerouting remains architectural as we 4157 * treat undefined registers in this range as RAZ. 4158 */ 4159 static int kvm_emulate_cp15_id_reg(struct kvm_vcpu *vcpu, 4160 struct sys_reg_params *params) 4161 { 4162 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4163 4164 /* Treat impossible writes to RO registers as UNDEFINED */ 4165 if (params->is_write) { 4166 unhandled_cp_access(vcpu, params); 4167 return 1; 4168 } 4169 4170 params->Op0 = 3; 4171 4172 /* 4173 * All registers where CRm > 3 are known to be UNKNOWN/RAZ from AArch32. 4174 * Avoid conflicting with future expansion of AArch64 feature registers 4175 * and simply treat them as RAZ here. 4176 */ 4177 if (params->CRm > 3) 4178 params->regval = 0; 4179 else if (!emulate_sys_reg(vcpu, params)) 4180 return 1; 4181 4182 vcpu_set_reg(vcpu, Rt, params->regval); 4183 return 1; 4184 } 4185 4186 /** 4187 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access 4188 * @vcpu: The VCPU pointer 4189 * @params: &struct sys_reg_params 4190 * @global: &struct sys_reg_desc 4191 * @nr_global: size of the @global array 4192 */ 4193 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu, 4194 struct sys_reg_params *params, 4195 const struct sys_reg_desc *global, 4196 size_t nr_global) 4197 { 4198 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4199 4200 params->regval = vcpu_get_reg(vcpu, Rt); 4201 4202 if (emulate_cp(vcpu, params, global, nr_global)) { 4203 if (!params->is_write) 4204 vcpu_set_reg(vcpu, Rt, params->regval); 4205 return 1; 4206 } 4207 4208 unhandled_cp_access(vcpu, params); 4209 return 1; 4210 } 4211 4212 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu) 4213 { 4214 return kvm_handle_cp_64(vcpu, cp15_64_regs, ARRAY_SIZE(cp15_64_regs)); 4215 } 4216 4217 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu) 4218 { 4219 struct sys_reg_params params; 4220 4221 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu)); 4222 4223 /* 4224 * Certain AArch32 ID registers are handled by rerouting to the AArch64 4225 * system register table. Registers in the ID range where CRm=0 are 4226 * excluded from this scheme as they do not trivially map into AArch64 4227 * system register encodings. 4228 */ 4229 if (params.Op1 == 0 && params.CRn == 0 && params.CRm) 4230 return kvm_emulate_cp15_id_reg(vcpu, ¶ms); 4231 4232 return kvm_handle_cp_32(vcpu, ¶ms, cp15_regs, ARRAY_SIZE(cp15_regs)); 4233 } 4234 4235 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu) 4236 { 4237 return kvm_handle_cp_64(vcpu, cp14_64_regs, ARRAY_SIZE(cp14_64_regs)); 4238 } 4239 4240 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu) 4241 { 4242 struct sys_reg_params params; 4243 4244 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu)); 4245 4246 return kvm_handle_cp_32(vcpu, ¶ms, cp14_regs, ARRAY_SIZE(cp14_regs)); 4247 } 4248 4249 /** 4250 * emulate_sys_reg - Emulate a guest access to an AArch64 system register 4251 * @vcpu: The VCPU pointer 4252 * @params: Decoded system register parameters 4253 * 4254 * Return: true if the system register access was successful, false otherwise. 4255 */ 4256 static bool emulate_sys_reg(struct kvm_vcpu *vcpu, 4257 struct sys_reg_params *params) 4258 { 4259 const struct sys_reg_desc *r; 4260 4261 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 4262 if (likely(r)) { 4263 perform_access(vcpu, params, r); 4264 return true; 4265 } 4266 4267 print_sys_reg_msg(params, 4268 "Unsupported guest sys_reg access at: %lx [%08lx]\n", 4269 *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 4270 kvm_inject_undefined(vcpu); 4271 4272 return false; 4273 } 4274 4275 static const struct sys_reg_desc *idregs_debug_find(struct kvm *kvm, u8 pos) 4276 { 4277 unsigned long i, idreg_idx = 0; 4278 4279 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { 4280 const struct sys_reg_desc *r = &sys_reg_descs[i]; 4281 4282 if (!is_vm_ftr_id_reg(reg_to_encoding(r))) 4283 continue; 4284 4285 if (idreg_idx == pos) 4286 return r; 4287 4288 idreg_idx++; 4289 } 4290 4291 return NULL; 4292 } 4293 4294 static void *idregs_debug_start(struct seq_file *s, loff_t *pos) 4295 { 4296 struct kvm *kvm = s->private; 4297 u8 *iter; 4298 4299 mutex_lock(&kvm->arch.config_lock); 4300 4301 iter = &kvm->arch.idreg_debugfs_iter; 4302 if (test_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags) && 4303 *iter == (u8)~0) { 4304 *iter = *pos; 4305 if (!idregs_debug_find(kvm, *iter)) 4306 iter = NULL; 4307 } else { 4308 iter = ERR_PTR(-EBUSY); 4309 } 4310 4311 mutex_unlock(&kvm->arch.config_lock); 4312 4313 return iter; 4314 } 4315 4316 static void *idregs_debug_next(struct seq_file *s, void *v, loff_t *pos) 4317 { 4318 struct kvm *kvm = s->private; 4319 4320 (*pos)++; 4321 4322 if (idregs_debug_find(kvm, kvm->arch.idreg_debugfs_iter + 1)) { 4323 kvm->arch.idreg_debugfs_iter++; 4324 4325 return &kvm->arch.idreg_debugfs_iter; 4326 } 4327 4328 return NULL; 4329 } 4330 4331 static void idregs_debug_stop(struct seq_file *s, void *v) 4332 { 4333 struct kvm *kvm = s->private; 4334 4335 if (IS_ERR(v)) 4336 return; 4337 4338 mutex_lock(&kvm->arch.config_lock); 4339 4340 kvm->arch.idreg_debugfs_iter = ~0; 4341 4342 mutex_unlock(&kvm->arch.config_lock); 4343 } 4344 4345 static int idregs_debug_show(struct seq_file *s, void *v) 4346 { 4347 const struct sys_reg_desc *desc; 4348 struct kvm *kvm = s->private; 4349 4350 desc = idregs_debug_find(kvm, kvm->arch.idreg_debugfs_iter); 4351 4352 if (!desc->name) 4353 return 0; 4354 4355 seq_printf(s, "%20s:\t%016llx\n", 4356 desc->name, kvm_read_vm_id_reg(kvm, reg_to_encoding(desc))); 4357 4358 return 0; 4359 } 4360 4361 static const struct seq_operations idregs_debug_sops = { 4362 .start = idregs_debug_start, 4363 .next = idregs_debug_next, 4364 .stop = idregs_debug_stop, 4365 .show = idregs_debug_show, 4366 }; 4367 4368 DEFINE_SEQ_ATTRIBUTE(idregs_debug); 4369 4370 void kvm_sys_regs_create_debugfs(struct kvm *kvm) 4371 { 4372 kvm->arch.idreg_debugfs_iter = ~0; 4373 4374 debugfs_create_file("idregs", 0444, kvm->debugfs_dentry, kvm, 4375 &idregs_debug_fops); 4376 } 4377 4378 static void reset_vm_ftr_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *reg) 4379 { 4380 u32 id = reg_to_encoding(reg); 4381 struct kvm *kvm = vcpu->kvm; 4382 4383 if (test_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags)) 4384 return; 4385 4386 kvm_set_vm_id_reg(kvm, id, reg->reset(vcpu, reg)); 4387 } 4388 4389 static void reset_vcpu_ftr_id_reg(struct kvm_vcpu *vcpu, 4390 const struct sys_reg_desc *reg) 4391 { 4392 if (kvm_vcpu_initialized(vcpu)) 4393 return; 4394 4395 reg->reset(vcpu, reg); 4396 } 4397 4398 /** 4399 * kvm_reset_sys_regs - sets system registers to reset value 4400 * @vcpu: The VCPU pointer 4401 * 4402 * This function finds the right table above and sets the registers on the 4403 * virtual CPU struct to their architecturally defined reset values. 4404 */ 4405 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu) 4406 { 4407 struct kvm *kvm = vcpu->kvm; 4408 unsigned long i; 4409 4410 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { 4411 const struct sys_reg_desc *r = &sys_reg_descs[i]; 4412 4413 if (!r->reset) 4414 continue; 4415 4416 if (is_vm_ftr_id_reg(reg_to_encoding(r))) 4417 reset_vm_ftr_id_reg(vcpu, r); 4418 else if (is_vcpu_ftr_id_reg(reg_to_encoding(r))) 4419 reset_vcpu_ftr_id_reg(vcpu, r); 4420 else 4421 r->reset(vcpu, r); 4422 } 4423 4424 set_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags); 4425 } 4426 4427 /** 4428 * kvm_handle_sys_reg -- handles a system instruction or mrs/msr instruction 4429 * trap on a guest execution 4430 * @vcpu: The VCPU pointer 4431 */ 4432 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu) 4433 { 4434 const struct sys_reg_desc *desc = NULL; 4435 struct sys_reg_params params; 4436 unsigned long esr = kvm_vcpu_get_esr(vcpu); 4437 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4438 int sr_idx; 4439 4440 trace_kvm_handle_sys_reg(esr); 4441 4442 if (triage_sysreg_trap(vcpu, &sr_idx)) 4443 return 1; 4444 4445 params = esr_sys64_to_params(esr); 4446 params.regval = vcpu_get_reg(vcpu, Rt); 4447 4448 /* System registers have Op0=={2,3}, as per DDI487 J.a C5.1.2 */ 4449 if (params.Op0 == 2 || params.Op0 == 3) 4450 desc = &sys_reg_descs[sr_idx]; 4451 else 4452 desc = &sys_insn_descs[sr_idx]; 4453 4454 perform_access(vcpu, ¶ms, desc); 4455 4456 /* Read from system register? */ 4457 if (!params.is_write && 4458 (params.Op0 == 2 || params.Op0 == 3)) 4459 vcpu_set_reg(vcpu, Rt, params.regval); 4460 4461 return 1; 4462 } 4463 4464 /****************************************************************************** 4465 * Userspace API 4466 *****************************************************************************/ 4467 4468 static bool index_to_params(u64 id, struct sys_reg_params *params) 4469 { 4470 switch (id & KVM_REG_SIZE_MASK) { 4471 case KVM_REG_SIZE_U64: 4472 /* Any unused index bits means it's not valid. */ 4473 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK 4474 | KVM_REG_ARM_COPROC_MASK 4475 | KVM_REG_ARM64_SYSREG_OP0_MASK 4476 | KVM_REG_ARM64_SYSREG_OP1_MASK 4477 | KVM_REG_ARM64_SYSREG_CRN_MASK 4478 | KVM_REG_ARM64_SYSREG_CRM_MASK 4479 | KVM_REG_ARM64_SYSREG_OP2_MASK)) 4480 return false; 4481 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK) 4482 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT); 4483 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK) 4484 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT); 4485 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK) 4486 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT); 4487 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK) 4488 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT); 4489 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK) 4490 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT); 4491 return true; 4492 default: 4493 return false; 4494 } 4495 } 4496 4497 const struct sys_reg_desc *get_reg_by_id(u64 id, 4498 const struct sys_reg_desc table[], 4499 unsigned int num) 4500 { 4501 struct sys_reg_params params; 4502 4503 if (!index_to_params(id, ¶ms)) 4504 return NULL; 4505 4506 return find_reg(¶ms, table, num); 4507 } 4508 4509 /* Decode an index value, and find the sys_reg_desc entry. */ 4510 static const struct sys_reg_desc * 4511 id_to_sys_reg_desc(struct kvm_vcpu *vcpu, u64 id, 4512 const struct sys_reg_desc table[], unsigned int num) 4513 4514 { 4515 const struct sys_reg_desc *r; 4516 4517 /* We only do sys_reg for now. */ 4518 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG) 4519 return NULL; 4520 4521 r = get_reg_by_id(id, table, num); 4522 4523 /* Not saved in the sys_reg array and not otherwise accessible? */ 4524 if (r && (!(r->reg || r->get_user) || sysreg_hidden(vcpu, r))) 4525 r = NULL; 4526 4527 return r; 4528 } 4529 4530 /* 4531 * These are the invariant sys_reg registers: we let the guest see the 4532 * host versions of these, so they're part of the guest state. 4533 * 4534 * A future CPU may provide a mechanism to present different values to 4535 * the guest, or a future kvm may trap them. 4536 */ 4537 4538 #define FUNCTION_INVARIANT(reg) \ 4539 static u64 reset_##reg(struct kvm_vcpu *v, \ 4540 const struct sys_reg_desc *r) \ 4541 { \ 4542 ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \ 4543 return ((struct sys_reg_desc *)r)->val; \ 4544 } 4545 4546 FUNCTION_INVARIANT(midr_el1) 4547 FUNCTION_INVARIANT(revidr_el1) 4548 FUNCTION_INVARIANT(aidr_el1) 4549 4550 /* ->val is filled in by kvm_sys_reg_table_init() */ 4551 static struct sys_reg_desc invariant_sys_regs[] __ro_after_init = { 4552 { SYS_DESC(SYS_MIDR_EL1), NULL, reset_midr_el1 }, 4553 { SYS_DESC(SYS_REVIDR_EL1), NULL, reset_revidr_el1 }, 4554 { SYS_DESC(SYS_AIDR_EL1), NULL, reset_aidr_el1 }, 4555 }; 4556 4557 static int get_invariant_sys_reg(u64 id, u64 __user *uaddr) 4558 { 4559 const struct sys_reg_desc *r; 4560 4561 r = get_reg_by_id(id, invariant_sys_regs, 4562 ARRAY_SIZE(invariant_sys_regs)); 4563 if (!r) 4564 return -ENOENT; 4565 4566 return put_user(r->val, uaddr); 4567 } 4568 4569 static int set_invariant_sys_reg(u64 id, u64 __user *uaddr) 4570 { 4571 const struct sys_reg_desc *r; 4572 u64 val; 4573 4574 r = get_reg_by_id(id, invariant_sys_regs, 4575 ARRAY_SIZE(invariant_sys_regs)); 4576 if (!r) 4577 return -ENOENT; 4578 4579 if (get_user(val, uaddr)) 4580 return -EFAULT; 4581 4582 /* This is what we mean by invariant: you can't change it. */ 4583 if (r->val != val) 4584 return -EINVAL; 4585 4586 return 0; 4587 } 4588 4589 static int demux_c15_get(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) 4590 { 4591 u32 val; 4592 u32 __user *uval = uaddr; 4593 4594 /* Fail if we have unknown bits set. */ 4595 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 4596 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 4597 return -ENOENT; 4598 4599 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 4600 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 4601 if (KVM_REG_SIZE(id) != 4) 4602 return -ENOENT; 4603 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 4604 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 4605 if (val >= CSSELR_MAX) 4606 return -ENOENT; 4607 4608 return put_user(get_ccsidr(vcpu, val), uval); 4609 default: 4610 return -ENOENT; 4611 } 4612 } 4613 4614 static int demux_c15_set(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) 4615 { 4616 u32 val, newval; 4617 u32 __user *uval = uaddr; 4618 4619 /* Fail if we have unknown bits set. */ 4620 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 4621 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 4622 return -ENOENT; 4623 4624 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 4625 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 4626 if (KVM_REG_SIZE(id) != 4) 4627 return -ENOENT; 4628 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 4629 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 4630 if (val >= CSSELR_MAX) 4631 return -ENOENT; 4632 4633 if (get_user(newval, uval)) 4634 return -EFAULT; 4635 4636 return set_ccsidr(vcpu, val, newval); 4637 default: 4638 return -ENOENT; 4639 } 4640 } 4641 4642 int kvm_sys_reg_get_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg, 4643 const struct sys_reg_desc table[], unsigned int num) 4644 { 4645 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr; 4646 const struct sys_reg_desc *r; 4647 u64 val; 4648 int ret; 4649 4650 r = id_to_sys_reg_desc(vcpu, reg->id, table, num); 4651 if (!r || sysreg_hidden(vcpu, r)) 4652 return -ENOENT; 4653 4654 if (r->get_user) { 4655 ret = (r->get_user)(vcpu, r, &val); 4656 } else { 4657 val = __vcpu_sys_reg(vcpu, r->reg); 4658 ret = 0; 4659 } 4660 4661 if (!ret) 4662 ret = put_user(val, uaddr); 4663 4664 return ret; 4665 } 4666 4667 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 4668 { 4669 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 4670 int err; 4671 4672 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 4673 return demux_c15_get(vcpu, reg->id, uaddr); 4674 4675 err = get_invariant_sys_reg(reg->id, uaddr); 4676 if (err != -ENOENT) 4677 return err; 4678 4679 return kvm_sys_reg_get_user(vcpu, reg, 4680 sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 4681 } 4682 4683 int kvm_sys_reg_set_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg, 4684 const struct sys_reg_desc table[], unsigned int num) 4685 { 4686 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr; 4687 const struct sys_reg_desc *r; 4688 u64 val; 4689 int ret; 4690 4691 if (get_user(val, uaddr)) 4692 return -EFAULT; 4693 4694 r = id_to_sys_reg_desc(vcpu, reg->id, table, num); 4695 if (!r || sysreg_hidden(vcpu, r)) 4696 return -ENOENT; 4697 4698 if (sysreg_user_write_ignore(vcpu, r)) 4699 return 0; 4700 4701 if (r->set_user) { 4702 ret = (r->set_user)(vcpu, r, val); 4703 } else { 4704 __vcpu_sys_reg(vcpu, r->reg) = val; 4705 ret = 0; 4706 } 4707 4708 return ret; 4709 } 4710 4711 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 4712 { 4713 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 4714 int err; 4715 4716 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 4717 return demux_c15_set(vcpu, reg->id, uaddr); 4718 4719 err = set_invariant_sys_reg(reg->id, uaddr); 4720 if (err != -ENOENT) 4721 return err; 4722 4723 return kvm_sys_reg_set_user(vcpu, reg, 4724 sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 4725 } 4726 4727 static unsigned int num_demux_regs(void) 4728 { 4729 return CSSELR_MAX; 4730 } 4731 4732 static int write_demux_regids(u64 __user *uindices) 4733 { 4734 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX; 4735 unsigned int i; 4736 4737 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR; 4738 for (i = 0; i < CSSELR_MAX; i++) { 4739 if (put_user(val | i, uindices)) 4740 return -EFAULT; 4741 uindices++; 4742 } 4743 return 0; 4744 } 4745 4746 static u64 sys_reg_to_index(const struct sys_reg_desc *reg) 4747 { 4748 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | 4749 KVM_REG_ARM64_SYSREG | 4750 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) | 4751 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) | 4752 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) | 4753 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) | 4754 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT)); 4755 } 4756 4757 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind) 4758 { 4759 if (!*uind) 4760 return true; 4761 4762 if (put_user(sys_reg_to_index(reg), *uind)) 4763 return false; 4764 4765 (*uind)++; 4766 return true; 4767 } 4768 4769 static int walk_one_sys_reg(const struct kvm_vcpu *vcpu, 4770 const struct sys_reg_desc *rd, 4771 u64 __user **uind, 4772 unsigned int *total) 4773 { 4774 /* 4775 * Ignore registers we trap but don't save, 4776 * and for which no custom user accessor is provided. 4777 */ 4778 if (!(rd->reg || rd->get_user)) 4779 return 0; 4780 4781 if (sysreg_hidden(vcpu, rd)) 4782 return 0; 4783 4784 if (!copy_reg_to_user(rd, uind)) 4785 return -EFAULT; 4786 4787 (*total)++; 4788 return 0; 4789 } 4790 4791 /* Assumed ordered tables, see kvm_sys_reg_table_init. */ 4792 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind) 4793 { 4794 const struct sys_reg_desc *i2, *end2; 4795 unsigned int total = 0; 4796 int err; 4797 4798 i2 = sys_reg_descs; 4799 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs); 4800 4801 while (i2 != end2) { 4802 err = walk_one_sys_reg(vcpu, i2++, &uind, &total); 4803 if (err) 4804 return err; 4805 } 4806 return total; 4807 } 4808 4809 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu) 4810 { 4811 return ARRAY_SIZE(invariant_sys_regs) 4812 + num_demux_regs() 4813 + walk_sys_regs(vcpu, (u64 __user *)NULL); 4814 } 4815 4816 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) 4817 { 4818 unsigned int i; 4819 int err; 4820 4821 /* Then give them all the invariant registers' indices. */ 4822 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) { 4823 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices)) 4824 return -EFAULT; 4825 uindices++; 4826 } 4827 4828 err = walk_sys_regs(vcpu, uindices); 4829 if (err < 0) 4830 return err; 4831 uindices += err; 4832 4833 return write_demux_regids(uindices); 4834 } 4835 4836 #define KVM_ARM_FEATURE_ID_RANGE_INDEX(r) \ 4837 KVM_ARM_FEATURE_ID_RANGE_IDX(sys_reg_Op0(r), \ 4838 sys_reg_Op1(r), \ 4839 sys_reg_CRn(r), \ 4840 sys_reg_CRm(r), \ 4841 sys_reg_Op2(r)) 4842 4843 int kvm_vm_ioctl_get_reg_writable_masks(struct kvm *kvm, struct reg_mask_range *range) 4844 { 4845 const void *zero_page = page_to_virt(ZERO_PAGE(0)); 4846 u64 __user *masks = (u64 __user *)range->addr; 4847 4848 /* Only feature id range is supported, reserved[13] must be zero. */ 4849 if (range->range || 4850 memcmp(range->reserved, zero_page, sizeof(range->reserved))) 4851 return -EINVAL; 4852 4853 /* Wipe the whole thing first */ 4854 if (clear_user(masks, KVM_ARM_FEATURE_ID_RANGE_SIZE * sizeof(__u64))) 4855 return -EFAULT; 4856 4857 for (int i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { 4858 const struct sys_reg_desc *reg = &sys_reg_descs[i]; 4859 u32 encoding = reg_to_encoding(reg); 4860 u64 val; 4861 4862 if (!is_feature_id_reg(encoding) || !reg->set_user) 4863 continue; 4864 4865 if (!reg->val || 4866 (is_aa32_id_reg(encoding) && !kvm_supports_32bit_el0())) { 4867 continue; 4868 } 4869 val = reg->val; 4870 4871 if (put_user(val, (masks + KVM_ARM_FEATURE_ID_RANGE_INDEX(encoding)))) 4872 return -EFAULT; 4873 } 4874 4875 return 0; 4876 } 4877 4878 static void vcpu_set_hcr(struct kvm_vcpu *vcpu) 4879 { 4880 struct kvm *kvm = vcpu->kvm; 4881 4882 if (has_vhe() || has_hvhe()) 4883 vcpu->arch.hcr_el2 |= HCR_E2H; 4884 if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN)) { 4885 /* route synchronous external abort exceptions to EL2 */ 4886 vcpu->arch.hcr_el2 |= HCR_TEA; 4887 /* trap error record accesses */ 4888 vcpu->arch.hcr_el2 |= HCR_TERR; 4889 } 4890 4891 if (cpus_have_final_cap(ARM64_HAS_STAGE2_FWB)) 4892 vcpu->arch.hcr_el2 |= HCR_FWB; 4893 4894 if (cpus_have_final_cap(ARM64_HAS_EVT) && 4895 !cpus_have_final_cap(ARM64_MISMATCHED_CACHE_TYPE) && 4896 kvm_read_vm_id_reg(kvm, SYS_CTR_EL0) == read_sanitised_ftr_reg(SYS_CTR_EL0)) 4897 vcpu->arch.hcr_el2 |= HCR_TID4; 4898 else 4899 vcpu->arch.hcr_el2 |= HCR_TID2; 4900 4901 if (vcpu_el1_is_32bit(vcpu)) 4902 vcpu->arch.hcr_el2 &= ~HCR_RW; 4903 4904 if (kvm_has_mte(vcpu->kvm)) 4905 vcpu->arch.hcr_el2 |= HCR_ATA; 4906 4907 /* 4908 * In the absence of FGT, we cannot independently trap TLBI 4909 * Range instructions. This isn't great, but trapping all 4910 * TLBIs would be far worse. Live with it... 4911 */ 4912 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 4913 vcpu->arch.hcr_el2 |= HCR_TTLBOS; 4914 } 4915 4916 void kvm_calculate_traps(struct kvm_vcpu *vcpu) 4917 { 4918 struct kvm *kvm = vcpu->kvm; 4919 4920 mutex_lock(&kvm->arch.config_lock); 4921 vcpu_set_hcr(vcpu); 4922 vcpu_set_ich_hcr(vcpu); 4923 4924 if (cpus_have_final_cap(ARM64_HAS_HCX)) { 4925 /* 4926 * In general, all HCRX_EL2 bits are gated by a feature. 4927 * The only reason we can set SMPME without checking any 4928 * feature is that its effects are not directly observable 4929 * from the guest. 4930 */ 4931 vcpu->arch.hcrx_el2 = HCRX_EL2_SMPME; 4932 4933 if (kvm_has_feat(kvm, ID_AA64ISAR2_EL1, MOPS, IMP)) 4934 vcpu->arch.hcrx_el2 |= (HCRX_EL2_MSCEn | HCRX_EL2_MCE2); 4935 4936 if (kvm_has_tcr2(kvm)) 4937 vcpu->arch.hcrx_el2 |= HCRX_EL2_TCR2En; 4938 4939 if (kvm_has_fpmr(kvm)) 4940 vcpu->arch.hcrx_el2 |= HCRX_EL2_EnFPM; 4941 } 4942 4943 if (test_bit(KVM_ARCH_FLAG_FGU_INITIALIZED, &kvm->arch.flags)) 4944 goto out; 4945 4946 kvm->arch.fgu[HFGxTR_GROUP] = (HFGxTR_EL2_nAMAIR2_EL1 | 4947 HFGxTR_EL2_nMAIR2_EL1 | 4948 HFGxTR_EL2_nS2POR_EL1 | 4949 HFGxTR_EL2_nACCDATA_EL1 | 4950 HFGxTR_EL2_nSMPRI_EL1_MASK | 4951 HFGxTR_EL2_nTPIDR2_EL0_MASK); 4952 4953 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 4954 kvm->arch.fgu[HFGITR_GROUP] |= (HFGITR_EL2_TLBIRVAALE1OS| 4955 HFGITR_EL2_TLBIRVALE1OS | 4956 HFGITR_EL2_TLBIRVAAE1OS | 4957 HFGITR_EL2_TLBIRVAE1OS | 4958 HFGITR_EL2_TLBIVAALE1OS | 4959 HFGITR_EL2_TLBIVALE1OS | 4960 HFGITR_EL2_TLBIVAAE1OS | 4961 HFGITR_EL2_TLBIASIDE1OS | 4962 HFGITR_EL2_TLBIVAE1OS | 4963 HFGITR_EL2_TLBIVMALLE1OS); 4964 4965 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE)) 4966 kvm->arch.fgu[HFGITR_GROUP] |= (HFGITR_EL2_TLBIRVAALE1 | 4967 HFGITR_EL2_TLBIRVALE1 | 4968 HFGITR_EL2_TLBIRVAAE1 | 4969 HFGITR_EL2_TLBIRVAE1 | 4970 HFGITR_EL2_TLBIRVAALE1IS| 4971 HFGITR_EL2_TLBIRVALE1IS | 4972 HFGITR_EL2_TLBIRVAAE1IS | 4973 HFGITR_EL2_TLBIRVAE1IS | 4974 HFGITR_EL2_TLBIRVAALE1OS| 4975 HFGITR_EL2_TLBIRVALE1OS | 4976 HFGITR_EL2_TLBIRVAAE1OS | 4977 HFGITR_EL2_TLBIRVAE1OS); 4978 4979 if (!kvm_has_feat(kvm, ID_AA64ISAR2_EL1, ATS1A, IMP)) 4980 kvm->arch.fgu[HFGITR_GROUP] |= HFGITR_EL2_ATS1E1A; 4981 4982 if (!kvm_has_feat(kvm, ID_AA64MMFR1_EL1, PAN, PAN2)) 4983 kvm->arch.fgu[HFGITR_GROUP] |= (HFGITR_EL2_ATS1E1RP | 4984 HFGITR_EL2_ATS1E1WP); 4985 4986 if (!kvm_has_s1pie(kvm)) 4987 kvm->arch.fgu[HFGxTR_GROUP] |= (HFGxTR_EL2_nPIRE0_EL1 | 4988 HFGxTR_EL2_nPIR_EL1); 4989 4990 if (!kvm_has_s1poe(kvm)) 4991 kvm->arch.fgu[HFGxTR_GROUP] |= (HFGxTR_EL2_nPOR_EL1 | 4992 HFGxTR_EL2_nPOR_EL0); 4993 4994 if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, AMU, IMP)) 4995 kvm->arch.fgu[HAFGRTR_GROUP] |= ~(HAFGRTR_EL2_RES0 | 4996 HAFGRTR_EL2_RES1); 4997 4998 set_bit(KVM_ARCH_FLAG_FGU_INITIALIZED, &kvm->arch.flags); 4999 out: 5000 mutex_unlock(&kvm->arch.config_lock); 5001 } 5002 5003 /* 5004 * Perform last adjustments to the ID registers that are implied by the 5005 * configuration outside of the ID regs themselves, as well as any 5006 * initialisation that directly depend on these ID registers (such as 5007 * RES0/RES1 behaviours). This is not the place to configure traps though. 5008 * 5009 * Because this can be called once per CPU, changes must be idempotent. 5010 */ 5011 int kvm_finalize_sys_regs(struct kvm_vcpu *vcpu) 5012 { 5013 struct kvm *kvm = vcpu->kvm; 5014 5015 guard(mutex)(&kvm->arch.config_lock); 5016 5017 if (!(static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif) && 5018 irqchip_in_kernel(kvm) && 5019 kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3)) { 5020 kvm->arch.id_regs[IDREG_IDX(SYS_ID_AA64PFR0_EL1)] &= ~ID_AA64PFR0_EL1_GIC_MASK; 5021 kvm->arch.id_regs[IDREG_IDX(SYS_ID_PFR1_EL1)] &= ~ID_PFR1_EL1_GIC_MASK; 5022 } 5023 5024 if (vcpu_has_nv(vcpu)) { 5025 int ret = kvm_init_nv_sysregs(kvm); 5026 if (ret) 5027 return ret; 5028 } 5029 5030 return 0; 5031 } 5032 5033 int __init kvm_sys_reg_table_init(void) 5034 { 5035 bool valid = true; 5036 unsigned int i; 5037 int ret = 0; 5038 5039 /* Make sure tables are unique and in order. */ 5040 valid &= check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), false); 5041 valid &= check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), true); 5042 valid &= check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), true); 5043 valid &= check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), true); 5044 valid &= check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), true); 5045 valid &= check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs), false); 5046 valid &= check_sysreg_table(sys_insn_descs, ARRAY_SIZE(sys_insn_descs), false); 5047 5048 if (!valid) 5049 return -EINVAL; 5050 5051 /* We abuse the reset function to overwrite the table itself. */ 5052 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) 5053 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]); 5054 5055 ret = populate_nv_trap_config(); 5056 5057 for (i = 0; !ret && i < ARRAY_SIZE(sys_reg_descs); i++) 5058 ret = populate_sysreg_config(sys_reg_descs + i, i); 5059 5060 for (i = 0; !ret && i < ARRAY_SIZE(sys_insn_descs); i++) 5061 ret = populate_sysreg_config(sys_insn_descs + i, i); 5062 5063 return ret; 5064 } 5065