1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/kvm/coproc.c: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Authors: Rusty Russell <rusty@rustcorp.com.au> 9 * Christoffer Dall <c.dall@virtualopensystems.com> 10 */ 11 12 #include <linux/bitfield.h> 13 #include <linux/bsearch.h> 14 #include <linux/cacheinfo.h> 15 #include <linux/debugfs.h> 16 #include <linux/kvm_host.h> 17 #include <linux/mm.h> 18 #include <linux/printk.h> 19 #include <linux/uaccess.h> 20 21 #include <asm/cacheflush.h> 22 #include <asm/cputype.h> 23 #include <asm/debug-monitors.h> 24 #include <asm/esr.h> 25 #include <asm/kvm_arm.h> 26 #include <asm/kvm_emulate.h> 27 #include <asm/kvm_hyp.h> 28 #include <asm/kvm_mmu.h> 29 #include <asm/kvm_nested.h> 30 #include <asm/perf_event.h> 31 #include <asm/sysreg.h> 32 33 #include <trace/events/kvm.h> 34 35 #include "sys_regs.h" 36 37 #include "trace.h" 38 39 /* 40 * For AArch32, we only take care of what is being trapped. Anything 41 * that has to do with init and userspace access has to go via the 42 * 64bit interface. 43 */ 44 45 static u64 sys_reg_to_index(const struct sys_reg_desc *reg); 46 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 47 u64 val); 48 49 static bool bad_trap(struct kvm_vcpu *vcpu, 50 struct sys_reg_params *params, 51 const struct sys_reg_desc *r, 52 const char *msg) 53 { 54 WARN_ONCE(1, "Unexpected %s\n", msg); 55 print_sys_reg_instr(params); 56 kvm_inject_undefined(vcpu); 57 return false; 58 } 59 60 static bool read_from_write_only(struct kvm_vcpu *vcpu, 61 struct sys_reg_params *params, 62 const struct sys_reg_desc *r) 63 { 64 return bad_trap(vcpu, params, r, 65 "sys_reg read to write-only register"); 66 } 67 68 static bool write_to_read_only(struct kvm_vcpu *vcpu, 69 struct sys_reg_params *params, 70 const struct sys_reg_desc *r) 71 { 72 return bad_trap(vcpu, params, r, 73 "sys_reg write to read-only register"); 74 } 75 76 #define PURE_EL2_SYSREG(el2) \ 77 case el2: { \ 78 *el1r = el2; \ 79 return true; \ 80 } 81 82 #define MAPPED_EL2_SYSREG(el2, el1, fn) \ 83 case el2: { \ 84 *xlate = fn; \ 85 *el1r = el1; \ 86 return true; \ 87 } 88 89 static bool get_el2_to_el1_mapping(unsigned int reg, 90 unsigned int *el1r, u64 (**xlate)(u64)) 91 { 92 switch (reg) { 93 PURE_EL2_SYSREG( VPIDR_EL2 ); 94 PURE_EL2_SYSREG( VMPIDR_EL2 ); 95 PURE_EL2_SYSREG( ACTLR_EL2 ); 96 PURE_EL2_SYSREG( HCR_EL2 ); 97 PURE_EL2_SYSREG( MDCR_EL2 ); 98 PURE_EL2_SYSREG( HSTR_EL2 ); 99 PURE_EL2_SYSREG( HACR_EL2 ); 100 PURE_EL2_SYSREG( VTTBR_EL2 ); 101 PURE_EL2_SYSREG( VTCR_EL2 ); 102 PURE_EL2_SYSREG( RVBAR_EL2 ); 103 PURE_EL2_SYSREG( TPIDR_EL2 ); 104 PURE_EL2_SYSREG( HPFAR_EL2 ); 105 PURE_EL2_SYSREG( CNTHCTL_EL2 ); 106 MAPPED_EL2_SYSREG(SCTLR_EL2, SCTLR_EL1, 107 translate_sctlr_el2_to_sctlr_el1 ); 108 MAPPED_EL2_SYSREG(CPTR_EL2, CPACR_EL1, 109 translate_cptr_el2_to_cpacr_el1 ); 110 MAPPED_EL2_SYSREG(TTBR0_EL2, TTBR0_EL1, 111 translate_ttbr0_el2_to_ttbr0_el1 ); 112 MAPPED_EL2_SYSREG(TTBR1_EL2, TTBR1_EL1, NULL ); 113 MAPPED_EL2_SYSREG(TCR_EL2, TCR_EL1, 114 translate_tcr_el2_to_tcr_el1 ); 115 MAPPED_EL2_SYSREG(VBAR_EL2, VBAR_EL1, NULL ); 116 MAPPED_EL2_SYSREG(AFSR0_EL2, AFSR0_EL1, NULL ); 117 MAPPED_EL2_SYSREG(AFSR1_EL2, AFSR1_EL1, NULL ); 118 MAPPED_EL2_SYSREG(ESR_EL2, ESR_EL1, NULL ); 119 MAPPED_EL2_SYSREG(FAR_EL2, FAR_EL1, NULL ); 120 MAPPED_EL2_SYSREG(MAIR_EL2, MAIR_EL1, NULL ); 121 MAPPED_EL2_SYSREG(AMAIR_EL2, AMAIR_EL1, NULL ); 122 MAPPED_EL2_SYSREG(ELR_EL2, ELR_EL1, NULL ); 123 MAPPED_EL2_SYSREG(SPSR_EL2, SPSR_EL1, NULL ); 124 MAPPED_EL2_SYSREG(ZCR_EL2, ZCR_EL1, NULL ); 125 default: 126 return false; 127 } 128 } 129 130 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg) 131 { 132 u64 val = 0x8badf00d8badf00d; 133 u64 (*xlate)(u64) = NULL; 134 unsigned int el1r; 135 136 if (!vcpu_get_flag(vcpu, SYSREGS_ON_CPU)) 137 goto memory_read; 138 139 if (unlikely(get_el2_to_el1_mapping(reg, &el1r, &xlate))) { 140 if (!is_hyp_ctxt(vcpu)) 141 goto memory_read; 142 143 /* 144 * If this register does not have an EL1 counterpart, 145 * then read the stored EL2 version. 146 */ 147 if (reg == el1r) 148 goto memory_read; 149 150 /* 151 * If we have a non-VHE guest and that the sysreg 152 * requires translation to be used at EL1, use the 153 * in-memory copy instead. 154 */ 155 if (!vcpu_el2_e2h_is_set(vcpu) && xlate) 156 goto memory_read; 157 158 /* Get the current version of the EL1 counterpart. */ 159 WARN_ON(!__vcpu_read_sys_reg_from_cpu(el1r, &val)); 160 return val; 161 } 162 163 /* EL1 register can't be on the CPU if the guest is in vEL2. */ 164 if (unlikely(is_hyp_ctxt(vcpu))) 165 goto memory_read; 166 167 if (__vcpu_read_sys_reg_from_cpu(reg, &val)) 168 return val; 169 170 memory_read: 171 return __vcpu_sys_reg(vcpu, reg); 172 } 173 174 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg) 175 { 176 u64 (*xlate)(u64) = NULL; 177 unsigned int el1r; 178 179 if (!vcpu_get_flag(vcpu, SYSREGS_ON_CPU)) 180 goto memory_write; 181 182 if (unlikely(get_el2_to_el1_mapping(reg, &el1r, &xlate))) { 183 if (!is_hyp_ctxt(vcpu)) 184 goto memory_write; 185 186 /* 187 * Always store a copy of the write to memory to avoid having 188 * to reverse-translate virtual EL2 system registers for a 189 * non-VHE guest hypervisor. 190 */ 191 __vcpu_sys_reg(vcpu, reg) = val; 192 193 /* No EL1 counterpart? We're done here.? */ 194 if (reg == el1r) 195 return; 196 197 if (!vcpu_el2_e2h_is_set(vcpu) && xlate) 198 val = xlate(val); 199 200 /* Redirect this to the EL1 version of the register. */ 201 WARN_ON(!__vcpu_write_sys_reg_to_cpu(val, el1r)); 202 return; 203 } 204 205 /* EL1 register can't be on the CPU if the guest is in vEL2. */ 206 if (unlikely(is_hyp_ctxt(vcpu))) 207 goto memory_write; 208 209 if (__vcpu_write_sys_reg_to_cpu(val, reg)) 210 return; 211 212 memory_write: 213 __vcpu_sys_reg(vcpu, reg) = val; 214 } 215 216 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */ 217 #define CSSELR_MAX 14 218 219 /* 220 * Returns the minimum line size for the selected cache, expressed as 221 * Log2(bytes). 222 */ 223 static u8 get_min_cache_line_size(bool icache) 224 { 225 u64 ctr = read_sanitised_ftr_reg(SYS_CTR_EL0); 226 u8 field; 227 228 if (icache) 229 field = SYS_FIELD_GET(CTR_EL0, IminLine, ctr); 230 else 231 field = SYS_FIELD_GET(CTR_EL0, DminLine, ctr); 232 233 /* 234 * Cache line size is represented as Log2(words) in CTR_EL0. 235 * Log2(bytes) can be derived with the following: 236 * 237 * Log2(words) + 2 = Log2(bytes / 4) + 2 238 * = Log2(bytes) - 2 + 2 239 * = Log2(bytes) 240 */ 241 return field + 2; 242 } 243 244 /* Which cache CCSIDR represents depends on CSSELR value. */ 245 static u32 get_ccsidr(struct kvm_vcpu *vcpu, u32 csselr) 246 { 247 u8 line_size; 248 249 if (vcpu->arch.ccsidr) 250 return vcpu->arch.ccsidr[csselr]; 251 252 line_size = get_min_cache_line_size(csselr & CSSELR_EL1_InD); 253 254 /* 255 * Fabricate a CCSIDR value as the overriding value does not exist. 256 * The real CCSIDR value will not be used as it can vary by the 257 * physical CPU which the vcpu currently resides in. 258 * 259 * The line size is determined with get_min_cache_line_size(), which 260 * should be valid for all CPUs even if they have different cache 261 * configuration. 262 * 263 * The associativity bits are cleared, meaning the geometry of all data 264 * and unified caches (which are guaranteed to be PIPT and thus 265 * non-aliasing) are 1 set and 1 way. 266 * Guests should not be doing cache operations by set/way at all, and 267 * for this reason, we trap them and attempt to infer the intent, so 268 * that we can flush the entire guest's address space at the appropriate 269 * time. The exposed geometry minimizes the number of the traps. 270 * [If guests should attempt to infer aliasing properties from the 271 * geometry (which is not permitted by the architecture), they would 272 * only do so for virtually indexed caches.] 273 * 274 * We don't check if the cache level exists as it is allowed to return 275 * an UNKNOWN value if not. 276 */ 277 return SYS_FIELD_PREP(CCSIDR_EL1, LineSize, line_size - 4); 278 } 279 280 static int set_ccsidr(struct kvm_vcpu *vcpu, u32 csselr, u32 val) 281 { 282 u8 line_size = FIELD_GET(CCSIDR_EL1_LineSize, val) + 4; 283 u32 *ccsidr = vcpu->arch.ccsidr; 284 u32 i; 285 286 if ((val & CCSIDR_EL1_RES0) || 287 line_size < get_min_cache_line_size(csselr & CSSELR_EL1_InD)) 288 return -EINVAL; 289 290 if (!ccsidr) { 291 if (val == get_ccsidr(vcpu, csselr)) 292 return 0; 293 294 ccsidr = kmalloc_array(CSSELR_MAX, sizeof(u32), GFP_KERNEL_ACCOUNT); 295 if (!ccsidr) 296 return -ENOMEM; 297 298 for (i = 0; i < CSSELR_MAX; i++) 299 ccsidr[i] = get_ccsidr(vcpu, i); 300 301 vcpu->arch.ccsidr = ccsidr; 302 } 303 304 ccsidr[csselr] = val; 305 306 return 0; 307 } 308 309 static bool access_rw(struct kvm_vcpu *vcpu, 310 struct sys_reg_params *p, 311 const struct sys_reg_desc *r) 312 { 313 if (p->is_write) 314 vcpu_write_sys_reg(vcpu, p->regval, r->reg); 315 else 316 p->regval = vcpu_read_sys_reg(vcpu, r->reg); 317 318 return true; 319 } 320 321 /* 322 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized). 323 */ 324 static bool access_dcsw(struct kvm_vcpu *vcpu, 325 struct sys_reg_params *p, 326 const struct sys_reg_desc *r) 327 { 328 if (!p->is_write) 329 return read_from_write_only(vcpu, p, r); 330 331 /* 332 * Only track S/W ops if we don't have FWB. It still indicates 333 * that the guest is a bit broken (S/W operations should only 334 * be done by firmware, knowing that there is only a single 335 * CPU left in the system, and certainly not from non-secure 336 * software). 337 */ 338 if (!cpus_have_final_cap(ARM64_HAS_STAGE2_FWB)) 339 kvm_set_way_flush(vcpu); 340 341 return true; 342 } 343 344 static bool access_dcgsw(struct kvm_vcpu *vcpu, 345 struct sys_reg_params *p, 346 const struct sys_reg_desc *r) 347 { 348 if (!kvm_has_mte(vcpu->kvm)) { 349 kvm_inject_undefined(vcpu); 350 return false; 351 } 352 353 /* Treat MTE S/W ops as we treat the classic ones: with contempt */ 354 return access_dcsw(vcpu, p, r); 355 } 356 357 static void get_access_mask(const struct sys_reg_desc *r, u64 *mask, u64 *shift) 358 { 359 switch (r->aarch32_map) { 360 case AA32_LO: 361 *mask = GENMASK_ULL(31, 0); 362 *shift = 0; 363 break; 364 case AA32_HI: 365 *mask = GENMASK_ULL(63, 32); 366 *shift = 32; 367 break; 368 default: 369 *mask = GENMASK_ULL(63, 0); 370 *shift = 0; 371 break; 372 } 373 } 374 375 /* 376 * Generic accessor for VM registers. Only called as long as HCR_TVM 377 * is set. If the guest enables the MMU, we stop trapping the VM 378 * sys_regs and leave it in complete control of the caches. 379 */ 380 static bool access_vm_reg(struct kvm_vcpu *vcpu, 381 struct sys_reg_params *p, 382 const struct sys_reg_desc *r) 383 { 384 bool was_enabled = vcpu_has_cache_enabled(vcpu); 385 u64 val, mask, shift; 386 387 if (reg_to_encoding(r) == SYS_TCR2_EL1 && 388 !kvm_has_feat(vcpu->kvm, ID_AA64MMFR3_EL1, TCRX, IMP)) { 389 kvm_inject_undefined(vcpu); 390 return false; 391 } 392 393 BUG_ON(!p->is_write); 394 395 get_access_mask(r, &mask, &shift); 396 397 if (~mask) { 398 val = vcpu_read_sys_reg(vcpu, r->reg); 399 val &= ~mask; 400 } else { 401 val = 0; 402 } 403 404 val |= (p->regval & (mask >> shift)) << shift; 405 vcpu_write_sys_reg(vcpu, val, r->reg); 406 407 kvm_toggle_cache(vcpu, was_enabled); 408 return true; 409 } 410 411 static bool access_actlr(struct kvm_vcpu *vcpu, 412 struct sys_reg_params *p, 413 const struct sys_reg_desc *r) 414 { 415 u64 mask, shift; 416 417 if (p->is_write) 418 return ignore_write(vcpu, p); 419 420 get_access_mask(r, &mask, &shift); 421 p->regval = (vcpu_read_sys_reg(vcpu, r->reg) & mask) >> shift; 422 423 return true; 424 } 425 426 /* 427 * Trap handler for the GICv3 SGI generation system register. 428 * Forward the request to the VGIC emulation. 429 * The cp15_64 code makes sure this automatically works 430 * for both AArch64 and AArch32 accesses. 431 */ 432 static bool access_gic_sgi(struct kvm_vcpu *vcpu, 433 struct sys_reg_params *p, 434 const struct sys_reg_desc *r) 435 { 436 bool g1; 437 438 if (!p->is_write) 439 return read_from_write_only(vcpu, p, r); 440 441 /* 442 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates 443 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group, 444 * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively 445 * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure 446 * group. 447 */ 448 if (p->Op0 == 0) { /* AArch32 */ 449 switch (p->Op1) { 450 default: /* Keep GCC quiet */ 451 case 0: /* ICC_SGI1R */ 452 g1 = true; 453 break; 454 case 1: /* ICC_ASGI1R */ 455 case 2: /* ICC_SGI0R */ 456 g1 = false; 457 break; 458 } 459 } else { /* AArch64 */ 460 switch (p->Op2) { 461 default: /* Keep GCC quiet */ 462 case 5: /* ICC_SGI1R_EL1 */ 463 g1 = true; 464 break; 465 case 6: /* ICC_ASGI1R_EL1 */ 466 case 7: /* ICC_SGI0R_EL1 */ 467 g1 = false; 468 break; 469 } 470 } 471 472 vgic_v3_dispatch_sgi(vcpu, p->regval, g1); 473 474 return true; 475 } 476 477 static bool access_gic_sre(struct kvm_vcpu *vcpu, 478 struct sys_reg_params *p, 479 const struct sys_reg_desc *r) 480 { 481 if (p->is_write) 482 return ignore_write(vcpu, p); 483 484 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre; 485 return true; 486 } 487 488 static bool trap_raz_wi(struct kvm_vcpu *vcpu, 489 struct sys_reg_params *p, 490 const struct sys_reg_desc *r) 491 { 492 if (p->is_write) 493 return ignore_write(vcpu, p); 494 else 495 return read_zero(vcpu, p); 496 } 497 498 static bool trap_undef(struct kvm_vcpu *vcpu, 499 struct sys_reg_params *p, 500 const struct sys_reg_desc *r) 501 { 502 kvm_inject_undefined(vcpu); 503 return false; 504 } 505 506 /* 507 * ARMv8.1 mandates at least a trivial LORegion implementation, where all the 508 * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0 509 * system, these registers should UNDEF. LORID_EL1 being a RO register, we 510 * treat it separately. 511 */ 512 static bool trap_loregion(struct kvm_vcpu *vcpu, 513 struct sys_reg_params *p, 514 const struct sys_reg_desc *r) 515 { 516 u32 sr = reg_to_encoding(r); 517 518 if (!kvm_has_feat(vcpu->kvm, ID_AA64MMFR1_EL1, LO, IMP)) { 519 kvm_inject_undefined(vcpu); 520 return false; 521 } 522 523 if (p->is_write && sr == SYS_LORID_EL1) 524 return write_to_read_only(vcpu, p, r); 525 526 return trap_raz_wi(vcpu, p, r); 527 } 528 529 static bool trap_oslar_el1(struct kvm_vcpu *vcpu, 530 struct sys_reg_params *p, 531 const struct sys_reg_desc *r) 532 { 533 u64 oslsr; 534 535 if (!p->is_write) 536 return read_from_write_only(vcpu, p, r); 537 538 /* Forward the OSLK bit to OSLSR */ 539 oslsr = __vcpu_sys_reg(vcpu, OSLSR_EL1) & ~OSLSR_EL1_OSLK; 540 if (p->regval & OSLAR_EL1_OSLK) 541 oslsr |= OSLSR_EL1_OSLK; 542 543 __vcpu_sys_reg(vcpu, OSLSR_EL1) = oslsr; 544 return true; 545 } 546 547 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu, 548 struct sys_reg_params *p, 549 const struct sys_reg_desc *r) 550 { 551 if (p->is_write) 552 return write_to_read_only(vcpu, p, r); 553 554 p->regval = __vcpu_sys_reg(vcpu, r->reg); 555 return true; 556 } 557 558 static int set_oslsr_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 559 u64 val) 560 { 561 /* 562 * The only modifiable bit is the OSLK bit. Refuse the write if 563 * userspace attempts to change any other bit in the register. 564 */ 565 if ((val ^ rd->val) & ~OSLSR_EL1_OSLK) 566 return -EINVAL; 567 568 __vcpu_sys_reg(vcpu, rd->reg) = val; 569 return 0; 570 } 571 572 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu, 573 struct sys_reg_params *p, 574 const struct sys_reg_desc *r) 575 { 576 if (p->is_write) { 577 return ignore_write(vcpu, p); 578 } else { 579 p->regval = read_sysreg(dbgauthstatus_el1); 580 return true; 581 } 582 } 583 584 /* 585 * We want to avoid world-switching all the DBG registers all the 586 * time: 587 * 588 * - If we've touched any debug register, it is likely that we're 589 * going to touch more of them. It then makes sense to disable the 590 * traps and start doing the save/restore dance 591 * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is 592 * then mandatory to save/restore the registers, as the guest 593 * depends on them. 594 * 595 * For this, we use a DIRTY bit, indicating the guest has modified the 596 * debug registers, used as follow: 597 * 598 * On guest entry: 599 * - If the dirty bit is set (because we're coming back from trapping), 600 * disable the traps, save host registers, restore guest registers. 601 * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), 602 * set the dirty bit, disable the traps, save host registers, 603 * restore guest registers. 604 * - Otherwise, enable the traps 605 * 606 * On guest exit: 607 * - If the dirty bit is set, save guest registers, restore host 608 * registers and clear the dirty bit. This ensure that the host can 609 * now use the debug registers. 610 */ 611 static bool trap_debug_regs(struct kvm_vcpu *vcpu, 612 struct sys_reg_params *p, 613 const struct sys_reg_desc *r) 614 { 615 access_rw(vcpu, p, r); 616 if (p->is_write) 617 vcpu_set_flag(vcpu, DEBUG_DIRTY); 618 619 trace_trap_reg(__func__, r->reg, p->is_write, p->regval); 620 621 return true; 622 } 623 624 /* 625 * reg_to_dbg/dbg_to_reg 626 * 627 * A 32 bit write to a debug register leave top bits alone 628 * A 32 bit read from a debug register only returns the bottom bits 629 * 630 * All writes will set the DEBUG_DIRTY flag to ensure the hyp code 631 * switches between host and guest values in future. 632 */ 633 static void reg_to_dbg(struct kvm_vcpu *vcpu, 634 struct sys_reg_params *p, 635 const struct sys_reg_desc *rd, 636 u64 *dbg_reg) 637 { 638 u64 mask, shift, val; 639 640 get_access_mask(rd, &mask, &shift); 641 642 val = *dbg_reg; 643 val &= ~mask; 644 val |= (p->regval & (mask >> shift)) << shift; 645 *dbg_reg = val; 646 647 vcpu_set_flag(vcpu, DEBUG_DIRTY); 648 } 649 650 static void dbg_to_reg(struct kvm_vcpu *vcpu, 651 struct sys_reg_params *p, 652 const struct sys_reg_desc *rd, 653 u64 *dbg_reg) 654 { 655 u64 mask, shift; 656 657 get_access_mask(rd, &mask, &shift); 658 p->regval = (*dbg_reg & mask) >> shift; 659 } 660 661 static bool trap_bvr(struct kvm_vcpu *vcpu, 662 struct sys_reg_params *p, 663 const struct sys_reg_desc *rd) 664 { 665 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm]; 666 667 if (p->is_write) 668 reg_to_dbg(vcpu, p, rd, dbg_reg); 669 else 670 dbg_to_reg(vcpu, p, rd, dbg_reg); 671 672 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); 673 674 return true; 675 } 676 677 static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 678 u64 val) 679 { 680 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = val; 681 return 0; 682 } 683 684 static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 685 u64 *val) 686 { 687 *val = vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm]; 688 return 0; 689 } 690 691 static u64 reset_bvr(struct kvm_vcpu *vcpu, 692 const struct sys_reg_desc *rd) 693 { 694 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = rd->val; 695 return rd->val; 696 } 697 698 static bool trap_bcr(struct kvm_vcpu *vcpu, 699 struct sys_reg_params *p, 700 const struct sys_reg_desc *rd) 701 { 702 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm]; 703 704 if (p->is_write) 705 reg_to_dbg(vcpu, p, rd, dbg_reg); 706 else 707 dbg_to_reg(vcpu, p, rd, dbg_reg); 708 709 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); 710 711 return true; 712 } 713 714 static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 715 u64 val) 716 { 717 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = val; 718 return 0; 719 } 720 721 static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 722 u64 *val) 723 { 724 *val = vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm]; 725 return 0; 726 } 727 728 static u64 reset_bcr(struct kvm_vcpu *vcpu, 729 const struct sys_reg_desc *rd) 730 { 731 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = rd->val; 732 return rd->val; 733 } 734 735 static bool trap_wvr(struct kvm_vcpu *vcpu, 736 struct sys_reg_params *p, 737 const struct sys_reg_desc *rd) 738 { 739 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]; 740 741 if (p->is_write) 742 reg_to_dbg(vcpu, p, rd, dbg_reg); 743 else 744 dbg_to_reg(vcpu, p, rd, dbg_reg); 745 746 trace_trap_reg(__func__, rd->CRm, p->is_write, 747 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]); 748 749 return true; 750 } 751 752 static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 753 u64 val) 754 { 755 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = val; 756 return 0; 757 } 758 759 static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 760 u64 *val) 761 { 762 *val = vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]; 763 return 0; 764 } 765 766 static u64 reset_wvr(struct kvm_vcpu *vcpu, 767 const struct sys_reg_desc *rd) 768 { 769 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = rd->val; 770 return rd->val; 771 } 772 773 static bool trap_wcr(struct kvm_vcpu *vcpu, 774 struct sys_reg_params *p, 775 const struct sys_reg_desc *rd) 776 { 777 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm]; 778 779 if (p->is_write) 780 reg_to_dbg(vcpu, p, rd, dbg_reg); 781 else 782 dbg_to_reg(vcpu, p, rd, dbg_reg); 783 784 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); 785 786 return true; 787 } 788 789 static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 790 u64 val) 791 { 792 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = val; 793 return 0; 794 } 795 796 static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 797 u64 *val) 798 { 799 *val = vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm]; 800 return 0; 801 } 802 803 static u64 reset_wcr(struct kvm_vcpu *vcpu, 804 const struct sys_reg_desc *rd) 805 { 806 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = rd->val; 807 return rd->val; 808 } 809 810 static u64 reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 811 { 812 u64 amair = read_sysreg(amair_el1); 813 vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1); 814 return amair; 815 } 816 817 static u64 reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 818 { 819 u64 actlr = read_sysreg(actlr_el1); 820 vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1); 821 return actlr; 822 } 823 824 static u64 reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 825 { 826 u64 mpidr; 827 828 /* 829 * Map the vcpu_id into the first three affinity level fields of 830 * the MPIDR. We limit the number of VCPUs in level 0 due to a 831 * limitation to 16 CPUs in that level in the ICC_SGIxR registers 832 * of the GICv3 to be able to address each CPU directly when 833 * sending IPIs. 834 */ 835 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0); 836 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1); 837 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2); 838 mpidr |= (1ULL << 31); 839 vcpu_write_sys_reg(vcpu, mpidr, MPIDR_EL1); 840 841 return mpidr; 842 } 843 844 static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu, 845 const struct sys_reg_desc *r) 846 { 847 if (kvm_vcpu_has_pmu(vcpu)) 848 return 0; 849 850 return REG_HIDDEN; 851 } 852 853 static u64 reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 854 { 855 u64 mask = BIT(ARMV8_PMU_CYCLE_IDX); 856 u8 n = vcpu->kvm->arch.pmcr_n; 857 858 if (n) 859 mask |= GENMASK(n - 1, 0); 860 861 reset_unknown(vcpu, r); 862 __vcpu_sys_reg(vcpu, r->reg) &= mask; 863 864 return __vcpu_sys_reg(vcpu, r->reg); 865 } 866 867 static u64 reset_pmevcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 868 { 869 reset_unknown(vcpu, r); 870 __vcpu_sys_reg(vcpu, r->reg) &= GENMASK(31, 0); 871 872 return __vcpu_sys_reg(vcpu, r->reg); 873 } 874 875 static u64 reset_pmevtyper(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 876 { 877 /* This thing will UNDEF, who cares about the reset value? */ 878 if (!kvm_vcpu_has_pmu(vcpu)) 879 return 0; 880 881 reset_unknown(vcpu, r); 882 __vcpu_sys_reg(vcpu, r->reg) &= kvm_pmu_evtyper_mask(vcpu->kvm); 883 884 return __vcpu_sys_reg(vcpu, r->reg); 885 } 886 887 static u64 reset_pmselr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 888 { 889 reset_unknown(vcpu, r); 890 __vcpu_sys_reg(vcpu, r->reg) &= ARMV8_PMU_COUNTER_MASK; 891 892 return __vcpu_sys_reg(vcpu, r->reg); 893 } 894 895 static u64 reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 896 { 897 u64 pmcr = 0; 898 899 if (!kvm_supports_32bit_el0()) 900 pmcr |= ARMV8_PMU_PMCR_LC; 901 902 /* 903 * The value of PMCR.N field is included when the 904 * vCPU register is read via kvm_vcpu_read_pmcr(). 905 */ 906 __vcpu_sys_reg(vcpu, r->reg) = pmcr; 907 908 return __vcpu_sys_reg(vcpu, r->reg); 909 } 910 911 static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags) 912 { 913 u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0); 914 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu); 915 916 if (!enabled) 917 kvm_inject_undefined(vcpu); 918 919 return !enabled; 920 } 921 922 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu) 923 { 924 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN); 925 } 926 927 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu) 928 { 929 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN); 930 } 931 932 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu) 933 { 934 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN); 935 } 936 937 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu) 938 { 939 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN); 940 } 941 942 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 943 const struct sys_reg_desc *r) 944 { 945 u64 val; 946 947 if (pmu_access_el0_disabled(vcpu)) 948 return false; 949 950 if (p->is_write) { 951 /* 952 * Only update writeable bits of PMCR (continuing into 953 * kvm_pmu_handle_pmcr() as well) 954 */ 955 val = kvm_vcpu_read_pmcr(vcpu); 956 val &= ~ARMV8_PMU_PMCR_MASK; 957 val |= p->regval & ARMV8_PMU_PMCR_MASK; 958 if (!kvm_supports_32bit_el0()) 959 val |= ARMV8_PMU_PMCR_LC; 960 kvm_pmu_handle_pmcr(vcpu, val); 961 } else { 962 /* PMCR.P & PMCR.C are RAZ */ 963 val = kvm_vcpu_read_pmcr(vcpu) 964 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C); 965 p->regval = val; 966 } 967 968 return true; 969 } 970 971 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 972 const struct sys_reg_desc *r) 973 { 974 if (pmu_access_event_counter_el0_disabled(vcpu)) 975 return false; 976 977 if (p->is_write) 978 __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval; 979 else 980 /* return PMSELR.SEL field */ 981 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0) 982 & ARMV8_PMU_COUNTER_MASK; 983 984 return true; 985 } 986 987 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 988 const struct sys_reg_desc *r) 989 { 990 u64 pmceid, mask, shift; 991 992 BUG_ON(p->is_write); 993 994 if (pmu_access_el0_disabled(vcpu)) 995 return false; 996 997 get_access_mask(r, &mask, &shift); 998 999 pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1)); 1000 pmceid &= mask; 1001 pmceid >>= shift; 1002 1003 p->regval = pmceid; 1004 1005 return true; 1006 } 1007 1008 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx) 1009 { 1010 u64 pmcr, val; 1011 1012 pmcr = kvm_vcpu_read_pmcr(vcpu); 1013 val = FIELD_GET(ARMV8_PMU_PMCR_N, pmcr); 1014 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) { 1015 kvm_inject_undefined(vcpu); 1016 return false; 1017 } 1018 1019 return true; 1020 } 1021 1022 static int get_pmu_evcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 1023 u64 *val) 1024 { 1025 u64 idx; 1026 1027 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 0) 1028 /* PMCCNTR_EL0 */ 1029 idx = ARMV8_PMU_CYCLE_IDX; 1030 else 1031 /* PMEVCNTRn_EL0 */ 1032 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 1033 1034 *val = kvm_pmu_get_counter_value(vcpu, idx); 1035 return 0; 1036 } 1037 1038 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu, 1039 struct sys_reg_params *p, 1040 const struct sys_reg_desc *r) 1041 { 1042 u64 idx = ~0UL; 1043 1044 if (r->CRn == 9 && r->CRm == 13) { 1045 if (r->Op2 == 2) { 1046 /* PMXEVCNTR_EL0 */ 1047 if (pmu_access_event_counter_el0_disabled(vcpu)) 1048 return false; 1049 1050 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) 1051 & ARMV8_PMU_COUNTER_MASK; 1052 } else if (r->Op2 == 0) { 1053 /* PMCCNTR_EL0 */ 1054 if (pmu_access_cycle_counter_el0_disabled(vcpu)) 1055 return false; 1056 1057 idx = ARMV8_PMU_CYCLE_IDX; 1058 } 1059 } else if (r->CRn == 0 && r->CRm == 9) { 1060 /* PMCCNTR */ 1061 if (pmu_access_event_counter_el0_disabled(vcpu)) 1062 return false; 1063 1064 idx = ARMV8_PMU_CYCLE_IDX; 1065 } else if (r->CRn == 14 && (r->CRm & 12) == 8) { 1066 /* PMEVCNTRn_EL0 */ 1067 if (pmu_access_event_counter_el0_disabled(vcpu)) 1068 return false; 1069 1070 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 1071 } 1072 1073 /* Catch any decoding mistake */ 1074 WARN_ON(idx == ~0UL); 1075 1076 if (!pmu_counter_idx_valid(vcpu, idx)) 1077 return false; 1078 1079 if (p->is_write) { 1080 if (pmu_access_el0_disabled(vcpu)) 1081 return false; 1082 1083 kvm_pmu_set_counter_value(vcpu, idx, p->regval); 1084 } else { 1085 p->regval = kvm_pmu_get_counter_value(vcpu, idx); 1086 } 1087 1088 return true; 1089 } 1090 1091 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1092 const struct sys_reg_desc *r) 1093 { 1094 u64 idx, reg; 1095 1096 if (pmu_access_el0_disabled(vcpu)) 1097 return false; 1098 1099 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) { 1100 /* PMXEVTYPER_EL0 */ 1101 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK; 1102 reg = PMEVTYPER0_EL0 + idx; 1103 } else if (r->CRn == 14 && (r->CRm & 12) == 12) { 1104 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 1105 if (idx == ARMV8_PMU_CYCLE_IDX) 1106 reg = PMCCFILTR_EL0; 1107 else 1108 /* PMEVTYPERn_EL0 */ 1109 reg = PMEVTYPER0_EL0 + idx; 1110 } else { 1111 BUG(); 1112 } 1113 1114 if (!pmu_counter_idx_valid(vcpu, idx)) 1115 return false; 1116 1117 if (p->is_write) { 1118 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx); 1119 kvm_vcpu_pmu_restore_guest(vcpu); 1120 } else { 1121 p->regval = __vcpu_sys_reg(vcpu, reg); 1122 } 1123 1124 return true; 1125 } 1126 1127 static int set_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 val) 1128 { 1129 bool set; 1130 1131 val &= kvm_pmu_valid_counter_mask(vcpu); 1132 1133 switch (r->reg) { 1134 case PMOVSSET_EL0: 1135 /* CRm[1] being set indicates a SET register, and CLR otherwise */ 1136 set = r->CRm & 2; 1137 break; 1138 default: 1139 /* Op2[0] being set indicates a SET register, and CLR otherwise */ 1140 set = r->Op2 & 1; 1141 break; 1142 } 1143 1144 if (set) 1145 __vcpu_sys_reg(vcpu, r->reg) |= val; 1146 else 1147 __vcpu_sys_reg(vcpu, r->reg) &= ~val; 1148 1149 return 0; 1150 } 1151 1152 static int get_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 *val) 1153 { 1154 u64 mask = kvm_pmu_valid_counter_mask(vcpu); 1155 1156 *val = __vcpu_sys_reg(vcpu, r->reg) & mask; 1157 return 0; 1158 } 1159 1160 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1161 const struct sys_reg_desc *r) 1162 { 1163 u64 val, mask; 1164 1165 if (pmu_access_el0_disabled(vcpu)) 1166 return false; 1167 1168 mask = kvm_pmu_valid_counter_mask(vcpu); 1169 if (p->is_write) { 1170 val = p->regval & mask; 1171 if (r->Op2 & 0x1) { 1172 /* accessing PMCNTENSET_EL0 */ 1173 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val; 1174 kvm_pmu_enable_counter_mask(vcpu, val); 1175 kvm_vcpu_pmu_restore_guest(vcpu); 1176 } else { 1177 /* accessing PMCNTENCLR_EL0 */ 1178 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val; 1179 kvm_pmu_disable_counter_mask(vcpu, val); 1180 } 1181 } else { 1182 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0); 1183 } 1184 1185 return true; 1186 } 1187 1188 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1189 const struct sys_reg_desc *r) 1190 { 1191 u64 mask = kvm_pmu_valid_counter_mask(vcpu); 1192 1193 if (check_pmu_access_disabled(vcpu, 0)) 1194 return false; 1195 1196 if (p->is_write) { 1197 u64 val = p->regval & mask; 1198 1199 if (r->Op2 & 0x1) 1200 /* accessing PMINTENSET_EL1 */ 1201 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val; 1202 else 1203 /* accessing PMINTENCLR_EL1 */ 1204 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val; 1205 } else { 1206 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1); 1207 } 1208 1209 return true; 1210 } 1211 1212 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1213 const struct sys_reg_desc *r) 1214 { 1215 u64 mask = kvm_pmu_valid_counter_mask(vcpu); 1216 1217 if (pmu_access_el0_disabled(vcpu)) 1218 return false; 1219 1220 if (p->is_write) { 1221 if (r->CRm & 0x2) 1222 /* accessing PMOVSSET_EL0 */ 1223 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask); 1224 else 1225 /* accessing PMOVSCLR_EL0 */ 1226 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask); 1227 } else { 1228 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0); 1229 } 1230 1231 return true; 1232 } 1233 1234 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1235 const struct sys_reg_desc *r) 1236 { 1237 u64 mask; 1238 1239 if (!p->is_write) 1240 return read_from_write_only(vcpu, p, r); 1241 1242 if (pmu_write_swinc_el0_disabled(vcpu)) 1243 return false; 1244 1245 mask = kvm_pmu_valid_counter_mask(vcpu); 1246 kvm_pmu_software_increment(vcpu, p->regval & mask); 1247 return true; 1248 } 1249 1250 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1251 const struct sys_reg_desc *r) 1252 { 1253 if (p->is_write) { 1254 if (!vcpu_mode_priv(vcpu)) { 1255 kvm_inject_undefined(vcpu); 1256 return false; 1257 } 1258 1259 __vcpu_sys_reg(vcpu, PMUSERENR_EL0) = 1260 p->regval & ARMV8_PMU_USERENR_MASK; 1261 } else { 1262 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0) 1263 & ARMV8_PMU_USERENR_MASK; 1264 } 1265 1266 return true; 1267 } 1268 1269 static int get_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 1270 u64 *val) 1271 { 1272 *val = kvm_vcpu_read_pmcr(vcpu); 1273 return 0; 1274 } 1275 1276 static int set_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 1277 u64 val) 1278 { 1279 u8 new_n = FIELD_GET(ARMV8_PMU_PMCR_N, val); 1280 struct kvm *kvm = vcpu->kvm; 1281 1282 mutex_lock(&kvm->arch.config_lock); 1283 1284 /* 1285 * The vCPU can't have more counters than the PMU hardware 1286 * implements. Ignore this error to maintain compatibility 1287 * with the existing KVM behavior. 1288 */ 1289 if (!kvm_vm_has_ran_once(kvm) && 1290 new_n <= kvm_arm_pmu_get_max_counters(kvm)) 1291 kvm->arch.pmcr_n = new_n; 1292 1293 mutex_unlock(&kvm->arch.config_lock); 1294 1295 /* 1296 * Ignore writes to RES0 bits, read only bits that are cleared on 1297 * vCPU reset, and writable bits that KVM doesn't support yet. 1298 * (i.e. only PMCR.N and bits [7:0] are mutable from userspace) 1299 * The LP bit is RES0 when FEAT_PMUv3p5 is not supported on the vCPU. 1300 * But, we leave the bit as it is here, as the vCPU's PMUver might 1301 * be changed later (NOTE: the bit will be cleared on first vCPU run 1302 * if necessary). 1303 */ 1304 val &= ARMV8_PMU_PMCR_MASK; 1305 1306 /* The LC bit is RES1 when AArch32 is not supported */ 1307 if (!kvm_supports_32bit_el0()) 1308 val |= ARMV8_PMU_PMCR_LC; 1309 1310 __vcpu_sys_reg(vcpu, r->reg) = val; 1311 return 0; 1312 } 1313 1314 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */ 1315 #define DBG_BCR_BVR_WCR_WVR_EL1(n) \ 1316 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \ 1317 trap_bvr, reset_bvr, 0, 0, get_bvr, set_bvr }, \ 1318 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \ 1319 trap_bcr, reset_bcr, 0, 0, get_bcr, set_bcr }, \ 1320 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \ 1321 trap_wvr, reset_wvr, 0, 0, get_wvr, set_wvr }, \ 1322 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \ 1323 trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr } 1324 1325 #define PMU_SYS_REG(name) \ 1326 SYS_DESC(SYS_##name), .reset = reset_pmu_reg, \ 1327 .visibility = pmu_visibility 1328 1329 /* Macro to expand the PMEVCNTRn_EL0 register */ 1330 #define PMU_PMEVCNTR_EL0(n) \ 1331 { PMU_SYS_REG(PMEVCNTRn_EL0(n)), \ 1332 .reset = reset_pmevcntr, .get_user = get_pmu_evcntr, \ 1333 .access = access_pmu_evcntr, .reg = (PMEVCNTR0_EL0 + n), } 1334 1335 /* Macro to expand the PMEVTYPERn_EL0 register */ 1336 #define PMU_PMEVTYPER_EL0(n) \ 1337 { PMU_SYS_REG(PMEVTYPERn_EL0(n)), \ 1338 .reset = reset_pmevtyper, \ 1339 .access = access_pmu_evtyper, .reg = (PMEVTYPER0_EL0 + n), } 1340 1341 static bool undef_access(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1342 const struct sys_reg_desc *r) 1343 { 1344 kvm_inject_undefined(vcpu); 1345 1346 return false; 1347 } 1348 1349 /* Macro to expand the AMU counter and type registers*/ 1350 #define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), undef_access } 1351 #define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), undef_access } 1352 #define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), undef_access } 1353 #define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), undef_access } 1354 1355 static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu, 1356 const struct sys_reg_desc *rd) 1357 { 1358 return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN; 1359 } 1360 1361 /* 1362 * If we land here on a PtrAuth access, that is because we didn't 1363 * fixup the access on exit by allowing the PtrAuth sysregs. The only 1364 * way this happens is when the guest does not have PtrAuth support 1365 * enabled. 1366 */ 1367 #define __PTRAUTH_KEY(k) \ 1368 { SYS_DESC(SYS_## k), undef_access, reset_unknown, k, \ 1369 .visibility = ptrauth_visibility} 1370 1371 #define PTRAUTH_KEY(k) \ 1372 __PTRAUTH_KEY(k ## KEYLO_EL1), \ 1373 __PTRAUTH_KEY(k ## KEYHI_EL1) 1374 1375 static bool access_arch_timer(struct kvm_vcpu *vcpu, 1376 struct sys_reg_params *p, 1377 const struct sys_reg_desc *r) 1378 { 1379 enum kvm_arch_timers tmr; 1380 enum kvm_arch_timer_regs treg; 1381 u64 reg = reg_to_encoding(r); 1382 1383 switch (reg) { 1384 case SYS_CNTP_TVAL_EL0: 1385 case SYS_AARCH32_CNTP_TVAL: 1386 tmr = TIMER_PTIMER; 1387 treg = TIMER_REG_TVAL; 1388 break; 1389 case SYS_CNTP_CTL_EL0: 1390 case SYS_AARCH32_CNTP_CTL: 1391 tmr = TIMER_PTIMER; 1392 treg = TIMER_REG_CTL; 1393 break; 1394 case SYS_CNTP_CVAL_EL0: 1395 case SYS_AARCH32_CNTP_CVAL: 1396 tmr = TIMER_PTIMER; 1397 treg = TIMER_REG_CVAL; 1398 break; 1399 case SYS_CNTPCT_EL0: 1400 case SYS_CNTPCTSS_EL0: 1401 case SYS_AARCH32_CNTPCT: 1402 tmr = TIMER_PTIMER; 1403 treg = TIMER_REG_CNT; 1404 break; 1405 default: 1406 print_sys_reg_msg(p, "%s", "Unhandled trapped timer register"); 1407 kvm_inject_undefined(vcpu); 1408 return false; 1409 } 1410 1411 if (p->is_write) 1412 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval); 1413 else 1414 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg); 1415 1416 return true; 1417 } 1418 1419 static s64 kvm_arm64_ftr_safe_value(u32 id, const struct arm64_ftr_bits *ftrp, 1420 s64 new, s64 cur) 1421 { 1422 struct arm64_ftr_bits kvm_ftr = *ftrp; 1423 1424 /* Some features have different safe value type in KVM than host features */ 1425 switch (id) { 1426 case SYS_ID_AA64DFR0_EL1: 1427 switch (kvm_ftr.shift) { 1428 case ID_AA64DFR0_EL1_PMUVer_SHIFT: 1429 kvm_ftr.type = FTR_LOWER_SAFE; 1430 break; 1431 case ID_AA64DFR0_EL1_DebugVer_SHIFT: 1432 kvm_ftr.type = FTR_LOWER_SAFE; 1433 break; 1434 } 1435 break; 1436 case SYS_ID_DFR0_EL1: 1437 if (kvm_ftr.shift == ID_DFR0_EL1_PerfMon_SHIFT) 1438 kvm_ftr.type = FTR_LOWER_SAFE; 1439 break; 1440 } 1441 1442 return arm64_ftr_safe_value(&kvm_ftr, new, cur); 1443 } 1444 1445 /* 1446 * arm64_check_features() - Check if a feature register value constitutes 1447 * a subset of features indicated by the idreg's KVM sanitised limit. 1448 * 1449 * This function will check if each feature field of @val is the "safe" value 1450 * against idreg's KVM sanitised limit return from reset() callback. 1451 * If a field value in @val is the same as the one in limit, it is always 1452 * considered the safe value regardless For register fields that are not in 1453 * writable, only the value in limit is considered the safe value. 1454 * 1455 * Return: 0 if all the fields are safe. Otherwise, return negative errno. 1456 */ 1457 static int arm64_check_features(struct kvm_vcpu *vcpu, 1458 const struct sys_reg_desc *rd, 1459 u64 val) 1460 { 1461 const struct arm64_ftr_reg *ftr_reg; 1462 const struct arm64_ftr_bits *ftrp = NULL; 1463 u32 id = reg_to_encoding(rd); 1464 u64 writable_mask = rd->val; 1465 u64 limit = rd->reset(vcpu, rd); 1466 u64 mask = 0; 1467 1468 /* 1469 * Hidden and unallocated ID registers may not have a corresponding 1470 * struct arm64_ftr_reg. Of course, if the register is RAZ we know the 1471 * only safe value is 0. 1472 */ 1473 if (sysreg_visible_as_raz(vcpu, rd)) 1474 return val ? -E2BIG : 0; 1475 1476 ftr_reg = get_arm64_ftr_reg(id); 1477 if (!ftr_reg) 1478 return -EINVAL; 1479 1480 ftrp = ftr_reg->ftr_bits; 1481 1482 for (; ftrp && ftrp->width; ftrp++) { 1483 s64 f_val, f_lim, safe_val; 1484 u64 ftr_mask; 1485 1486 ftr_mask = arm64_ftr_mask(ftrp); 1487 if ((ftr_mask & writable_mask) != ftr_mask) 1488 continue; 1489 1490 f_val = arm64_ftr_value(ftrp, val); 1491 f_lim = arm64_ftr_value(ftrp, limit); 1492 mask |= ftr_mask; 1493 1494 if (f_val == f_lim) 1495 safe_val = f_val; 1496 else 1497 safe_val = kvm_arm64_ftr_safe_value(id, ftrp, f_val, f_lim); 1498 1499 if (safe_val != f_val) 1500 return -E2BIG; 1501 } 1502 1503 /* For fields that are not writable, values in limit are the safe values. */ 1504 if ((val & ~mask) != (limit & ~mask)) 1505 return -E2BIG; 1506 1507 return 0; 1508 } 1509 1510 static u8 pmuver_to_perfmon(u8 pmuver) 1511 { 1512 switch (pmuver) { 1513 case ID_AA64DFR0_EL1_PMUVer_IMP: 1514 return ID_DFR0_EL1_PerfMon_PMUv3; 1515 case ID_AA64DFR0_EL1_PMUVer_IMP_DEF: 1516 return ID_DFR0_EL1_PerfMon_IMPDEF; 1517 default: 1518 /* Anything ARMv8.1+ and NI have the same value. For now. */ 1519 return pmuver; 1520 } 1521 } 1522 1523 /* Read a sanitised cpufeature ID register by sys_reg_desc */ 1524 static u64 __kvm_read_sanitised_id_reg(const struct kvm_vcpu *vcpu, 1525 const struct sys_reg_desc *r) 1526 { 1527 u32 id = reg_to_encoding(r); 1528 u64 val; 1529 1530 if (sysreg_visible_as_raz(vcpu, r)) 1531 return 0; 1532 1533 val = read_sanitised_ftr_reg(id); 1534 1535 switch (id) { 1536 case SYS_ID_AA64PFR1_EL1: 1537 if (!kvm_has_mte(vcpu->kvm)) 1538 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE); 1539 1540 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_SME); 1541 break; 1542 case SYS_ID_AA64ISAR1_EL1: 1543 if (!vcpu_has_ptrauth(vcpu)) 1544 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) | 1545 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) | 1546 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) | 1547 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI)); 1548 break; 1549 case SYS_ID_AA64ISAR2_EL1: 1550 if (!vcpu_has_ptrauth(vcpu)) 1551 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) | 1552 ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3)); 1553 if (!cpus_have_final_cap(ARM64_HAS_WFXT)) 1554 val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT); 1555 break; 1556 case SYS_ID_AA64MMFR2_EL1: 1557 val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK; 1558 break; 1559 case SYS_ID_MMFR4_EL1: 1560 val &= ~ARM64_FEATURE_MASK(ID_MMFR4_EL1_CCIDX); 1561 break; 1562 } 1563 1564 return val; 1565 } 1566 1567 static u64 kvm_read_sanitised_id_reg(struct kvm_vcpu *vcpu, 1568 const struct sys_reg_desc *r) 1569 { 1570 return __kvm_read_sanitised_id_reg(vcpu, r); 1571 } 1572 1573 static u64 read_id_reg(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 1574 { 1575 return kvm_read_vm_id_reg(vcpu->kvm, reg_to_encoding(r)); 1576 } 1577 1578 static bool is_feature_id_reg(u32 encoding) 1579 { 1580 return (sys_reg_Op0(encoding) == 3 && 1581 (sys_reg_Op1(encoding) < 2 || sys_reg_Op1(encoding) == 3) && 1582 sys_reg_CRn(encoding) == 0 && 1583 sys_reg_CRm(encoding) <= 7); 1584 } 1585 1586 /* 1587 * Return true if the register's (Op0, Op1, CRn, CRm, Op2) is 1588 * (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8, which is the range of ID 1589 * registers KVM maintains on a per-VM basis. 1590 */ 1591 static inline bool is_vm_ftr_id_reg(u32 id) 1592 { 1593 if (id == SYS_CTR_EL0) 1594 return true; 1595 1596 return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 && 1597 sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 && 1598 sys_reg_CRm(id) < 8); 1599 } 1600 1601 static inline bool is_vcpu_ftr_id_reg(u32 id) 1602 { 1603 return is_feature_id_reg(id) && !is_vm_ftr_id_reg(id); 1604 } 1605 1606 static inline bool is_aa32_id_reg(u32 id) 1607 { 1608 return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 && 1609 sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 && 1610 sys_reg_CRm(id) <= 3); 1611 } 1612 1613 static unsigned int id_visibility(const struct kvm_vcpu *vcpu, 1614 const struct sys_reg_desc *r) 1615 { 1616 u32 id = reg_to_encoding(r); 1617 1618 switch (id) { 1619 case SYS_ID_AA64ZFR0_EL1: 1620 if (!vcpu_has_sve(vcpu)) 1621 return REG_RAZ; 1622 break; 1623 } 1624 1625 return 0; 1626 } 1627 1628 static unsigned int aa32_id_visibility(const struct kvm_vcpu *vcpu, 1629 const struct sys_reg_desc *r) 1630 { 1631 /* 1632 * AArch32 ID registers are UNKNOWN if AArch32 isn't implemented at any 1633 * EL. Promote to RAZ/WI in order to guarantee consistency between 1634 * systems. 1635 */ 1636 if (!kvm_supports_32bit_el0()) 1637 return REG_RAZ | REG_USER_WI; 1638 1639 return id_visibility(vcpu, r); 1640 } 1641 1642 static unsigned int raz_visibility(const struct kvm_vcpu *vcpu, 1643 const struct sys_reg_desc *r) 1644 { 1645 return REG_RAZ; 1646 } 1647 1648 /* cpufeature ID register access trap handlers */ 1649 1650 static bool access_id_reg(struct kvm_vcpu *vcpu, 1651 struct sys_reg_params *p, 1652 const struct sys_reg_desc *r) 1653 { 1654 if (p->is_write) 1655 return write_to_read_only(vcpu, p, r); 1656 1657 p->regval = read_id_reg(vcpu, r); 1658 1659 return true; 1660 } 1661 1662 /* Visibility overrides for SVE-specific control registers */ 1663 static unsigned int sve_visibility(const struct kvm_vcpu *vcpu, 1664 const struct sys_reg_desc *rd) 1665 { 1666 if (vcpu_has_sve(vcpu)) 1667 return 0; 1668 1669 return REG_HIDDEN; 1670 } 1671 1672 static u64 read_sanitised_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, 1673 const struct sys_reg_desc *rd) 1674 { 1675 u64 val = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1676 1677 if (!vcpu_has_sve(vcpu)) 1678 val &= ~ID_AA64PFR0_EL1_SVE_MASK; 1679 1680 /* 1681 * The default is to expose CSV2 == 1 if the HW isn't affected. 1682 * Although this is a per-CPU feature, we make it global because 1683 * asymmetric systems are just a nuisance. 1684 * 1685 * Userspace can override this as long as it doesn't promise 1686 * the impossible. 1687 */ 1688 if (arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED) { 1689 val &= ~ID_AA64PFR0_EL1_CSV2_MASK; 1690 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV2, IMP); 1691 } 1692 if (arm64_get_meltdown_state() == SPECTRE_UNAFFECTED) { 1693 val &= ~ID_AA64PFR0_EL1_CSV3_MASK; 1694 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV3, IMP); 1695 } 1696 1697 if (kvm_vgic_global_state.type == VGIC_V3) { 1698 val &= ~ID_AA64PFR0_EL1_GIC_MASK; 1699 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, GIC, IMP); 1700 } 1701 1702 val &= ~ID_AA64PFR0_EL1_AMU_MASK; 1703 1704 return val; 1705 } 1706 1707 #define ID_REG_LIMIT_FIELD_ENUM(val, reg, field, limit) \ 1708 ({ \ 1709 u64 __f_val = FIELD_GET(reg##_##field##_MASK, val); \ 1710 (val) &= ~reg##_##field##_MASK; \ 1711 (val) |= FIELD_PREP(reg##_##field##_MASK, \ 1712 min(__f_val, \ 1713 (u64)SYS_FIELD_VALUE(reg, field, limit))); \ 1714 (val); \ 1715 }) 1716 1717 static u64 read_sanitised_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, 1718 const struct sys_reg_desc *rd) 1719 { 1720 u64 val = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); 1721 1722 val = ID_REG_LIMIT_FIELD_ENUM(val, ID_AA64DFR0_EL1, DebugVer, V8P8); 1723 1724 /* 1725 * Only initialize the PMU version if the vCPU was configured with one. 1726 */ 1727 val &= ~ID_AA64DFR0_EL1_PMUVer_MASK; 1728 if (kvm_vcpu_has_pmu(vcpu)) 1729 val |= SYS_FIELD_PREP(ID_AA64DFR0_EL1, PMUVer, 1730 kvm_arm_pmu_get_pmuver_limit()); 1731 1732 /* Hide SPE from guests */ 1733 val &= ~ID_AA64DFR0_EL1_PMSVer_MASK; 1734 1735 return val; 1736 } 1737 1738 static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, 1739 const struct sys_reg_desc *rd, 1740 u64 val) 1741 { 1742 u8 debugver = SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, val); 1743 u8 pmuver = SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, val); 1744 1745 /* 1746 * Prior to commit 3d0dba5764b9 ("KVM: arm64: PMU: Move the 1747 * ID_AA64DFR0_EL1.PMUver limit to VM creation"), KVM erroneously 1748 * exposed an IMP_DEF PMU to userspace and the guest on systems w/ 1749 * non-architectural PMUs. Of course, PMUv3 is the only game in town for 1750 * PMU virtualization, so the IMP_DEF value was rather user-hostile. 1751 * 1752 * At minimum, we're on the hook to allow values that were given to 1753 * userspace by KVM. Cover our tracks here and replace the IMP_DEF value 1754 * with a more sensible NI. The value of an ID register changing under 1755 * the nose of the guest is unfortunate, but is certainly no more 1756 * surprising than an ill-guided PMU driver poking at impdef system 1757 * registers that end in an UNDEF... 1758 */ 1759 if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF) 1760 val &= ~ID_AA64DFR0_EL1_PMUVer_MASK; 1761 1762 /* 1763 * ID_AA64DFR0_EL1.DebugVer is one of those awkward fields with a 1764 * nonzero minimum safe value. 1765 */ 1766 if (debugver < ID_AA64DFR0_EL1_DebugVer_IMP) 1767 return -EINVAL; 1768 1769 return set_id_reg(vcpu, rd, val); 1770 } 1771 1772 static u64 read_sanitised_id_dfr0_el1(struct kvm_vcpu *vcpu, 1773 const struct sys_reg_desc *rd) 1774 { 1775 u8 perfmon = pmuver_to_perfmon(kvm_arm_pmu_get_pmuver_limit()); 1776 u64 val = read_sanitised_ftr_reg(SYS_ID_DFR0_EL1); 1777 1778 val &= ~ID_DFR0_EL1_PerfMon_MASK; 1779 if (kvm_vcpu_has_pmu(vcpu)) 1780 val |= SYS_FIELD_PREP(ID_DFR0_EL1, PerfMon, perfmon); 1781 1782 val = ID_REG_LIMIT_FIELD_ENUM(val, ID_DFR0_EL1, CopDbg, Debugv8p8); 1783 1784 return val; 1785 } 1786 1787 static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, 1788 const struct sys_reg_desc *rd, 1789 u64 val) 1790 { 1791 u8 perfmon = SYS_FIELD_GET(ID_DFR0_EL1, PerfMon, val); 1792 u8 copdbg = SYS_FIELD_GET(ID_DFR0_EL1, CopDbg, val); 1793 1794 if (perfmon == ID_DFR0_EL1_PerfMon_IMPDEF) { 1795 val &= ~ID_DFR0_EL1_PerfMon_MASK; 1796 perfmon = 0; 1797 } 1798 1799 /* 1800 * Allow DFR0_EL1.PerfMon to be set from userspace as long as 1801 * it doesn't promise more than what the HW gives us on the 1802 * AArch64 side (as everything is emulated with that), and 1803 * that this is a PMUv3. 1804 */ 1805 if (perfmon != 0 && perfmon < ID_DFR0_EL1_PerfMon_PMUv3) 1806 return -EINVAL; 1807 1808 if (copdbg < ID_DFR0_EL1_CopDbg_Armv8) 1809 return -EINVAL; 1810 1811 return set_id_reg(vcpu, rd, val); 1812 } 1813 1814 /* 1815 * cpufeature ID register user accessors 1816 * 1817 * For now, these registers are immutable for userspace, so no values 1818 * are stored, and for set_id_reg() we don't allow the effective value 1819 * to be changed. 1820 */ 1821 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1822 u64 *val) 1823 { 1824 /* 1825 * Avoid locking if the VM has already started, as the ID registers are 1826 * guaranteed to be invariant at that point. 1827 */ 1828 if (kvm_vm_has_ran_once(vcpu->kvm)) { 1829 *val = read_id_reg(vcpu, rd); 1830 return 0; 1831 } 1832 1833 mutex_lock(&vcpu->kvm->arch.config_lock); 1834 *val = read_id_reg(vcpu, rd); 1835 mutex_unlock(&vcpu->kvm->arch.config_lock); 1836 1837 return 0; 1838 } 1839 1840 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1841 u64 val) 1842 { 1843 u32 id = reg_to_encoding(rd); 1844 int ret; 1845 1846 mutex_lock(&vcpu->kvm->arch.config_lock); 1847 1848 /* 1849 * Once the VM has started the ID registers are immutable. Reject any 1850 * write that does not match the final register value. 1851 */ 1852 if (kvm_vm_has_ran_once(vcpu->kvm)) { 1853 if (val != read_id_reg(vcpu, rd)) 1854 ret = -EBUSY; 1855 else 1856 ret = 0; 1857 1858 mutex_unlock(&vcpu->kvm->arch.config_lock); 1859 return ret; 1860 } 1861 1862 ret = arm64_check_features(vcpu, rd, val); 1863 if (!ret) 1864 kvm_set_vm_id_reg(vcpu->kvm, id, val); 1865 1866 mutex_unlock(&vcpu->kvm->arch.config_lock); 1867 1868 /* 1869 * arm64_check_features() returns -E2BIG to indicate the register's 1870 * feature set is a superset of the maximally-allowed register value. 1871 * While it would be nice to precisely describe this to userspace, the 1872 * existing UAPI for KVM_SET_ONE_REG has it that invalid register 1873 * writes return -EINVAL. 1874 */ 1875 if (ret == -E2BIG) 1876 ret = -EINVAL; 1877 return ret; 1878 } 1879 1880 void kvm_set_vm_id_reg(struct kvm *kvm, u32 reg, u64 val) 1881 { 1882 u64 *p = __vm_id_reg(&kvm->arch, reg); 1883 1884 lockdep_assert_held(&kvm->arch.config_lock); 1885 1886 if (KVM_BUG_ON(kvm_vm_has_ran_once(kvm) || !p, kvm)) 1887 return; 1888 1889 *p = val; 1890 } 1891 1892 static int get_raz_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1893 u64 *val) 1894 { 1895 *val = 0; 1896 return 0; 1897 } 1898 1899 static int set_wi_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1900 u64 val) 1901 { 1902 return 0; 1903 } 1904 1905 static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1906 const struct sys_reg_desc *r) 1907 { 1908 if (p->is_write) 1909 return write_to_read_only(vcpu, p, r); 1910 1911 p->regval = kvm_read_vm_id_reg(vcpu->kvm, SYS_CTR_EL0); 1912 return true; 1913 } 1914 1915 static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1916 const struct sys_reg_desc *r) 1917 { 1918 if (p->is_write) 1919 return write_to_read_only(vcpu, p, r); 1920 1921 p->regval = __vcpu_sys_reg(vcpu, r->reg); 1922 return true; 1923 } 1924 1925 /* 1926 * Fabricate a CLIDR_EL1 value instead of using the real value, which can vary 1927 * by the physical CPU which the vcpu currently resides in. 1928 */ 1929 static u64 reset_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 1930 { 1931 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0); 1932 u64 clidr; 1933 u8 loc; 1934 1935 if ((ctr_el0 & CTR_EL0_IDC)) { 1936 /* 1937 * Data cache clean to the PoU is not required so LoUU and LoUIS 1938 * will not be set and a unified cache, which will be marked as 1939 * LoC, will be added. 1940 * 1941 * If not DIC, let the unified cache L2 so that an instruction 1942 * cache can be added as L1 later. 1943 */ 1944 loc = (ctr_el0 & CTR_EL0_DIC) ? 1 : 2; 1945 clidr = CACHE_TYPE_UNIFIED << CLIDR_CTYPE_SHIFT(loc); 1946 } else { 1947 /* 1948 * Data cache clean to the PoU is required so let L1 have a data 1949 * cache and mark it as LoUU and LoUIS. As L1 has a data cache, 1950 * it can be marked as LoC too. 1951 */ 1952 loc = 1; 1953 clidr = 1 << CLIDR_LOUU_SHIFT; 1954 clidr |= 1 << CLIDR_LOUIS_SHIFT; 1955 clidr |= CACHE_TYPE_DATA << CLIDR_CTYPE_SHIFT(1); 1956 } 1957 1958 /* 1959 * Instruction cache invalidation to the PoU is required so let L1 have 1960 * an instruction cache. If L1 already has a data cache, it will be 1961 * CACHE_TYPE_SEPARATE. 1962 */ 1963 if (!(ctr_el0 & CTR_EL0_DIC)) 1964 clidr |= CACHE_TYPE_INST << CLIDR_CTYPE_SHIFT(1); 1965 1966 clidr |= loc << CLIDR_LOC_SHIFT; 1967 1968 /* 1969 * Add tag cache unified to data cache. Allocation tags and data are 1970 * unified in a cache line so that it looks valid even if there is only 1971 * one cache line. 1972 */ 1973 if (kvm_has_mte(vcpu->kvm)) 1974 clidr |= 2 << CLIDR_TTYPE_SHIFT(loc); 1975 1976 __vcpu_sys_reg(vcpu, r->reg) = clidr; 1977 1978 return __vcpu_sys_reg(vcpu, r->reg); 1979 } 1980 1981 static int set_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1982 u64 val) 1983 { 1984 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0); 1985 u64 idc = !CLIDR_LOC(val) || (!CLIDR_LOUIS(val) && !CLIDR_LOUU(val)); 1986 1987 if ((val & CLIDR_EL1_RES0) || (!(ctr_el0 & CTR_EL0_IDC) && idc)) 1988 return -EINVAL; 1989 1990 __vcpu_sys_reg(vcpu, rd->reg) = val; 1991 1992 return 0; 1993 } 1994 1995 static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1996 const struct sys_reg_desc *r) 1997 { 1998 int reg = r->reg; 1999 2000 if (p->is_write) 2001 vcpu_write_sys_reg(vcpu, p->regval, reg); 2002 else 2003 p->regval = vcpu_read_sys_reg(vcpu, reg); 2004 return true; 2005 } 2006 2007 static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2008 const struct sys_reg_desc *r) 2009 { 2010 u32 csselr; 2011 2012 if (p->is_write) 2013 return write_to_read_only(vcpu, p, r); 2014 2015 csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1); 2016 csselr &= CSSELR_EL1_Level | CSSELR_EL1_InD; 2017 if (csselr < CSSELR_MAX) 2018 p->regval = get_ccsidr(vcpu, csselr); 2019 2020 return true; 2021 } 2022 2023 static unsigned int mte_visibility(const struct kvm_vcpu *vcpu, 2024 const struct sys_reg_desc *rd) 2025 { 2026 if (kvm_has_mte(vcpu->kvm)) 2027 return 0; 2028 2029 return REG_HIDDEN; 2030 } 2031 2032 #define MTE_REG(name) { \ 2033 SYS_DESC(SYS_##name), \ 2034 .access = undef_access, \ 2035 .reset = reset_unknown, \ 2036 .reg = name, \ 2037 .visibility = mte_visibility, \ 2038 } 2039 2040 static unsigned int el2_visibility(const struct kvm_vcpu *vcpu, 2041 const struct sys_reg_desc *rd) 2042 { 2043 if (vcpu_has_nv(vcpu)) 2044 return 0; 2045 2046 return REG_HIDDEN; 2047 } 2048 2049 static bool bad_vncr_trap(struct kvm_vcpu *vcpu, 2050 struct sys_reg_params *p, 2051 const struct sys_reg_desc *r) 2052 { 2053 /* 2054 * We really shouldn't be here, and this is likely the result 2055 * of a misconfigured trap, as this register should target the 2056 * VNCR page, and nothing else. 2057 */ 2058 return bad_trap(vcpu, p, r, 2059 "trap of VNCR-backed register"); 2060 } 2061 2062 static bool bad_redir_trap(struct kvm_vcpu *vcpu, 2063 struct sys_reg_params *p, 2064 const struct sys_reg_desc *r) 2065 { 2066 /* 2067 * We really shouldn't be here, and this is likely the result 2068 * of a misconfigured trap, as this register should target the 2069 * corresponding EL1, and nothing else. 2070 */ 2071 return bad_trap(vcpu, p, r, 2072 "trap of EL2 register redirected to EL1"); 2073 } 2074 2075 #define EL2_REG(name, acc, rst, v) { \ 2076 SYS_DESC(SYS_##name), \ 2077 .access = acc, \ 2078 .reset = rst, \ 2079 .reg = name, \ 2080 .visibility = el2_visibility, \ 2081 .val = v, \ 2082 } 2083 2084 #define EL2_REG_VNCR(name, rst, v) EL2_REG(name, bad_vncr_trap, rst, v) 2085 #define EL2_REG_REDIR(name, rst, v) EL2_REG(name, bad_redir_trap, rst, v) 2086 2087 /* 2088 * EL{0,1}2 registers are the EL2 view on an EL0 or EL1 register when 2089 * HCR_EL2.E2H==1, and only in the sysreg table for convenience of 2090 * handling traps. Given that, they are always hidden from userspace. 2091 */ 2092 static unsigned int hidden_user_visibility(const struct kvm_vcpu *vcpu, 2093 const struct sys_reg_desc *rd) 2094 { 2095 return REG_HIDDEN_USER; 2096 } 2097 2098 #define EL12_REG(name, acc, rst, v) { \ 2099 SYS_DESC(SYS_##name##_EL12), \ 2100 .access = acc, \ 2101 .reset = rst, \ 2102 .reg = name##_EL1, \ 2103 .val = v, \ 2104 .visibility = hidden_user_visibility, \ 2105 } 2106 2107 /* 2108 * Since reset() callback and field val are not used for idregs, they will be 2109 * used for specific purposes for idregs. 2110 * The reset() would return KVM sanitised register value. The value would be the 2111 * same as the host kernel sanitised value if there is no KVM sanitisation. 2112 * The val would be used as a mask indicating writable fields for the idreg. 2113 * Only bits with 1 are writable from userspace. This mask might not be 2114 * necessary in the future whenever all ID registers are enabled as writable 2115 * from userspace. 2116 */ 2117 2118 #define ID_DESC(name) \ 2119 SYS_DESC(SYS_##name), \ 2120 .access = access_id_reg, \ 2121 .get_user = get_id_reg \ 2122 2123 /* sys_reg_desc initialiser for known cpufeature ID registers */ 2124 #define ID_SANITISED(name) { \ 2125 ID_DESC(name), \ 2126 .set_user = set_id_reg, \ 2127 .visibility = id_visibility, \ 2128 .reset = kvm_read_sanitised_id_reg, \ 2129 .val = 0, \ 2130 } 2131 2132 /* sys_reg_desc initialiser for known cpufeature ID registers */ 2133 #define AA32_ID_SANITISED(name) { \ 2134 ID_DESC(name), \ 2135 .set_user = set_id_reg, \ 2136 .visibility = aa32_id_visibility, \ 2137 .reset = kvm_read_sanitised_id_reg, \ 2138 .val = 0, \ 2139 } 2140 2141 /* sys_reg_desc initialiser for writable ID registers */ 2142 #define ID_WRITABLE(name, mask) { \ 2143 ID_DESC(name), \ 2144 .set_user = set_id_reg, \ 2145 .visibility = id_visibility, \ 2146 .reset = kvm_read_sanitised_id_reg, \ 2147 .val = mask, \ 2148 } 2149 2150 /* 2151 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID 2152 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2 2153 * (1 <= crm < 8, 0 <= Op2 < 8). 2154 */ 2155 #define ID_UNALLOCATED(crm, op2) { \ 2156 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \ 2157 .access = access_id_reg, \ 2158 .get_user = get_id_reg, \ 2159 .set_user = set_id_reg, \ 2160 .visibility = raz_visibility, \ 2161 .reset = kvm_read_sanitised_id_reg, \ 2162 .val = 0, \ 2163 } 2164 2165 /* 2166 * sys_reg_desc initialiser for known ID registers that we hide from guests. 2167 * For now, these are exposed just like unallocated ID regs: they appear 2168 * RAZ for the guest. 2169 */ 2170 #define ID_HIDDEN(name) { \ 2171 ID_DESC(name), \ 2172 .set_user = set_id_reg, \ 2173 .visibility = raz_visibility, \ 2174 .reset = kvm_read_sanitised_id_reg, \ 2175 .val = 0, \ 2176 } 2177 2178 static bool access_sp_el1(struct kvm_vcpu *vcpu, 2179 struct sys_reg_params *p, 2180 const struct sys_reg_desc *r) 2181 { 2182 if (p->is_write) 2183 __vcpu_sys_reg(vcpu, SP_EL1) = p->regval; 2184 else 2185 p->regval = __vcpu_sys_reg(vcpu, SP_EL1); 2186 2187 return true; 2188 } 2189 2190 static bool access_elr(struct kvm_vcpu *vcpu, 2191 struct sys_reg_params *p, 2192 const struct sys_reg_desc *r) 2193 { 2194 if (p->is_write) 2195 vcpu_write_sys_reg(vcpu, p->regval, ELR_EL1); 2196 else 2197 p->regval = vcpu_read_sys_reg(vcpu, ELR_EL1); 2198 2199 return true; 2200 } 2201 2202 static bool access_spsr(struct kvm_vcpu *vcpu, 2203 struct sys_reg_params *p, 2204 const struct sys_reg_desc *r) 2205 { 2206 if (p->is_write) 2207 __vcpu_sys_reg(vcpu, SPSR_EL1) = p->regval; 2208 else 2209 p->regval = __vcpu_sys_reg(vcpu, SPSR_EL1); 2210 2211 return true; 2212 } 2213 2214 static u64 reset_hcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 2215 { 2216 u64 val = r->val; 2217 2218 if (!cpus_have_final_cap(ARM64_HAS_HCR_NV1)) 2219 val |= HCR_E2H; 2220 2221 return __vcpu_sys_reg(vcpu, r->reg) = val; 2222 } 2223 2224 static unsigned int sve_el2_visibility(const struct kvm_vcpu *vcpu, 2225 const struct sys_reg_desc *rd) 2226 { 2227 unsigned int r; 2228 2229 r = el2_visibility(vcpu, rd); 2230 if (r) 2231 return r; 2232 2233 return sve_visibility(vcpu, rd); 2234 } 2235 2236 static bool access_zcr_el2(struct kvm_vcpu *vcpu, 2237 struct sys_reg_params *p, 2238 const struct sys_reg_desc *r) 2239 { 2240 unsigned int vq; 2241 2242 if (guest_hyp_sve_traps_enabled(vcpu)) { 2243 kvm_inject_nested_sve_trap(vcpu); 2244 return true; 2245 } 2246 2247 if (!p->is_write) { 2248 p->regval = vcpu_read_sys_reg(vcpu, ZCR_EL2); 2249 return true; 2250 } 2251 2252 vq = SYS_FIELD_GET(ZCR_ELx, LEN, p->regval) + 1; 2253 vq = min(vq, vcpu_sve_max_vq(vcpu)); 2254 vcpu_write_sys_reg(vcpu, vq - 1, ZCR_EL2); 2255 return true; 2256 } 2257 2258 /* 2259 * Architected system registers. 2260 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2 2261 * 2262 * Debug handling: We do trap most, if not all debug related system 2263 * registers. The implementation is good enough to ensure that a guest 2264 * can use these with minimal performance degradation. The drawback is 2265 * that we don't implement any of the external debug architecture. 2266 * This should be revisited if we ever encounter a more demanding 2267 * guest... 2268 */ 2269 static const struct sys_reg_desc sys_reg_descs[] = { 2270 DBG_BCR_BVR_WCR_WVR_EL1(0), 2271 DBG_BCR_BVR_WCR_WVR_EL1(1), 2272 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 }, 2273 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 }, 2274 DBG_BCR_BVR_WCR_WVR_EL1(2), 2275 DBG_BCR_BVR_WCR_WVR_EL1(3), 2276 DBG_BCR_BVR_WCR_WVR_EL1(4), 2277 DBG_BCR_BVR_WCR_WVR_EL1(5), 2278 DBG_BCR_BVR_WCR_WVR_EL1(6), 2279 DBG_BCR_BVR_WCR_WVR_EL1(7), 2280 DBG_BCR_BVR_WCR_WVR_EL1(8), 2281 DBG_BCR_BVR_WCR_WVR_EL1(9), 2282 DBG_BCR_BVR_WCR_WVR_EL1(10), 2283 DBG_BCR_BVR_WCR_WVR_EL1(11), 2284 DBG_BCR_BVR_WCR_WVR_EL1(12), 2285 DBG_BCR_BVR_WCR_WVR_EL1(13), 2286 DBG_BCR_BVR_WCR_WVR_EL1(14), 2287 DBG_BCR_BVR_WCR_WVR_EL1(15), 2288 2289 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi }, 2290 { SYS_DESC(SYS_OSLAR_EL1), trap_oslar_el1 }, 2291 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1, 2292 OSLSR_EL1_OSLM_IMPLEMENTED, .set_user = set_oslsr_el1, }, 2293 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi }, 2294 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi }, 2295 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi }, 2296 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi }, 2297 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 }, 2298 2299 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi }, 2300 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi }, 2301 // DBGDTR[TR]X_EL0 share the same encoding 2302 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi }, 2303 2304 { SYS_DESC(SYS_DBGVCR32_EL2), trap_undef, reset_val, DBGVCR32_EL2, 0 }, 2305 2306 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 }, 2307 2308 /* 2309 * ID regs: all ID_SANITISED() entries here must have corresponding 2310 * entries in arm64_ftr_regs[]. 2311 */ 2312 2313 /* AArch64 mappings of the AArch32 ID registers */ 2314 /* CRm=1 */ 2315 AA32_ID_SANITISED(ID_PFR0_EL1), 2316 AA32_ID_SANITISED(ID_PFR1_EL1), 2317 { SYS_DESC(SYS_ID_DFR0_EL1), 2318 .access = access_id_reg, 2319 .get_user = get_id_reg, 2320 .set_user = set_id_dfr0_el1, 2321 .visibility = aa32_id_visibility, 2322 .reset = read_sanitised_id_dfr0_el1, 2323 .val = ID_DFR0_EL1_PerfMon_MASK | 2324 ID_DFR0_EL1_CopDbg_MASK, }, 2325 ID_HIDDEN(ID_AFR0_EL1), 2326 AA32_ID_SANITISED(ID_MMFR0_EL1), 2327 AA32_ID_SANITISED(ID_MMFR1_EL1), 2328 AA32_ID_SANITISED(ID_MMFR2_EL1), 2329 AA32_ID_SANITISED(ID_MMFR3_EL1), 2330 2331 /* CRm=2 */ 2332 AA32_ID_SANITISED(ID_ISAR0_EL1), 2333 AA32_ID_SANITISED(ID_ISAR1_EL1), 2334 AA32_ID_SANITISED(ID_ISAR2_EL1), 2335 AA32_ID_SANITISED(ID_ISAR3_EL1), 2336 AA32_ID_SANITISED(ID_ISAR4_EL1), 2337 AA32_ID_SANITISED(ID_ISAR5_EL1), 2338 AA32_ID_SANITISED(ID_MMFR4_EL1), 2339 AA32_ID_SANITISED(ID_ISAR6_EL1), 2340 2341 /* CRm=3 */ 2342 AA32_ID_SANITISED(MVFR0_EL1), 2343 AA32_ID_SANITISED(MVFR1_EL1), 2344 AA32_ID_SANITISED(MVFR2_EL1), 2345 ID_UNALLOCATED(3,3), 2346 AA32_ID_SANITISED(ID_PFR2_EL1), 2347 ID_HIDDEN(ID_DFR1_EL1), 2348 AA32_ID_SANITISED(ID_MMFR5_EL1), 2349 ID_UNALLOCATED(3,7), 2350 2351 /* AArch64 ID registers */ 2352 /* CRm=4 */ 2353 { SYS_DESC(SYS_ID_AA64PFR0_EL1), 2354 .access = access_id_reg, 2355 .get_user = get_id_reg, 2356 .set_user = set_id_reg, 2357 .reset = read_sanitised_id_aa64pfr0_el1, 2358 .val = ~(ID_AA64PFR0_EL1_AMU | 2359 ID_AA64PFR0_EL1_MPAM | 2360 ID_AA64PFR0_EL1_SVE | 2361 ID_AA64PFR0_EL1_RAS | 2362 ID_AA64PFR0_EL1_GIC | 2363 ID_AA64PFR0_EL1_AdvSIMD | 2364 ID_AA64PFR0_EL1_FP), }, 2365 ID_SANITISED(ID_AA64PFR1_EL1), 2366 ID_UNALLOCATED(4,2), 2367 ID_UNALLOCATED(4,3), 2368 ID_WRITABLE(ID_AA64ZFR0_EL1, ~ID_AA64ZFR0_EL1_RES0), 2369 ID_HIDDEN(ID_AA64SMFR0_EL1), 2370 ID_UNALLOCATED(4,6), 2371 ID_UNALLOCATED(4,7), 2372 2373 /* CRm=5 */ 2374 { SYS_DESC(SYS_ID_AA64DFR0_EL1), 2375 .access = access_id_reg, 2376 .get_user = get_id_reg, 2377 .set_user = set_id_aa64dfr0_el1, 2378 .reset = read_sanitised_id_aa64dfr0_el1, 2379 .val = ID_AA64DFR0_EL1_PMUVer_MASK | 2380 ID_AA64DFR0_EL1_DebugVer_MASK, }, 2381 ID_SANITISED(ID_AA64DFR1_EL1), 2382 ID_UNALLOCATED(5,2), 2383 ID_UNALLOCATED(5,3), 2384 ID_HIDDEN(ID_AA64AFR0_EL1), 2385 ID_HIDDEN(ID_AA64AFR1_EL1), 2386 ID_UNALLOCATED(5,6), 2387 ID_UNALLOCATED(5,7), 2388 2389 /* CRm=6 */ 2390 ID_WRITABLE(ID_AA64ISAR0_EL1, ~ID_AA64ISAR0_EL1_RES0), 2391 ID_WRITABLE(ID_AA64ISAR1_EL1, ~(ID_AA64ISAR1_EL1_GPI | 2392 ID_AA64ISAR1_EL1_GPA | 2393 ID_AA64ISAR1_EL1_API | 2394 ID_AA64ISAR1_EL1_APA)), 2395 ID_WRITABLE(ID_AA64ISAR2_EL1, ~(ID_AA64ISAR2_EL1_RES0 | 2396 ID_AA64ISAR2_EL1_APA3 | 2397 ID_AA64ISAR2_EL1_GPA3)), 2398 ID_UNALLOCATED(6,3), 2399 ID_UNALLOCATED(6,4), 2400 ID_UNALLOCATED(6,5), 2401 ID_UNALLOCATED(6,6), 2402 ID_UNALLOCATED(6,7), 2403 2404 /* CRm=7 */ 2405 ID_WRITABLE(ID_AA64MMFR0_EL1, ~(ID_AA64MMFR0_EL1_RES0 | 2406 ID_AA64MMFR0_EL1_TGRAN4_2 | 2407 ID_AA64MMFR0_EL1_TGRAN64_2 | 2408 ID_AA64MMFR0_EL1_TGRAN16_2)), 2409 ID_WRITABLE(ID_AA64MMFR1_EL1, ~(ID_AA64MMFR1_EL1_RES0 | 2410 ID_AA64MMFR1_EL1_HCX | 2411 ID_AA64MMFR1_EL1_TWED | 2412 ID_AA64MMFR1_EL1_XNX | 2413 ID_AA64MMFR1_EL1_VH | 2414 ID_AA64MMFR1_EL1_VMIDBits)), 2415 ID_WRITABLE(ID_AA64MMFR2_EL1, ~(ID_AA64MMFR2_EL1_RES0 | 2416 ID_AA64MMFR2_EL1_EVT | 2417 ID_AA64MMFR2_EL1_FWB | 2418 ID_AA64MMFR2_EL1_IDS | 2419 ID_AA64MMFR2_EL1_NV | 2420 ID_AA64MMFR2_EL1_CCIDX)), 2421 ID_SANITISED(ID_AA64MMFR3_EL1), 2422 ID_SANITISED(ID_AA64MMFR4_EL1), 2423 ID_UNALLOCATED(7,5), 2424 ID_UNALLOCATED(7,6), 2425 ID_UNALLOCATED(7,7), 2426 2427 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 }, 2428 { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 }, 2429 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 }, 2430 2431 MTE_REG(RGSR_EL1), 2432 MTE_REG(GCR_EL1), 2433 2434 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility }, 2435 { SYS_DESC(SYS_TRFCR_EL1), undef_access }, 2436 { SYS_DESC(SYS_SMPRI_EL1), undef_access }, 2437 { SYS_DESC(SYS_SMCR_EL1), undef_access }, 2438 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 }, 2439 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 }, 2440 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 }, 2441 { SYS_DESC(SYS_TCR2_EL1), access_vm_reg, reset_val, TCR2_EL1, 0 }, 2442 2443 PTRAUTH_KEY(APIA), 2444 PTRAUTH_KEY(APIB), 2445 PTRAUTH_KEY(APDA), 2446 PTRAUTH_KEY(APDB), 2447 PTRAUTH_KEY(APGA), 2448 2449 { SYS_DESC(SYS_SPSR_EL1), access_spsr}, 2450 { SYS_DESC(SYS_ELR_EL1), access_elr}, 2451 2452 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 }, 2453 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 }, 2454 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 }, 2455 2456 { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi }, 2457 { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi }, 2458 { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi }, 2459 { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi }, 2460 { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi }, 2461 { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi }, 2462 { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi }, 2463 { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi }, 2464 2465 MTE_REG(TFSR_EL1), 2466 MTE_REG(TFSRE0_EL1), 2467 2468 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 }, 2469 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 }, 2470 2471 { SYS_DESC(SYS_PMSCR_EL1), undef_access }, 2472 { SYS_DESC(SYS_PMSNEVFR_EL1), undef_access }, 2473 { SYS_DESC(SYS_PMSICR_EL1), undef_access }, 2474 { SYS_DESC(SYS_PMSIRR_EL1), undef_access }, 2475 { SYS_DESC(SYS_PMSFCR_EL1), undef_access }, 2476 { SYS_DESC(SYS_PMSEVFR_EL1), undef_access }, 2477 { SYS_DESC(SYS_PMSLATFR_EL1), undef_access }, 2478 { SYS_DESC(SYS_PMSIDR_EL1), undef_access }, 2479 { SYS_DESC(SYS_PMBLIMITR_EL1), undef_access }, 2480 { SYS_DESC(SYS_PMBPTR_EL1), undef_access }, 2481 { SYS_DESC(SYS_PMBSR_EL1), undef_access }, 2482 /* PMBIDR_EL1 is not trapped */ 2483 2484 { PMU_SYS_REG(PMINTENSET_EL1), 2485 .access = access_pminten, .reg = PMINTENSET_EL1, 2486 .get_user = get_pmreg, .set_user = set_pmreg }, 2487 { PMU_SYS_REG(PMINTENCLR_EL1), 2488 .access = access_pminten, .reg = PMINTENSET_EL1, 2489 .get_user = get_pmreg, .set_user = set_pmreg }, 2490 { SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi }, 2491 2492 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 }, 2493 { SYS_DESC(SYS_PIRE0_EL1), NULL, reset_unknown, PIRE0_EL1 }, 2494 { SYS_DESC(SYS_PIR_EL1), NULL, reset_unknown, PIR_EL1 }, 2495 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 }, 2496 2497 { SYS_DESC(SYS_LORSA_EL1), trap_loregion }, 2498 { SYS_DESC(SYS_LOREA_EL1), trap_loregion }, 2499 { SYS_DESC(SYS_LORN_EL1), trap_loregion }, 2500 { SYS_DESC(SYS_LORC_EL1), trap_loregion }, 2501 { SYS_DESC(SYS_LORID_EL1), trap_loregion }, 2502 2503 { SYS_DESC(SYS_VBAR_EL1), access_rw, reset_val, VBAR_EL1, 0 }, 2504 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 }, 2505 2506 { SYS_DESC(SYS_ICC_IAR0_EL1), write_to_read_only }, 2507 { SYS_DESC(SYS_ICC_EOIR0_EL1), read_from_write_only }, 2508 { SYS_DESC(SYS_ICC_HPPIR0_EL1), write_to_read_only }, 2509 { SYS_DESC(SYS_ICC_DIR_EL1), read_from_write_only }, 2510 { SYS_DESC(SYS_ICC_RPR_EL1), write_to_read_only }, 2511 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi }, 2512 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi }, 2513 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi }, 2514 { SYS_DESC(SYS_ICC_IAR1_EL1), write_to_read_only }, 2515 { SYS_DESC(SYS_ICC_EOIR1_EL1), read_from_write_only }, 2516 { SYS_DESC(SYS_ICC_HPPIR1_EL1), write_to_read_only }, 2517 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre }, 2518 2519 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 }, 2520 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 }, 2521 2522 { SYS_DESC(SYS_ACCDATA_EL1), undef_access }, 2523 2524 { SYS_DESC(SYS_SCXTNUM_EL1), undef_access }, 2525 2526 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0}, 2527 2528 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr }, 2529 { SYS_DESC(SYS_CLIDR_EL1), access_clidr, reset_clidr, CLIDR_EL1, 2530 .set_user = set_clidr, .val = ~CLIDR_EL1_RES0 }, 2531 { SYS_DESC(SYS_CCSIDR2_EL1), undef_access }, 2532 { SYS_DESC(SYS_SMIDR_EL1), undef_access }, 2533 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, 2534 ID_WRITABLE(CTR_EL0, CTR_EL0_DIC_MASK | 2535 CTR_EL0_IDC_MASK | 2536 CTR_EL0_DminLine_MASK | 2537 CTR_EL0_IminLine_MASK), 2538 { SYS_DESC(SYS_SVCR), undef_access }, 2539 2540 { PMU_SYS_REG(PMCR_EL0), .access = access_pmcr, .reset = reset_pmcr, 2541 .reg = PMCR_EL0, .get_user = get_pmcr, .set_user = set_pmcr }, 2542 { PMU_SYS_REG(PMCNTENSET_EL0), 2543 .access = access_pmcnten, .reg = PMCNTENSET_EL0, 2544 .get_user = get_pmreg, .set_user = set_pmreg }, 2545 { PMU_SYS_REG(PMCNTENCLR_EL0), 2546 .access = access_pmcnten, .reg = PMCNTENSET_EL0, 2547 .get_user = get_pmreg, .set_user = set_pmreg }, 2548 { PMU_SYS_REG(PMOVSCLR_EL0), 2549 .access = access_pmovs, .reg = PMOVSSET_EL0, 2550 .get_user = get_pmreg, .set_user = set_pmreg }, 2551 /* 2552 * PM_SWINC_EL0 is exposed to userspace as RAZ/WI, as it was 2553 * previously (and pointlessly) advertised in the past... 2554 */ 2555 { PMU_SYS_REG(PMSWINC_EL0), 2556 .get_user = get_raz_reg, .set_user = set_wi_reg, 2557 .access = access_pmswinc, .reset = NULL }, 2558 { PMU_SYS_REG(PMSELR_EL0), 2559 .access = access_pmselr, .reset = reset_pmselr, .reg = PMSELR_EL0 }, 2560 { PMU_SYS_REG(PMCEID0_EL0), 2561 .access = access_pmceid, .reset = NULL }, 2562 { PMU_SYS_REG(PMCEID1_EL0), 2563 .access = access_pmceid, .reset = NULL }, 2564 { PMU_SYS_REG(PMCCNTR_EL0), 2565 .access = access_pmu_evcntr, .reset = reset_unknown, 2566 .reg = PMCCNTR_EL0, .get_user = get_pmu_evcntr}, 2567 { PMU_SYS_REG(PMXEVTYPER_EL0), 2568 .access = access_pmu_evtyper, .reset = NULL }, 2569 { PMU_SYS_REG(PMXEVCNTR_EL0), 2570 .access = access_pmu_evcntr, .reset = NULL }, 2571 /* 2572 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero 2573 * in 32bit mode. Here we choose to reset it as zero for consistency. 2574 */ 2575 { PMU_SYS_REG(PMUSERENR_EL0), .access = access_pmuserenr, 2576 .reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 }, 2577 { PMU_SYS_REG(PMOVSSET_EL0), 2578 .access = access_pmovs, .reg = PMOVSSET_EL0, 2579 .get_user = get_pmreg, .set_user = set_pmreg }, 2580 2581 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 }, 2582 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 }, 2583 { SYS_DESC(SYS_TPIDR2_EL0), undef_access }, 2584 2585 { SYS_DESC(SYS_SCXTNUM_EL0), undef_access }, 2586 2587 { SYS_DESC(SYS_AMCR_EL0), undef_access }, 2588 { SYS_DESC(SYS_AMCFGR_EL0), undef_access }, 2589 { SYS_DESC(SYS_AMCGCR_EL0), undef_access }, 2590 { SYS_DESC(SYS_AMUSERENR_EL0), undef_access }, 2591 { SYS_DESC(SYS_AMCNTENCLR0_EL0), undef_access }, 2592 { SYS_DESC(SYS_AMCNTENSET0_EL0), undef_access }, 2593 { SYS_DESC(SYS_AMCNTENCLR1_EL0), undef_access }, 2594 { SYS_DESC(SYS_AMCNTENSET1_EL0), undef_access }, 2595 AMU_AMEVCNTR0_EL0(0), 2596 AMU_AMEVCNTR0_EL0(1), 2597 AMU_AMEVCNTR0_EL0(2), 2598 AMU_AMEVCNTR0_EL0(3), 2599 AMU_AMEVCNTR0_EL0(4), 2600 AMU_AMEVCNTR0_EL0(5), 2601 AMU_AMEVCNTR0_EL0(6), 2602 AMU_AMEVCNTR0_EL0(7), 2603 AMU_AMEVCNTR0_EL0(8), 2604 AMU_AMEVCNTR0_EL0(9), 2605 AMU_AMEVCNTR0_EL0(10), 2606 AMU_AMEVCNTR0_EL0(11), 2607 AMU_AMEVCNTR0_EL0(12), 2608 AMU_AMEVCNTR0_EL0(13), 2609 AMU_AMEVCNTR0_EL0(14), 2610 AMU_AMEVCNTR0_EL0(15), 2611 AMU_AMEVTYPER0_EL0(0), 2612 AMU_AMEVTYPER0_EL0(1), 2613 AMU_AMEVTYPER0_EL0(2), 2614 AMU_AMEVTYPER0_EL0(3), 2615 AMU_AMEVTYPER0_EL0(4), 2616 AMU_AMEVTYPER0_EL0(5), 2617 AMU_AMEVTYPER0_EL0(6), 2618 AMU_AMEVTYPER0_EL0(7), 2619 AMU_AMEVTYPER0_EL0(8), 2620 AMU_AMEVTYPER0_EL0(9), 2621 AMU_AMEVTYPER0_EL0(10), 2622 AMU_AMEVTYPER0_EL0(11), 2623 AMU_AMEVTYPER0_EL0(12), 2624 AMU_AMEVTYPER0_EL0(13), 2625 AMU_AMEVTYPER0_EL0(14), 2626 AMU_AMEVTYPER0_EL0(15), 2627 AMU_AMEVCNTR1_EL0(0), 2628 AMU_AMEVCNTR1_EL0(1), 2629 AMU_AMEVCNTR1_EL0(2), 2630 AMU_AMEVCNTR1_EL0(3), 2631 AMU_AMEVCNTR1_EL0(4), 2632 AMU_AMEVCNTR1_EL0(5), 2633 AMU_AMEVCNTR1_EL0(6), 2634 AMU_AMEVCNTR1_EL0(7), 2635 AMU_AMEVCNTR1_EL0(8), 2636 AMU_AMEVCNTR1_EL0(9), 2637 AMU_AMEVCNTR1_EL0(10), 2638 AMU_AMEVCNTR1_EL0(11), 2639 AMU_AMEVCNTR1_EL0(12), 2640 AMU_AMEVCNTR1_EL0(13), 2641 AMU_AMEVCNTR1_EL0(14), 2642 AMU_AMEVCNTR1_EL0(15), 2643 AMU_AMEVTYPER1_EL0(0), 2644 AMU_AMEVTYPER1_EL0(1), 2645 AMU_AMEVTYPER1_EL0(2), 2646 AMU_AMEVTYPER1_EL0(3), 2647 AMU_AMEVTYPER1_EL0(4), 2648 AMU_AMEVTYPER1_EL0(5), 2649 AMU_AMEVTYPER1_EL0(6), 2650 AMU_AMEVTYPER1_EL0(7), 2651 AMU_AMEVTYPER1_EL0(8), 2652 AMU_AMEVTYPER1_EL0(9), 2653 AMU_AMEVTYPER1_EL0(10), 2654 AMU_AMEVTYPER1_EL0(11), 2655 AMU_AMEVTYPER1_EL0(12), 2656 AMU_AMEVTYPER1_EL0(13), 2657 AMU_AMEVTYPER1_EL0(14), 2658 AMU_AMEVTYPER1_EL0(15), 2659 2660 { SYS_DESC(SYS_CNTPCT_EL0), access_arch_timer }, 2661 { SYS_DESC(SYS_CNTPCTSS_EL0), access_arch_timer }, 2662 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer }, 2663 { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer }, 2664 { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer }, 2665 2666 /* PMEVCNTRn_EL0 */ 2667 PMU_PMEVCNTR_EL0(0), 2668 PMU_PMEVCNTR_EL0(1), 2669 PMU_PMEVCNTR_EL0(2), 2670 PMU_PMEVCNTR_EL0(3), 2671 PMU_PMEVCNTR_EL0(4), 2672 PMU_PMEVCNTR_EL0(5), 2673 PMU_PMEVCNTR_EL0(6), 2674 PMU_PMEVCNTR_EL0(7), 2675 PMU_PMEVCNTR_EL0(8), 2676 PMU_PMEVCNTR_EL0(9), 2677 PMU_PMEVCNTR_EL0(10), 2678 PMU_PMEVCNTR_EL0(11), 2679 PMU_PMEVCNTR_EL0(12), 2680 PMU_PMEVCNTR_EL0(13), 2681 PMU_PMEVCNTR_EL0(14), 2682 PMU_PMEVCNTR_EL0(15), 2683 PMU_PMEVCNTR_EL0(16), 2684 PMU_PMEVCNTR_EL0(17), 2685 PMU_PMEVCNTR_EL0(18), 2686 PMU_PMEVCNTR_EL0(19), 2687 PMU_PMEVCNTR_EL0(20), 2688 PMU_PMEVCNTR_EL0(21), 2689 PMU_PMEVCNTR_EL0(22), 2690 PMU_PMEVCNTR_EL0(23), 2691 PMU_PMEVCNTR_EL0(24), 2692 PMU_PMEVCNTR_EL0(25), 2693 PMU_PMEVCNTR_EL0(26), 2694 PMU_PMEVCNTR_EL0(27), 2695 PMU_PMEVCNTR_EL0(28), 2696 PMU_PMEVCNTR_EL0(29), 2697 PMU_PMEVCNTR_EL0(30), 2698 /* PMEVTYPERn_EL0 */ 2699 PMU_PMEVTYPER_EL0(0), 2700 PMU_PMEVTYPER_EL0(1), 2701 PMU_PMEVTYPER_EL0(2), 2702 PMU_PMEVTYPER_EL0(3), 2703 PMU_PMEVTYPER_EL0(4), 2704 PMU_PMEVTYPER_EL0(5), 2705 PMU_PMEVTYPER_EL0(6), 2706 PMU_PMEVTYPER_EL0(7), 2707 PMU_PMEVTYPER_EL0(8), 2708 PMU_PMEVTYPER_EL0(9), 2709 PMU_PMEVTYPER_EL0(10), 2710 PMU_PMEVTYPER_EL0(11), 2711 PMU_PMEVTYPER_EL0(12), 2712 PMU_PMEVTYPER_EL0(13), 2713 PMU_PMEVTYPER_EL0(14), 2714 PMU_PMEVTYPER_EL0(15), 2715 PMU_PMEVTYPER_EL0(16), 2716 PMU_PMEVTYPER_EL0(17), 2717 PMU_PMEVTYPER_EL0(18), 2718 PMU_PMEVTYPER_EL0(19), 2719 PMU_PMEVTYPER_EL0(20), 2720 PMU_PMEVTYPER_EL0(21), 2721 PMU_PMEVTYPER_EL0(22), 2722 PMU_PMEVTYPER_EL0(23), 2723 PMU_PMEVTYPER_EL0(24), 2724 PMU_PMEVTYPER_EL0(25), 2725 PMU_PMEVTYPER_EL0(26), 2726 PMU_PMEVTYPER_EL0(27), 2727 PMU_PMEVTYPER_EL0(28), 2728 PMU_PMEVTYPER_EL0(29), 2729 PMU_PMEVTYPER_EL0(30), 2730 /* 2731 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero 2732 * in 32bit mode. Here we choose to reset it as zero for consistency. 2733 */ 2734 { PMU_SYS_REG(PMCCFILTR_EL0), .access = access_pmu_evtyper, 2735 .reset = reset_val, .reg = PMCCFILTR_EL0, .val = 0 }, 2736 2737 EL2_REG_VNCR(VPIDR_EL2, reset_unknown, 0), 2738 EL2_REG_VNCR(VMPIDR_EL2, reset_unknown, 0), 2739 EL2_REG(SCTLR_EL2, access_rw, reset_val, SCTLR_EL2_RES1), 2740 EL2_REG(ACTLR_EL2, access_rw, reset_val, 0), 2741 EL2_REG_VNCR(HCR_EL2, reset_hcr, 0), 2742 EL2_REG(MDCR_EL2, access_rw, reset_val, 0), 2743 EL2_REG(CPTR_EL2, access_rw, reset_val, CPTR_NVHE_EL2_RES1), 2744 EL2_REG_VNCR(HSTR_EL2, reset_val, 0), 2745 EL2_REG_VNCR(HFGRTR_EL2, reset_val, 0), 2746 EL2_REG_VNCR(HFGWTR_EL2, reset_val, 0), 2747 EL2_REG_VNCR(HFGITR_EL2, reset_val, 0), 2748 EL2_REG_VNCR(HACR_EL2, reset_val, 0), 2749 2750 { SYS_DESC(SYS_ZCR_EL2), .access = access_zcr_el2, .reset = reset_val, 2751 .visibility = sve_el2_visibility, .reg = ZCR_EL2 }, 2752 2753 EL2_REG_VNCR(HCRX_EL2, reset_val, 0), 2754 2755 EL2_REG(TTBR0_EL2, access_rw, reset_val, 0), 2756 EL2_REG(TTBR1_EL2, access_rw, reset_val, 0), 2757 EL2_REG(TCR_EL2, access_rw, reset_val, TCR_EL2_RES1), 2758 EL2_REG_VNCR(VTTBR_EL2, reset_val, 0), 2759 EL2_REG_VNCR(VTCR_EL2, reset_val, 0), 2760 2761 { SYS_DESC(SYS_DACR32_EL2), trap_undef, reset_unknown, DACR32_EL2 }, 2762 EL2_REG_VNCR(HDFGRTR_EL2, reset_val, 0), 2763 EL2_REG_VNCR(HDFGWTR_EL2, reset_val, 0), 2764 EL2_REG_VNCR(HAFGRTR_EL2, reset_val, 0), 2765 EL2_REG_REDIR(SPSR_EL2, reset_val, 0), 2766 EL2_REG_REDIR(ELR_EL2, reset_val, 0), 2767 { SYS_DESC(SYS_SP_EL1), access_sp_el1}, 2768 2769 /* AArch32 SPSR_* are RES0 if trapped from a NV guest */ 2770 { SYS_DESC(SYS_SPSR_irq), .access = trap_raz_wi, 2771 .visibility = hidden_user_visibility }, 2772 { SYS_DESC(SYS_SPSR_abt), .access = trap_raz_wi, 2773 .visibility = hidden_user_visibility }, 2774 { SYS_DESC(SYS_SPSR_und), .access = trap_raz_wi, 2775 .visibility = hidden_user_visibility }, 2776 { SYS_DESC(SYS_SPSR_fiq), .access = trap_raz_wi, 2777 .visibility = hidden_user_visibility }, 2778 2779 { SYS_DESC(SYS_IFSR32_EL2), trap_undef, reset_unknown, IFSR32_EL2 }, 2780 EL2_REG(AFSR0_EL2, access_rw, reset_val, 0), 2781 EL2_REG(AFSR1_EL2, access_rw, reset_val, 0), 2782 EL2_REG_REDIR(ESR_EL2, reset_val, 0), 2783 { SYS_DESC(SYS_FPEXC32_EL2), trap_undef, reset_val, FPEXC32_EL2, 0x700 }, 2784 2785 EL2_REG_REDIR(FAR_EL2, reset_val, 0), 2786 EL2_REG(HPFAR_EL2, access_rw, reset_val, 0), 2787 2788 EL2_REG(MAIR_EL2, access_rw, reset_val, 0), 2789 EL2_REG(AMAIR_EL2, access_rw, reset_val, 0), 2790 2791 EL2_REG(VBAR_EL2, access_rw, reset_val, 0), 2792 EL2_REG(RVBAR_EL2, access_rw, reset_val, 0), 2793 { SYS_DESC(SYS_RMR_EL2), trap_undef }, 2794 2795 EL2_REG(CONTEXTIDR_EL2, access_rw, reset_val, 0), 2796 EL2_REG(TPIDR_EL2, access_rw, reset_val, 0), 2797 2798 EL2_REG_VNCR(CNTVOFF_EL2, reset_val, 0), 2799 EL2_REG(CNTHCTL_EL2, access_rw, reset_val, 0), 2800 2801 EL12_REG(CNTKCTL, access_rw, reset_val, 0), 2802 2803 EL2_REG(SP_EL2, NULL, reset_unknown, 0), 2804 }; 2805 2806 static bool kvm_supported_tlbi_s12_op(struct kvm_vcpu *vpcu, u32 instr) 2807 { 2808 struct kvm *kvm = vpcu->kvm; 2809 u8 CRm = sys_reg_CRm(instr); 2810 2811 if (sys_reg_CRn(instr) == TLBI_CRn_nXS && 2812 !kvm_has_feat(kvm, ID_AA64ISAR1_EL1, XS, IMP)) 2813 return false; 2814 2815 if (CRm == TLBI_CRm_nROS && 2816 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 2817 return false; 2818 2819 return true; 2820 } 2821 2822 static bool handle_alle1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2823 const struct sys_reg_desc *r) 2824 { 2825 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 2826 2827 if (!kvm_supported_tlbi_s12_op(vcpu, sys_encoding)) { 2828 kvm_inject_undefined(vcpu); 2829 return false; 2830 } 2831 2832 write_lock(&vcpu->kvm->mmu_lock); 2833 2834 /* 2835 * Drop all shadow S2s, resulting in S1/S2 TLBIs for each of the 2836 * corresponding VMIDs. 2837 */ 2838 kvm_nested_s2_unmap(vcpu->kvm); 2839 2840 write_unlock(&vcpu->kvm->mmu_lock); 2841 2842 return true; 2843 } 2844 2845 static bool kvm_supported_tlbi_ipas2_op(struct kvm_vcpu *vpcu, u32 instr) 2846 { 2847 struct kvm *kvm = vpcu->kvm; 2848 u8 CRm = sys_reg_CRm(instr); 2849 u8 Op2 = sys_reg_Op2(instr); 2850 2851 if (sys_reg_CRn(instr) == TLBI_CRn_nXS && 2852 !kvm_has_feat(kvm, ID_AA64ISAR1_EL1, XS, IMP)) 2853 return false; 2854 2855 if (CRm == TLBI_CRm_IPAIS && (Op2 == 2 || Op2 == 6) && 2856 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE)) 2857 return false; 2858 2859 if (CRm == TLBI_CRm_IPAONS && (Op2 == 0 || Op2 == 4) && 2860 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 2861 return false; 2862 2863 if (CRm == TLBI_CRm_IPAONS && (Op2 == 3 || Op2 == 7) && 2864 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE)) 2865 return false; 2866 2867 return true; 2868 } 2869 2870 /* Only defined here as this is an internal "abstraction" */ 2871 union tlbi_info { 2872 struct { 2873 u64 start; 2874 u64 size; 2875 } range; 2876 2877 struct { 2878 u64 addr; 2879 } ipa; 2880 2881 struct { 2882 u64 addr; 2883 u32 encoding; 2884 } va; 2885 }; 2886 2887 static void s2_mmu_unmap_range(struct kvm_s2_mmu *mmu, 2888 const union tlbi_info *info) 2889 { 2890 kvm_stage2_unmap_range(mmu, info->range.start, info->range.size); 2891 } 2892 2893 static bool handle_vmalls12e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2894 const struct sys_reg_desc *r) 2895 { 2896 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 2897 u64 limit, vttbr; 2898 2899 if (!kvm_supported_tlbi_s12_op(vcpu, sys_encoding)) { 2900 kvm_inject_undefined(vcpu); 2901 return false; 2902 } 2903 2904 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 2905 limit = BIT_ULL(kvm_get_pa_bits(vcpu->kvm)); 2906 2907 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 2908 &(union tlbi_info) { 2909 .range = { 2910 .start = 0, 2911 .size = limit, 2912 }, 2913 }, 2914 s2_mmu_unmap_range); 2915 2916 return true; 2917 } 2918 2919 static bool handle_ripas2e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2920 const struct sys_reg_desc *r) 2921 { 2922 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 2923 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 2924 u64 base, range, tg, num, scale; 2925 int shift; 2926 2927 if (!kvm_supported_tlbi_ipas2_op(vcpu, sys_encoding)) { 2928 kvm_inject_undefined(vcpu); 2929 return false; 2930 } 2931 2932 /* 2933 * Because the shadow S2 structure doesn't necessarily reflect that 2934 * of the guest's S2 (different base granule size, for example), we 2935 * decide to ignore TTL and only use the described range. 2936 */ 2937 tg = FIELD_GET(GENMASK(47, 46), p->regval); 2938 scale = FIELD_GET(GENMASK(45, 44), p->regval); 2939 num = FIELD_GET(GENMASK(43, 39), p->regval); 2940 base = p->regval & GENMASK(36, 0); 2941 2942 switch(tg) { 2943 case 1: 2944 shift = 12; 2945 break; 2946 case 2: 2947 shift = 14; 2948 break; 2949 case 3: 2950 default: /* IMPDEF: handle tg==0 as 64k */ 2951 shift = 16; 2952 break; 2953 } 2954 2955 base <<= shift; 2956 range = __TLBI_RANGE_PAGES(num, scale) << shift; 2957 2958 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 2959 &(union tlbi_info) { 2960 .range = { 2961 .start = base, 2962 .size = range, 2963 }, 2964 }, 2965 s2_mmu_unmap_range); 2966 2967 return true; 2968 } 2969 2970 static void s2_mmu_unmap_ipa(struct kvm_s2_mmu *mmu, 2971 const union tlbi_info *info) 2972 { 2973 unsigned long max_size; 2974 u64 base_addr; 2975 2976 /* 2977 * We drop a number of things from the supplied value: 2978 * 2979 * - NS bit: we're non-secure only. 2980 * 2981 * - IPA[51:48]: We don't support 52bit IPA just yet... 2982 * 2983 * And of course, adjust the IPA to be on an actual address. 2984 */ 2985 base_addr = (info->ipa.addr & GENMASK_ULL(35, 0)) << 12; 2986 max_size = compute_tlb_inval_range(mmu, info->ipa.addr); 2987 base_addr &= ~(max_size - 1); 2988 2989 kvm_stage2_unmap_range(mmu, base_addr, max_size); 2990 } 2991 2992 static bool handle_ipas2e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2993 const struct sys_reg_desc *r) 2994 { 2995 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 2996 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 2997 2998 if (!kvm_supported_tlbi_ipas2_op(vcpu, sys_encoding)) { 2999 kvm_inject_undefined(vcpu); 3000 return false; 3001 } 3002 3003 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 3004 &(union tlbi_info) { 3005 .ipa = { 3006 .addr = p->regval, 3007 }, 3008 }, 3009 s2_mmu_unmap_ipa); 3010 3011 return true; 3012 } 3013 3014 static void s2_mmu_tlbi_s1e1(struct kvm_s2_mmu *mmu, 3015 const union tlbi_info *info) 3016 { 3017 WARN_ON(__kvm_tlbi_s1e2(mmu, info->va.addr, info->va.encoding)); 3018 } 3019 3020 static bool handle_tlbi_el1(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3021 const struct sys_reg_desc *r) 3022 { 3023 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3024 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 3025 3026 /* 3027 * If we're here, this is because we've trapped on a EL1 TLBI 3028 * instruction that affects the EL1 translation regime while 3029 * we're running in a context that doesn't allow us to let the 3030 * HW do its thing (aka vEL2): 3031 * 3032 * - HCR_EL2.E2H == 0 : a non-VHE guest 3033 * - HCR_EL2.{E2H,TGE} == { 1, 0 } : a VHE guest in guest mode 3034 * 3035 * We don't expect these helpers to ever be called when running 3036 * in a vEL1 context. 3037 */ 3038 3039 WARN_ON(!vcpu_is_el2(vcpu)); 3040 3041 if (!kvm_supported_tlbi_s1e1_op(vcpu, sys_encoding)) { 3042 kvm_inject_undefined(vcpu); 3043 return false; 3044 } 3045 3046 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 3047 &(union tlbi_info) { 3048 .va = { 3049 .addr = p->regval, 3050 .encoding = sys_encoding, 3051 }, 3052 }, 3053 s2_mmu_tlbi_s1e1); 3054 3055 return true; 3056 } 3057 3058 #define SYS_INSN(insn, access_fn) \ 3059 { \ 3060 SYS_DESC(OP_##insn), \ 3061 .access = (access_fn), \ 3062 } 3063 3064 static struct sys_reg_desc sys_insn_descs[] = { 3065 { SYS_DESC(SYS_DC_ISW), access_dcsw }, 3066 { SYS_DESC(SYS_DC_IGSW), access_dcgsw }, 3067 { SYS_DESC(SYS_DC_IGDSW), access_dcgsw }, 3068 { SYS_DESC(SYS_DC_CSW), access_dcsw }, 3069 { SYS_DESC(SYS_DC_CGSW), access_dcgsw }, 3070 { SYS_DESC(SYS_DC_CGDSW), access_dcgsw }, 3071 { SYS_DESC(SYS_DC_CISW), access_dcsw }, 3072 { SYS_DESC(SYS_DC_CIGSW), access_dcgsw }, 3073 { SYS_DESC(SYS_DC_CIGDSW), access_dcgsw }, 3074 3075 SYS_INSN(TLBI_VMALLE1OS, handle_tlbi_el1), 3076 SYS_INSN(TLBI_VAE1OS, handle_tlbi_el1), 3077 SYS_INSN(TLBI_ASIDE1OS, handle_tlbi_el1), 3078 SYS_INSN(TLBI_VAAE1OS, handle_tlbi_el1), 3079 SYS_INSN(TLBI_VALE1OS, handle_tlbi_el1), 3080 SYS_INSN(TLBI_VAALE1OS, handle_tlbi_el1), 3081 3082 SYS_INSN(TLBI_RVAE1IS, handle_tlbi_el1), 3083 SYS_INSN(TLBI_RVAAE1IS, handle_tlbi_el1), 3084 SYS_INSN(TLBI_RVALE1IS, handle_tlbi_el1), 3085 SYS_INSN(TLBI_RVAALE1IS, handle_tlbi_el1), 3086 3087 SYS_INSN(TLBI_VMALLE1IS, handle_tlbi_el1), 3088 SYS_INSN(TLBI_VAE1IS, handle_tlbi_el1), 3089 SYS_INSN(TLBI_ASIDE1IS, handle_tlbi_el1), 3090 SYS_INSN(TLBI_VAAE1IS, handle_tlbi_el1), 3091 SYS_INSN(TLBI_VALE1IS, handle_tlbi_el1), 3092 SYS_INSN(TLBI_VAALE1IS, handle_tlbi_el1), 3093 3094 SYS_INSN(TLBI_RVAE1OS, handle_tlbi_el1), 3095 SYS_INSN(TLBI_RVAAE1OS, handle_tlbi_el1), 3096 SYS_INSN(TLBI_RVALE1OS, handle_tlbi_el1), 3097 SYS_INSN(TLBI_RVAALE1OS, handle_tlbi_el1), 3098 3099 SYS_INSN(TLBI_RVAE1, handle_tlbi_el1), 3100 SYS_INSN(TLBI_RVAAE1, handle_tlbi_el1), 3101 SYS_INSN(TLBI_RVALE1, handle_tlbi_el1), 3102 SYS_INSN(TLBI_RVAALE1, handle_tlbi_el1), 3103 3104 SYS_INSN(TLBI_VMALLE1, handle_tlbi_el1), 3105 SYS_INSN(TLBI_VAE1, handle_tlbi_el1), 3106 SYS_INSN(TLBI_ASIDE1, handle_tlbi_el1), 3107 SYS_INSN(TLBI_VAAE1, handle_tlbi_el1), 3108 SYS_INSN(TLBI_VALE1, handle_tlbi_el1), 3109 SYS_INSN(TLBI_VAALE1, handle_tlbi_el1), 3110 3111 SYS_INSN(TLBI_VMALLE1OSNXS, handle_tlbi_el1), 3112 SYS_INSN(TLBI_VAE1OSNXS, handle_tlbi_el1), 3113 SYS_INSN(TLBI_ASIDE1OSNXS, handle_tlbi_el1), 3114 SYS_INSN(TLBI_VAAE1OSNXS, handle_tlbi_el1), 3115 SYS_INSN(TLBI_VALE1OSNXS, handle_tlbi_el1), 3116 SYS_INSN(TLBI_VAALE1OSNXS, handle_tlbi_el1), 3117 3118 SYS_INSN(TLBI_RVAE1ISNXS, handle_tlbi_el1), 3119 SYS_INSN(TLBI_RVAAE1ISNXS, handle_tlbi_el1), 3120 SYS_INSN(TLBI_RVALE1ISNXS, handle_tlbi_el1), 3121 SYS_INSN(TLBI_RVAALE1ISNXS, handle_tlbi_el1), 3122 3123 SYS_INSN(TLBI_VMALLE1ISNXS, handle_tlbi_el1), 3124 SYS_INSN(TLBI_VAE1ISNXS, handle_tlbi_el1), 3125 SYS_INSN(TLBI_ASIDE1ISNXS, handle_tlbi_el1), 3126 SYS_INSN(TLBI_VAAE1ISNXS, handle_tlbi_el1), 3127 SYS_INSN(TLBI_VALE1ISNXS, handle_tlbi_el1), 3128 SYS_INSN(TLBI_VAALE1ISNXS, handle_tlbi_el1), 3129 3130 SYS_INSN(TLBI_RVAE1OSNXS, handle_tlbi_el1), 3131 SYS_INSN(TLBI_RVAAE1OSNXS, handle_tlbi_el1), 3132 SYS_INSN(TLBI_RVALE1OSNXS, handle_tlbi_el1), 3133 SYS_INSN(TLBI_RVAALE1OSNXS, handle_tlbi_el1), 3134 3135 SYS_INSN(TLBI_RVAE1NXS, handle_tlbi_el1), 3136 SYS_INSN(TLBI_RVAAE1NXS, handle_tlbi_el1), 3137 SYS_INSN(TLBI_RVALE1NXS, handle_tlbi_el1), 3138 SYS_INSN(TLBI_RVAALE1NXS, handle_tlbi_el1), 3139 3140 SYS_INSN(TLBI_VMALLE1NXS, handle_tlbi_el1), 3141 SYS_INSN(TLBI_VAE1NXS, handle_tlbi_el1), 3142 SYS_INSN(TLBI_ASIDE1NXS, handle_tlbi_el1), 3143 SYS_INSN(TLBI_VAAE1NXS, handle_tlbi_el1), 3144 SYS_INSN(TLBI_VALE1NXS, handle_tlbi_el1), 3145 SYS_INSN(TLBI_VAALE1NXS, handle_tlbi_el1), 3146 3147 SYS_INSN(TLBI_IPAS2E1IS, handle_ipas2e1is), 3148 SYS_INSN(TLBI_RIPAS2E1IS, handle_ripas2e1is), 3149 SYS_INSN(TLBI_IPAS2LE1IS, handle_ipas2e1is), 3150 SYS_INSN(TLBI_RIPAS2LE1IS, handle_ripas2e1is), 3151 3152 SYS_INSN(TLBI_ALLE2OS, trap_undef), 3153 SYS_INSN(TLBI_VAE2OS, trap_undef), 3154 SYS_INSN(TLBI_ALLE1OS, handle_alle1is), 3155 SYS_INSN(TLBI_VALE2OS, trap_undef), 3156 SYS_INSN(TLBI_VMALLS12E1OS, handle_vmalls12e1is), 3157 3158 SYS_INSN(TLBI_RVAE2IS, trap_undef), 3159 SYS_INSN(TLBI_RVALE2IS, trap_undef), 3160 3161 SYS_INSN(TLBI_ALLE1IS, handle_alle1is), 3162 SYS_INSN(TLBI_VMALLS12E1IS, handle_vmalls12e1is), 3163 SYS_INSN(TLBI_IPAS2E1OS, handle_ipas2e1is), 3164 SYS_INSN(TLBI_IPAS2E1, handle_ipas2e1is), 3165 SYS_INSN(TLBI_RIPAS2E1, handle_ripas2e1is), 3166 SYS_INSN(TLBI_RIPAS2E1OS, handle_ripas2e1is), 3167 SYS_INSN(TLBI_IPAS2LE1OS, handle_ipas2e1is), 3168 SYS_INSN(TLBI_IPAS2LE1, handle_ipas2e1is), 3169 SYS_INSN(TLBI_RIPAS2LE1, handle_ripas2e1is), 3170 SYS_INSN(TLBI_RIPAS2LE1OS, handle_ripas2e1is), 3171 SYS_INSN(TLBI_RVAE2OS, trap_undef), 3172 SYS_INSN(TLBI_RVALE2OS, trap_undef), 3173 SYS_INSN(TLBI_RVAE2, trap_undef), 3174 SYS_INSN(TLBI_RVALE2, trap_undef), 3175 SYS_INSN(TLBI_ALLE1, handle_alle1is), 3176 SYS_INSN(TLBI_VMALLS12E1, handle_vmalls12e1is), 3177 3178 SYS_INSN(TLBI_IPAS2E1ISNXS, handle_ipas2e1is), 3179 SYS_INSN(TLBI_RIPAS2E1ISNXS, handle_ripas2e1is), 3180 SYS_INSN(TLBI_IPAS2LE1ISNXS, handle_ipas2e1is), 3181 SYS_INSN(TLBI_RIPAS2LE1ISNXS, handle_ripas2e1is), 3182 3183 SYS_INSN(TLBI_ALLE2OSNXS, trap_undef), 3184 SYS_INSN(TLBI_VAE2OSNXS, trap_undef), 3185 SYS_INSN(TLBI_ALLE1OSNXS, handle_alle1is), 3186 SYS_INSN(TLBI_VALE2OSNXS, trap_undef), 3187 SYS_INSN(TLBI_VMALLS12E1OSNXS, handle_vmalls12e1is), 3188 3189 SYS_INSN(TLBI_RVAE2ISNXS, trap_undef), 3190 SYS_INSN(TLBI_RVALE2ISNXS, trap_undef), 3191 SYS_INSN(TLBI_ALLE2ISNXS, trap_undef), 3192 SYS_INSN(TLBI_VAE2ISNXS, trap_undef), 3193 3194 SYS_INSN(TLBI_ALLE1ISNXS, handle_alle1is), 3195 SYS_INSN(TLBI_VALE2ISNXS, trap_undef), 3196 SYS_INSN(TLBI_VMALLS12E1ISNXS, handle_vmalls12e1is), 3197 SYS_INSN(TLBI_IPAS2E1OSNXS, handle_ipas2e1is), 3198 SYS_INSN(TLBI_IPAS2E1NXS, handle_ipas2e1is), 3199 SYS_INSN(TLBI_RIPAS2E1NXS, handle_ripas2e1is), 3200 SYS_INSN(TLBI_RIPAS2E1OSNXS, handle_ripas2e1is), 3201 SYS_INSN(TLBI_IPAS2LE1OSNXS, handle_ipas2e1is), 3202 SYS_INSN(TLBI_IPAS2LE1NXS, handle_ipas2e1is), 3203 SYS_INSN(TLBI_RIPAS2LE1NXS, handle_ripas2e1is), 3204 SYS_INSN(TLBI_RIPAS2LE1OSNXS, handle_ripas2e1is), 3205 SYS_INSN(TLBI_RVAE2OSNXS, trap_undef), 3206 SYS_INSN(TLBI_RVALE2OSNXS, trap_undef), 3207 SYS_INSN(TLBI_RVAE2NXS, trap_undef), 3208 SYS_INSN(TLBI_RVALE2NXS, trap_undef), 3209 SYS_INSN(TLBI_ALLE2NXS, trap_undef), 3210 SYS_INSN(TLBI_VAE2NXS, trap_undef), 3211 SYS_INSN(TLBI_ALLE1NXS, handle_alle1is), 3212 SYS_INSN(TLBI_VALE2NXS, trap_undef), 3213 SYS_INSN(TLBI_VMALLS12E1NXS, handle_vmalls12e1is), 3214 }; 3215 3216 static bool trap_dbgdidr(struct kvm_vcpu *vcpu, 3217 struct sys_reg_params *p, 3218 const struct sys_reg_desc *r) 3219 { 3220 if (p->is_write) { 3221 return ignore_write(vcpu, p); 3222 } else { 3223 u64 dfr = kvm_read_vm_id_reg(vcpu->kvm, SYS_ID_AA64DFR0_EL1); 3224 u32 el3 = kvm_has_feat(vcpu->kvm, ID_AA64PFR0_EL1, EL3, IMP); 3225 3226 p->regval = ((SYS_FIELD_GET(ID_AA64DFR0_EL1, WRPs, dfr) << 28) | 3227 (SYS_FIELD_GET(ID_AA64DFR0_EL1, BRPs, dfr) << 24) | 3228 (SYS_FIELD_GET(ID_AA64DFR0_EL1, CTX_CMPs, dfr) << 20) | 3229 (SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, dfr) << 16) | 3230 (1 << 15) | (el3 << 14) | (el3 << 12)); 3231 return true; 3232 } 3233 } 3234 3235 /* 3236 * AArch32 debug register mappings 3237 * 3238 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0] 3239 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32] 3240 * 3241 * None of the other registers share their location, so treat them as 3242 * if they were 64bit. 3243 */ 3244 #define DBG_BCR_BVR_WCR_WVR(n) \ 3245 /* DBGBVRn */ \ 3246 { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \ 3247 /* DBGBCRn */ \ 3248 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \ 3249 /* DBGWVRn */ \ 3250 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \ 3251 /* DBGWCRn */ \ 3252 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n } 3253 3254 #define DBGBXVR(n) \ 3255 { AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_bvr, NULL, n } 3256 3257 /* 3258 * Trapped cp14 registers. We generally ignore most of the external 3259 * debug, on the principle that they don't really make sense to a 3260 * guest. Revisit this one day, would this principle change. 3261 */ 3262 static const struct sys_reg_desc cp14_regs[] = { 3263 /* DBGDIDR */ 3264 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgdidr }, 3265 /* DBGDTRRXext */ 3266 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi }, 3267 3268 DBG_BCR_BVR_WCR_WVR(0), 3269 /* DBGDSCRint */ 3270 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi }, 3271 DBG_BCR_BVR_WCR_WVR(1), 3272 /* DBGDCCINT */ 3273 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug_regs, NULL, MDCCINT_EL1 }, 3274 /* DBGDSCRext */ 3275 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug_regs, NULL, MDSCR_EL1 }, 3276 DBG_BCR_BVR_WCR_WVR(2), 3277 /* DBGDTR[RT]Xint */ 3278 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi }, 3279 /* DBGDTR[RT]Xext */ 3280 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi }, 3281 DBG_BCR_BVR_WCR_WVR(3), 3282 DBG_BCR_BVR_WCR_WVR(4), 3283 DBG_BCR_BVR_WCR_WVR(5), 3284 /* DBGWFAR */ 3285 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi }, 3286 /* DBGOSECCR */ 3287 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi }, 3288 DBG_BCR_BVR_WCR_WVR(6), 3289 /* DBGVCR */ 3290 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug_regs, NULL, DBGVCR32_EL2 }, 3291 DBG_BCR_BVR_WCR_WVR(7), 3292 DBG_BCR_BVR_WCR_WVR(8), 3293 DBG_BCR_BVR_WCR_WVR(9), 3294 DBG_BCR_BVR_WCR_WVR(10), 3295 DBG_BCR_BVR_WCR_WVR(11), 3296 DBG_BCR_BVR_WCR_WVR(12), 3297 DBG_BCR_BVR_WCR_WVR(13), 3298 DBG_BCR_BVR_WCR_WVR(14), 3299 DBG_BCR_BVR_WCR_WVR(15), 3300 3301 /* DBGDRAR (32bit) */ 3302 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi }, 3303 3304 DBGBXVR(0), 3305 /* DBGOSLAR */ 3306 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_oslar_el1 }, 3307 DBGBXVR(1), 3308 /* DBGOSLSR */ 3309 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1, NULL, OSLSR_EL1 }, 3310 DBGBXVR(2), 3311 DBGBXVR(3), 3312 /* DBGOSDLR */ 3313 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi }, 3314 DBGBXVR(4), 3315 /* DBGPRCR */ 3316 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi }, 3317 DBGBXVR(5), 3318 DBGBXVR(6), 3319 DBGBXVR(7), 3320 DBGBXVR(8), 3321 DBGBXVR(9), 3322 DBGBXVR(10), 3323 DBGBXVR(11), 3324 DBGBXVR(12), 3325 DBGBXVR(13), 3326 DBGBXVR(14), 3327 DBGBXVR(15), 3328 3329 /* DBGDSAR (32bit) */ 3330 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi }, 3331 3332 /* DBGDEVID2 */ 3333 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi }, 3334 /* DBGDEVID1 */ 3335 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi }, 3336 /* DBGDEVID */ 3337 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi }, 3338 /* DBGCLAIMSET */ 3339 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi }, 3340 /* DBGCLAIMCLR */ 3341 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi }, 3342 /* DBGAUTHSTATUS */ 3343 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 }, 3344 }; 3345 3346 /* Trapped cp14 64bit registers */ 3347 static const struct sys_reg_desc cp14_64_regs[] = { 3348 /* DBGDRAR (64bit) */ 3349 { Op1( 0), CRm( 1), .access = trap_raz_wi }, 3350 3351 /* DBGDSAR (64bit) */ 3352 { Op1( 0), CRm( 2), .access = trap_raz_wi }, 3353 }; 3354 3355 #define CP15_PMU_SYS_REG(_map, _Op1, _CRn, _CRm, _Op2) \ 3356 AA32(_map), \ 3357 Op1(_Op1), CRn(_CRn), CRm(_CRm), Op2(_Op2), \ 3358 .visibility = pmu_visibility 3359 3360 /* Macro to expand the PMEVCNTRn register */ 3361 #define PMU_PMEVCNTR(n) \ 3362 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \ 3363 (0b1000 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \ 3364 .access = access_pmu_evcntr } 3365 3366 /* Macro to expand the PMEVTYPERn register */ 3367 #define PMU_PMEVTYPER(n) \ 3368 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \ 3369 (0b1100 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \ 3370 .access = access_pmu_evtyper } 3371 /* 3372 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding, 3373 * depending on the way they are accessed (as a 32bit or a 64bit 3374 * register). 3375 */ 3376 static const struct sys_reg_desc cp15_regs[] = { 3377 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr }, 3378 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, SCTLR_EL1 }, 3379 /* ACTLR */ 3380 { AA32(LO), Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr, NULL, ACTLR_EL1 }, 3381 /* ACTLR2 */ 3382 { AA32(HI), Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr, NULL, ACTLR_EL1 }, 3383 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, 3384 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, TTBR1_EL1 }, 3385 /* TTBCR */ 3386 { AA32(LO), Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 }, 3387 /* TTBCR2 */ 3388 { AA32(HI), Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, TCR_EL1 }, 3389 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, DACR32_EL2 }, 3390 /* DFSR */ 3391 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, ESR_EL1 }, 3392 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, IFSR32_EL2 }, 3393 /* ADFSR */ 3394 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, AFSR0_EL1 }, 3395 /* AIFSR */ 3396 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, AFSR1_EL1 }, 3397 /* DFAR */ 3398 { AA32(LO), Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, FAR_EL1 }, 3399 /* IFAR */ 3400 { AA32(HI), Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, FAR_EL1 }, 3401 3402 /* 3403 * DC{C,I,CI}SW operations: 3404 */ 3405 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw }, 3406 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw }, 3407 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw }, 3408 3409 /* PMU */ 3410 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 0), .access = access_pmcr }, 3411 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 1), .access = access_pmcnten }, 3412 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 2), .access = access_pmcnten }, 3413 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 3), .access = access_pmovs }, 3414 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 4), .access = access_pmswinc }, 3415 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 5), .access = access_pmselr }, 3416 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 6), .access = access_pmceid }, 3417 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 7), .access = access_pmceid }, 3418 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 0), .access = access_pmu_evcntr }, 3419 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 1), .access = access_pmu_evtyper }, 3420 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 2), .access = access_pmu_evcntr }, 3421 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 0), .access = access_pmuserenr }, 3422 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 1), .access = access_pminten }, 3423 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 2), .access = access_pminten }, 3424 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 3), .access = access_pmovs }, 3425 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 4), .access = access_pmceid }, 3426 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 5), .access = access_pmceid }, 3427 /* PMMIR */ 3428 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 6), .access = trap_raz_wi }, 3429 3430 /* PRRR/MAIR0 */ 3431 { AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 }, 3432 /* NMRR/MAIR1 */ 3433 { AA32(HI), Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, MAIR_EL1 }, 3434 /* AMAIR0 */ 3435 { AA32(LO), Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, AMAIR_EL1 }, 3436 /* AMAIR1 */ 3437 { AA32(HI), Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, AMAIR_EL1 }, 3438 3439 /* ICC_SRE */ 3440 { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre }, 3441 3442 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, CONTEXTIDR_EL1 }, 3443 3444 /* Arch Tmers */ 3445 { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer }, 3446 { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer }, 3447 3448 /* PMEVCNTRn */ 3449 PMU_PMEVCNTR(0), 3450 PMU_PMEVCNTR(1), 3451 PMU_PMEVCNTR(2), 3452 PMU_PMEVCNTR(3), 3453 PMU_PMEVCNTR(4), 3454 PMU_PMEVCNTR(5), 3455 PMU_PMEVCNTR(6), 3456 PMU_PMEVCNTR(7), 3457 PMU_PMEVCNTR(8), 3458 PMU_PMEVCNTR(9), 3459 PMU_PMEVCNTR(10), 3460 PMU_PMEVCNTR(11), 3461 PMU_PMEVCNTR(12), 3462 PMU_PMEVCNTR(13), 3463 PMU_PMEVCNTR(14), 3464 PMU_PMEVCNTR(15), 3465 PMU_PMEVCNTR(16), 3466 PMU_PMEVCNTR(17), 3467 PMU_PMEVCNTR(18), 3468 PMU_PMEVCNTR(19), 3469 PMU_PMEVCNTR(20), 3470 PMU_PMEVCNTR(21), 3471 PMU_PMEVCNTR(22), 3472 PMU_PMEVCNTR(23), 3473 PMU_PMEVCNTR(24), 3474 PMU_PMEVCNTR(25), 3475 PMU_PMEVCNTR(26), 3476 PMU_PMEVCNTR(27), 3477 PMU_PMEVCNTR(28), 3478 PMU_PMEVCNTR(29), 3479 PMU_PMEVCNTR(30), 3480 /* PMEVTYPERn */ 3481 PMU_PMEVTYPER(0), 3482 PMU_PMEVTYPER(1), 3483 PMU_PMEVTYPER(2), 3484 PMU_PMEVTYPER(3), 3485 PMU_PMEVTYPER(4), 3486 PMU_PMEVTYPER(5), 3487 PMU_PMEVTYPER(6), 3488 PMU_PMEVTYPER(7), 3489 PMU_PMEVTYPER(8), 3490 PMU_PMEVTYPER(9), 3491 PMU_PMEVTYPER(10), 3492 PMU_PMEVTYPER(11), 3493 PMU_PMEVTYPER(12), 3494 PMU_PMEVTYPER(13), 3495 PMU_PMEVTYPER(14), 3496 PMU_PMEVTYPER(15), 3497 PMU_PMEVTYPER(16), 3498 PMU_PMEVTYPER(17), 3499 PMU_PMEVTYPER(18), 3500 PMU_PMEVTYPER(19), 3501 PMU_PMEVTYPER(20), 3502 PMU_PMEVTYPER(21), 3503 PMU_PMEVTYPER(22), 3504 PMU_PMEVTYPER(23), 3505 PMU_PMEVTYPER(24), 3506 PMU_PMEVTYPER(25), 3507 PMU_PMEVTYPER(26), 3508 PMU_PMEVTYPER(27), 3509 PMU_PMEVTYPER(28), 3510 PMU_PMEVTYPER(29), 3511 PMU_PMEVTYPER(30), 3512 /* PMCCFILTR */ 3513 { CP15_PMU_SYS_REG(DIRECT, 0, 14, 15, 7), .access = access_pmu_evtyper }, 3514 3515 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr }, 3516 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr }, 3517 3518 /* CCSIDR2 */ 3519 { Op1(1), CRn( 0), CRm( 0), Op2(2), undef_access }, 3520 3521 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 }, 3522 }; 3523 3524 static const struct sys_reg_desc cp15_64_regs[] = { 3525 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, 3526 { CP15_PMU_SYS_REG(DIRECT, 0, 0, 9, 0), .access = access_pmu_evcntr }, 3527 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */ 3528 { SYS_DESC(SYS_AARCH32_CNTPCT), access_arch_timer }, 3529 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 }, 3530 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */ 3531 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */ 3532 { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer }, 3533 { SYS_DESC(SYS_AARCH32_CNTPCTSS), access_arch_timer }, 3534 }; 3535 3536 static bool check_sysreg_table(const struct sys_reg_desc *table, unsigned int n, 3537 bool is_32) 3538 { 3539 unsigned int i; 3540 3541 for (i = 0; i < n; i++) { 3542 if (!is_32 && table[i].reg && !table[i].reset) { 3543 kvm_err("sys_reg table %pS entry %d (%s) lacks reset\n", 3544 &table[i], i, table[i].name); 3545 return false; 3546 } 3547 3548 if (i && cmp_sys_reg(&table[i-1], &table[i]) >= 0) { 3549 kvm_err("sys_reg table %pS entry %d (%s -> %s) out of order\n", 3550 &table[i], i, table[i - 1].name, table[i].name); 3551 return false; 3552 } 3553 } 3554 3555 return true; 3556 } 3557 3558 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu) 3559 { 3560 kvm_inject_undefined(vcpu); 3561 return 1; 3562 } 3563 3564 static void perform_access(struct kvm_vcpu *vcpu, 3565 struct sys_reg_params *params, 3566 const struct sys_reg_desc *r) 3567 { 3568 trace_kvm_sys_access(*vcpu_pc(vcpu), params, r); 3569 3570 /* Check for regs disabled by runtime config */ 3571 if (sysreg_hidden(vcpu, r)) { 3572 kvm_inject_undefined(vcpu); 3573 return; 3574 } 3575 3576 /* 3577 * Not having an accessor means that we have configured a trap 3578 * that we don't know how to handle. This certainly qualifies 3579 * as a gross bug that should be fixed right away. 3580 */ 3581 BUG_ON(!r->access); 3582 3583 /* Skip instruction if instructed so */ 3584 if (likely(r->access(vcpu, params, r))) 3585 kvm_incr_pc(vcpu); 3586 } 3587 3588 /* 3589 * emulate_cp -- tries to match a sys_reg access in a handling table, and 3590 * call the corresponding trap handler. 3591 * 3592 * @params: pointer to the descriptor of the access 3593 * @table: array of trap descriptors 3594 * @num: size of the trap descriptor array 3595 * 3596 * Return true if the access has been handled, false if not. 3597 */ 3598 static bool emulate_cp(struct kvm_vcpu *vcpu, 3599 struct sys_reg_params *params, 3600 const struct sys_reg_desc *table, 3601 size_t num) 3602 { 3603 const struct sys_reg_desc *r; 3604 3605 if (!table) 3606 return false; /* Not handled */ 3607 3608 r = find_reg(params, table, num); 3609 3610 if (r) { 3611 perform_access(vcpu, params, r); 3612 return true; 3613 } 3614 3615 /* Not handled */ 3616 return false; 3617 } 3618 3619 static void unhandled_cp_access(struct kvm_vcpu *vcpu, 3620 struct sys_reg_params *params) 3621 { 3622 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu); 3623 int cp = -1; 3624 3625 switch (esr_ec) { 3626 case ESR_ELx_EC_CP15_32: 3627 case ESR_ELx_EC_CP15_64: 3628 cp = 15; 3629 break; 3630 case ESR_ELx_EC_CP14_MR: 3631 case ESR_ELx_EC_CP14_64: 3632 cp = 14; 3633 break; 3634 default: 3635 WARN_ON(1); 3636 } 3637 3638 print_sys_reg_msg(params, 3639 "Unsupported guest CP%d access at: %08lx [%08lx]\n", 3640 cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 3641 kvm_inject_undefined(vcpu); 3642 } 3643 3644 /** 3645 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access 3646 * @vcpu: The VCPU pointer 3647 * @global: &struct sys_reg_desc 3648 * @nr_global: size of the @global array 3649 */ 3650 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu, 3651 const struct sys_reg_desc *global, 3652 size_t nr_global) 3653 { 3654 struct sys_reg_params params; 3655 u64 esr = kvm_vcpu_get_esr(vcpu); 3656 int Rt = kvm_vcpu_sys_get_rt(vcpu); 3657 int Rt2 = (esr >> 10) & 0x1f; 3658 3659 params.CRm = (esr >> 1) & 0xf; 3660 params.is_write = ((esr & 1) == 0); 3661 3662 params.Op0 = 0; 3663 params.Op1 = (esr >> 16) & 0xf; 3664 params.Op2 = 0; 3665 params.CRn = 0; 3666 3667 /* 3668 * Make a 64-bit value out of Rt and Rt2. As we use the same trap 3669 * backends between AArch32 and AArch64, we get away with it. 3670 */ 3671 if (params.is_write) { 3672 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff; 3673 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32; 3674 } 3675 3676 /* 3677 * If the table contains a handler, handle the 3678 * potential register operation in the case of a read and return 3679 * with success. 3680 */ 3681 if (emulate_cp(vcpu, ¶ms, global, nr_global)) { 3682 /* Split up the value between registers for the read side */ 3683 if (!params.is_write) { 3684 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval)); 3685 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval)); 3686 } 3687 3688 return 1; 3689 } 3690 3691 unhandled_cp_access(vcpu, ¶ms); 3692 return 1; 3693 } 3694 3695 static bool emulate_sys_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *params); 3696 3697 /* 3698 * The CP10 ID registers are architecturally mapped to AArch64 feature 3699 * registers. Abuse that fact so we can rely on the AArch64 handler for accesses 3700 * from AArch32. 3701 */ 3702 static bool kvm_esr_cp10_id_to_sys64(u64 esr, struct sys_reg_params *params) 3703 { 3704 u8 reg_id = (esr >> 10) & 0xf; 3705 bool valid; 3706 3707 params->is_write = ((esr & 1) == 0); 3708 params->Op0 = 3; 3709 params->Op1 = 0; 3710 params->CRn = 0; 3711 params->CRm = 3; 3712 3713 /* CP10 ID registers are read-only */ 3714 valid = !params->is_write; 3715 3716 switch (reg_id) { 3717 /* MVFR0 */ 3718 case 0b0111: 3719 params->Op2 = 0; 3720 break; 3721 /* MVFR1 */ 3722 case 0b0110: 3723 params->Op2 = 1; 3724 break; 3725 /* MVFR2 */ 3726 case 0b0101: 3727 params->Op2 = 2; 3728 break; 3729 default: 3730 valid = false; 3731 } 3732 3733 if (valid) 3734 return true; 3735 3736 kvm_pr_unimpl("Unhandled cp10 register %s: %u\n", 3737 params->is_write ? "write" : "read", reg_id); 3738 return false; 3739 } 3740 3741 /** 3742 * kvm_handle_cp10_id() - Handles a VMRS trap on guest access to a 'Media and 3743 * VFP Register' from AArch32. 3744 * @vcpu: The vCPU pointer 3745 * 3746 * MVFR{0-2} are architecturally mapped to the AArch64 MVFR{0-2}_EL1 registers. 3747 * Work out the correct AArch64 system register encoding and reroute to the 3748 * AArch64 system register emulation. 3749 */ 3750 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu) 3751 { 3752 int Rt = kvm_vcpu_sys_get_rt(vcpu); 3753 u64 esr = kvm_vcpu_get_esr(vcpu); 3754 struct sys_reg_params params; 3755 3756 /* UNDEF on any unhandled register access */ 3757 if (!kvm_esr_cp10_id_to_sys64(esr, ¶ms)) { 3758 kvm_inject_undefined(vcpu); 3759 return 1; 3760 } 3761 3762 if (emulate_sys_reg(vcpu, ¶ms)) 3763 vcpu_set_reg(vcpu, Rt, params.regval); 3764 3765 return 1; 3766 } 3767 3768 /** 3769 * kvm_emulate_cp15_id_reg() - Handles an MRC trap on a guest CP15 access where 3770 * CRn=0, which corresponds to the AArch32 feature 3771 * registers. 3772 * @vcpu: the vCPU pointer 3773 * @params: the system register access parameters. 3774 * 3775 * Our cp15 system register tables do not enumerate the AArch32 feature 3776 * registers. Conveniently, our AArch64 table does, and the AArch32 system 3777 * register encoding can be trivially remapped into the AArch64 for the feature 3778 * registers: Append op0=3, leaving op1, CRn, CRm, and op2 the same. 3779 * 3780 * According to DDI0487G.b G7.3.1, paragraph "Behavior of VMSAv8-32 32-bit 3781 * System registers with (coproc=0b1111, CRn==c0)", read accesses from this 3782 * range are either UNKNOWN or RES0. Rerouting remains architectural as we 3783 * treat undefined registers in this range as RAZ. 3784 */ 3785 static int kvm_emulate_cp15_id_reg(struct kvm_vcpu *vcpu, 3786 struct sys_reg_params *params) 3787 { 3788 int Rt = kvm_vcpu_sys_get_rt(vcpu); 3789 3790 /* Treat impossible writes to RO registers as UNDEFINED */ 3791 if (params->is_write) { 3792 unhandled_cp_access(vcpu, params); 3793 return 1; 3794 } 3795 3796 params->Op0 = 3; 3797 3798 /* 3799 * All registers where CRm > 3 are known to be UNKNOWN/RAZ from AArch32. 3800 * Avoid conflicting with future expansion of AArch64 feature registers 3801 * and simply treat them as RAZ here. 3802 */ 3803 if (params->CRm > 3) 3804 params->regval = 0; 3805 else if (!emulate_sys_reg(vcpu, params)) 3806 return 1; 3807 3808 vcpu_set_reg(vcpu, Rt, params->regval); 3809 return 1; 3810 } 3811 3812 /** 3813 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access 3814 * @vcpu: The VCPU pointer 3815 * @params: &struct sys_reg_params 3816 * @global: &struct sys_reg_desc 3817 * @nr_global: size of the @global array 3818 */ 3819 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu, 3820 struct sys_reg_params *params, 3821 const struct sys_reg_desc *global, 3822 size_t nr_global) 3823 { 3824 int Rt = kvm_vcpu_sys_get_rt(vcpu); 3825 3826 params->regval = vcpu_get_reg(vcpu, Rt); 3827 3828 if (emulate_cp(vcpu, params, global, nr_global)) { 3829 if (!params->is_write) 3830 vcpu_set_reg(vcpu, Rt, params->regval); 3831 return 1; 3832 } 3833 3834 unhandled_cp_access(vcpu, params); 3835 return 1; 3836 } 3837 3838 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu) 3839 { 3840 return kvm_handle_cp_64(vcpu, cp15_64_regs, ARRAY_SIZE(cp15_64_regs)); 3841 } 3842 3843 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu) 3844 { 3845 struct sys_reg_params params; 3846 3847 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu)); 3848 3849 /* 3850 * Certain AArch32 ID registers are handled by rerouting to the AArch64 3851 * system register table. Registers in the ID range where CRm=0 are 3852 * excluded from this scheme as they do not trivially map into AArch64 3853 * system register encodings. 3854 */ 3855 if (params.Op1 == 0 && params.CRn == 0 && params.CRm) 3856 return kvm_emulate_cp15_id_reg(vcpu, ¶ms); 3857 3858 return kvm_handle_cp_32(vcpu, ¶ms, cp15_regs, ARRAY_SIZE(cp15_regs)); 3859 } 3860 3861 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu) 3862 { 3863 return kvm_handle_cp_64(vcpu, cp14_64_regs, ARRAY_SIZE(cp14_64_regs)); 3864 } 3865 3866 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu) 3867 { 3868 struct sys_reg_params params; 3869 3870 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu)); 3871 3872 return kvm_handle_cp_32(vcpu, ¶ms, cp14_regs, ARRAY_SIZE(cp14_regs)); 3873 } 3874 3875 /** 3876 * emulate_sys_reg - Emulate a guest access to an AArch64 system register 3877 * @vcpu: The VCPU pointer 3878 * @params: Decoded system register parameters 3879 * 3880 * Return: true if the system register access was successful, false otherwise. 3881 */ 3882 static bool emulate_sys_reg(struct kvm_vcpu *vcpu, 3883 struct sys_reg_params *params) 3884 { 3885 const struct sys_reg_desc *r; 3886 3887 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 3888 if (likely(r)) { 3889 perform_access(vcpu, params, r); 3890 return true; 3891 } 3892 3893 print_sys_reg_msg(params, 3894 "Unsupported guest sys_reg access at: %lx [%08lx]\n", 3895 *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 3896 kvm_inject_undefined(vcpu); 3897 3898 return false; 3899 } 3900 3901 static const struct sys_reg_desc *idregs_debug_find(struct kvm *kvm, u8 pos) 3902 { 3903 unsigned long i, idreg_idx = 0; 3904 3905 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { 3906 const struct sys_reg_desc *r = &sys_reg_descs[i]; 3907 3908 if (!is_vm_ftr_id_reg(reg_to_encoding(r))) 3909 continue; 3910 3911 if (idreg_idx == pos) 3912 return r; 3913 3914 idreg_idx++; 3915 } 3916 3917 return NULL; 3918 } 3919 3920 static void *idregs_debug_start(struct seq_file *s, loff_t *pos) 3921 { 3922 struct kvm *kvm = s->private; 3923 u8 *iter; 3924 3925 mutex_lock(&kvm->arch.config_lock); 3926 3927 iter = &kvm->arch.idreg_debugfs_iter; 3928 if (test_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags) && 3929 *iter == (u8)~0) { 3930 *iter = *pos; 3931 if (!idregs_debug_find(kvm, *iter)) 3932 iter = NULL; 3933 } else { 3934 iter = ERR_PTR(-EBUSY); 3935 } 3936 3937 mutex_unlock(&kvm->arch.config_lock); 3938 3939 return iter; 3940 } 3941 3942 static void *idregs_debug_next(struct seq_file *s, void *v, loff_t *pos) 3943 { 3944 struct kvm *kvm = s->private; 3945 3946 (*pos)++; 3947 3948 if (idregs_debug_find(kvm, kvm->arch.idreg_debugfs_iter + 1)) { 3949 kvm->arch.idreg_debugfs_iter++; 3950 3951 return &kvm->arch.idreg_debugfs_iter; 3952 } 3953 3954 return NULL; 3955 } 3956 3957 static void idregs_debug_stop(struct seq_file *s, void *v) 3958 { 3959 struct kvm *kvm = s->private; 3960 3961 if (IS_ERR(v)) 3962 return; 3963 3964 mutex_lock(&kvm->arch.config_lock); 3965 3966 kvm->arch.idreg_debugfs_iter = ~0; 3967 3968 mutex_unlock(&kvm->arch.config_lock); 3969 } 3970 3971 static int idregs_debug_show(struct seq_file *s, void *v) 3972 { 3973 const struct sys_reg_desc *desc; 3974 struct kvm *kvm = s->private; 3975 3976 desc = idregs_debug_find(kvm, kvm->arch.idreg_debugfs_iter); 3977 3978 if (!desc->name) 3979 return 0; 3980 3981 seq_printf(s, "%20s:\t%016llx\n", 3982 desc->name, kvm_read_vm_id_reg(kvm, reg_to_encoding(desc))); 3983 3984 return 0; 3985 } 3986 3987 static const struct seq_operations idregs_debug_sops = { 3988 .start = idregs_debug_start, 3989 .next = idregs_debug_next, 3990 .stop = idregs_debug_stop, 3991 .show = idregs_debug_show, 3992 }; 3993 3994 DEFINE_SEQ_ATTRIBUTE(idregs_debug); 3995 3996 void kvm_sys_regs_create_debugfs(struct kvm *kvm) 3997 { 3998 kvm->arch.idreg_debugfs_iter = ~0; 3999 4000 debugfs_create_file("idregs", 0444, kvm->debugfs_dentry, kvm, 4001 &idregs_debug_fops); 4002 } 4003 4004 static void reset_vm_ftr_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *reg) 4005 { 4006 u32 id = reg_to_encoding(reg); 4007 struct kvm *kvm = vcpu->kvm; 4008 4009 if (test_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags)) 4010 return; 4011 4012 kvm_set_vm_id_reg(kvm, id, reg->reset(vcpu, reg)); 4013 } 4014 4015 static void reset_vcpu_ftr_id_reg(struct kvm_vcpu *vcpu, 4016 const struct sys_reg_desc *reg) 4017 { 4018 if (kvm_vcpu_initialized(vcpu)) 4019 return; 4020 4021 reg->reset(vcpu, reg); 4022 } 4023 4024 /** 4025 * kvm_reset_sys_regs - sets system registers to reset value 4026 * @vcpu: The VCPU pointer 4027 * 4028 * This function finds the right table above and sets the registers on the 4029 * virtual CPU struct to their architecturally defined reset values. 4030 */ 4031 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu) 4032 { 4033 struct kvm *kvm = vcpu->kvm; 4034 unsigned long i; 4035 4036 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { 4037 const struct sys_reg_desc *r = &sys_reg_descs[i]; 4038 4039 if (!r->reset) 4040 continue; 4041 4042 if (is_vm_ftr_id_reg(reg_to_encoding(r))) 4043 reset_vm_ftr_id_reg(vcpu, r); 4044 else if (is_vcpu_ftr_id_reg(reg_to_encoding(r))) 4045 reset_vcpu_ftr_id_reg(vcpu, r); 4046 else 4047 r->reset(vcpu, r); 4048 } 4049 4050 set_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags); 4051 } 4052 4053 /** 4054 * kvm_handle_sys_reg -- handles a system instruction or mrs/msr instruction 4055 * trap on a guest execution 4056 * @vcpu: The VCPU pointer 4057 */ 4058 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu) 4059 { 4060 const struct sys_reg_desc *desc = NULL; 4061 struct sys_reg_params params; 4062 unsigned long esr = kvm_vcpu_get_esr(vcpu); 4063 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4064 int sr_idx; 4065 4066 trace_kvm_handle_sys_reg(esr); 4067 4068 if (triage_sysreg_trap(vcpu, &sr_idx)) 4069 return 1; 4070 4071 params = esr_sys64_to_params(esr); 4072 params.regval = vcpu_get_reg(vcpu, Rt); 4073 4074 /* System registers have Op0=={2,3}, as per DDI487 J.a C5.1.2 */ 4075 if (params.Op0 == 2 || params.Op0 == 3) 4076 desc = &sys_reg_descs[sr_idx]; 4077 else 4078 desc = &sys_insn_descs[sr_idx]; 4079 4080 perform_access(vcpu, ¶ms, desc); 4081 4082 /* Read from system register? */ 4083 if (!params.is_write && 4084 (params.Op0 == 2 || params.Op0 == 3)) 4085 vcpu_set_reg(vcpu, Rt, params.regval); 4086 4087 return 1; 4088 } 4089 4090 /****************************************************************************** 4091 * Userspace API 4092 *****************************************************************************/ 4093 4094 static bool index_to_params(u64 id, struct sys_reg_params *params) 4095 { 4096 switch (id & KVM_REG_SIZE_MASK) { 4097 case KVM_REG_SIZE_U64: 4098 /* Any unused index bits means it's not valid. */ 4099 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK 4100 | KVM_REG_ARM_COPROC_MASK 4101 | KVM_REG_ARM64_SYSREG_OP0_MASK 4102 | KVM_REG_ARM64_SYSREG_OP1_MASK 4103 | KVM_REG_ARM64_SYSREG_CRN_MASK 4104 | KVM_REG_ARM64_SYSREG_CRM_MASK 4105 | KVM_REG_ARM64_SYSREG_OP2_MASK)) 4106 return false; 4107 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK) 4108 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT); 4109 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK) 4110 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT); 4111 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK) 4112 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT); 4113 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK) 4114 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT); 4115 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK) 4116 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT); 4117 return true; 4118 default: 4119 return false; 4120 } 4121 } 4122 4123 const struct sys_reg_desc *get_reg_by_id(u64 id, 4124 const struct sys_reg_desc table[], 4125 unsigned int num) 4126 { 4127 struct sys_reg_params params; 4128 4129 if (!index_to_params(id, ¶ms)) 4130 return NULL; 4131 4132 return find_reg(¶ms, table, num); 4133 } 4134 4135 /* Decode an index value, and find the sys_reg_desc entry. */ 4136 static const struct sys_reg_desc * 4137 id_to_sys_reg_desc(struct kvm_vcpu *vcpu, u64 id, 4138 const struct sys_reg_desc table[], unsigned int num) 4139 4140 { 4141 const struct sys_reg_desc *r; 4142 4143 /* We only do sys_reg for now. */ 4144 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG) 4145 return NULL; 4146 4147 r = get_reg_by_id(id, table, num); 4148 4149 /* Not saved in the sys_reg array and not otherwise accessible? */ 4150 if (r && (!(r->reg || r->get_user) || sysreg_hidden(vcpu, r))) 4151 r = NULL; 4152 4153 return r; 4154 } 4155 4156 /* 4157 * These are the invariant sys_reg registers: we let the guest see the 4158 * host versions of these, so they're part of the guest state. 4159 * 4160 * A future CPU may provide a mechanism to present different values to 4161 * the guest, or a future kvm may trap them. 4162 */ 4163 4164 #define FUNCTION_INVARIANT(reg) \ 4165 static u64 reset_##reg(struct kvm_vcpu *v, \ 4166 const struct sys_reg_desc *r) \ 4167 { \ 4168 ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \ 4169 return ((struct sys_reg_desc *)r)->val; \ 4170 } 4171 4172 FUNCTION_INVARIANT(midr_el1) 4173 FUNCTION_INVARIANT(revidr_el1) 4174 FUNCTION_INVARIANT(aidr_el1) 4175 4176 /* ->val is filled in by kvm_sys_reg_table_init() */ 4177 static struct sys_reg_desc invariant_sys_regs[] __ro_after_init = { 4178 { SYS_DESC(SYS_MIDR_EL1), NULL, reset_midr_el1 }, 4179 { SYS_DESC(SYS_REVIDR_EL1), NULL, reset_revidr_el1 }, 4180 { SYS_DESC(SYS_AIDR_EL1), NULL, reset_aidr_el1 }, 4181 }; 4182 4183 static int get_invariant_sys_reg(u64 id, u64 __user *uaddr) 4184 { 4185 const struct sys_reg_desc *r; 4186 4187 r = get_reg_by_id(id, invariant_sys_regs, 4188 ARRAY_SIZE(invariant_sys_regs)); 4189 if (!r) 4190 return -ENOENT; 4191 4192 return put_user(r->val, uaddr); 4193 } 4194 4195 static int set_invariant_sys_reg(u64 id, u64 __user *uaddr) 4196 { 4197 const struct sys_reg_desc *r; 4198 u64 val; 4199 4200 r = get_reg_by_id(id, invariant_sys_regs, 4201 ARRAY_SIZE(invariant_sys_regs)); 4202 if (!r) 4203 return -ENOENT; 4204 4205 if (get_user(val, uaddr)) 4206 return -EFAULT; 4207 4208 /* This is what we mean by invariant: you can't change it. */ 4209 if (r->val != val) 4210 return -EINVAL; 4211 4212 return 0; 4213 } 4214 4215 static int demux_c15_get(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) 4216 { 4217 u32 val; 4218 u32 __user *uval = uaddr; 4219 4220 /* Fail if we have unknown bits set. */ 4221 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 4222 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 4223 return -ENOENT; 4224 4225 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 4226 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 4227 if (KVM_REG_SIZE(id) != 4) 4228 return -ENOENT; 4229 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 4230 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 4231 if (val >= CSSELR_MAX) 4232 return -ENOENT; 4233 4234 return put_user(get_ccsidr(vcpu, val), uval); 4235 default: 4236 return -ENOENT; 4237 } 4238 } 4239 4240 static int demux_c15_set(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) 4241 { 4242 u32 val, newval; 4243 u32 __user *uval = uaddr; 4244 4245 /* Fail if we have unknown bits set. */ 4246 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 4247 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 4248 return -ENOENT; 4249 4250 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 4251 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 4252 if (KVM_REG_SIZE(id) != 4) 4253 return -ENOENT; 4254 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 4255 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 4256 if (val >= CSSELR_MAX) 4257 return -ENOENT; 4258 4259 if (get_user(newval, uval)) 4260 return -EFAULT; 4261 4262 return set_ccsidr(vcpu, val, newval); 4263 default: 4264 return -ENOENT; 4265 } 4266 } 4267 4268 int kvm_sys_reg_get_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg, 4269 const struct sys_reg_desc table[], unsigned int num) 4270 { 4271 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr; 4272 const struct sys_reg_desc *r; 4273 u64 val; 4274 int ret; 4275 4276 r = id_to_sys_reg_desc(vcpu, reg->id, table, num); 4277 if (!r || sysreg_hidden_user(vcpu, r)) 4278 return -ENOENT; 4279 4280 if (r->get_user) { 4281 ret = (r->get_user)(vcpu, r, &val); 4282 } else { 4283 val = __vcpu_sys_reg(vcpu, r->reg); 4284 ret = 0; 4285 } 4286 4287 if (!ret) 4288 ret = put_user(val, uaddr); 4289 4290 return ret; 4291 } 4292 4293 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 4294 { 4295 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 4296 int err; 4297 4298 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 4299 return demux_c15_get(vcpu, reg->id, uaddr); 4300 4301 err = get_invariant_sys_reg(reg->id, uaddr); 4302 if (err != -ENOENT) 4303 return err; 4304 4305 return kvm_sys_reg_get_user(vcpu, reg, 4306 sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 4307 } 4308 4309 int kvm_sys_reg_set_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg, 4310 const struct sys_reg_desc table[], unsigned int num) 4311 { 4312 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr; 4313 const struct sys_reg_desc *r; 4314 u64 val; 4315 int ret; 4316 4317 if (get_user(val, uaddr)) 4318 return -EFAULT; 4319 4320 r = id_to_sys_reg_desc(vcpu, reg->id, table, num); 4321 if (!r || sysreg_hidden_user(vcpu, r)) 4322 return -ENOENT; 4323 4324 if (sysreg_user_write_ignore(vcpu, r)) 4325 return 0; 4326 4327 if (r->set_user) { 4328 ret = (r->set_user)(vcpu, r, val); 4329 } else { 4330 __vcpu_sys_reg(vcpu, r->reg) = val; 4331 ret = 0; 4332 } 4333 4334 return ret; 4335 } 4336 4337 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 4338 { 4339 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 4340 int err; 4341 4342 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 4343 return demux_c15_set(vcpu, reg->id, uaddr); 4344 4345 err = set_invariant_sys_reg(reg->id, uaddr); 4346 if (err != -ENOENT) 4347 return err; 4348 4349 return kvm_sys_reg_set_user(vcpu, reg, 4350 sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 4351 } 4352 4353 static unsigned int num_demux_regs(void) 4354 { 4355 return CSSELR_MAX; 4356 } 4357 4358 static int write_demux_regids(u64 __user *uindices) 4359 { 4360 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX; 4361 unsigned int i; 4362 4363 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR; 4364 for (i = 0; i < CSSELR_MAX; i++) { 4365 if (put_user(val | i, uindices)) 4366 return -EFAULT; 4367 uindices++; 4368 } 4369 return 0; 4370 } 4371 4372 static u64 sys_reg_to_index(const struct sys_reg_desc *reg) 4373 { 4374 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | 4375 KVM_REG_ARM64_SYSREG | 4376 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) | 4377 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) | 4378 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) | 4379 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) | 4380 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT)); 4381 } 4382 4383 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind) 4384 { 4385 if (!*uind) 4386 return true; 4387 4388 if (put_user(sys_reg_to_index(reg), *uind)) 4389 return false; 4390 4391 (*uind)++; 4392 return true; 4393 } 4394 4395 static int walk_one_sys_reg(const struct kvm_vcpu *vcpu, 4396 const struct sys_reg_desc *rd, 4397 u64 __user **uind, 4398 unsigned int *total) 4399 { 4400 /* 4401 * Ignore registers we trap but don't save, 4402 * and for which no custom user accessor is provided. 4403 */ 4404 if (!(rd->reg || rd->get_user)) 4405 return 0; 4406 4407 if (sysreg_hidden_user(vcpu, rd)) 4408 return 0; 4409 4410 if (!copy_reg_to_user(rd, uind)) 4411 return -EFAULT; 4412 4413 (*total)++; 4414 return 0; 4415 } 4416 4417 /* Assumed ordered tables, see kvm_sys_reg_table_init. */ 4418 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind) 4419 { 4420 const struct sys_reg_desc *i2, *end2; 4421 unsigned int total = 0; 4422 int err; 4423 4424 i2 = sys_reg_descs; 4425 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs); 4426 4427 while (i2 != end2) { 4428 err = walk_one_sys_reg(vcpu, i2++, &uind, &total); 4429 if (err) 4430 return err; 4431 } 4432 return total; 4433 } 4434 4435 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu) 4436 { 4437 return ARRAY_SIZE(invariant_sys_regs) 4438 + num_demux_regs() 4439 + walk_sys_regs(vcpu, (u64 __user *)NULL); 4440 } 4441 4442 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) 4443 { 4444 unsigned int i; 4445 int err; 4446 4447 /* Then give them all the invariant registers' indices. */ 4448 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) { 4449 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices)) 4450 return -EFAULT; 4451 uindices++; 4452 } 4453 4454 err = walk_sys_regs(vcpu, uindices); 4455 if (err < 0) 4456 return err; 4457 uindices += err; 4458 4459 return write_demux_regids(uindices); 4460 } 4461 4462 #define KVM_ARM_FEATURE_ID_RANGE_INDEX(r) \ 4463 KVM_ARM_FEATURE_ID_RANGE_IDX(sys_reg_Op0(r), \ 4464 sys_reg_Op1(r), \ 4465 sys_reg_CRn(r), \ 4466 sys_reg_CRm(r), \ 4467 sys_reg_Op2(r)) 4468 4469 int kvm_vm_ioctl_get_reg_writable_masks(struct kvm *kvm, struct reg_mask_range *range) 4470 { 4471 const void *zero_page = page_to_virt(ZERO_PAGE(0)); 4472 u64 __user *masks = (u64 __user *)range->addr; 4473 4474 /* Only feature id range is supported, reserved[13] must be zero. */ 4475 if (range->range || 4476 memcmp(range->reserved, zero_page, sizeof(range->reserved))) 4477 return -EINVAL; 4478 4479 /* Wipe the whole thing first */ 4480 if (clear_user(masks, KVM_ARM_FEATURE_ID_RANGE_SIZE * sizeof(__u64))) 4481 return -EFAULT; 4482 4483 for (int i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { 4484 const struct sys_reg_desc *reg = &sys_reg_descs[i]; 4485 u32 encoding = reg_to_encoding(reg); 4486 u64 val; 4487 4488 if (!is_feature_id_reg(encoding) || !reg->set_user) 4489 continue; 4490 4491 if (!reg->val || 4492 (is_aa32_id_reg(encoding) && !kvm_supports_32bit_el0())) { 4493 continue; 4494 } 4495 val = reg->val; 4496 4497 if (put_user(val, (masks + KVM_ARM_FEATURE_ID_RANGE_INDEX(encoding)))) 4498 return -EFAULT; 4499 } 4500 4501 return 0; 4502 } 4503 4504 static void vcpu_set_hcr(struct kvm_vcpu *vcpu) 4505 { 4506 struct kvm *kvm = vcpu->kvm; 4507 4508 if (has_vhe() || has_hvhe()) 4509 vcpu->arch.hcr_el2 |= HCR_E2H; 4510 if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN)) { 4511 /* route synchronous external abort exceptions to EL2 */ 4512 vcpu->arch.hcr_el2 |= HCR_TEA; 4513 /* trap error record accesses */ 4514 vcpu->arch.hcr_el2 |= HCR_TERR; 4515 } 4516 4517 if (cpus_have_final_cap(ARM64_HAS_STAGE2_FWB)) 4518 vcpu->arch.hcr_el2 |= HCR_FWB; 4519 4520 if (cpus_have_final_cap(ARM64_HAS_EVT) && 4521 !cpus_have_final_cap(ARM64_MISMATCHED_CACHE_TYPE) && 4522 kvm_read_vm_id_reg(kvm, SYS_CTR_EL0) == read_sanitised_ftr_reg(SYS_CTR_EL0)) 4523 vcpu->arch.hcr_el2 |= HCR_TID4; 4524 else 4525 vcpu->arch.hcr_el2 |= HCR_TID2; 4526 4527 if (vcpu_el1_is_32bit(vcpu)) 4528 vcpu->arch.hcr_el2 &= ~HCR_RW; 4529 4530 if (kvm_has_mte(vcpu->kvm)) 4531 vcpu->arch.hcr_el2 |= HCR_ATA; 4532 4533 /* 4534 * In the absence of FGT, we cannot independently trap TLBI 4535 * Range instructions. This isn't great, but trapping all 4536 * TLBIs would be far worse. Live with it... 4537 */ 4538 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 4539 vcpu->arch.hcr_el2 |= HCR_TTLBOS; 4540 } 4541 4542 void kvm_calculate_traps(struct kvm_vcpu *vcpu) 4543 { 4544 struct kvm *kvm = vcpu->kvm; 4545 4546 mutex_lock(&kvm->arch.config_lock); 4547 vcpu_set_hcr(vcpu); 4548 4549 if (cpus_have_final_cap(ARM64_HAS_HCX)) { 4550 /* 4551 * In general, all HCRX_EL2 bits are gated by a feature. 4552 * The only reason we can set SMPME without checking any 4553 * feature is that its effects are not directly observable 4554 * from the guest. 4555 */ 4556 vcpu->arch.hcrx_el2 = HCRX_EL2_SMPME; 4557 4558 if (kvm_has_feat(kvm, ID_AA64ISAR2_EL1, MOPS, IMP)) 4559 vcpu->arch.hcrx_el2 |= (HCRX_EL2_MSCEn | HCRX_EL2_MCE2); 4560 4561 if (kvm_has_feat(kvm, ID_AA64MMFR3_EL1, TCRX, IMP)) 4562 vcpu->arch.hcrx_el2 |= HCRX_EL2_TCR2En; 4563 } 4564 4565 if (test_bit(KVM_ARCH_FLAG_FGU_INITIALIZED, &kvm->arch.flags)) 4566 goto out; 4567 4568 kvm->arch.fgu[HFGxTR_GROUP] = (HFGxTR_EL2_nAMAIR2_EL1 | 4569 HFGxTR_EL2_nMAIR2_EL1 | 4570 HFGxTR_EL2_nS2POR_EL1 | 4571 HFGxTR_EL2_nPOR_EL1 | 4572 HFGxTR_EL2_nPOR_EL0 | 4573 HFGxTR_EL2_nACCDATA_EL1 | 4574 HFGxTR_EL2_nSMPRI_EL1_MASK | 4575 HFGxTR_EL2_nTPIDR2_EL0_MASK); 4576 4577 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 4578 kvm->arch.fgu[HFGITR_GROUP] |= (HFGITR_EL2_TLBIRVAALE1OS| 4579 HFGITR_EL2_TLBIRVALE1OS | 4580 HFGITR_EL2_TLBIRVAAE1OS | 4581 HFGITR_EL2_TLBIRVAE1OS | 4582 HFGITR_EL2_TLBIVAALE1OS | 4583 HFGITR_EL2_TLBIVALE1OS | 4584 HFGITR_EL2_TLBIVAAE1OS | 4585 HFGITR_EL2_TLBIASIDE1OS | 4586 HFGITR_EL2_TLBIVAE1OS | 4587 HFGITR_EL2_TLBIVMALLE1OS); 4588 4589 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE)) 4590 kvm->arch.fgu[HFGITR_GROUP] |= (HFGITR_EL2_TLBIRVAALE1 | 4591 HFGITR_EL2_TLBIRVALE1 | 4592 HFGITR_EL2_TLBIRVAAE1 | 4593 HFGITR_EL2_TLBIRVAE1 | 4594 HFGITR_EL2_TLBIRVAALE1IS| 4595 HFGITR_EL2_TLBIRVALE1IS | 4596 HFGITR_EL2_TLBIRVAAE1IS | 4597 HFGITR_EL2_TLBIRVAE1IS | 4598 HFGITR_EL2_TLBIRVAALE1OS| 4599 HFGITR_EL2_TLBIRVALE1OS | 4600 HFGITR_EL2_TLBIRVAAE1OS | 4601 HFGITR_EL2_TLBIRVAE1OS); 4602 4603 if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, S1PIE, IMP)) 4604 kvm->arch.fgu[HFGxTR_GROUP] |= (HFGxTR_EL2_nPIRE0_EL1 | 4605 HFGxTR_EL2_nPIR_EL1); 4606 4607 if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, AMU, IMP)) 4608 kvm->arch.fgu[HAFGRTR_GROUP] |= ~(HAFGRTR_EL2_RES0 | 4609 HAFGRTR_EL2_RES1); 4610 4611 set_bit(KVM_ARCH_FLAG_FGU_INITIALIZED, &kvm->arch.flags); 4612 out: 4613 mutex_unlock(&kvm->arch.config_lock); 4614 } 4615 4616 int __init kvm_sys_reg_table_init(void) 4617 { 4618 bool valid = true; 4619 unsigned int i; 4620 int ret = 0; 4621 4622 /* Make sure tables are unique and in order. */ 4623 valid &= check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), false); 4624 valid &= check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), true); 4625 valid &= check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), true); 4626 valid &= check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), true); 4627 valid &= check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), true); 4628 valid &= check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs), false); 4629 valid &= check_sysreg_table(sys_insn_descs, ARRAY_SIZE(sys_insn_descs), false); 4630 4631 if (!valid) 4632 return -EINVAL; 4633 4634 /* We abuse the reset function to overwrite the table itself. */ 4635 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) 4636 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]); 4637 4638 ret = populate_nv_trap_config(); 4639 4640 for (i = 0; !ret && i < ARRAY_SIZE(sys_reg_descs); i++) 4641 ret = populate_sysreg_config(sys_reg_descs + i, i); 4642 4643 for (i = 0; !ret && i < ARRAY_SIZE(sys_insn_descs); i++) 4644 ret = populate_sysreg_config(sys_insn_descs + i, i); 4645 4646 return ret; 4647 } 4648