1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/kvm/coproc.c: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Authors: Rusty Russell <rusty@rustcorp.com.au> 9 * Christoffer Dall <c.dall@virtualopensystems.com> 10 */ 11 12 #include <linux/bsearch.h> 13 #include <linux/kvm_host.h> 14 #include <linux/mm.h> 15 #include <linux/printk.h> 16 #include <linux/uaccess.h> 17 18 #include <asm/cacheflush.h> 19 #include <asm/cputype.h> 20 #include <asm/debug-monitors.h> 21 #include <asm/esr.h> 22 #include <asm/kvm_arm.h> 23 #include <asm/kvm_coproc.h> 24 #include <asm/kvm_emulate.h> 25 #include <asm/kvm_hyp.h> 26 #include <asm/kvm_mmu.h> 27 #include <asm/perf_event.h> 28 #include <asm/sysreg.h> 29 30 #include <trace/events/kvm.h> 31 32 #include "sys_regs.h" 33 34 #include "trace.h" 35 36 /* 37 * All of this file is extremly similar to the ARM coproc.c, but the 38 * types are different. My gut feeling is that it should be pretty 39 * easy to merge, but that would be an ABI breakage -- again. VFP 40 * would also need to be abstracted. 41 * 42 * For AArch32, we only take care of what is being trapped. Anything 43 * that has to do with init and userspace access has to go via the 44 * 64bit interface. 45 */ 46 47 static bool read_from_write_only(struct kvm_vcpu *vcpu, 48 struct sys_reg_params *params, 49 const struct sys_reg_desc *r) 50 { 51 WARN_ONCE(1, "Unexpected sys_reg read to write-only register\n"); 52 print_sys_reg_instr(params); 53 kvm_inject_undefined(vcpu); 54 return false; 55 } 56 57 static bool write_to_read_only(struct kvm_vcpu *vcpu, 58 struct sys_reg_params *params, 59 const struct sys_reg_desc *r) 60 { 61 WARN_ONCE(1, "Unexpected sys_reg write to read-only register\n"); 62 print_sys_reg_instr(params); 63 kvm_inject_undefined(vcpu); 64 return false; 65 } 66 67 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg) 68 { 69 if (!vcpu->arch.sysregs_loaded_on_cpu) 70 goto immediate_read; 71 72 /* 73 * System registers listed in the switch are not saved on every 74 * exit from the guest but are only saved on vcpu_put. 75 * 76 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but 77 * should never be listed below, because the guest cannot modify its 78 * own MPIDR_EL1 and MPIDR_EL1 is accessed for VCPU A from VCPU B's 79 * thread when emulating cross-VCPU communication. 80 */ 81 switch (reg) { 82 case CSSELR_EL1: return read_sysreg_s(SYS_CSSELR_EL1); 83 case SCTLR_EL1: return read_sysreg_s(SYS_SCTLR_EL12); 84 case ACTLR_EL1: return read_sysreg_s(SYS_ACTLR_EL1); 85 case CPACR_EL1: return read_sysreg_s(SYS_CPACR_EL12); 86 case TTBR0_EL1: return read_sysreg_s(SYS_TTBR0_EL12); 87 case TTBR1_EL1: return read_sysreg_s(SYS_TTBR1_EL12); 88 case TCR_EL1: return read_sysreg_s(SYS_TCR_EL12); 89 case ESR_EL1: return read_sysreg_s(SYS_ESR_EL12); 90 case AFSR0_EL1: return read_sysreg_s(SYS_AFSR0_EL12); 91 case AFSR1_EL1: return read_sysreg_s(SYS_AFSR1_EL12); 92 case FAR_EL1: return read_sysreg_s(SYS_FAR_EL12); 93 case MAIR_EL1: return read_sysreg_s(SYS_MAIR_EL12); 94 case VBAR_EL1: return read_sysreg_s(SYS_VBAR_EL12); 95 case CONTEXTIDR_EL1: return read_sysreg_s(SYS_CONTEXTIDR_EL12); 96 case TPIDR_EL0: return read_sysreg_s(SYS_TPIDR_EL0); 97 case TPIDRRO_EL0: return read_sysreg_s(SYS_TPIDRRO_EL0); 98 case TPIDR_EL1: return read_sysreg_s(SYS_TPIDR_EL1); 99 case AMAIR_EL1: return read_sysreg_s(SYS_AMAIR_EL12); 100 case CNTKCTL_EL1: return read_sysreg_s(SYS_CNTKCTL_EL12); 101 case PAR_EL1: return read_sysreg_s(SYS_PAR_EL1); 102 case DACR32_EL2: return read_sysreg_s(SYS_DACR32_EL2); 103 case IFSR32_EL2: return read_sysreg_s(SYS_IFSR32_EL2); 104 case DBGVCR32_EL2: return read_sysreg_s(SYS_DBGVCR32_EL2); 105 } 106 107 immediate_read: 108 return __vcpu_sys_reg(vcpu, reg); 109 } 110 111 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg) 112 { 113 if (!vcpu->arch.sysregs_loaded_on_cpu) 114 goto immediate_write; 115 116 /* 117 * System registers listed in the switch are not restored on every 118 * entry to the guest but are only restored on vcpu_load. 119 * 120 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but 121 * should never be listed below, because the the MPIDR should only be 122 * set once, before running the VCPU, and never changed later. 123 */ 124 switch (reg) { 125 case CSSELR_EL1: write_sysreg_s(val, SYS_CSSELR_EL1); return; 126 case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); return; 127 case ACTLR_EL1: write_sysreg_s(val, SYS_ACTLR_EL1); return; 128 case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); return; 129 case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); return; 130 case TTBR1_EL1: write_sysreg_s(val, SYS_TTBR1_EL12); return; 131 case TCR_EL1: write_sysreg_s(val, SYS_TCR_EL12); return; 132 case ESR_EL1: write_sysreg_s(val, SYS_ESR_EL12); return; 133 case AFSR0_EL1: write_sysreg_s(val, SYS_AFSR0_EL12); return; 134 case AFSR1_EL1: write_sysreg_s(val, SYS_AFSR1_EL12); return; 135 case FAR_EL1: write_sysreg_s(val, SYS_FAR_EL12); return; 136 case MAIR_EL1: write_sysreg_s(val, SYS_MAIR_EL12); return; 137 case VBAR_EL1: write_sysreg_s(val, SYS_VBAR_EL12); return; 138 case CONTEXTIDR_EL1: write_sysreg_s(val, SYS_CONTEXTIDR_EL12); return; 139 case TPIDR_EL0: write_sysreg_s(val, SYS_TPIDR_EL0); return; 140 case TPIDRRO_EL0: write_sysreg_s(val, SYS_TPIDRRO_EL0); return; 141 case TPIDR_EL1: write_sysreg_s(val, SYS_TPIDR_EL1); return; 142 case AMAIR_EL1: write_sysreg_s(val, SYS_AMAIR_EL12); return; 143 case CNTKCTL_EL1: write_sysreg_s(val, SYS_CNTKCTL_EL12); return; 144 case PAR_EL1: write_sysreg_s(val, SYS_PAR_EL1); return; 145 case DACR32_EL2: write_sysreg_s(val, SYS_DACR32_EL2); return; 146 case IFSR32_EL2: write_sysreg_s(val, SYS_IFSR32_EL2); return; 147 case DBGVCR32_EL2: write_sysreg_s(val, SYS_DBGVCR32_EL2); return; 148 } 149 150 immediate_write: 151 __vcpu_sys_reg(vcpu, reg) = val; 152 } 153 154 /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */ 155 static u32 cache_levels; 156 157 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */ 158 #define CSSELR_MAX 12 159 160 /* Which cache CCSIDR represents depends on CSSELR value. */ 161 static u32 get_ccsidr(u32 csselr) 162 { 163 u32 ccsidr; 164 165 /* Make sure noone else changes CSSELR during this! */ 166 local_irq_disable(); 167 write_sysreg(csselr, csselr_el1); 168 isb(); 169 ccsidr = read_sysreg(ccsidr_el1); 170 local_irq_enable(); 171 172 return ccsidr; 173 } 174 175 /* 176 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized). 177 */ 178 static bool access_dcsw(struct kvm_vcpu *vcpu, 179 struct sys_reg_params *p, 180 const struct sys_reg_desc *r) 181 { 182 if (!p->is_write) 183 return read_from_write_only(vcpu, p, r); 184 185 /* 186 * Only track S/W ops if we don't have FWB. It still indicates 187 * that the guest is a bit broken (S/W operations should only 188 * be done by firmware, knowing that there is only a single 189 * CPU left in the system, and certainly not from non-secure 190 * software). 191 */ 192 if (!cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) 193 kvm_set_way_flush(vcpu); 194 195 return true; 196 } 197 198 /* 199 * Generic accessor for VM registers. Only called as long as HCR_TVM 200 * is set. If the guest enables the MMU, we stop trapping the VM 201 * sys_regs and leave it in complete control of the caches. 202 */ 203 static bool access_vm_reg(struct kvm_vcpu *vcpu, 204 struct sys_reg_params *p, 205 const struct sys_reg_desc *r) 206 { 207 bool was_enabled = vcpu_has_cache_enabled(vcpu); 208 u64 val; 209 int reg = r->reg; 210 211 BUG_ON(!p->is_write); 212 213 /* See the 32bit mapping in kvm_host.h */ 214 if (p->is_aarch32) 215 reg = r->reg / 2; 216 217 if (!p->is_aarch32 || !p->is_32bit) { 218 val = p->regval; 219 } else { 220 val = vcpu_read_sys_reg(vcpu, reg); 221 if (r->reg % 2) 222 val = (p->regval << 32) | (u64)lower_32_bits(val); 223 else 224 val = ((u64)upper_32_bits(val) << 32) | 225 lower_32_bits(p->regval); 226 } 227 vcpu_write_sys_reg(vcpu, val, reg); 228 229 kvm_toggle_cache(vcpu, was_enabled); 230 return true; 231 } 232 233 /* 234 * Trap handler for the GICv3 SGI generation system register. 235 * Forward the request to the VGIC emulation. 236 * The cp15_64 code makes sure this automatically works 237 * for both AArch64 and AArch32 accesses. 238 */ 239 static bool access_gic_sgi(struct kvm_vcpu *vcpu, 240 struct sys_reg_params *p, 241 const struct sys_reg_desc *r) 242 { 243 bool g1; 244 245 if (!p->is_write) 246 return read_from_write_only(vcpu, p, r); 247 248 /* 249 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates 250 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group, 251 * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively 252 * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure 253 * group. 254 */ 255 if (p->is_aarch32) { 256 switch (p->Op1) { 257 default: /* Keep GCC quiet */ 258 case 0: /* ICC_SGI1R */ 259 g1 = true; 260 break; 261 case 1: /* ICC_ASGI1R */ 262 case 2: /* ICC_SGI0R */ 263 g1 = false; 264 break; 265 } 266 } else { 267 switch (p->Op2) { 268 default: /* Keep GCC quiet */ 269 case 5: /* ICC_SGI1R_EL1 */ 270 g1 = true; 271 break; 272 case 6: /* ICC_ASGI1R_EL1 */ 273 case 7: /* ICC_SGI0R_EL1 */ 274 g1 = false; 275 break; 276 } 277 } 278 279 vgic_v3_dispatch_sgi(vcpu, p->regval, g1); 280 281 return true; 282 } 283 284 static bool access_gic_sre(struct kvm_vcpu *vcpu, 285 struct sys_reg_params *p, 286 const struct sys_reg_desc *r) 287 { 288 if (p->is_write) 289 return ignore_write(vcpu, p); 290 291 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre; 292 return true; 293 } 294 295 static bool trap_raz_wi(struct kvm_vcpu *vcpu, 296 struct sys_reg_params *p, 297 const struct sys_reg_desc *r) 298 { 299 if (p->is_write) 300 return ignore_write(vcpu, p); 301 else 302 return read_zero(vcpu, p); 303 } 304 305 /* 306 * ARMv8.1 mandates at least a trivial LORegion implementation, where all the 307 * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0 308 * system, these registers should UNDEF. LORID_EL1 being a RO register, we 309 * treat it separately. 310 */ 311 static bool trap_loregion(struct kvm_vcpu *vcpu, 312 struct sys_reg_params *p, 313 const struct sys_reg_desc *r) 314 { 315 u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 316 u32 sr = sys_reg((u32)r->Op0, (u32)r->Op1, 317 (u32)r->CRn, (u32)r->CRm, (u32)r->Op2); 318 319 if (!(val & (0xfUL << ID_AA64MMFR1_LOR_SHIFT))) { 320 kvm_inject_undefined(vcpu); 321 return false; 322 } 323 324 if (p->is_write && sr == SYS_LORID_EL1) 325 return write_to_read_only(vcpu, p, r); 326 327 return trap_raz_wi(vcpu, p, r); 328 } 329 330 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu, 331 struct sys_reg_params *p, 332 const struct sys_reg_desc *r) 333 { 334 if (p->is_write) { 335 return ignore_write(vcpu, p); 336 } else { 337 p->regval = (1 << 3); 338 return true; 339 } 340 } 341 342 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu, 343 struct sys_reg_params *p, 344 const struct sys_reg_desc *r) 345 { 346 if (p->is_write) { 347 return ignore_write(vcpu, p); 348 } else { 349 p->regval = read_sysreg(dbgauthstatus_el1); 350 return true; 351 } 352 } 353 354 /* 355 * We want to avoid world-switching all the DBG registers all the 356 * time: 357 * 358 * - If we've touched any debug register, it is likely that we're 359 * going to touch more of them. It then makes sense to disable the 360 * traps and start doing the save/restore dance 361 * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is 362 * then mandatory to save/restore the registers, as the guest 363 * depends on them. 364 * 365 * For this, we use a DIRTY bit, indicating the guest has modified the 366 * debug registers, used as follow: 367 * 368 * On guest entry: 369 * - If the dirty bit is set (because we're coming back from trapping), 370 * disable the traps, save host registers, restore guest registers. 371 * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), 372 * set the dirty bit, disable the traps, save host registers, 373 * restore guest registers. 374 * - Otherwise, enable the traps 375 * 376 * On guest exit: 377 * - If the dirty bit is set, save guest registers, restore host 378 * registers and clear the dirty bit. This ensure that the host can 379 * now use the debug registers. 380 */ 381 static bool trap_debug_regs(struct kvm_vcpu *vcpu, 382 struct sys_reg_params *p, 383 const struct sys_reg_desc *r) 384 { 385 if (p->is_write) { 386 vcpu_write_sys_reg(vcpu, p->regval, r->reg); 387 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY; 388 } else { 389 p->regval = vcpu_read_sys_reg(vcpu, r->reg); 390 } 391 392 trace_trap_reg(__func__, r->reg, p->is_write, p->regval); 393 394 return true; 395 } 396 397 /* 398 * reg_to_dbg/dbg_to_reg 399 * 400 * A 32 bit write to a debug register leave top bits alone 401 * A 32 bit read from a debug register only returns the bottom bits 402 * 403 * All writes will set the KVM_ARM64_DEBUG_DIRTY flag to ensure the 404 * hyp.S code switches between host and guest values in future. 405 */ 406 static void reg_to_dbg(struct kvm_vcpu *vcpu, 407 struct sys_reg_params *p, 408 u64 *dbg_reg) 409 { 410 u64 val = p->regval; 411 412 if (p->is_32bit) { 413 val &= 0xffffffffUL; 414 val |= ((*dbg_reg >> 32) << 32); 415 } 416 417 *dbg_reg = val; 418 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY; 419 } 420 421 static void dbg_to_reg(struct kvm_vcpu *vcpu, 422 struct sys_reg_params *p, 423 u64 *dbg_reg) 424 { 425 p->regval = *dbg_reg; 426 if (p->is_32bit) 427 p->regval &= 0xffffffffUL; 428 } 429 430 static bool trap_bvr(struct kvm_vcpu *vcpu, 431 struct sys_reg_params *p, 432 const struct sys_reg_desc *rd) 433 { 434 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg]; 435 436 if (p->is_write) 437 reg_to_dbg(vcpu, p, dbg_reg); 438 else 439 dbg_to_reg(vcpu, p, dbg_reg); 440 441 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg); 442 443 return true; 444 } 445 446 static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 447 const struct kvm_one_reg *reg, void __user *uaddr) 448 { 449 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg]; 450 451 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) 452 return -EFAULT; 453 return 0; 454 } 455 456 static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 457 const struct kvm_one_reg *reg, void __user *uaddr) 458 { 459 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg]; 460 461 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) 462 return -EFAULT; 463 return 0; 464 } 465 466 static void reset_bvr(struct kvm_vcpu *vcpu, 467 const struct sys_reg_desc *rd) 468 { 469 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg] = rd->val; 470 } 471 472 static bool trap_bcr(struct kvm_vcpu *vcpu, 473 struct sys_reg_params *p, 474 const struct sys_reg_desc *rd) 475 { 476 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg]; 477 478 if (p->is_write) 479 reg_to_dbg(vcpu, p, dbg_reg); 480 else 481 dbg_to_reg(vcpu, p, dbg_reg); 482 483 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg); 484 485 return true; 486 } 487 488 static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 489 const struct kvm_one_reg *reg, void __user *uaddr) 490 { 491 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg]; 492 493 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) 494 return -EFAULT; 495 496 return 0; 497 } 498 499 static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 500 const struct kvm_one_reg *reg, void __user *uaddr) 501 { 502 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg]; 503 504 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) 505 return -EFAULT; 506 return 0; 507 } 508 509 static void reset_bcr(struct kvm_vcpu *vcpu, 510 const struct sys_reg_desc *rd) 511 { 512 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg] = rd->val; 513 } 514 515 static bool trap_wvr(struct kvm_vcpu *vcpu, 516 struct sys_reg_params *p, 517 const struct sys_reg_desc *rd) 518 { 519 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]; 520 521 if (p->is_write) 522 reg_to_dbg(vcpu, p, dbg_reg); 523 else 524 dbg_to_reg(vcpu, p, dbg_reg); 525 526 trace_trap_reg(__func__, rd->reg, p->is_write, 527 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]); 528 529 return true; 530 } 531 532 static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 533 const struct kvm_one_reg *reg, void __user *uaddr) 534 { 535 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]; 536 537 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) 538 return -EFAULT; 539 return 0; 540 } 541 542 static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 543 const struct kvm_one_reg *reg, void __user *uaddr) 544 { 545 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]; 546 547 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) 548 return -EFAULT; 549 return 0; 550 } 551 552 static void reset_wvr(struct kvm_vcpu *vcpu, 553 const struct sys_reg_desc *rd) 554 { 555 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg] = rd->val; 556 } 557 558 static bool trap_wcr(struct kvm_vcpu *vcpu, 559 struct sys_reg_params *p, 560 const struct sys_reg_desc *rd) 561 { 562 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg]; 563 564 if (p->is_write) 565 reg_to_dbg(vcpu, p, dbg_reg); 566 else 567 dbg_to_reg(vcpu, p, dbg_reg); 568 569 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg); 570 571 return true; 572 } 573 574 static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 575 const struct kvm_one_reg *reg, void __user *uaddr) 576 { 577 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg]; 578 579 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) 580 return -EFAULT; 581 return 0; 582 } 583 584 static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 585 const struct kvm_one_reg *reg, void __user *uaddr) 586 { 587 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg]; 588 589 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) 590 return -EFAULT; 591 return 0; 592 } 593 594 static void reset_wcr(struct kvm_vcpu *vcpu, 595 const struct sys_reg_desc *rd) 596 { 597 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg] = rd->val; 598 } 599 600 static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 601 { 602 u64 amair = read_sysreg(amair_el1); 603 vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1); 604 } 605 606 static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 607 { 608 u64 mpidr; 609 610 /* 611 * Map the vcpu_id into the first three affinity level fields of 612 * the MPIDR. We limit the number of VCPUs in level 0 due to a 613 * limitation to 16 CPUs in that level in the ICC_SGIxR registers 614 * of the GICv3 to be able to address each CPU directly when 615 * sending IPIs. 616 */ 617 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0); 618 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1); 619 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2); 620 vcpu_write_sys_reg(vcpu, (1ULL << 31) | mpidr, MPIDR_EL1); 621 } 622 623 static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 624 { 625 u64 pmcr, val; 626 627 pmcr = read_sysreg(pmcr_el0); 628 /* 629 * Writable bits of PMCR_EL0 (ARMV8_PMU_PMCR_MASK) are reset to UNKNOWN 630 * except PMCR.E resetting to zero. 631 */ 632 val = ((pmcr & ~ARMV8_PMU_PMCR_MASK) 633 | (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E); 634 if (!system_supports_32bit_el0()) 635 val |= ARMV8_PMU_PMCR_LC; 636 __vcpu_sys_reg(vcpu, r->reg) = val; 637 } 638 639 static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags) 640 { 641 u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0); 642 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu); 643 644 if (!enabled) 645 kvm_inject_undefined(vcpu); 646 647 return !enabled; 648 } 649 650 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu) 651 { 652 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN); 653 } 654 655 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu) 656 { 657 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN); 658 } 659 660 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu) 661 { 662 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN); 663 } 664 665 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu) 666 { 667 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN); 668 } 669 670 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 671 const struct sys_reg_desc *r) 672 { 673 u64 val; 674 675 if (!kvm_arm_pmu_v3_ready(vcpu)) 676 return trap_raz_wi(vcpu, p, r); 677 678 if (pmu_access_el0_disabled(vcpu)) 679 return false; 680 681 if (p->is_write) { 682 /* Only update writeable bits of PMCR */ 683 val = __vcpu_sys_reg(vcpu, PMCR_EL0); 684 val &= ~ARMV8_PMU_PMCR_MASK; 685 val |= p->regval & ARMV8_PMU_PMCR_MASK; 686 if (!system_supports_32bit_el0()) 687 val |= ARMV8_PMU_PMCR_LC; 688 __vcpu_sys_reg(vcpu, PMCR_EL0) = val; 689 kvm_pmu_handle_pmcr(vcpu, val); 690 kvm_vcpu_pmu_restore_guest(vcpu); 691 } else { 692 /* PMCR.P & PMCR.C are RAZ */ 693 val = __vcpu_sys_reg(vcpu, PMCR_EL0) 694 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C); 695 p->regval = val; 696 } 697 698 return true; 699 } 700 701 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 702 const struct sys_reg_desc *r) 703 { 704 if (!kvm_arm_pmu_v3_ready(vcpu)) 705 return trap_raz_wi(vcpu, p, r); 706 707 if (pmu_access_event_counter_el0_disabled(vcpu)) 708 return false; 709 710 if (p->is_write) 711 __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval; 712 else 713 /* return PMSELR.SEL field */ 714 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0) 715 & ARMV8_PMU_COUNTER_MASK; 716 717 return true; 718 } 719 720 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 721 const struct sys_reg_desc *r) 722 { 723 u64 pmceid; 724 725 if (!kvm_arm_pmu_v3_ready(vcpu)) 726 return trap_raz_wi(vcpu, p, r); 727 728 BUG_ON(p->is_write); 729 730 if (pmu_access_el0_disabled(vcpu)) 731 return false; 732 733 if (!(p->Op2 & 1)) 734 pmceid = read_sysreg(pmceid0_el0); 735 else 736 pmceid = read_sysreg(pmceid1_el0); 737 738 p->regval = pmceid; 739 740 return true; 741 } 742 743 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx) 744 { 745 u64 pmcr, val; 746 747 pmcr = __vcpu_sys_reg(vcpu, PMCR_EL0); 748 val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK; 749 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) { 750 kvm_inject_undefined(vcpu); 751 return false; 752 } 753 754 return true; 755 } 756 757 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu, 758 struct sys_reg_params *p, 759 const struct sys_reg_desc *r) 760 { 761 u64 idx; 762 763 if (!kvm_arm_pmu_v3_ready(vcpu)) 764 return trap_raz_wi(vcpu, p, r); 765 766 if (r->CRn == 9 && r->CRm == 13) { 767 if (r->Op2 == 2) { 768 /* PMXEVCNTR_EL0 */ 769 if (pmu_access_event_counter_el0_disabled(vcpu)) 770 return false; 771 772 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) 773 & ARMV8_PMU_COUNTER_MASK; 774 } else if (r->Op2 == 0) { 775 /* PMCCNTR_EL0 */ 776 if (pmu_access_cycle_counter_el0_disabled(vcpu)) 777 return false; 778 779 idx = ARMV8_PMU_CYCLE_IDX; 780 } else { 781 return false; 782 } 783 } else if (r->CRn == 0 && r->CRm == 9) { 784 /* PMCCNTR */ 785 if (pmu_access_event_counter_el0_disabled(vcpu)) 786 return false; 787 788 idx = ARMV8_PMU_CYCLE_IDX; 789 } else if (r->CRn == 14 && (r->CRm & 12) == 8) { 790 /* PMEVCNTRn_EL0 */ 791 if (pmu_access_event_counter_el0_disabled(vcpu)) 792 return false; 793 794 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 795 } else { 796 return false; 797 } 798 799 if (!pmu_counter_idx_valid(vcpu, idx)) 800 return false; 801 802 if (p->is_write) { 803 if (pmu_access_el0_disabled(vcpu)) 804 return false; 805 806 kvm_pmu_set_counter_value(vcpu, idx, p->regval); 807 } else { 808 p->regval = kvm_pmu_get_counter_value(vcpu, idx); 809 } 810 811 return true; 812 } 813 814 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 815 const struct sys_reg_desc *r) 816 { 817 u64 idx, reg; 818 819 if (!kvm_arm_pmu_v3_ready(vcpu)) 820 return trap_raz_wi(vcpu, p, r); 821 822 if (pmu_access_el0_disabled(vcpu)) 823 return false; 824 825 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) { 826 /* PMXEVTYPER_EL0 */ 827 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK; 828 reg = PMEVTYPER0_EL0 + idx; 829 } else if (r->CRn == 14 && (r->CRm & 12) == 12) { 830 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 831 if (idx == ARMV8_PMU_CYCLE_IDX) 832 reg = PMCCFILTR_EL0; 833 else 834 /* PMEVTYPERn_EL0 */ 835 reg = PMEVTYPER0_EL0 + idx; 836 } else { 837 BUG(); 838 } 839 840 if (!pmu_counter_idx_valid(vcpu, idx)) 841 return false; 842 843 if (p->is_write) { 844 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx); 845 __vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK; 846 kvm_vcpu_pmu_restore_guest(vcpu); 847 } else { 848 p->regval = __vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK; 849 } 850 851 return true; 852 } 853 854 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 855 const struct sys_reg_desc *r) 856 { 857 u64 val, mask; 858 859 if (!kvm_arm_pmu_v3_ready(vcpu)) 860 return trap_raz_wi(vcpu, p, r); 861 862 if (pmu_access_el0_disabled(vcpu)) 863 return false; 864 865 mask = kvm_pmu_valid_counter_mask(vcpu); 866 if (p->is_write) { 867 val = p->regval & mask; 868 if (r->Op2 & 0x1) { 869 /* accessing PMCNTENSET_EL0 */ 870 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val; 871 kvm_pmu_enable_counter_mask(vcpu, val); 872 kvm_vcpu_pmu_restore_guest(vcpu); 873 } else { 874 /* accessing PMCNTENCLR_EL0 */ 875 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val; 876 kvm_pmu_disable_counter_mask(vcpu, val); 877 } 878 } else { 879 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask; 880 } 881 882 return true; 883 } 884 885 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 886 const struct sys_reg_desc *r) 887 { 888 u64 mask = kvm_pmu_valid_counter_mask(vcpu); 889 890 if (!kvm_arm_pmu_v3_ready(vcpu)) 891 return trap_raz_wi(vcpu, p, r); 892 893 if (!vcpu_mode_priv(vcpu)) { 894 kvm_inject_undefined(vcpu); 895 return false; 896 } 897 898 if (p->is_write) { 899 u64 val = p->regval & mask; 900 901 if (r->Op2 & 0x1) 902 /* accessing PMINTENSET_EL1 */ 903 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val; 904 else 905 /* accessing PMINTENCLR_EL1 */ 906 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val; 907 } else { 908 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1) & mask; 909 } 910 911 return true; 912 } 913 914 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 915 const struct sys_reg_desc *r) 916 { 917 u64 mask = kvm_pmu_valid_counter_mask(vcpu); 918 919 if (!kvm_arm_pmu_v3_ready(vcpu)) 920 return trap_raz_wi(vcpu, p, r); 921 922 if (pmu_access_el0_disabled(vcpu)) 923 return false; 924 925 if (p->is_write) { 926 if (r->CRm & 0x2) 927 /* accessing PMOVSSET_EL0 */ 928 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask); 929 else 930 /* accessing PMOVSCLR_EL0 */ 931 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask); 932 } else { 933 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0) & mask; 934 } 935 936 return true; 937 } 938 939 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 940 const struct sys_reg_desc *r) 941 { 942 u64 mask; 943 944 if (!kvm_arm_pmu_v3_ready(vcpu)) 945 return trap_raz_wi(vcpu, p, r); 946 947 if (!p->is_write) 948 return read_from_write_only(vcpu, p, r); 949 950 if (pmu_write_swinc_el0_disabled(vcpu)) 951 return false; 952 953 mask = kvm_pmu_valid_counter_mask(vcpu); 954 kvm_pmu_software_increment(vcpu, p->regval & mask); 955 return true; 956 } 957 958 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 959 const struct sys_reg_desc *r) 960 { 961 if (!kvm_arm_pmu_v3_ready(vcpu)) 962 return trap_raz_wi(vcpu, p, r); 963 964 if (p->is_write) { 965 if (!vcpu_mode_priv(vcpu)) { 966 kvm_inject_undefined(vcpu); 967 return false; 968 } 969 970 __vcpu_sys_reg(vcpu, PMUSERENR_EL0) = 971 p->regval & ARMV8_PMU_USERENR_MASK; 972 } else { 973 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0) 974 & ARMV8_PMU_USERENR_MASK; 975 } 976 977 return true; 978 } 979 980 #define reg_to_encoding(x) \ 981 sys_reg((u32)(x)->Op0, (u32)(x)->Op1, \ 982 (u32)(x)->CRn, (u32)(x)->CRm, (u32)(x)->Op2); 983 984 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */ 985 #define DBG_BCR_BVR_WCR_WVR_EL1(n) \ 986 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \ 987 trap_bvr, reset_bvr, 0, 0, get_bvr, set_bvr }, \ 988 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \ 989 trap_bcr, reset_bcr, 0, 0, get_bcr, set_bcr }, \ 990 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \ 991 trap_wvr, reset_wvr, 0, 0, get_wvr, set_wvr }, \ 992 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \ 993 trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr } 994 995 /* Macro to expand the PMEVCNTRn_EL0 register */ 996 #define PMU_PMEVCNTR_EL0(n) \ 997 { SYS_DESC(SYS_PMEVCNTRn_EL0(n)), \ 998 access_pmu_evcntr, reset_unknown, (PMEVCNTR0_EL0 + n), } 999 1000 /* Macro to expand the PMEVTYPERn_EL0 register */ 1001 #define PMU_PMEVTYPER_EL0(n) \ 1002 { SYS_DESC(SYS_PMEVTYPERn_EL0(n)), \ 1003 access_pmu_evtyper, reset_unknown, (PMEVTYPER0_EL0 + n), } 1004 1005 static bool access_amu(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1006 const struct sys_reg_desc *r) 1007 { 1008 kvm_inject_undefined(vcpu); 1009 1010 return false; 1011 } 1012 1013 /* Macro to expand the AMU counter and type registers*/ 1014 #define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), access_amu } 1015 #define AMU_AMEVTYPE0_EL0(n) { SYS_DESC(SYS_AMEVTYPE0_EL0(n)), access_amu } 1016 #define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), access_amu } 1017 #define AMU_AMEVTYPE1_EL0(n) { SYS_DESC(SYS_AMEVTYPE1_EL0(n)), access_amu } 1018 1019 static bool trap_ptrauth(struct kvm_vcpu *vcpu, 1020 struct sys_reg_params *p, 1021 const struct sys_reg_desc *rd) 1022 { 1023 kvm_arm_vcpu_ptrauth_trap(vcpu); 1024 1025 /* 1026 * Return false for both cases as we never skip the trapped 1027 * instruction: 1028 * 1029 * - Either we re-execute the same key register access instruction 1030 * after enabling ptrauth. 1031 * - Or an UNDEF is injected as ptrauth is not supported/enabled. 1032 */ 1033 return false; 1034 } 1035 1036 static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu, 1037 const struct sys_reg_desc *rd) 1038 { 1039 return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN_USER | REG_HIDDEN_GUEST; 1040 } 1041 1042 #define __PTRAUTH_KEY(k) \ 1043 { SYS_DESC(SYS_## k), trap_ptrauth, reset_unknown, k, \ 1044 .visibility = ptrauth_visibility} 1045 1046 #define PTRAUTH_KEY(k) \ 1047 __PTRAUTH_KEY(k ## KEYLO_EL1), \ 1048 __PTRAUTH_KEY(k ## KEYHI_EL1) 1049 1050 static bool access_arch_timer(struct kvm_vcpu *vcpu, 1051 struct sys_reg_params *p, 1052 const struct sys_reg_desc *r) 1053 { 1054 enum kvm_arch_timers tmr; 1055 enum kvm_arch_timer_regs treg; 1056 u64 reg = reg_to_encoding(r); 1057 1058 switch (reg) { 1059 case SYS_CNTP_TVAL_EL0: 1060 case SYS_AARCH32_CNTP_TVAL: 1061 tmr = TIMER_PTIMER; 1062 treg = TIMER_REG_TVAL; 1063 break; 1064 case SYS_CNTP_CTL_EL0: 1065 case SYS_AARCH32_CNTP_CTL: 1066 tmr = TIMER_PTIMER; 1067 treg = TIMER_REG_CTL; 1068 break; 1069 case SYS_CNTP_CVAL_EL0: 1070 case SYS_AARCH32_CNTP_CVAL: 1071 tmr = TIMER_PTIMER; 1072 treg = TIMER_REG_CVAL; 1073 break; 1074 default: 1075 BUG(); 1076 } 1077 1078 if (p->is_write) 1079 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval); 1080 else 1081 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg); 1082 1083 return true; 1084 } 1085 1086 /* Read a sanitised cpufeature ID register by sys_reg_desc */ 1087 static u64 read_id_reg(const struct kvm_vcpu *vcpu, 1088 struct sys_reg_desc const *r, bool raz) 1089 { 1090 u32 id = sys_reg((u32)r->Op0, (u32)r->Op1, 1091 (u32)r->CRn, (u32)r->CRm, (u32)r->Op2); 1092 u64 val = raz ? 0 : read_sanitised_ftr_reg(id); 1093 1094 if (id == SYS_ID_AA64PFR0_EL1) { 1095 if (!vcpu_has_sve(vcpu)) 1096 val &= ~(0xfUL << ID_AA64PFR0_SVE_SHIFT); 1097 val &= ~(0xfUL << ID_AA64PFR0_AMU_SHIFT); 1098 } else if (id == SYS_ID_AA64ISAR1_EL1 && !vcpu_has_ptrauth(vcpu)) { 1099 val &= ~((0xfUL << ID_AA64ISAR1_APA_SHIFT) | 1100 (0xfUL << ID_AA64ISAR1_API_SHIFT) | 1101 (0xfUL << ID_AA64ISAR1_GPA_SHIFT) | 1102 (0xfUL << ID_AA64ISAR1_GPI_SHIFT)); 1103 } else if (id == SYS_ID_AA64DFR0_EL1) { 1104 /* Limit guests to PMUv3 for ARMv8.1 */ 1105 val = cpuid_feature_cap_perfmon_field(val, 1106 ID_AA64DFR0_PMUVER_SHIFT, 1107 ID_AA64DFR0_PMUVER_8_1); 1108 } else if (id == SYS_ID_DFR0_EL1) { 1109 /* Limit guests to PMUv3 for ARMv8.1 */ 1110 val = cpuid_feature_cap_perfmon_field(val, 1111 ID_DFR0_PERFMON_SHIFT, 1112 ID_DFR0_PERFMON_8_1); 1113 } 1114 1115 return val; 1116 } 1117 1118 /* cpufeature ID register access trap handlers */ 1119 1120 static bool __access_id_reg(struct kvm_vcpu *vcpu, 1121 struct sys_reg_params *p, 1122 const struct sys_reg_desc *r, 1123 bool raz) 1124 { 1125 if (p->is_write) 1126 return write_to_read_only(vcpu, p, r); 1127 1128 p->regval = read_id_reg(vcpu, r, raz); 1129 return true; 1130 } 1131 1132 static bool access_id_reg(struct kvm_vcpu *vcpu, 1133 struct sys_reg_params *p, 1134 const struct sys_reg_desc *r) 1135 { 1136 return __access_id_reg(vcpu, p, r, false); 1137 } 1138 1139 static bool access_raz_id_reg(struct kvm_vcpu *vcpu, 1140 struct sys_reg_params *p, 1141 const struct sys_reg_desc *r) 1142 { 1143 return __access_id_reg(vcpu, p, r, true); 1144 } 1145 1146 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id); 1147 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id); 1148 static u64 sys_reg_to_index(const struct sys_reg_desc *reg); 1149 1150 /* Visibility overrides for SVE-specific control registers */ 1151 static unsigned int sve_visibility(const struct kvm_vcpu *vcpu, 1152 const struct sys_reg_desc *rd) 1153 { 1154 if (vcpu_has_sve(vcpu)) 1155 return 0; 1156 1157 return REG_HIDDEN_USER | REG_HIDDEN_GUEST; 1158 } 1159 1160 /* Visibility overrides for SVE-specific ID registers */ 1161 static unsigned int sve_id_visibility(const struct kvm_vcpu *vcpu, 1162 const struct sys_reg_desc *rd) 1163 { 1164 if (vcpu_has_sve(vcpu)) 1165 return 0; 1166 1167 return REG_HIDDEN_USER; 1168 } 1169 1170 /* Generate the emulated ID_AA64ZFR0_EL1 value exposed to the guest */ 1171 static u64 guest_id_aa64zfr0_el1(const struct kvm_vcpu *vcpu) 1172 { 1173 if (!vcpu_has_sve(vcpu)) 1174 return 0; 1175 1176 return read_sanitised_ftr_reg(SYS_ID_AA64ZFR0_EL1); 1177 } 1178 1179 static bool access_id_aa64zfr0_el1(struct kvm_vcpu *vcpu, 1180 struct sys_reg_params *p, 1181 const struct sys_reg_desc *rd) 1182 { 1183 if (p->is_write) 1184 return write_to_read_only(vcpu, p, rd); 1185 1186 p->regval = guest_id_aa64zfr0_el1(vcpu); 1187 return true; 1188 } 1189 1190 static int get_id_aa64zfr0_el1(struct kvm_vcpu *vcpu, 1191 const struct sys_reg_desc *rd, 1192 const struct kvm_one_reg *reg, void __user *uaddr) 1193 { 1194 u64 val; 1195 1196 if (WARN_ON(!vcpu_has_sve(vcpu))) 1197 return -ENOENT; 1198 1199 val = guest_id_aa64zfr0_el1(vcpu); 1200 return reg_to_user(uaddr, &val, reg->id); 1201 } 1202 1203 static int set_id_aa64zfr0_el1(struct kvm_vcpu *vcpu, 1204 const struct sys_reg_desc *rd, 1205 const struct kvm_one_reg *reg, void __user *uaddr) 1206 { 1207 const u64 id = sys_reg_to_index(rd); 1208 int err; 1209 u64 val; 1210 1211 if (WARN_ON(!vcpu_has_sve(vcpu))) 1212 return -ENOENT; 1213 1214 err = reg_from_user(&val, uaddr, id); 1215 if (err) 1216 return err; 1217 1218 /* This is what we mean by invariant: you can't change it. */ 1219 if (val != guest_id_aa64zfr0_el1(vcpu)) 1220 return -EINVAL; 1221 1222 return 0; 1223 } 1224 1225 /* 1226 * cpufeature ID register user accessors 1227 * 1228 * For now, these registers are immutable for userspace, so no values 1229 * are stored, and for set_id_reg() we don't allow the effective value 1230 * to be changed. 1231 */ 1232 static int __get_id_reg(const struct kvm_vcpu *vcpu, 1233 const struct sys_reg_desc *rd, void __user *uaddr, 1234 bool raz) 1235 { 1236 const u64 id = sys_reg_to_index(rd); 1237 const u64 val = read_id_reg(vcpu, rd, raz); 1238 1239 return reg_to_user(uaddr, &val, id); 1240 } 1241 1242 static int __set_id_reg(const struct kvm_vcpu *vcpu, 1243 const struct sys_reg_desc *rd, void __user *uaddr, 1244 bool raz) 1245 { 1246 const u64 id = sys_reg_to_index(rd); 1247 int err; 1248 u64 val; 1249 1250 err = reg_from_user(&val, uaddr, id); 1251 if (err) 1252 return err; 1253 1254 /* This is what we mean by invariant: you can't change it. */ 1255 if (val != read_id_reg(vcpu, rd, raz)) 1256 return -EINVAL; 1257 1258 return 0; 1259 } 1260 1261 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1262 const struct kvm_one_reg *reg, void __user *uaddr) 1263 { 1264 return __get_id_reg(vcpu, rd, uaddr, false); 1265 } 1266 1267 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1268 const struct kvm_one_reg *reg, void __user *uaddr) 1269 { 1270 return __set_id_reg(vcpu, rd, uaddr, false); 1271 } 1272 1273 static int get_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1274 const struct kvm_one_reg *reg, void __user *uaddr) 1275 { 1276 return __get_id_reg(vcpu, rd, uaddr, true); 1277 } 1278 1279 static int set_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1280 const struct kvm_one_reg *reg, void __user *uaddr) 1281 { 1282 return __set_id_reg(vcpu, rd, uaddr, true); 1283 } 1284 1285 static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1286 const struct sys_reg_desc *r) 1287 { 1288 if (p->is_write) 1289 return write_to_read_only(vcpu, p, r); 1290 1291 p->regval = read_sanitised_ftr_reg(SYS_CTR_EL0); 1292 return true; 1293 } 1294 1295 static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1296 const struct sys_reg_desc *r) 1297 { 1298 if (p->is_write) 1299 return write_to_read_only(vcpu, p, r); 1300 1301 p->regval = read_sysreg(clidr_el1); 1302 return true; 1303 } 1304 1305 static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1306 const struct sys_reg_desc *r) 1307 { 1308 if (p->is_write) 1309 vcpu_write_sys_reg(vcpu, p->regval, r->reg); 1310 else 1311 p->regval = vcpu_read_sys_reg(vcpu, r->reg); 1312 return true; 1313 } 1314 1315 static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1316 const struct sys_reg_desc *r) 1317 { 1318 u32 csselr; 1319 1320 if (p->is_write) 1321 return write_to_read_only(vcpu, p, r); 1322 1323 csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1); 1324 p->regval = get_ccsidr(csselr); 1325 1326 /* 1327 * Guests should not be doing cache operations by set/way at all, and 1328 * for this reason, we trap them and attempt to infer the intent, so 1329 * that we can flush the entire guest's address space at the appropriate 1330 * time. 1331 * To prevent this trapping from causing performance problems, let's 1332 * expose the geometry of all data and unified caches (which are 1333 * guaranteed to be PIPT and thus non-aliasing) as 1 set and 1 way. 1334 * [If guests should attempt to infer aliasing properties from the 1335 * geometry (which is not permitted by the architecture), they would 1336 * only do so for virtually indexed caches.] 1337 */ 1338 if (!(csselr & 1)) // data or unified cache 1339 p->regval &= ~GENMASK(27, 3); 1340 return true; 1341 } 1342 1343 /* sys_reg_desc initialiser for known cpufeature ID registers */ 1344 #define ID_SANITISED(name) { \ 1345 SYS_DESC(SYS_##name), \ 1346 .access = access_id_reg, \ 1347 .get_user = get_id_reg, \ 1348 .set_user = set_id_reg, \ 1349 } 1350 1351 /* 1352 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID 1353 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2 1354 * (1 <= crm < 8, 0 <= Op2 < 8). 1355 */ 1356 #define ID_UNALLOCATED(crm, op2) { \ 1357 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \ 1358 .access = access_raz_id_reg, \ 1359 .get_user = get_raz_id_reg, \ 1360 .set_user = set_raz_id_reg, \ 1361 } 1362 1363 /* 1364 * sys_reg_desc initialiser for known ID registers that we hide from guests. 1365 * For now, these are exposed just like unallocated ID regs: they appear 1366 * RAZ for the guest. 1367 */ 1368 #define ID_HIDDEN(name) { \ 1369 SYS_DESC(SYS_##name), \ 1370 .access = access_raz_id_reg, \ 1371 .get_user = get_raz_id_reg, \ 1372 .set_user = set_raz_id_reg, \ 1373 } 1374 1375 /* 1376 * Architected system registers. 1377 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2 1378 * 1379 * Debug handling: We do trap most, if not all debug related system 1380 * registers. The implementation is good enough to ensure that a guest 1381 * can use these with minimal performance degradation. The drawback is 1382 * that we don't implement any of the external debug, none of the 1383 * OSlock protocol. This should be revisited if we ever encounter a 1384 * more demanding guest... 1385 */ 1386 static const struct sys_reg_desc sys_reg_descs[] = { 1387 { SYS_DESC(SYS_DC_ISW), access_dcsw }, 1388 { SYS_DESC(SYS_DC_CSW), access_dcsw }, 1389 { SYS_DESC(SYS_DC_CISW), access_dcsw }, 1390 1391 DBG_BCR_BVR_WCR_WVR_EL1(0), 1392 DBG_BCR_BVR_WCR_WVR_EL1(1), 1393 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 }, 1394 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 }, 1395 DBG_BCR_BVR_WCR_WVR_EL1(2), 1396 DBG_BCR_BVR_WCR_WVR_EL1(3), 1397 DBG_BCR_BVR_WCR_WVR_EL1(4), 1398 DBG_BCR_BVR_WCR_WVR_EL1(5), 1399 DBG_BCR_BVR_WCR_WVR_EL1(6), 1400 DBG_BCR_BVR_WCR_WVR_EL1(7), 1401 DBG_BCR_BVR_WCR_WVR_EL1(8), 1402 DBG_BCR_BVR_WCR_WVR_EL1(9), 1403 DBG_BCR_BVR_WCR_WVR_EL1(10), 1404 DBG_BCR_BVR_WCR_WVR_EL1(11), 1405 DBG_BCR_BVR_WCR_WVR_EL1(12), 1406 DBG_BCR_BVR_WCR_WVR_EL1(13), 1407 DBG_BCR_BVR_WCR_WVR_EL1(14), 1408 DBG_BCR_BVR_WCR_WVR_EL1(15), 1409 1410 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi }, 1411 { SYS_DESC(SYS_OSLAR_EL1), trap_raz_wi }, 1412 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1 }, 1413 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi }, 1414 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi }, 1415 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi }, 1416 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi }, 1417 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 }, 1418 1419 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi }, 1420 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi }, 1421 // DBGDTR[TR]X_EL0 share the same encoding 1422 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi }, 1423 1424 { SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 }, 1425 1426 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 }, 1427 1428 /* 1429 * ID regs: all ID_SANITISED() entries here must have corresponding 1430 * entries in arm64_ftr_regs[]. 1431 */ 1432 1433 /* AArch64 mappings of the AArch32 ID registers */ 1434 /* CRm=1 */ 1435 ID_SANITISED(ID_PFR0_EL1), 1436 ID_SANITISED(ID_PFR1_EL1), 1437 ID_SANITISED(ID_DFR0_EL1), 1438 ID_HIDDEN(ID_AFR0_EL1), 1439 ID_SANITISED(ID_MMFR0_EL1), 1440 ID_SANITISED(ID_MMFR1_EL1), 1441 ID_SANITISED(ID_MMFR2_EL1), 1442 ID_SANITISED(ID_MMFR3_EL1), 1443 1444 /* CRm=2 */ 1445 ID_SANITISED(ID_ISAR0_EL1), 1446 ID_SANITISED(ID_ISAR1_EL1), 1447 ID_SANITISED(ID_ISAR2_EL1), 1448 ID_SANITISED(ID_ISAR3_EL1), 1449 ID_SANITISED(ID_ISAR4_EL1), 1450 ID_SANITISED(ID_ISAR5_EL1), 1451 ID_SANITISED(ID_MMFR4_EL1), 1452 ID_SANITISED(ID_ISAR6_EL1), 1453 1454 /* CRm=3 */ 1455 ID_SANITISED(MVFR0_EL1), 1456 ID_SANITISED(MVFR1_EL1), 1457 ID_SANITISED(MVFR2_EL1), 1458 ID_UNALLOCATED(3,3), 1459 ID_UNALLOCATED(3,4), 1460 ID_UNALLOCATED(3,5), 1461 ID_UNALLOCATED(3,6), 1462 ID_UNALLOCATED(3,7), 1463 1464 /* AArch64 ID registers */ 1465 /* CRm=4 */ 1466 ID_SANITISED(ID_AA64PFR0_EL1), 1467 ID_SANITISED(ID_AA64PFR1_EL1), 1468 ID_UNALLOCATED(4,2), 1469 ID_UNALLOCATED(4,3), 1470 { SYS_DESC(SYS_ID_AA64ZFR0_EL1), access_id_aa64zfr0_el1, .get_user = get_id_aa64zfr0_el1, .set_user = set_id_aa64zfr0_el1, .visibility = sve_id_visibility }, 1471 ID_UNALLOCATED(4,5), 1472 ID_UNALLOCATED(4,6), 1473 ID_UNALLOCATED(4,7), 1474 1475 /* CRm=5 */ 1476 ID_SANITISED(ID_AA64DFR0_EL1), 1477 ID_SANITISED(ID_AA64DFR1_EL1), 1478 ID_UNALLOCATED(5,2), 1479 ID_UNALLOCATED(5,3), 1480 ID_HIDDEN(ID_AA64AFR0_EL1), 1481 ID_HIDDEN(ID_AA64AFR1_EL1), 1482 ID_UNALLOCATED(5,6), 1483 ID_UNALLOCATED(5,7), 1484 1485 /* CRm=6 */ 1486 ID_SANITISED(ID_AA64ISAR0_EL1), 1487 ID_SANITISED(ID_AA64ISAR1_EL1), 1488 ID_UNALLOCATED(6,2), 1489 ID_UNALLOCATED(6,3), 1490 ID_UNALLOCATED(6,4), 1491 ID_UNALLOCATED(6,5), 1492 ID_UNALLOCATED(6,6), 1493 ID_UNALLOCATED(6,7), 1494 1495 /* CRm=7 */ 1496 ID_SANITISED(ID_AA64MMFR0_EL1), 1497 ID_SANITISED(ID_AA64MMFR1_EL1), 1498 ID_SANITISED(ID_AA64MMFR2_EL1), 1499 ID_UNALLOCATED(7,3), 1500 ID_UNALLOCATED(7,4), 1501 ID_UNALLOCATED(7,5), 1502 ID_UNALLOCATED(7,6), 1503 ID_UNALLOCATED(7,7), 1504 1505 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 }, 1506 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 }, 1507 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility }, 1508 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 }, 1509 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 }, 1510 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 }, 1511 1512 PTRAUTH_KEY(APIA), 1513 PTRAUTH_KEY(APIB), 1514 PTRAUTH_KEY(APDA), 1515 PTRAUTH_KEY(APDB), 1516 PTRAUTH_KEY(APGA), 1517 1518 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 }, 1519 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 }, 1520 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 }, 1521 1522 { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi }, 1523 { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi }, 1524 { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi }, 1525 { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi }, 1526 { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi }, 1527 { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi }, 1528 { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi }, 1529 { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi }, 1530 1531 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 }, 1532 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 }, 1533 1534 { SYS_DESC(SYS_PMINTENSET_EL1), access_pminten, reset_unknown, PMINTENSET_EL1 }, 1535 { SYS_DESC(SYS_PMINTENCLR_EL1), access_pminten, NULL, PMINTENSET_EL1 }, 1536 1537 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 }, 1538 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 }, 1539 1540 { SYS_DESC(SYS_LORSA_EL1), trap_loregion }, 1541 { SYS_DESC(SYS_LOREA_EL1), trap_loregion }, 1542 { SYS_DESC(SYS_LORN_EL1), trap_loregion }, 1543 { SYS_DESC(SYS_LORC_EL1), trap_loregion }, 1544 { SYS_DESC(SYS_LORID_EL1), trap_loregion }, 1545 1546 { SYS_DESC(SYS_VBAR_EL1), NULL, reset_val, VBAR_EL1, 0 }, 1547 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 }, 1548 1549 { SYS_DESC(SYS_ICC_IAR0_EL1), write_to_read_only }, 1550 { SYS_DESC(SYS_ICC_EOIR0_EL1), read_from_write_only }, 1551 { SYS_DESC(SYS_ICC_HPPIR0_EL1), write_to_read_only }, 1552 { SYS_DESC(SYS_ICC_DIR_EL1), read_from_write_only }, 1553 { SYS_DESC(SYS_ICC_RPR_EL1), write_to_read_only }, 1554 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi }, 1555 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi }, 1556 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi }, 1557 { SYS_DESC(SYS_ICC_IAR1_EL1), write_to_read_only }, 1558 { SYS_DESC(SYS_ICC_EOIR1_EL1), read_from_write_only }, 1559 { SYS_DESC(SYS_ICC_HPPIR1_EL1), write_to_read_only }, 1560 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre }, 1561 1562 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 }, 1563 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 }, 1564 1565 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0}, 1566 1567 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr }, 1568 { SYS_DESC(SYS_CLIDR_EL1), access_clidr }, 1569 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, 1570 { SYS_DESC(SYS_CTR_EL0), access_ctr }, 1571 1572 { SYS_DESC(SYS_PMCR_EL0), access_pmcr, reset_pmcr, PMCR_EL0 }, 1573 { SYS_DESC(SYS_PMCNTENSET_EL0), access_pmcnten, reset_unknown, PMCNTENSET_EL0 }, 1574 { SYS_DESC(SYS_PMCNTENCLR_EL0), access_pmcnten, NULL, PMCNTENSET_EL0 }, 1575 { SYS_DESC(SYS_PMOVSCLR_EL0), access_pmovs, NULL, PMOVSSET_EL0 }, 1576 { SYS_DESC(SYS_PMSWINC_EL0), access_pmswinc, reset_unknown, PMSWINC_EL0 }, 1577 { SYS_DESC(SYS_PMSELR_EL0), access_pmselr, reset_unknown, PMSELR_EL0 }, 1578 { SYS_DESC(SYS_PMCEID0_EL0), access_pmceid }, 1579 { SYS_DESC(SYS_PMCEID1_EL0), access_pmceid }, 1580 { SYS_DESC(SYS_PMCCNTR_EL0), access_pmu_evcntr, reset_unknown, PMCCNTR_EL0 }, 1581 { SYS_DESC(SYS_PMXEVTYPER_EL0), access_pmu_evtyper }, 1582 { SYS_DESC(SYS_PMXEVCNTR_EL0), access_pmu_evcntr }, 1583 /* 1584 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero 1585 * in 32bit mode. Here we choose to reset it as zero for consistency. 1586 */ 1587 { SYS_DESC(SYS_PMUSERENR_EL0), access_pmuserenr, reset_val, PMUSERENR_EL0, 0 }, 1588 { SYS_DESC(SYS_PMOVSSET_EL0), access_pmovs, reset_unknown, PMOVSSET_EL0 }, 1589 1590 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 }, 1591 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 }, 1592 1593 { SYS_DESC(SYS_AMCR_EL0), access_amu }, 1594 { SYS_DESC(SYS_AMCFGR_EL0), access_amu }, 1595 { SYS_DESC(SYS_AMCGCR_EL0), access_amu }, 1596 { SYS_DESC(SYS_AMUSERENR_EL0), access_amu }, 1597 { SYS_DESC(SYS_AMCNTENCLR0_EL0), access_amu }, 1598 { SYS_DESC(SYS_AMCNTENSET0_EL0), access_amu }, 1599 { SYS_DESC(SYS_AMCNTENCLR1_EL0), access_amu }, 1600 { SYS_DESC(SYS_AMCNTENSET1_EL0), access_amu }, 1601 AMU_AMEVCNTR0_EL0(0), 1602 AMU_AMEVCNTR0_EL0(1), 1603 AMU_AMEVCNTR0_EL0(2), 1604 AMU_AMEVCNTR0_EL0(3), 1605 AMU_AMEVCNTR0_EL0(4), 1606 AMU_AMEVCNTR0_EL0(5), 1607 AMU_AMEVCNTR0_EL0(6), 1608 AMU_AMEVCNTR0_EL0(7), 1609 AMU_AMEVCNTR0_EL0(8), 1610 AMU_AMEVCNTR0_EL0(9), 1611 AMU_AMEVCNTR0_EL0(10), 1612 AMU_AMEVCNTR0_EL0(11), 1613 AMU_AMEVCNTR0_EL0(12), 1614 AMU_AMEVCNTR0_EL0(13), 1615 AMU_AMEVCNTR0_EL0(14), 1616 AMU_AMEVCNTR0_EL0(15), 1617 AMU_AMEVTYPE0_EL0(0), 1618 AMU_AMEVTYPE0_EL0(1), 1619 AMU_AMEVTYPE0_EL0(2), 1620 AMU_AMEVTYPE0_EL0(3), 1621 AMU_AMEVTYPE0_EL0(4), 1622 AMU_AMEVTYPE0_EL0(5), 1623 AMU_AMEVTYPE0_EL0(6), 1624 AMU_AMEVTYPE0_EL0(7), 1625 AMU_AMEVTYPE0_EL0(8), 1626 AMU_AMEVTYPE0_EL0(9), 1627 AMU_AMEVTYPE0_EL0(10), 1628 AMU_AMEVTYPE0_EL0(11), 1629 AMU_AMEVTYPE0_EL0(12), 1630 AMU_AMEVTYPE0_EL0(13), 1631 AMU_AMEVTYPE0_EL0(14), 1632 AMU_AMEVTYPE0_EL0(15), 1633 AMU_AMEVCNTR1_EL0(0), 1634 AMU_AMEVCNTR1_EL0(1), 1635 AMU_AMEVCNTR1_EL0(2), 1636 AMU_AMEVCNTR1_EL0(3), 1637 AMU_AMEVCNTR1_EL0(4), 1638 AMU_AMEVCNTR1_EL0(5), 1639 AMU_AMEVCNTR1_EL0(6), 1640 AMU_AMEVCNTR1_EL0(7), 1641 AMU_AMEVCNTR1_EL0(8), 1642 AMU_AMEVCNTR1_EL0(9), 1643 AMU_AMEVCNTR1_EL0(10), 1644 AMU_AMEVCNTR1_EL0(11), 1645 AMU_AMEVCNTR1_EL0(12), 1646 AMU_AMEVCNTR1_EL0(13), 1647 AMU_AMEVCNTR1_EL0(14), 1648 AMU_AMEVCNTR1_EL0(15), 1649 AMU_AMEVTYPE1_EL0(0), 1650 AMU_AMEVTYPE1_EL0(1), 1651 AMU_AMEVTYPE1_EL0(2), 1652 AMU_AMEVTYPE1_EL0(3), 1653 AMU_AMEVTYPE1_EL0(4), 1654 AMU_AMEVTYPE1_EL0(5), 1655 AMU_AMEVTYPE1_EL0(6), 1656 AMU_AMEVTYPE1_EL0(7), 1657 AMU_AMEVTYPE1_EL0(8), 1658 AMU_AMEVTYPE1_EL0(9), 1659 AMU_AMEVTYPE1_EL0(10), 1660 AMU_AMEVTYPE1_EL0(11), 1661 AMU_AMEVTYPE1_EL0(12), 1662 AMU_AMEVTYPE1_EL0(13), 1663 AMU_AMEVTYPE1_EL0(14), 1664 AMU_AMEVTYPE1_EL0(15), 1665 1666 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer }, 1667 { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer }, 1668 { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer }, 1669 1670 /* PMEVCNTRn_EL0 */ 1671 PMU_PMEVCNTR_EL0(0), 1672 PMU_PMEVCNTR_EL0(1), 1673 PMU_PMEVCNTR_EL0(2), 1674 PMU_PMEVCNTR_EL0(3), 1675 PMU_PMEVCNTR_EL0(4), 1676 PMU_PMEVCNTR_EL0(5), 1677 PMU_PMEVCNTR_EL0(6), 1678 PMU_PMEVCNTR_EL0(7), 1679 PMU_PMEVCNTR_EL0(8), 1680 PMU_PMEVCNTR_EL0(9), 1681 PMU_PMEVCNTR_EL0(10), 1682 PMU_PMEVCNTR_EL0(11), 1683 PMU_PMEVCNTR_EL0(12), 1684 PMU_PMEVCNTR_EL0(13), 1685 PMU_PMEVCNTR_EL0(14), 1686 PMU_PMEVCNTR_EL0(15), 1687 PMU_PMEVCNTR_EL0(16), 1688 PMU_PMEVCNTR_EL0(17), 1689 PMU_PMEVCNTR_EL0(18), 1690 PMU_PMEVCNTR_EL0(19), 1691 PMU_PMEVCNTR_EL0(20), 1692 PMU_PMEVCNTR_EL0(21), 1693 PMU_PMEVCNTR_EL0(22), 1694 PMU_PMEVCNTR_EL0(23), 1695 PMU_PMEVCNTR_EL0(24), 1696 PMU_PMEVCNTR_EL0(25), 1697 PMU_PMEVCNTR_EL0(26), 1698 PMU_PMEVCNTR_EL0(27), 1699 PMU_PMEVCNTR_EL0(28), 1700 PMU_PMEVCNTR_EL0(29), 1701 PMU_PMEVCNTR_EL0(30), 1702 /* PMEVTYPERn_EL0 */ 1703 PMU_PMEVTYPER_EL0(0), 1704 PMU_PMEVTYPER_EL0(1), 1705 PMU_PMEVTYPER_EL0(2), 1706 PMU_PMEVTYPER_EL0(3), 1707 PMU_PMEVTYPER_EL0(4), 1708 PMU_PMEVTYPER_EL0(5), 1709 PMU_PMEVTYPER_EL0(6), 1710 PMU_PMEVTYPER_EL0(7), 1711 PMU_PMEVTYPER_EL0(8), 1712 PMU_PMEVTYPER_EL0(9), 1713 PMU_PMEVTYPER_EL0(10), 1714 PMU_PMEVTYPER_EL0(11), 1715 PMU_PMEVTYPER_EL0(12), 1716 PMU_PMEVTYPER_EL0(13), 1717 PMU_PMEVTYPER_EL0(14), 1718 PMU_PMEVTYPER_EL0(15), 1719 PMU_PMEVTYPER_EL0(16), 1720 PMU_PMEVTYPER_EL0(17), 1721 PMU_PMEVTYPER_EL0(18), 1722 PMU_PMEVTYPER_EL0(19), 1723 PMU_PMEVTYPER_EL0(20), 1724 PMU_PMEVTYPER_EL0(21), 1725 PMU_PMEVTYPER_EL0(22), 1726 PMU_PMEVTYPER_EL0(23), 1727 PMU_PMEVTYPER_EL0(24), 1728 PMU_PMEVTYPER_EL0(25), 1729 PMU_PMEVTYPER_EL0(26), 1730 PMU_PMEVTYPER_EL0(27), 1731 PMU_PMEVTYPER_EL0(28), 1732 PMU_PMEVTYPER_EL0(29), 1733 PMU_PMEVTYPER_EL0(30), 1734 /* 1735 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero 1736 * in 32bit mode. Here we choose to reset it as zero for consistency. 1737 */ 1738 { SYS_DESC(SYS_PMCCFILTR_EL0), access_pmu_evtyper, reset_val, PMCCFILTR_EL0, 0 }, 1739 1740 { SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 }, 1741 { SYS_DESC(SYS_IFSR32_EL2), NULL, reset_unknown, IFSR32_EL2 }, 1742 { SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x700 }, 1743 }; 1744 1745 static bool trap_dbgidr(struct kvm_vcpu *vcpu, 1746 struct sys_reg_params *p, 1747 const struct sys_reg_desc *r) 1748 { 1749 if (p->is_write) { 1750 return ignore_write(vcpu, p); 1751 } else { 1752 u64 dfr = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); 1753 u64 pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1754 u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL3_SHIFT); 1755 1756 p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) | 1757 (((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) | 1758 (((dfr >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) << 20) 1759 | (6 << 16) | (el3 << 14) | (el3 << 12)); 1760 return true; 1761 } 1762 } 1763 1764 static bool trap_debug32(struct kvm_vcpu *vcpu, 1765 struct sys_reg_params *p, 1766 const struct sys_reg_desc *r) 1767 { 1768 if (p->is_write) { 1769 vcpu_cp14(vcpu, r->reg) = p->regval; 1770 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY; 1771 } else { 1772 p->regval = vcpu_cp14(vcpu, r->reg); 1773 } 1774 1775 return true; 1776 } 1777 1778 /* AArch32 debug register mappings 1779 * 1780 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0] 1781 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32] 1782 * 1783 * All control registers and watchpoint value registers are mapped to 1784 * the lower 32 bits of their AArch64 equivalents. We share the trap 1785 * handlers with the above AArch64 code which checks what mode the 1786 * system is in. 1787 */ 1788 1789 static bool trap_xvr(struct kvm_vcpu *vcpu, 1790 struct sys_reg_params *p, 1791 const struct sys_reg_desc *rd) 1792 { 1793 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg]; 1794 1795 if (p->is_write) { 1796 u64 val = *dbg_reg; 1797 1798 val &= 0xffffffffUL; 1799 val |= p->regval << 32; 1800 *dbg_reg = val; 1801 1802 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY; 1803 } else { 1804 p->regval = *dbg_reg >> 32; 1805 } 1806 1807 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg); 1808 1809 return true; 1810 } 1811 1812 #define DBG_BCR_BVR_WCR_WVR(n) \ 1813 /* DBGBVRn */ \ 1814 { Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \ 1815 /* DBGBCRn */ \ 1816 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \ 1817 /* DBGWVRn */ \ 1818 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \ 1819 /* DBGWCRn */ \ 1820 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n } 1821 1822 #define DBGBXVR(n) \ 1823 { Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_xvr, NULL, n } 1824 1825 /* 1826 * Trapped cp14 registers. We generally ignore most of the external 1827 * debug, on the principle that they don't really make sense to a 1828 * guest. Revisit this one day, would this principle change. 1829 */ 1830 static const struct sys_reg_desc cp14_regs[] = { 1831 /* DBGIDR */ 1832 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgidr }, 1833 /* DBGDTRRXext */ 1834 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi }, 1835 1836 DBG_BCR_BVR_WCR_WVR(0), 1837 /* DBGDSCRint */ 1838 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi }, 1839 DBG_BCR_BVR_WCR_WVR(1), 1840 /* DBGDCCINT */ 1841 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug32 }, 1842 /* DBGDSCRext */ 1843 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug32 }, 1844 DBG_BCR_BVR_WCR_WVR(2), 1845 /* DBGDTR[RT]Xint */ 1846 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi }, 1847 /* DBGDTR[RT]Xext */ 1848 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi }, 1849 DBG_BCR_BVR_WCR_WVR(3), 1850 DBG_BCR_BVR_WCR_WVR(4), 1851 DBG_BCR_BVR_WCR_WVR(5), 1852 /* DBGWFAR */ 1853 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi }, 1854 /* DBGOSECCR */ 1855 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi }, 1856 DBG_BCR_BVR_WCR_WVR(6), 1857 /* DBGVCR */ 1858 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug32 }, 1859 DBG_BCR_BVR_WCR_WVR(7), 1860 DBG_BCR_BVR_WCR_WVR(8), 1861 DBG_BCR_BVR_WCR_WVR(9), 1862 DBG_BCR_BVR_WCR_WVR(10), 1863 DBG_BCR_BVR_WCR_WVR(11), 1864 DBG_BCR_BVR_WCR_WVR(12), 1865 DBG_BCR_BVR_WCR_WVR(13), 1866 DBG_BCR_BVR_WCR_WVR(14), 1867 DBG_BCR_BVR_WCR_WVR(15), 1868 1869 /* DBGDRAR (32bit) */ 1870 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi }, 1871 1872 DBGBXVR(0), 1873 /* DBGOSLAR */ 1874 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi }, 1875 DBGBXVR(1), 1876 /* DBGOSLSR */ 1877 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 }, 1878 DBGBXVR(2), 1879 DBGBXVR(3), 1880 /* DBGOSDLR */ 1881 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi }, 1882 DBGBXVR(4), 1883 /* DBGPRCR */ 1884 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi }, 1885 DBGBXVR(5), 1886 DBGBXVR(6), 1887 DBGBXVR(7), 1888 DBGBXVR(8), 1889 DBGBXVR(9), 1890 DBGBXVR(10), 1891 DBGBXVR(11), 1892 DBGBXVR(12), 1893 DBGBXVR(13), 1894 DBGBXVR(14), 1895 DBGBXVR(15), 1896 1897 /* DBGDSAR (32bit) */ 1898 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi }, 1899 1900 /* DBGDEVID2 */ 1901 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi }, 1902 /* DBGDEVID1 */ 1903 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi }, 1904 /* DBGDEVID */ 1905 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi }, 1906 /* DBGCLAIMSET */ 1907 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi }, 1908 /* DBGCLAIMCLR */ 1909 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi }, 1910 /* DBGAUTHSTATUS */ 1911 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 }, 1912 }; 1913 1914 /* Trapped cp14 64bit registers */ 1915 static const struct sys_reg_desc cp14_64_regs[] = { 1916 /* DBGDRAR (64bit) */ 1917 { Op1( 0), CRm( 1), .access = trap_raz_wi }, 1918 1919 /* DBGDSAR (64bit) */ 1920 { Op1( 0), CRm( 2), .access = trap_raz_wi }, 1921 }; 1922 1923 /* Macro to expand the PMEVCNTRn register */ 1924 #define PMU_PMEVCNTR(n) \ 1925 /* PMEVCNTRn */ \ 1926 { Op1(0), CRn(0b1110), \ 1927 CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \ 1928 access_pmu_evcntr } 1929 1930 /* Macro to expand the PMEVTYPERn register */ 1931 #define PMU_PMEVTYPER(n) \ 1932 /* PMEVTYPERn */ \ 1933 { Op1(0), CRn(0b1110), \ 1934 CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \ 1935 access_pmu_evtyper } 1936 1937 /* 1938 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding, 1939 * depending on the way they are accessed (as a 32bit or a 64bit 1940 * register). 1941 */ 1942 static const struct sys_reg_desc cp15_regs[] = { 1943 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr }, 1944 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, c1_SCTLR }, 1945 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 }, 1946 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 }, 1947 { Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR }, 1948 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, c3_DACR }, 1949 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, c5_DFSR }, 1950 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, c5_IFSR }, 1951 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, c5_ADFSR }, 1952 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, c5_AIFSR }, 1953 { Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, c6_DFAR }, 1954 { Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, c6_IFAR }, 1955 1956 /* 1957 * DC{C,I,CI}SW operations: 1958 */ 1959 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw }, 1960 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw }, 1961 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw }, 1962 1963 /* PMU */ 1964 { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr }, 1965 { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcnten }, 1966 { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcnten }, 1967 { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs }, 1968 { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc }, 1969 { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr }, 1970 { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid }, 1971 { Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid }, 1972 { Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_evcntr }, 1973 { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper }, 1974 { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr }, 1975 { Op1( 0), CRn( 9), CRm(14), Op2( 0), access_pmuserenr }, 1976 { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pminten }, 1977 { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pminten }, 1978 { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovs }, 1979 1980 { Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR }, 1981 { Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR }, 1982 { Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, c10_AMAIR0 }, 1983 { Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 }, 1984 1985 /* ICC_SRE */ 1986 { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre }, 1987 1988 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID }, 1989 1990 /* Arch Tmers */ 1991 { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer }, 1992 { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer }, 1993 1994 /* PMEVCNTRn */ 1995 PMU_PMEVCNTR(0), 1996 PMU_PMEVCNTR(1), 1997 PMU_PMEVCNTR(2), 1998 PMU_PMEVCNTR(3), 1999 PMU_PMEVCNTR(4), 2000 PMU_PMEVCNTR(5), 2001 PMU_PMEVCNTR(6), 2002 PMU_PMEVCNTR(7), 2003 PMU_PMEVCNTR(8), 2004 PMU_PMEVCNTR(9), 2005 PMU_PMEVCNTR(10), 2006 PMU_PMEVCNTR(11), 2007 PMU_PMEVCNTR(12), 2008 PMU_PMEVCNTR(13), 2009 PMU_PMEVCNTR(14), 2010 PMU_PMEVCNTR(15), 2011 PMU_PMEVCNTR(16), 2012 PMU_PMEVCNTR(17), 2013 PMU_PMEVCNTR(18), 2014 PMU_PMEVCNTR(19), 2015 PMU_PMEVCNTR(20), 2016 PMU_PMEVCNTR(21), 2017 PMU_PMEVCNTR(22), 2018 PMU_PMEVCNTR(23), 2019 PMU_PMEVCNTR(24), 2020 PMU_PMEVCNTR(25), 2021 PMU_PMEVCNTR(26), 2022 PMU_PMEVCNTR(27), 2023 PMU_PMEVCNTR(28), 2024 PMU_PMEVCNTR(29), 2025 PMU_PMEVCNTR(30), 2026 /* PMEVTYPERn */ 2027 PMU_PMEVTYPER(0), 2028 PMU_PMEVTYPER(1), 2029 PMU_PMEVTYPER(2), 2030 PMU_PMEVTYPER(3), 2031 PMU_PMEVTYPER(4), 2032 PMU_PMEVTYPER(5), 2033 PMU_PMEVTYPER(6), 2034 PMU_PMEVTYPER(7), 2035 PMU_PMEVTYPER(8), 2036 PMU_PMEVTYPER(9), 2037 PMU_PMEVTYPER(10), 2038 PMU_PMEVTYPER(11), 2039 PMU_PMEVTYPER(12), 2040 PMU_PMEVTYPER(13), 2041 PMU_PMEVTYPER(14), 2042 PMU_PMEVTYPER(15), 2043 PMU_PMEVTYPER(16), 2044 PMU_PMEVTYPER(17), 2045 PMU_PMEVTYPER(18), 2046 PMU_PMEVTYPER(19), 2047 PMU_PMEVTYPER(20), 2048 PMU_PMEVTYPER(21), 2049 PMU_PMEVTYPER(22), 2050 PMU_PMEVTYPER(23), 2051 PMU_PMEVTYPER(24), 2052 PMU_PMEVTYPER(25), 2053 PMU_PMEVTYPER(26), 2054 PMU_PMEVTYPER(27), 2055 PMU_PMEVTYPER(28), 2056 PMU_PMEVTYPER(29), 2057 PMU_PMEVTYPER(30), 2058 /* PMCCFILTR */ 2059 { Op1(0), CRn(14), CRm(15), Op2(7), access_pmu_evtyper }, 2060 2061 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr }, 2062 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr }, 2063 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, c0_CSSELR }, 2064 }; 2065 2066 static const struct sys_reg_desc cp15_64_regs[] = { 2067 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR0 }, 2068 { Op1( 0), CRn( 0), CRm( 9), Op2( 0), access_pmu_evcntr }, 2069 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */ 2070 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 }, 2071 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */ 2072 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */ 2073 { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer }, 2074 }; 2075 2076 /* Target specific emulation tables */ 2077 static struct kvm_sys_reg_target_table *target_tables[KVM_ARM_NUM_TARGETS]; 2078 2079 void kvm_register_target_sys_reg_table(unsigned int target, 2080 struct kvm_sys_reg_target_table *table) 2081 { 2082 target_tables[target] = table; 2083 } 2084 2085 /* Get specific register table for this target. */ 2086 static const struct sys_reg_desc *get_target_table(unsigned target, 2087 bool mode_is_64, 2088 size_t *num) 2089 { 2090 struct kvm_sys_reg_target_table *table; 2091 2092 table = target_tables[target]; 2093 if (mode_is_64) { 2094 *num = table->table64.num; 2095 return table->table64.table; 2096 } else { 2097 *num = table->table32.num; 2098 return table->table32.table; 2099 } 2100 } 2101 2102 static int match_sys_reg(const void *key, const void *elt) 2103 { 2104 const unsigned long pval = (unsigned long)key; 2105 const struct sys_reg_desc *r = elt; 2106 2107 return pval - reg_to_encoding(r); 2108 } 2109 2110 static const struct sys_reg_desc *find_reg(const struct sys_reg_params *params, 2111 const struct sys_reg_desc table[], 2112 unsigned int num) 2113 { 2114 unsigned long pval = reg_to_encoding(params); 2115 2116 return bsearch((void *)pval, table, num, sizeof(table[0]), match_sys_reg); 2117 } 2118 2119 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run) 2120 { 2121 kvm_inject_undefined(vcpu); 2122 return 1; 2123 } 2124 2125 static void perform_access(struct kvm_vcpu *vcpu, 2126 struct sys_reg_params *params, 2127 const struct sys_reg_desc *r) 2128 { 2129 trace_kvm_sys_access(*vcpu_pc(vcpu), params, r); 2130 2131 /* Check for regs disabled by runtime config */ 2132 if (sysreg_hidden_from_guest(vcpu, r)) { 2133 kvm_inject_undefined(vcpu); 2134 return; 2135 } 2136 2137 /* 2138 * Not having an accessor means that we have configured a trap 2139 * that we don't know how to handle. This certainly qualifies 2140 * as a gross bug that should be fixed right away. 2141 */ 2142 BUG_ON(!r->access); 2143 2144 /* Skip instruction if instructed so */ 2145 if (likely(r->access(vcpu, params, r))) 2146 kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu)); 2147 } 2148 2149 /* 2150 * emulate_cp -- tries to match a sys_reg access in a handling table, and 2151 * call the corresponding trap handler. 2152 * 2153 * @params: pointer to the descriptor of the access 2154 * @table: array of trap descriptors 2155 * @num: size of the trap descriptor array 2156 * 2157 * Return 0 if the access has been handled, and -1 if not. 2158 */ 2159 static int emulate_cp(struct kvm_vcpu *vcpu, 2160 struct sys_reg_params *params, 2161 const struct sys_reg_desc *table, 2162 size_t num) 2163 { 2164 const struct sys_reg_desc *r; 2165 2166 if (!table) 2167 return -1; /* Not handled */ 2168 2169 r = find_reg(params, table, num); 2170 2171 if (r) { 2172 perform_access(vcpu, params, r); 2173 return 0; 2174 } 2175 2176 /* Not handled */ 2177 return -1; 2178 } 2179 2180 static void unhandled_cp_access(struct kvm_vcpu *vcpu, 2181 struct sys_reg_params *params) 2182 { 2183 u8 hsr_ec = kvm_vcpu_trap_get_class(vcpu); 2184 int cp = -1; 2185 2186 switch(hsr_ec) { 2187 case ESR_ELx_EC_CP15_32: 2188 case ESR_ELx_EC_CP15_64: 2189 cp = 15; 2190 break; 2191 case ESR_ELx_EC_CP14_MR: 2192 case ESR_ELx_EC_CP14_64: 2193 cp = 14; 2194 break; 2195 default: 2196 WARN_ON(1); 2197 } 2198 2199 print_sys_reg_msg(params, 2200 "Unsupported guest CP%d access at: %08lx [%08lx]\n", 2201 cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 2202 kvm_inject_undefined(vcpu); 2203 } 2204 2205 /** 2206 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access 2207 * @vcpu: The VCPU pointer 2208 * @run: The kvm_run struct 2209 */ 2210 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu, 2211 const struct sys_reg_desc *global, 2212 size_t nr_global, 2213 const struct sys_reg_desc *target_specific, 2214 size_t nr_specific) 2215 { 2216 struct sys_reg_params params; 2217 u32 hsr = kvm_vcpu_get_hsr(vcpu); 2218 int Rt = kvm_vcpu_sys_get_rt(vcpu); 2219 int Rt2 = (hsr >> 10) & 0x1f; 2220 2221 params.is_aarch32 = true; 2222 params.is_32bit = false; 2223 params.CRm = (hsr >> 1) & 0xf; 2224 params.is_write = ((hsr & 1) == 0); 2225 2226 params.Op0 = 0; 2227 params.Op1 = (hsr >> 16) & 0xf; 2228 params.Op2 = 0; 2229 params.CRn = 0; 2230 2231 /* 2232 * Make a 64-bit value out of Rt and Rt2. As we use the same trap 2233 * backends between AArch32 and AArch64, we get away with it. 2234 */ 2235 if (params.is_write) { 2236 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff; 2237 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32; 2238 } 2239 2240 /* 2241 * Try to emulate the coprocessor access using the target 2242 * specific table first, and using the global table afterwards. 2243 * If either of the tables contains a handler, handle the 2244 * potential register operation in the case of a read and return 2245 * with success. 2246 */ 2247 if (!emulate_cp(vcpu, ¶ms, target_specific, nr_specific) || 2248 !emulate_cp(vcpu, ¶ms, global, nr_global)) { 2249 /* Split up the value between registers for the read side */ 2250 if (!params.is_write) { 2251 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval)); 2252 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval)); 2253 } 2254 2255 return 1; 2256 } 2257 2258 unhandled_cp_access(vcpu, ¶ms); 2259 return 1; 2260 } 2261 2262 /** 2263 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access 2264 * @vcpu: The VCPU pointer 2265 * @run: The kvm_run struct 2266 */ 2267 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu, 2268 const struct sys_reg_desc *global, 2269 size_t nr_global, 2270 const struct sys_reg_desc *target_specific, 2271 size_t nr_specific) 2272 { 2273 struct sys_reg_params params; 2274 u32 hsr = kvm_vcpu_get_hsr(vcpu); 2275 int Rt = kvm_vcpu_sys_get_rt(vcpu); 2276 2277 params.is_aarch32 = true; 2278 params.is_32bit = true; 2279 params.CRm = (hsr >> 1) & 0xf; 2280 params.regval = vcpu_get_reg(vcpu, Rt); 2281 params.is_write = ((hsr & 1) == 0); 2282 params.CRn = (hsr >> 10) & 0xf; 2283 params.Op0 = 0; 2284 params.Op1 = (hsr >> 14) & 0x7; 2285 params.Op2 = (hsr >> 17) & 0x7; 2286 2287 if (!emulate_cp(vcpu, ¶ms, target_specific, nr_specific) || 2288 !emulate_cp(vcpu, ¶ms, global, nr_global)) { 2289 if (!params.is_write) 2290 vcpu_set_reg(vcpu, Rt, params.regval); 2291 return 1; 2292 } 2293 2294 unhandled_cp_access(vcpu, ¶ms); 2295 return 1; 2296 } 2297 2298 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run) 2299 { 2300 const struct sys_reg_desc *target_specific; 2301 size_t num; 2302 2303 target_specific = get_target_table(vcpu->arch.target, false, &num); 2304 return kvm_handle_cp_64(vcpu, 2305 cp15_64_regs, ARRAY_SIZE(cp15_64_regs), 2306 target_specific, num); 2307 } 2308 2309 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run) 2310 { 2311 const struct sys_reg_desc *target_specific; 2312 size_t num; 2313 2314 target_specific = get_target_table(vcpu->arch.target, false, &num); 2315 return kvm_handle_cp_32(vcpu, 2316 cp15_regs, ARRAY_SIZE(cp15_regs), 2317 target_specific, num); 2318 } 2319 2320 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu, struct kvm_run *run) 2321 { 2322 return kvm_handle_cp_64(vcpu, 2323 cp14_64_regs, ARRAY_SIZE(cp14_64_regs), 2324 NULL, 0); 2325 } 2326 2327 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu, struct kvm_run *run) 2328 { 2329 return kvm_handle_cp_32(vcpu, 2330 cp14_regs, ARRAY_SIZE(cp14_regs), 2331 NULL, 0); 2332 } 2333 2334 static bool is_imp_def_sys_reg(struct sys_reg_params *params) 2335 { 2336 // See ARM DDI 0487E.a, section D12.3.2 2337 return params->Op0 == 3 && (params->CRn & 0b1011) == 0b1011; 2338 } 2339 2340 static int emulate_sys_reg(struct kvm_vcpu *vcpu, 2341 struct sys_reg_params *params) 2342 { 2343 size_t num; 2344 const struct sys_reg_desc *table, *r; 2345 2346 table = get_target_table(vcpu->arch.target, true, &num); 2347 2348 /* Search target-specific then generic table. */ 2349 r = find_reg(params, table, num); 2350 if (!r) 2351 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 2352 2353 if (likely(r)) { 2354 perform_access(vcpu, params, r); 2355 } else if (is_imp_def_sys_reg(params)) { 2356 kvm_inject_undefined(vcpu); 2357 } else { 2358 print_sys_reg_msg(params, 2359 "Unsupported guest sys_reg access at: %lx [%08lx]\n", 2360 *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 2361 kvm_inject_undefined(vcpu); 2362 } 2363 return 1; 2364 } 2365 2366 static void reset_sys_reg_descs(struct kvm_vcpu *vcpu, 2367 const struct sys_reg_desc *table, size_t num, 2368 unsigned long *bmap) 2369 { 2370 unsigned long i; 2371 2372 for (i = 0; i < num; i++) 2373 if (table[i].reset) { 2374 int reg = table[i].reg; 2375 2376 table[i].reset(vcpu, &table[i]); 2377 if (reg > 0 && reg < NR_SYS_REGS) 2378 set_bit(reg, bmap); 2379 } 2380 } 2381 2382 /** 2383 * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access 2384 * @vcpu: The VCPU pointer 2385 * @run: The kvm_run struct 2386 */ 2387 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu, struct kvm_run *run) 2388 { 2389 struct sys_reg_params params; 2390 unsigned long esr = kvm_vcpu_get_hsr(vcpu); 2391 int Rt = kvm_vcpu_sys_get_rt(vcpu); 2392 int ret; 2393 2394 trace_kvm_handle_sys_reg(esr); 2395 2396 params.is_aarch32 = false; 2397 params.is_32bit = false; 2398 params.Op0 = (esr >> 20) & 3; 2399 params.Op1 = (esr >> 14) & 0x7; 2400 params.CRn = (esr >> 10) & 0xf; 2401 params.CRm = (esr >> 1) & 0xf; 2402 params.Op2 = (esr >> 17) & 0x7; 2403 params.regval = vcpu_get_reg(vcpu, Rt); 2404 params.is_write = !(esr & 1); 2405 2406 ret = emulate_sys_reg(vcpu, ¶ms); 2407 2408 if (!params.is_write) 2409 vcpu_set_reg(vcpu, Rt, params.regval); 2410 return ret; 2411 } 2412 2413 /****************************************************************************** 2414 * Userspace API 2415 *****************************************************************************/ 2416 2417 static bool index_to_params(u64 id, struct sys_reg_params *params) 2418 { 2419 switch (id & KVM_REG_SIZE_MASK) { 2420 case KVM_REG_SIZE_U64: 2421 /* Any unused index bits means it's not valid. */ 2422 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK 2423 | KVM_REG_ARM_COPROC_MASK 2424 | KVM_REG_ARM64_SYSREG_OP0_MASK 2425 | KVM_REG_ARM64_SYSREG_OP1_MASK 2426 | KVM_REG_ARM64_SYSREG_CRN_MASK 2427 | KVM_REG_ARM64_SYSREG_CRM_MASK 2428 | KVM_REG_ARM64_SYSREG_OP2_MASK)) 2429 return false; 2430 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK) 2431 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT); 2432 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK) 2433 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT); 2434 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK) 2435 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT); 2436 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK) 2437 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT); 2438 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK) 2439 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT); 2440 return true; 2441 default: 2442 return false; 2443 } 2444 } 2445 2446 const struct sys_reg_desc *find_reg_by_id(u64 id, 2447 struct sys_reg_params *params, 2448 const struct sys_reg_desc table[], 2449 unsigned int num) 2450 { 2451 if (!index_to_params(id, params)) 2452 return NULL; 2453 2454 return find_reg(params, table, num); 2455 } 2456 2457 /* Decode an index value, and find the sys_reg_desc entry. */ 2458 static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu, 2459 u64 id) 2460 { 2461 size_t num; 2462 const struct sys_reg_desc *table, *r; 2463 struct sys_reg_params params; 2464 2465 /* We only do sys_reg for now. */ 2466 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG) 2467 return NULL; 2468 2469 if (!index_to_params(id, ¶ms)) 2470 return NULL; 2471 2472 table = get_target_table(vcpu->arch.target, true, &num); 2473 r = find_reg(¶ms, table, num); 2474 if (!r) 2475 r = find_reg(¶ms, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 2476 2477 /* Not saved in the sys_reg array and not otherwise accessible? */ 2478 if (r && !(r->reg || r->get_user)) 2479 r = NULL; 2480 2481 return r; 2482 } 2483 2484 /* 2485 * These are the invariant sys_reg registers: we let the guest see the 2486 * host versions of these, so they're part of the guest state. 2487 * 2488 * A future CPU may provide a mechanism to present different values to 2489 * the guest, or a future kvm may trap them. 2490 */ 2491 2492 #define FUNCTION_INVARIANT(reg) \ 2493 static void get_##reg(struct kvm_vcpu *v, \ 2494 const struct sys_reg_desc *r) \ 2495 { \ 2496 ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \ 2497 } 2498 2499 FUNCTION_INVARIANT(midr_el1) 2500 FUNCTION_INVARIANT(revidr_el1) 2501 FUNCTION_INVARIANT(clidr_el1) 2502 FUNCTION_INVARIANT(aidr_el1) 2503 2504 static void get_ctr_el0(struct kvm_vcpu *v, const struct sys_reg_desc *r) 2505 { 2506 ((struct sys_reg_desc *)r)->val = read_sanitised_ftr_reg(SYS_CTR_EL0); 2507 } 2508 2509 /* ->val is filled in by kvm_sys_reg_table_init() */ 2510 static struct sys_reg_desc invariant_sys_regs[] = { 2511 { SYS_DESC(SYS_MIDR_EL1), NULL, get_midr_el1 }, 2512 { SYS_DESC(SYS_REVIDR_EL1), NULL, get_revidr_el1 }, 2513 { SYS_DESC(SYS_CLIDR_EL1), NULL, get_clidr_el1 }, 2514 { SYS_DESC(SYS_AIDR_EL1), NULL, get_aidr_el1 }, 2515 { SYS_DESC(SYS_CTR_EL0), NULL, get_ctr_el0 }, 2516 }; 2517 2518 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id) 2519 { 2520 if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0) 2521 return -EFAULT; 2522 return 0; 2523 } 2524 2525 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id) 2526 { 2527 if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0) 2528 return -EFAULT; 2529 return 0; 2530 } 2531 2532 static int get_invariant_sys_reg(u64 id, void __user *uaddr) 2533 { 2534 struct sys_reg_params params; 2535 const struct sys_reg_desc *r; 2536 2537 r = find_reg_by_id(id, ¶ms, invariant_sys_regs, 2538 ARRAY_SIZE(invariant_sys_regs)); 2539 if (!r) 2540 return -ENOENT; 2541 2542 return reg_to_user(uaddr, &r->val, id); 2543 } 2544 2545 static int set_invariant_sys_reg(u64 id, void __user *uaddr) 2546 { 2547 struct sys_reg_params params; 2548 const struct sys_reg_desc *r; 2549 int err; 2550 u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */ 2551 2552 r = find_reg_by_id(id, ¶ms, invariant_sys_regs, 2553 ARRAY_SIZE(invariant_sys_regs)); 2554 if (!r) 2555 return -ENOENT; 2556 2557 err = reg_from_user(&val, uaddr, id); 2558 if (err) 2559 return err; 2560 2561 /* This is what we mean by invariant: you can't change it. */ 2562 if (r->val != val) 2563 return -EINVAL; 2564 2565 return 0; 2566 } 2567 2568 static bool is_valid_cache(u32 val) 2569 { 2570 u32 level, ctype; 2571 2572 if (val >= CSSELR_MAX) 2573 return false; 2574 2575 /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */ 2576 level = (val >> 1); 2577 ctype = (cache_levels >> (level * 3)) & 7; 2578 2579 switch (ctype) { 2580 case 0: /* No cache */ 2581 return false; 2582 case 1: /* Instruction cache only */ 2583 return (val & 1); 2584 case 2: /* Data cache only */ 2585 case 4: /* Unified cache */ 2586 return !(val & 1); 2587 case 3: /* Separate instruction and data caches */ 2588 return true; 2589 default: /* Reserved: we can't know instruction or data. */ 2590 return false; 2591 } 2592 } 2593 2594 static int demux_c15_get(u64 id, void __user *uaddr) 2595 { 2596 u32 val; 2597 u32 __user *uval = uaddr; 2598 2599 /* Fail if we have unknown bits set. */ 2600 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 2601 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 2602 return -ENOENT; 2603 2604 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 2605 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 2606 if (KVM_REG_SIZE(id) != 4) 2607 return -ENOENT; 2608 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 2609 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 2610 if (!is_valid_cache(val)) 2611 return -ENOENT; 2612 2613 return put_user(get_ccsidr(val), uval); 2614 default: 2615 return -ENOENT; 2616 } 2617 } 2618 2619 static int demux_c15_set(u64 id, void __user *uaddr) 2620 { 2621 u32 val, newval; 2622 u32 __user *uval = uaddr; 2623 2624 /* Fail if we have unknown bits set. */ 2625 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 2626 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 2627 return -ENOENT; 2628 2629 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 2630 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 2631 if (KVM_REG_SIZE(id) != 4) 2632 return -ENOENT; 2633 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 2634 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 2635 if (!is_valid_cache(val)) 2636 return -ENOENT; 2637 2638 if (get_user(newval, uval)) 2639 return -EFAULT; 2640 2641 /* This is also invariant: you can't change it. */ 2642 if (newval != get_ccsidr(val)) 2643 return -EINVAL; 2644 return 0; 2645 default: 2646 return -ENOENT; 2647 } 2648 } 2649 2650 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 2651 { 2652 const struct sys_reg_desc *r; 2653 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 2654 2655 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 2656 return demux_c15_get(reg->id, uaddr); 2657 2658 if (KVM_REG_SIZE(reg->id) != sizeof(__u64)) 2659 return -ENOENT; 2660 2661 r = index_to_sys_reg_desc(vcpu, reg->id); 2662 if (!r) 2663 return get_invariant_sys_reg(reg->id, uaddr); 2664 2665 /* Check for regs disabled by runtime config */ 2666 if (sysreg_hidden_from_user(vcpu, r)) 2667 return -ENOENT; 2668 2669 if (r->get_user) 2670 return (r->get_user)(vcpu, r, reg, uaddr); 2671 2672 return reg_to_user(uaddr, &__vcpu_sys_reg(vcpu, r->reg), reg->id); 2673 } 2674 2675 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 2676 { 2677 const struct sys_reg_desc *r; 2678 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 2679 2680 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 2681 return demux_c15_set(reg->id, uaddr); 2682 2683 if (KVM_REG_SIZE(reg->id) != sizeof(__u64)) 2684 return -ENOENT; 2685 2686 r = index_to_sys_reg_desc(vcpu, reg->id); 2687 if (!r) 2688 return set_invariant_sys_reg(reg->id, uaddr); 2689 2690 /* Check for regs disabled by runtime config */ 2691 if (sysreg_hidden_from_user(vcpu, r)) 2692 return -ENOENT; 2693 2694 if (r->set_user) 2695 return (r->set_user)(vcpu, r, reg, uaddr); 2696 2697 return reg_from_user(&__vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id); 2698 } 2699 2700 static unsigned int num_demux_regs(void) 2701 { 2702 unsigned int i, count = 0; 2703 2704 for (i = 0; i < CSSELR_MAX; i++) 2705 if (is_valid_cache(i)) 2706 count++; 2707 2708 return count; 2709 } 2710 2711 static int write_demux_regids(u64 __user *uindices) 2712 { 2713 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX; 2714 unsigned int i; 2715 2716 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR; 2717 for (i = 0; i < CSSELR_MAX; i++) { 2718 if (!is_valid_cache(i)) 2719 continue; 2720 if (put_user(val | i, uindices)) 2721 return -EFAULT; 2722 uindices++; 2723 } 2724 return 0; 2725 } 2726 2727 static u64 sys_reg_to_index(const struct sys_reg_desc *reg) 2728 { 2729 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | 2730 KVM_REG_ARM64_SYSREG | 2731 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) | 2732 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) | 2733 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) | 2734 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) | 2735 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT)); 2736 } 2737 2738 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind) 2739 { 2740 if (!*uind) 2741 return true; 2742 2743 if (put_user(sys_reg_to_index(reg), *uind)) 2744 return false; 2745 2746 (*uind)++; 2747 return true; 2748 } 2749 2750 static int walk_one_sys_reg(const struct kvm_vcpu *vcpu, 2751 const struct sys_reg_desc *rd, 2752 u64 __user **uind, 2753 unsigned int *total) 2754 { 2755 /* 2756 * Ignore registers we trap but don't save, 2757 * and for which no custom user accessor is provided. 2758 */ 2759 if (!(rd->reg || rd->get_user)) 2760 return 0; 2761 2762 if (sysreg_hidden_from_user(vcpu, rd)) 2763 return 0; 2764 2765 if (!copy_reg_to_user(rd, uind)) 2766 return -EFAULT; 2767 2768 (*total)++; 2769 return 0; 2770 } 2771 2772 /* Assumed ordered tables, see kvm_sys_reg_table_init. */ 2773 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind) 2774 { 2775 const struct sys_reg_desc *i1, *i2, *end1, *end2; 2776 unsigned int total = 0; 2777 size_t num; 2778 int err; 2779 2780 /* We check for duplicates here, to allow arch-specific overrides. */ 2781 i1 = get_target_table(vcpu->arch.target, true, &num); 2782 end1 = i1 + num; 2783 i2 = sys_reg_descs; 2784 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs); 2785 2786 BUG_ON(i1 == end1 || i2 == end2); 2787 2788 /* Walk carefully, as both tables may refer to the same register. */ 2789 while (i1 || i2) { 2790 int cmp = cmp_sys_reg(i1, i2); 2791 /* target-specific overrides generic entry. */ 2792 if (cmp <= 0) 2793 err = walk_one_sys_reg(vcpu, i1, &uind, &total); 2794 else 2795 err = walk_one_sys_reg(vcpu, i2, &uind, &total); 2796 2797 if (err) 2798 return err; 2799 2800 if (cmp <= 0 && ++i1 == end1) 2801 i1 = NULL; 2802 if (cmp >= 0 && ++i2 == end2) 2803 i2 = NULL; 2804 } 2805 return total; 2806 } 2807 2808 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu) 2809 { 2810 return ARRAY_SIZE(invariant_sys_regs) 2811 + num_demux_regs() 2812 + walk_sys_regs(vcpu, (u64 __user *)NULL); 2813 } 2814 2815 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) 2816 { 2817 unsigned int i; 2818 int err; 2819 2820 /* Then give them all the invariant registers' indices. */ 2821 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) { 2822 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices)) 2823 return -EFAULT; 2824 uindices++; 2825 } 2826 2827 err = walk_sys_regs(vcpu, uindices); 2828 if (err < 0) 2829 return err; 2830 uindices += err; 2831 2832 return write_demux_regids(uindices); 2833 } 2834 2835 static int check_sysreg_table(const struct sys_reg_desc *table, unsigned int n) 2836 { 2837 unsigned int i; 2838 2839 for (i = 1; i < n; i++) { 2840 if (cmp_sys_reg(&table[i-1], &table[i]) >= 0) { 2841 kvm_err("sys_reg table %p out of order (%d)\n", table, i - 1); 2842 return 1; 2843 } 2844 } 2845 2846 return 0; 2847 } 2848 2849 void kvm_sys_reg_table_init(void) 2850 { 2851 unsigned int i; 2852 struct sys_reg_desc clidr; 2853 2854 /* Make sure tables are unique and in order. */ 2855 BUG_ON(check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs))); 2856 BUG_ON(check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs))); 2857 BUG_ON(check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs))); 2858 BUG_ON(check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs))); 2859 BUG_ON(check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs))); 2860 BUG_ON(check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs))); 2861 2862 /* We abuse the reset function to overwrite the table itself. */ 2863 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) 2864 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]); 2865 2866 /* 2867 * CLIDR format is awkward, so clean it up. See ARM B4.1.20: 2868 * 2869 * If software reads the Cache Type fields from Ctype1 2870 * upwards, once it has seen a value of 0b000, no caches 2871 * exist at further-out levels of the hierarchy. So, for 2872 * example, if Ctype3 is the first Cache Type field with a 2873 * value of 0b000, the values of Ctype4 to Ctype7 must be 2874 * ignored. 2875 */ 2876 get_clidr_el1(NULL, &clidr); /* Ugly... */ 2877 cache_levels = clidr.val; 2878 for (i = 0; i < 7; i++) 2879 if (((cache_levels >> (i*3)) & 7) == 0) 2880 break; 2881 /* Clear all higher bits. */ 2882 cache_levels &= (1 << (i*3))-1; 2883 } 2884 2885 /** 2886 * kvm_reset_sys_regs - sets system registers to reset value 2887 * @vcpu: The VCPU pointer 2888 * 2889 * This function finds the right table above and sets the registers on the 2890 * virtual CPU struct to their architecturally defined reset values. 2891 */ 2892 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu) 2893 { 2894 size_t num; 2895 const struct sys_reg_desc *table; 2896 DECLARE_BITMAP(bmap, NR_SYS_REGS) = { 0, }; 2897 2898 /* Generic chip reset first (so target could override). */ 2899 reset_sys_reg_descs(vcpu, sys_reg_descs, ARRAY_SIZE(sys_reg_descs), bmap); 2900 2901 table = get_target_table(vcpu->arch.target, true, &num); 2902 reset_sys_reg_descs(vcpu, table, num, bmap); 2903 2904 for (num = 1; num < NR_SYS_REGS; num++) { 2905 if (WARN(!test_bit(num, bmap), 2906 "Didn't reset __vcpu_sys_reg(%zi)\n", num)) 2907 break; 2908 } 2909 } 2910