1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/kvm/coproc.c: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Authors: Rusty Russell <rusty@rustcorp.com.au> 9 * Christoffer Dall <c.dall@virtualopensystems.com> 10 */ 11 12 #include <linux/bitfield.h> 13 #include <linux/bsearch.h> 14 #include <linux/kvm_host.h> 15 #include <linux/mm.h> 16 #include <linux/printk.h> 17 #include <linux/uaccess.h> 18 19 #include <asm/cacheflush.h> 20 #include <asm/cputype.h> 21 #include <asm/debug-monitors.h> 22 #include <asm/esr.h> 23 #include <asm/kvm_arm.h> 24 #include <asm/kvm_emulate.h> 25 #include <asm/kvm_hyp.h> 26 #include <asm/kvm_mmu.h> 27 #include <asm/perf_event.h> 28 #include <asm/sysreg.h> 29 30 #include <trace/events/kvm.h> 31 32 #include "sys_regs.h" 33 34 #include "trace.h" 35 36 /* 37 * All of this file is extremely similar to the ARM coproc.c, but the 38 * types are different. My gut feeling is that it should be pretty 39 * easy to merge, but that would be an ABI breakage -- again. VFP 40 * would also need to be abstracted. 41 * 42 * For AArch32, we only take care of what is being trapped. Anything 43 * that has to do with init and userspace access has to go via the 44 * 64bit interface. 45 */ 46 47 static bool read_from_write_only(struct kvm_vcpu *vcpu, 48 struct sys_reg_params *params, 49 const struct sys_reg_desc *r) 50 { 51 WARN_ONCE(1, "Unexpected sys_reg read to write-only register\n"); 52 print_sys_reg_instr(params); 53 kvm_inject_undefined(vcpu); 54 return false; 55 } 56 57 static bool write_to_read_only(struct kvm_vcpu *vcpu, 58 struct sys_reg_params *params, 59 const struct sys_reg_desc *r) 60 { 61 WARN_ONCE(1, "Unexpected sys_reg write to read-only register\n"); 62 print_sys_reg_instr(params); 63 kvm_inject_undefined(vcpu); 64 return false; 65 } 66 67 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg) 68 { 69 u64 val = 0x8badf00d8badf00d; 70 71 if (vcpu->arch.sysregs_loaded_on_cpu && 72 __vcpu_read_sys_reg_from_cpu(reg, &val)) 73 return val; 74 75 return __vcpu_sys_reg(vcpu, reg); 76 } 77 78 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg) 79 { 80 if (vcpu->arch.sysregs_loaded_on_cpu && 81 __vcpu_write_sys_reg_to_cpu(val, reg)) 82 return; 83 84 __vcpu_sys_reg(vcpu, reg) = val; 85 } 86 87 /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */ 88 static u32 cache_levels; 89 90 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */ 91 #define CSSELR_MAX 14 92 93 /* Which cache CCSIDR represents depends on CSSELR value. */ 94 static u32 get_ccsidr(u32 csselr) 95 { 96 u32 ccsidr; 97 98 /* Make sure noone else changes CSSELR during this! */ 99 local_irq_disable(); 100 write_sysreg(csselr, csselr_el1); 101 isb(); 102 ccsidr = read_sysreg(ccsidr_el1); 103 local_irq_enable(); 104 105 return ccsidr; 106 } 107 108 /* 109 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized). 110 */ 111 static bool access_dcsw(struct kvm_vcpu *vcpu, 112 struct sys_reg_params *p, 113 const struct sys_reg_desc *r) 114 { 115 if (!p->is_write) 116 return read_from_write_only(vcpu, p, r); 117 118 /* 119 * Only track S/W ops if we don't have FWB. It still indicates 120 * that the guest is a bit broken (S/W operations should only 121 * be done by firmware, knowing that there is only a single 122 * CPU left in the system, and certainly not from non-secure 123 * software). 124 */ 125 if (!cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) 126 kvm_set_way_flush(vcpu); 127 128 return true; 129 } 130 131 static void get_access_mask(const struct sys_reg_desc *r, u64 *mask, u64 *shift) 132 { 133 switch (r->aarch32_map) { 134 case AA32_LO: 135 *mask = GENMASK_ULL(31, 0); 136 *shift = 0; 137 break; 138 case AA32_HI: 139 *mask = GENMASK_ULL(63, 32); 140 *shift = 32; 141 break; 142 default: 143 *mask = GENMASK_ULL(63, 0); 144 *shift = 0; 145 break; 146 } 147 } 148 149 /* 150 * Generic accessor for VM registers. Only called as long as HCR_TVM 151 * is set. If the guest enables the MMU, we stop trapping the VM 152 * sys_regs and leave it in complete control of the caches. 153 */ 154 static bool access_vm_reg(struct kvm_vcpu *vcpu, 155 struct sys_reg_params *p, 156 const struct sys_reg_desc *r) 157 { 158 bool was_enabled = vcpu_has_cache_enabled(vcpu); 159 u64 val, mask, shift; 160 161 BUG_ON(!p->is_write); 162 163 get_access_mask(r, &mask, &shift); 164 165 if (~mask) { 166 val = vcpu_read_sys_reg(vcpu, r->reg); 167 val &= ~mask; 168 } else { 169 val = 0; 170 } 171 172 val |= (p->regval & (mask >> shift)) << shift; 173 vcpu_write_sys_reg(vcpu, val, r->reg); 174 175 kvm_toggle_cache(vcpu, was_enabled); 176 return true; 177 } 178 179 static bool access_actlr(struct kvm_vcpu *vcpu, 180 struct sys_reg_params *p, 181 const struct sys_reg_desc *r) 182 { 183 u64 mask, shift; 184 185 if (p->is_write) 186 return ignore_write(vcpu, p); 187 188 get_access_mask(r, &mask, &shift); 189 p->regval = (vcpu_read_sys_reg(vcpu, r->reg) & mask) >> shift; 190 191 return true; 192 } 193 194 /* 195 * Trap handler for the GICv3 SGI generation system register. 196 * Forward the request to the VGIC emulation. 197 * The cp15_64 code makes sure this automatically works 198 * for both AArch64 and AArch32 accesses. 199 */ 200 static bool access_gic_sgi(struct kvm_vcpu *vcpu, 201 struct sys_reg_params *p, 202 const struct sys_reg_desc *r) 203 { 204 bool g1; 205 206 if (!p->is_write) 207 return read_from_write_only(vcpu, p, r); 208 209 /* 210 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates 211 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group, 212 * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively 213 * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure 214 * group. 215 */ 216 if (p->Op0 == 0) { /* AArch32 */ 217 switch (p->Op1) { 218 default: /* Keep GCC quiet */ 219 case 0: /* ICC_SGI1R */ 220 g1 = true; 221 break; 222 case 1: /* ICC_ASGI1R */ 223 case 2: /* ICC_SGI0R */ 224 g1 = false; 225 break; 226 } 227 } else { /* AArch64 */ 228 switch (p->Op2) { 229 default: /* Keep GCC quiet */ 230 case 5: /* ICC_SGI1R_EL1 */ 231 g1 = true; 232 break; 233 case 6: /* ICC_ASGI1R_EL1 */ 234 case 7: /* ICC_SGI0R_EL1 */ 235 g1 = false; 236 break; 237 } 238 } 239 240 vgic_v3_dispatch_sgi(vcpu, p->regval, g1); 241 242 return true; 243 } 244 245 static bool access_gic_sre(struct kvm_vcpu *vcpu, 246 struct sys_reg_params *p, 247 const struct sys_reg_desc *r) 248 { 249 if (p->is_write) 250 return ignore_write(vcpu, p); 251 252 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre; 253 return true; 254 } 255 256 static bool trap_raz_wi(struct kvm_vcpu *vcpu, 257 struct sys_reg_params *p, 258 const struct sys_reg_desc *r) 259 { 260 if (p->is_write) 261 return ignore_write(vcpu, p); 262 else 263 return read_zero(vcpu, p); 264 } 265 266 /* 267 * ARMv8.1 mandates at least a trivial LORegion implementation, where all the 268 * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0 269 * system, these registers should UNDEF. LORID_EL1 being a RO register, we 270 * treat it separately. 271 */ 272 static bool trap_loregion(struct kvm_vcpu *vcpu, 273 struct sys_reg_params *p, 274 const struct sys_reg_desc *r) 275 { 276 u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 277 u32 sr = reg_to_encoding(r); 278 279 if (!(val & (0xfUL << ID_AA64MMFR1_LOR_SHIFT))) { 280 kvm_inject_undefined(vcpu); 281 return false; 282 } 283 284 if (p->is_write && sr == SYS_LORID_EL1) 285 return write_to_read_only(vcpu, p, r); 286 287 return trap_raz_wi(vcpu, p, r); 288 } 289 290 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu, 291 struct sys_reg_params *p, 292 const struct sys_reg_desc *r) 293 { 294 if (p->is_write) { 295 return ignore_write(vcpu, p); 296 } else { 297 p->regval = (1 << 3); 298 return true; 299 } 300 } 301 302 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu, 303 struct sys_reg_params *p, 304 const struct sys_reg_desc *r) 305 { 306 if (p->is_write) { 307 return ignore_write(vcpu, p); 308 } else { 309 p->regval = read_sysreg(dbgauthstatus_el1); 310 return true; 311 } 312 } 313 314 /* 315 * We want to avoid world-switching all the DBG registers all the 316 * time: 317 * 318 * - If we've touched any debug register, it is likely that we're 319 * going to touch more of them. It then makes sense to disable the 320 * traps and start doing the save/restore dance 321 * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is 322 * then mandatory to save/restore the registers, as the guest 323 * depends on them. 324 * 325 * For this, we use a DIRTY bit, indicating the guest has modified the 326 * debug registers, used as follow: 327 * 328 * On guest entry: 329 * - If the dirty bit is set (because we're coming back from trapping), 330 * disable the traps, save host registers, restore guest registers. 331 * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), 332 * set the dirty bit, disable the traps, save host registers, 333 * restore guest registers. 334 * - Otherwise, enable the traps 335 * 336 * On guest exit: 337 * - If the dirty bit is set, save guest registers, restore host 338 * registers and clear the dirty bit. This ensure that the host can 339 * now use the debug registers. 340 */ 341 static bool trap_debug_regs(struct kvm_vcpu *vcpu, 342 struct sys_reg_params *p, 343 const struct sys_reg_desc *r) 344 { 345 if (p->is_write) { 346 vcpu_write_sys_reg(vcpu, p->regval, r->reg); 347 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY; 348 } else { 349 p->regval = vcpu_read_sys_reg(vcpu, r->reg); 350 } 351 352 trace_trap_reg(__func__, r->reg, p->is_write, p->regval); 353 354 return true; 355 } 356 357 /* 358 * reg_to_dbg/dbg_to_reg 359 * 360 * A 32 bit write to a debug register leave top bits alone 361 * A 32 bit read from a debug register only returns the bottom bits 362 * 363 * All writes will set the KVM_ARM64_DEBUG_DIRTY flag to ensure the 364 * hyp.S code switches between host and guest values in future. 365 */ 366 static void reg_to_dbg(struct kvm_vcpu *vcpu, 367 struct sys_reg_params *p, 368 const struct sys_reg_desc *rd, 369 u64 *dbg_reg) 370 { 371 u64 mask, shift, val; 372 373 get_access_mask(rd, &mask, &shift); 374 375 val = *dbg_reg; 376 val &= ~mask; 377 val |= (p->regval & (mask >> shift)) << shift; 378 *dbg_reg = val; 379 380 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY; 381 } 382 383 static void dbg_to_reg(struct kvm_vcpu *vcpu, 384 struct sys_reg_params *p, 385 const struct sys_reg_desc *rd, 386 u64 *dbg_reg) 387 { 388 u64 mask, shift; 389 390 get_access_mask(rd, &mask, &shift); 391 p->regval = (*dbg_reg & mask) >> shift; 392 } 393 394 static bool trap_bvr(struct kvm_vcpu *vcpu, 395 struct sys_reg_params *p, 396 const struct sys_reg_desc *rd) 397 { 398 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm]; 399 400 if (p->is_write) 401 reg_to_dbg(vcpu, p, rd, dbg_reg); 402 else 403 dbg_to_reg(vcpu, p, rd, dbg_reg); 404 405 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); 406 407 return true; 408 } 409 410 static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 411 const struct kvm_one_reg *reg, void __user *uaddr) 412 { 413 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm]; 414 415 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) 416 return -EFAULT; 417 return 0; 418 } 419 420 static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 421 const struct kvm_one_reg *reg, void __user *uaddr) 422 { 423 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm]; 424 425 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) 426 return -EFAULT; 427 return 0; 428 } 429 430 static void reset_bvr(struct kvm_vcpu *vcpu, 431 const struct sys_reg_desc *rd) 432 { 433 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = rd->val; 434 } 435 436 static bool trap_bcr(struct kvm_vcpu *vcpu, 437 struct sys_reg_params *p, 438 const struct sys_reg_desc *rd) 439 { 440 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm]; 441 442 if (p->is_write) 443 reg_to_dbg(vcpu, p, rd, dbg_reg); 444 else 445 dbg_to_reg(vcpu, p, rd, dbg_reg); 446 447 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); 448 449 return true; 450 } 451 452 static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 453 const struct kvm_one_reg *reg, void __user *uaddr) 454 { 455 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm]; 456 457 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) 458 return -EFAULT; 459 460 return 0; 461 } 462 463 static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 464 const struct kvm_one_reg *reg, void __user *uaddr) 465 { 466 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm]; 467 468 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) 469 return -EFAULT; 470 return 0; 471 } 472 473 static void reset_bcr(struct kvm_vcpu *vcpu, 474 const struct sys_reg_desc *rd) 475 { 476 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = rd->val; 477 } 478 479 static bool trap_wvr(struct kvm_vcpu *vcpu, 480 struct sys_reg_params *p, 481 const struct sys_reg_desc *rd) 482 { 483 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]; 484 485 if (p->is_write) 486 reg_to_dbg(vcpu, p, rd, dbg_reg); 487 else 488 dbg_to_reg(vcpu, p, rd, dbg_reg); 489 490 trace_trap_reg(__func__, rd->CRm, p->is_write, 491 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]); 492 493 return true; 494 } 495 496 static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 497 const struct kvm_one_reg *reg, void __user *uaddr) 498 { 499 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]; 500 501 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) 502 return -EFAULT; 503 return 0; 504 } 505 506 static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 507 const struct kvm_one_reg *reg, void __user *uaddr) 508 { 509 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]; 510 511 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) 512 return -EFAULT; 513 return 0; 514 } 515 516 static void reset_wvr(struct kvm_vcpu *vcpu, 517 const struct sys_reg_desc *rd) 518 { 519 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = rd->val; 520 } 521 522 static bool trap_wcr(struct kvm_vcpu *vcpu, 523 struct sys_reg_params *p, 524 const struct sys_reg_desc *rd) 525 { 526 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm]; 527 528 if (p->is_write) 529 reg_to_dbg(vcpu, p, rd, dbg_reg); 530 else 531 dbg_to_reg(vcpu, p, rd, dbg_reg); 532 533 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); 534 535 return true; 536 } 537 538 static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 539 const struct kvm_one_reg *reg, void __user *uaddr) 540 { 541 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm]; 542 543 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) 544 return -EFAULT; 545 return 0; 546 } 547 548 static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 549 const struct kvm_one_reg *reg, void __user *uaddr) 550 { 551 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm]; 552 553 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) 554 return -EFAULT; 555 return 0; 556 } 557 558 static void reset_wcr(struct kvm_vcpu *vcpu, 559 const struct sys_reg_desc *rd) 560 { 561 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = rd->val; 562 } 563 564 static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 565 { 566 u64 amair = read_sysreg(amair_el1); 567 vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1); 568 } 569 570 static void reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 571 { 572 u64 actlr = read_sysreg(actlr_el1); 573 vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1); 574 } 575 576 static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 577 { 578 u64 mpidr; 579 580 /* 581 * Map the vcpu_id into the first three affinity level fields of 582 * the MPIDR. We limit the number of VCPUs in level 0 due to a 583 * limitation to 16 CPUs in that level in the ICC_SGIxR registers 584 * of the GICv3 to be able to address each CPU directly when 585 * sending IPIs. 586 */ 587 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0); 588 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1); 589 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2); 590 vcpu_write_sys_reg(vcpu, (1ULL << 31) | mpidr, MPIDR_EL1); 591 } 592 593 static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu, 594 const struct sys_reg_desc *r) 595 { 596 if (kvm_vcpu_has_pmu(vcpu)) 597 return 0; 598 599 return REG_HIDDEN; 600 } 601 602 static void reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 603 { 604 u64 n, mask = BIT(ARMV8_PMU_CYCLE_IDX); 605 606 /* No PMU available, any PMU reg may UNDEF... */ 607 if (!kvm_arm_support_pmu_v3()) 608 return; 609 610 n = read_sysreg(pmcr_el0) >> ARMV8_PMU_PMCR_N_SHIFT; 611 n &= ARMV8_PMU_PMCR_N_MASK; 612 if (n) 613 mask |= GENMASK(n - 1, 0); 614 615 reset_unknown(vcpu, r); 616 __vcpu_sys_reg(vcpu, r->reg) &= mask; 617 } 618 619 static void reset_pmevcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 620 { 621 reset_unknown(vcpu, r); 622 __vcpu_sys_reg(vcpu, r->reg) &= GENMASK(31, 0); 623 } 624 625 static void reset_pmevtyper(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 626 { 627 reset_unknown(vcpu, r); 628 __vcpu_sys_reg(vcpu, r->reg) &= ARMV8_PMU_EVTYPE_MASK; 629 } 630 631 static void reset_pmselr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 632 { 633 reset_unknown(vcpu, r); 634 __vcpu_sys_reg(vcpu, r->reg) &= ARMV8_PMU_COUNTER_MASK; 635 } 636 637 static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 638 { 639 u64 pmcr, val; 640 641 /* No PMU available, PMCR_EL0 may UNDEF... */ 642 if (!kvm_arm_support_pmu_v3()) 643 return; 644 645 pmcr = read_sysreg(pmcr_el0); 646 /* 647 * Writable bits of PMCR_EL0 (ARMV8_PMU_PMCR_MASK) are reset to UNKNOWN 648 * except PMCR.E resetting to zero. 649 */ 650 val = ((pmcr & ~ARMV8_PMU_PMCR_MASK) 651 | (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E); 652 if (!system_supports_32bit_el0()) 653 val |= ARMV8_PMU_PMCR_LC; 654 __vcpu_sys_reg(vcpu, r->reg) = val; 655 } 656 657 static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags) 658 { 659 u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0); 660 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu); 661 662 if (!enabled) 663 kvm_inject_undefined(vcpu); 664 665 return !enabled; 666 } 667 668 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu) 669 { 670 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN); 671 } 672 673 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu) 674 { 675 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN); 676 } 677 678 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu) 679 { 680 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN); 681 } 682 683 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu) 684 { 685 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN); 686 } 687 688 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 689 const struct sys_reg_desc *r) 690 { 691 u64 val; 692 693 if (pmu_access_el0_disabled(vcpu)) 694 return false; 695 696 if (p->is_write) { 697 /* Only update writeable bits of PMCR */ 698 val = __vcpu_sys_reg(vcpu, PMCR_EL0); 699 val &= ~ARMV8_PMU_PMCR_MASK; 700 val |= p->regval & ARMV8_PMU_PMCR_MASK; 701 if (!system_supports_32bit_el0()) 702 val |= ARMV8_PMU_PMCR_LC; 703 __vcpu_sys_reg(vcpu, PMCR_EL0) = val; 704 kvm_pmu_handle_pmcr(vcpu, val); 705 kvm_vcpu_pmu_restore_guest(vcpu); 706 } else { 707 /* PMCR.P & PMCR.C are RAZ */ 708 val = __vcpu_sys_reg(vcpu, PMCR_EL0) 709 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C); 710 p->regval = val; 711 } 712 713 return true; 714 } 715 716 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 717 const struct sys_reg_desc *r) 718 { 719 if (pmu_access_event_counter_el0_disabled(vcpu)) 720 return false; 721 722 if (p->is_write) 723 __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval; 724 else 725 /* return PMSELR.SEL field */ 726 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0) 727 & ARMV8_PMU_COUNTER_MASK; 728 729 return true; 730 } 731 732 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 733 const struct sys_reg_desc *r) 734 { 735 u64 pmceid, mask, shift; 736 737 BUG_ON(p->is_write); 738 739 if (pmu_access_el0_disabled(vcpu)) 740 return false; 741 742 get_access_mask(r, &mask, &shift); 743 744 pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1)); 745 pmceid &= mask; 746 pmceid >>= shift; 747 748 p->regval = pmceid; 749 750 return true; 751 } 752 753 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx) 754 { 755 u64 pmcr, val; 756 757 pmcr = __vcpu_sys_reg(vcpu, PMCR_EL0); 758 val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK; 759 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) { 760 kvm_inject_undefined(vcpu); 761 return false; 762 } 763 764 return true; 765 } 766 767 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu, 768 struct sys_reg_params *p, 769 const struct sys_reg_desc *r) 770 { 771 u64 idx = ~0UL; 772 773 if (r->CRn == 9 && r->CRm == 13) { 774 if (r->Op2 == 2) { 775 /* PMXEVCNTR_EL0 */ 776 if (pmu_access_event_counter_el0_disabled(vcpu)) 777 return false; 778 779 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) 780 & ARMV8_PMU_COUNTER_MASK; 781 } else if (r->Op2 == 0) { 782 /* PMCCNTR_EL0 */ 783 if (pmu_access_cycle_counter_el0_disabled(vcpu)) 784 return false; 785 786 idx = ARMV8_PMU_CYCLE_IDX; 787 } 788 } else if (r->CRn == 0 && r->CRm == 9) { 789 /* PMCCNTR */ 790 if (pmu_access_event_counter_el0_disabled(vcpu)) 791 return false; 792 793 idx = ARMV8_PMU_CYCLE_IDX; 794 } else if (r->CRn == 14 && (r->CRm & 12) == 8) { 795 /* PMEVCNTRn_EL0 */ 796 if (pmu_access_event_counter_el0_disabled(vcpu)) 797 return false; 798 799 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 800 } 801 802 /* Catch any decoding mistake */ 803 WARN_ON(idx == ~0UL); 804 805 if (!pmu_counter_idx_valid(vcpu, idx)) 806 return false; 807 808 if (p->is_write) { 809 if (pmu_access_el0_disabled(vcpu)) 810 return false; 811 812 kvm_pmu_set_counter_value(vcpu, idx, p->regval); 813 } else { 814 p->regval = kvm_pmu_get_counter_value(vcpu, idx); 815 } 816 817 return true; 818 } 819 820 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 821 const struct sys_reg_desc *r) 822 { 823 u64 idx, reg; 824 825 if (pmu_access_el0_disabled(vcpu)) 826 return false; 827 828 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) { 829 /* PMXEVTYPER_EL0 */ 830 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK; 831 reg = PMEVTYPER0_EL0 + idx; 832 } else if (r->CRn == 14 && (r->CRm & 12) == 12) { 833 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 834 if (idx == ARMV8_PMU_CYCLE_IDX) 835 reg = PMCCFILTR_EL0; 836 else 837 /* PMEVTYPERn_EL0 */ 838 reg = PMEVTYPER0_EL0 + idx; 839 } else { 840 BUG(); 841 } 842 843 if (!pmu_counter_idx_valid(vcpu, idx)) 844 return false; 845 846 if (p->is_write) { 847 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx); 848 __vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK; 849 kvm_vcpu_pmu_restore_guest(vcpu); 850 } else { 851 p->regval = __vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK; 852 } 853 854 return true; 855 } 856 857 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 858 const struct sys_reg_desc *r) 859 { 860 u64 val, mask; 861 862 if (pmu_access_el0_disabled(vcpu)) 863 return false; 864 865 mask = kvm_pmu_valid_counter_mask(vcpu); 866 if (p->is_write) { 867 val = p->regval & mask; 868 if (r->Op2 & 0x1) { 869 /* accessing PMCNTENSET_EL0 */ 870 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val; 871 kvm_pmu_enable_counter_mask(vcpu, val); 872 kvm_vcpu_pmu_restore_guest(vcpu); 873 } else { 874 /* accessing PMCNTENCLR_EL0 */ 875 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val; 876 kvm_pmu_disable_counter_mask(vcpu, val); 877 } 878 } else { 879 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0); 880 } 881 882 return true; 883 } 884 885 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 886 const struct sys_reg_desc *r) 887 { 888 u64 mask = kvm_pmu_valid_counter_mask(vcpu); 889 890 if (check_pmu_access_disabled(vcpu, 0)) 891 return false; 892 893 if (p->is_write) { 894 u64 val = p->regval & mask; 895 896 if (r->Op2 & 0x1) 897 /* accessing PMINTENSET_EL1 */ 898 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val; 899 else 900 /* accessing PMINTENCLR_EL1 */ 901 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val; 902 } else { 903 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1); 904 } 905 906 return true; 907 } 908 909 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 910 const struct sys_reg_desc *r) 911 { 912 u64 mask = kvm_pmu_valid_counter_mask(vcpu); 913 914 if (pmu_access_el0_disabled(vcpu)) 915 return false; 916 917 if (p->is_write) { 918 if (r->CRm & 0x2) 919 /* accessing PMOVSSET_EL0 */ 920 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask); 921 else 922 /* accessing PMOVSCLR_EL0 */ 923 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask); 924 } else { 925 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0); 926 } 927 928 return true; 929 } 930 931 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 932 const struct sys_reg_desc *r) 933 { 934 u64 mask; 935 936 if (!p->is_write) 937 return read_from_write_only(vcpu, p, r); 938 939 if (pmu_write_swinc_el0_disabled(vcpu)) 940 return false; 941 942 mask = kvm_pmu_valid_counter_mask(vcpu); 943 kvm_pmu_software_increment(vcpu, p->regval & mask); 944 return true; 945 } 946 947 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 948 const struct sys_reg_desc *r) 949 { 950 if (p->is_write) { 951 if (!vcpu_mode_priv(vcpu)) { 952 kvm_inject_undefined(vcpu); 953 return false; 954 } 955 956 __vcpu_sys_reg(vcpu, PMUSERENR_EL0) = 957 p->regval & ARMV8_PMU_USERENR_MASK; 958 } else { 959 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0) 960 & ARMV8_PMU_USERENR_MASK; 961 } 962 963 return true; 964 } 965 966 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */ 967 #define DBG_BCR_BVR_WCR_WVR_EL1(n) \ 968 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \ 969 trap_bvr, reset_bvr, 0, 0, get_bvr, set_bvr }, \ 970 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \ 971 trap_bcr, reset_bcr, 0, 0, get_bcr, set_bcr }, \ 972 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \ 973 trap_wvr, reset_wvr, 0, 0, get_wvr, set_wvr }, \ 974 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \ 975 trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr } 976 977 #define PMU_SYS_REG(r) \ 978 SYS_DESC(r), .reset = reset_pmu_reg, .visibility = pmu_visibility 979 980 /* Macro to expand the PMEVCNTRn_EL0 register */ 981 #define PMU_PMEVCNTR_EL0(n) \ 982 { PMU_SYS_REG(SYS_PMEVCNTRn_EL0(n)), \ 983 .reset = reset_pmevcntr, \ 984 .access = access_pmu_evcntr, .reg = (PMEVCNTR0_EL0 + n), } 985 986 /* Macro to expand the PMEVTYPERn_EL0 register */ 987 #define PMU_PMEVTYPER_EL0(n) \ 988 { PMU_SYS_REG(SYS_PMEVTYPERn_EL0(n)), \ 989 .reset = reset_pmevtyper, \ 990 .access = access_pmu_evtyper, .reg = (PMEVTYPER0_EL0 + n), } 991 992 static bool undef_access(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 993 const struct sys_reg_desc *r) 994 { 995 kvm_inject_undefined(vcpu); 996 997 return false; 998 } 999 1000 /* Macro to expand the AMU counter and type registers*/ 1001 #define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), undef_access } 1002 #define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), undef_access } 1003 #define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), undef_access } 1004 #define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), undef_access } 1005 1006 static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu, 1007 const struct sys_reg_desc *rd) 1008 { 1009 return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN; 1010 } 1011 1012 /* 1013 * If we land here on a PtrAuth access, that is because we didn't 1014 * fixup the access on exit by allowing the PtrAuth sysregs. The only 1015 * way this happens is when the guest does not have PtrAuth support 1016 * enabled. 1017 */ 1018 #define __PTRAUTH_KEY(k) \ 1019 { SYS_DESC(SYS_## k), undef_access, reset_unknown, k, \ 1020 .visibility = ptrauth_visibility} 1021 1022 #define PTRAUTH_KEY(k) \ 1023 __PTRAUTH_KEY(k ## KEYLO_EL1), \ 1024 __PTRAUTH_KEY(k ## KEYHI_EL1) 1025 1026 static bool access_arch_timer(struct kvm_vcpu *vcpu, 1027 struct sys_reg_params *p, 1028 const struct sys_reg_desc *r) 1029 { 1030 enum kvm_arch_timers tmr; 1031 enum kvm_arch_timer_regs treg; 1032 u64 reg = reg_to_encoding(r); 1033 1034 switch (reg) { 1035 case SYS_CNTP_TVAL_EL0: 1036 case SYS_AARCH32_CNTP_TVAL: 1037 tmr = TIMER_PTIMER; 1038 treg = TIMER_REG_TVAL; 1039 break; 1040 case SYS_CNTP_CTL_EL0: 1041 case SYS_AARCH32_CNTP_CTL: 1042 tmr = TIMER_PTIMER; 1043 treg = TIMER_REG_CTL; 1044 break; 1045 case SYS_CNTP_CVAL_EL0: 1046 case SYS_AARCH32_CNTP_CVAL: 1047 tmr = TIMER_PTIMER; 1048 treg = TIMER_REG_CVAL; 1049 break; 1050 default: 1051 BUG(); 1052 } 1053 1054 if (p->is_write) 1055 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval); 1056 else 1057 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg); 1058 1059 return true; 1060 } 1061 1062 /* Read a sanitised cpufeature ID register by sys_reg_desc */ 1063 static u64 read_id_reg(const struct kvm_vcpu *vcpu, 1064 struct sys_reg_desc const *r, bool raz) 1065 { 1066 u32 id = reg_to_encoding(r); 1067 u64 val; 1068 1069 if (raz) 1070 return 0; 1071 1072 val = read_sanitised_ftr_reg(id); 1073 1074 switch (id) { 1075 case SYS_ID_AA64PFR0_EL1: 1076 if (!vcpu_has_sve(vcpu)) 1077 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_SVE); 1078 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_AMU); 1079 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_CSV2); 1080 val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_CSV2), (u64)vcpu->kvm->arch.pfr0_csv2); 1081 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_CSV3); 1082 val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_CSV3), (u64)vcpu->kvm->arch.pfr0_csv3); 1083 if (irqchip_in_kernel(vcpu->kvm) && 1084 vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) { 1085 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_GIC); 1086 val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_GIC), 1); 1087 } 1088 break; 1089 case SYS_ID_AA64PFR1_EL1: 1090 if (!kvm_has_mte(vcpu->kvm)) 1091 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_MTE); 1092 break; 1093 case SYS_ID_AA64ISAR1_EL1: 1094 if (!vcpu_has_ptrauth(vcpu)) 1095 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_APA) | 1096 ARM64_FEATURE_MASK(ID_AA64ISAR1_API) | 1097 ARM64_FEATURE_MASK(ID_AA64ISAR1_GPA) | 1098 ARM64_FEATURE_MASK(ID_AA64ISAR1_GPI)); 1099 break; 1100 case SYS_ID_AA64ISAR2_EL1: 1101 if (!vcpu_has_ptrauth(vcpu)) 1102 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_APA3) | 1103 ARM64_FEATURE_MASK(ID_AA64ISAR2_GPA3)); 1104 break; 1105 case SYS_ID_AA64DFR0_EL1: 1106 /* Limit debug to ARMv8.0 */ 1107 val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_DEBUGVER); 1108 val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_DEBUGVER), 6); 1109 /* Limit guests to PMUv3 for ARMv8.4 */ 1110 val = cpuid_feature_cap_perfmon_field(val, 1111 ID_AA64DFR0_PMUVER_SHIFT, 1112 kvm_vcpu_has_pmu(vcpu) ? ID_AA64DFR0_PMUVER_8_4 : 0); 1113 /* Hide SPE from guests */ 1114 val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_PMSVER); 1115 break; 1116 case SYS_ID_DFR0_EL1: 1117 /* Limit guests to PMUv3 for ARMv8.4 */ 1118 val = cpuid_feature_cap_perfmon_field(val, 1119 ID_DFR0_PERFMON_SHIFT, 1120 kvm_vcpu_has_pmu(vcpu) ? ID_DFR0_PERFMON_8_4 : 0); 1121 break; 1122 } 1123 1124 return val; 1125 } 1126 1127 static unsigned int id_visibility(const struct kvm_vcpu *vcpu, 1128 const struct sys_reg_desc *r) 1129 { 1130 u32 id = reg_to_encoding(r); 1131 1132 switch (id) { 1133 case SYS_ID_AA64ZFR0_EL1: 1134 if (!vcpu_has_sve(vcpu)) 1135 return REG_RAZ; 1136 break; 1137 } 1138 1139 return 0; 1140 } 1141 1142 /* cpufeature ID register access trap handlers */ 1143 1144 static bool __access_id_reg(struct kvm_vcpu *vcpu, 1145 struct sys_reg_params *p, 1146 const struct sys_reg_desc *r, 1147 bool raz) 1148 { 1149 if (p->is_write) 1150 return write_to_read_only(vcpu, p, r); 1151 1152 p->regval = read_id_reg(vcpu, r, raz); 1153 return true; 1154 } 1155 1156 static bool access_id_reg(struct kvm_vcpu *vcpu, 1157 struct sys_reg_params *p, 1158 const struct sys_reg_desc *r) 1159 { 1160 bool raz = sysreg_visible_as_raz(vcpu, r); 1161 1162 return __access_id_reg(vcpu, p, r, raz); 1163 } 1164 1165 static bool access_raz_id_reg(struct kvm_vcpu *vcpu, 1166 struct sys_reg_params *p, 1167 const struct sys_reg_desc *r) 1168 { 1169 return __access_id_reg(vcpu, p, r, true); 1170 } 1171 1172 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id); 1173 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id); 1174 static u64 sys_reg_to_index(const struct sys_reg_desc *reg); 1175 1176 /* Visibility overrides for SVE-specific control registers */ 1177 static unsigned int sve_visibility(const struct kvm_vcpu *vcpu, 1178 const struct sys_reg_desc *rd) 1179 { 1180 if (vcpu_has_sve(vcpu)) 1181 return 0; 1182 1183 return REG_HIDDEN; 1184 } 1185 1186 static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, 1187 const struct sys_reg_desc *rd, 1188 const struct kvm_one_reg *reg, void __user *uaddr) 1189 { 1190 const u64 id = sys_reg_to_index(rd); 1191 u8 csv2, csv3; 1192 int err; 1193 u64 val; 1194 1195 err = reg_from_user(&val, uaddr, id); 1196 if (err) 1197 return err; 1198 1199 /* 1200 * Allow AA64PFR0_EL1.CSV2 to be set from userspace as long as 1201 * it doesn't promise more than what is actually provided (the 1202 * guest could otherwise be covered in ectoplasmic residue). 1203 */ 1204 csv2 = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR0_CSV2_SHIFT); 1205 if (csv2 > 1 || 1206 (csv2 && arm64_get_spectre_v2_state() != SPECTRE_UNAFFECTED)) 1207 return -EINVAL; 1208 1209 /* Same thing for CSV3 */ 1210 csv3 = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR0_CSV3_SHIFT); 1211 if (csv3 > 1 || 1212 (csv3 && arm64_get_meltdown_state() != SPECTRE_UNAFFECTED)) 1213 return -EINVAL; 1214 1215 /* We can only differ with CSV[23], and anything else is an error */ 1216 val ^= read_id_reg(vcpu, rd, false); 1217 val &= ~((0xFUL << ID_AA64PFR0_CSV2_SHIFT) | 1218 (0xFUL << ID_AA64PFR0_CSV3_SHIFT)); 1219 if (val) 1220 return -EINVAL; 1221 1222 vcpu->kvm->arch.pfr0_csv2 = csv2; 1223 vcpu->kvm->arch.pfr0_csv3 = csv3 ; 1224 1225 return 0; 1226 } 1227 1228 /* 1229 * cpufeature ID register user accessors 1230 * 1231 * For now, these registers are immutable for userspace, so no values 1232 * are stored, and for set_id_reg() we don't allow the effective value 1233 * to be changed. 1234 */ 1235 static int __get_id_reg(const struct kvm_vcpu *vcpu, 1236 const struct sys_reg_desc *rd, void __user *uaddr, 1237 bool raz) 1238 { 1239 const u64 id = sys_reg_to_index(rd); 1240 const u64 val = read_id_reg(vcpu, rd, raz); 1241 1242 return reg_to_user(uaddr, &val, id); 1243 } 1244 1245 static int __set_id_reg(const struct kvm_vcpu *vcpu, 1246 const struct sys_reg_desc *rd, void __user *uaddr, 1247 bool raz) 1248 { 1249 const u64 id = sys_reg_to_index(rd); 1250 int err; 1251 u64 val; 1252 1253 err = reg_from_user(&val, uaddr, id); 1254 if (err) 1255 return err; 1256 1257 /* This is what we mean by invariant: you can't change it. */ 1258 if (val != read_id_reg(vcpu, rd, raz)) 1259 return -EINVAL; 1260 1261 return 0; 1262 } 1263 1264 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1265 const struct kvm_one_reg *reg, void __user *uaddr) 1266 { 1267 bool raz = sysreg_visible_as_raz(vcpu, rd); 1268 1269 return __get_id_reg(vcpu, rd, uaddr, raz); 1270 } 1271 1272 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1273 const struct kvm_one_reg *reg, void __user *uaddr) 1274 { 1275 bool raz = sysreg_visible_as_raz(vcpu, rd); 1276 1277 return __set_id_reg(vcpu, rd, uaddr, raz); 1278 } 1279 1280 static int set_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1281 const struct kvm_one_reg *reg, void __user *uaddr) 1282 { 1283 return __set_id_reg(vcpu, rd, uaddr, true); 1284 } 1285 1286 static int get_raz_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1287 const struct kvm_one_reg *reg, void __user *uaddr) 1288 { 1289 const u64 id = sys_reg_to_index(rd); 1290 const u64 val = 0; 1291 1292 return reg_to_user(uaddr, &val, id); 1293 } 1294 1295 static int set_wi_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1296 const struct kvm_one_reg *reg, void __user *uaddr) 1297 { 1298 int err; 1299 u64 val; 1300 1301 /* Perform the access even if we are going to ignore the value */ 1302 err = reg_from_user(&val, uaddr, sys_reg_to_index(rd)); 1303 if (err) 1304 return err; 1305 1306 return 0; 1307 } 1308 1309 static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1310 const struct sys_reg_desc *r) 1311 { 1312 if (p->is_write) 1313 return write_to_read_only(vcpu, p, r); 1314 1315 p->regval = read_sanitised_ftr_reg(SYS_CTR_EL0); 1316 return true; 1317 } 1318 1319 static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1320 const struct sys_reg_desc *r) 1321 { 1322 if (p->is_write) 1323 return write_to_read_only(vcpu, p, r); 1324 1325 p->regval = read_sysreg(clidr_el1); 1326 return true; 1327 } 1328 1329 static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1330 const struct sys_reg_desc *r) 1331 { 1332 int reg = r->reg; 1333 1334 if (p->is_write) 1335 vcpu_write_sys_reg(vcpu, p->regval, reg); 1336 else 1337 p->regval = vcpu_read_sys_reg(vcpu, reg); 1338 return true; 1339 } 1340 1341 static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1342 const struct sys_reg_desc *r) 1343 { 1344 u32 csselr; 1345 1346 if (p->is_write) 1347 return write_to_read_only(vcpu, p, r); 1348 1349 csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1); 1350 p->regval = get_ccsidr(csselr); 1351 1352 /* 1353 * Guests should not be doing cache operations by set/way at all, and 1354 * for this reason, we trap them and attempt to infer the intent, so 1355 * that we can flush the entire guest's address space at the appropriate 1356 * time. 1357 * To prevent this trapping from causing performance problems, let's 1358 * expose the geometry of all data and unified caches (which are 1359 * guaranteed to be PIPT and thus non-aliasing) as 1 set and 1 way. 1360 * [If guests should attempt to infer aliasing properties from the 1361 * geometry (which is not permitted by the architecture), they would 1362 * only do so for virtually indexed caches.] 1363 */ 1364 if (!(csselr & 1)) // data or unified cache 1365 p->regval &= ~GENMASK(27, 3); 1366 return true; 1367 } 1368 1369 static unsigned int mte_visibility(const struct kvm_vcpu *vcpu, 1370 const struct sys_reg_desc *rd) 1371 { 1372 if (kvm_has_mte(vcpu->kvm)) 1373 return 0; 1374 1375 return REG_HIDDEN; 1376 } 1377 1378 #define MTE_REG(name) { \ 1379 SYS_DESC(SYS_##name), \ 1380 .access = undef_access, \ 1381 .reset = reset_unknown, \ 1382 .reg = name, \ 1383 .visibility = mte_visibility, \ 1384 } 1385 1386 /* sys_reg_desc initialiser for known cpufeature ID registers */ 1387 #define ID_SANITISED(name) { \ 1388 SYS_DESC(SYS_##name), \ 1389 .access = access_id_reg, \ 1390 .get_user = get_id_reg, \ 1391 .set_user = set_id_reg, \ 1392 .visibility = id_visibility, \ 1393 } 1394 1395 /* 1396 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID 1397 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2 1398 * (1 <= crm < 8, 0 <= Op2 < 8). 1399 */ 1400 #define ID_UNALLOCATED(crm, op2) { \ 1401 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \ 1402 .access = access_raz_id_reg, \ 1403 .get_user = get_raz_reg, \ 1404 .set_user = set_raz_id_reg, \ 1405 } 1406 1407 /* 1408 * sys_reg_desc initialiser for known ID registers that we hide from guests. 1409 * For now, these are exposed just like unallocated ID regs: they appear 1410 * RAZ for the guest. 1411 */ 1412 #define ID_HIDDEN(name) { \ 1413 SYS_DESC(SYS_##name), \ 1414 .access = access_raz_id_reg, \ 1415 .get_user = get_raz_reg, \ 1416 .set_user = set_raz_id_reg, \ 1417 } 1418 1419 /* 1420 * Architected system registers. 1421 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2 1422 * 1423 * Debug handling: We do trap most, if not all debug related system 1424 * registers. The implementation is good enough to ensure that a guest 1425 * can use these with minimal performance degradation. The drawback is 1426 * that we don't implement any of the external debug, none of the 1427 * OSlock protocol. This should be revisited if we ever encounter a 1428 * more demanding guest... 1429 */ 1430 static const struct sys_reg_desc sys_reg_descs[] = { 1431 { SYS_DESC(SYS_DC_ISW), access_dcsw }, 1432 { SYS_DESC(SYS_DC_CSW), access_dcsw }, 1433 { SYS_DESC(SYS_DC_CISW), access_dcsw }, 1434 1435 DBG_BCR_BVR_WCR_WVR_EL1(0), 1436 DBG_BCR_BVR_WCR_WVR_EL1(1), 1437 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 }, 1438 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 }, 1439 DBG_BCR_BVR_WCR_WVR_EL1(2), 1440 DBG_BCR_BVR_WCR_WVR_EL1(3), 1441 DBG_BCR_BVR_WCR_WVR_EL1(4), 1442 DBG_BCR_BVR_WCR_WVR_EL1(5), 1443 DBG_BCR_BVR_WCR_WVR_EL1(6), 1444 DBG_BCR_BVR_WCR_WVR_EL1(7), 1445 DBG_BCR_BVR_WCR_WVR_EL1(8), 1446 DBG_BCR_BVR_WCR_WVR_EL1(9), 1447 DBG_BCR_BVR_WCR_WVR_EL1(10), 1448 DBG_BCR_BVR_WCR_WVR_EL1(11), 1449 DBG_BCR_BVR_WCR_WVR_EL1(12), 1450 DBG_BCR_BVR_WCR_WVR_EL1(13), 1451 DBG_BCR_BVR_WCR_WVR_EL1(14), 1452 DBG_BCR_BVR_WCR_WVR_EL1(15), 1453 1454 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi }, 1455 { SYS_DESC(SYS_OSLAR_EL1), trap_raz_wi }, 1456 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1 }, 1457 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi }, 1458 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi }, 1459 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi }, 1460 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi }, 1461 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 }, 1462 1463 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi }, 1464 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi }, 1465 // DBGDTR[TR]X_EL0 share the same encoding 1466 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi }, 1467 1468 { SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 }, 1469 1470 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 }, 1471 1472 /* 1473 * ID regs: all ID_SANITISED() entries here must have corresponding 1474 * entries in arm64_ftr_regs[]. 1475 */ 1476 1477 /* AArch64 mappings of the AArch32 ID registers */ 1478 /* CRm=1 */ 1479 ID_SANITISED(ID_PFR0_EL1), 1480 ID_SANITISED(ID_PFR1_EL1), 1481 ID_SANITISED(ID_DFR0_EL1), 1482 ID_HIDDEN(ID_AFR0_EL1), 1483 ID_SANITISED(ID_MMFR0_EL1), 1484 ID_SANITISED(ID_MMFR1_EL1), 1485 ID_SANITISED(ID_MMFR2_EL1), 1486 ID_SANITISED(ID_MMFR3_EL1), 1487 1488 /* CRm=2 */ 1489 ID_SANITISED(ID_ISAR0_EL1), 1490 ID_SANITISED(ID_ISAR1_EL1), 1491 ID_SANITISED(ID_ISAR2_EL1), 1492 ID_SANITISED(ID_ISAR3_EL1), 1493 ID_SANITISED(ID_ISAR4_EL1), 1494 ID_SANITISED(ID_ISAR5_EL1), 1495 ID_SANITISED(ID_MMFR4_EL1), 1496 ID_SANITISED(ID_ISAR6_EL1), 1497 1498 /* CRm=3 */ 1499 ID_SANITISED(MVFR0_EL1), 1500 ID_SANITISED(MVFR1_EL1), 1501 ID_SANITISED(MVFR2_EL1), 1502 ID_UNALLOCATED(3,3), 1503 ID_SANITISED(ID_PFR2_EL1), 1504 ID_HIDDEN(ID_DFR1_EL1), 1505 ID_SANITISED(ID_MMFR5_EL1), 1506 ID_UNALLOCATED(3,7), 1507 1508 /* AArch64 ID registers */ 1509 /* CRm=4 */ 1510 { SYS_DESC(SYS_ID_AA64PFR0_EL1), .access = access_id_reg, 1511 .get_user = get_id_reg, .set_user = set_id_aa64pfr0_el1, }, 1512 ID_SANITISED(ID_AA64PFR1_EL1), 1513 ID_UNALLOCATED(4,2), 1514 ID_UNALLOCATED(4,3), 1515 ID_SANITISED(ID_AA64ZFR0_EL1), 1516 ID_UNALLOCATED(4,5), 1517 ID_UNALLOCATED(4,6), 1518 ID_UNALLOCATED(4,7), 1519 1520 /* CRm=5 */ 1521 ID_SANITISED(ID_AA64DFR0_EL1), 1522 ID_SANITISED(ID_AA64DFR1_EL1), 1523 ID_UNALLOCATED(5,2), 1524 ID_UNALLOCATED(5,3), 1525 ID_HIDDEN(ID_AA64AFR0_EL1), 1526 ID_HIDDEN(ID_AA64AFR1_EL1), 1527 ID_UNALLOCATED(5,6), 1528 ID_UNALLOCATED(5,7), 1529 1530 /* CRm=6 */ 1531 ID_SANITISED(ID_AA64ISAR0_EL1), 1532 ID_SANITISED(ID_AA64ISAR1_EL1), 1533 ID_SANITISED(ID_AA64ISAR2_EL1), 1534 ID_UNALLOCATED(6,3), 1535 ID_UNALLOCATED(6,4), 1536 ID_UNALLOCATED(6,5), 1537 ID_UNALLOCATED(6,6), 1538 ID_UNALLOCATED(6,7), 1539 1540 /* CRm=7 */ 1541 ID_SANITISED(ID_AA64MMFR0_EL1), 1542 ID_SANITISED(ID_AA64MMFR1_EL1), 1543 ID_SANITISED(ID_AA64MMFR2_EL1), 1544 ID_UNALLOCATED(7,3), 1545 ID_UNALLOCATED(7,4), 1546 ID_UNALLOCATED(7,5), 1547 ID_UNALLOCATED(7,6), 1548 ID_UNALLOCATED(7,7), 1549 1550 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 }, 1551 { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 }, 1552 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 }, 1553 1554 MTE_REG(RGSR_EL1), 1555 MTE_REG(GCR_EL1), 1556 1557 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility }, 1558 { SYS_DESC(SYS_TRFCR_EL1), undef_access }, 1559 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 }, 1560 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 }, 1561 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 }, 1562 1563 PTRAUTH_KEY(APIA), 1564 PTRAUTH_KEY(APIB), 1565 PTRAUTH_KEY(APDA), 1566 PTRAUTH_KEY(APDB), 1567 PTRAUTH_KEY(APGA), 1568 1569 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 }, 1570 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 }, 1571 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 }, 1572 1573 { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi }, 1574 { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi }, 1575 { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi }, 1576 { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi }, 1577 { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi }, 1578 { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi }, 1579 { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi }, 1580 { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi }, 1581 1582 MTE_REG(TFSR_EL1), 1583 MTE_REG(TFSRE0_EL1), 1584 1585 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 }, 1586 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 }, 1587 1588 { SYS_DESC(SYS_PMSCR_EL1), undef_access }, 1589 { SYS_DESC(SYS_PMSNEVFR_EL1), undef_access }, 1590 { SYS_DESC(SYS_PMSICR_EL1), undef_access }, 1591 { SYS_DESC(SYS_PMSIRR_EL1), undef_access }, 1592 { SYS_DESC(SYS_PMSFCR_EL1), undef_access }, 1593 { SYS_DESC(SYS_PMSEVFR_EL1), undef_access }, 1594 { SYS_DESC(SYS_PMSLATFR_EL1), undef_access }, 1595 { SYS_DESC(SYS_PMSIDR_EL1), undef_access }, 1596 { SYS_DESC(SYS_PMBLIMITR_EL1), undef_access }, 1597 { SYS_DESC(SYS_PMBPTR_EL1), undef_access }, 1598 { SYS_DESC(SYS_PMBSR_EL1), undef_access }, 1599 /* PMBIDR_EL1 is not trapped */ 1600 1601 { PMU_SYS_REG(SYS_PMINTENSET_EL1), 1602 .access = access_pminten, .reg = PMINTENSET_EL1 }, 1603 { PMU_SYS_REG(SYS_PMINTENCLR_EL1), 1604 .access = access_pminten, .reg = PMINTENSET_EL1 }, 1605 { SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi }, 1606 1607 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 }, 1608 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 }, 1609 1610 { SYS_DESC(SYS_LORSA_EL1), trap_loregion }, 1611 { SYS_DESC(SYS_LOREA_EL1), trap_loregion }, 1612 { SYS_DESC(SYS_LORN_EL1), trap_loregion }, 1613 { SYS_DESC(SYS_LORC_EL1), trap_loregion }, 1614 { SYS_DESC(SYS_LORID_EL1), trap_loregion }, 1615 1616 { SYS_DESC(SYS_VBAR_EL1), NULL, reset_val, VBAR_EL1, 0 }, 1617 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 }, 1618 1619 { SYS_DESC(SYS_ICC_IAR0_EL1), write_to_read_only }, 1620 { SYS_DESC(SYS_ICC_EOIR0_EL1), read_from_write_only }, 1621 { SYS_DESC(SYS_ICC_HPPIR0_EL1), write_to_read_only }, 1622 { SYS_DESC(SYS_ICC_DIR_EL1), read_from_write_only }, 1623 { SYS_DESC(SYS_ICC_RPR_EL1), write_to_read_only }, 1624 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi }, 1625 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi }, 1626 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi }, 1627 { SYS_DESC(SYS_ICC_IAR1_EL1), write_to_read_only }, 1628 { SYS_DESC(SYS_ICC_EOIR1_EL1), read_from_write_only }, 1629 { SYS_DESC(SYS_ICC_HPPIR1_EL1), write_to_read_only }, 1630 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre }, 1631 1632 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 }, 1633 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 }, 1634 1635 { SYS_DESC(SYS_SCXTNUM_EL1), undef_access }, 1636 1637 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0}, 1638 1639 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr }, 1640 { SYS_DESC(SYS_CLIDR_EL1), access_clidr }, 1641 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, 1642 { SYS_DESC(SYS_CTR_EL0), access_ctr }, 1643 1644 { PMU_SYS_REG(SYS_PMCR_EL0), .access = access_pmcr, 1645 .reset = reset_pmcr, .reg = PMCR_EL0 }, 1646 { PMU_SYS_REG(SYS_PMCNTENSET_EL0), 1647 .access = access_pmcnten, .reg = PMCNTENSET_EL0 }, 1648 { PMU_SYS_REG(SYS_PMCNTENCLR_EL0), 1649 .access = access_pmcnten, .reg = PMCNTENSET_EL0 }, 1650 { PMU_SYS_REG(SYS_PMOVSCLR_EL0), 1651 .access = access_pmovs, .reg = PMOVSSET_EL0 }, 1652 /* 1653 * PM_SWINC_EL0 is exposed to userspace as RAZ/WI, as it was 1654 * previously (and pointlessly) advertised in the past... 1655 */ 1656 { PMU_SYS_REG(SYS_PMSWINC_EL0), 1657 .get_user = get_raz_reg, .set_user = set_wi_reg, 1658 .access = access_pmswinc, .reset = NULL }, 1659 { PMU_SYS_REG(SYS_PMSELR_EL0), 1660 .access = access_pmselr, .reset = reset_pmselr, .reg = PMSELR_EL0 }, 1661 { PMU_SYS_REG(SYS_PMCEID0_EL0), 1662 .access = access_pmceid, .reset = NULL }, 1663 { PMU_SYS_REG(SYS_PMCEID1_EL0), 1664 .access = access_pmceid, .reset = NULL }, 1665 { PMU_SYS_REG(SYS_PMCCNTR_EL0), 1666 .access = access_pmu_evcntr, .reset = reset_unknown, .reg = PMCCNTR_EL0 }, 1667 { PMU_SYS_REG(SYS_PMXEVTYPER_EL0), 1668 .access = access_pmu_evtyper, .reset = NULL }, 1669 { PMU_SYS_REG(SYS_PMXEVCNTR_EL0), 1670 .access = access_pmu_evcntr, .reset = NULL }, 1671 /* 1672 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero 1673 * in 32bit mode. Here we choose to reset it as zero for consistency. 1674 */ 1675 { PMU_SYS_REG(SYS_PMUSERENR_EL0), .access = access_pmuserenr, 1676 .reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 }, 1677 { PMU_SYS_REG(SYS_PMOVSSET_EL0), 1678 .access = access_pmovs, .reg = PMOVSSET_EL0 }, 1679 1680 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 }, 1681 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 }, 1682 1683 { SYS_DESC(SYS_SCXTNUM_EL0), undef_access }, 1684 1685 { SYS_DESC(SYS_AMCR_EL0), undef_access }, 1686 { SYS_DESC(SYS_AMCFGR_EL0), undef_access }, 1687 { SYS_DESC(SYS_AMCGCR_EL0), undef_access }, 1688 { SYS_DESC(SYS_AMUSERENR_EL0), undef_access }, 1689 { SYS_DESC(SYS_AMCNTENCLR0_EL0), undef_access }, 1690 { SYS_DESC(SYS_AMCNTENSET0_EL0), undef_access }, 1691 { SYS_DESC(SYS_AMCNTENCLR1_EL0), undef_access }, 1692 { SYS_DESC(SYS_AMCNTENSET1_EL0), undef_access }, 1693 AMU_AMEVCNTR0_EL0(0), 1694 AMU_AMEVCNTR0_EL0(1), 1695 AMU_AMEVCNTR0_EL0(2), 1696 AMU_AMEVCNTR0_EL0(3), 1697 AMU_AMEVCNTR0_EL0(4), 1698 AMU_AMEVCNTR0_EL0(5), 1699 AMU_AMEVCNTR0_EL0(6), 1700 AMU_AMEVCNTR0_EL0(7), 1701 AMU_AMEVCNTR0_EL0(8), 1702 AMU_AMEVCNTR0_EL0(9), 1703 AMU_AMEVCNTR0_EL0(10), 1704 AMU_AMEVCNTR0_EL0(11), 1705 AMU_AMEVCNTR0_EL0(12), 1706 AMU_AMEVCNTR0_EL0(13), 1707 AMU_AMEVCNTR0_EL0(14), 1708 AMU_AMEVCNTR0_EL0(15), 1709 AMU_AMEVTYPER0_EL0(0), 1710 AMU_AMEVTYPER0_EL0(1), 1711 AMU_AMEVTYPER0_EL0(2), 1712 AMU_AMEVTYPER0_EL0(3), 1713 AMU_AMEVTYPER0_EL0(4), 1714 AMU_AMEVTYPER0_EL0(5), 1715 AMU_AMEVTYPER0_EL0(6), 1716 AMU_AMEVTYPER0_EL0(7), 1717 AMU_AMEVTYPER0_EL0(8), 1718 AMU_AMEVTYPER0_EL0(9), 1719 AMU_AMEVTYPER0_EL0(10), 1720 AMU_AMEVTYPER0_EL0(11), 1721 AMU_AMEVTYPER0_EL0(12), 1722 AMU_AMEVTYPER0_EL0(13), 1723 AMU_AMEVTYPER0_EL0(14), 1724 AMU_AMEVTYPER0_EL0(15), 1725 AMU_AMEVCNTR1_EL0(0), 1726 AMU_AMEVCNTR1_EL0(1), 1727 AMU_AMEVCNTR1_EL0(2), 1728 AMU_AMEVCNTR1_EL0(3), 1729 AMU_AMEVCNTR1_EL0(4), 1730 AMU_AMEVCNTR1_EL0(5), 1731 AMU_AMEVCNTR1_EL0(6), 1732 AMU_AMEVCNTR1_EL0(7), 1733 AMU_AMEVCNTR1_EL0(8), 1734 AMU_AMEVCNTR1_EL0(9), 1735 AMU_AMEVCNTR1_EL0(10), 1736 AMU_AMEVCNTR1_EL0(11), 1737 AMU_AMEVCNTR1_EL0(12), 1738 AMU_AMEVCNTR1_EL0(13), 1739 AMU_AMEVCNTR1_EL0(14), 1740 AMU_AMEVCNTR1_EL0(15), 1741 AMU_AMEVTYPER1_EL0(0), 1742 AMU_AMEVTYPER1_EL0(1), 1743 AMU_AMEVTYPER1_EL0(2), 1744 AMU_AMEVTYPER1_EL0(3), 1745 AMU_AMEVTYPER1_EL0(4), 1746 AMU_AMEVTYPER1_EL0(5), 1747 AMU_AMEVTYPER1_EL0(6), 1748 AMU_AMEVTYPER1_EL0(7), 1749 AMU_AMEVTYPER1_EL0(8), 1750 AMU_AMEVTYPER1_EL0(9), 1751 AMU_AMEVTYPER1_EL0(10), 1752 AMU_AMEVTYPER1_EL0(11), 1753 AMU_AMEVTYPER1_EL0(12), 1754 AMU_AMEVTYPER1_EL0(13), 1755 AMU_AMEVTYPER1_EL0(14), 1756 AMU_AMEVTYPER1_EL0(15), 1757 1758 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer }, 1759 { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer }, 1760 { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer }, 1761 1762 /* PMEVCNTRn_EL0 */ 1763 PMU_PMEVCNTR_EL0(0), 1764 PMU_PMEVCNTR_EL0(1), 1765 PMU_PMEVCNTR_EL0(2), 1766 PMU_PMEVCNTR_EL0(3), 1767 PMU_PMEVCNTR_EL0(4), 1768 PMU_PMEVCNTR_EL0(5), 1769 PMU_PMEVCNTR_EL0(6), 1770 PMU_PMEVCNTR_EL0(7), 1771 PMU_PMEVCNTR_EL0(8), 1772 PMU_PMEVCNTR_EL0(9), 1773 PMU_PMEVCNTR_EL0(10), 1774 PMU_PMEVCNTR_EL0(11), 1775 PMU_PMEVCNTR_EL0(12), 1776 PMU_PMEVCNTR_EL0(13), 1777 PMU_PMEVCNTR_EL0(14), 1778 PMU_PMEVCNTR_EL0(15), 1779 PMU_PMEVCNTR_EL0(16), 1780 PMU_PMEVCNTR_EL0(17), 1781 PMU_PMEVCNTR_EL0(18), 1782 PMU_PMEVCNTR_EL0(19), 1783 PMU_PMEVCNTR_EL0(20), 1784 PMU_PMEVCNTR_EL0(21), 1785 PMU_PMEVCNTR_EL0(22), 1786 PMU_PMEVCNTR_EL0(23), 1787 PMU_PMEVCNTR_EL0(24), 1788 PMU_PMEVCNTR_EL0(25), 1789 PMU_PMEVCNTR_EL0(26), 1790 PMU_PMEVCNTR_EL0(27), 1791 PMU_PMEVCNTR_EL0(28), 1792 PMU_PMEVCNTR_EL0(29), 1793 PMU_PMEVCNTR_EL0(30), 1794 /* PMEVTYPERn_EL0 */ 1795 PMU_PMEVTYPER_EL0(0), 1796 PMU_PMEVTYPER_EL0(1), 1797 PMU_PMEVTYPER_EL0(2), 1798 PMU_PMEVTYPER_EL0(3), 1799 PMU_PMEVTYPER_EL0(4), 1800 PMU_PMEVTYPER_EL0(5), 1801 PMU_PMEVTYPER_EL0(6), 1802 PMU_PMEVTYPER_EL0(7), 1803 PMU_PMEVTYPER_EL0(8), 1804 PMU_PMEVTYPER_EL0(9), 1805 PMU_PMEVTYPER_EL0(10), 1806 PMU_PMEVTYPER_EL0(11), 1807 PMU_PMEVTYPER_EL0(12), 1808 PMU_PMEVTYPER_EL0(13), 1809 PMU_PMEVTYPER_EL0(14), 1810 PMU_PMEVTYPER_EL0(15), 1811 PMU_PMEVTYPER_EL0(16), 1812 PMU_PMEVTYPER_EL0(17), 1813 PMU_PMEVTYPER_EL0(18), 1814 PMU_PMEVTYPER_EL0(19), 1815 PMU_PMEVTYPER_EL0(20), 1816 PMU_PMEVTYPER_EL0(21), 1817 PMU_PMEVTYPER_EL0(22), 1818 PMU_PMEVTYPER_EL0(23), 1819 PMU_PMEVTYPER_EL0(24), 1820 PMU_PMEVTYPER_EL0(25), 1821 PMU_PMEVTYPER_EL0(26), 1822 PMU_PMEVTYPER_EL0(27), 1823 PMU_PMEVTYPER_EL0(28), 1824 PMU_PMEVTYPER_EL0(29), 1825 PMU_PMEVTYPER_EL0(30), 1826 /* 1827 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero 1828 * in 32bit mode. Here we choose to reset it as zero for consistency. 1829 */ 1830 { PMU_SYS_REG(SYS_PMCCFILTR_EL0), .access = access_pmu_evtyper, 1831 .reset = reset_val, .reg = PMCCFILTR_EL0, .val = 0 }, 1832 1833 { SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 }, 1834 { SYS_DESC(SYS_IFSR32_EL2), NULL, reset_unknown, IFSR32_EL2 }, 1835 { SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x700 }, 1836 }; 1837 1838 static bool trap_dbgdidr(struct kvm_vcpu *vcpu, 1839 struct sys_reg_params *p, 1840 const struct sys_reg_desc *r) 1841 { 1842 if (p->is_write) { 1843 return ignore_write(vcpu, p); 1844 } else { 1845 u64 dfr = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); 1846 u64 pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1847 u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL3_SHIFT); 1848 1849 p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) | 1850 (((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) | 1851 (((dfr >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) << 20) 1852 | (6 << 16) | (1 << 15) | (el3 << 14) | (el3 << 12)); 1853 return true; 1854 } 1855 } 1856 1857 /* 1858 * AArch32 debug register mappings 1859 * 1860 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0] 1861 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32] 1862 * 1863 * None of the other registers share their location, so treat them as 1864 * if they were 64bit. 1865 */ 1866 #define DBG_BCR_BVR_WCR_WVR(n) \ 1867 /* DBGBVRn */ \ 1868 { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \ 1869 /* DBGBCRn */ \ 1870 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \ 1871 /* DBGWVRn */ \ 1872 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \ 1873 /* DBGWCRn */ \ 1874 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n } 1875 1876 #define DBGBXVR(n) \ 1877 { AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_bvr, NULL, n } 1878 1879 /* 1880 * Trapped cp14 registers. We generally ignore most of the external 1881 * debug, on the principle that they don't really make sense to a 1882 * guest. Revisit this one day, would this principle change. 1883 */ 1884 static const struct sys_reg_desc cp14_regs[] = { 1885 /* DBGDIDR */ 1886 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgdidr }, 1887 /* DBGDTRRXext */ 1888 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi }, 1889 1890 DBG_BCR_BVR_WCR_WVR(0), 1891 /* DBGDSCRint */ 1892 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi }, 1893 DBG_BCR_BVR_WCR_WVR(1), 1894 /* DBGDCCINT */ 1895 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug_regs, NULL, MDCCINT_EL1 }, 1896 /* DBGDSCRext */ 1897 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug_regs, NULL, MDSCR_EL1 }, 1898 DBG_BCR_BVR_WCR_WVR(2), 1899 /* DBGDTR[RT]Xint */ 1900 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi }, 1901 /* DBGDTR[RT]Xext */ 1902 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi }, 1903 DBG_BCR_BVR_WCR_WVR(3), 1904 DBG_BCR_BVR_WCR_WVR(4), 1905 DBG_BCR_BVR_WCR_WVR(5), 1906 /* DBGWFAR */ 1907 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi }, 1908 /* DBGOSECCR */ 1909 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi }, 1910 DBG_BCR_BVR_WCR_WVR(6), 1911 /* DBGVCR */ 1912 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug_regs, NULL, DBGVCR32_EL2 }, 1913 DBG_BCR_BVR_WCR_WVR(7), 1914 DBG_BCR_BVR_WCR_WVR(8), 1915 DBG_BCR_BVR_WCR_WVR(9), 1916 DBG_BCR_BVR_WCR_WVR(10), 1917 DBG_BCR_BVR_WCR_WVR(11), 1918 DBG_BCR_BVR_WCR_WVR(12), 1919 DBG_BCR_BVR_WCR_WVR(13), 1920 DBG_BCR_BVR_WCR_WVR(14), 1921 DBG_BCR_BVR_WCR_WVR(15), 1922 1923 /* DBGDRAR (32bit) */ 1924 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi }, 1925 1926 DBGBXVR(0), 1927 /* DBGOSLAR */ 1928 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi }, 1929 DBGBXVR(1), 1930 /* DBGOSLSR */ 1931 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 }, 1932 DBGBXVR(2), 1933 DBGBXVR(3), 1934 /* DBGOSDLR */ 1935 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi }, 1936 DBGBXVR(4), 1937 /* DBGPRCR */ 1938 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi }, 1939 DBGBXVR(5), 1940 DBGBXVR(6), 1941 DBGBXVR(7), 1942 DBGBXVR(8), 1943 DBGBXVR(9), 1944 DBGBXVR(10), 1945 DBGBXVR(11), 1946 DBGBXVR(12), 1947 DBGBXVR(13), 1948 DBGBXVR(14), 1949 DBGBXVR(15), 1950 1951 /* DBGDSAR (32bit) */ 1952 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi }, 1953 1954 /* DBGDEVID2 */ 1955 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi }, 1956 /* DBGDEVID1 */ 1957 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi }, 1958 /* DBGDEVID */ 1959 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi }, 1960 /* DBGCLAIMSET */ 1961 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi }, 1962 /* DBGCLAIMCLR */ 1963 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi }, 1964 /* DBGAUTHSTATUS */ 1965 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 }, 1966 }; 1967 1968 /* Trapped cp14 64bit registers */ 1969 static const struct sys_reg_desc cp14_64_regs[] = { 1970 /* DBGDRAR (64bit) */ 1971 { Op1( 0), CRm( 1), .access = trap_raz_wi }, 1972 1973 /* DBGDSAR (64bit) */ 1974 { Op1( 0), CRm( 2), .access = trap_raz_wi }, 1975 }; 1976 1977 /* Macro to expand the PMEVCNTRn register */ 1978 #define PMU_PMEVCNTR(n) \ 1979 /* PMEVCNTRn */ \ 1980 { Op1(0), CRn(0b1110), \ 1981 CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \ 1982 access_pmu_evcntr } 1983 1984 /* Macro to expand the PMEVTYPERn register */ 1985 #define PMU_PMEVTYPER(n) \ 1986 /* PMEVTYPERn */ \ 1987 { Op1(0), CRn(0b1110), \ 1988 CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \ 1989 access_pmu_evtyper } 1990 1991 /* 1992 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding, 1993 * depending on the way they are accessed (as a 32bit or a 64bit 1994 * register). 1995 */ 1996 static const struct sys_reg_desc cp15_regs[] = { 1997 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr }, 1998 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, SCTLR_EL1 }, 1999 /* ACTLR */ 2000 { AA32(LO), Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr, NULL, ACTLR_EL1 }, 2001 /* ACTLR2 */ 2002 { AA32(HI), Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr, NULL, ACTLR_EL1 }, 2003 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, 2004 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, TTBR1_EL1 }, 2005 /* TTBCR */ 2006 { AA32(LO), Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 }, 2007 /* TTBCR2 */ 2008 { AA32(HI), Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, TCR_EL1 }, 2009 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, DACR32_EL2 }, 2010 /* DFSR */ 2011 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, ESR_EL1 }, 2012 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, IFSR32_EL2 }, 2013 /* ADFSR */ 2014 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, AFSR0_EL1 }, 2015 /* AIFSR */ 2016 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, AFSR1_EL1 }, 2017 /* DFAR */ 2018 { AA32(LO), Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, FAR_EL1 }, 2019 /* IFAR */ 2020 { AA32(HI), Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, FAR_EL1 }, 2021 2022 /* 2023 * DC{C,I,CI}SW operations: 2024 */ 2025 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw }, 2026 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw }, 2027 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw }, 2028 2029 /* PMU */ 2030 { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr }, 2031 { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcnten }, 2032 { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcnten }, 2033 { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs }, 2034 { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc }, 2035 { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr }, 2036 { AA32(LO), Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid }, 2037 { AA32(LO), Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid }, 2038 { Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_evcntr }, 2039 { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper }, 2040 { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr }, 2041 { Op1( 0), CRn( 9), CRm(14), Op2( 0), access_pmuserenr }, 2042 { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pminten }, 2043 { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pminten }, 2044 { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovs }, 2045 { AA32(HI), Op1( 0), CRn( 9), CRm(14), Op2( 4), access_pmceid }, 2046 { AA32(HI), Op1( 0), CRn( 9), CRm(14), Op2( 5), access_pmceid }, 2047 /* PMMIR */ 2048 { Op1( 0), CRn( 9), CRm(14), Op2( 6), trap_raz_wi }, 2049 2050 /* PRRR/MAIR0 */ 2051 { AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 }, 2052 /* NMRR/MAIR1 */ 2053 { AA32(HI), Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, MAIR_EL1 }, 2054 /* AMAIR0 */ 2055 { AA32(LO), Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, AMAIR_EL1 }, 2056 /* AMAIR1 */ 2057 { AA32(HI), Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, AMAIR_EL1 }, 2058 2059 /* ICC_SRE */ 2060 { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre }, 2061 2062 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, CONTEXTIDR_EL1 }, 2063 2064 /* Arch Tmers */ 2065 { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer }, 2066 { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer }, 2067 2068 /* PMEVCNTRn */ 2069 PMU_PMEVCNTR(0), 2070 PMU_PMEVCNTR(1), 2071 PMU_PMEVCNTR(2), 2072 PMU_PMEVCNTR(3), 2073 PMU_PMEVCNTR(4), 2074 PMU_PMEVCNTR(5), 2075 PMU_PMEVCNTR(6), 2076 PMU_PMEVCNTR(7), 2077 PMU_PMEVCNTR(8), 2078 PMU_PMEVCNTR(9), 2079 PMU_PMEVCNTR(10), 2080 PMU_PMEVCNTR(11), 2081 PMU_PMEVCNTR(12), 2082 PMU_PMEVCNTR(13), 2083 PMU_PMEVCNTR(14), 2084 PMU_PMEVCNTR(15), 2085 PMU_PMEVCNTR(16), 2086 PMU_PMEVCNTR(17), 2087 PMU_PMEVCNTR(18), 2088 PMU_PMEVCNTR(19), 2089 PMU_PMEVCNTR(20), 2090 PMU_PMEVCNTR(21), 2091 PMU_PMEVCNTR(22), 2092 PMU_PMEVCNTR(23), 2093 PMU_PMEVCNTR(24), 2094 PMU_PMEVCNTR(25), 2095 PMU_PMEVCNTR(26), 2096 PMU_PMEVCNTR(27), 2097 PMU_PMEVCNTR(28), 2098 PMU_PMEVCNTR(29), 2099 PMU_PMEVCNTR(30), 2100 /* PMEVTYPERn */ 2101 PMU_PMEVTYPER(0), 2102 PMU_PMEVTYPER(1), 2103 PMU_PMEVTYPER(2), 2104 PMU_PMEVTYPER(3), 2105 PMU_PMEVTYPER(4), 2106 PMU_PMEVTYPER(5), 2107 PMU_PMEVTYPER(6), 2108 PMU_PMEVTYPER(7), 2109 PMU_PMEVTYPER(8), 2110 PMU_PMEVTYPER(9), 2111 PMU_PMEVTYPER(10), 2112 PMU_PMEVTYPER(11), 2113 PMU_PMEVTYPER(12), 2114 PMU_PMEVTYPER(13), 2115 PMU_PMEVTYPER(14), 2116 PMU_PMEVTYPER(15), 2117 PMU_PMEVTYPER(16), 2118 PMU_PMEVTYPER(17), 2119 PMU_PMEVTYPER(18), 2120 PMU_PMEVTYPER(19), 2121 PMU_PMEVTYPER(20), 2122 PMU_PMEVTYPER(21), 2123 PMU_PMEVTYPER(22), 2124 PMU_PMEVTYPER(23), 2125 PMU_PMEVTYPER(24), 2126 PMU_PMEVTYPER(25), 2127 PMU_PMEVTYPER(26), 2128 PMU_PMEVTYPER(27), 2129 PMU_PMEVTYPER(28), 2130 PMU_PMEVTYPER(29), 2131 PMU_PMEVTYPER(30), 2132 /* PMCCFILTR */ 2133 { Op1(0), CRn(14), CRm(15), Op2(7), access_pmu_evtyper }, 2134 2135 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr }, 2136 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr }, 2137 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 }, 2138 }; 2139 2140 static const struct sys_reg_desc cp15_64_regs[] = { 2141 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, 2142 { Op1( 0), CRn( 0), CRm( 9), Op2( 0), access_pmu_evcntr }, 2143 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */ 2144 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 }, 2145 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */ 2146 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */ 2147 { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer }, 2148 }; 2149 2150 static int check_sysreg_table(const struct sys_reg_desc *table, unsigned int n, 2151 bool is_32) 2152 { 2153 unsigned int i; 2154 2155 for (i = 0; i < n; i++) { 2156 if (!is_32 && table[i].reg && !table[i].reset) { 2157 kvm_err("sys_reg table %p entry %d has lacks reset\n", 2158 table, i); 2159 return 1; 2160 } 2161 2162 if (i && cmp_sys_reg(&table[i-1], &table[i]) >= 0) { 2163 kvm_err("sys_reg table %p out of order (%d)\n", table, i - 1); 2164 return 1; 2165 } 2166 } 2167 2168 return 0; 2169 } 2170 2171 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu) 2172 { 2173 kvm_inject_undefined(vcpu); 2174 return 1; 2175 } 2176 2177 static void perform_access(struct kvm_vcpu *vcpu, 2178 struct sys_reg_params *params, 2179 const struct sys_reg_desc *r) 2180 { 2181 trace_kvm_sys_access(*vcpu_pc(vcpu), params, r); 2182 2183 /* Check for regs disabled by runtime config */ 2184 if (sysreg_hidden(vcpu, r)) { 2185 kvm_inject_undefined(vcpu); 2186 return; 2187 } 2188 2189 /* 2190 * Not having an accessor means that we have configured a trap 2191 * that we don't know how to handle. This certainly qualifies 2192 * as a gross bug that should be fixed right away. 2193 */ 2194 BUG_ON(!r->access); 2195 2196 /* Skip instruction if instructed so */ 2197 if (likely(r->access(vcpu, params, r))) 2198 kvm_incr_pc(vcpu); 2199 } 2200 2201 /* 2202 * emulate_cp -- tries to match a sys_reg access in a handling table, and 2203 * call the corresponding trap handler. 2204 * 2205 * @params: pointer to the descriptor of the access 2206 * @table: array of trap descriptors 2207 * @num: size of the trap descriptor array 2208 * 2209 * Return 0 if the access has been handled, and -1 if not. 2210 */ 2211 static int emulate_cp(struct kvm_vcpu *vcpu, 2212 struct sys_reg_params *params, 2213 const struct sys_reg_desc *table, 2214 size_t num) 2215 { 2216 const struct sys_reg_desc *r; 2217 2218 if (!table) 2219 return -1; /* Not handled */ 2220 2221 r = find_reg(params, table, num); 2222 2223 if (r) { 2224 perform_access(vcpu, params, r); 2225 return 0; 2226 } 2227 2228 /* Not handled */ 2229 return -1; 2230 } 2231 2232 static void unhandled_cp_access(struct kvm_vcpu *vcpu, 2233 struct sys_reg_params *params) 2234 { 2235 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu); 2236 int cp = -1; 2237 2238 switch (esr_ec) { 2239 case ESR_ELx_EC_CP15_32: 2240 case ESR_ELx_EC_CP15_64: 2241 cp = 15; 2242 break; 2243 case ESR_ELx_EC_CP14_MR: 2244 case ESR_ELx_EC_CP14_64: 2245 cp = 14; 2246 break; 2247 default: 2248 WARN_ON(1); 2249 } 2250 2251 print_sys_reg_msg(params, 2252 "Unsupported guest CP%d access at: %08lx [%08lx]\n", 2253 cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 2254 kvm_inject_undefined(vcpu); 2255 } 2256 2257 /** 2258 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access 2259 * @vcpu: The VCPU pointer 2260 * @run: The kvm_run struct 2261 */ 2262 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu, 2263 const struct sys_reg_desc *global, 2264 size_t nr_global) 2265 { 2266 struct sys_reg_params params; 2267 u32 esr = kvm_vcpu_get_esr(vcpu); 2268 int Rt = kvm_vcpu_sys_get_rt(vcpu); 2269 int Rt2 = (esr >> 10) & 0x1f; 2270 2271 params.CRm = (esr >> 1) & 0xf; 2272 params.is_write = ((esr & 1) == 0); 2273 2274 params.Op0 = 0; 2275 params.Op1 = (esr >> 16) & 0xf; 2276 params.Op2 = 0; 2277 params.CRn = 0; 2278 2279 /* 2280 * Make a 64-bit value out of Rt and Rt2. As we use the same trap 2281 * backends between AArch32 and AArch64, we get away with it. 2282 */ 2283 if (params.is_write) { 2284 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff; 2285 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32; 2286 } 2287 2288 /* 2289 * If the table contains a handler, handle the 2290 * potential register operation in the case of a read and return 2291 * with success. 2292 */ 2293 if (!emulate_cp(vcpu, ¶ms, global, nr_global)) { 2294 /* Split up the value between registers for the read side */ 2295 if (!params.is_write) { 2296 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval)); 2297 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval)); 2298 } 2299 2300 return 1; 2301 } 2302 2303 unhandled_cp_access(vcpu, ¶ms); 2304 return 1; 2305 } 2306 2307 /** 2308 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access 2309 * @vcpu: The VCPU pointer 2310 * @run: The kvm_run struct 2311 */ 2312 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu, 2313 const struct sys_reg_desc *global, 2314 size_t nr_global) 2315 { 2316 struct sys_reg_params params; 2317 u32 esr = kvm_vcpu_get_esr(vcpu); 2318 int Rt = kvm_vcpu_sys_get_rt(vcpu); 2319 2320 params.CRm = (esr >> 1) & 0xf; 2321 params.regval = vcpu_get_reg(vcpu, Rt); 2322 params.is_write = ((esr & 1) == 0); 2323 params.CRn = (esr >> 10) & 0xf; 2324 params.Op0 = 0; 2325 params.Op1 = (esr >> 14) & 0x7; 2326 params.Op2 = (esr >> 17) & 0x7; 2327 2328 if (!emulate_cp(vcpu, ¶ms, global, nr_global)) { 2329 if (!params.is_write) 2330 vcpu_set_reg(vcpu, Rt, params.regval); 2331 return 1; 2332 } 2333 2334 unhandled_cp_access(vcpu, ¶ms); 2335 return 1; 2336 } 2337 2338 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu) 2339 { 2340 return kvm_handle_cp_64(vcpu, cp15_64_regs, ARRAY_SIZE(cp15_64_regs)); 2341 } 2342 2343 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu) 2344 { 2345 return kvm_handle_cp_32(vcpu, cp15_regs, ARRAY_SIZE(cp15_regs)); 2346 } 2347 2348 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu) 2349 { 2350 return kvm_handle_cp_64(vcpu, cp14_64_regs, ARRAY_SIZE(cp14_64_regs)); 2351 } 2352 2353 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu) 2354 { 2355 return kvm_handle_cp_32(vcpu, cp14_regs, ARRAY_SIZE(cp14_regs)); 2356 } 2357 2358 static bool is_imp_def_sys_reg(struct sys_reg_params *params) 2359 { 2360 // See ARM DDI 0487E.a, section D12.3.2 2361 return params->Op0 == 3 && (params->CRn & 0b1011) == 0b1011; 2362 } 2363 2364 static int emulate_sys_reg(struct kvm_vcpu *vcpu, 2365 struct sys_reg_params *params) 2366 { 2367 const struct sys_reg_desc *r; 2368 2369 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 2370 2371 if (likely(r)) { 2372 perform_access(vcpu, params, r); 2373 } else if (is_imp_def_sys_reg(params)) { 2374 kvm_inject_undefined(vcpu); 2375 } else { 2376 print_sys_reg_msg(params, 2377 "Unsupported guest sys_reg access at: %lx [%08lx]\n", 2378 *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 2379 kvm_inject_undefined(vcpu); 2380 } 2381 return 1; 2382 } 2383 2384 /** 2385 * kvm_reset_sys_regs - sets system registers to reset value 2386 * @vcpu: The VCPU pointer 2387 * 2388 * This function finds the right table above and sets the registers on the 2389 * virtual CPU struct to their architecturally defined reset values. 2390 */ 2391 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu) 2392 { 2393 unsigned long i; 2394 2395 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) 2396 if (sys_reg_descs[i].reset) 2397 sys_reg_descs[i].reset(vcpu, &sys_reg_descs[i]); 2398 } 2399 2400 /** 2401 * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access 2402 * @vcpu: The VCPU pointer 2403 */ 2404 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu) 2405 { 2406 struct sys_reg_params params; 2407 unsigned long esr = kvm_vcpu_get_esr(vcpu); 2408 int Rt = kvm_vcpu_sys_get_rt(vcpu); 2409 int ret; 2410 2411 trace_kvm_handle_sys_reg(esr); 2412 2413 params = esr_sys64_to_params(esr); 2414 params.regval = vcpu_get_reg(vcpu, Rt); 2415 2416 ret = emulate_sys_reg(vcpu, ¶ms); 2417 2418 if (!params.is_write) 2419 vcpu_set_reg(vcpu, Rt, params.regval); 2420 return ret; 2421 } 2422 2423 /****************************************************************************** 2424 * Userspace API 2425 *****************************************************************************/ 2426 2427 static bool index_to_params(u64 id, struct sys_reg_params *params) 2428 { 2429 switch (id & KVM_REG_SIZE_MASK) { 2430 case KVM_REG_SIZE_U64: 2431 /* Any unused index bits means it's not valid. */ 2432 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK 2433 | KVM_REG_ARM_COPROC_MASK 2434 | KVM_REG_ARM64_SYSREG_OP0_MASK 2435 | KVM_REG_ARM64_SYSREG_OP1_MASK 2436 | KVM_REG_ARM64_SYSREG_CRN_MASK 2437 | KVM_REG_ARM64_SYSREG_CRM_MASK 2438 | KVM_REG_ARM64_SYSREG_OP2_MASK)) 2439 return false; 2440 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK) 2441 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT); 2442 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK) 2443 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT); 2444 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK) 2445 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT); 2446 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK) 2447 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT); 2448 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK) 2449 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT); 2450 return true; 2451 default: 2452 return false; 2453 } 2454 } 2455 2456 const struct sys_reg_desc *find_reg_by_id(u64 id, 2457 struct sys_reg_params *params, 2458 const struct sys_reg_desc table[], 2459 unsigned int num) 2460 { 2461 if (!index_to_params(id, params)) 2462 return NULL; 2463 2464 return find_reg(params, table, num); 2465 } 2466 2467 /* Decode an index value, and find the sys_reg_desc entry. */ 2468 static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu, 2469 u64 id) 2470 { 2471 const struct sys_reg_desc *r; 2472 struct sys_reg_params params; 2473 2474 /* We only do sys_reg for now. */ 2475 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG) 2476 return NULL; 2477 2478 if (!index_to_params(id, ¶ms)) 2479 return NULL; 2480 2481 r = find_reg(¶ms, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 2482 2483 /* Not saved in the sys_reg array and not otherwise accessible? */ 2484 if (r && !(r->reg || r->get_user)) 2485 r = NULL; 2486 2487 return r; 2488 } 2489 2490 /* 2491 * These are the invariant sys_reg registers: we let the guest see the 2492 * host versions of these, so they're part of the guest state. 2493 * 2494 * A future CPU may provide a mechanism to present different values to 2495 * the guest, or a future kvm may trap them. 2496 */ 2497 2498 #define FUNCTION_INVARIANT(reg) \ 2499 static void get_##reg(struct kvm_vcpu *v, \ 2500 const struct sys_reg_desc *r) \ 2501 { \ 2502 ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \ 2503 } 2504 2505 FUNCTION_INVARIANT(midr_el1) 2506 FUNCTION_INVARIANT(revidr_el1) 2507 FUNCTION_INVARIANT(clidr_el1) 2508 FUNCTION_INVARIANT(aidr_el1) 2509 2510 static void get_ctr_el0(struct kvm_vcpu *v, const struct sys_reg_desc *r) 2511 { 2512 ((struct sys_reg_desc *)r)->val = read_sanitised_ftr_reg(SYS_CTR_EL0); 2513 } 2514 2515 /* ->val is filled in by kvm_sys_reg_table_init() */ 2516 static struct sys_reg_desc invariant_sys_regs[] = { 2517 { SYS_DESC(SYS_MIDR_EL1), NULL, get_midr_el1 }, 2518 { SYS_DESC(SYS_REVIDR_EL1), NULL, get_revidr_el1 }, 2519 { SYS_DESC(SYS_CLIDR_EL1), NULL, get_clidr_el1 }, 2520 { SYS_DESC(SYS_AIDR_EL1), NULL, get_aidr_el1 }, 2521 { SYS_DESC(SYS_CTR_EL0), NULL, get_ctr_el0 }, 2522 }; 2523 2524 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id) 2525 { 2526 if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0) 2527 return -EFAULT; 2528 return 0; 2529 } 2530 2531 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id) 2532 { 2533 if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0) 2534 return -EFAULT; 2535 return 0; 2536 } 2537 2538 static int get_invariant_sys_reg(u64 id, void __user *uaddr) 2539 { 2540 struct sys_reg_params params; 2541 const struct sys_reg_desc *r; 2542 2543 r = find_reg_by_id(id, ¶ms, invariant_sys_regs, 2544 ARRAY_SIZE(invariant_sys_regs)); 2545 if (!r) 2546 return -ENOENT; 2547 2548 return reg_to_user(uaddr, &r->val, id); 2549 } 2550 2551 static int set_invariant_sys_reg(u64 id, void __user *uaddr) 2552 { 2553 struct sys_reg_params params; 2554 const struct sys_reg_desc *r; 2555 int err; 2556 u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */ 2557 2558 r = find_reg_by_id(id, ¶ms, invariant_sys_regs, 2559 ARRAY_SIZE(invariant_sys_regs)); 2560 if (!r) 2561 return -ENOENT; 2562 2563 err = reg_from_user(&val, uaddr, id); 2564 if (err) 2565 return err; 2566 2567 /* This is what we mean by invariant: you can't change it. */ 2568 if (r->val != val) 2569 return -EINVAL; 2570 2571 return 0; 2572 } 2573 2574 static bool is_valid_cache(u32 val) 2575 { 2576 u32 level, ctype; 2577 2578 if (val >= CSSELR_MAX) 2579 return false; 2580 2581 /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */ 2582 level = (val >> 1); 2583 ctype = (cache_levels >> (level * 3)) & 7; 2584 2585 switch (ctype) { 2586 case 0: /* No cache */ 2587 return false; 2588 case 1: /* Instruction cache only */ 2589 return (val & 1); 2590 case 2: /* Data cache only */ 2591 case 4: /* Unified cache */ 2592 return !(val & 1); 2593 case 3: /* Separate instruction and data caches */ 2594 return true; 2595 default: /* Reserved: we can't know instruction or data. */ 2596 return false; 2597 } 2598 } 2599 2600 static int demux_c15_get(u64 id, void __user *uaddr) 2601 { 2602 u32 val; 2603 u32 __user *uval = uaddr; 2604 2605 /* Fail if we have unknown bits set. */ 2606 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 2607 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 2608 return -ENOENT; 2609 2610 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 2611 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 2612 if (KVM_REG_SIZE(id) != 4) 2613 return -ENOENT; 2614 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 2615 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 2616 if (!is_valid_cache(val)) 2617 return -ENOENT; 2618 2619 return put_user(get_ccsidr(val), uval); 2620 default: 2621 return -ENOENT; 2622 } 2623 } 2624 2625 static int demux_c15_set(u64 id, void __user *uaddr) 2626 { 2627 u32 val, newval; 2628 u32 __user *uval = uaddr; 2629 2630 /* Fail if we have unknown bits set. */ 2631 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 2632 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 2633 return -ENOENT; 2634 2635 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 2636 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 2637 if (KVM_REG_SIZE(id) != 4) 2638 return -ENOENT; 2639 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 2640 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 2641 if (!is_valid_cache(val)) 2642 return -ENOENT; 2643 2644 if (get_user(newval, uval)) 2645 return -EFAULT; 2646 2647 /* This is also invariant: you can't change it. */ 2648 if (newval != get_ccsidr(val)) 2649 return -EINVAL; 2650 return 0; 2651 default: 2652 return -ENOENT; 2653 } 2654 } 2655 2656 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 2657 { 2658 const struct sys_reg_desc *r; 2659 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 2660 2661 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 2662 return demux_c15_get(reg->id, uaddr); 2663 2664 if (KVM_REG_SIZE(reg->id) != sizeof(__u64)) 2665 return -ENOENT; 2666 2667 r = index_to_sys_reg_desc(vcpu, reg->id); 2668 if (!r) 2669 return get_invariant_sys_reg(reg->id, uaddr); 2670 2671 /* Check for regs disabled by runtime config */ 2672 if (sysreg_hidden(vcpu, r)) 2673 return -ENOENT; 2674 2675 if (r->get_user) 2676 return (r->get_user)(vcpu, r, reg, uaddr); 2677 2678 return reg_to_user(uaddr, &__vcpu_sys_reg(vcpu, r->reg), reg->id); 2679 } 2680 2681 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 2682 { 2683 const struct sys_reg_desc *r; 2684 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 2685 2686 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 2687 return demux_c15_set(reg->id, uaddr); 2688 2689 if (KVM_REG_SIZE(reg->id) != sizeof(__u64)) 2690 return -ENOENT; 2691 2692 r = index_to_sys_reg_desc(vcpu, reg->id); 2693 if (!r) 2694 return set_invariant_sys_reg(reg->id, uaddr); 2695 2696 /* Check for regs disabled by runtime config */ 2697 if (sysreg_hidden(vcpu, r)) 2698 return -ENOENT; 2699 2700 if (r->set_user) 2701 return (r->set_user)(vcpu, r, reg, uaddr); 2702 2703 return reg_from_user(&__vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id); 2704 } 2705 2706 static unsigned int num_demux_regs(void) 2707 { 2708 unsigned int i, count = 0; 2709 2710 for (i = 0; i < CSSELR_MAX; i++) 2711 if (is_valid_cache(i)) 2712 count++; 2713 2714 return count; 2715 } 2716 2717 static int write_demux_regids(u64 __user *uindices) 2718 { 2719 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX; 2720 unsigned int i; 2721 2722 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR; 2723 for (i = 0; i < CSSELR_MAX; i++) { 2724 if (!is_valid_cache(i)) 2725 continue; 2726 if (put_user(val | i, uindices)) 2727 return -EFAULT; 2728 uindices++; 2729 } 2730 return 0; 2731 } 2732 2733 static u64 sys_reg_to_index(const struct sys_reg_desc *reg) 2734 { 2735 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | 2736 KVM_REG_ARM64_SYSREG | 2737 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) | 2738 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) | 2739 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) | 2740 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) | 2741 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT)); 2742 } 2743 2744 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind) 2745 { 2746 if (!*uind) 2747 return true; 2748 2749 if (put_user(sys_reg_to_index(reg), *uind)) 2750 return false; 2751 2752 (*uind)++; 2753 return true; 2754 } 2755 2756 static int walk_one_sys_reg(const struct kvm_vcpu *vcpu, 2757 const struct sys_reg_desc *rd, 2758 u64 __user **uind, 2759 unsigned int *total) 2760 { 2761 /* 2762 * Ignore registers we trap but don't save, 2763 * and for which no custom user accessor is provided. 2764 */ 2765 if (!(rd->reg || rd->get_user)) 2766 return 0; 2767 2768 if (sysreg_hidden(vcpu, rd)) 2769 return 0; 2770 2771 if (!copy_reg_to_user(rd, uind)) 2772 return -EFAULT; 2773 2774 (*total)++; 2775 return 0; 2776 } 2777 2778 /* Assumed ordered tables, see kvm_sys_reg_table_init. */ 2779 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind) 2780 { 2781 const struct sys_reg_desc *i2, *end2; 2782 unsigned int total = 0; 2783 int err; 2784 2785 i2 = sys_reg_descs; 2786 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs); 2787 2788 while (i2 != end2) { 2789 err = walk_one_sys_reg(vcpu, i2++, &uind, &total); 2790 if (err) 2791 return err; 2792 } 2793 return total; 2794 } 2795 2796 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu) 2797 { 2798 return ARRAY_SIZE(invariant_sys_regs) 2799 + num_demux_regs() 2800 + walk_sys_regs(vcpu, (u64 __user *)NULL); 2801 } 2802 2803 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) 2804 { 2805 unsigned int i; 2806 int err; 2807 2808 /* Then give them all the invariant registers' indices. */ 2809 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) { 2810 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices)) 2811 return -EFAULT; 2812 uindices++; 2813 } 2814 2815 err = walk_sys_regs(vcpu, uindices); 2816 if (err < 0) 2817 return err; 2818 uindices += err; 2819 2820 return write_demux_regids(uindices); 2821 } 2822 2823 void kvm_sys_reg_table_init(void) 2824 { 2825 unsigned int i; 2826 struct sys_reg_desc clidr; 2827 2828 /* Make sure tables are unique and in order. */ 2829 BUG_ON(check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), false)); 2830 BUG_ON(check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), true)); 2831 BUG_ON(check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), true)); 2832 BUG_ON(check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), true)); 2833 BUG_ON(check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), true)); 2834 BUG_ON(check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs), false)); 2835 2836 /* We abuse the reset function to overwrite the table itself. */ 2837 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) 2838 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]); 2839 2840 /* 2841 * CLIDR format is awkward, so clean it up. See ARM B4.1.20: 2842 * 2843 * If software reads the Cache Type fields from Ctype1 2844 * upwards, once it has seen a value of 0b000, no caches 2845 * exist at further-out levels of the hierarchy. So, for 2846 * example, if Ctype3 is the first Cache Type field with a 2847 * value of 0b000, the values of Ctype4 to Ctype7 must be 2848 * ignored. 2849 */ 2850 get_clidr_el1(NULL, &clidr); /* Ugly... */ 2851 cache_levels = clidr.val; 2852 for (i = 0; i < 7; i++) 2853 if (((cache_levels >> (i*3)) & 7) == 0) 2854 break; 2855 /* Clear all higher bits. */ 2856 cache_levels &= (1 << (i*3))-1; 2857 } 2858