1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/kvm/coproc.c: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Authors: Rusty Russell <rusty@rustcorp.com.au> 9 * Christoffer Dall <c.dall@virtualopensystems.com> 10 */ 11 12 #include <linux/bitfield.h> 13 #include <linux/bsearch.h> 14 #include <linux/cacheinfo.h> 15 #include <linux/debugfs.h> 16 #include <linux/kvm_host.h> 17 #include <linux/mm.h> 18 #include <linux/printk.h> 19 #include <linux/uaccess.h> 20 21 #include <asm/arm_pmuv3.h> 22 #include <asm/cacheflush.h> 23 #include <asm/cputype.h> 24 #include <asm/debug-monitors.h> 25 #include <asm/esr.h> 26 #include <asm/kvm_arm.h> 27 #include <asm/kvm_emulate.h> 28 #include <asm/kvm_hyp.h> 29 #include <asm/kvm_mmu.h> 30 #include <asm/kvm_nested.h> 31 #include <asm/perf_event.h> 32 #include <asm/sysreg.h> 33 34 #include <trace/events/kvm.h> 35 36 #include "sys_regs.h" 37 #include "vgic/vgic.h" 38 39 #include "trace.h" 40 41 /* 42 * For AArch32, we only take care of what is being trapped. Anything 43 * that has to do with init and userspace access has to go via the 44 * 64bit interface. 45 */ 46 47 static u64 sys_reg_to_index(const struct sys_reg_desc *reg); 48 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 49 u64 val); 50 51 static bool undef_access(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 52 const struct sys_reg_desc *r) 53 { 54 kvm_inject_undefined(vcpu); 55 return false; 56 } 57 58 static bool bad_trap(struct kvm_vcpu *vcpu, 59 struct sys_reg_params *params, 60 const struct sys_reg_desc *r, 61 const char *msg) 62 { 63 WARN_ONCE(1, "Unexpected %s\n", msg); 64 print_sys_reg_instr(params); 65 return undef_access(vcpu, params, r); 66 } 67 68 static bool read_from_write_only(struct kvm_vcpu *vcpu, 69 struct sys_reg_params *params, 70 const struct sys_reg_desc *r) 71 { 72 return bad_trap(vcpu, params, r, 73 "sys_reg read to write-only register"); 74 } 75 76 static bool write_to_read_only(struct kvm_vcpu *vcpu, 77 struct sys_reg_params *params, 78 const struct sys_reg_desc *r) 79 { 80 return bad_trap(vcpu, params, r, 81 "sys_reg write to read-only register"); 82 } 83 84 #define PURE_EL2_SYSREG(el2) \ 85 case el2: { \ 86 *el1r = el2; \ 87 return true; \ 88 } 89 90 #define MAPPED_EL2_SYSREG(el2, el1, fn) \ 91 case el2: { \ 92 *xlate = fn; \ 93 *el1r = el1; \ 94 return true; \ 95 } 96 97 static bool get_el2_to_el1_mapping(unsigned int reg, 98 unsigned int *el1r, u64 (**xlate)(u64)) 99 { 100 switch (reg) { 101 PURE_EL2_SYSREG( VPIDR_EL2 ); 102 PURE_EL2_SYSREG( VMPIDR_EL2 ); 103 PURE_EL2_SYSREG( ACTLR_EL2 ); 104 PURE_EL2_SYSREG( HCR_EL2 ); 105 PURE_EL2_SYSREG( MDCR_EL2 ); 106 PURE_EL2_SYSREG( HSTR_EL2 ); 107 PURE_EL2_SYSREG( HACR_EL2 ); 108 PURE_EL2_SYSREG( VTTBR_EL2 ); 109 PURE_EL2_SYSREG( VTCR_EL2 ); 110 PURE_EL2_SYSREG( RVBAR_EL2 ); 111 PURE_EL2_SYSREG( TPIDR_EL2 ); 112 PURE_EL2_SYSREG( HPFAR_EL2 ); 113 PURE_EL2_SYSREG( HCRX_EL2 ); 114 PURE_EL2_SYSREG( HFGRTR_EL2 ); 115 PURE_EL2_SYSREG( HFGWTR_EL2 ); 116 PURE_EL2_SYSREG( HFGITR_EL2 ); 117 PURE_EL2_SYSREG( HDFGRTR_EL2 ); 118 PURE_EL2_SYSREG( HDFGWTR_EL2 ); 119 PURE_EL2_SYSREG( HAFGRTR_EL2 ); 120 PURE_EL2_SYSREG( CNTVOFF_EL2 ); 121 PURE_EL2_SYSREG( CNTHCTL_EL2 ); 122 MAPPED_EL2_SYSREG(SCTLR_EL2, SCTLR_EL1, 123 translate_sctlr_el2_to_sctlr_el1 ); 124 MAPPED_EL2_SYSREG(CPTR_EL2, CPACR_EL1, 125 translate_cptr_el2_to_cpacr_el1 ); 126 MAPPED_EL2_SYSREG(TTBR0_EL2, TTBR0_EL1, 127 translate_ttbr0_el2_to_ttbr0_el1 ); 128 MAPPED_EL2_SYSREG(TTBR1_EL2, TTBR1_EL1, NULL ); 129 MAPPED_EL2_SYSREG(TCR_EL2, TCR_EL1, 130 translate_tcr_el2_to_tcr_el1 ); 131 MAPPED_EL2_SYSREG(VBAR_EL2, VBAR_EL1, NULL ); 132 MAPPED_EL2_SYSREG(AFSR0_EL2, AFSR0_EL1, NULL ); 133 MAPPED_EL2_SYSREG(AFSR1_EL2, AFSR1_EL1, NULL ); 134 MAPPED_EL2_SYSREG(ESR_EL2, ESR_EL1, NULL ); 135 MAPPED_EL2_SYSREG(FAR_EL2, FAR_EL1, NULL ); 136 MAPPED_EL2_SYSREG(MAIR_EL2, MAIR_EL1, NULL ); 137 MAPPED_EL2_SYSREG(AMAIR_EL2, AMAIR_EL1, NULL ); 138 MAPPED_EL2_SYSREG(ELR_EL2, ELR_EL1, NULL ); 139 MAPPED_EL2_SYSREG(SPSR_EL2, SPSR_EL1, NULL ); 140 MAPPED_EL2_SYSREG(ZCR_EL2, ZCR_EL1, NULL ); 141 MAPPED_EL2_SYSREG(CONTEXTIDR_EL2, CONTEXTIDR_EL1, NULL ); 142 default: 143 return false; 144 } 145 } 146 147 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg) 148 { 149 u64 val = 0x8badf00d8badf00d; 150 u64 (*xlate)(u64) = NULL; 151 unsigned int el1r; 152 153 if (!vcpu_get_flag(vcpu, SYSREGS_ON_CPU)) 154 goto memory_read; 155 156 if (unlikely(get_el2_to_el1_mapping(reg, &el1r, &xlate))) { 157 if (!is_hyp_ctxt(vcpu)) 158 goto memory_read; 159 160 /* 161 * CNTHCTL_EL2 requires some special treatment to 162 * account for the bits that can be set via CNTKCTL_EL1. 163 */ 164 switch (reg) { 165 case CNTHCTL_EL2: 166 if (vcpu_el2_e2h_is_set(vcpu)) { 167 val = read_sysreg_el1(SYS_CNTKCTL); 168 val &= CNTKCTL_VALID_BITS; 169 val |= __vcpu_sys_reg(vcpu, reg) & ~CNTKCTL_VALID_BITS; 170 return val; 171 } 172 break; 173 } 174 175 /* 176 * If this register does not have an EL1 counterpart, 177 * then read the stored EL2 version. 178 */ 179 if (reg == el1r) 180 goto memory_read; 181 182 /* 183 * If we have a non-VHE guest and that the sysreg 184 * requires translation to be used at EL1, use the 185 * in-memory copy instead. 186 */ 187 if (!vcpu_el2_e2h_is_set(vcpu) && xlate) 188 goto memory_read; 189 190 /* Get the current version of the EL1 counterpart. */ 191 WARN_ON(!__vcpu_read_sys_reg_from_cpu(el1r, &val)); 192 return val; 193 } 194 195 /* EL1 register can't be on the CPU if the guest is in vEL2. */ 196 if (unlikely(is_hyp_ctxt(vcpu))) 197 goto memory_read; 198 199 if (__vcpu_read_sys_reg_from_cpu(reg, &val)) 200 return val; 201 202 memory_read: 203 return __vcpu_sys_reg(vcpu, reg); 204 } 205 206 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg) 207 { 208 u64 (*xlate)(u64) = NULL; 209 unsigned int el1r; 210 211 if (!vcpu_get_flag(vcpu, SYSREGS_ON_CPU)) 212 goto memory_write; 213 214 if (unlikely(get_el2_to_el1_mapping(reg, &el1r, &xlate))) { 215 if (!is_hyp_ctxt(vcpu)) 216 goto memory_write; 217 218 /* 219 * Always store a copy of the write to memory to avoid having 220 * to reverse-translate virtual EL2 system registers for a 221 * non-VHE guest hypervisor. 222 */ 223 __vcpu_sys_reg(vcpu, reg) = val; 224 225 switch (reg) { 226 case CNTHCTL_EL2: 227 /* 228 * If E2H=0, CNHTCTL_EL2 is a pure shadow register. 229 * Otherwise, some of the bits are backed by 230 * CNTKCTL_EL1, while the rest is kept in memory. 231 * Yes, this is fun stuff. 232 */ 233 if (vcpu_el2_e2h_is_set(vcpu)) 234 write_sysreg_el1(val, SYS_CNTKCTL); 235 return; 236 } 237 238 /* No EL1 counterpart? We're done here.? */ 239 if (reg == el1r) 240 return; 241 242 if (!vcpu_el2_e2h_is_set(vcpu) && xlate) 243 val = xlate(val); 244 245 /* Redirect this to the EL1 version of the register. */ 246 WARN_ON(!__vcpu_write_sys_reg_to_cpu(val, el1r)); 247 return; 248 } 249 250 /* EL1 register can't be on the CPU if the guest is in vEL2. */ 251 if (unlikely(is_hyp_ctxt(vcpu))) 252 goto memory_write; 253 254 if (__vcpu_write_sys_reg_to_cpu(val, reg)) 255 return; 256 257 memory_write: 258 __vcpu_sys_reg(vcpu, reg) = val; 259 } 260 261 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */ 262 #define CSSELR_MAX 14 263 264 /* 265 * Returns the minimum line size for the selected cache, expressed as 266 * Log2(bytes). 267 */ 268 static u8 get_min_cache_line_size(bool icache) 269 { 270 u64 ctr = read_sanitised_ftr_reg(SYS_CTR_EL0); 271 u8 field; 272 273 if (icache) 274 field = SYS_FIELD_GET(CTR_EL0, IminLine, ctr); 275 else 276 field = SYS_FIELD_GET(CTR_EL0, DminLine, ctr); 277 278 /* 279 * Cache line size is represented as Log2(words) in CTR_EL0. 280 * Log2(bytes) can be derived with the following: 281 * 282 * Log2(words) + 2 = Log2(bytes / 4) + 2 283 * = Log2(bytes) - 2 + 2 284 * = Log2(bytes) 285 */ 286 return field + 2; 287 } 288 289 /* Which cache CCSIDR represents depends on CSSELR value. */ 290 static u32 get_ccsidr(struct kvm_vcpu *vcpu, u32 csselr) 291 { 292 u8 line_size; 293 294 if (vcpu->arch.ccsidr) 295 return vcpu->arch.ccsidr[csselr]; 296 297 line_size = get_min_cache_line_size(csselr & CSSELR_EL1_InD); 298 299 /* 300 * Fabricate a CCSIDR value as the overriding value does not exist. 301 * The real CCSIDR value will not be used as it can vary by the 302 * physical CPU which the vcpu currently resides in. 303 * 304 * The line size is determined with get_min_cache_line_size(), which 305 * should be valid for all CPUs even if they have different cache 306 * configuration. 307 * 308 * The associativity bits are cleared, meaning the geometry of all data 309 * and unified caches (which are guaranteed to be PIPT and thus 310 * non-aliasing) are 1 set and 1 way. 311 * Guests should not be doing cache operations by set/way at all, and 312 * for this reason, we trap them and attempt to infer the intent, so 313 * that we can flush the entire guest's address space at the appropriate 314 * time. The exposed geometry minimizes the number of the traps. 315 * [If guests should attempt to infer aliasing properties from the 316 * geometry (which is not permitted by the architecture), they would 317 * only do so for virtually indexed caches.] 318 * 319 * We don't check if the cache level exists as it is allowed to return 320 * an UNKNOWN value if not. 321 */ 322 return SYS_FIELD_PREP(CCSIDR_EL1, LineSize, line_size - 4); 323 } 324 325 static int set_ccsidr(struct kvm_vcpu *vcpu, u32 csselr, u32 val) 326 { 327 u8 line_size = FIELD_GET(CCSIDR_EL1_LineSize, val) + 4; 328 u32 *ccsidr = vcpu->arch.ccsidr; 329 u32 i; 330 331 if ((val & CCSIDR_EL1_RES0) || 332 line_size < get_min_cache_line_size(csselr & CSSELR_EL1_InD)) 333 return -EINVAL; 334 335 if (!ccsidr) { 336 if (val == get_ccsidr(vcpu, csselr)) 337 return 0; 338 339 ccsidr = kmalloc_array(CSSELR_MAX, sizeof(u32), GFP_KERNEL_ACCOUNT); 340 if (!ccsidr) 341 return -ENOMEM; 342 343 for (i = 0; i < CSSELR_MAX; i++) 344 ccsidr[i] = get_ccsidr(vcpu, i); 345 346 vcpu->arch.ccsidr = ccsidr; 347 } 348 349 ccsidr[csselr] = val; 350 351 return 0; 352 } 353 354 static bool access_rw(struct kvm_vcpu *vcpu, 355 struct sys_reg_params *p, 356 const struct sys_reg_desc *r) 357 { 358 if (p->is_write) 359 vcpu_write_sys_reg(vcpu, p->regval, r->reg); 360 else 361 p->regval = vcpu_read_sys_reg(vcpu, r->reg); 362 363 return true; 364 } 365 366 /* 367 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized). 368 */ 369 static bool access_dcsw(struct kvm_vcpu *vcpu, 370 struct sys_reg_params *p, 371 const struct sys_reg_desc *r) 372 { 373 if (!p->is_write) 374 return read_from_write_only(vcpu, p, r); 375 376 /* 377 * Only track S/W ops if we don't have FWB. It still indicates 378 * that the guest is a bit broken (S/W operations should only 379 * be done by firmware, knowing that there is only a single 380 * CPU left in the system, and certainly not from non-secure 381 * software). 382 */ 383 if (!cpus_have_final_cap(ARM64_HAS_STAGE2_FWB)) 384 kvm_set_way_flush(vcpu); 385 386 return true; 387 } 388 389 static bool access_dcgsw(struct kvm_vcpu *vcpu, 390 struct sys_reg_params *p, 391 const struct sys_reg_desc *r) 392 { 393 if (!kvm_has_mte(vcpu->kvm)) 394 return undef_access(vcpu, p, r); 395 396 /* Treat MTE S/W ops as we treat the classic ones: with contempt */ 397 return access_dcsw(vcpu, p, r); 398 } 399 400 static void get_access_mask(const struct sys_reg_desc *r, u64 *mask, u64 *shift) 401 { 402 switch (r->aarch32_map) { 403 case AA32_LO: 404 *mask = GENMASK_ULL(31, 0); 405 *shift = 0; 406 break; 407 case AA32_HI: 408 *mask = GENMASK_ULL(63, 32); 409 *shift = 32; 410 break; 411 default: 412 *mask = GENMASK_ULL(63, 0); 413 *shift = 0; 414 break; 415 } 416 } 417 418 /* 419 * Generic accessor for VM registers. Only called as long as HCR_TVM 420 * is set. If the guest enables the MMU, we stop trapping the VM 421 * sys_regs and leave it in complete control of the caches. 422 */ 423 static bool access_vm_reg(struct kvm_vcpu *vcpu, 424 struct sys_reg_params *p, 425 const struct sys_reg_desc *r) 426 { 427 bool was_enabled = vcpu_has_cache_enabled(vcpu); 428 u64 val, mask, shift; 429 430 if (reg_to_encoding(r) == SYS_TCR2_EL1 && 431 !kvm_has_feat(vcpu->kvm, ID_AA64MMFR3_EL1, TCRX, IMP)) 432 return undef_access(vcpu, p, r); 433 434 BUG_ON(!p->is_write); 435 436 get_access_mask(r, &mask, &shift); 437 438 if (~mask) { 439 val = vcpu_read_sys_reg(vcpu, r->reg); 440 val &= ~mask; 441 } else { 442 val = 0; 443 } 444 445 val |= (p->regval & (mask >> shift)) << shift; 446 vcpu_write_sys_reg(vcpu, val, r->reg); 447 448 kvm_toggle_cache(vcpu, was_enabled); 449 return true; 450 } 451 452 static bool access_actlr(struct kvm_vcpu *vcpu, 453 struct sys_reg_params *p, 454 const struct sys_reg_desc *r) 455 { 456 u64 mask, shift; 457 458 if (p->is_write) 459 return ignore_write(vcpu, p); 460 461 get_access_mask(r, &mask, &shift); 462 p->regval = (vcpu_read_sys_reg(vcpu, r->reg) & mask) >> shift; 463 464 return true; 465 } 466 467 /* 468 * Trap handler for the GICv3 SGI generation system register. 469 * Forward the request to the VGIC emulation. 470 * The cp15_64 code makes sure this automatically works 471 * for both AArch64 and AArch32 accesses. 472 */ 473 static bool access_gic_sgi(struct kvm_vcpu *vcpu, 474 struct sys_reg_params *p, 475 const struct sys_reg_desc *r) 476 { 477 bool g1; 478 479 if (!kvm_has_gicv3(vcpu->kvm)) 480 return undef_access(vcpu, p, r); 481 482 if (!p->is_write) 483 return read_from_write_only(vcpu, p, r); 484 485 /* 486 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates 487 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group, 488 * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively 489 * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure 490 * group. 491 */ 492 if (p->Op0 == 0) { /* AArch32 */ 493 switch (p->Op1) { 494 default: /* Keep GCC quiet */ 495 case 0: /* ICC_SGI1R */ 496 g1 = true; 497 break; 498 case 1: /* ICC_ASGI1R */ 499 case 2: /* ICC_SGI0R */ 500 g1 = false; 501 break; 502 } 503 } else { /* AArch64 */ 504 switch (p->Op2) { 505 default: /* Keep GCC quiet */ 506 case 5: /* ICC_SGI1R_EL1 */ 507 g1 = true; 508 break; 509 case 6: /* ICC_ASGI1R_EL1 */ 510 case 7: /* ICC_SGI0R_EL1 */ 511 g1 = false; 512 break; 513 } 514 } 515 516 vgic_v3_dispatch_sgi(vcpu, p->regval, g1); 517 518 return true; 519 } 520 521 static bool access_gic_sre(struct kvm_vcpu *vcpu, 522 struct sys_reg_params *p, 523 const struct sys_reg_desc *r) 524 { 525 if (!kvm_has_gicv3(vcpu->kvm)) 526 return undef_access(vcpu, p, r); 527 528 if (p->is_write) 529 return ignore_write(vcpu, p); 530 531 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre; 532 return true; 533 } 534 535 static bool trap_raz_wi(struct kvm_vcpu *vcpu, 536 struct sys_reg_params *p, 537 const struct sys_reg_desc *r) 538 { 539 if (p->is_write) 540 return ignore_write(vcpu, p); 541 else 542 return read_zero(vcpu, p); 543 } 544 545 /* 546 * ARMv8.1 mandates at least a trivial LORegion implementation, where all the 547 * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0 548 * system, these registers should UNDEF. LORID_EL1 being a RO register, we 549 * treat it separately. 550 */ 551 static bool trap_loregion(struct kvm_vcpu *vcpu, 552 struct sys_reg_params *p, 553 const struct sys_reg_desc *r) 554 { 555 u32 sr = reg_to_encoding(r); 556 557 if (!kvm_has_feat(vcpu->kvm, ID_AA64MMFR1_EL1, LO, IMP)) 558 return undef_access(vcpu, p, r); 559 560 if (p->is_write && sr == SYS_LORID_EL1) 561 return write_to_read_only(vcpu, p, r); 562 563 return trap_raz_wi(vcpu, p, r); 564 } 565 566 static bool trap_oslar_el1(struct kvm_vcpu *vcpu, 567 struct sys_reg_params *p, 568 const struct sys_reg_desc *r) 569 { 570 u64 oslsr; 571 572 if (!p->is_write) 573 return read_from_write_only(vcpu, p, r); 574 575 /* Forward the OSLK bit to OSLSR */ 576 oslsr = __vcpu_sys_reg(vcpu, OSLSR_EL1) & ~OSLSR_EL1_OSLK; 577 if (p->regval & OSLAR_EL1_OSLK) 578 oslsr |= OSLSR_EL1_OSLK; 579 580 __vcpu_sys_reg(vcpu, OSLSR_EL1) = oslsr; 581 return true; 582 } 583 584 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu, 585 struct sys_reg_params *p, 586 const struct sys_reg_desc *r) 587 { 588 if (p->is_write) 589 return write_to_read_only(vcpu, p, r); 590 591 p->regval = __vcpu_sys_reg(vcpu, r->reg); 592 return true; 593 } 594 595 static int set_oslsr_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 596 u64 val) 597 { 598 /* 599 * The only modifiable bit is the OSLK bit. Refuse the write if 600 * userspace attempts to change any other bit in the register. 601 */ 602 if ((val ^ rd->val) & ~OSLSR_EL1_OSLK) 603 return -EINVAL; 604 605 __vcpu_sys_reg(vcpu, rd->reg) = val; 606 return 0; 607 } 608 609 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu, 610 struct sys_reg_params *p, 611 const struct sys_reg_desc *r) 612 { 613 if (p->is_write) { 614 return ignore_write(vcpu, p); 615 } else { 616 p->regval = read_sysreg(dbgauthstatus_el1); 617 return true; 618 } 619 } 620 621 /* 622 * We want to avoid world-switching all the DBG registers all the 623 * time: 624 * 625 * - If we've touched any debug register, it is likely that we're 626 * going to touch more of them. It then makes sense to disable the 627 * traps and start doing the save/restore dance 628 * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is 629 * then mandatory to save/restore the registers, as the guest 630 * depends on them. 631 * 632 * For this, we use a DIRTY bit, indicating the guest has modified the 633 * debug registers, used as follow: 634 * 635 * On guest entry: 636 * - If the dirty bit is set (because we're coming back from trapping), 637 * disable the traps, save host registers, restore guest registers. 638 * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), 639 * set the dirty bit, disable the traps, save host registers, 640 * restore guest registers. 641 * - Otherwise, enable the traps 642 * 643 * On guest exit: 644 * - If the dirty bit is set, save guest registers, restore host 645 * registers and clear the dirty bit. This ensure that the host can 646 * now use the debug registers. 647 */ 648 static bool trap_debug_regs(struct kvm_vcpu *vcpu, 649 struct sys_reg_params *p, 650 const struct sys_reg_desc *r) 651 { 652 access_rw(vcpu, p, r); 653 if (p->is_write) 654 vcpu_set_flag(vcpu, DEBUG_DIRTY); 655 656 trace_trap_reg(__func__, r->reg, p->is_write, p->regval); 657 658 return true; 659 } 660 661 /* 662 * reg_to_dbg/dbg_to_reg 663 * 664 * A 32 bit write to a debug register leave top bits alone 665 * A 32 bit read from a debug register only returns the bottom bits 666 * 667 * All writes will set the DEBUG_DIRTY flag to ensure the hyp code 668 * switches between host and guest values in future. 669 */ 670 static void reg_to_dbg(struct kvm_vcpu *vcpu, 671 struct sys_reg_params *p, 672 const struct sys_reg_desc *rd, 673 u64 *dbg_reg) 674 { 675 u64 mask, shift, val; 676 677 get_access_mask(rd, &mask, &shift); 678 679 val = *dbg_reg; 680 val &= ~mask; 681 val |= (p->regval & (mask >> shift)) << shift; 682 *dbg_reg = val; 683 684 vcpu_set_flag(vcpu, DEBUG_DIRTY); 685 } 686 687 static void dbg_to_reg(struct kvm_vcpu *vcpu, 688 struct sys_reg_params *p, 689 const struct sys_reg_desc *rd, 690 u64 *dbg_reg) 691 { 692 u64 mask, shift; 693 694 get_access_mask(rd, &mask, &shift); 695 p->regval = (*dbg_reg & mask) >> shift; 696 } 697 698 static bool trap_bvr(struct kvm_vcpu *vcpu, 699 struct sys_reg_params *p, 700 const struct sys_reg_desc *rd) 701 { 702 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm]; 703 704 if (p->is_write) 705 reg_to_dbg(vcpu, p, rd, dbg_reg); 706 else 707 dbg_to_reg(vcpu, p, rd, dbg_reg); 708 709 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); 710 711 return true; 712 } 713 714 static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 715 u64 val) 716 { 717 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = val; 718 return 0; 719 } 720 721 static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 722 u64 *val) 723 { 724 *val = vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm]; 725 return 0; 726 } 727 728 static u64 reset_bvr(struct kvm_vcpu *vcpu, 729 const struct sys_reg_desc *rd) 730 { 731 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = rd->val; 732 return rd->val; 733 } 734 735 static bool trap_bcr(struct kvm_vcpu *vcpu, 736 struct sys_reg_params *p, 737 const struct sys_reg_desc *rd) 738 { 739 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm]; 740 741 if (p->is_write) 742 reg_to_dbg(vcpu, p, rd, dbg_reg); 743 else 744 dbg_to_reg(vcpu, p, rd, dbg_reg); 745 746 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); 747 748 return true; 749 } 750 751 static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 752 u64 val) 753 { 754 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = val; 755 return 0; 756 } 757 758 static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 759 u64 *val) 760 { 761 *val = vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm]; 762 return 0; 763 } 764 765 static u64 reset_bcr(struct kvm_vcpu *vcpu, 766 const struct sys_reg_desc *rd) 767 { 768 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = rd->val; 769 return rd->val; 770 } 771 772 static bool trap_wvr(struct kvm_vcpu *vcpu, 773 struct sys_reg_params *p, 774 const struct sys_reg_desc *rd) 775 { 776 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]; 777 778 if (p->is_write) 779 reg_to_dbg(vcpu, p, rd, dbg_reg); 780 else 781 dbg_to_reg(vcpu, p, rd, dbg_reg); 782 783 trace_trap_reg(__func__, rd->CRm, p->is_write, 784 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]); 785 786 return true; 787 } 788 789 static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 790 u64 val) 791 { 792 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = val; 793 return 0; 794 } 795 796 static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 797 u64 *val) 798 { 799 *val = vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]; 800 return 0; 801 } 802 803 static u64 reset_wvr(struct kvm_vcpu *vcpu, 804 const struct sys_reg_desc *rd) 805 { 806 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = rd->val; 807 return rd->val; 808 } 809 810 static bool trap_wcr(struct kvm_vcpu *vcpu, 811 struct sys_reg_params *p, 812 const struct sys_reg_desc *rd) 813 { 814 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm]; 815 816 if (p->is_write) 817 reg_to_dbg(vcpu, p, rd, dbg_reg); 818 else 819 dbg_to_reg(vcpu, p, rd, dbg_reg); 820 821 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); 822 823 return true; 824 } 825 826 static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 827 u64 val) 828 { 829 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = val; 830 return 0; 831 } 832 833 static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 834 u64 *val) 835 { 836 *val = vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm]; 837 return 0; 838 } 839 840 static u64 reset_wcr(struct kvm_vcpu *vcpu, 841 const struct sys_reg_desc *rd) 842 { 843 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = rd->val; 844 return rd->val; 845 } 846 847 static u64 reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 848 { 849 u64 amair = read_sysreg(amair_el1); 850 vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1); 851 return amair; 852 } 853 854 static u64 reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 855 { 856 u64 actlr = read_sysreg(actlr_el1); 857 vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1); 858 return actlr; 859 } 860 861 static u64 reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 862 { 863 u64 mpidr; 864 865 /* 866 * Map the vcpu_id into the first three affinity level fields of 867 * the MPIDR. We limit the number of VCPUs in level 0 due to a 868 * limitation to 16 CPUs in that level in the ICC_SGIxR registers 869 * of the GICv3 to be able to address each CPU directly when 870 * sending IPIs. 871 */ 872 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0); 873 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1); 874 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2); 875 mpidr |= (1ULL << 31); 876 vcpu_write_sys_reg(vcpu, mpidr, MPIDR_EL1); 877 878 return mpidr; 879 } 880 881 static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu, 882 const struct sys_reg_desc *r) 883 { 884 if (kvm_vcpu_has_pmu(vcpu)) 885 return 0; 886 887 return REG_HIDDEN; 888 } 889 890 static u64 reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 891 { 892 u64 mask = BIT(ARMV8_PMU_CYCLE_IDX); 893 u8 n = vcpu->kvm->arch.pmcr_n; 894 895 if (n) 896 mask |= GENMASK(n - 1, 0); 897 898 reset_unknown(vcpu, r); 899 __vcpu_sys_reg(vcpu, r->reg) &= mask; 900 901 return __vcpu_sys_reg(vcpu, r->reg); 902 } 903 904 static u64 reset_pmevcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 905 { 906 reset_unknown(vcpu, r); 907 __vcpu_sys_reg(vcpu, r->reg) &= GENMASK(31, 0); 908 909 return __vcpu_sys_reg(vcpu, r->reg); 910 } 911 912 static u64 reset_pmevtyper(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 913 { 914 /* This thing will UNDEF, who cares about the reset value? */ 915 if (!kvm_vcpu_has_pmu(vcpu)) 916 return 0; 917 918 reset_unknown(vcpu, r); 919 __vcpu_sys_reg(vcpu, r->reg) &= kvm_pmu_evtyper_mask(vcpu->kvm); 920 921 return __vcpu_sys_reg(vcpu, r->reg); 922 } 923 924 static u64 reset_pmselr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 925 { 926 reset_unknown(vcpu, r); 927 __vcpu_sys_reg(vcpu, r->reg) &= PMSELR_EL0_SEL_MASK; 928 929 return __vcpu_sys_reg(vcpu, r->reg); 930 } 931 932 static u64 reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 933 { 934 u64 pmcr = 0; 935 936 if (!kvm_supports_32bit_el0()) 937 pmcr |= ARMV8_PMU_PMCR_LC; 938 939 /* 940 * The value of PMCR.N field is included when the 941 * vCPU register is read via kvm_vcpu_read_pmcr(). 942 */ 943 __vcpu_sys_reg(vcpu, r->reg) = pmcr; 944 945 return __vcpu_sys_reg(vcpu, r->reg); 946 } 947 948 static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags) 949 { 950 u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0); 951 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu); 952 953 if (!enabled) 954 kvm_inject_undefined(vcpu); 955 956 return !enabled; 957 } 958 959 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu) 960 { 961 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN); 962 } 963 964 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu) 965 { 966 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN); 967 } 968 969 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu) 970 { 971 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN); 972 } 973 974 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu) 975 { 976 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN); 977 } 978 979 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 980 const struct sys_reg_desc *r) 981 { 982 u64 val; 983 984 if (pmu_access_el0_disabled(vcpu)) 985 return false; 986 987 if (p->is_write) { 988 /* 989 * Only update writeable bits of PMCR (continuing into 990 * kvm_pmu_handle_pmcr() as well) 991 */ 992 val = kvm_vcpu_read_pmcr(vcpu); 993 val &= ~ARMV8_PMU_PMCR_MASK; 994 val |= p->regval & ARMV8_PMU_PMCR_MASK; 995 if (!kvm_supports_32bit_el0()) 996 val |= ARMV8_PMU_PMCR_LC; 997 kvm_pmu_handle_pmcr(vcpu, val); 998 } else { 999 /* PMCR.P & PMCR.C are RAZ */ 1000 val = kvm_vcpu_read_pmcr(vcpu) 1001 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C); 1002 p->regval = val; 1003 } 1004 1005 return true; 1006 } 1007 1008 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1009 const struct sys_reg_desc *r) 1010 { 1011 if (pmu_access_event_counter_el0_disabled(vcpu)) 1012 return false; 1013 1014 if (p->is_write) 1015 __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval; 1016 else 1017 /* return PMSELR.SEL field */ 1018 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0) 1019 & PMSELR_EL0_SEL_MASK; 1020 1021 return true; 1022 } 1023 1024 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1025 const struct sys_reg_desc *r) 1026 { 1027 u64 pmceid, mask, shift; 1028 1029 BUG_ON(p->is_write); 1030 1031 if (pmu_access_el0_disabled(vcpu)) 1032 return false; 1033 1034 get_access_mask(r, &mask, &shift); 1035 1036 pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1)); 1037 pmceid &= mask; 1038 pmceid >>= shift; 1039 1040 p->regval = pmceid; 1041 1042 return true; 1043 } 1044 1045 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx) 1046 { 1047 u64 pmcr, val; 1048 1049 pmcr = kvm_vcpu_read_pmcr(vcpu); 1050 val = FIELD_GET(ARMV8_PMU_PMCR_N, pmcr); 1051 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) { 1052 kvm_inject_undefined(vcpu); 1053 return false; 1054 } 1055 1056 return true; 1057 } 1058 1059 static int get_pmu_evcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 1060 u64 *val) 1061 { 1062 u64 idx; 1063 1064 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 0) 1065 /* PMCCNTR_EL0 */ 1066 idx = ARMV8_PMU_CYCLE_IDX; 1067 else 1068 /* PMEVCNTRn_EL0 */ 1069 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 1070 1071 *val = kvm_pmu_get_counter_value(vcpu, idx); 1072 return 0; 1073 } 1074 1075 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu, 1076 struct sys_reg_params *p, 1077 const struct sys_reg_desc *r) 1078 { 1079 u64 idx = ~0UL; 1080 1081 if (r->CRn == 9 && r->CRm == 13) { 1082 if (r->Op2 == 2) { 1083 /* PMXEVCNTR_EL0 */ 1084 if (pmu_access_event_counter_el0_disabled(vcpu)) 1085 return false; 1086 1087 idx = SYS_FIELD_GET(PMSELR_EL0, SEL, 1088 __vcpu_sys_reg(vcpu, PMSELR_EL0)); 1089 } else if (r->Op2 == 0) { 1090 /* PMCCNTR_EL0 */ 1091 if (pmu_access_cycle_counter_el0_disabled(vcpu)) 1092 return false; 1093 1094 idx = ARMV8_PMU_CYCLE_IDX; 1095 } 1096 } else if (r->CRn == 0 && r->CRm == 9) { 1097 /* PMCCNTR */ 1098 if (pmu_access_event_counter_el0_disabled(vcpu)) 1099 return false; 1100 1101 idx = ARMV8_PMU_CYCLE_IDX; 1102 } else if (r->CRn == 14 && (r->CRm & 12) == 8) { 1103 /* PMEVCNTRn_EL0 */ 1104 if (pmu_access_event_counter_el0_disabled(vcpu)) 1105 return false; 1106 1107 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 1108 } 1109 1110 /* Catch any decoding mistake */ 1111 WARN_ON(idx == ~0UL); 1112 1113 if (!pmu_counter_idx_valid(vcpu, idx)) 1114 return false; 1115 1116 if (p->is_write) { 1117 if (pmu_access_el0_disabled(vcpu)) 1118 return false; 1119 1120 kvm_pmu_set_counter_value(vcpu, idx, p->regval); 1121 } else { 1122 p->regval = kvm_pmu_get_counter_value(vcpu, idx); 1123 } 1124 1125 return true; 1126 } 1127 1128 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1129 const struct sys_reg_desc *r) 1130 { 1131 u64 idx, reg; 1132 1133 if (pmu_access_el0_disabled(vcpu)) 1134 return false; 1135 1136 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) { 1137 /* PMXEVTYPER_EL0 */ 1138 idx = SYS_FIELD_GET(PMSELR_EL0, SEL, __vcpu_sys_reg(vcpu, PMSELR_EL0)); 1139 reg = PMEVTYPER0_EL0 + idx; 1140 } else if (r->CRn == 14 && (r->CRm & 12) == 12) { 1141 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 1142 if (idx == ARMV8_PMU_CYCLE_IDX) 1143 reg = PMCCFILTR_EL0; 1144 else 1145 /* PMEVTYPERn_EL0 */ 1146 reg = PMEVTYPER0_EL0 + idx; 1147 } else { 1148 BUG(); 1149 } 1150 1151 if (!pmu_counter_idx_valid(vcpu, idx)) 1152 return false; 1153 1154 if (p->is_write) { 1155 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx); 1156 kvm_vcpu_pmu_restore_guest(vcpu); 1157 } else { 1158 p->regval = __vcpu_sys_reg(vcpu, reg); 1159 } 1160 1161 return true; 1162 } 1163 1164 static int set_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 val) 1165 { 1166 bool set; 1167 1168 val &= kvm_pmu_valid_counter_mask(vcpu); 1169 1170 switch (r->reg) { 1171 case PMOVSSET_EL0: 1172 /* CRm[1] being set indicates a SET register, and CLR otherwise */ 1173 set = r->CRm & 2; 1174 break; 1175 default: 1176 /* Op2[0] being set indicates a SET register, and CLR otherwise */ 1177 set = r->Op2 & 1; 1178 break; 1179 } 1180 1181 if (set) 1182 __vcpu_sys_reg(vcpu, r->reg) |= val; 1183 else 1184 __vcpu_sys_reg(vcpu, r->reg) &= ~val; 1185 1186 return 0; 1187 } 1188 1189 static int get_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 *val) 1190 { 1191 u64 mask = kvm_pmu_valid_counter_mask(vcpu); 1192 1193 *val = __vcpu_sys_reg(vcpu, r->reg) & mask; 1194 return 0; 1195 } 1196 1197 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1198 const struct sys_reg_desc *r) 1199 { 1200 u64 val, mask; 1201 1202 if (pmu_access_el0_disabled(vcpu)) 1203 return false; 1204 1205 mask = kvm_pmu_valid_counter_mask(vcpu); 1206 if (p->is_write) { 1207 val = p->regval & mask; 1208 if (r->Op2 & 0x1) { 1209 /* accessing PMCNTENSET_EL0 */ 1210 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val; 1211 kvm_pmu_enable_counter_mask(vcpu, val); 1212 kvm_vcpu_pmu_restore_guest(vcpu); 1213 } else { 1214 /* accessing PMCNTENCLR_EL0 */ 1215 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val; 1216 kvm_pmu_disable_counter_mask(vcpu, val); 1217 } 1218 } else { 1219 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0); 1220 } 1221 1222 return true; 1223 } 1224 1225 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1226 const struct sys_reg_desc *r) 1227 { 1228 u64 mask = kvm_pmu_valid_counter_mask(vcpu); 1229 1230 if (check_pmu_access_disabled(vcpu, 0)) 1231 return false; 1232 1233 if (p->is_write) { 1234 u64 val = p->regval & mask; 1235 1236 if (r->Op2 & 0x1) 1237 /* accessing PMINTENSET_EL1 */ 1238 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val; 1239 else 1240 /* accessing PMINTENCLR_EL1 */ 1241 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val; 1242 } else { 1243 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1); 1244 } 1245 1246 return true; 1247 } 1248 1249 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1250 const struct sys_reg_desc *r) 1251 { 1252 u64 mask = kvm_pmu_valid_counter_mask(vcpu); 1253 1254 if (pmu_access_el0_disabled(vcpu)) 1255 return false; 1256 1257 if (p->is_write) { 1258 if (r->CRm & 0x2) 1259 /* accessing PMOVSSET_EL0 */ 1260 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask); 1261 else 1262 /* accessing PMOVSCLR_EL0 */ 1263 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask); 1264 } else { 1265 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0); 1266 } 1267 1268 return true; 1269 } 1270 1271 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1272 const struct sys_reg_desc *r) 1273 { 1274 u64 mask; 1275 1276 if (!p->is_write) 1277 return read_from_write_only(vcpu, p, r); 1278 1279 if (pmu_write_swinc_el0_disabled(vcpu)) 1280 return false; 1281 1282 mask = kvm_pmu_valid_counter_mask(vcpu); 1283 kvm_pmu_software_increment(vcpu, p->regval & mask); 1284 return true; 1285 } 1286 1287 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1288 const struct sys_reg_desc *r) 1289 { 1290 if (p->is_write) { 1291 if (!vcpu_mode_priv(vcpu)) 1292 return undef_access(vcpu, p, r); 1293 1294 __vcpu_sys_reg(vcpu, PMUSERENR_EL0) = 1295 p->regval & ARMV8_PMU_USERENR_MASK; 1296 } else { 1297 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0) 1298 & ARMV8_PMU_USERENR_MASK; 1299 } 1300 1301 return true; 1302 } 1303 1304 static int get_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 1305 u64 *val) 1306 { 1307 *val = kvm_vcpu_read_pmcr(vcpu); 1308 return 0; 1309 } 1310 1311 static int set_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 1312 u64 val) 1313 { 1314 u8 new_n = FIELD_GET(ARMV8_PMU_PMCR_N, val); 1315 struct kvm *kvm = vcpu->kvm; 1316 1317 mutex_lock(&kvm->arch.config_lock); 1318 1319 /* 1320 * The vCPU can't have more counters than the PMU hardware 1321 * implements. Ignore this error to maintain compatibility 1322 * with the existing KVM behavior. 1323 */ 1324 if (!kvm_vm_has_ran_once(kvm) && 1325 new_n <= kvm_arm_pmu_get_max_counters(kvm)) 1326 kvm->arch.pmcr_n = new_n; 1327 1328 mutex_unlock(&kvm->arch.config_lock); 1329 1330 /* 1331 * Ignore writes to RES0 bits, read only bits that are cleared on 1332 * vCPU reset, and writable bits that KVM doesn't support yet. 1333 * (i.e. only PMCR.N and bits [7:0] are mutable from userspace) 1334 * The LP bit is RES0 when FEAT_PMUv3p5 is not supported on the vCPU. 1335 * But, we leave the bit as it is here, as the vCPU's PMUver might 1336 * be changed later (NOTE: the bit will be cleared on first vCPU run 1337 * if necessary). 1338 */ 1339 val &= ARMV8_PMU_PMCR_MASK; 1340 1341 /* The LC bit is RES1 when AArch32 is not supported */ 1342 if (!kvm_supports_32bit_el0()) 1343 val |= ARMV8_PMU_PMCR_LC; 1344 1345 __vcpu_sys_reg(vcpu, r->reg) = val; 1346 return 0; 1347 } 1348 1349 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */ 1350 #define DBG_BCR_BVR_WCR_WVR_EL1(n) \ 1351 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \ 1352 trap_bvr, reset_bvr, 0, 0, get_bvr, set_bvr }, \ 1353 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \ 1354 trap_bcr, reset_bcr, 0, 0, get_bcr, set_bcr }, \ 1355 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \ 1356 trap_wvr, reset_wvr, 0, 0, get_wvr, set_wvr }, \ 1357 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \ 1358 trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr } 1359 1360 #define PMU_SYS_REG(name) \ 1361 SYS_DESC(SYS_##name), .reset = reset_pmu_reg, \ 1362 .visibility = pmu_visibility 1363 1364 /* Macro to expand the PMEVCNTRn_EL0 register */ 1365 #define PMU_PMEVCNTR_EL0(n) \ 1366 { PMU_SYS_REG(PMEVCNTRn_EL0(n)), \ 1367 .reset = reset_pmevcntr, .get_user = get_pmu_evcntr, \ 1368 .access = access_pmu_evcntr, .reg = (PMEVCNTR0_EL0 + n), } 1369 1370 /* Macro to expand the PMEVTYPERn_EL0 register */ 1371 #define PMU_PMEVTYPER_EL0(n) \ 1372 { PMU_SYS_REG(PMEVTYPERn_EL0(n)), \ 1373 .reset = reset_pmevtyper, \ 1374 .access = access_pmu_evtyper, .reg = (PMEVTYPER0_EL0 + n), } 1375 1376 /* Macro to expand the AMU counter and type registers*/ 1377 #define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), undef_access } 1378 #define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), undef_access } 1379 #define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), undef_access } 1380 #define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), undef_access } 1381 1382 static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu, 1383 const struct sys_reg_desc *rd) 1384 { 1385 return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN; 1386 } 1387 1388 /* 1389 * If we land here on a PtrAuth access, that is because we didn't 1390 * fixup the access on exit by allowing the PtrAuth sysregs. The only 1391 * way this happens is when the guest does not have PtrAuth support 1392 * enabled. 1393 */ 1394 #define __PTRAUTH_KEY(k) \ 1395 { SYS_DESC(SYS_## k), undef_access, reset_unknown, k, \ 1396 .visibility = ptrauth_visibility} 1397 1398 #define PTRAUTH_KEY(k) \ 1399 __PTRAUTH_KEY(k ## KEYLO_EL1), \ 1400 __PTRAUTH_KEY(k ## KEYHI_EL1) 1401 1402 static bool access_arch_timer(struct kvm_vcpu *vcpu, 1403 struct sys_reg_params *p, 1404 const struct sys_reg_desc *r) 1405 { 1406 enum kvm_arch_timers tmr; 1407 enum kvm_arch_timer_regs treg; 1408 u64 reg = reg_to_encoding(r); 1409 1410 switch (reg) { 1411 case SYS_CNTP_TVAL_EL0: 1412 case SYS_AARCH32_CNTP_TVAL: 1413 tmr = TIMER_PTIMER; 1414 treg = TIMER_REG_TVAL; 1415 break; 1416 case SYS_CNTP_CTL_EL0: 1417 case SYS_AARCH32_CNTP_CTL: 1418 tmr = TIMER_PTIMER; 1419 treg = TIMER_REG_CTL; 1420 break; 1421 case SYS_CNTP_CVAL_EL0: 1422 case SYS_AARCH32_CNTP_CVAL: 1423 tmr = TIMER_PTIMER; 1424 treg = TIMER_REG_CVAL; 1425 break; 1426 case SYS_CNTPCT_EL0: 1427 case SYS_CNTPCTSS_EL0: 1428 case SYS_AARCH32_CNTPCT: 1429 tmr = TIMER_PTIMER; 1430 treg = TIMER_REG_CNT; 1431 break; 1432 default: 1433 print_sys_reg_msg(p, "%s", "Unhandled trapped timer register"); 1434 return undef_access(vcpu, p, r); 1435 } 1436 1437 if (p->is_write) 1438 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval); 1439 else 1440 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg); 1441 1442 return true; 1443 } 1444 1445 static s64 kvm_arm64_ftr_safe_value(u32 id, const struct arm64_ftr_bits *ftrp, 1446 s64 new, s64 cur) 1447 { 1448 struct arm64_ftr_bits kvm_ftr = *ftrp; 1449 1450 /* Some features have different safe value type in KVM than host features */ 1451 switch (id) { 1452 case SYS_ID_AA64DFR0_EL1: 1453 switch (kvm_ftr.shift) { 1454 case ID_AA64DFR0_EL1_PMUVer_SHIFT: 1455 kvm_ftr.type = FTR_LOWER_SAFE; 1456 break; 1457 case ID_AA64DFR0_EL1_DebugVer_SHIFT: 1458 kvm_ftr.type = FTR_LOWER_SAFE; 1459 break; 1460 } 1461 break; 1462 case SYS_ID_DFR0_EL1: 1463 if (kvm_ftr.shift == ID_DFR0_EL1_PerfMon_SHIFT) 1464 kvm_ftr.type = FTR_LOWER_SAFE; 1465 break; 1466 } 1467 1468 return arm64_ftr_safe_value(&kvm_ftr, new, cur); 1469 } 1470 1471 /* 1472 * arm64_check_features() - Check if a feature register value constitutes 1473 * a subset of features indicated by the idreg's KVM sanitised limit. 1474 * 1475 * This function will check if each feature field of @val is the "safe" value 1476 * against idreg's KVM sanitised limit return from reset() callback. 1477 * If a field value in @val is the same as the one in limit, it is always 1478 * considered the safe value regardless For register fields that are not in 1479 * writable, only the value in limit is considered the safe value. 1480 * 1481 * Return: 0 if all the fields are safe. Otherwise, return negative errno. 1482 */ 1483 static int arm64_check_features(struct kvm_vcpu *vcpu, 1484 const struct sys_reg_desc *rd, 1485 u64 val) 1486 { 1487 const struct arm64_ftr_reg *ftr_reg; 1488 const struct arm64_ftr_bits *ftrp = NULL; 1489 u32 id = reg_to_encoding(rd); 1490 u64 writable_mask = rd->val; 1491 u64 limit = rd->reset(vcpu, rd); 1492 u64 mask = 0; 1493 1494 /* 1495 * Hidden and unallocated ID registers may not have a corresponding 1496 * struct arm64_ftr_reg. Of course, if the register is RAZ we know the 1497 * only safe value is 0. 1498 */ 1499 if (sysreg_visible_as_raz(vcpu, rd)) 1500 return val ? -E2BIG : 0; 1501 1502 ftr_reg = get_arm64_ftr_reg(id); 1503 if (!ftr_reg) 1504 return -EINVAL; 1505 1506 ftrp = ftr_reg->ftr_bits; 1507 1508 for (; ftrp && ftrp->width; ftrp++) { 1509 s64 f_val, f_lim, safe_val; 1510 u64 ftr_mask; 1511 1512 ftr_mask = arm64_ftr_mask(ftrp); 1513 if ((ftr_mask & writable_mask) != ftr_mask) 1514 continue; 1515 1516 f_val = arm64_ftr_value(ftrp, val); 1517 f_lim = arm64_ftr_value(ftrp, limit); 1518 mask |= ftr_mask; 1519 1520 if (f_val == f_lim) 1521 safe_val = f_val; 1522 else 1523 safe_val = kvm_arm64_ftr_safe_value(id, ftrp, f_val, f_lim); 1524 1525 if (safe_val != f_val) 1526 return -E2BIG; 1527 } 1528 1529 /* For fields that are not writable, values in limit are the safe values. */ 1530 if ((val & ~mask) != (limit & ~mask)) 1531 return -E2BIG; 1532 1533 return 0; 1534 } 1535 1536 static u8 pmuver_to_perfmon(u8 pmuver) 1537 { 1538 switch (pmuver) { 1539 case ID_AA64DFR0_EL1_PMUVer_IMP: 1540 return ID_DFR0_EL1_PerfMon_PMUv3; 1541 case ID_AA64DFR0_EL1_PMUVer_IMP_DEF: 1542 return ID_DFR0_EL1_PerfMon_IMPDEF; 1543 default: 1544 /* Anything ARMv8.1+ and NI have the same value. For now. */ 1545 return pmuver; 1546 } 1547 } 1548 1549 /* Read a sanitised cpufeature ID register by sys_reg_desc */ 1550 static u64 __kvm_read_sanitised_id_reg(const struct kvm_vcpu *vcpu, 1551 const struct sys_reg_desc *r) 1552 { 1553 u32 id = reg_to_encoding(r); 1554 u64 val; 1555 1556 if (sysreg_visible_as_raz(vcpu, r)) 1557 return 0; 1558 1559 val = read_sanitised_ftr_reg(id); 1560 1561 switch (id) { 1562 case SYS_ID_AA64PFR1_EL1: 1563 if (!kvm_has_mte(vcpu->kvm)) 1564 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE); 1565 1566 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_SME); 1567 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_RNDR_trap); 1568 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_NMI); 1569 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE_frac); 1570 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_GCS); 1571 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_THE); 1572 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTEX); 1573 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_DF2); 1574 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_PFAR); 1575 break; 1576 case SYS_ID_AA64PFR2_EL1: 1577 /* We only expose FPMR */ 1578 val &= ID_AA64PFR2_EL1_FPMR; 1579 break; 1580 case SYS_ID_AA64ISAR1_EL1: 1581 if (!vcpu_has_ptrauth(vcpu)) 1582 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) | 1583 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) | 1584 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) | 1585 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI)); 1586 break; 1587 case SYS_ID_AA64ISAR2_EL1: 1588 if (!vcpu_has_ptrauth(vcpu)) 1589 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) | 1590 ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3)); 1591 if (!cpus_have_final_cap(ARM64_HAS_WFXT)) 1592 val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT); 1593 break; 1594 case SYS_ID_AA64MMFR2_EL1: 1595 val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK; 1596 break; 1597 case SYS_ID_AA64MMFR3_EL1: 1598 val &= ID_AA64MMFR3_EL1_TCRX | ID_AA64MMFR3_EL1_S1POE | 1599 ID_AA64MMFR3_EL1_S1PIE; 1600 break; 1601 case SYS_ID_MMFR4_EL1: 1602 val &= ~ARM64_FEATURE_MASK(ID_MMFR4_EL1_CCIDX); 1603 break; 1604 } 1605 1606 return val; 1607 } 1608 1609 static u64 kvm_read_sanitised_id_reg(struct kvm_vcpu *vcpu, 1610 const struct sys_reg_desc *r) 1611 { 1612 return __kvm_read_sanitised_id_reg(vcpu, r); 1613 } 1614 1615 static u64 read_id_reg(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 1616 { 1617 return kvm_read_vm_id_reg(vcpu->kvm, reg_to_encoding(r)); 1618 } 1619 1620 static bool is_feature_id_reg(u32 encoding) 1621 { 1622 return (sys_reg_Op0(encoding) == 3 && 1623 (sys_reg_Op1(encoding) < 2 || sys_reg_Op1(encoding) == 3) && 1624 sys_reg_CRn(encoding) == 0 && 1625 sys_reg_CRm(encoding) <= 7); 1626 } 1627 1628 /* 1629 * Return true if the register's (Op0, Op1, CRn, CRm, Op2) is 1630 * (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8, which is the range of ID 1631 * registers KVM maintains on a per-VM basis. 1632 */ 1633 static inline bool is_vm_ftr_id_reg(u32 id) 1634 { 1635 if (id == SYS_CTR_EL0) 1636 return true; 1637 1638 return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 && 1639 sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 && 1640 sys_reg_CRm(id) < 8); 1641 } 1642 1643 static inline bool is_vcpu_ftr_id_reg(u32 id) 1644 { 1645 return is_feature_id_reg(id) && !is_vm_ftr_id_reg(id); 1646 } 1647 1648 static inline bool is_aa32_id_reg(u32 id) 1649 { 1650 return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 && 1651 sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 && 1652 sys_reg_CRm(id) <= 3); 1653 } 1654 1655 static unsigned int id_visibility(const struct kvm_vcpu *vcpu, 1656 const struct sys_reg_desc *r) 1657 { 1658 u32 id = reg_to_encoding(r); 1659 1660 switch (id) { 1661 case SYS_ID_AA64ZFR0_EL1: 1662 if (!vcpu_has_sve(vcpu)) 1663 return REG_RAZ; 1664 break; 1665 } 1666 1667 return 0; 1668 } 1669 1670 static unsigned int aa32_id_visibility(const struct kvm_vcpu *vcpu, 1671 const struct sys_reg_desc *r) 1672 { 1673 /* 1674 * AArch32 ID registers are UNKNOWN if AArch32 isn't implemented at any 1675 * EL. Promote to RAZ/WI in order to guarantee consistency between 1676 * systems. 1677 */ 1678 if (!kvm_supports_32bit_el0()) 1679 return REG_RAZ | REG_USER_WI; 1680 1681 return id_visibility(vcpu, r); 1682 } 1683 1684 static unsigned int raz_visibility(const struct kvm_vcpu *vcpu, 1685 const struct sys_reg_desc *r) 1686 { 1687 return REG_RAZ; 1688 } 1689 1690 /* cpufeature ID register access trap handlers */ 1691 1692 static bool access_id_reg(struct kvm_vcpu *vcpu, 1693 struct sys_reg_params *p, 1694 const struct sys_reg_desc *r) 1695 { 1696 if (p->is_write) 1697 return write_to_read_only(vcpu, p, r); 1698 1699 p->regval = read_id_reg(vcpu, r); 1700 1701 return true; 1702 } 1703 1704 /* Visibility overrides for SVE-specific control registers */ 1705 static unsigned int sve_visibility(const struct kvm_vcpu *vcpu, 1706 const struct sys_reg_desc *rd) 1707 { 1708 if (vcpu_has_sve(vcpu)) 1709 return 0; 1710 1711 return REG_HIDDEN; 1712 } 1713 1714 static unsigned int sme_visibility(const struct kvm_vcpu *vcpu, 1715 const struct sys_reg_desc *rd) 1716 { 1717 if (kvm_has_feat(vcpu->kvm, ID_AA64PFR1_EL1, SME, IMP)) 1718 return 0; 1719 1720 return REG_HIDDEN; 1721 } 1722 1723 static unsigned int fp8_visibility(const struct kvm_vcpu *vcpu, 1724 const struct sys_reg_desc *rd) 1725 { 1726 if (kvm_has_fpmr(vcpu->kvm)) 1727 return 0; 1728 1729 return REG_HIDDEN; 1730 } 1731 1732 static u64 read_sanitised_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, 1733 const struct sys_reg_desc *rd) 1734 { 1735 u64 val = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1736 1737 if (!vcpu_has_sve(vcpu)) 1738 val &= ~ID_AA64PFR0_EL1_SVE_MASK; 1739 1740 /* 1741 * The default is to expose CSV2 == 1 if the HW isn't affected. 1742 * Although this is a per-CPU feature, we make it global because 1743 * asymmetric systems are just a nuisance. 1744 * 1745 * Userspace can override this as long as it doesn't promise 1746 * the impossible. 1747 */ 1748 if (arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED) { 1749 val &= ~ID_AA64PFR0_EL1_CSV2_MASK; 1750 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV2, IMP); 1751 } 1752 if (arm64_get_meltdown_state() == SPECTRE_UNAFFECTED) { 1753 val &= ~ID_AA64PFR0_EL1_CSV3_MASK; 1754 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV3, IMP); 1755 } 1756 1757 if (kvm_vgic_global_state.type == VGIC_V3) { 1758 val &= ~ID_AA64PFR0_EL1_GIC_MASK; 1759 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, GIC, IMP); 1760 } 1761 1762 val &= ~ID_AA64PFR0_EL1_AMU_MASK; 1763 1764 return val; 1765 } 1766 1767 #define ID_REG_LIMIT_FIELD_ENUM(val, reg, field, limit) \ 1768 ({ \ 1769 u64 __f_val = FIELD_GET(reg##_##field##_MASK, val); \ 1770 (val) &= ~reg##_##field##_MASK; \ 1771 (val) |= FIELD_PREP(reg##_##field##_MASK, \ 1772 min(__f_val, \ 1773 (u64)SYS_FIELD_VALUE(reg, field, limit))); \ 1774 (val); \ 1775 }) 1776 1777 static u64 read_sanitised_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, 1778 const struct sys_reg_desc *rd) 1779 { 1780 u64 val = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); 1781 1782 val = ID_REG_LIMIT_FIELD_ENUM(val, ID_AA64DFR0_EL1, DebugVer, V8P8); 1783 1784 /* 1785 * Only initialize the PMU version if the vCPU was configured with one. 1786 */ 1787 val &= ~ID_AA64DFR0_EL1_PMUVer_MASK; 1788 if (kvm_vcpu_has_pmu(vcpu)) 1789 val |= SYS_FIELD_PREP(ID_AA64DFR0_EL1, PMUVer, 1790 kvm_arm_pmu_get_pmuver_limit()); 1791 1792 /* Hide SPE from guests */ 1793 val &= ~ID_AA64DFR0_EL1_PMSVer_MASK; 1794 1795 return val; 1796 } 1797 1798 static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, 1799 const struct sys_reg_desc *rd, 1800 u64 val) 1801 { 1802 u8 debugver = SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, val); 1803 u8 pmuver = SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, val); 1804 1805 /* 1806 * Prior to commit 3d0dba5764b9 ("KVM: arm64: PMU: Move the 1807 * ID_AA64DFR0_EL1.PMUver limit to VM creation"), KVM erroneously 1808 * exposed an IMP_DEF PMU to userspace and the guest on systems w/ 1809 * non-architectural PMUs. Of course, PMUv3 is the only game in town for 1810 * PMU virtualization, so the IMP_DEF value was rather user-hostile. 1811 * 1812 * At minimum, we're on the hook to allow values that were given to 1813 * userspace by KVM. Cover our tracks here and replace the IMP_DEF value 1814 * with a more sensible NI. The value of an ID register changing under 1815 * the nose of the guest is unfortunate, but is certainly no more 1816 * surprising than an ill-guided PMU driver poking at impdef system 1817 * registers that end in an UNDEF... 1818 */ 1819 if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF) 1820 val &= ~ID_AA64DFR0_EL1_PMUVer_MASK; 1821 1822 /* 1823 * ID_AA64DFR0_EL1.DebugVer is one of those awkward fields with a 1824 * nonzero minimum safe value. 1825 */ 1826 if (debugver < ID_AA64DFR0_EL1_DebugVer_IMP) 1827 return -EINVAL; 1828 1829 return set_id_reg(vcpu, rd, val); 1830 } 1831 1832 static u64 read_sanitised_id_dfr0_el1(struct kvm_vcpu *vcpu, 1833 const struct sys_reg_desc *rd) 1834 { 1835 u8 perfmon = pmuver_to_perfmon(kvm_arm_pmu_get_pmuver_limit()); 1836 u64 val = read_sanitised_ftr_reg(SYS_ID_DFR0_EL1); 1837 1838 val &= ~ID_DFR0_EL1_PerfMon_MASK; 1839 if (kvm_vcpu_has_pmu(vcpu)) 1840 val |= SYS_FIELD_PREP(ID_DFR0_EL1, PerfMon, perfmon); 1841 1842 val = ID_REG_LIMIT_FIELD_ENUM(val, ID_DFR0_EL1, CopDbg, Debugv8p8); 1843 1844 return val; 1845 } 1846 1847 static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, 1848 const struct sys_reg_desc *rd, 1849 u64 val) 1850 { 1851 u8 perfmon = SYS_FIELD_GET(ID_DFR0_EL1, PerfMon, val); 1852 u8 copdbg = SYS_FIELD_GET(ID_DFR0_EL1, CopDbg, val); 1853 1854 if (perfmon == ID_DFR0_EL1_PerfMon_IMPDEF) { 1855 val &= ~ID_DFR0_EL1_PerfMon_MASK; 1856 perfmon = 0; 1857 } 1858 1859 /* 1860 * Allow DFR0_EL1.PerfMon to be set from userspace as long as 1861 * it doesn't promise more than what the HW gives us on the 1862 * AArch64 side (as everything is emulated with that), and 1863 * that this is a PMUv3. 1864 */ 1865 if (perfmon != 0 && perfmon < ID_DFR0_EL1_PerfMon_PMUv3) 1866 return -EINVAL; 1867 1868 if (copdbg < ID_DFR0_EL1_CopDbg_Armv8) 1869 return -EINVAL; 1870 1871 return set_id_reg(vcpu, rd, val); 1872 } 1873 1874 /* 1875 * cpufeature ID register user accessors 1876 * 1877 * For now, these registers are immutable for userspace, so no values 1878 * are stored, and for set_id_reg() we don't allow the effective value 1879 * to be changed. 1880 */ 1881 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1882 u64 *val) 1883 { 1884 /* 1885 * Avoid locking if the VM has already started, as the ID registers are 1886 * guaranteed to be invariant at that point. 1887 */ 1888 if (kvm_vm_has_ran_once(vcpu->kvm)) { 1889 *val = read_id_reg(vcpu, rd); 1890 return 0; 1891 } 1892 1893 mutex_lock(&vcpu->kvm->arch.config_lock); 1894 *val = read_id_reg(vcpu, rd); 1895 mutex_unlock(&vcpu->kvm->arch.config_lock); 1896 1897 return 0; 1898 } 1899 1900 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1901 u64 val) 1902 { 1903 u32 id = reg_to_encoding(rd); 1904 int ret; 1905 1906 mutex_lock(&vcpu->kvm->arch.config_lock); 1907 1908 /* 1909 * Once the VM has started the ID registers are immutable. Reject any 1910 * write that does not match the final register value. 1911 */ 1912 if (kvm_vm_has_ran_once(vcpu->kvm)) { 1913 if (val != read_id_reg(vcpu, rd)) 1914 ret = -EBUSY; 1915 else 1916 ret = 0; 1917 1918 mutex_unlock(&vcpu->kvm->arch.config_lock); 1919 return ret; 1920 } 1921 1922 ret = arm64_check_features(vcpu, rd, val); 1923 if (!ret) 1924 kvm_set_vm_id_reg(vcpu->kvm, id, val); 1925 1926 mutex_unlock(&vcpu->kvm->arch.config_lock); 1927 1928 /* 1929 * arm64_check_features() returns -E2BIG to indicate the register's 1930 * feature set is a superset of the maximally-allowed register value. 1931 * While it would be nice to precisely describe this to userspace, the 1932 * existing UAPI for KVM_SET_ONE_REG has it that invalid register 1933 * writes return -EINVAL. 1934 */ 1935 if (ret == -E2BIG) 1936 ret = -EINVAL; 1937 return ret; 1938 } 1939 1940 void kvm_set_vm_id_reg(struct kvm *kvm, u32 reg, u64 val) 1941 { 1942 u64 *p = __vm_id_reg(&kvm->arch, reg); 1943 1944 lockdep_assert_held(&kvm->arch.config_lock); 1945 1946 if (KVM_BUG_ON(kvm_vm_has_ran_once(kvm) || !p, kvm)) 1947 return; 1948 1949 *p = val; 1950 } 1951 1952 static int get_raz_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1953 u64 *val) 1954 { 1955 *val = 0; 1956 return 0; 1957 } 1958 1959 static int set_wi_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1960 u64 val) 1961 { 1962 return 0; 1963 } 1964 1965 static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1966 const struct sys_reg_desc *r) 1967 { 1968 if (p->is_write) 1969 return write_to_read_only(vcpu, p, r); 1970 1971 p->regval = kvm_read_vm_id_reg(vcpu->kvm, SYS_CTR_EL0); 1972 return true; 1973 } 1974 1975 static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1976 const struct sys_reg_desc *r) 1977 { 1978 if (p->is_write) 1979 return write_to_read_only(vcpu, p, r); 1980 1981 p->regval = __vcpu_sys_reg(vcpu, r->reg); 1982 return true; 1983 } 1984 1985 /* 1986 * Fabricate a CLIDR_EL1 value instead of using the real value, which can vary 1987 * by the physical CPU which the vcpu currently resides in. 1988 */ 1989 static u64 reset_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 1990 { 1991 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0); 1992 u64 clidr; 1993 u8 loc; 1994 1995 if ((ctr_el0 & CTR_EL0_IDC)) { 1996 /* 1997 * Data cache clean to the PoU is not required so LoUU and LoUIS 1998 * will not be set and a unified cache, which will be marked as 1999 * LoC, will be added. 2000 * 2001 * If not DIC, let the unified cache L2 so that an instruction 2002 * cache can be added as L1 later. 2003 */ 2004 loc = (ctr_el0 & CTR_EL0_DIC) ? 1 : 2; 2005 clidr = CACHE_TYPE_UNIFIED << CLIDR_CTYPE_SHIFT(loc); 2006 } else { 2007 /* 2008 * Data cache clean to the PoU is required so let L1 have a data 2009 * cache and mark it as LoUU and LoUIS. As L1 has a data cache, 2010 * it can be marked as LoC too. 2011 */ 2012 loc = 1; 2013 clidr = 1 << CLIDR_LOUU_SHIFT; 2014 clidr |= 1 << CLIDR_LOUIS_SHIFT; 2015 clidr |= CACHE_TYPE_DATA << CLIDR_CTYPE_SHIFT(1); 2016 } 2017 2018 /* 2019 * Instruction cache invalidation to the PoU is required so let L1 have 2020 * an instruction cache. If L1 already has a data cache, it will be 2021 * CACHE_TYPE_SEPARATE. 2022 */ 2023 if (!(ctr_el0 & CTR_EL0_DIC)) 2024 clidr |= CACHE_TYPE_INST << CLIDR_CTYPE_SHIFT(1); 2025 2026 clidr |= loc << CLIDR_LOC_SHIFT; 2027 2028 /* 2029 * Add tag cache unified to data cache. Allocation tags and data are 2030 * unified in a cache line so that it looks valid even if there is only 2031 * one cache line. 2032 */ 2033 if (kvm_has_mte(vcpu->kvm)) 2034 clidr |= 2ULL << CLIDR_TTYPE_SHIFT(loc); 2035 2036 __vcpu_sys_reg(vcpu, r->reg) = clidr; 2037 2038 return __vcpu_sys_reg(vcpu, r->reg); 2039 } 2040 2041 static int set_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 2042 u64 val) 2043 { 2044 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0); 2045 u64 idc = !CLIDR_LOC(val) || (!CLIDR_LOUIS(val) && !CLIDR_LOUU(val)); 2046 2047 if ((val & CLIDR_EL1_RES0) || (!(ctr_el0 & CTR_EL0_IDC) && idc)) 2048 return -EINVAL; 2049 2050 __vcpu_sys_reg(vcpu, rd->reg) = val; 2051 2052 return 0; 2053 } 2054 2055 static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2056 const struct sys_reg_desc *r) 2057 { 2058 int reg = r->reg; 2059 2060 if (p->is_write) 2061 vcpu_write_sys_reg(vcpu, p->regval, reg); 2062 else 2063 p->regval = vcpu_read_sys_reg(vcpu, reg); 2064 return true; 2065 } 2066 2067 static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2068 const struct sys_reg_desc *r) 2069 { 2070 u32 csselr; 2071 2072 if (p->is_write) 2073 return write_to_read_only(vcpu, p, r); 2074 2075 csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1); 2076 csselr &= CSSELR_EL1_Level | CSSELR_EL1_InD; 2077 if (csselr < CSSELR_MAX) 2078 p->regval = get_ccsidr(vcpu, csselr); 2079 2080 return true; 2081 } 2082 2083 static unsigned int mte_visibility(const struct kvm_vcpu *vcpu, 2084 const struct sys_reg_desc *rd) 2085 { 2086 if (kvm_has_mte(vcpu->kvm)) 2087 return 0; 2088 2089 return REG_HIDDEN; 2090 } 2091 2092 #define MTE_REG(name) { \ 2093 SYS_DESC(SYS_##name), \ 2094 .access = undef_access, \ 2095 .reset = reset_unknown, \ 2096 .reg = name, \ 2097 .visibility = mte_visibility, \ 2098 } 2099 2100 static unsigned int el2_visibility(const struct kvm_vcpu *vcpu, 2101 const struct sys_reg_desc *rd) 2102 { 2103 if (vcpu_has_nv(vcpu)) 2104 return 0; 2105 2106 return REG_HIDDEN; 2107 } 2108 2109 static bool bad_vncr_trap(struct kvm_vcpu *vcpu, 2110 struct sys_reg_params *p, 2111 const struct sys_reg_desc *r) 2112 { 2113 /* 2114 * We really shouldn't be here, and this is likely the result 2115 * of a misconfigured trap, as this register should target the 2116 * VNCR page, and nothing else. 2117 */ 2118 return bad_trap(vcpu, p, r, 2119 "trap of VNCR-backed register"); 2120 } 2121 2122 static bool bad_redir_trap(struct kvm_vcpu *vcpu, 2123 struct sys_reg_params *p, 2124 const struct sys_reg_desc *r) 2125 { 2126 /* 2127 * We really shouldn't be here, and this is likely the result 2128 * of a misconfigured trap, as this register should target the 2129 * corresponding EL1, and nothing else. 2130 */ 2131 return bad_trap(vcpu, p, r, 2132 "trap of EL2 register redirected to EL1"); 2133 } 2134 2135 #define EL2_REG(name, acc, rst, v) { \ 2136 SYS_DESC(SYS_##name), \ 2137 .access = acc, \ 2138 .reset = rst, \ 2139 .reg = name, \ 2140 .visibility = el2_visibility, \ 2141 .val = v, \ 2142 } 2143 2144 #define EL2_REG_VNCR(name, rst, v) EL2_REG(name, bad_vncr_trap, rst, v) 2145 #define EL2_REG_REDIR(name, rst, v) EL2_REG(name, bad_redir_trap, rst, v) 2146 2147 /* 2148 * Since reset() callback and field val are not used for idregs, they will be 2149 * used for specific purposes for idregs. 2150 * The reset() would return KVM sanitised register value. The value would be the 2151 * same as the host kernel sanitised value if there is no KVM sanitisation. 2152 * The val would be used as a mask indicating writable fields for the idreg. 2153 * Only bits with 1 are writable from userspace. This mask might not be 2154 * necessary in the future whenever all ID registers are enabled as writable 2155 * from userspace. 2156 */ 2157 2158 #define ID_DESC(name) \ 2159 SYS_DESC(SYS_##name), \ 2160 .access = access_id_reg, \ 2161 .get_user = get_id_reg \ 2162 2163 /* sys_reg_desc initialiser for known cpufeature ID registers */ 2164 #define ID_SANITISED(name) { \ 2165 ID_DESC(name), \ 2166 .set_user = set_id_reg, \ 2167 .visibility = id_visibility, \ 2168 .reset = kvm_read_sanitised_id_reg, \ 2169 .val = 0, \ 2170 } 2171 2172 /* sys_reg_desc initialiser for known cpufeature ID registers */ 2173 #define AA32_ID_SANITISED(name) { \ 2174 ID_DESC(name), \ 2175 .set_user = set_id_reg, \ 2176 .visibility = aa32_id_visibility, \ 2177 .reset = kvm_read_sanitised_id_reg, \ 2178 .val = 0, \ 2179 } 2180 2181 /* sys_reg_desc initialiser for writable ID registers */ 2182 #define ID_WRITABLE(name, mask) { \ 2183 ID_DESC(name), \ 2184 .set_user = set_id_reg, \ 2185 .visibility = id_visibility, \ 2186 .reset = kvm_read_sanitised_id_reg, \ 2187 .val = mask, \ 2188 } 2189 2190 /* 2191 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID 2192 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2 2193 * (1 <= crm < 8, 0 <= Op2 < 8). 2194 */ 2195 #define ID_UNALLOCATED(crm, op2) { \ 2196 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \ 2197 .access = access_id_reg, \ 2198 .get_user = get_id_reg, \ 2199 .set_user = set_id_reg, \ 2200 .visibility = raz_visibility, \ 2201 .reset = kvm_read_sanitised_id_reg, \ 2202 .val = 0, \ 2203 } 2204 2205 /* 2206 * sys_reg_desc initialiser for known ID registers that we hide from guests. 2207 * For now, these are exposed just like unallocated ID regs: they appear 2208 * RAZ for the guest. 2209 */ 2210 #define ID_HIDDEN(name) { \ 2211 ID_DESC(name), \ 2212 .set_user = set_id_reg, \ 2213 .visibility = raz_visibility, \ 2214 .reset = kvm_read_sanitised_id_reg, \ 2215 .val = 0, \ 2216 } 2217 2218 static bool access_sp_el1(struct kvm_vcpu *vcpu, 2219 struct sys_reg_params *p, 2220 const struct sys_reg_desc *r) 2221 { 2222 if (p->is_write) 2223 __vcpu_sys_reg(vcpu, SP_EL1) = p->regval; 2224 else 2225 p->regval = __vcpu_sys_reg(vcpu, SP_EL1); 2226 2227 return true; 2228 } 2229 2230 static bool access_elr(struct kvm_vcpu *vcpu, 2231 struct sys_reg_params *p, 2232 const struct sys_reg_desc *r) 2233 { 2234 if (p->is_write) 2235 vcpu_write_sys_reg(vcpu, p->regval, ELR_EL1); 2236 else 2237 p->regval = vcpu_read_sys_reg(vcpu, ELR_EL1); 2238 2239 return true; 2240 } 2241 2242 static bool access_spsr(struct kvm_vcpu *vcpu, 2243 struct sys_reg_params *p, 2244 const struct sys_reg_desc *r) 2245 { 2246 if (p->is_write) 2247 __vcpu_sys_reg(vcpu, SPSR_EL1) = p->regval; 2248 else 2249 p->regval = __vcpu_sys_reg(vcpu, SPSR_EL1); 2250 2251 return true; 2252 } 2253 2254 static bool access_cntkctl_el12(struct kvm_vcpu *vcpu, 2255 struct sys_reg_params *p, 2256 const struct sys_reg_desc *r) 2257 { 2258 if (p->is_write) 2259 __vcpu_sys_reg(vcpu, CNTKCTL_EL1) = p->regval; 2260 else 2261 p->regval = __vcpu_sys_reg(vcpu, CNTKCTL_EL1); 2262 2263 return true; 2264 } 2265 2266 static u64 reset_hcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 2267 { 2268 u64 val = r->val; 2269 2270 if (!cpus_have_final_cap(ARM64_HAS_HCR_NV1)) 2271 val |= HCR_E2H; 2272 2273 return __vcpu_sys_reg(vcpu, r->reg) = val; 2274 } 2275 2276 static unsigned int sve_el2_visibility(const struct kvm_vcpu *vcpu, 2277 const struct sys_reg_desc *rd) 2278 { 2279 unsigned int r; 2280 2281 r = el2_visibility(vcpu, rd); 2282 if (r) 2283 return r; 2284 2285 return sve_visibility(vcpu, rd); 2286 } 2287 2288 static bool access_zcr_el2(struct kvm_vcpu *vcpu, 2289 struct sys_reg_params *p, 2290 const struct sys_reg_desc *r) 2291 { 2292 unsigned int vq; 2293 2294 if (guest_hyp_sve_traps_enabled(vcpu)) { 2295 kvm_inject_nested_sve_trap(vcpu); 2296 return true; 2297 } 2298 2299 if (!p->is_write) { 2300 p->regval = vcpu_read_sys_reg(vcpu, ZCR_EL2); 2301 return true; 2302 } 2303 2304 vq = SYS_FIELD_GET(ZCR_ELx, LEN, p->regval) + 1; 2305 vq = min(vq, vcpu_sve_max_vq(vcpu)); 2306 vcpu_write_sys_reg(vcpu, vq - 1, ZCR_EL2); 2307 return true; 2308 } 2309 2310 static unsigned int s1poe_visibility(const struct kvm_vcpu *vcpu, 2311 const struct sys_reg_desc *rd) 2312 { 2313 if (kvm_has_feat(vcpu->kvm, ID_AA64MMFR3_EL1, S1POE, IMP)) 2314 return 0; 2315 2316 return REG_HIDDEN; 2317 } 2318 2319 /* 2320 * Architected system registers. 2321 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2 2322 * 2323 * Debug handling: We do trap most, if not all debug related system 2324 * registers. The implementation is good enough to ensure that a guest 2325 * can use these with minimal performance degradation. The drawback is 2326 * that we don't implement any of the external debug architecture. 2327 * This should be revisited if we ever encounter a more demanding 2328 * guest... 2329 */ 2330 static const struct sys_reg_desc sys_reg_descs[] = { 2331 DBG_BCR_BVR_WCR_WVR_EL1(0), 2332 DBG_BCR_BVR_WCR_WVR_EL1(1), 2333 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 }, 2334 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 }, 2335 DBG_BCR_BVR_WCR_WVR_EL1(2), 2336 DBG_BCR_BVR_WCR_WVR_EL1(3), 2337 DBG_BCR_BVR_WCR_WVR_EL1(4), 2338 DBG_BCR_BVR_WCR_WVR_EL1(5), 2339 DBG_BCR_BVR_WCR_WVR_EL1(6), 2340 DBG_BCR_BVR_WCR_WVR_EL1(7), 2341 DBG_BCR_BVR_WCR_WVR_EL1(8), 2342 DBG_BCR_BVR_WCR_WVR_EL1(9), 2343 DBG_BCR_BVR_WCR_WVR_EL1(10), 2344 DBG_BCR_BVR_WCR_WVR_EL1(11), 2345 DBG_BCR_BVR_WCR_WVR_EL1(12), 2346 DBG_BCR_BVR_WCR_WVR_EL1(13), 2347 DBG_BCR_BVR_WCR_WVR_EL1(14), 2348 DBG_BCR_BVR_WCR_WVR_EL1(15), 2349 2350 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi }, 2351 { SYS_DESC(SYS_OSLAR_EL1), trap_oslar_el1 }, 2352 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1, 2353 OSLSR_EL1_OSLM_IMPLEMENTED, .set_user = set_oslsr_el1, }, 2354 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi }, 2355 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi }, 2356 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi }, 2357 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi }, 2358 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 }, 2359 2360 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi }, 2361 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi }, 2362 // DBGDTR[TR]X_EL0 share the same encoding 2363 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi }, 2364 2365 { SYS_DESC(SYS_DBGVCR32_EL2), undef_access, reset_val, DBGVCR32_EL2, 0 }, 2366 2367 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 }, 2368 2369 /* 2370 * ID regs: all ID_SANITISED() entries here must have corresponding 2371 * entries in arm64_ftr_regs[]. 2372 */ 2373 2374 /* AArch64 mappings of the AArch32 ID registers */ 2375 /* CRm=1 */ 2376 AA32_ID_SANITISED(ID_PFR0_EL1), 2377 AA32_ID_SANITISED(ID_PFR1_EL1), 2378 { SYS_DESC(SYS_ID_DFR0_EL1), 2379 .access = access_id_reg, 2380 .get_user = get_id_reg, 2381 .set_user = set_id_dfr0_el1, 2382 .visibility = aa32_id_visibility, 2383 .reset = read_sanitised_id_dfr0_el1, 2384 .val = ID_DFR0_EL1_PerfMon_MASK | 2385 ID_DFR0_EL1_CopDbg_MASK, }, 2386 ID_HIDDEN(ID_AFR0_EL1), 2387 AA32_ID_SANITISED(ID_MMFR0_EL1), 2388 AA32_ID_SANITISED(ID_MMFR1_EL1), 2389 AA32_ID_SANITISED(ID_MMFR2_EL1), 2390 AA32_ID_SANITISED(ID_MMFR3_EL1), 2391 2392 /* CRm=2 */ 2393 AA32_ID_SANITISED(ID_ISAR0_EL1), 2394 AA32_ID_SANITISED(ID_ISAR1_EL1), 2395 AA32_ID_SANITISED(ID_ISAR2_EL1), 2396 AA32_ID_SANITISED(ID_ISAR3_EL1), 2397 AA32_ID_SANITISED(ID_ISAR4_EL1), 2398 AA32_ID_SANITISED(ID_ISAR5_EL1), 2399 AA32_ID_SANITISED(ID_MMFR4_EL1), 2400 AA32_ID_SANITISED(ID_ISAR6_EL1), 2401 2402 /* CRm=3 */ 2403 AA32_ID_SANITISED(MVFR0_EL1), 2404 AA32_ID_SANITISED(MVFR1_EL1), 2405 AA32_ID_SANITISED(MVFR2_EL1), 2406 ID_UNALLOCATED(3,3), 2407 AA32_ID_SANITISED(ID_PFR2_EL1), 2408 ID_HIDDEN(ID_DFR1_EL1), 2409 AA32_ID_SANITISED(ID_MMFR5_EL1), 2410 ID_UNALLOCATED(3,7), 2411 2412 /* AArch64 ID registers */ 2413 /* CRm=4 */ 2414 { SYS_DESC(SYS_ID_AA64PFR0_EL1), 2415 .access = access_id_reg, 2416 .get_user = get_id_reg, 2417 .set_user = set_id_reg, 2418 .reset = read_sanitised_id_aa64pfr0_el1, 2419 .val = ~(ID_AA64PFR0_EL1_AMU | 2420 ID_AA64PFR0_EL1_MPAM | 2421 ID_AA64PFR0_EL1_SVE | 2422 ID_AA64PFR0_EL1_RAS | 2423 ID_AA64PFR0_EL1_AdvSIMD | 2424 ID_AA64PFR0_EL1_FP), }, 2425 ID_WRITABLE(ID_AA64PFR1_EL1, ~(ID_AA64PFR1_EL1_PFAR | 2426 ID_AA64PFR1_EL1_DF2 | 2427 ID_AA64PFR1_EL1_MTEX | 2428 ID_AA64PFR1_EL1_THE | 2429 ID_AA64PFR1_EL1_GCS | 2430 ID_AA64PFR1_EL1_MTE_frac | 2431 ID_AA64PFR1_EL1_NMI | 2432 ID_AA64PFR1_EL1_RNDR_trap | 2433 ID_AA64PFR1_EL1_SME | 2434 ID_AA64PFR1_EL1_RES0 | 2435 ID_AA64PFR1_EL1_MPAM_frac | 2436 ID_AA64PFR1_EL1_RAS_frac | 2437 ID_AA64PFR1_EL1_MTE)), 2438 ID_WRITABLE(ID_AA64PFR2_EL1, ID_AA64PFR2_EL1_FPMR), 2439 ID_UNALLOCATED(4,3), 2440 ID_WRITABLE(ID_AA64ZFR0_EL1, ~ID_AA64ZFR0_EL1_RES0), 2441 ID_HIDDEN(ID_AA64SMFR0_EL1), 2442 ID_UNALLOCATED(4,6), 2443 ID_WRITABLE(ID_AA64FPFR0_EL1, ~ID_AA64FPFR0_EL1_RES0), 2444 2445 /* CRm=5 */ 2446 { SYS_DESC(SYS_ID_AA64DFR0_EL1), 2447 .access = access_id_reg, 2448 .get_user = get_id_reg, 2449 .set_user = set_id_aa64dfr0_el1, 2450 .reset = read_sanitised_id_aa64dfr0_el1, 2451 /* 2452 * Prior to FEAT_Debugv8.9, the architecture defines context-aware 2453 * breakpoints (CTX_CMPs) as the highest numbered breakpoints (BRPs). 2454 * KVM does not trap + emulate the breakpoint registers, and as such 2455 * cannot support a layout that misaligns with the underlying hardware. 2456 * While it may be possible to describe a subset that aligns with 2457 * hardware, just prevent changes to BRPs and CTX_CMPs altogether for 2458 * simplicity. 2459 * 2460 * See DDI0487K.a, section D2.8.3 Breakpoint types and linking 2461 * of breakpoints for more details. 2462 */ 2463 .val = ID_AA64DFR0_EL1_DoubleLock_MASK | 2464 ID_AA64DFR0_EL1_WRPs_MASK | 2465 ID_AA64DFR0_EL1_PMUVer_MASK | 2466 ID_AA64DFR0_EL1_DebugVer_MASK, }, 2467 ID_SANITISED(ID_AA64DFR1_EL1), 2468 ID_UNALLOCATED(5,2), 2469 ID_UNALLOCATED(5,3), 2470 ID_HIDDEN(ID_AA64AFR0_EL1), 2471 ID_HIDDEN(ID_AA64AFR1_EL1), 2472 ID_UNALLOCATED(5,6), 2473 ID_UNALLOCATED(5,7), 2474 2475 /* CRm=6 */ 2476 ID_WRITABLE(ID_AA64ISAR0_EL1, ~ID_AA64ISAR0_EL1_RES0), 2477 ID_WRITABLE(ID_AA64ISAR1_EL1, ~(ID_AA64ISAR1_EL1_GPI | 2478 ID_AA64ISAR1_EL1_GPA | 2479 ID_AA64ISAR1_EL1_API | 2480 ID_AA64ISAR1_EL1_APA)), 2481 ID_WRITABLE(ID_AA64ISAR2_EL1, ~(ID_AA64ISAR2_EL1_RES0 | 2482 ID_AA64ISAR2_EL1_APA3 | 2483 ID_AA64ISAR2_EL1_GPA3)), 2484 ID_UNALLOCATED(6,3), 2485 ID_UNALLOCATED(6,4), 2486 ID_UNALLOCATED(6,5), 2487 ID_UNALLOCATED(6,6), 2488 ID_UNALLOCATED(6,7), 2489 2490 /* CRm=7 */ 2491 ID_WRITABLE(ID_AA64MMFR0_EL1, ~(ID_AA64MMFR0_EL1_RES0 | 2492 ID_AA64MMFR0_EL1_TGRAN4_2 | 2493 ID_AA64MMFR0_EL1_TGRAN64_2 | 2494 ID_AA64MMFR0_EL1_TGRAN16_2)), 2495 ID_WRITABLE(ID_AA64MMFR1_EL1, ~(ID_AA64MMFR1_EL1_RES0 | 2496 ID_AA64MMFR1_EL1_HCX | 2497 ID_AA64MMFR1_EL1_TWED | 2498 ID_AA64MMFR1_EL1_XNX | 2499 ID_AA64MMFR1_EL1_VH | 2500 ID_AA64MMFR1_EL1_VMIDBits)), 2501 ID_WRITABLE(ID_AA64MMFR2_EL1, ~(ID_AA64MMFR2_EL1_RES0 | 2502 ID_AA64MMFR2_EL1_EVT | 2503 ID_AA64MMFR2_EL1_FWB | 2504 ID_AA64MMFR2_EL1_IDS | 2505 ID_AA64MMFR2_EL1_NV | 2506 ID_AA64MMFR2_EL1_CCIDX)), 2507 ID_WRITABLE(ID_AA64MMFR3_EL1, (ID_AA64MMFR3_EL1_TCRX | 2508 ID_AA64MMFR3_EL1_S1PIE | 2509 ID_AA64MMFR3_EL1_S1POE)), 2510 ID_SANITISED(ID_AA64MMFR4_EL1), 2511 ID_UNALLOCATED(7,5), 2512 ID_UNALLOCATED(7,6), 2513 ID_UNALLOCATED(7,7), 2514 2515 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 }, 2516 { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 }, 2517 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 }, 2518 2519 MTE_REG(RGSR_EL1), 2520 MTE_REG(GCR_EL1), 2521 2522 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility }, 2523 { SYS_DESC(SYS_TRFCR_EL1), undef_access }, 2524 { SYS_DESC(SYS_SMPRI_EL1), undef_access }, 2525 { SYS_DESC(SYS_SMCR_EL1), undef_access }, 2526 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 }, 2527 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 }, 2528 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 }, 2529 { SYS_DESC(SYS_TCR2_EL1), access_vm_reg, reset_val, TCR2_EL1, 0 }, 2530 2531 PTRAUTH_KEY(APIA), 2532 PTRAUTH_KEY(APIB), 2533 PTRAUTH_KEY(APDA), 2534 PTRAUTH_KEY(APDB), 2535 PTRAUTH_KEY(APGA), 2536 2537 { SYS_DESC(SYS_SPSR_EL1), access_spsr}, 2538 { SYS_DESC(SYS_ELR_EL1), access_elr}, 2539 2540 { SYS_DESC(SYS_ICC_PMR_EL1), undef_access }, 2541 2542 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 }, 2543 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 }, 2544 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 }, 2545 2546 { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi }, 2547 { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi }, 2548 { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi }, 2549 { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi }, 2550 { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi }, 2551 { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi }, 2552 { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi }, 2553 { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi }, 2554 2555 MTE_REG(TFSR_EL1), 2556 MTE_REG(TFSRE0_EL1), 2557 2558 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 }, 2559 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 }, 2560 2561 { SYS_DESC(SYS_PMSCR_EL1), undef_access }, 2562 { SYS_DESC(SYS_PMSNEVFR_EL1), undef_access }, 2563 { SYS_DESC(SYS_PMSICR_EL1), undef_access }, 2564 { SYS_DESC(SYS_PMSIRR_EL1), undef_access }, 2565 { SYS_DESC(SYS_PMSFCR_EL1), undef_access }, 2566 { SYS_DESC(SYS_PMSEVFR_EL1), undef_access }, 2567 { SYS_DESC(SYS_PMSLATFR_EL1), undef_access }, 2568 { SYS_DESC(SYS_PMSIDR_EL1), undef_access }, 2569 { SYS_DESC(SYS_PMBLIMITR_EL1), undef_access }, 2570 { SYS_DESC(SYS_PMBPTR_EL1), undef_access }, 2571 { SYS_DESC(SYS_PMBSR_EL1), undef_access }, 2572 /* PMBIDR_EL1 is not trapped */ 2573 2574 { PMU_SYS_REG(PMINTENSET_EL1), 2575 .access = access_pminten, .reg = PMINTENSET_EL1, 2576 .get_user = get_pmreg, .set_user = set_pmreg }, 2577 { PMU_SYS_REG(PMINTENCLR_EL1), 2578 .access = access_pminten, .reg = PMINTENSET_EL1, 2579 .get_user = get_pmreg, .set_user = set_pmreg }, 2580 { SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi }, 2581 2582 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 }, 2583 { SYS_DESC(SYS_PIRE0_EL1), NULL, reset_unknown, PIRE0_EL1 }, 2584 { SYS_DESC(SYS_PIR_EL1), NULL, reset_unknown, PIR_EL1 }, 2585 { SYS_DESC(SYS_POR_EL1), NULL, reset_unknown, POR_EL1, 2586 .visibility = s1poe_visibility }, 2587 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 }, 2588 2589 { SYS_DESC(SYS_LORSA_EL1), trap_loregion }, 2590 { SYS_DESC(SYS_LOREA_EL1), trap_loregion }, 2591 { SYS_DESC(SYS_LORN_EL1), trap_loregion }, 2592 { SYS_DESC(SYS_LORC_EL1), trap_loregion }, 2593 { SYS_DESC(SYS_LORID_EL1), trap_loregion }, 2594 2595 { SYS_DESC(SYS_VBAR_EL1), access_rw, reset_val, VBAR_EL1, 0 }, 2596 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 }, 2597 2598 { SYS_DESC(SYS_ICC_IAR0_EL1), undef_access }, 2599 { SYS_DESC(SYS_ICC_EOIR0_EL1), undef_access }, 2600 { SYS_DESC(SYS_ICC_HPPIR0_EL1), undef_access }, 2601 { SYS_DESC(SYS_ICC_BPR0_EL1), undef_access }, 2602 { SYS_DESC(SYS_ICC_AP0R0_EL1), undef_access }, 2603 { SYS_DESC(SYS_ICC_AP0R1_EL1), undef_access }, 2604 { SYS_DESC(SYS_ICC_AP0R2_EL1), undef_access }, 2605 { SYS_DESC(SYS_ICC_AP0R3_EL1), undef_access }, 2606 { SYS_DESC(SYS_ICC_AP1R0_EL1), undef_access }, 2607 { SYS_DESC(SYS_ICC_AP1R1_EL1), undef_access }, 2608 { SYS_DESC(SYS_ICC_AP1R2_EL1), undef_access }, 2609 { SYS_DESC(SYS_ICC_AP1R3_EL1), undef_access }, 2610 { SYS_DESC(SYS_ICC_DIR_EL1), undef_access }, 2611 { SYS_DESC(SYS_ICC_RPR_EL1), undef_access }, 2612 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi }, 2613 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi }, 2614 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi }, 2615 { SYS_DESC(SYS_ICC_IAR1_EL1), undef_access }, 2616 { SYS_DESC(SYS_ICC_EOIR1_EL1), undef_access }, 2617 { SYS_DESC(SYS_ICC_HPPIR1_EL1), undef_access }, 2618 { SYS_DESC(SYS_ICC_BPR1_EL1), undef_access }, 2619 { SYS_DESC(SYS_ICC_CTLR_EL1), undef_access }, 2620 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre }, 2621 { SYS_DESC(SYS_ICC_IGRPEN0_EL1), undef_access }, 2622 { SYS_DESC(SYS_ICC_IGRPEN1_EL1), undef_access }, 2623 2624 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 }, 2625 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 }, 2626 2627 { SYS_DESC(SYS_ACCDATA_EL1), undef_access }, 2628 2629 { SYS_DESC(SYS_SCXTNUM_EL1), undef_access }, 2630 2631 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0}, 2632 2633 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr }, 2634 { SYS_DESC(SYS_CLIDR_EL1), access_clidr, reset_clidr, CLIDR_EL1, 2635 .set_user = set_clidr, .val = ~CLIDR_EL1_RES0 }, 2636 { SYS_DESC(SYS_CCSIDR2_EL1), undef_access }, 2637 { SYS_DESC(SYS_SMIDR_EL1), undef_access }, 2638 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, 2639 ID_WRITABLE(CTR_EL0, CTR_EL0_DIC_MASK | 2640 CTR_EL0_IDC_MASK | 2641 CTR_EL0_DminLine_MASK | 2642 CTR_EL0_IminLine_MASK), 2643 { SYS_DESC(SYS_SVCR), undef_access, reset_val, SVCR, 0, .visibility = sme_visibility }, 2644 { SYS_DESC(SYS_FPMR), undef_access, reset_val, FPMR, 0, .visibility = fp8_visibility }, 2645 2646 { PMU_SYS_REG(PMCR_EL0), .access = access_pmcr, .reset = reset_pmcr, 2647 .reg = PMCR_EL0, .get_user = get_pmcr, .set_user = set_pmcr }, 2648 { PMU_SYS_REG(PMCNTENSET_EL0), 2649 .access = access_pmcnten, .reg = PMCNTENSET_EL0, 2650 .get_user = get_pmreg, .set_user = set_pmreg }, 2651 { PMU_SYS_REG(PMCNTENCLR_EL0), 2652 .access = access_pmcnten, .reg = PMCNTENSET_EL0, 2653 .get_user = get_pmreg, .set_user = set_pmreg }, 2654 { PMU_SYS_REG(PMOVSCLR_EL0), 2655 .access = access_pmovs, .reg = PMOVSSET_EL0, 2656 .get_user = get_pmreg, .set_user = set_pmreg }, 2657 /* 2658 * PM_SWINC_EL0 is exposed to userspace as RAZ/WI, as it was 2659 * previously (and pointlessly) advertised in the past... 2660 */ 2661 { PMU_SYS_REG(PMSWINC_EL0), 2662 .get_user = get_raz_reg, .set_user = set_wi_reg, 2663 .access = access_pmswinc, .reset = NULL }, 2664 { PMU_SYS_REG(PMSELR_EL0), 2665 .access = access_pmselr, .reset = reset_pmselr, .reg = PMSELR_EL0 }, 2666 { PMU_SYS_REG(PMCEID0_EL0), 2667 .access = access_pmceid, .reset = NULL }, 2668 { PMU_SYS_REG(PMCEID1_EL0), 2669 .access = access_pmceid, .reset = NULL }, 2670 { PMU_SYS_REG(PMCCNTR_EL0), 2671 .access = access_pmu_evcntr, .reset = reset_unknown, 2672 .reg = PMCCNTR_EL0, .get_user = get_pmu_evcntr}, 2673 { PMU_SYS_REG(PMXEVTYPER_EL0), 2674 .access = access_pmu_evtyper, .reset = NULL }, 2675 { PMU_SYS_REG(PMXEVCNTR_EL0), 2676 .access = access_pmu_evcntr, .reset = NULL }, 2677 /* 2678 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero 2679 * in 32bit mode. Here we choose to reset it as zero for consistency. 2680 */ 2681 { PMU_SYS_REG(PMUSERENR_EL0), .access = access_pmuserenr, 2682 .reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 }, 2683 { PMU_SYS_REG(PMOVSSET_EL0), 2684 .access = access_pmovs, .reg = PMOVSSET_EL0, 2685 .get_user = get_pmreg, .set_user = set_pmreg }, 2686 2687 { SYS_DESC(SYS_POR_EL0), NULL, reset_unknown, POR_EL0, 2688 .visibility = s1poe_visibility }, 2689 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 }, 2690 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 }, 2691 { SYS_DESC(SYS_TPIDR2_EL0), undef_access }, 2692 2693 { SYS_DESC(SYS_SCXTNUM_EL0), undef_access }, 2694 2695 { SYS_DESC(SYS_AMCR_EL0), undef_access }, 2696 { SYS_DESC(SYS_AMCFGR_EL0), undef_access }, 2697 { SYS_DESC(SYS_AMCGCR_EL0), undef_access }, 2698 { SYS_DESC(SYS_AMUSERENR_EL0), undef_access }, 2699 { SYS_DESC(SYS_AMCNTENCLR0_EL0), undef_access }, 2700 { SYS_DESC(SYS_AMCNTENSET0_EL0), undef_access }, 2701 { SYS_DESC(SYS_AMCNTENCLR1_EL0), undef_access }, 2702 { SYS_DESC(SYS_AMCNTENSET1_EL0), undef_access }, 2703 AMU_AMEVCNTR0_EL0(0), 2704 AMU_AMEVCNTR0_EL0(1), 2705 AMU_AMEVCNTR0_EL0(2), 2706 AMU_AMEVCNTR0_EL0(3), 2707 AMU_AMEVCNTR0_EL0(4), 2708 AMU_AMEVCNTR0_EL0(5), 2709 AMU_AMEVCNTR0_EL0(6), 2710 AMU_AMEVCNTR0_EL0(7), 2711 AMU_AMEVCNTR0_EL0(8), 2712 AMU_AMEVCNTR0_EL0(9), 2713 AMU_AMEVCNTR0_EL0(10), 2714 AMU_AMEVCNTR0_EL0(11), 2715 AMU_AMEVCNTR0_EL0(12), 2716 AMU_AMEVCNTR0_EL0(13), 2717 AMU_AMEVCNTR0_EL0(14), 2718 AMU_AMEVCNTR0_EL0(15), 2719 AMU_AMEVTYPER0_EL0(0), 2720 AMU_AMEVTYPER0_EL0(1), 2721 AMU_AMEVTYPER0_EL0(2), 2722 AMU_AMEVTYPER0_EL0(3), 2723 AMU_AMEVTYPER0_EL0(4), 2724 AMU_AMEVTYPER0_EL0(5), 2725 AMU_AMEVTYPER0_EL0(6), 2726 AMU_AMEVTYPER0_EL0(7), 2727 AMU_AMEVTYPER0_EL0(8), 2728 AMU_AMEVTYPER0_EL0(9), 2729 AMU_AMEVTYPER0_EL0(10), 2730 AMU_AMEVTYPER0_EL0(11), 2731 AMU_AMEVTYPER0_EL0(12), 2732 AMU_AMEVTYPER0_EL0(13), 2733 AMU_AMEVTYPER0_EL0(14), 2734 AMU_AMEVTYPER0_EL0(15), 2735 AMU_AMEVCNTR1_EL0(0), 2736 AMU_AMEVCNTR1_EL0(1), 2737 AMU_AMEVCNTR1_EL0(2), 2738 AMU_AMEVCNTR1_EL0(3), 2739 AMU_AMEVCNTR1_EL0(4), 2740 AMU_AMEVCNTR1_EL0(5), 2741 AMU_AMEVCNTR1_EL0(6), 2742 AMU_AMEVCNTR1_EL0(7), 2743 AMU_AMEVCNTR1_EL0(8), 2744 AMU_AMEVCNTR1_EL0(9), 2745 AMU_AMEVCNTR1_EL0(10), 2746 AMU_AMEVCNTR1_EL0(11), 2747 AMU_AMEVCNTR1_EL0(12), 2748 AMU_AMEVCNTR1_EL0(13), 2749 AMU_AMEVCNTR1_EL0(14), 2750 AMU_AMEVCNTR1_EL0(15), 2751 AMU_AMEVTYPER1_EL0(0), 2752 AMU_AMEVTYPER1_EL0(1), 2753 AMU_AMEVTYPER1_EL0(2), 2754 AMU_AMEVTYPER1_EL0(3), 2755 AMU_AMEVTYPER1_EL0(4), 2756 AMU_AMEVTYPER1_EL0(5), 2757 AMU_AMEVTYPER1_EL0(6), 2758 AMU_AMEVTYPER1_EL0(7), 2759 AMU_AMEVTYPER1_EL0(8), 2760 AMU_AMEVTYPER1_EL0(9), 2761 AMU_AMEVTYPER1_EL0(10), 2762 AMU_AMEVTYPER1_EL0(11), 2763 AMU_AMEVTYPER1_EL0(12), 2764 AMU_AMEVTYPER1_EL0(13), 2765 AMU_AMEVTYPER1_EL0(14), 2766 AMU_AMEVTYPER1_EL0(15), 2767 2768 { SYS_DESC(SYS_CNTPCT_EL0), access_arch_timer }, 2769 { SYS_DESC(SYS_CNTPCTSS_EL0), access_arch_timer }, 2770 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer }, 2771 { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer }, 2772 { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer }, 2773 2774 /* PMEVCNTRn_EL0 */ 2775 PMU_PMEVCNTR_EL0(0), 2776 PMU_PMEVCNTR_EL0(1), 2777 PMU_PMEVCNTR_EL0(2), 2778 PMU_PMEVCNTR_EL0(3), 2779 PMU_PMEVCNTR_EL0(4), 2780 PMU_PMEVCNTR_EL0(5), 2781 PMU_PMEVCNTR_EL0(6), 2782 PMU_PMEVCNTR_EL0(7), 2783 PMU_PMEVCNTR_EL0(8), 2784 PMU_PMEVCNTR_EL0(9), 2785 PMU_PMEVCNTR_EL0(10), 2786 PMU_PMEVCNTR_EL0(11), 2787 PMU_PMEVCNTR_EL0(12), 2788 PMU_PMEVCNTR_EL0(13), 2789 PMU_PMEVCNTR_EL0(14), 2790 PMU_PMEVCNTR_EL0(15), 2791 PMU_PMEVCNTR_EL0(16), 2792 PMU_PMEVCNTR_EL0(17), 2793 PMU_PMEVCNTR_EL0(18), 2794 PMU_PMEVCNTR_EL0(19), 2795 PMU_PMEVCNTR_EL0(20), 2796 PMU_PMEVCNTR_EL0(21), 2797 PMU_PMEVCNTR_EL0(22), 2798 PMU_PMEVCNTR_EL0(23), 2799 PMU_PMEVCNTR_EL0(24), 2800 PMU_PMEVCNTR_EL0(25), 2801 PMU_PMEVCNTR_EL0(26), 2802 PMU_PMEVCNTR_EL0(27), 2803 PMU_PMEVCNTR_EL0(28), 2804 PMU_PMEVCNTR_EL0(29), 2805 PMU_PMEVCNTR_EL0(30), 2806 /* PMEVTYPERn_EL0 */ 2807 PMU_PMEVTYPER_EL0(0), 2808 PMU_PMEVTYPER_EL0(1), 2809 PMU_PMEVTYPER_EL0(2), 2810 PMU_PMEVTYPER_EL0(3), 2811 PMU_PMEVTYPER_EL0(4), 2812 PMU_PMEVTYPER_EL0(5), 2813 PMU_PMEVTYPER_EL0(6), 2814 PMU_PMEVTYPER_EL0(7), 2815 PMU_PMEVTYPER_EL0(8), 2816 PMU_PMEVTYPER_EL0(9), 2817 PMU_PMEVTYPER_EL0(10), 2818 PMU_PMEVTYPER_EL0(11), 2819 PMU_PMEVTYPER_EL0(12), 2820 PMU_PMEVTYPER_EL0(13), 2821 PMU_PMEVTYPER_EL0(14), 2822 PMU_PMEVTYPER_EL0(15), 2823 PMU_PMEVTYPER_EL0(16), 2824 PMU_PMEVTYPER_EL0(17), 2825 PMU_PMEVTYPER_EL0(18), 2826 PMU_PMEVTYPER_EL0(19), 2827 PMU_PMEVTYPER_EL0(20), 2828 PMU_PMEVTYPER_EL0(21), 2829 PMU_PMEVTYPER_EL0(22), 2830 PMU_PMEVTYPER_EL0(23), 2831 PMU_PMEVTYPER_EL0(24), 2832 PMU_PMEVTYPER_EL0(25), 2833 PMU_PMEVTYPER_EL0(26), 2834 PMU_PMEVTYPER_EL0(27), 2835 PMU_PMEVTYPER_EL0(28), 2836 PMU_PMEVTYPER_EL0(29), 2837 PMU_PMEVTYPER_EL0(30), 2838 /* 2839 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero 2840 * in 32bit mode. Here we choose to reset it as zero for consistency. 2841 */ 2842 { PMU_SYS_REG(PMCCFILTR_EL0), .access = access_pmu_evtyper, 2843 .reset = reset_val, .reg = PMCCFILTR_EL0, .val = 0 }, 2844 2845 EL2_REG_VNCR(VPIDR_EL2, reset_unknown, 0), 2846 EL2_REG_VNCR(VMPIDR_EL2, reset_unknown, 0), 2847 EL2_REG(SCTLR_EL2, access_rw, reset_val, SCTLR_EL2_RES1), 2848 EL2_REG(ACTLR_EL2, access_rw, reset_val, 0), 2849 EL2_REG_VNCR(HCR_EL2, reset_hcr, 0), 2850 EL2_REG(MDCR_EL2, access_rw, reset_val, 0), 2851 EL2_REG(CPTR_EL2, access_rw, reset_val, CPTR_NVHE_EL2_RES1), 2852 EL2_REG_VNCR(HSTR_EL2, reset_val, 0), 2853 EL2_REG_VNCR(HFGRTR_EL2, reset_val, 0), 2854 EL2_REG_VNCR(HFGWTR_EL2, reset_val, 0), 2855 EL2_REG_VNCR(HFGITR_EL2, reset_val, 0), 2856 EL2_REG_VNCR(HACR_EL2, reset_val, 0), 2857 2858 { SYS_DESC(SYS_ZCR_EL2), .access = access_zcr_el2, .reset = reset_val, 2859 .visibility = sve_el2_visibility, .reg = ZCR_EL2 }, 2860 2861 EL2_REG_VNCR(HCRX_EL2, reset_val, 0), 2862 2863 EL2_REG(TTBR0_EL2, access_rw, reset_val, 0), 2864 EL2_REG(TTBR1_EL2, access_rw, reset_val, 0), 2865 EL2_REG(TCR_EL2, access_rw, reset_val, TCR_EL2_RES1), 2866 EL2_REG_VNCR(VTTBR_EL2, reset_val, 0), 2867 EL2_REG_VNCR(VTCR_EL2, reset_val, 0), 2868 2869 { SYS_DESC(SYS_DACR32_EL2), undef_access, reset_unknown, DACR32_EL2 }, 2870 EL2_REG_VNCR(HDFGRTR_EL2, reset_val, 0), 2871 EL2_REG_VNCR(HDFGWTR_EL2, reset_val, 0), 2872 EL2_REG_VNCR(HAFGRTR_EL2, reset_val, 0), 2873 EL2_REG_REDIR(SPSR_EL2, reset_val, 0), 2874 EL2_REG_REDIR(ELR_EL2, reset_val, 0), 2875 { SYS_DESC(SYS_SP_EL1), access_sp_el1}, 2876 2877 /* AArch32 SPSR_* are RES0 if trapped from a NV guest */ 2878 { SYS_DESC(SYS_SPSR_irq), .access = trap_raz_wi }, 2879 { SYS_DESC(SYS_SPSR_abt), .access = trap_raz_wi }, 2880 { SYS_DESC(SYS_SPSR_und), .access = trap_raz_wi }, 2881 { SYS_DESC(SYS_SPSR_fiq), .access = trap_raz_wi }, 2882 2883 { SYS_DESC(SYS_IFSR32_EL2), undef_access, reset_unknown, IFSR32_EL2 }, 2884 EL2_REG(AFSR0_EL2, access_rw, reset_val, 0), 2885 EL2_REG(AFSR1_EL2, access_rw, reset_val, 0), 2886 EL2_REG_REDIR(ESR_EL2, reset_val, 0), 2887 { SYS_DESC(SYS_FPEXC32_EL2), undef_access, reset_val, FPEXC32_EL2, 0x700 }, 2888 2889 EL2_REG_REDIR(FAR_EL2, reset_val, 0), 2890 EL2_REG(HPFAR_EL2, access_rw, reset_val, 0), 2891 2892 EL2_REG(MAIR_EL2, access_rw, reset_val, 0), 2893 EL2_REG(AMAIR_EL2, access_rw, reset_val, 0), 2894 2895 EL2_REG(VBAR_EL2, access_rw, reset_val, 0), 2896 EL2_REG(RVBAR_EL2, access_rw, reset_val, 0), 2897 { SYS_DESC(SYS_RMR_EL2), undef_access }, 2898 2899 EL2_REG_VNCR(ICH_HCR_EL2, reset_val, 0), 2900 2901 EL2_REG(CONTEXTIDR_EL2, access_rw, reset_val, 0), 2902 EL2_REG(TPIDR_EL2, access_rw, reset_val, 0), 2903 2904 EL2_REG_VNCR(CNTVOFF_EL2, reset_val, 0), 2905 EL2_REG(CNTHCTL_EL2, access_rw, reset_val, 0), 2906 2907 { SYS_DESC(SYS_CNTKCTL_EL12), access_cntkctl_el12 }, 2908 2909 EL2_REG(SP_EL2, NULL, reset_unknown, 0), 2910 }; 2911 2912 static bool handle_at_s1e01(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2913 const struct sys_reg_desc *r) 2914 { 2915 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 2916 2917 __kvm_at_s1e01(vcpu, op, p->regval); 2918 2919 return true; 2920 } 2921 2922 static bool handle_at_s1e2(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2923 const struct sys_reg_desc *r) 2924 { 2925 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 2926 2927 /* There is no FGT associated with AT S1E2A :-( */ 2928 if (op == OP_AT_S1E2A && 2929 !kvm_has_feat(vcpu->kvm, ID_AA64ISAR2_EL1, ATS1A, IMP)) { 2930 kvm_inject_undefined(vcpu); 2931 return false; 2932 } 2933 2934 __kvm_at_s1e2(vcpu, op, p->regval); 2935 2936 return true; 2937 } 2938 2939 static bool handle_at_s12(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2940 const struct sys_reg_desc *r) 2941 { 2942 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 2943 2944 __kvm_at_s12(vcpu, op, p->regval); 2945 2946 return true; 2947 } 2948 2949 static bool kvm_supported_tlbi_s12_op(struct kvm_vcpu *vpcu, u32 instr) 2950 { 2951 struct kvm *kvm = vpcu->kvm; 2952 u8 CRm = sys_reg_CRm(instr); 2953 2954 if (sys_reg_CRn(instr) == TLBI_CRn_nXS && 2955 !kvm_has_feat(kvm, ID_AA64ISAR1_EL1, XS, IMP)) 2956 return false; 2957 2958 if (CRm == TLBI_CRm_nROS && 2959 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 2960 return false; 2961 2962 return true; 2963 } 2964 2965 static bool handle_alle1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2966 const struct sys_reg_desc *r) 2967 { 2968 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 2969 2970 if (!kvm_supported_tlbi_s12_op(vcpu, sys_encoding)) 2971 return undef_access(vcpu, p, r); 2972 2973 write_lock(&vcpu->kvm->mmu_lock); 2974 2975 /* 2976 * Drop all shadow S2s, resulting in S1/S2 TLBIs for each of the 2977 * corresponding VMIDs. 2978 */ 2979 kvm_nested_s2_unmap(vcpu->kvm, true); 2980 2981 write_unlock(&vcpu->kvm->mmu_lock); 2982 2983 return true; 2984 } 2985 2986 static bool kvm_supported_tlbi_ipas2_op(struct kvm_vcpu *vpcu, u32 instr) 2987 { 2988 struct kvm *kvm = vpcu->kvm; 2989 u8 CRm = sys_reg_CRm(instr); 2990 u8 Op2 = sys_reg_Op2(instr); 2991 2992 if (sys_reg_CRn(instr) == TLBI_CRn_nXS && 2993 !kvm_has_feat(kvm, ID_AA64ISAR1_EL1, XS, IMP)) 2994 return false; 2995 2996 if (CRm == TLBI_CRm_IPAIS && (Op2 == 2 || Op2 == 6) && 2997 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE)) 2998 return false; 2999 3000 if (CRm == TLBI_CRm_IPAONS && (Op2 == 0 || Op2 == 4) && 3001 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 3002 return false; 3003 3004 if (CRm == TLBI_CRm_IPAONS && (Op2 == 3 || Op2 == 7) && 3005 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE)) 3006 return false; 3007 3008 return true; 3009 } 3010 3011 /* Only defined here as this is an internal "abstraction" */ 3012 union tlbi_info { 3013 struct { 3014 u64 start; 3015 u64 size; 3016 } range; 3017 3018 struct { 3019 u64 addr; 3020 } ipa; 3021 3022 struct { 3023 u64 addr; 3024 u32 encoding; 3025 } va; 3026 }; 3027 3028 static void s2_mmu_unmap_range(struct kvm_s2_mmu *mmu, 3029 const union tlbi_info *info) 3030 { 3031 /* 3032 * The unmap operation is allowed to drop the MMU lock and block, which 3033 * means that @mmu could be used for a different context than the one 3034 * currently being invalidated. 3035 * 3036 * This behavior is still safe, as: 3037 * 3038 * 1) The vCPU(s) that recycled the MMU are responsible for invalidating 3039 * the entire MMU before reusing it, which still honors the intent 3040 * of a TLBI. 3041 * 3042 * 2) Until the guest TLBI instruction is 'retired' (i.e. increment PC 3043 * and ERET to the guest), other vCPUs are allowed to use stale 3044 * translations. 3045 * 3046 * 3) Accidentally unmapping an unrelated MMU context is nonfatal, and 3047 * at worst may cause more aborts for shadow stage-2 fills. 3048 * 3049 * Dropping the MMU lock also implies that shadow stage-2 fills could 3050 * happen behind the back of the TLBI. This is still safe, though, as 3051 * the L1 needs to put its stage-2 in a consistent state before doing 3052 * the TLBI. 3053 */ 3054 kvm_stage2_unmap_range(mmu, info->range.start, info->range.size, true); 3055 } 3056 3057 static bool handle_vmalls12e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3058 const struct sys_reg_desc *r) 3059 { 3060 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3061 u64 limit, vttbr; 3062 3063 if (!kvm_supported_tlbi_s12_op(vcpu, sys_encoding)) 3064 return undef_access(vcpu, p, r); 3065 3066 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 3067 limit = BIT_ULL(kvm_get_pa_bits(vcpu->kvm)); 3068 3069 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 3070 &(union tlbi_info) { 3071 .range = { 3072 .start = 0, 3073 .size = limit, 3074 }, 3075 }, 3076 s2_mmu_unmap_range); 3077 3078 return true; 3079 } 3080 3081 static bool handle_ripas2e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3082 const struct sys_reg_desc *r) 3083 { 3084 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3085 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 3086 u64 base, range, tg, num, scale; 3087 int shift; 3088 3089 if (!kvm_supported_tlbi_ipas2_op(vcpu, sys_encoding)) 3090 return undef_access(vcpu, p, r); 3091 3092 /* 3093 * Because the shadow S2 structure doesn't necessarily reflect that 3094 * of the guest's S2 (different base granule size, for example), we 3095 * decide to ignore TTL and only use the described range. 3096 */ 3097 tg = FIELD_GET(GENMASK(47, 46), p->regval); 3098 scale = FIELD_GET(GENMASK(45, 44), p->regval); 3099 num = FIELD_GET(GENMASK(43, 39), p->regval); 3100 base = p->regval & GENMASK(36, 0); 3101 3102 switch(tg) { 3103 case 1: 3104 shift = 12; 3105 break; 3106 case 2: 3107 shift = 14; 3108 break; 3109 case 3: 3110 default: /* IMPDEF: handle tg==0 as 64k */ 3111 shift = 16; 3112 break; 3113 } 3114 3115 base <<= shift; 3116 range = __TLBI_RANGE_PAGES(num, scale) << shift; 3117 3118 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 3119 &(union tlbi_info) { 3120 .range = { 3121 .start = base, 3122 .size = range, 3123 }, 3124 }, 3125 s2_mmu_unmap_range); 3126 3127 return true; 3128 } 3129 3130 static void s2_mmu_unmap_ipa(struct kvm_s2_mmu *mmu, 3131 const union tlbi_info *info) 3132 { 3133 unsigned long max_size; 3134 u64 base_addr; 3135 3136 /* 3137 * We drop a number of things from the supplied value: 3138 * 3139 * - NS bit: we're non-secure only. 3140 * 3141 * - IPA[51:48]: We don't support 52bit IPA just yet... 3142 * 3143 * And of course, adjust the IPA to be on an actual address. 3144 */ 3145 base_addr = (info->ipa.addr & GENMASK_ULL(35, 0)) << 12; 3146 max_size = compute_tlb_inval_range(mmu, info->ipa.addr); 3147 base_addr &= ~(max_size - 1); 3148 3149 /* 3150 * See comment in s2_mmu_unmap_range() for why this is allowed to 3151 * reschedule. 3152 */ 3153 kvm_stage2_unmap_range(mmu, base_addr, max_size, true); 3154 } 3155 3156 static bool handle_ipas2e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3157 const struct sys_reg_desc *r) 3158 { 3159 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3160 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 3161 3162 if (!kvm_supported_tlbi_ipas2_op(vcpu, sys_encoding)) 3163 return undef_access(vcpu, p, r); 3164 3165 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 3166 &(union tlbi_info) { 3167 .ipa = { 3168 .addr = p->regval, 3169 }, 3170 }, 3171 s2_mmu_unmap_ipa); 3172 3173 return true; 3174 } 3175 3176 static void s2_mmu_tlbi_s1e1(struct kvm_s2_mmu *mmu, 3177 const union tlbi_info *info) 3178 { 3179 WARN_ON(__kvm_tlbi_s1e2(mmu, info->va.addr, info->va.encoding)); 3180 } 3181 3182 static bool handle_tlbi_el1(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3183 const struct sys_reg_desc *r) 3184 { 3185 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3186 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 3187 3188 /* 3189 * If we're here, this is because we've trapped on a EL1 TLBI 3190 * instruction that affects the EL1 translation regime while 3191 * we're running in a context that doesn't allow us to let the 3192 * HW do its thing (aka vEL2): 3193 * 3194 * - HCR_EL2.E2H == 0 : a non-VHE guest 3195 * - HCR_EL2.{E2H,TGE} == { 1, 0 } : a VHE guest in guest mode 3196 * 3197 * We don't expect these helpers to ever be called when running 3198 * in a vEL1 context. 3199 */ 3200 3201 WARN_ON(!vcpu_is_el2(vcpu)); 3202 3203 if (!kvm_supported_tlbi_s1e1_op(vcpu, sys_encoding)) 3204 return undef_access(vcpu, p, r); 3205 3206 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 3207 &(union tlbi_info) { 3208 .va = { 3209 .addr = p->regval, 3210 .encoding = sys_encoding, 3211 }, 3212 }, 3213 s2_mmu_tlbi_s1e1); 3214 3215 return true; 3216 } 3217 3218 #define SYS_INSN(insn, access_fn) \ 3219 { \ 3220 SYS_DESC(OP_##insn), \ 3221 .access = (access_fn), \ 3222 } 3223 3224 static struct sys_reg_desc sys_insn_descs[] = { 3225 { SYS_DESC(SYS_DC_ISW), access_dcsw }, 3226 { SYS_DESC(SYS_DC_IGSW), access_dcgsw }, 3227 { SYS_DESC(SYS_DC_IGDSW), access_dcgsw }, 3228 3229 SYS_INSN(AT_S1E1R, handle_at_s1e01), 3230 SYS_INSN(AT_S1E1W, handle_at_s1e01), 3231 SYS_INSN(AT_S1E0R, handle_at_s1e01), 3232 SYS_INSN(AT_S1E0W, handle_at_s1e01), 3233 SYS_INSN(AT_S1E1RP, handle_at_s1e01), 3234 SYS_INSN(AT_S1E1WP, handle_at_s1e01), 3235 3236 { SYS_DESC(SYS_DC_CSW), access_dcsw }, 3237 { SYS_DESC(SYS_DC_CGSW), access_dcgsw }, 3238 { SYS_DESC(SYS_DC_CGDSW), access_dcgsw }, 3239 { SYS_DESC(SYS_DC_CISW), access_dcsw }, 3240 { SYS_DESC(SYS_DC_CIGSW), access_dcgsw }, 3241 { SYS_DESC(SYS_DC_CIGDSW), access_dcgsw }, 3242 3243 SYS_INSN(TLBI_VMALLE1OS, handle_tlbi_el1), 3244 SYS_INSN(TLBI_VAE1OS, handle_tlbi_el1), 3245 SYS_INSN(TLBI_ASIDE1OS, handle_tlbi_el1), 3246 SYS_INSN(TLBI_VAAE1OS, handle_tlbi_el1), 3247 SYS_INSN(TLBI_VALE1OS, handle_tlbi_el1), 3248 SYS_INSN(TLBI_VAALE1OS, handle_tlbi_el1), 3249 3250 SYS_INSN(TLBI_RVAE1IS, handle_tlbi_el1), 3251 SYS_INSN(TLBI_RVAAE1IS, handle_tlbi_el1), 3252 SYS_INSN(TLBI_RVALE1IS, handle_tlbi_el1), 3253 SYS_INSN(TLBI_RVAALE1IS, handle_tlbi_el1), 3254 3255 SYS_INSN(TLBI_VMALLE1IS, handle_tlbi_el1), 3256 SYS_INSN(TLBI_VAE1IS, handle_tlbi_el1), 3257 SYS_INSN(TLBI_ASIDE1IS, handle_tlbi_el1), 3258 SYS_INSN(TLBI_VAAE1IS, handle_tlbi_el1), 3259 SYS_INSN(TLBI_VALE1IS, handle_tlbi_el1), 3260 SYS_INSN(TLBI_VAALE1IS, handle_tlbi_el1), 3261 3262 SYS_INSN(TLBI_RVAE1OS, handle_tlbi_el1), 3263 SYS_INSN(TLBI_RVAAE1OS, handle_tlbi_el1), 3264 SYS_INSN(TLBI_RVALE1OS, handle_tlbi_el1), 3265 SYS_INSN(TLBI_RVAALE1OS, handle_tlbi_el1), 3266 3267 SYS_INSN(TLBI_RVAE1, handle_tlbi_el1), 3268 SYS_INSN(TLBI_RVAAE1, handle_tlbi_el1), 3269 SYS_INSN(TLBI_RVALE1, handle_tlbi_el1), 3270 SYS_INSN(TLBI_RVAALE1, handle_tlbi_el1), 3271 3272 SYS_INSN(TLBI_VMALLE1, handle_tlbi_el1), 3273 SYS_INSN(TLBI_VAE1, handle_tlbi_el1), 3274 SYS_INSN(TLBI_ASIDE1, handle_tlbi_el1), 3275 SYS_INSN(TLBI_VAAE1, handle_tlbi_el1), 3276 SYS_INSN(TLBI_VALE1, handle_tlbi_el1), 3277 SYS_INSN(TLBI_VAALE1, handle_tlbi_el1), 3278 3279 SYS_INSN(TLBI_VMALLE1OSNXS, handle_tlbi_el1), 3280 SYS_INSN(TLBI_VAE1OSNXS, handle_tlbi_el1), 3281 SYS_INSN(TLBI_ASIDE1OSNXS, handle_tlbi_el1), 3282 SYS_INSN(TLBI_VAAE1OSNXS, handle_tlbi_el1), 3283 SYS_INSN(TLBI_VALE1OSNXS, handle_tlbi_el1), 3284 SYS_INSN(TLBI_VAALE1OSNXS, handle_tlbi_el1), 3285 3286 SYS_INSN(TLBI_RVAE1ISNXS, handle_tlbi_el1), 3287 SYS_INSN(TLBI_RVAAE1ISNXS, handle_tlbi_el1), 3288 SYS_INSN(TLBI_RVALE1ISNXS, handle_tlbi_el1), 3289 SYS_INSN(TLBI_RVAALE1ISNXS, handle_tlbi_el1), 3290 3291 SYS_INSN(TLBI_VMALLE1ISNXS, handle_tlbi_el1), 3292 SYS_INSN(TLBI_VAE1ISNXS, handle_tlbi_el1), 3293 SYS_INSN(TLBI_ASIDE1ISNXS, handle_tlbi_el1), 3294 SYS_INSN(TLBI_VAAE1ISNXS, handle_tlbi_el1), 3295 SYS_INSN(TLBI_VALE1ISNXS, handle_tlbi_el1), 3296 SYS_INSN(TLBI_VAALE1ISNXS, handle_tlbi_el1), 3297 3298 SYS_INSN(TLBI_RVAE1OSNXS, handle_tlbi_el1), 3299 SYS_INSN(TLBI_RVAAE1OSNXS, handle_tlbi_el1), 3300 SYS_INSN(TLBI_RVALE1OSNXS, handle_tlbi_el1), 3301 SYS_INSN(TLBI_RVAALE1OSNXS, handle_tlbi_el1), 3302 3303 SYS_INSN(TLBI_RVAE1NXS, handle_tlbi_el1), 3304 SYS_INSN(TLBI_RVAAE1NXS, handle_tlbi_el1), 3305 SYS_INSN(TLBI_RVALE1NXS, handle_tlbi_el1), 3306 SYS_INSN(TLBI_RVAALE1NXS, handle_tlbi_el1), 3307 3308 SYS_INSN(TLBI_VMALLE1NXS, handle_tlbi_el1), 3309 SYS_INSN(TLBI_VAE1NXS, handle_tlbi_el1), 3310 SYS_INSN(TLBI_ASIDE1NXS, handle_tlbi_el1), 3311 SYS_INSN(TLBI_VAAE1NXS, handle_tlbi_el1), 3312 SYS_INSN(TLBI_VALE1NXS, handle_tlbi_el1), 3313 SYS_INSN(TLBI_VAALE1NXS, handle_tlbi_el1), 3314 3315 SYS_INSN(AT_S1E2R, handle_at_s1e2), 3316 SYS_INSN(AT_S1E2W, handle_at_s1e2), 3317 SYS_INSN(AT_S12E1R, handle_at_s12), 3318 SYS_INSN(AT_S12E1W, handle_at_s12), 3319 SYS_INSN(AT_S12E0R, handle_at_s12), 3320 SYS_INSN(AT_S12E0W, handle_at_s12), 3321 SYS_INSN(AT_S1E2A, handle_at_s1e2), 3322 3323 SYS_INSN(TLBI_IPAS2E1IS, handle_ipas2e1is), 3324 SYS_INSN(TLBI_RIPAS2E1IS, handle_ripas2e1is), 3325 SYS_INSN(TLBI_IPAS2LE1IS, handle_ipas2e1is), 3326 SYS_INSN(TLBI_RIPAS2LE1IS, handle_ripas2e1is), 3327 3328 SYS_INSN(TLBI_ALLE2OS, undef_access), 3329 SYS_INSN(TLBI_VAE2OS, undef_access), 3330 SYS_INSN(TLBI_ALLE1OS, handle_alle1is), 3331 SYS_INSN(TLBI_VALE2OS, undef_access), 3332 SYS_INSN(TLBI_VMALLS12E1OS, handle_vmalls12e1is), 3333 3334 SYS_INSN(TLBI_RVAE2IS, undef_access), 3335 SYS_INSN(TLBI_RVALE2IS, undef_access), 3336 3337 SYS_INSN(TLBI_ALLE1IS, handle_alle1is), 3338 SYS_INSN(TLBI_VMALLS12E1IS, handle_vmalls12e1is), 3339 SYS_INSN(TLBI_IPAS2E1OS, handle_ipas2e1is), 3340 SYS_INSN(TLBI_IPAS2E1, handle_ipas2e1is), 3341 SYS_INSN(TLBI_RIPAS2E1, handle_ripas2e1is), 3342 SYS_INSN(TLBI_RIPAS2E1OS, handle_ripas2e1is), 3343 SYS_INSN(TLBI_IPAS2LE1OS, handle_ipas2e1is), 3344 SYS_INSN(TLBI_IPAS2LE1, handle_ipas2e1is), 3345 SYS_INSN(TLBI_RIPAS2LE1, handle_ripas2e1is), 3346 SYS_INSN(TLBI_RIPAS2LE1OS, handle_ripas2e1is), 3347 SYS_INSN(TLBI_RVAE2OS, undef_access), 3348 SYS_INSN(TLBI_RVALE2OS, undef_access), 3349 SYS_INSN(TLBI_RVAE2, undef_access), 3350 SYS_INSN(TLBI_RVALE2, undef_access), 3351 SYS_INSN(TLBI_ALLE1, handle_alle1is), 3352 SYS_INSN(TLBI_VMALLS12E1, handle_vmalls12e1is), 3353 3354 SYS_INSN(TLBI_IPAS2E1ISNXS, handle_ipas2e1is), 3355 SYS_INSN(TLBI_RIPAS2E1ISNXS, handle_ripas2e1is), 3356 SYS_INSN(TLBI_IPAS2LE1ISNXS, handle_ipas2e1is), 3357 SYS_INSN(TLBI_RIPAS2LE1ISNXS, handle_ripas2e1is), 3358 3359 SYS_INSN(TLBI_ALLE2OSNXS, undef_access), 3360 SYS_INSN(TLBI_VAE2OSNXS, undef_access), 3361 SYS_INSN(TLBI_ALLE1OSNXS, handle_alle1is), 3362 SYS_INSN(TLBI_VALE2OSNXS, undef_access), 3363 SYS_INSN(TLBI_VMALLS12E1OSNXS, handle_vmalls12e1is), 3364 3365 SYS_INSN(TLBI_RVAE2ISNXS, undef_access), 3366 SYS_INSN(TLBI_RVALE2ISNXS, undef_access), 3367 SYS_INSN(TLBI_ALLE2ISNXS, undef_access), 3368 SYS_INSN(TLBI_VAE2ISNXS, undef_access), 3369 3370 SYS_INSN(TLBI_ALLE1ISNXS, handle_alle1is), 3371 SYS_INSN(TLBI_VALE2ISNXS, undef_access), 3372 SYS_INSN(TLBI_VMALLS12E1ISNXS, handle_vmalls12e1is), 3373 SYS_INSN(TLBI_IPAS2E1OSNXS, handle_ipas2e1is), 3374 SYS_INSN(TLBI_IPAS2E1NXS, handle_ipas2e1is), 3375 SYS_INSN(TLBI_RIPAS2E1NXS, handle_ripas2e1is), 3376 SYS_INSN(TLBI_RIPAS2E1OSNXS, handle_ripas2e1is), 3377 SYS_INSN(TLBI_IPAS2LE1OSNXS, handle_ipas2e1is), 3378 SYS_INSN(TLBI_IPAS2LE1NXS, handle_ipas2e1is), 3379 SYS_INSN(TLBI_RIPAS2LE1NXS, handle_ripas2e1is), 3380 SYS_INSN(TLBI_RIPAS2LE1OSNXS, handle_ripas2e1is), 3381 SYS_INSN(TLBI_RVAE2OSNXS, undef_access), 3382 SYS_INSN(TLBI_RVALE2OSNXS, undef_access), 3383 SYS_INSN(TLBI_RVAE2NXS, undef_access), 3384 SYS_INSN(TLBI_RVALE2NXS, undef_access), 3385 SYS_INSN(TLBI_ALLE2NXS, undef_access), 3386 SYS_INSN(TLBI_VAE2NXS, undef_access), 3387 SYS_INSN(TLBI_ALLE1NXS, handle_alle1is), 3388 SYS_INSN(TLBI_VALE2NXS, undef_access), 3389 SYS_INSN(TLBI_VMALLS12E1NXS, handle_vmalls12e1is), 3390 }; 3391 3392 static bool trap_dbgdidr(struct kvm_vcpu *vcpu, 3393 struct sys_reg_params *p, 3394 const struct sys_reg_desc *r) 3395 { 3396 if (p->is_write) { 3397 return ignore_write(vcpu, p); 3398 } else { 3399 u64 dfr = kvm_read_vm_id_reg(vcpu->kvm, SYS_ID_AA64DFR0_EL1); 3400 u32 el3 = kvm_has_feat(vcpu->kvm, ID_AA64PFR0_EL1, EL3, IMP); 3401 3402 p->regval = ((SYS_FIELD_GET(ID_AA64DFR0_EL1, WRPs, dfr) << 28) | 3403 (SYS_FIELD_GET(ID_AA64DFR0_EL1, BRPs, dfr) << 24) | 3404 (SYS_FIELD_GET(ID_AA64DFR0_EL1, CTX_CMPs, dfr) << 20) | 3405 (SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, dfr) << 16) | 3406 (1 << 15) | (el3 << 14) | (el3 << 12)); 3407 return true; 3408 } 3409 } 3410 3411 /* 3412 * AArch32 debug register mappings 3413 * 3414 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0] 3415 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32] 3416 * 3417 * None of the other registers share their location, so treat them as 3418 * if they were 64bit. 3419 */ 3420 #define DBG_BCR_BVR_WCR_WVR(n) \ 3421 /* DBGBVRn */ \ 3422 { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \ 3423 /* DBGBCRn */ \ 3424 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \ 3425 /* DBGWVRn */ \ 3426 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \ 3427 /* DBGWCRn */ \ 3428 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n } 3429 3430 #define DBGBXVR(n) \ 3431 { AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_bvr, NULL, n } 3432 3433 /* 3434 * Trapped cp14 registers. We generally ignore most of the external 3435 * debug, on the principle that they don't really make sense to a 3436 * guest. Revisit this one day, would this principle change. 3437 */ 3438 static const struct sys_reg_desc cp14_regs[] = { 3439 /* DBGDIDR */ 3440 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgdidr }, 3441 /* DBGDTRRXext */ 3442 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi }, 3443 3444 DBG_BCR_BVR_WCR_WVR(0), 3445 /* DBGDSCRint */ 3446 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi }, 3447 DBG_BCR_BVR_WCR_WVR(1), 3448 /* DBGDCCINT */ 3449 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug_regs, NULL, MDCCINT_EL1 }, 3450 /* DBGDSCRext */ 3451 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug_regs, NULL, MDSCR_EL1 }, 3452 DBG_BCR_BVR_WCR_WVR(2), 3453 /* DBGDTR[RT]Xint */ 3454 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi }, 3455 /* DBGDTR[RT]Xext */ 3456 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi }, 3457 DBG_BCR_BVR_WCR_WVR(3), 3458 DBG_BCR_BVR_WCR_WVR(4), 3459 DBG_BCR_BVR_WCR_WVR(5), 3460 /* DBGWFAR */ 3461 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi }, 3462 /* DBGOSECCR */ 3463 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi }, 3464 DBG_BCR_BVR_WCR_WVR(6), 3465 /* DBGVCR */ 3466 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug_regs, NULL, DBGVCR32_EL2 }, 3467 DBG_BCR_BVR_WCR_WVR(7), 3468 DBG_BCR_BVR_WCR_WVR(8), 3469 DBG_BCR_BVR_WCR_WVR(9), 3470 DBG_BCR_BVR_WCR_WVR(10), 3471 DBG_BCR_BVR_WCR_WVR(11), 3472 DBG_BCR_BVR_WCR_WVR(12), 3473 DBG_BCR_BVR_WCR_WVR(13), 3474 DBG_BCR_BVR_WCR_WVR(14), 3475 DBG_BCR_BVR_WCR_WVR(15), 3476 3477 /* DBGDRAR (32bit) */ 3478 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi }, 3479 3480 DBGBXVR(0), 3481 /* DBGOSLAR */ 3482 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_oslar_el1 }, 3483 DBGBXVR(1), 3484 /* DBGOSLSR */ 3485 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1, NULL, OSLSR_EL1 }, 3486 DBGBXVR(2), 3487 DBGBXVR(3), 3488 /* DBGOSDLR */ 3489 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi }, 3490 DBGBXVR(4), 3491 /* DBGPRCR */ 3492 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi }, 3493 DBGBXVR(5), 3494 DBGBXVR(6), 3495 DBGBXVR(7), 3496 DBGBXVR(8), 3497 DBGBXVR(9), 3498 DBGBXVR(10), 3499 DBGBXVR(11), 3500 DBGBXVR(12), 3501 DBGBXVR(13), 3502 DBGBXVR(14), 3503 DBGBXVR(15), 3504 3505 /* DBGDSAR (32bit) */ 3506 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi }, 3507 3508 /* DBGDEVID2 */ 3509 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi }, 3510 /* DBGDEVID1 */ 3511 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi }, 3512 /* DBGDEVID */ 3513 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi }, 3514 /* DBGCLAIMSET */ 3515 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi }, 3516 /* DBGCLAIMCLR */ 3517 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi }, 3518 /* DBGAUTHSTATUS */ 3519 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 }, 3520 }; 3521 3522 /* Trapped cp14 64bit registers */ 3523 static const struct sys_reg_desc cp14_64_regs[] = { 3524 /* DBGDRAR (64bit) */ 3525 { Op1( 0), CRm( 1), .access = trap_raz_wi }, 3526 3527 /* DBGDSAR (64bit) */ 3528 { Op1( 0), CRm( 2), .access = trap_raz_wi }, 3529 }; 3530 3531 #define CP15_PMU_SYS_REG(_map, _Op1, _CRn, _CRm, _Op2) \ 3532 AA32(_map), \ 3533 Op1(_Op1), CRn(_CRn), CRm(_CRm), Op2(_Op2), \ 3534 .visibility = pmu_visibility 3535 3536 /* Macro to expand the PMEVCNTRn register */ 3537 #define PMU_PMEVCNTR(n) \ 3538 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \ 3539 (0b1000 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \ 3540 .access = access_pmu_evcntr } 3541 3542 /* Macro to expand the PMEVTYPERn register */ 3543 #define PMU_PMEVTYPER(n) \ 3544 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \ 3545 (0b1100 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \ 3546 .access = access_pmu_evtyper } 3547 /* 3548 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding, 3549 * depending on the way they are accessed (as a 32bit or a 64bit 3550 * register). 3551 */ 3552 static const struct sys_reg_desc cp15_regs[] = { 3553 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr }, 3554 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, SCTLR_EL1 }, 3555 /* ACTLR */ 3556 { AA32(LO), Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr, NULL, ACTLR_EL1 }, 3557 /* ACTLR2 */ 3558 { AA32(HI), Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr, NULL, ACTLR_EL1 }, 3559 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, 3560 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, TTBR1_EL1 }, 3561 /* TTBCR */ 3562 { AA32(LO), Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 }, 3563 /* TTBCR2 */ 3564 { AA32(HI), Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, TCR_EL1 }, 3565 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, DACR32_EL2 }, 3566 { CP15_SYS_DESC(SYS_ICC_PMR_EL1), undef_access }, 3567 /* DFSR */ 3568 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, ESR_EL1 }, 3569 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, IFSR32_EL2 }, 3570 /* ADFSR */ 3571 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, AFSR0_EL1 }, 3572 /* AIFSR */ 3573 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, AFSR1_EL1 }, 3574 /* DFAR */ 3575 { AA32(LO), Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, FAR_EL1 }, 3576 /* IFAR */ 3577 { AA32(HI), Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, FAR_EL1 }, 3578 3579 /* 3580 * DC{C,I,CI}SW operations: 3581 */ 3582 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw }, 3583 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw }, 3584 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw }, 3585 3586 /* PMU */ 3587 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 0), .access = access_pmcr }, 3588 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 1), .access = access_pmcnten }, 3589 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 2), .access = access_pmcnten }, 3590 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 3), .access = access_pmovs }, 3591 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 4), .access = access_pmswinc }, 3592 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 5), .access = access_pmselr }, 3593 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 6), .access = access_pmceid }, 3594 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 7), .access = access_pmceid }, 3595 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 0), .access = access_pmu_evcntr }, 3596 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 1), .access = access_pmu_evtyper }, 3597 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 2), .access = access_pmu_evcntr }, 3598 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 0), .access = access_pmuserenr }, 3599 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 1), .access = access_pminten }, 3600 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 2), .access = access_pminten }, 3601 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 3), .access = access_pmovs }, 3602 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 4), .access = access_pmceid }, 3603 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 5), .access = access_pmceid }, 3604 /* PMMIR */ 3605 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 6), .access = trap_raz_wi }, 3606 3607 /* PRRR/MAIR0 */ 3608 { AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 }, 3609 /* NMRR/MAIR1 */ 3610 { AA32(HI), Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, MAIR_EL1 }, 3611 /* AMAIR0 */ 3612 { AA32(LO), Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, AMAIR_EL1 }, 3613 /* AMAIR1 */ 3614 { AA32(HI), Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, AMAIR_EL1 }, 3615 3616 { CP15_SYS_DESC(SYS_ICC_IAR0_EL1), undef_access }, 3617 { CP15_SYS_DESC(SYS_ICC_EOIR0_EL1), undef_access }, 3618 { CP15_SYS_DESC(SYS_ICC_HPPIR0_EL1), undef_access }, 3619 { CP15_SYS_DESC(SYS_ICC_BPR0_EL1), undef_access }, 3620 { CP15_SYS_DESC(SYS_ICC_AP0R0_EL1), undef_access }, 3621 { CP15_SYS_DESC(SYS_ICC_AP0R1_EL1), undef_access }, 3622 { CP15_SYS_DESC(SYS_ICC_AP0R2_EL1), undef_access }, 3623 { CP15_SYS_DESC(SYS_ICC_AP0R3_EL1), undef_access }, 3624 { CP15_SYS_DESC(SYS_ICC_AP1R0_EL1), undef_access }, 3625 { CP15_SYS_DESC(SYS_ICC_AP1R1_EL1), undef_access }, 3626 { CP15_SYS_DESC(SYS_ICC_AP1R2_EL1), undef_access }, 3627 { CP15_SYS_DESC(SYS_ICC_AP1R3_EL1), undef_access }, 3628 { CP15_SYS_DESC(SYS_ICC_DIR_EL1), undef_access }, 3629 { CP15_SYS_DESC(SYS_ICC_RPR_EL1), undef_access }, 3630 { CP15_SYS_DESC(SYS_ICC_IAR1_EL1), undef_access }, 3631 { CP15_SYS_DESC(SYS_ICC_EOIR1_EL1), undef_access }, 3632 { CP15_SYS_DESC(SYS_ICC_HPPIR1_EL1), undef_access }, 3633 { CP15_SYS_DESC(SYS_ICC_BPR1_EL1), undef_access }, 3634 { CP15_SYS_DESC(SYS_ICC_CTLR_EL1), undef_access }, 3635 { CP15_SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre }, 3636 { CP15_SYS_DESC(SYS_ICC_IGRPEN0_EL1), undef_access }, 3637 { CP15_SYS_DESC(SYS_ICC_IGRPEN1_EL1), undef_access }, 3638 3639 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, CONTEXTIDR_EL1 }, 3640 3641 /* Arch Tmers */ 3642 { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer }, 3643 { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer }, 3644 3645 /* PMEVCNTRn */ 3646 PMU_PMEVCNTR(0), 3647 PMU_PMEVCNTR(1), 3648 PMU_PMEVCNTR(2), 3649 PMU_PMEVCNTR(3), 3650 PMU_PMEVCNTR(4), 3651 PMU_PMEVCNTR(5), 3652 PMU_PMEVCNTR(6), 3653 PMU_PMEVCNTR(7), 3654 PMU_PMEVCNTR(8), 3655 PMU_PMEVCNTR(9), 3656 PMU_PMEVCNTR(10), 3657 PMU_PMEVCNTR(11), 3658 PMU_PMEVCNTR(12), 3659 PMU_PMEVCNTR(13), 3660 PMU_PMEVCNTR(14), 3661 PMU_PMEVCNTR(15), 3662 PMU_PMEVCNTR(16), 3663 PMU_PMEVCNTR(17), 3664 PMU_PMEVCNTR(18), 3665 PMU_PMEVCNTR(19), 3666 PMU_PMEVCNTR(20), 3667 PMU_PMEVCNTR(21), 3668 PMU_PMEVCNTR(22), 3669 PMU_PMEVCNTR(23), 3670 PMU_PMEVCNTR(24), 3671 PMU_PMEVCNTR(25), 3672 PMU_PMEVCNTR(26), 3673 PMU_PMEVCNTR(27), 3674 PMU_PMEVCNTR(28), 3675 PMU_PMEVCNTR(29), 3676 PMU_PMEVCNTR(30), 3677 /* PMEVTYPERn */ 3678 PMU_PMEVTYPER(0), 3679 PMU_PMEVTYPER(1), 3680 PMU_PMEVTYPER(2), 3681 PMU_PMEVTYPER(3), 3682 PMU_PMEVTYPER(4), 3683 PMU_PMEVTYPER(5), 3684 PMU_PMEVTYPER(6), 3685 PMU_PMEVTYPER(7), 3686 PMU_PMEVTYPER(8), 3687 PMU_PMEVTYPER(9), 3688 PMU_PMEVTYPER(10), 3689 PMU_PMEVTYPER(11), 3690 PMU_PMEVTYPER(12), 3691 PMU_PMEVTYPER(13), 3692 PMU_PMEVTYPER(14), 3693 PMU_PMEVTYPER(15), 3694 PMU_PMEVTYPER(16), 3695 PMU_PMEVTYPER(17), 3696 PMU_PMEVTYPER(18), 3697 PMU_PMEVTYPER(19), 3698 PMU_PMEVTYPER(20), 3699 PMU_PMEVTYPER(21), 3700 PMU_PMEVTYPER(22), 3701 PMU_PMEVTYPER(23), 3702 PMU_PMEVTYPER(24), 3703 PMU_PMEVTYPER(25), 3704 PMU_PMEVTYPER(26), 3705 PMU_PMEVTYPER(27), 3706 PMU_PMEVTYPER(28), 3707 PMU_PMEVTYPER(29), 3708 PMU_PMEVTYPER(30), 3709 /* PMCCFILTR */ 3710 { CP15_PMU_SYS_REG(DIRECT, 0, 14, 15, 7), .access = access_pmu_evtyper }, 3711 3712 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr }, 3713 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr }, 3714 3715 /* CCSIDR2 */ 3716 { Op1(1), CRn( 0), CRm( 0), Op2(2), undef_access }, 3717 3718 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 }, 3719 }; 3720 3721 static const struct sys_reg_desc cp15_64_regs[] = { 3722 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, 3723 { CP15_PMU_SYS_REG(DIRECT, 0, 0, 9, 0), .access = access_pmu_evcntr }, 3724 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */ 3725 { SYS_DESC(SYS_AARCH32_CNTPCT), access_arch_timer }, 3726 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 }, 3727 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */ 3728 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */ 3729 { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer }, 3730 { SYS_DESC(SYS_AARCH32_CNTPCTSS), access_arch_timer }, 3731 }; 3732 3733 static bool check_sysreg_table(const struct sys_reg_desc *table, unsigned int n, 3734 bool is_32) 3735 { 3736 unsigned int i; 3737 3738 for (i = 0; i < n; i++) { 3739 if (!is_32 && table[i].reg && !table[i].reset) { 3740 kvm_err("sys_reg table %pS entry %d (%s) lacks reset\n", 3741 &table[i], i, table[i].name); 3742 return false; 3743 } 3744 3745 if (i && cmp_sys_reg(&table[i-1], &table[i]) >= 0) { 3746 kvm_err("sys_reg table %pS entry %d (%s -> %s) out of order\n", 3747 &table[i], i, table[i - 1].name, table[i].name); 3748 return false; 3749 } 3750 } 3751 3752 return true; 3753 } 3754 3755 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu) 3756 { 3757 kvm_inject_undefined(vcpu); 3758 return 1; 3759 } 3760 3761 static void perform_access(struct kvm_vcpu *vcpu, 3762 struct sys_reg_params *params, 3763 const struct sys_reg_desc *r) 3764 { 3765 trace_kvm_sys_access(*vcpu_pc(vcpu), params, r); 3766 3767 /* Check for regs disabled by runtime config */ 3768 if (sysreg_hidden(vcpu, r)) { 3769 kvm_inject_undefined(vcpu); 3770 return; 3771 } 3772 3773 /* 3774 * Not having an accessor means that we have configured a trap 3775 * that we don't know how to handle. This certainly qualifies 3776 * as a gross bug that should be fixed right away. 3777 */ 3778 BUG_ON(!r->access); 3779 3780 /* Skip instruction if instructed so */ 3781 if (likely(r->access(vcpu, params, r))) 3782 kvm_incr_pc(vcpu); 3783 } 3784 3785 /* 3786 * emulate_cp -- tries to match a sys_reg access in a handling table, and 3787 * call the corresponding trap handler. 3788 * 3789 * @params: pointer to the descriptor of the access 3790 * @table: array of trap descriptors 3791 * @num: size of the trap descriptor array 3792 * 3793 * Return true if the access has been handled, false if not. 3794 */ 3795 static bool emulate_cp(struct kvm_vcpu *vcpu, 3796 struct sys_reg_params *params, 3797 const struct sys_reg_desc *table, 3798 size_t num) 3799 { 3800 const struct sys_reg_desc *r; 3801 3802 if (!table) 3803 return false; /* Not handled */ 3804 3805 r = find_reg(params, table, num); 3806 3807 if (r) { 3808 perform_access(vcpu, params, r); 3809 return true; 3810 } 3811 3812 /* Not handled */ 3813 return false; 3814 } 3815 3816 static void unhandled_cp_access(struct kvm_vcpu *vcpu, 3817 struct sys_reg_params *params) 3818 { 3819 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu); 3820 int cp = -1; 3821 3822 switch (esr_ec) { 3823 case ESR_ELx_EC_CP15_32: 3824 case ESR_ELx_EC_CP15_64: 3825 cp = 15; 3826 break; 3827 case ESR_ELx_EC_CP14_MR: 3828 case ESR_ELx_EC_CP14_64: 3829 cp = 14; 3830 break; 3831 default: 3832 WARN_ON(1); 3833 } 3834 3835 print_sys_reg_msg(params, 3836 "Unsupported guest CP%d access at: %08lx [%08lx]\n", 3837 cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 3838 kvm_inject_undefined(vcpu); 3839 } 3840 3841 /** 3842 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access 3843 * @vcpu: The VCPU pointer 3844 * @global: &struct sys_reg_desc 3845 * @nr_global: size of the @global array 3846 */ 3847 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu, 3848 const struct sys_reg_desc *global, 3849 size_t nr_global) 3850 { 3851 struct sys_reg_params params; 3852 u64 esr = kvm_vcpu_get_esr(vcpu); 3853 int Rt = kvm_vcpu_sys_get_rt(vcpu); 3854 int Rt2 = (esr >> 10) & 0x1f; 3855 3856 params.CRm = (esr >> 1) & 0xf; 3857 params.is_write = ((esr & 1) == 0); 3858 3859 params.Op0 = 0; 3860 params.Op1 = (esr >> 16) & 0xf; 3861 params.Op2 = 0; 3862 params.CRn = 0; 3863 3864 /* 3865 * Make a 64-bit value out of Rt and Rt2. As we use the same trap 3866 * backends between AArch32 and AArch64, we get away with it. 3867 */ 3868 if (params.is_write) { 3869 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff; 3870 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32; 3871 } 3872 3873 /* 3874 * If the table contains a handler, handle the 3875 * potential register operation in the case of a read and return 3876 * with success. 3877 */ 3878 if (emulate_cp(vcpu, ¶ms, global, nr_global)) { 3879 /* Split up the value between registers for the read side */ 3880 if (!params.is_write) { 3881 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval)); 3882 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval)); 3883 } 3884 3885 return 1; 3886 } 3887 3888 unhandled_cp_access(vcpu, ¶ms); 3889 return 1; 3890 } 3891 3892 static bool emulate_sys_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *params); 3893 3894 /* 3895 * The CP10 ID registers are architecturally mapped to AArch64 feature 3896 * registers. Abuse that fact so we can rely on the AArch64 handler for accesses 3897 * from AArch32. 3898 */ 3899 static bool kvm_esr_cp10_id_to_sys64(u64 esr, struct sys_reg_params *params) 3900 { 3901 u8 reg_id = (esr >> 10) & 0xf; 3902 bool valid; 3903 3904 params->is_write = ((esr & 1) == 0); 3905 params->Op0 = 3; 3906 params->Op1 = 0; 3907 params->CRn = 0; 3908 params->CRm = 3; 3909 3910 /* CP10 ID registers are read-only */ 3911 valid = !params->is_write; 3912 3913 switch (reg_id) { 3914 /* MVFR0 */ 3915 case 0b0111: 3916 params->Op2 = 0; 3917 break; 3918 /* MVFR1 */ 3919 case 0b0110: 3920 params->Op2 = 1; 3921 break; 3922 /* MVFR2 */ 3923 case 0b0101: 3924 params->Op2 = 2; 3925 break; 3926 default: 3927 valid = false; 3928 } 3929 3930 if (valid) 3931 return true; 3932 3933 kvm_pr_unimpl("Unhandled cp10 register %s: %u\n", 3934 params->is_write ? "write" : "read", reg_id); 3935 return false; 3936 } 3937 3938 /** 3939 * kvm_handle_cp10_id() - Handles a VMRS trap on guest access to a 'Media and 3940 * VFP Register' from AArch32. 3941 * @vcpu: The vCPU pointer 3942 * 3943 * MVFR{0-2} are architecturally mapped to the AArch64 MVFR{0-2}_EL1 registers. 3944 * Work out the correct AArch64 system register encoding and reroute to the 3945 * AArch64 system register emulation. 3946 */ 3947 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu) 3948 { 3949 int Rt = kvm_vcpu_sys_get_rt(vcpu); 3950 u64 esr = kvm_vcpu_get_esr(vcpu); 3951 struct sys_reg_params params; 3952 3953 /* UNDEF on any unhandled register access */ 3954 if (!kvm_esr_cp10_id_to_sys64(esr, ¶ms)) { 3955 kvm_inject_undefined(vcpu); 3956 return 1; 3957 } 3958 3959 if (emulate_sys_reg(vcpu, ¶ms)) 3960 vcpu_set_reg(vcpu, Rt, params.regval); 3961 3962 return 1; 3963 } 3964 3965 /** 3966 * kvm_emulate_cp15_id_reg() - Handles an MRC trap on a guest CP15 access where 3967 * CRn=0, which corresponds to the AArch32 feature 3968 * registers. 3969 * @vcpu: the vCPU pointer 3970 * @params: the system register access parameters. 3971 * 3972 * Our cp15 system register tables do not enumerate the AArch32 feature 3973 * registers. Conveniently, our AArch64 table does, and the AArch32 system 3974 * register encoding can be trivially remapped into the AArch64 for the feature 3975 * registers: Append op0=3, leaving op1, CRn, CRm, and op2 the same. 3976 * 3977 * According to DDI0487G.b G7.3.1, paragraph "Behavior of VMSAv8-32 32-bit 3978 * System registers with (coproc=0b1111, CRn==c0)", read accesses from this 3979 * range are either UNKNOWN or RES0. Rerouting remains architectural as we 3980 * treat undefined registers in this range as RAZ. 3981 */ 3982 static int kvm_emulate_cp15_id_reg(struct kvm_vcpu *vcpu, 3983 struct sys_reg_params *params) 3984 { 3985 int Rt = kvm_vcpu_sys_get_rt(vcpu); 3986 3987 /* Treat impossible writes to RO registers as UNDEFINED */ 3988 if (params->is_write) { 3989 unhandled_cp_access(vcpu, params); 3990 return 1; 3991 } 3992 3993 params->Op0 = 3; 3994 3995 /* 3996 * All registers where CRm > 3 are known to be UNKNOWN/RAZ from AArch32. 3997 * Avoid conflicting with future expansion of AArch64 feature registers 3998 * and simply treat them as RAZ here. 3999 */ 4000 if (params->CRm > 3) 4001 params->regval = 0; 4002 else if (!emulate_sys_reg(vcpu, params)) 4003 return 1; 4004 4005 vcpu_set_reg(vcpu, Rt, params->regval); 4006 return 1; 4007 } 4008 4009 /** 4010 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access 4011 * @vcpu: The VCPU pointer 4012 * @params: &struct sys_reg_params 4013 * @global: &struct sys_reg_desc 4014 * @nr_global: size of the @global array 4015 */ 4016 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu, 4017 struct sys_reg_params *params, 4018 const struct sys_reg_desc *global, 4019 size_t nr_global) 4020 { 4021 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4022 4023 params->regval = vcpu_get_reg(vcpu, Rt); 4024 4025 if (emulate_cp(vcpu, params, global, nr_global)) { 4026 if (!params->is_write) 4027 vcpu_set_reg(vcpu, Rt, params->regval); 4028 return 1; 4029 } 4030 4031 unhandled_cp_access(vcpu, params); 4032 return 1; 4033 } 4034 4035 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu) 4036 { 4037 return kvm_handle_cp_64(vcpu, cp15_64_regs, ARRAY_SIZE(cp15_64_regs)); 4038 } 4039 4040 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu) 4041 { 4042 struct sys_reg_params params; 4043 4044 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu)); 4045 4046 /* 4047 * Certain AArch32 ID registers are handled by rerouting to the AArch64 4048 * system register table. Registers in the ID range where CRm=0 are 4049 * excluded from this scheme as they do not trivially map into AArch64 4050 * system register encodings. 4051 */ 4052 if (params.Op1 == 0 && params.CRn == 0 && params.CRm) 4053 return kvm_emulate_cp15_id_reg(vcpu, ¶ms); 4054 4055 return kvm_handle_cp_32(vcpu, ¶ms, cp15_regs, ARRAY_SIZE(cp15_regs)); 4056 } 4057 4058 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu) 4059 { 4060 return kvm_handle_cp_64(vcpu, cp14_64_regs, ARRAY_SIZE(cp14_64_regs)); 4061 } 4062 4063 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu) 4064 { 4065 struct sys_reg_params params; 4066 4067 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu)); 4068 4069 return kvm_handle_cp_32(vcpu, ¶ms, cp14_regs, ARRAY_SIZE(cp14_regs)); 4070 } 4071 4072 /** 4073 * emulate_sys_reg - Emulate a guest access to an AArch64 system register 4074 * @vcpu: The VCPU pointer 4075 * @params: Decoded system register parameters 4076 * 4077 * Return: true if the system register access was successful, false otherwise. 4078 */ 4079 static bool emulate_sys_reg(struct kvm_vcpu *vcpu, 4080 struct sys_reg_params *params) 4081 { 4082 const struct sys_reg_desc *r; 4083 4084 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 4085 if (likely(r)) { 4086 perform_access(vcpu, params, r); 4087 return true; 4088 } 4089 4090 print_sys_reg_msg(params, 4091 "Unsupported guest sys_reg access at: %lx [%08lx]\n", 4092 *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 4093 kvm_inject_undefined(vcpu); 4094 4095 return false; 4096 } 4097 4098 static const struct sys_reg_desc *idregs_debug_find(struct kvm *kvm, u8 pos) 4099 { 4100 unsigned long i, idreg_idx = 0; 4101 4102 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { 4103 const struct sys_reg_desc *r = &sys_reg_descs[i]; 4104 4105 if (!is_vm_ftr_id_reg(reg_to_encoding(r))) 4106 continue; 4107 4108 if (idreg_idx == pos) 4109 return r; 4110 4111 idreg_idx++; 4112 } 4113 4114 return NULL; 4115 } 4116 4117 static void *idregs_debug_start(struct seq_file *s, loff_t *pos) 4118 { 4119 struct kvm *kvm = s->private; 4120 u8 *iter; 4121 4122 mutex_lock(&kvm->arch.config_lock); 4123 4124 iter = &kvm->arch.idreg_debugfs_iter; 4125 if (test_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags) && 4126 *iter == (u8)~0) { 4127 *iter = *pos; 4128 if (!idregs_debug_find(kvm, *iter)) 4129 iter = NULL; 4130 } else { 4131 iter = ERR_PTR(-EBUSY); 4132 } 4133 4134 mutex_unlock(&kvm->arch.config_lock); 4135 4136 return iter; 4137 } 4138 4139 static void *idregs_debug_next(struct seq_file *s, void *v, loff_t *pos) 4140 { 4141 struct kvm *kvm = s->private; 4142 4143 (*pos)++; 4144 4145 if (idregs_debug_find(kvm, kvm->arch.idreg_debugfs_iter + 1)) { 4146 kvm->arch.idreg_debugfs_iter++; 4147 4148 return &kvm->arch.idreg_debugfs_iter; 4149 } 4150 4151 return NULL; 4152 } 4153 4154 static void idregs_debug_stop(struct seq_file *s, void *v) 4155 { 4156 struct kvm *kvm = s->private; 4157 4158 if (IS_ERR(v)) 4159 return; 4160 4161 mutex_lock(&kvm->arch.config_lock); 4162 4163 kvm->arch.idreg_debugfs_iter = ~0; 4164 4165 mutex_unlock(&kvm->arch.config_lock); 4166 } 4167 4168 static int idregs_debug_show(struct seq_file *s, void *v) 4169 { 4170 const struct sys_reg_desc *desc; 4171 struct kvm *kvm = s->private; 4172 4173 desc = idregs_debug_find(kvm, kvm->arch.idreg_debugfs_iter); 4174 4175 if (!desc->name) 4176 return 0; 4177 4178 seq_printf(s, "%20s:\t%016llx\n", 4179 desc->name, kvm_read_vm_id_reg(kvm, reg_to_encoding(desc))); 4180 4181 return 0; 4182 } 4183 4184 static const struct seq_operations idregs_debug_sops = { 4185 .start = idregs_debug_start, 4186 .next = idregs_debug_next, 4187 .stop = idregs_debug_stop, 4188 .show = idregs_debug_show, 4189 }; 4190 4191 DEFINE_SEQ_ATTRIBUTE(idregs_debug); 4192 4193 void kvm_sys_regs_create_debugfs(struct kvm *kvm) 4194 { 4195 kvm->arch.idreg_debugfs_iter = ~0; 4196 4197 debugfs_create_file("idregs", 0444, kvm->debugfs_dentry, kvm, 4198 &idregs_debug_fops); 4199 } 4200 4201 static void reset_vm_ftr_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *reg) 4202 { 4203 u32 id = reg_to_encoding(reg); 4204 struct kvm *kvm = vcpu->kvm; 4205 4206 if (test_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags)) 4207 return; 4208 4209 kvm_set_vm_id_reg(kvm, id, reg->reset(vcpu, reg)); 4210 } 4211 4212 static void reset_vcpu_ftr_id_reg(struct kvm_vcpu *vcpu, 4213 const struct sys_reg_desc *reg) 4214 { 4215 if (kvm_vcpu_initialized(vcpu)) 4216 return; 4217 4218 reg->reset(vcpu, reg); 4219 } 4220 4221 /** 4222 * kvm_reset_sys_regs - sets system registers to reset value 4223 * @vcpu: The VCPU pointer 4224 * 4225 * This function finds the right table above and sets the registers on the 4226 * virtual CPU struct to their architecturally defined reset values. 4227 */ 4228 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu) 4229 { 4230 struct kvm *kvm = vcpu->kvm; 4231 unsigned long i; 4232 4233 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { 4234 const struct sys_reg_desc *r = &sys_reg_descs[i]; 4235 4236 if (!r->reset) 4237 continue; 4238 4239 if (is_vm_ftr_id_reg(reg_to_encoding(r))) 4240 reset_vm_ftr_id_reg(vcpu, r); 4241 else if (is_vcpu_ftr_id_reg(reg_to_encoding(r))) 4242 reset_vcpu_ftr_id_reg(vcpu, r); 4243 else 4244 r->reset(vcpu, r); 4245 } 4246 4247 set_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags); 4248 } 4249 4250 /** 4251 * kvm_handle_sys_reg -- handles a system instruction or mrs/msr instruction 4252 * trap on a guest execution 4253 * @vcpu: The VCPU pointer 4254 */ 4255 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu) 4256 { 4257 const struct sys_reg_desc *desc = NULL; 4258 struct sys_reg_params params; 4259 unsigned long esr = kvm_vcpu_get_esr(vcpu); 4260 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4261 int sr_idx; 4262 4263 trace_kvm_handle_sys_reg(esr); 4264 4265 if (triage_sysreg_trap(vcpu, &sr_idx)) 4266 return 1; 4267 4268 params = esr_sys64_to_params(esr); 4269 params.regval = vcpu_get_reg(vcpu, Rt); 4270 4271 /* System registers have Op0=={2,3}, as per DDI487 J.a C5.1.2 */ 4272 if (params.Op0 == 2 || params.Op0 == 3) 4273 desc = &sys_reg_descs[sr_idx]; 4274 else 4275 desc = &sys_insn_descs[sr_idx]; 4276 4277 perform_access(vcpu, ¶ms, desc); 4278 4279 /* Read from system register? */ 4280 if (!params.is_write && 4281 (params.Op0 == 2 || params.Op0 == 3)) 4282 vcpu_set_reg(vcpu, Rt, params.regval); 4283 4284 return 1; 4285 } 4286 4287 /****************************************************************************** 4288 * Userspace API 4289 *****************************************************************************/ 4290 4291 static bool index_to_params(u64 id, struct sys_reg_params *params) 4292 { 4293 switch (id & KVM_REG_SIZE_MASK) { 4294 case KVM_REG_SIZE_U64: 4295 /* Any unused index bits means it's not valid. */ 4296 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK 4297 | KVM_REG_ARM_COPROC_MASK 4298 | KVM_REG_ARM64_SYSREG_OP0_MASK 4299 | KVM_REG_ARM64_SYSREG_OP1_MASK 4300 | KVM_REG_ARM64_SYSREG_CRN_MASK 4301 | KVM_REG_ARM64_SYSREG_CRM_MASK 4302 | KVM_REG_ARM64_SYSREG_OP2_MASK)) 4303 return false; 4304 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK) 4305 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT); 4306 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK) 4307 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT); 4308 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK) 4309 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT); 4310 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK) 4311 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT); 4312 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK) 4313 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT); 4314 return true; 4315 default: 4316 return false; 4317 } 4318 } 4319 4320 const struct sys_reg_desc *get_reg_by_id(u64 id, 4321 const struct sys_reg_desc table[], 4322 unsigned int num) 4323 { 4324 struct sys_reg_params params; 4325 4326 if (!index_to_params(id, ¶ms)) 4327 return NULL; 4328 4329 return find_reg(¶ms, table, num); 4330 } 4331 4332 /* Decode an index value, and find the sys_reg_desc entry. */ 4333 static const struct sys_reg_desc * 4334 id_to_sys_reg_desc(struct kvm_vcpu *vcpu, u64 id, 4335 const struct sys_reg_desc table[], unsigned int num) 4336 4337 { 4338 const struct sys_reg_desc *r; 4339 4340 /* We only do sys_reg for now. */ 4341 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG) 4342 return NULL; 4343 4344 r = get_reg_by_id(id, table, num); 4345 4346 /* Not saved in the sys_reg array and not otherwise accessible? */ 4347 if (r && (!(r->reg || r->get_user) || sysreg_hidden(vcpu, r))) 4348 r = NULL; 4349 4350 return r; 4351 } 4352 4353 /* 4354 * These are the invariant sys_reg registers: we let the guest see the 4355 * host versions of these, so they're part of the guest state. 4356 * 4357 * A future CPU may provide a mechanism to present different values to 4358 * the guest, or a future kvm may trap them. 4359 */ 4360 4361 #define FUNCTION_INVARIANT(reg) \ 4362 static u64 reset_##reg(struct kvm_vcpu *v, \ 4363 const struct sys_reg_desc *r) \ 4364 { \ 4365 ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \ 4366 return ((struct sys_reg_desc *)r)->val; \ 4367 } 4368 4369 FUNCTION_INVARIANT(midr_el1) 4370 FUNCTION_INVARIANT(revidr_el1) 4371 FUNCTION_INVARIANT(aidr_el1) 4372 4373 /* ->val is filled in by kvm_sys_reg_table_init() */ 4374 static struct sys_reg_desc invariant_sys_regs[] __ro_after_init = { 4375 { SYS_DESC(SYS_MIDR_EL1), NULL, reset_midr_el1 }, 4376 { SYS_DESC(SYS_REVIDR_EL1), NULL, reset_revidr_el1 }, 4377 { SYS_DESC(SYS_AIDR_EL1), NULL, reset_aidr_el1 }, 4378 }; 4379 4380 static int get_invariant_sys_reg(u64 id, u64 __user *uaddr) 4381 { 4382 const struct sys_reg_desc *r; 4383 4384 r = get_reg_by_id(id, invariant_sys_regs, 4385 ARRAY_SIZE(invariant_sys_regs)); 4386 if (!r) 4387 return -ENOENT; 4388 4389 return put_user(r->val, uaddr); 4390 } 4391 4392 static int set_invariant_sys_reg(u64 id, u64 __user *uaddr) 4393 { 4394 const struct sys_reg_desc *r; 4395 u64 val; 4396 4397 r = get_reg_by_id(id, invariant_sys_regs, 4398 ARRAY_SIZE(invariant_sys_regs)); 4399 if (!r) 4400 return -ENOENT; 4401 4402 if (get_user(val, uaddr)) 4403 return -EFAULT; 4404 4405 /* This is what we mean by invariant: you can't change it. */ 4406 if (r->val != val) 4407 return -EINVAL; 4408 4409 return 0; 4410 } 4411 4412 static int demux_c15_get(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) 4413 { 4414 u32 val; 4415 u32 __user *uval = uaddr; 4416 4417 /* Fail if we have unknown bits set. */ 4418 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 4419 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 4420 return -ENOENT; 4421 4422 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 4423 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 4424 if (KVM_REG_SIZE(id) != 4) 4425 return -ENOENT; 4426 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 4427 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 4428 if (val >= CSSELR_MAX) 4429 return -ENOENT; 4430 4431 return put_user(get_ccsidr(vcpu, val), uval); 4432 default: 4433 return -ENOENT; 4434 } 4435 } 4436 4437 static int demux_c15_set(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) 4438 { 4439 u32 val, newval; 4440 u32 __user *uval = uaddr; 4441 4442 /* Fail if we have unknown bits set. */ 4443 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 4444 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 4445 return -ENOENT; 4446 4447 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 4448 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 4449 if (KVM_REG_SIZE(id) != 4) 4450 return -ENOENT; 4451 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 4452 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 4453 if (val >= CSSELR_MAX) 4454 return -ENOENT; 4455 4456 if (get_user(newval, uval)) 4457 return -EFAULT; 4458 4459 return set_ccsidr(vcpu, val, newval); 4460 default: 4461 return -ENOENT; 4462 } 4463 } 4464 4465 int kvm_sys_reg_get_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg, 4466 const struct sys_reg_desc table[], unsigned int num) 4467 { 4468 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr; 4469 const struct sys_reg_desc *r; 4470 u64 val; 4471 int ret; 4472 4473 r = id_to_sys_reg_desc(vcpu, reg->id, table, num); 4474 if (!r || sysreg_hidden(vcpu, r)) 4475 return -ENOENT; 4476 4477 if (r->get_user) { 4478 ret = (r->get_user)(vcpu, r, &val); 4479 } else { 4480 val = __vcpu_sys_reg(vcpu, r->reg); 4481 ret = 0; 4482 } 4483 4484 if (!ret) 4485 ret = put_user(val, uaddr); 4486 4487 return ret; 4488 } 4489 4490 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 4491 { 4492 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 4493 int err; 4494 4495 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 4496 return demux_c15_get(vcpu, reg->id, uaddr); 4497 4498 err = get_invariant_sys_reg(reg->id, uaddr); 4499 if (err != -ENOENT) 4500 return err; 4501 4502 return kvm_sys_reg_get_user(vcpu, reg, 4503 sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 4504 } 4505 4506 int kvm_sys_reg_set_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg, 4507 const struct sys_reg_desc table[], unsigned int num) 4508 { 4509 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr; 4510 const struct sys_reg_desc *r; 4511 u64 val; 4512 int ret; 4513 4514 if (get_user(val, uaddr)) 4515 return -EFAULT; 4516 4517 r = id_to_sys_reg_desc(vcpu, reg->id, table, num); 4518 if (!r || sysreg_hidden(vcpu, r)) 4519 return -ENOENT; 4520 4521 if (sysreg_user_write_ignore(vcpu, r)) 4522 return 0; 4523 4524 if (r->set_user) { 4525 ret = (r->set_user)(vcpu, r, val); 4526 } else { 4527 __vcpu_sys_reg(vcpu, r->reg) = val; 4528 ret = 0; 4529 } 4530 4531 return ret; 4532 } 4533 4534 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 4535 { 4536 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 4537 int err; 4538 4539 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 4540 return demux_c15_set(vcpu, reg->id, uaddr); 4541 4542 err = set_invariant_sys_reg(reg->id, uaddr); 4543 if (err != -ENOENT) 4544 return err; 4545 4546 return kvm_sys_reg_set_user(vcpu, reg, 4547 sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 4548 } 4549 4550 static unsigned int num_demux_regs(void) 4551 { 4552 return CSSELR_MAX; 4553 } 4554 4555 static int write_demux_regids(u64 __user *uindices) 4556 { 4557 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX; 4558 unsigned int i; 4559 4560 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR; 4561 for (i = 0; i < CSSELR_MAX; i++) { 4562 if (put_user(val | i, uindices)) 4563 return -EFAULT; 4564 uindices++; 4565 } 4566 return 0; 4567 } 4568 4569 static u64 sys_reg_to_index(const struct sys_reg_desc *reg) 4570 { 4571 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | 4572 KVM_REG_ARM64_SYSREG | 4573 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) | 4574 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) | 4575 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) | 4576 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) | 4577 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT)); 4578 } 4579 4580 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind) 4581 { 4582 if (!*uind) 4583 return true; 4584 4585 if (put_user(sys_reg_to_index(reg), *uind)) 4586 return false; 4587 4588 (*uind)++; 4589 return true; 4590 } 4591 4592 static int walk_one_sys_reg(const struct kvm_vcpu *vcpu, 4593 const struct sys_reg_desc *rd, 4594 u64 __user **uind, 4595 unsigned int *total) 4596 { 4597 /* 4598 * Ignore registers we trap but don't save, 4599 * and for which no custom user accessor is provided. 4600 */ 4601 if (!(rd->reg || rd->get_user)) 4602 return 0; 4603 4604 if (sysreg_hidden(vcpu, rd)) 4605 return 0; 4606 4607 if (!copy_reg_to_user(rd, uind)) 4608 return -EFAULT; 4609 4610 (*total)++; 4611 return 0; 4612 } 4613 4614 /* Assumed ordered tables, see kvm_sys_reg_table_init. */ 4615 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind) 4616 { 4617 const struct sys_reg_desc *i2, *end2; 4618 unsigned int total = 0; 4619 int err; 4620 4621 i2 = sys_reg_descs; 4622 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs); 4623 4624 while (i2 != end2) { 4625 err = walk_one_sys_reg(vcpu, i2++, &uind, &total); 4626 if (err) 4627 return err; 4628 } 4629 return total; 4630 } 4631 4632 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu) 4633 { 4634 return ARRAY_SIZE(invariant_sys_regs) 4635 + num_demux_regs() 4636 + walk_sys_regs(vcpu, (u64 __user *)NULL); 4637 } 4638 4639 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) 4640 { 4641 unsigned int i; 4642 int err; 4643 4644 /* Then give them all the invariant registers' indices. */ 4645 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) { 4646 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices)) 4647 return -EFAULT; 4648 uindices++; 4649 } 4650 4651 err = walk_sys_regs(vcpu, uindices); 4652 if (err < 0) 4653 return err; 4654 uindices += err; 4655 4656 return write_demux_regids(uindices); 4657 } 4658 4659 #define KVM_ARM_FEATURE_ID_RANGE_INDEX(r) \ 4660 KVM_ARM_FEATURE_ID_RANGE_IDX(sys_reg_Op0(r), \ 4661 sys_reg_Op1(r), \ 4662 sys_reg_CRn(r), \ 4663 sys_reg_CRm(r), \ 4664 sys_reg_Op2(r)) 4665 4666 int kvm_vm_ioctl_get_reg_writable_masks(struct kvm *kvm, struct reg_mask_range *range) 4667 { 4668 const void *zero_page = page_to_virt(ZERO_PAGE(0)); 4669 u64 __user *masks = (u64 __user *)range->addr; 4670 4671 /* Only feature id range is supported, reserved[13] must be zero. */ 4672 if (range->range || 4673 memcmp(range->reserved, zero_page, sizeof(range->reserved))) 4674 return -EINVAL; 4675 4676 /* Wipe the whole thing first */ 4677 if (clear_user(masks, KVM_ARM_FEATURE_ID_RANGE_SIZE * sizeof(__u64))) 4678 return -EFAULT; 4679 4680 for (int i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { 4681 const struct sys_reg_desc *reg = &sys_reg_descs[i]; 4682 u32 encoding = reg_to_encoding(reg); 4683 u64 val; 4684 4685 if (!is_feature_id_reg(encoding) || !reg->set_user) 4686 continue; 4687 4688 if (!reg->val || 4689 (is_aa32_id_reg(encoding) && !kvm_supports_32bit_el0())) { 4690 continue; 4691 } 4692 val = reg->val; 4693 4694 if (put_user(val, (masks + KVM_ARM_FEATURE_ID_RANGE_INDEX(encoding)))) 4695 return -EFAULT; 4696 } 4697 4698 return 0; 4699 } 4700 4701 static void vcpu_set_hcr(struct kvm_vcpu *vcpu) 4702 { 4703 struct kvm *kvm = vcpu->kvm; 4704 4705 if (has_vhe() || has_hvhe()) 4706 vcpu->arch.hcr_el2 |= HCR_E2H; 4707 if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN)) { 4708 /* route synchronous external abort exceptions to EL2 */ 4709 vcpu->arch.hcr_el2 |= HCR_TEA; 4710 /* trap error record accesses */ 4711 vcpu->arch.hcr_el2 |= HCR_TERR; 4712 } 4713 4714 if (cpus_have_final_cap(ARM64_HAS_STAGE2_FWB)) 4715 vcpu->arch.hcr_el2 |= HCR_FWB; 4716 4717 if (cpus_have_final_cap(ARM64_HAS_EVT) && 4718 !cpus_have_final_cap(ARM64_MISMATCHED_CACHE_TYPE) && 4719 kvm_read_vm_id_reg(kvm, SYS_CTR_EL0) == read_sanitised_ftr_reg(SYS_CTR_EL0)) 4720 vcpu->arch.hcr_el2 |= HCR_TID4; 4721 else 4722 vcpu->arch.hcr_el2 |= HCR_TID2; 4723 4724 if (vcpu_el1_is_32bit(vcpu)) 4725 vcpu->arch.hcr_el2 &= ~HCR_RW; 4726 4727 if (kvm_has_mte(vcpu->kvm)) 4728 vcpu->arch.hcr_el2 |= HCR_ATA; 4729 4730 /* 4731 * In the absence of FGT, we cannot independently trap TLBI 4732 * Range instructions. This isn't great, but trapping all 4733 * TLBIs would be far worse. Live with it... 4734 */ 4735 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 4736 vcpu->arch.hcr_el2 |= HCR_TTLBOS; 4737 } 4738 4739 void kvm_calculate_traps(struct kvm_vcpu *vcpu) 4740 { 4741 struct kvm *kvm = vcpu->kvm; 4742 4743 mutex_lock(&kvm->arch.config_lock); 4744 vcpu_set_hcr(vcpu); 4745 vcpu_set_ich_hcr(vcpu); 4746 4747 if (cpus_have_final_cap(ARM64_HAS_HCX)) { 4748 /* 4749 * In general, all HCRX_EL2 bits are gated by a feature. 4750 * The only reason we can set SMPME without checking any 4751 * feature is that its effects are not directly observable 4752 * from the guest. 4753 */ 4754 vcpu->arch.hcrx_el2 = HCRX_EL2_SMPME; 4755 4756 if (kvm_has_feat(kvm, ID_AA64ISAR2_EL1, MOPS, IMP)) 4757 vcpu->arch.hcrx_el2 |= (HCRX_EL2_MSCEn | HCRX_EL2_MCE2); 4758 4759 if (kvm_has_feat(kvm, ID_AA64MMFR3_EL1, TCRX, IMP)) 4760 vcpu->arch.hcrx_el2 |= HCRX_EL2_TCR2En; 4761 4762 if (kvm_has_fpmr(kvm)) 4763 vcpu->arch.hcrx_el2 |= HCRX_EL2_EnFPM; 4764 } 4765 4766 if (test_bit(KVM_ARCH_FLAG_FGU_INITIALIZED, &kvm->arch.flags)) 4767 goto out; 4768 4769 kvm->arch.fgu[HFGxTR_GROUP] = (HFGxTR_EL2_nAMAIR2_EL1 | 4770 HFGxTR_EL2_nMAIR2_EL1 | 4771 HFGxTR_EL2_nS2POR_EL1 | 4772 HFGxTR_EL2_nACCDATA_EL1 | 4773 HFGxTR_EL2_nSMPRI_EL1_MASK | 4774 HFGxTR_EL2_nTPIDR2_EL0_MASK); 4775 4776 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 4777 kvm->arch.fgu[HFGITR_GROUP] |= (HFGITR_EL2_TLBIRVAALE1OS| 4778 HFGITR_EL2_TLBIRVALE1OS | 4779 HFGITR_EL2_TLBIRVAAE1OS | 4780 HFGITR_EL2_TLBIRVAE1OS | 4781 HFGITR_EL2_TLBIVAALE1OS | 4782 HFGITR_EL2_TLBIVALE1OS | 4783 HFGITR_EL2_TLBIVAAE1OS | 4784 HFGITR_EL2_TLBIASIDE1OS | 4785 HFGITR_EL2_TLBIVAE1OS | 4786 HFGITR_EL2_TLBIVMALLE1OS); 4787 4788 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE)) 4789 kvm->arch.fgu[HFGITR_GROUP] |= (HFGITR_EL2_TLBIRVAALE1 | 4790 HFGITR_EL2_TLBIRVALE1 | 4791 HFGITR_EL2_TLBIRVAAE1 | 4792 HFGITR_EL2_TLBIRVAE1 | 4793 HFGITR_EL2_TLBIRVAALE1IS| 4794 HFGITR_EL2_TLBIRVALE1IS | 4795 HFGITR_EL2_TLBIRVAAE1IS | 4796 HFGITR_EL2_TLBIRVAE1IS | 4797 HFGITR_EL2_TLBIRVAALE1OS| 4798 HFGITR_EL2_TLBIRVALE1OS | 4799 HFGITR_EL2_TLBIRVAAE1OS | 4800 HFGITR_EL2_TLBIRVAE1OS); 4801 4802 if (!kvm_has_feat(kvm, ID_AA64ISAR2_EL1, ATS1A, IMP)) 4803 kvm->arch.fgu[HFGITR_GROUP] |= HFGITR_EL2_ATS1E1A; 4804 4805 if (!kvm_has_feat(kvm, ID_AA64MMFR1_EL1, PAN, PAN2)) 4806 kvm->arch.fgu[HFGITR_GROUP] |= (HFGITR_EL2_ATS1E1RP | 4807 HFGITR_EL2_ATS1E1WP); 4808 4809 if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, S1PIE, IMP)) 4810 kvm->arch.fgu[HFGxTR_GROUP] |= (HFGxTR_EL2_nPIRE0_EL1 | 4811 HFGxTR_EL2_nPIR_EL1); 4812 4813 if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, S1POE, IMP)) 4814 kvm->arch.fgu[HFGxTR_GROUP] |= (HFGxTR_EL2_nPOR_EL1 | 4815 HFGxTR_EL2_nPOR_EL0); 4816 4817 if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, AMU, IMP)) 4818 kvm->arch.fgu[HAFGRTR_GROUP] |= ~(HAFGRTR_EL2_RES0 | 4819 HAFGRTR_EL2_RES1); 4820 4821 set_bit(KVM_ARCH_FLAG_FGU_INITIALIZED, &kvm->arch.flags); 4822 out: 4823 mutex_unlock(&kvm->arch.config_lock); 4824 } 4825 4826 /* 4827 * Perform last adjustments to the ID registers that are implied by the 4828 * configuration outside of the ID regs themselves, as well as any 4829 * initialisation that directly depend on these ID registers (such as 4830 * RES0/RES1 behaviours). This is not the place to configure traps though. 4831 * 4832 * Because this can be called once per CPU, changes must be idempotent. 4833 */ 4834 int kvm_finalize_sys_regs(struct kvm_vcpu *vcpu) 4835 { 4836 struct kvm *kvm = vcpu->kvm; 4837 4838 guard(mutex)(&kvm->arch.config_lock); 4839 4840 if (!(static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif) && 4841 irqchip_in_kernel(kvm) && 4842 kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3)) { 4843 kvm->arch.id_regs[IDREG_IDX(SYS_ID_AA64PFR0_EL1)] &= ~ID_AA64PFR0_EL1_GIC_MASK; 4844 kvm->arch.id_regs[IDREG_IDX(SYS_ID_PFR1_EL1)] &= ~ID_PFR1_EL1_GIC_MASK; 4845 } 4846 4847 if (vcpu_has_nv(vcpu)) { 4848 int ret = kvm_init_nv_sysregs(kvm); 4849 if (ret) 4850 return ret; 4851 } 4852 4853 return 0; 4854 } 4855 4856 int __init kvm_sys_reg_table_init(void) 4857 { 4858 bool valid = true; 4859 unsigned int i; 4860 int ret = 0; 4861 4862 /* Make sure tables are unique and in order. */ 4863 valid &= check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), false); 4864 valid &= check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), true); 4865 valid &= check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), true); 4866 valid &= check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), true); 4867 valid &= check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), true); 4868 valid &= check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs), false); 4869 valid &= check_sysreg_table(sys_insn_descs, ARRAY_SIZE(sys_insn_descs), false); 4870 4871 if (!valid) 4872 return -EINVAL; 4873 4874 /* We abuse the reset function to overwrite the table itself. */ 4875 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) 4876 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]); 4877 4878 ret = populate_nv_trap_config(); 4879 4880 for (i = 0; !ret && i < ARRAY_SIZE(sys_reg_descs); i++) 4881 ret = populate_sysreg_config(sys_reg_descs + i, i); 4882 4883 for (i = 0; !ret && i < ARRAY_SIZE(sys_insn_descs); i++) 4884 ret = populate_sysreg_config(sys_insn_descs + i, i); 4885 4886 return ret; 4887 } 4888