1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/kvm/coproc.c: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Authors: Rusty Russell <rusty@rustcorp.com.au> 9 * Christoffer Dall <c.dall@virtualopensystems.com> 10 */ 11 12 #include <linux/bitfield.h> 13 #include <linux/bsearch.h> 14 #include <linux/cacheinfo.h> 15 #include <linux/debugfs.h> 16 #include <linux/kvm_host.h> 17 #include <linux/mm.h> 18 #include <linux/printk.h> 19 #include <linux/uaccess.h> 20 #include <linux/irqchip/arm-gic-v3.h> 21 22 #include <asm/arm_pmuv3.h> 23 #include <asm/cacheflush.h> 24 #include <asm/cputype.h> 25 #include <asm/debug-monitors.h> 26 #include <asm/esr.h> 27 #include <asm/kvm_arm.h> 28 #include <asm/kvm_emulate.h> 29 #include <asm/kvm_hyp.h> 30 #include <asm/kvm_mmu.h> 31 #include <asm/kvm_nested.h> 32 #include <asm/perf_event.h> 33 #include <asm/sysreg.h> 34 35 #include <trace/events/kvm.h> 36 37 #include "sys_regs.h" 38 #include "vgic/vgic.h" 39 40 #include "trace.h" 41 42 /* 43 * For AArch32, we only take care of what is being trapped. Anything 44 * that has to do with init and userspace access has to go via the 45 * 64bit interface. 46 */ 47 48 static u64 sys_reg_to_index(const struct sys_reg_desc *reg); 49 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 50 u64 val); 51 52 static bool undef_access(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 53 const struct sys_reg_desc *r) 54 { 55 kvm_inject_undefined(vcpu); 56 return false; 57 } 58 59 static bool bad_trap(struct kvm_vcpu *vcpu, 60 struct sys_reg_params *params, 61 const struct sys_reg_desc *r, 62 const char *msg) 63 { 64 WARN_ONCE(1, "Unexpected %s\n", msg); 65 print_sys_reg_instr(params); 66 return undef_access(vcpu, params, r); 67 } 68 69 static bool read_from_write_only(struct kvm_vcpu *vcpu, 70 struct sys_reg_params *params, 71 const struct sys_reg_desc *r) 72 { 73 return bad_trap(vcpu, params, r, 74 "sys_reg read to write-only register"); 75 } 76 77 static bool write_to_read_only(struct kvm_vcpu *vcpu, 78 struct sys_reg_params *params, 79 const struct sys_reg_desc *r) 80 { 81 return bad_trap(vcpu, params, r, 82 "sys_reg write to read-only register"); 83 } 84 85 #define PURE_EL2_SYSREG(el2) \ 86 case el2: { \ 87 *el1r = el2; \ 88 return true; \ 89 } 90 91 #define MAPPED_EL2_SYSREG(el2, el1, fn) \ 92 case el2: { \ 93 *xlate = fn; \ 94 *el1r = el1; \ 95 return true; \ 96 } 97 98 static bool get_el2_to_el1_mapping(unsigned int reg, 99 unsigned int *el1r, u64 (**xlate)(u64)) 100 { 101 switch (reg) { 102 PURE_EL2_SYSREG( VPIDR_EL2 ); 103 PURE_EL2_SYSREG( VMPIDR_EL2 ); 104 PURE_EL2_SYSREG( ACTLR_EL2 ); 105 PURE_EL2_SYSREG( HCR_EL2 ); 106 PURE_EL2_SYSREG( MDCR_EL2 ); 107 PURE_EL2_SYSREG( HSTR_EL2 ); 108 PURE_EL2_SYSREG( HACR_EL2 ); 109 PURE_EL2_SYSREG( VTTBR_EL2 ); 110 PURE_EL2_SYSREG( VTCR_EL2 ); 111 PURE_EL2_SYSREG( TPIDR_EL2 ); 112 PURE_EL2_SYSREG( HPFAR_EL2 ); 113 PURE_EL2_SYSREG( HCRX_EL2 ); 114 PURE_EL2_SYSREG( HFGRTR_EL2 ); 115 PURE_EL2_SYSREG( HFGWTR_EL2 ); 116 PURE_EL2_SYSREG( HFGITR_EL2 ); 117 PURE_EL2_SYSREG( HDFGRTR_EL2 ); 118 PURE_EL2_SYSREG( HDFGWTR_EL2 ); 119 PURE_EL2_SYSREG( HAFGRTR_EL2 ); 120 PURE_EL2_SYSREG( CNTVOFF_EL2 ); 121 PURE_EL2_SYSREG( CNTHCTL_EL2 ); 122 MAPPED_EL2_SYSREG(SCTLR_EL2, SCTLR_EL1, 123 translate_sctlr_el2_to_sctlr_el1 ); 124 MAPPED_EL2_SYSREG(CPTR_EL2, CPACR_EL1, 125 translate_cptr_el2_to_cpacr_el1 ); 126 MAPPED_EL2_SYSREG(TTBR0_EL2, TTBR0_EL1, 127 translate_ttbr0_el2_to_ttbr0_el1 ); 128 MAPPED_EL2_SYSREG(TTBR1_EL2, TTBR1_EL1, NULL ); 129 MAPPED_EL2_SYSREG(TCR_EL2, TCR_EL1, 130 translate_tcr_el2_to_tcr_el1 ); 131 MAPPED_EL2_SYSREG(VBAR_EL2, VBAR_EL1, NULL ); 132 MAPPED_EL2_SYSREG(AFSR0_EL2, AFSR0_EL1, NULL ); 133 MAPPED_EL2_SYSREG(AFSR1_EL2, AFSR1_EL1, NULL ); 134 MAPPED_EL2_SYSREG(ESR_EL2, ESR_EL1, NULL ); 135 MAPPED_EL2_SYSREG(FAR_EL2, FAR_EL1, NULL ); 136 MAPPED_EL2_SYSREG(MAIR_EL2, MAIR_EL1, NULL ); 137 MAPPED_EL2_SYSREG(TCR2_EL2, TCR2_EL1, NULL ); 138 MAPPED_EL2_SYSREG(PIR_EL2, PIR_EL1, NULL ); 139 MAPPED_EL2_SYSREG(PIRE0_EL2, PIRE0_EL1, NULL ); 140 MAPPED_EL2_SYSREG(POR_EL2, POR_EL1, NULL ); 141 MAPPED_EL2_SYSREG(AMAIR_EL2, AMAIR_EL1, NULL ); 142 MAPPED_EL2_SYSREG(ELR_EL2, ELR_EL1, NULL ); 143 MAPPED_EL2_SYSREG(SPSR_EL2, SPSR_EL1, NULL ); 144 MAPPED_EL2_SYSREG(ZCR_EL2, ZCR_EL1, NULL ); 145 MAPPED_EL2_SYSREG(CONTEXTIDR_EL2, CONTEXTIDR_EL1, NULL ); 146 MAPPED_EL2_SYSREG(SCTLR2_EL2, SCTLR2_EL1, NULL ); 147 default: 148 return false; 149 } 150 } 151 152 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg) 153 { 154 u64 val = 0x8badf00d8badf00d; 155 u64 (*xlate)(u64) = NULL; 156 unsigned int el1r; 157 158 if (!vcpu_get_flag(vcpu, SYSREGS_ON_CPU)) 159 goto memory_read; 160 161 if (unlikely(get_el2_to_el1_mapping(reg, &el1r, &xlate))) { 162 if (!is_hyp_ctxt(vcpu)) 163 goto memory_read; 164 165 /* 166 * CNTHCTL_EL2 requires some special treatment to 167 * account for the bits that can be set via CNTKCTL_EL1. 168 */ 169 switch (reg) { 170 case CNTHCTL_EL2: 171 if (vcpu_el2_e2h_is_set(vcpu)) { 172 val = read_sysreg_el1(SYS_CNTKCTL); 173 val &= CNTKCTL_VALID_BITS; 174 val |= __vcpu_sys_reg(vcpu, reg) & ~CNTKCTL_VALID_BITS; 175 return val; 176 } 177 break; 178 } 179 180 /* 181 * If this register does not have an EL1 counterpart, 182 * then read the stored EL2 version. 183 */ 184 if (reg == el1r) 185 goto memory_read; 186 187 /* 188 * If we have a non-VHE guest and that the sysreg 189 * requires translation to be used at EL1, use the 190 * in-memory copy instead. 191 */ 192 if (!vcpu_el2_e2h_is_set(vcpu) && xlate) 193 goto memory_read; 194 195 /* Get the current version of the EL1 counterpart. */ 196 WARN_ON(!__vcpu_read_sys_reg_from_cpu(el1r, &val)); 197 if (reg >= __SANITISED_REG_START__) 198 val = kvm_vcpu_apply_reg_masks(vcpu, reg, val); 199 200 return val; 201 } 202 203 /* EL1 register can't be on the CPU if the guest is in vEL2. */ 204 if (unlikely(is_hyp_ctxt(vcpu))) 205 goto memory_read; 206 207 if (__vcpu_read_sys_reg_from_cpu(reg, &val)) 208 return val; 209 210 memory_read: 211 return __vcpu_sys_reg(vcpu, reg); 212 } 213 214 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg) 215 { 216 u64 (*xlate)(u64) = NULL; 217 unsigned int el1r; 218 219 if (!vcpu_get_flag(vcpu, SYSREGS_ON_CPU)) 220 goto memory_write; 221 222 if (unlikely(get_el2_to_el1_mapping(reg, &el1r, &xlate))) { 223 if (!is_hyp_ctxt(vcpu)) 224 goto memory_write; 225 226 /* 227 * Always store a copy of the write to memory to avoid having 228 * to reverse-translate virtual EL2 system registers for a 229 * non-VHE guest hypervisor. 230 */ 231 __vcpu_assign_sys_reg(vcpu, reg, val); 232 233 switch (reg) { 234 case CNTHCTL_EL2: 235 /* 236 * If E2H=0, CNHTCTL_EL2 is a pure shadow register. 237 * Otherwise, some of the bits are backed by 238 * CNTKCTL_EL1, while the rest is kept in memory. 239 * Yes, this is fun stuff. 240 */ 241 if (vcpu_el2_e2h_is_set(vcpu)) 242 write_sysreg_el1(val, SYS_CNTKCTL); 243 return; 244 } 245 246 /* No EL1 counterpart? We're done here.? */ 247 if (reg == el1r) 248 return; 249 250 if (!vcpu_el2_e2h_is_set(vcpu) && xlate) 251 val = xlate(val); 252 253 /* Redirect this to the EL1 version of the register. */ 254 WARN_ON(!__vcpu_write_sys_reg_to_cpu(val, el1r)); 255 return; 256 } 257 258 /* EL1 register can't be on the CPU if the guest is in vEL2. */ 259 if (unlikely(is_hyp_ctxt(vcpu))) 260 goto memory_write; 261 262 if (__vcpu_write_sys_reg_to_cpu(val, reg)) 263 return; 264 265 memory_write: 266 __vcpu_assign_sys_reg(vcpu, reg, val); 267 } 268 269 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */ 270 #define CSSELR_MAX 14 271 272 /* 273 * Returns the minimum line size for the selected cache, expressed as 274 * Log2(bytes). 275 */ 276 static u8 get_min_cache_line_size(bool icache) 277 { 278 u64 ctr = read_sanitised_ftr_reg(SYS_CTR_EL0); 279 u8 field; 280 281 if (icache) 282 field = SYS_FIELD_GET(CTR_EL0, IminLine, ctr); 283 else 284 field = SYS_FIELD_GET(CTR_EL0, DminLine, ctr); 285 286 /* 287 * Cache line size is represented as Log2(words) in CTR_EL0. 288 * Log2(bytes) can be derived with the following: 289 * 290 * Log2(words) + 2 = Log2(bytes / 4) + 2 291 * = Log2(bytes) - 2 + 2 292 * = Log2(bytes) 293 */ 294 return field + 2; 295 } 296 297 /* Which cache CCSIDR represents depends on CSSELR value. */ 298 static u32 get_ccsidr(struct kvm_vcpu *vcpu, u32 csselr) 299 { 300 u8 line_size; 301 302 if (vcpu->arch.ccsidr) 303 return vcpu->arch.ccsidr[csselr]; 304 305 line_size = get_min_cache_line_size(csselr & CSSELR_EL1_InD); 306 307 /* 308 * Fabricate a CCSIDR value as the overriding value does not exist. 309 * The real CCSIDR value will not be used as it can vary by the 310 * physical CPU which the vcpu currently resides in. 311 * 312 * The line size is determined with get_min_cache_line_size(), which 313 * should be valid for all CPUs even if they have different cache 314 * configuration. 315 * 316 * The associativity bits are cleared, meaning the geometry of all data 317 * and unified caches (which are guaranteed to be PIPT and thus 318 * non-aliasing) are 1 set and 1 way. 319 * Guests should not be doing cache operations by set/way at all, and 320 * for this reason, we trap them and attempt to infer the intent, so 321 * that we can flush the entire guest's address space at the appropriate 322 * time. The exposed geometry minimizes the number of the traps. 323 * [If guests should attempt to infer aliasing properties from the 324 * geometry (which is not permitted by the architecture), they would 325 * only do so for virtually indexed caches.] 326 * 327 * We don't check if the cache level exists as it is allowed to return 328 * an UNKNOWN value if not. 329 */ 330 return SYS_FIELD_PREP(CCSIDR_EL1, LineSize, line_size - 4); 331 } 332 333 static int set_ccsidr(struct kvm_vcpu *vcpu, u32 csselr, u32 val) 334 { 335 u8 line_size = FIELD_GET(CCSIDR_EL1_LineSize, val) + 4; 336 u32 *ccsidr = vcpu->arch.ccsidr; 337 u32 i; 338 339 if ((val & CCSIDR_EL1_RES0) || 340 line_size < get_min_cache_line_size(csselr & CSSELR_EL1_InD)) 341 return -EINVAL; 342 343 if (!ccsidr) { 344 if (val == get_ccsidr(vcpu, csselr)) 345 return 0; 346 347 ccsidr = kmalloc_array(CSSELR_MAX, sizeof(u32), GFP_KERNEL_ACCOUNT); 348 if (!ccsidr) 349 return -ENOMEM; 350 351 for (i = 0; i < CSSELR_MAX; i++) 352 ccsidr[i] = get_ccsidr(vcpu, i); 353 354 vcpu->arch.ccsidr = ccsidr; 355 } 356 357 ccsidr[csselr] = val; 358 359 return 0; 360 } 361 362 static bool access_rw(struct kvm_vcpu *vcpu, 363 struct sys_reg_params *p, 364 const struct sys_reg_desc *r) 365 { 366 if (p->is_write) 367 vcpu_write_sys_reg(vcpu, p->regval, r->reg); 368 else 369 p->regval = vcpu_read_sys_reg(vcpu, r->reg); 370 371 return true; 372 } 373 374 /* 375 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized). 376 */ 377 static bool access_dcsw(struct kvm_vcpu *vcpu, 378 struct sys_reg_params *p, 379 const struct sys_reg_desc *r) 380 { 381 if (!p->is_write) 382 return read_from_write_only(vcpu, p, r); 383 384 /* 385 * Only track S/W ops if we don't have FWB. It still indicates 386 * that the guest is a bit broken (S/W operations should only 387 * be done by firmware, knowing that there is only a single 388 * CPU left in the system, and certainly not from non-secure 389 * software). 390 */ 391 if (!cpus_have_final_cap(ARM64_HAS_STAGE2_FWB)) 392 kvm_set_way_flush(vcpu); 393 394 return true; 395 } 396 397 static bool access_dcgsw(struct kvm_vcpu *vcpu, 398 struct sys_reg_params *p, 399 const struct sys_reg_desc *r) 400 { 401 if (!kvm_has_mte(vcpu->kvm)) 402 return undef_access(vcpu, p, r); 403 404 /* Treat MTE S/W ops as we treat the classic ones: with contempt */ 405 return access_dcsw(vcpu, p, r); 406 } 407 408 static void get_access_mask(const struct sys_reg_desc *r, u64 *mask, u64 *shift) 409 { 410 switch (r->aarch32_map) { 411 case AA32_LO: 412 *mask = GENMASK_ULL(31, 0); 413 *shift = 0; 414 break; 415 case AA32_HI: 416 *mask = GENMASK_ULL(63, 32); 417 *shift = 32; 418 break; 419 default: 420 *mask = GENMASK_ULL(63, 0); 421 *shift = 0; 422 break; 423 } 424 } 425 426 /* 427 * Generic accessor for VM registers. Only called as long as HCR_TVM 428 * is set. If the guest enables the MMU, we stop trapping the VM 429 * sys_regs and leave it in complete control of the caches. 430 */ 431 static bool access_vm_reg(struct kvm_vcpu *vcpu, 432 struct sys_reg_params *p, 433 const struct sys_reg_desc *r) 434 { 435 bool was_enabled = vcpu_has_cache_enabled(vcpu); 436 u64 val, mask, shift; 437 438 BUG_ON(!p->is_write); 439 440 get_access_mask(r, &mask, &shift); 441 442 if (~mask) { 443 val = vcpu_read_sys_reg(vcpu, r->reg); 444 val &= ~mask; 445 } else { 446 val = 0; 447 } 448 449 val |= (p->regval & (mask >> shift)) << shift; 450 vcpu_write_sys_reg(vcpu, val, r->reg); 451 452 kvm_toggle_cache(vcpu, was_enabled); 453 return true; 454 } 455 456 static bool access_actlr(struct kvm_vcpu *vcpu, 457 struct sys_reg_params *p, 458 const struct sys_reg_desc *r) 459 { 460 u64 mask, shift; 461 462 if (p->is_write) 463 return ignore_write(vcpu, p); 464 465 get_access_mask(r, &mask, &shift); 466 p->regval = (vcpu_read_sys_reg(vcpu, r->reg) & mask) >> shift; 467 468 return true; 469 } 470 471 /* 472 * Trap handler for the GICv3 SGI generation system register. 473 * Forward the request to the VGIC emulation. 474 * The cp15_64 code makes sure this automatically works 475 * for both AArch64 and AArch32 accesses. 476 */ 477 static bool access_gic_sgi(struct kvm_vcpu *vcpu, 478 struct sys_reg_params *p, 479 const struct sys_reg_desc *r) 480 { 481 bool g1; 482 483 if (!kvm_has_gicv3(vcpu->kvm)) 484 return undef_access(vcpu, p, r); 485 486 if (!p->is_write) 487 return read_from_write_only(vcpu, p, r); 488 489 /* 490 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates 491 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group, 492 * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively 493 * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure 494 * group. 495 */ 496 if (p->Op0 == 0) { /* AArch32 */ 497 switch (p->Op1) { 498 default: /* Keep GCC quiet */ 499 case 0: /* ICC_SGI1R */ 500 g1 = true; 501 break; 502 case 1: /* ICC_ASGI1R */ 503 case 2: /* ICC_SGI0R */ 504 g1 = false; 505 break; 506 } 507 } else { /* AArch64 */ 508 switch (p->Op2) { 509 default: /* Keep GCC quiet */ 510 case 5: /* ICC_SGI1R_EL1 */ 511 g1 = true; 512 break; 513 case 6: /* ICC_ASGI1R_EL1 */ 514 case 7: /* ICC_SGI0R_EL1 */ 515 g1 = false; 516 break; 517 } 518 } 519 520 vgic_v3_dispatch_sgi(vcpu, p->regval, g1); 521 522 return true; 523 } 524 525 static bool access_gic_sre(struct kvm_vcpu *vcpu, 526 struct sys_reg_params *p, 527 const struct sys_reg_desc *r) 528 { 529 if (!kvm_has_gicv3(vcpu->kvm)) 530 return undef_access(vcpu, p, r); 531 532 if (p->is_write) 533 return ignore_write(vcpu, p); 534 535 if (p->Op1 == 4) { /* ICC_SRE_EL2 */ 536 p->regval = KVM_ICC_SRE_EL2; 537 } else { /* ICC_SRE_EL1 */ 538 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre; 539 } 540 541 return true; 542 } 543 544 static bool trap_raz_wi(struct kvm_vcpu *vcpu, 545 struct sys_reg_params *p, 546 const struct sys_reg_desc *r) 547 { 548 if (p->is_write) 549 return ignore_write(vcpu, p); 550 else 551 return read_zero(vcpu, p); 552 } 553 554 /* 555 * ARMv8.1 mandates at least a trivial LORegion implementation, where all the 556 * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0 557 * system, these registers should UNDEF. LORID_EL1 being a RO register, we 558 * treat it separately. 559 */ 560 static bool trap_loregion(struct kvm_vcpu *vcpu, 561 struct sys_reg_params *p, 562 const struct sys_reg_desc *r) 563 { 564 u32 sr = reg_to_encoding(r); 565 566 if (!kvm_has_feat(vcpu->kvm, ID_AA64MMFR1_EL1, LO, IMP)) 567 return undef_access(vcpu, p, r); 568 569 if (p->is_write && sr == SYS_LORID_EL1) 570 return write_to_read_only(vcpu, p, r); 571 572 return trap_raz_wi(vcpu, p, r); 573 } 574 575 static bool trap_oslar_el1(struct kvm_vcpu *vcpu, 576 struct sys_reg_params *p, 577 const struct sys_reg_desc *r) 578 { 579 if (!p->is_write) 580 return read_from_write_only(vcpu, p, r); 581 582 kvm_debug_handle_oslar(vcpu, p->regval); 583 return true; 584 } 585 586 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu, 587 struct sys_reg_params *p, 588 const struct sys_reg_desc *r) 589 { 590 if (p->is_write) 591 return write_to_read_only(vcpu, p, r); 592 593 p->regval = __vcpu_sys_reg(vcpu, r->reg); 594 return true; 595 } 596 597 static int set_oslsr_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 598 u64 val) 599 { 600 /* 601 * The only modifiable bit is the OSLK bit. Refuse the write if 602 * userspace attempts to change any other bit in the register. 603 */ 604 if ((val ^ rd->val) & ~OSLSR_EL1_OSLK) 605 return -EINVAL; 606 607 __vcpu_assign_sys_reg(vcpu, rd->reg, val); 608 return 0; 609 } 610 611 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu, 612 struct sys_reg_params *p, 613 const struct sys_reg_desc *r) 614 { 615 if (p->is_write) { 616 return ignore_write(vcpu, p); 617 } else { 618 p->regval = read_sysreg(dbgauthstatus_el1); 619 return true; 620 } 621 } 622 623 static bool trap_debug_regs(struct kvm_vcpu *vcpu, 624 struct sys_reg_params *p, 625 const struct sys_reg_desc *r) 626 { 627 access_rw(vcpu, p, r); 628 629 kvm_debug_set_guest_ownership(vcpu); 630 return true; 631 } 632 633 /* 634 * reg_to_dbg/dbg_to_reg 635 * 636 * A 32 bit write to a debug register leave top bits alone 637 * A 32 bit read from a debug register only returns the bottom bits 638 */ 639 static void reg_to_dbg(struct kvm_vcpu *vcpu, 640 struct sys_reg_params *p, 641 const struct sys_reg_desc *rd, 642 u64 *dbg_reg) 643 { 644 u64 mask, shift, val; 645 646 get_access_mask(rd, &mask, &shift); 647 648 val = *dbg_reg; 649 val &= ~mask; 650 val |= (p->regval & (mask >> shift)) << shift; 651 *dbg_reg = val; 652 } 653 654 static void dbg_to_reg(struct kvm_vcpu *vcpu, 655 struct sys_reg_params *p, 656 const struct sys_reg_desc *rd, 657 u64 *dbg_reg) 658 { 659 u64 mask, shift; 660 661 get_access_mask(rd, &mask, &shift); 662 p->regval = (*dbg_reg & mask) >> shift; 663 } 664 665 static u64 *demux_wb_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd) 666 { 667 struct kvm_guest_debug_arch *dbg = &vcpu->arch.vcpu_debug_state; 668 669 switch (rd->Op2) { 670 case 0b100: 671 return &dbg->dbg_bvr[rd->CRm]; 672 case 0b101: 673 return &dbg->dbg_bcr[rd->CRm]; 674 case 0b110: 675 return &dbg->dbg_wvr[rd->CRm]; 676 case 0b111: 677 return &dbg->dbg_wcr[rd->CRm]; 678 default: 679 KVM_BUG_ON(1, vcpu->kvm); 680 return NULL; 681 } 682 } 683 684 static bool trap_dbg_wb_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 685 const struct sys_reg_desc *rd) 686 { 687 u64 *reg = demux_wb_reg(vcpu, rd); 688 689 if (!reg) 690 return false; 691 692 if (p->is_write) 693 reg_to_dbg(vcpu, p, rd, reg); 694 else 695 dbg_to_reg(vcpu, p, rd, reg); 696 697 kvm_debug_set_guest_ownership(vcpu); 698 return true; 699 } 700 701 static int set_dbg_wb_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 702 u64 val) 703 { 704 u64 *reg = demux_wb_reg(vcpu, rd); 705 706 if (!reg) 707 return -EINVAL; 708 709 *reg = val; 710 return 0; 711 } 712 713 static int get_dbg_wb_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 714 u64 *val) 715 { 716 u64 *reg = demux_wb_reg(vcpu, rd); 717 718 if (!reg) 719 return -EINVAL; 720 721 *val = *reg; 722 return 0; 723 } 724 725 static u64 reset_dbg_wb_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd) 726 { 727 u64 *reg = demux_wb_reg(vcpu, rd); 728 729 /* 730 * Bail early if we couldn't find storage for the register, the 731 * KVM_BUG_ON() in demux_wb_reg() will prevent this VM from ever 732 * being run. 733 */ 734 if (!reg) 735 return 0; 736 737 *reg = rd->val; 738 return rd->val; 739 } 740 741 static u64 reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 742 { 743 u64 amair = read_sysreg(amair_el1); 744 vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1); 745 return amair; 746 } 747 748 static u64 reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 749 { 750 u64 actlr = read_sysreg(actlr_el1); 751 vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1); 752 return actlr; 753 } 754 755 static u64 reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 756 { 757 u64 mpidr; 758 759 /* 760 * Map the vcpu_id into the first three affinity level fields of 761 * the MPIDR. We limit the number of VCPUs in level 0 due to a 762 * limitation to 16 CPUs in that level in the ICC_SGIxR registers 763 * of the GICv3 to be able to address each CPU directly when 764 * sending IPIs. 765 */ 766 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0); 767 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1); 768 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2); 769 mpidr |= (1ULL << 31); 770 vcpu_write_sys_reg(vcpu, mpidr, MPIDR_EL1); 771 772 return mpidr; 773 } 774 775 static unsigned int hidden_visibility(const struct kvm_vcpu *vcpu, 776 const struct sys_reg_desc *r) 777 { 778 return REG_HIDDEN; 779 } 780 781 static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu, 782 const struct sys_reg_desc *r) 783 { 784 if (kvm_vcpu_has_pmu(vcpu)) 785 return 0; 786 787 return REG_HIDDEN; 788 } 789 790 static u64 reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 791 { 792 u64 mask = BIT(ARMV8_PMU_CYCLE_IDX); 793 u8 n = vcpu->kvm->arch.nr_pmu_counters; 794 795 if (n) 796 mask |= GENMASK(n - 1, 0); 797 798 reset_unknown(vcpu, r); 799 __vcpu_rmw_sys_reg(vcpu, r->reg, &=, mask); 800 801 return __vcpu_sys_reg(vcpu, r->reg); 802 } 803 804 static u64 reset_pmevcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 805 { 806 reset_unknown(vcpu, r); 807 __vcpu_rmw_sys_reg(vcpu, r->reg, &=, GENMASK(31, 0)); 808 809 return __vcpu_sys_reg(vcpu, r->reg); 810 } 811 812 static u64 reset_pmevtyper(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 813 { 814 /* This thing will UNDEF, who cares about the reset value? */ 815 if (!kvm_vcpu_has_pmu(vcpu)) 816 return 0; 817 818 reset_unknown(vcpu, r); 819 __vcpu_rmw_sys_reg(vcpu, r->reg, &=, kvm_pmu_evtyper_mask(vcpu->kvm)); 820 821 return __vcpu_sys_reg(vcpu, r->reg); 822 } 823 824 static u64 reset_pmselr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 825 { 826 reset_unknown(vcpu, r); 827 __vcpu_rmw_sys_reg(vcpu, r->reg, &=, PMSELR_EL0_SEL_MASK); 828 829 return __vcpu_sys_reg(vcpu, r->reg); 830 } 831 832 static u64 reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 833 { 834 u64 pmcr = 0; 835 836 if (!kvm_supports_32bit_el0()) 837 pmcr |= ARMV8_PMU_PMCR_LC; 838 839 /* 840 * The value of PMCR.N field is included when the 841 * vCPU register is read via kvm_vcpu_read_pmcr(). 842 */ 843 __vcpu_assign_sys_reg(vcpu, r->reg, pmcr); 844 845 return __vcpu_sys_reg(vcpu, r->reg); 846 } 847 848 static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags) 849 { 850 u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0); 851 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu); 852 853 if (!enabled) 854 kvm_inject_undefined(vcpu); 855 856 return !enabled; 857 } 858 859 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu) 860 { 861 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN); 862 } 863 864 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu) 865 { 866 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN); 867 } 868 869 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu) 870 { 871 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN); 872 } 873 874 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu) 875 { 876 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN); 877 } 878 879 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 880 const struct sys_reg_desc *r) 881 { 882 u64 val; 883 884 if (pmu_access_el0_disabled(vcpu)) 885 return false; 886 887 if (p->is_write) { 888 /* 889 * Only update writeable bits of PMCR (continuing into 890 * kvm_pmu_handle_pmcr() as well) 891 */ 892 val = kvm_vcpu_read_pmcr(vcpu); 893 val &= ~ARMV8_PMU_PMCR_MASK; 894 val |= p->regval & ARMV8_PMU_PMCR_MASK; 895 if (!kvm_supports_32bit_el0()) 896 val |= ARMV8_PMU_PMCR_LC; 897 kvm_pmu_handle_pmcr(vcpu, val); 898 } else { 899 /* PMCR.P & PMCR.C are RAZ */ 900 val = kvm_vcpu_read_pmcr(vcpu) 901 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C); 902 p->regval = val; 903 } 904 905 return true; 906 } 907 908 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 909 const struct sys_reg_desc *r) 910 { 911 if (pmu_access_event_counter_el0_disabled(vcpu)) 912 return false; 913 914 if (p->is_write) 915 __vcpu_assign_sys_reg(vcpu, PMSELR_EL0, p->regval); 916 else 917 /* return PMSELR.SEL field */ 918 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0) 919 & PMSELR_EL0_SEL_MASK; 920 921 return true; 922 } 923 924 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 925 const struct sys_reg_desc *r) 926 { 927 u64 pmceid, mask, shift; 928 929 BUG_ON(p->is_write); 930 931 if (pmu_access_el0_disabled(vcpu)) 932 return false; 933 934 get_access_mask(r, &mask, &shift); 935 936 pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1)); 937 pmceid &= mask; 938 pmceid >>= shift; 939 940 p->regval = pmceid; 941 942 return true; 943 } 944 945 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx) 946 { 947 u64 pmcr, val; 948 949 pmcr = kvm_vcpu_read_pmcr(vcpu); 950 val = FIELD_GET(ARMV8_PMU_PMCR_N, pmcr); 951 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) { 952 kvm_inject_undefined(vcpu); 953 return false; 954 } 955 956 return true; 957 } 958 959 static int get_pmu_evcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 960 u64 *val) 961 { 962 u64 idx; 963 964 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 0) 965 /* PMCCNTR_EL0 */ 966 idx = ARMV8_PMU_CYCLE_IDX; 967 else 968 /* PMEVCNTRn_EL0 */ 969 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 970 971 *val = kvm_pmu_get_counter_value(vcpu, idx); 972 return 0; 973 } 974 975 static int set_pmu_evcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 976 u64 val) 977 { 978 u64 idx; 979 980 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 0) 981 /* PMCCNTR_EL0 */ 982 idx = ARMV8_PMU_CYCLE_IDX; 983 else 984 /* PMEVCNTRn_EL0 */ 985 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 986 987 kvm_pmu_set_counter_value_user(vcpu, idx, val); 988 return 0; 989 } 990 991 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu, 992 struct sys_reg_params *p, 993 const struct sys_reg_desc *r) 994 { 995 u64 idx = ~0UL; 996 997 if (r->CRn == 9 && r->CRm == 13) { 998 if (r->Op2 == 2) { 999 /* PMXEVCNTR_EL0 */ 1000 if (pmu_access_event_counter_el0_disabled(vcpu)) 1001 return false; 1002 1003 idx = SYS_FIELD_GET(PMSELR_EL0, SEL, 1004 __vcpu_sys_reg(vcpu, PMSELR_EL0)); 1005 } else if (r->Op2 == 0) { 1006 /* PMCCNTR_EL0 */ 1007 if (pmu_access_cycle_counter_el0_disabled(vcpu)) 1008 return false; 1009 1010 idx = ARMV8_PMU_CYCLE_IDX; 1011 } 1012 } else if (r->CRn == 0 && r->CRm == 9) { 1013 /* PMCCNTR */ 1014 if (pmu_access_event_counter_el0_disabled(vcpu)) 1015 return false; 1016 1017 idx = ARMV8_PMU_CYCLE_IDX; 1018 } else if (r->CRn == 14 && (r->CRm & 12) == 8) { 1019 /* PMEVCNTRn_EL0 */ 1020 if (pmu_access_event_counter_el0_disabled(vcpu)) 1021 return false; 1022 1023 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 1024 } 1025 1026 /* Catch any decoding mistake */ 1027 WARN_ON(idx == ~0UL); 1028 1029 if (!pmu_counter_idx_valid(vcpu, idx)) 1030 return false; 1031 1032 if (p->is_write) { 1033 if (pmu_access_el0_disabled(vcpu)) 1034 return false; 1035 1036 kvm_pmu_set_counter_value(vcpu, idx, p->regval); 1037 } else { 1038 p->regval = kvm_pmu_get_counter_value(vcpu, idx); 1039 } 1040 1041 return true; 1042 } 1043 1044 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1045 const struct sys_reg_desc *r) 1046 { 1047 u64 idx, reg; 1048 1049 if (pmu_access_el0_disabled(vcpu)) 1050 return false; 1051 1052 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) { 1053 /* PMXEVTYPER_EL0 */ 1054 idx = SYS_FIELD_GET(PMSELR_EL0, SEL, __vcpu_sys_reg(vcpu, PMSELR_EL0)); 1055 reg = PMEVTYPER0_EL0 + idx; 1056 } else if (r->CRn == 14 && (r->CRm & 12) == 12) { 1057 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 1058 if (idx == ARMV8_PMU_CYCLE_IDX) 1059 reg = PMCCFILTR_EL0; 1060 else 1061 /* PMEVTYPERn_EL0 */ 1062 reg = PMEVTYPER0_EL0 + idx; 1063 } else { 1064 BUG(); 1065 } 1066 1067 if (!pmu_counter_idx_valid(vcpu, idx)) 1068 return false; 1069 1070 if (p->is_write) { 1071 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx); 1072 kvm_vcpu_pmu_restore_guest(vcpu); 1073 } else { 1074 p->regval = __vcpu_sys_reg(vcpu, reg); 1075 } 1076 1077 return true; 1078 } 1079 1080 static int set_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 val) 1081 { 1082 u64 mask = kvm_pmu_accessible_counter_mask(vcpu); 1083 1084 __vcpu_assign_sys_reg(vcpu, r->reg, val & mask); 1085 kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu); 1086 1087 return 0; 1088 } 1089 1090 static int get_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 *val) 1091 { 1092 u64 mask = kvm_pmu_accessible_counter_mask(vcpu); 1093 1094 *val = __vcpu_sys_reg(vcpu, r->reg) & mask; 1095 return 0; 1096 } 1097 1098 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1099 const struct sys_reg_desc *r) 1100 { 1101 u64 val, mask; 1102 1103 if (pmu_access_el0_disabled(vcpu)) 1104 return false; 1105 1106 mask = kvm_pmu_accessible_counter_mask(vcpu); 1107 if (p->is_write) { 1108 val = p->regval & mask; 1109 if (r->Op2 & 0x1) 1110 /* accessing PMCNTENSET_EL0 */ 1111 __vcpu_rmw_sys_reg(vcpu, PMCNTENSET_EL0, |=, val); 1112 else 1113 /* accessing PMCNTENCLR_EL0 */ 1114 __vcpu_rmw_sys_reg(vcpu, PMCNTENSET_EL0, &=, ~val); 1115 1116 kvm_pmu_reprogram_counter_mask(vcpu, val); 1117 } else { 1118 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0); 1119 } 1120 1121 return true; 1122 } 1123 1124 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1125 const struct sys_reg_desc *r) 1126 { 1127 u64 mask = kvm_pmu_accessible_counter_mask(vcpu); 1128 1129 if (check_pmu_access_disabled(vcpu, 0)) 1130 return false; 1131 1132 if (p->is_write) { 1133 u64 val = p->regval & mask; 1134 1135 if (r->Op2 & 0x1) 1136 /* accessing PMINTENSET_EL1 */ 1137 __vcpu_rmw_sys_reg(vcpu, PMINTENSET_EL1, |=, val); 1138 else 1139 /* accessing PMINTENCLR_EL1 */ 1140 __vcpu_rmw_sys_reg(vcpu, PMINTENSET_EL1, &=, ~val); 1141 } else { 1142 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1); 1143 } 1144 1145 return true; 1146 } 1147 1148 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1149 const struct sys_reg_desc *r) 1150 { 1151 u64 mask = kvm_pmu_accessible_counter_mask(vcpu); 1152 1153 if (pmu_access_el0_disabled(vcpu)) 1154 return false; 1155 1156 if (p->is_write) { 1157 if (r->CRm & 0x2) 1158 /* accessing PMOVSSET_EL0 */ 1159 __vcpu_rmw_sys_reg(vcpu, PMOVSSET_EL0, |=, (p->regval & mask)); 1160 else 1161 /* accessing PMOVSCLR_EL0 */ 1162 __vcpu_rmw_sys_reg(vcpu, PMOVSSET_EL0, &=, ~(p->regval & mask)); 1163 } else { 1164 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0); 1165 } 1166 1167 return true; 1168 } 1169 1170 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1171 const struct sys_reg_desc *r) 1172 { 1173 u64 mask; 1174 1175 if (!p->is_write) 1176 return read_from_write_only(vcpu, p, r); 1177 1178 if (pmu_write_swinc_el0_disabled(vcpu)) 1179 return false; 1180 1181 mask = kvm_pmu_accessible_counter_mask(vcpu); 1182 kvm_pmu_software_increment(vcpu, p->regval & mask); 1183 return true; 1184 } 1185 1186 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1187 const struct sys_reg_desc *r) 1188 { 1189 if (p->is_write) { 1190 if (!vcpu_mode_priv(vcpu)) 1191 return undef_access(vcpu, p, r); 1192 1193 __vcpu_assign_sys_reg(vcpu, PMUSERENR_EL0, 1194 (p->regval & ARMV8_PMU_USERENR_MASK)); 1195 } else { 1196 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0) 1197 & ARMV8_PMU_USERENR_MASK; 1198 } 1199 1200 return true; 1201 } 1202 1203 static int get_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 1204 u64 *val) 1205 { 1206 *val = kvm_vcpu_read_pmcr(vcpu); 1207 return 0; 1208 } 1209 1210 static int set_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 1211 u64 val) 1212 { 1213 u8 new_n = FIELD_GET(ARMV8_PMU_PMCR_N, val); 1214 struct kvm *kvm = vcpu->kvm; 1215 1216 mutex_lock(&kvm->arch.config_lock); 1217 1218 /* 1219 * The vCPU can't have more counters than the PMU hardware 1220 * implements. Ignore this error to maintain compatibility 1221 * with the existing KVM behavior. 1222 */ 1223 if (!kvm_vm_has_ran_once(kvm) && 1224 !vcpu_has_nv(vcpu) && 1225 new_n <= kvm_arm_pmu_get_max_counters(kvm)) 1226 kvm->arch.nr_pmu_counters = new_n; 1227 1228 mutex_unlock(&kvm->arch.config_lock); 1229 1230 /* 1231 * Ignore writes to RES0 bits, read only bits that are cleared on 1232 * vCPU reset, and writable bits that KVM doesn't support yet. 1233 * (i.e. only PMCR.N and bits [7:0] are mutable from userspace) 1234 * The LP bit is RES0 when FEAT_PMUv3p5 is not supported on the vCPU. 1235 * But, we leave the bit as it is here, as the vCPU's PMUver might 1236 * be changed later (NOTE: the bit will be cleared on first vCPU run 1237 * if necessary). 1238 */ 1239 val &= ARMV8_PMU_PMCR_MASK; 1240 1241 /* The LC bit is RES1 when AArch32 is not supported */ 1242 if (!kvm_supports_32bit_el0()) 1243 val |= ARMV8_PMU_PMCR_LC; 1244 1245 __vcpu_assign_sys_reg(vcpu, r->reg, val); 1246 kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu); 1247 1248 return 0; 1249 } 1250 1251 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */ 1252 #define DBG_BCR_BVR_WCR_WVR_EL1(n) \ 1253 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \ 1254 trap_dbg_wb_reg, reset_dbg_wb_reg, 0, 0, \ 1255 get_dbg_wb_reg, set_dbg_wb_reg }, \ 1256 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \ 1257 trap_dbg_wb_reg, reset_dbg_wb_reg, 0, 0, \ 1258 get_dbg_wb_reg, set_dbg_wb_reg }, \ 1259 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \ 1260 trap_dbg_wb_reg, reset_dbg_wb_reg, 0, 0, \ 1261 get_dbg_wb_reg, set_dbg_wb_reg }, \ 1262 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \ 1263 trap_dbg_wb_reg, reset_dbg_wb_reg, 0, 0, \ 1264 get_dbg_wb_reg, set_dbg_wb_reg } 1265 1266 #define PMU_SYS_REG(name) \ 1267 SYS_DESC(SYS_##name), .reset = reset_pmu_reg, \ 1268 .visibility = pmu_visibility 1269 1270 /* Macro to expand the PMEVCNTRn_EL0 register */ 1271 #define PMU_PMEVCNTR_EL0(n) \ 1272 { PMU_SYS_REG(PMEVCNTRn_EL0(n)), \ 1273 .reset = reset_pmevcntr, .get_user = get_pmu_evcntr, \ 1274 .set_user = set_pmu_evcntr, \ 1275 .access = access_pmu_evcntr, .reg = (PMEVCNTR0_EL0 + n), } 1276 1277 /* Macro to expand the PMEVTYPERn_EL0 register */ 1278 #define PMU_PMEVTYPER_EL0(n) \ 1279 { PMU_SYS_REG(PMEVTYPERn_EL0(n)), \ 1280 .reset = reset_pmevtyper, \ 1281 .access = access_pmu_evtyper, .reg = (PMEVTYPER0_EL0 + n), } 1282 1283 /* Macro to expand the AMU counter and type registers*/ 1284 #define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), undef_access } 1285 #define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), undef_access } 1286 #define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), undef_access } 1287 #define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), undef_access } 1288 1289 static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu, 1290 const struct sys_reg_desc *rd) 1291 { 1292 return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN; 1293 } 1294 1295 /* 1296 * If we land here on a PtrAuth access, that is because we didn't 1297 * fixup the access on exit by allowing the PtrAuth sysregs. The only 1298 * way this happens is when the guest does not have PtrAuth support 1299 * enabled. 1300 */ 1301 #define __PTRAUTH_KEY(k) \ 1302 { SYS_DESC(SYS_## k), undef_access, reset_unknown, k, \ 1303 .visibility = ptrauth_visibility} 1304 1305 #define PTRAUTH_KEY(k) \ 1306 __PTRAUTH_KEY(k ## KEYLO_EL1), \ 1307 __PTRAUTH_KEY(k ## KEYHI_EL1) 1308 1309 static bool access_arch_timer(struct kvm_vcpu *vcpu, 1310 struct sys_reg_params *p, 1311 const struct sys_reg_desc *r) 1312 { 1313 enum kvm_arch_timers tmr; 1314 enum kvm_arch_timer_regs treg; 1315 u64 reg = reg_to_encoding(r); 1316 1317 switch (reg) { 1318 case SYS_CNTP_TVAL_EL0: 1319 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) 1320 tmr = TIMER_HPTIMER; 1321 else 1322 tmr = TIMER_PTIMER; 1323 treg = TIMER_REG_TVAL; 1324 break; 1325 1326 case SYS_CNTV_TVAL_EL0: 1327 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) 1328 tmr = TIMER_HVTIMER; 1329 else 1330 tmr = TIMER_VTIMER; 1331 treg = TIMER_REG_TVAL; 1332 break; 1333 1334 case SYS_AARCH32_CNTP_TVAL: 1335 case SYS_CNTP_TVAL_EL02: 1336 tmr = TIMER_PTIMER; 1337 treg = TIMER_REG_TVAL; 1338 break; 1339 1340 case SYS_CNTV_TVAL_EL02: 1341 tmr = TIMER_VTIMER; 1342 treg = TIMER_REG_TVAL; 1343 break; 1344 1345 case SYS_CNTHP_TVAL_EL2: 1346 tmr = TIMER_HPTIMER; 1347 treg = TIMER_REG_TVAL; 1348 break; 1349 1350 case SYS_CNTHV_TVAL_EL2: 1351 tmr = TIMER_HVTIMER; 1352 treg = TIMER_REG_TVAL; 1353 break; 1354 1355 case SYS_CNTP_CTL_EL0: 1356 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) 1357 tmr = TIMER_HPTIMER; 1358 else 1359 tmr = TIMER_PTIMER; 1360 treg = TIMER_REG_CTL; 1361 break; 1362 1363 case SYS_CNTV_CTL_EL0: 1364 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) 1365 tmr = TIMER_HVTIMER; 1366 else 1367 tmr = TIMER_VTIMER; 1368 treg = TIMER_REG_CTL; 1369 break; 1370 1371 case SYS_AARCH32_CNTP_CTL: 1372 case SYS_CNTP_CTL_EL02: 1373 tmr = TIMER_PTIMER; 1374 treg = TIMER_REG_CTL; 1375 break; 1376 1377 case SYS_CNTV_CTL_EL02: 1378 tmr = TIMER_VTIMER; 1379 treg = TIMER_REG_CTL; 1380 break; 1381 1382 case SYS_CNTHP_CTL_EL2: 1383 tmr = TIMER_HPTIMER; 1384 treg = TIMER_REG_CTL; 1385 break; 1386 1387 case SYS_CNTHV_CTL_EL2: 1388 tmr = TIMER_HVTIMER; 1389 treg = TIMER_REG_CTL; 1390 break; 1391 1392 case SYS_CNTP_CVAL_EL0: 1393 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) 1394 tmr = TIMER_HPTIMER; 1395 else 1396 tmr = TIMER_PTIMER; 1397 treg = TIMER_REG_CVAL; 1398 break; 1399 1400 case SYS_CNTV_CVAL_EL0: 1401 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) 1402 tmr = TIMER_HVTIMER; 1403 else 1404 tmr = TIMER_VTIMER; 1405 treg = TIMER_REG_CVAL; 1406 break; 1407 1408 case SYS_AARCH32_CNTP_CVAL: 1409 case SYS_CNTP_CVAL_EL02: 1410 tmr = TIMER_PTIMER; 1411 treg = TIMER_REG_CVAL; 1412 break; 1413 1414 case SYS_CNTV_CVAL_EL02: 1415 tmr = TIMER_VTIMER; 1416 treg = TIMER_REG_CVAL; 1417 break; 1418 1419 case SYS_CNTHP_CVAL_EL2: 1420 tmr = TIMER_HPTIMER; 1421 treg = TIMER_REG_CVAL; 1422 break; 1423 1424 case SYS_CNTHV_CVAL_EL2: 1425 tmr = TIMER_HVTIMER; 1426 treg = TIMER_REG_CVAL; 1427 break; 1428 1429 case SYS_CNTPCT_EL0: 1430 case SYS_CNTPCTSS_EL0: 1431 if (is_hyp_ctxt(vcpu)) 1432 tmr = TIMER_HPTIMER; 1433 else 1434 tmr = TIMER_PTIMER; 1435 treg = TIMER_REG_CNT; 1436 break; 1437 1438 case SYS_AARCH32_CNTPCT: 1439 case SYS_AARCH32_CNTPCTSS: 1440 tmr = TIMER_PTIMER; 1441 treg = TIMER_REG_CNT; 1442 break; 1443 1444 case SYS_CNTVCT_EL0: 1445 case SYS_CNTVCTSS_EL0: 1446 if (is_hyp_ctxt(vcpu)) 1447 tmr = TIMER_HVTIMER; 1448 else 1449 tmr = TIMER_VTIMER; 1450 treg = TIMER_REG_CNT; 1451 break; 1452 1453 case SYS_AARCH32_CNTVCT: 1454 case SYS_AARCH32_CNTVCTSS: 1455 tmr = TIMER_VTIMER; 1456 treg = TIMER_REG_CNT; 1457 break; 1458 1459 default: 1460 print_sys_reg_msg(p, "%s", "Unhandled trapped timer register"); 1461 return undef_access(vcpu, p, r); 1462 } 1463 1464 if (p->is_write) 1465 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval); 1466 else 1467 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg); 1468 1469 return true; 1470 } 1471 1472 static bool access_hv_timer(struct kvm_vcpu *vcpu, 1473 struct sys_reg_params *p, 1474 const struct sys_reg_desc *r) 1475 { 1476 if (!vcpu_el2_e2h_is_set(vcpu)) 1477 return undef_access(vcpu, p, r); 1478 1479 return access_arch_timer(vcpu, p, r); 1480 } 1481 1482 static s64 kvm_arm64_ftr_safe_value(u32 id, const struct arm64_ftr_bits *ftrp, 1483 s64 new, s64 cur) 1484 { 1485 struct arm64_ftr_bits kvm_ftr = *ftrp; 1486 1487 /* Some features have different safe value type in KVM than host features */ 1488 switch (id) { 1489 case SYS_ID_AA64DFR0_EL1: 1490 switch (kvm_ftr.shift) { 1491 case ID_AA64DFR0_EL1_PMUVer_SHIFT: 1492 kvm_ftr.type = FTR_LOWER_SAFE; 1493 break; 1494 case ID_AA64DFR0_EL1_DebugVer_SHIFT: 1495 kvm_ftr.type = FTR_LOWER_SAFE; 1496 break; 1497 } 1498 break; 1499 case SYS_ID_DFR0_EL1: 1500 if (kvm_ftr.shift == ID_DFR0_EL1_PerfMon_SHIFT) 1501 kvm_ftr.type = FTR_LOWER_SAFE; 1502 break; 1503 } 1504 1505 return arm64_ftr_safe_value(&kvm_ftr, new, cur); 1506 } 1507 1508 /* 1509 * arm64_check_features() - Check if a feature register value constitutes 1510 * a subset of features indicated by the idreg's KVM sanitised limit. 1511 * 1512 * This function will check if each feature field of @val is the "safe" value 1513 * against idreg's KVM sanitised limit return from reset() callback. 1514 * If a field value in @val is the same as the one in limit, it is always 1515 * considered the safe value regardless For register fields that are not in 1516 * writable, only the value in limit is considered the safe value. 1517 * 1518 * Return: 0 if all the fields are safe. Otherwise, return negative errno. 1519 */ 1520 static int arm64_check_features(struct kvm_vcpu *vcpu, 1521 const struct sys_reg_desc *rd, 1522 u64 val) 1523 { 1524 const struct arm64_ftr_reg *ftr_reg; 1525 const struct arm64_ftr_bits *ftrp = NULL; 1526 u32 id = reg_to_encoding(rd); 1527 u64 writable_mask = rd->val; 1528 u64 limit = rd->reset(vcpu, rd); 1529 u64 mask = 0; 1530 1531 /* 1532 * Hidden and unallocated ID registers may not have a corresponding 1533 * struct arm64_ftr_reg. Of course, if the register is RAZ we know the 1534 * only safe value is 0. 1535 */ 1536 if (sysreg_visible_as_raz(vcpu, rd)) 1537 return val ? -E2BIG : 0; 1538 1539 ftr_reg = get_arm64_ftr_reg(id); 1540 if (!ftr_reg) 1541 return -EINVAL; 1542 1543 ftrp = ftr_reg->ftr_bits; 1544 1545 for (; ftrp && ftrp->width; ftrp++) { 1546 s64 f_val, f_lim, safe_val; 1547 u64 ftr_mask; 1548 1549 ftr_mask = arm64_ftr_mask(ftrp); 1550 if ((ftr_mask & writable_mask) != ftr_mask) 1551 continue; 1552 1553 f_val = arm64_ftr_value(ftrp, val); 1554 f_lim = arm64_ftr_value(ftrp, limit); 1555 mask |= ftr_mask; 1556 1557 if (f_val == f_lim) 1558 safe_val = f_val; 1559 else 1560 safe_val = kvm_arm64_ftr_safe_value(id, ftrp, f_val, f_lim); 1561 1562 if (safe_val != f_val) 1563 return -E2BIG; 1564 } 1565 1566 /* For fields that are not writable, values in limit are the safe values. */ 1567 if ((val & ~mask) != (limit & ~mask)) 1568 return -E2BIG; 1569 1570 return 0; 1571 } 1572 1573 static u8 pmuver_to_perfmon(u8 pmuver) 1574 { 1575 switch (pmuver) { 1576 case ID_AA64DFR0_EL1_PMUVer_IMP: 1577 return ID_DFR0_EL1_PerfMon_PMUv3; 1578 case ID_AA64DFR0_EL1_PMUVer_IMP_DEF: 1579 return ID_DFR0_EL1_PerfMon_IMPDEF; 1580 default: 1581 /* Anything ARMv8.1+ and NI have the same value. For now. */ 1582 return pmuver; 1583 } 1584 } 1585 1586 static u64 sanitise_id_aa64pfr0_el1(const struct kvm_vcpu *vcpu, u64 val); 1587 static u64 sanitise_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, u64 val); 1588 1589 /* Read a sanitised cpufeature ID register by sys_reg_desc */ 1590 static u64 __kvm_read_sanitised_id_reg(const struct kvm_vcpu *vcpu, 1591 const struct sys_reg_desc *r) 1592 { 1593 u32 id = reg_to_encoding(r); 1594 u64 val; 1595 1596 if (sysreg_visible_as_raz(vcpu, r)) 1597 return 0; 1598 1599 val = read_sanitised_ftr_reg(id); 1600 1601 switch (id) { 1602 case SYS_ID_AA64DFR0_EL1: 1603 val = sanitise_id_aa64dfr0_el1(vcpu, val); 1604 break; 1605 case SYS_ID_AA64PFR0_EL1: 1606 val = sanitise_id_aa64pfr0_el1(vcpu, val); 1607 break; 1608 case SYS_ID_AA64PFR1_EL1: 1609 if (!kvm_has_mte(vcpu->kvm)) { 1610 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE); 1611 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE_frac); 1612 } 1613 1614 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_SME); 1615 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_RNDR_trap); 1616 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_NMI); 1617 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_GCS); 1618 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_THE); 1619 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTEX); 1620 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_PFAR); 1621 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MPAM_frac); 1622 break; 1623 case SYS_ID_AA64PFR2_EL1: 1624 val &= ID_AA64PFR2_EL1_FPMR | 1625 (kvm_has_mte(vcpu->kvm) ? 1626 ID_AA64PFR2_EL1_MTEFAR | ID_AA64PFR2_EL1_MTESTOREONLY : 1627 0); 1628 break; 1629 case SYS_ID_AA64ISAR1_EL1: 1630 if (!vcpu_has_ptrauth(vcpu)) 1631 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) | 1632 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) | 1633 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) | 1634 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI)); 1635 break; 1636 case SYS_ID_AA64ISAR2_EL1: 1637 if (!vcpu_has_ptrauth(vcpu)) 1638 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) | 1639 ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3)); 1640 if (!cpus_have_final_cap(ARM64_HAS_WFXT) || 1641 has_broken_cntvoff()) 1642 val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT); 1643 break; 1644 case SYS_ID_AA64ISAR3_EL1: 1645 val &= ID_AA64ISAR3_EL1_FPRCVT | ID_AA64ISAR3_EL1_FAMINMAX; 1646 break; 1647 case SYS_ID_AA64MMFR2_EL1: 1648 val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK; 1649 val &= ~ID_AA64MMFR2_EL1_NV; 1650 break; 1651 case SYS_ID_AA64MMFR3_EL1: 1652 val &= ID_AA64MMFR3_EL1_TCRX | 1653 ID_AA64MMFR3_EL1_SCTLRX | 1654 ID_AA64MMFR3_EL1_S1POE | 1655 ID_AA64MMFR3_EL1_S1PIE; 1656 break; 1657 case SYS_ID_MMFR4_EL1: 1658 val &= ~ARM64_FEATURE_MASK(ID_MMFR4_EL1_CCIDX); 1659 break; 1660 } 1661 1662 if (vcpu_has_nv(vcpu)) 1663 val = limit_nv_id_reg(vcpu->kvm, id, val); 1664 1665 return val; 1666 } 1667 1668 static u64 kvm_read_sanitised_id_reg(struct kvm_vcpu *vcpu, 1669 const struct sys_reg_desc *r) 1670 { 1671 return __kvm_read_sanitised_id_reg(vcpu, r); 1672 } 1673 1674 static u64 read_id_reg(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 1675 { 1676 return kvm_read_vm_id_reg(vcpu->kvm, reg_to_encoding(r)); 1677 } 1678 1679 static bool is_feature_id_reg(u32 encoding) 1680 { 1681 return (sys_reg_Op0(encoding) == 3 && 1682 (sys_reg_Op1(encoding) < 2 || sys_reg_Op1(encoding) == 3) && 1683 sys_reg_CRn(encoding) == 0 && 1684 sys_reg_CRm(encoding) <= 7); 1685 } 1686 1687 /* 1688 * Return true if the register's (Op0, Op1, CRn, CRm, Op2) is 1689 * (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8, which is the range of ID 1690 * registers KVM maintains on a per-VM basis. 1691 * 1692 * Additionally, the implementation ID registers and CTR_EL0 are handled as 1693 * per-VM registers. 1694 */ 1695 static inline bool is_vm_ftr_id_reg(u32 id) 1696 { 1697 switch (id) { 1698 case SYS_CTR_EL0: 1699 case SYS_MIDR_EL1: 1700 case SYS_REVIDR_EL1: 1701 case SYS_AIDR_EL1: 1702 return true; 1703 default: 1704 return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 && 1705 sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 && 1706 sys_reg_CRm(id) < 8); 1707 1708 } 1709 } 1710 1711 static inline bool is_vcpu_ftr_id_reg(u32 id) 1712 { 1713 return is_feature_id_reg(id) && !is_vm_ftr_id_reg(id); 1714 } 1715 1716 static inline bool is_aa32_id_reg(u32 id) 1717 { 1718 return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 && 1719 sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 && 1720 sys_reg_CRm(id) <= 3); 1721 } 1722 1723 static unsigned int id_visibility(const struct kvm_vcpu *vcpu, 1724 const struct sys_reg_desc *r) 1725 { 1726 u32 id = reg_to_encoding(r); 1727 1728 switch (id) { 1729 case SYS_ID_AA64ZFR0_EL1: 1730 if (!vcpu_has_sve(vcpu)) 1731 return REG_RAZ; 1732 break; 1733 } 1734 1735 return 0; 1736 } 1737 1738 static unsigned int aa32_id_visibility(const struct kvm_vcpu *vcpu, 1739 const struct sys_reg_desc *r) 1740 { 1741 /* 1742 * AArch32 ID registers are UNKNOWN if AArch32 isn't implemented at any 1743 * EL. Promote to RAZ/WI in order to guarantee consistency between 1744 * systems. 1745 */ 1746 if (!kvm_supports_32bit_el0()) 1747 return REG_RAZ | REG_USER_WI; 1748 1749 return id_visibility(vcpu, r); 1750 } 1751 1752 static unsigned int raz_visibility(const struct kvm_vcpu *vcpu, 1753 const struct sys_reg_desc *r) 1754 { 1755 return REG_RAZ; 1756 } 1757 1758 /* cpufeature ID register access trap handlers */ 1759 1760 static bool access_id_reg(struct kvm_vcpu *vcpu, 1761 struct sys_reg_params *p, 1762 const struct sys_reg_desc *r) 1763 { 1764 if (p->is_write) 1765 return write_to_read_only(vcpu, p, r); 1766 1767 p->regval = read_id_reg(vcpu, r); 1768 1769 return true; 1770 } 1771 1772 /* Visibility overrides for SVE-specific control registers */ 1773 static unsigned int sve_visibility(const struct kvm_vcpu *vcpu, 1774 const struct sys_reg_desc *rd) 1775 { 1776 if (vcpu_has_sve(vcpu)) 1777 return 0; 1778 1779 return REG_HIDDEN; 1780 } 1781 1782 static unsigned int sme_visibility(const struct kvm_vcpu *vcpu, 1783 const struct sys_reg_desc *rd) 1784 { 1785 if (kvm_has_feat(vcpu->kvm, ID_AA64PFR1_EL1, SME, IMP)) 1786 return 0; 1787 1788 return REG_HIDDEN; 1789 } 1790 1791 static unsigned int fp8_visibility(const struct kvm_vcpu *vcpu, 1792 const struct sys_reg_desc *rd) 1793 { 1794 if (kvm_has_fpmr(vcpu->kvm)) 1795 return 0; 1796 1797 return REG_HIDDEN; 1798 } 1799 1800 static u64 sanitise_id_aa64pfr0_el1(const struct kvm_vcpu *vcpu, u64 val) 1801 { 1802 if (!vcpu_has_sve(vcpu)) 1803 val &= ~ID_AA64PFR0_EL1_SVE_MASK; 1804 1805 /* 1806 * The default is to expose CSV2 == 1 if the HW isn't affected. 1807 * Although this is a per-CPU feature, we make it global because 1808 * asymmetric systems are just a nuisance. 1809 * 1810 * Userspace can override this as long as it doesn't promise 1811 * the impossible. 1812 */ 1813 if (arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED) { 1814 val &= ~ID_AA64PFR0_EL1_CSV2_MASK; 1815 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV2, IMP); 1816 } 1817 if (arm64_get_meltdown_state() == SPECTRE_UNAFFECTED) { 1818 val &= ~ID_AA64PFR0_EL1_CSV3_MASK; 1819 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV3, IMP); 1820 } 1821 1822 if (vgic_is_v3(vcpu->kvm)) { 1823 val &= ~ID_AA64PFR0_EL1_GIC_MASK; 1824 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, GIC, IMP); 1825 } 1826 1827 val &= ~ID_AA64PFR0_EL1_AMU_MASK; 1828 1829 /* 1830 * MPAM is disabled by default as KVM also needs a set of PARTID to 1831 * program the MPAMVPMx_EL2 PARTID remapping registers with. But some 1832 * older kernels let the guest see the ID bit. 1833 */ 1834 val &= ~ID_AA64PFR0_EL1_MPAM_MASK; 1835 1836 return val; 1837 } 1838 1839 static u64 sanitise_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, u64 val) 1840 { 1841 val = ID_REG_LIMIT_FIELD_ENUM(val, ID_AA64DFR0_EL1, DebugVer, V8P8); 1842 1843 /* 1844 * Only initialize the PMU version if the vCPU was configured with one. 1845 */ 1846 val &= ~ID_AA64DFR0_EL1_PMUVer_MASK; 1847 if (kvm_vcpu_has_pmu(vcpu)) 1848 val |= SYS_FIELD_PREP(ID_AA64DFR0_EL1, PMUVer, 1849 kvm_arm_pmu_get_pmuver_limit()); 1850 1851 /* Hide SPE from guests */ 1852 val &= ~ID_AA64DFR0_EL1_PMSVer_MASK; 1853 1854 /* Hide BRBE from guests */ 1855 val &= ~ID_AA64DFR0_EL1_BRBE_MASK; 1856 1857 return val; 1858 } 1859 1860 static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, 1861 const struct sys_reg_desc *rd, 1862 u64 val) 1863 { 1864 u8 debugver = SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, val); 1865 u8 pmuver = SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, val); 1866 1867 /* 1868 * Prior to commit 3d0dba5764b9 ("KVM: arm64: PMU: Move the 1869 * ID_AA64DFR0_EL1.PMUver limit to VM creation"), KVM erroneously 1870 * exposed an IMP_DEF PMU to userspace and the guest on systems w/ 1871 * non-architectural PMUs. Of course, PMUv3 is the only game in town for 1872 * PMU virtualization, so the IMP_DEF value was rather user-hostile. 1873 * 1874 * At minimum, we're on the hook to allow values that were given to 1875 * userspace by KVM. Cover our tracks here and replace the IMP_DEF value 1876 * with a more sensible NI. The value of an ID register changing under 1877 * the nose of the guest is unfortunate, but is certainly no more 1878 * surprising than an ill-guided PMU driver poking at impdef system 1879 * registers that end in an UNDEF... 1880 */ 1881 if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF) 1882 val &= ~ID_AA64DFR0_EL1_PMUVer_MASK; 1883 1884 /* 1885 * ID_AA64DFR0_EL1.DebugVer is one of those awkward fields with a 1886 * nonzero minimum safe value. 1887 */ 1888 if (debugver < ID_AA64DFR0_EL1_DebugVer_IMP) 1889 return -EINVAL; 1890 1891 return set_id_reg(vcpu, rd, val); 1892 } 1893 1894 static u64 read_sanitised_id_dfr0_el1(struct kvm_vcpu *vcpu, 1895 const struct sys_reg_desc *rd) 1896 { 1897 u8 perfmon; 1898 u64 val = read_sanitised_ftr_reg(SYS_ID_DFR0_EL1); 1899 1900 val &= ~ID_DFR0_EL1_PerfMon_MASK; 1901 if (kvm_vcpu_has_pmu(vcpu)) { 1902 perfmon = pmuver_to_perfmon(kvm_arm_pmu_get_pmuver_limit()); 1903 val |= SYS_FIELD_PREP(ID_DFR0_EL1, PerfMon, perfmon); 1904 } 1905 1906 val = ID_REG_LIMIT_FIELD_ENUM(val, ID_DFR0_EL1, CopDbg, Debugv8p8); 1907 1908 return val; 1909 } 1910 1911 static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, 1912 const struct sys_reg_desc *rd, 1913 u64 val) 1914 { 1915 u8 perfmon = SYS_FIELD_GET(ID_DFR0_EL1, PerfMon, val); 1916 u8 copdbg = SYS_FIELD_GET(ID_DFR0_EL1, CopDbg, val); 1917 1918 if (perfmon == ID_DFR0_EL1_PerfMon_IMPDEF) { 1919 val &= ~ID_DFR0_EL1_PerfMon_MASK; 1920 perfmon = 0; 1921 } 1922 1923 /* 1924 * Allow DFR0_EL1.PerfMon to be set from userspace as long as 1925 * it doesn't promise more than what the HW gives us on the 1926 * AArch64 side (as everything is emulated with that), and 1927 * that this is a PMUv3. 1928 */ 1929 if (perfmon != 0 && perfmon < ID_DFR0_EL1_PerfMon_PMUv3) 1930 return -EINVAL; 1931 1932 if (copdbg < ID_DFR0_EL1_CopDbg_Armv8) 1933 return -EINVAL; 1934 1935 return set_id_reg(vcpu, rd, val); 1936 } 1937 1938 static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, 1939 const struct sys_reg_desc *rd, u64 user_val) 1940 { 1941 u64 hw_val = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1942 u64 mpam_mask = ID_AA64PFR0_EL1_MPAM_MASK; 1943 1944 /* 1945 * Commit 011e5f5bf529f ("arm64/cpufeature: Add remaining feature bits 1946 * in ID_AA64PFR0 register") exposed the MPAM field of AA64PFR0_EL1 to 1947 * guests, but didn't add trap handling. KVM doesn't support MPAM and 1948 * always returns an UNDEF for these registers. The guest must see 0 1949 * for this field. 1950 * 1951 * But KVM must also accept values from user-space that were provided 1952 * by KVM. On CPUs that support MPAM, permit user-space to write 1953 * the sanitizied value to ID_AA64PFR0_EL1.MPAM, but ignore this field. 1954 */ 1955 if ((hw_val & mpam_mask) == (user_val & mpam_mask)) 1956 user_val &= ~ID_AA64PFR0_EL1_MPAM_MASK; 1957 1958 /* Fail the guest's request to disable the AA64 ISA at EL{0,1,2} */ 1959 if (!FIELD_GET(ID_AA64PFR0_EL1_EL0, user_val) || 1960 !FIELD_GET(ID_AA64PFR0_EL1_EL1, user_val) || 1961 (vcpu_has_nv(vcpu) && !FIELD_GET(ID_AA64PFR0_EL1_EL2, user_val))) 1962 return -EINVAL; 1963 1964 /* 1965 * If we are running on a GICv5 host and support FEAT_GCIE_LEGACY, then 1966 * we support GICv3. Fail attempts to do anything but set that to IMP. 1967 */ 1968 if (vgic_is_v3_compat(vcpu->kvm) && 1969 FIELD_GET(ID_AA64PFR0_EL1_GIC_MASK, user_val) != ID_AA64PFR0_EL1_GIC_IMP) 1970 return -EINVAL; 1971 1972 return set_id_reg(vcpu, rd, user_val); 1973 } 1974 1975 static int set_id_aa64pfr1_el1(struct kvm_vcpu *vcpu, 1976 const struct sys_reg_desc *rd, u64 user_val) 1977 { 1978 u64 hw_val = read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1); 1979 u64 mpam_mask = ID_AA64PFR1_EL1_MPAM_frac_MASK; 1980 u8 mte = SYS_FIELD_GET(ID_AA64PFR1_EL1, MTE, hw_val); 1981 u8 user_mte_frac = SYS_FIELD_GET(ID_AA64PFR1_EL1, MTE_frac, user_val); 1982 u8 hw_mte_frac = SYS_FIELD_GET(ID_AA64PFR1_EL1, MTE_frac, hw_val); 1983 1984 /* See set_id_aa64pfr0_el1 for comment about MPAM */ 1985 if ((hw_val & mpam_mask) == (user_val & mpam_mask)) 1986 user_val &= ~ID_AA64PFR1_EL1_MPAM_frac_MASK; 1987 1988 /* 1989 * Previously MTE_frac was hidden from guest. However, if the 1990 * hardware supports MTE2 but not MTE_ASYM_FAULT then a value 1991 * of 0 for this field indicates that the hardware supports 1992 * MTE_ASYNC. Whereas, 0xf indicates MTE_ASYNC is not supported. 1993 * 1994 * As KVM must accept values from KVM provided by user-space, 1995 * when ID_AA64PFR1_EL1.MTE is 2 allow user-space to set 1996 * ID_AA64PFR1_EL1.MTE_frac to 0. However, ignore it to avoid 1997 * incorrectly claiming hardware support for MTE_ASYNC in the 1998 * guest. 1999 */ 2000 2001 if (mte == ID_AA64PFR1_EL1_MTE_MTE2 && 2002 hw_mte_frac == ID_AA64PFR1_EL1_MTE_frac_NI && 2003 user_mte_frac == ID_AA64PFR1_EL1_MTE_frac_ASYNC) { 2004 user_val &= ~ID_AA64PFR1_EL1_MTE_frac_MASK; 2005 user_val |= hw_val & ID_AA64PFR1_EL1_MTE_frac_MASK; 2006 } 2007 2008 return set_id_reg(vcpu, rd, user_val); 2009 } 2010 2011 static int set_id_aa64mmfr0_el1(struct kvm_vcpu *vcpu, 2012 const struct sys_reg_desc *rd, u64 user_val) 2013 { 2014 u64 sanitized_val = kvm_read_sanitised_id_reg(vcpu, rd); 2015 u64 tgran2_mask = ID_AA64MMFR0_EL1_TGRAN4_2_MASK | 2016 ID_AA64MMFR0_EL1_TGRAN16_2_MASK | 2017 ID_AA64MMFR0_EL1_TGRAN64_2_MASK; 2018 2019 if (vcpu_has_nv(vcpu) && 2020 ((sanitized_val & tgran2_mask) != (user_val & tgran2_mask))) 2021 return -EINVAL; 2022 2023 return set_id_reg(vcpu, rd, user_val); 2024 } 2025 2026 static int set_id_aa64mmfr2_el1(struct kvm_vcpu *vcpu, 2027 const struct sys_reg_desc *rd, u64 user_val) 2028 { 2029 u64 hw_val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR2_EL1); 2030 u64 nv_mask = ID_AA64MMFR2_EL1_NV_MASK; 2031 2032 /* 2033 * We made the mistake to expose the now deprecated NV field, 2034 * so allow userspace to write it, but silently ignore it. 2035 */ 2036 if ((hw_val & nv_mask) == (user_val & nv_mask)) 2037 user_val &= ~nv_mask; 2038 2039 return set_id_reg(vcpu, rd, user_val); 2040 } 2041 2042 static int set_ctr_el0(struct kvm_vcpu *vcpu, 2043 const struct sys_reg_desc *rd, u64 user_val) 2044 { 2045 u8 user_L1Ip = SYS_FIELD_GET(CTR_EL0, L1Ip, user_val); 2046 2047 /* 2048 * Both AIVIVT (0b01) and VPIPT (0b00) are documented as reserved. 2049 * Hence only allow to set VIPT(0b10) or PIPT(0b11) for L1Ip based 2050 * on what hardware reports. 2051 * 2052 * Using a VIPT software model on PIPT will lead to over invalidation, 2053 * but still correct. Hence, we can allow downgrading PIPT to VIPT, 2054 * but not the other way around. This is handled via arm64_ftr_safe_value() 2055 * as CTR_EL0 ftr_bits has L1Ip field with type FTR_EXACT and safe value 2056 * set as VIPT. 2057 */ 2058 switch (user_L1Ip) { 2059 case CTR_EL0_L1Ip_RESERVED_VPIPT: 2060 case CTR_EL0_L1Ip_RESERVED_AIVIVT: 2061 return -EINVAL; 2062 case CTR_EL0_L1Ip_VIPT: 2063 case CTR_EL0_L1Ip_PIPT: 2064 return set_id_reg(vcpu, rd, user_val); 2065 default: 2066 return -ENOENT; 2067 } 2068 } 2069 2070 /* 2071 * cpufeature ID register user accessors 2072 * 2073 * For now, these registers are immutable for userspace, so no values 2074 * are stored, and for set_id_reg() we don't allow the effective value 2075 * to be changed. 2076 */ 2077 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 2078 u64 *val) 2079 { 2080 /* 2081 * Avoid locking if the VM has already started, as the ID registers are 2082 * guaranteed to be invariant at that point. 2083 */ 2084 if (kvm_vm_has_ran_once(vcpu->kvm)) { 2085 *val = read_id_reg(vcpu, rd); 2086 return 0; 2087 } 2088 2089 mutex_lock(&vcpu->kvm->arch.config_lock); 2090 *val = read_id_reg(vcpu, rd); 2091 mutex_unlock(&vcpu->kvm->arch.config_lock); 2092 2093 return 0; 2094 } 2095 2096 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 2097 u64 val) 2098 { 2099 u32 id = reg_to_encoding(rd); 2100 int ret; 2101 2102 mutex_lock(&vcpu->kvm->arch.config_lock); 2103 2104 /* 2105 * Once the VM has started the ID registers are immutable. Reject any 2106 * write that does not match the final register value. 2107 */ 2108 if (kvm_vm_has_ran_once(vcpu->kvm)) { 2109 if (val != read_id_reg(vcpu, rd)) 2110 ret = -EBUSY; 2111 else 2112 ret = 0; 2113 2114 mutex_unlock(&vcpu->kvm->arch.config_lock); 2115 return ret; 2116 } 2117 2118 ret = arm64_check_features(vcpu, rd, val); 2119 if (!ret) 2120 kvm_set_vm_id_reg(vcpu->kvm, id, val); 2121 2122 mutex_unlock(&vcpu->kvm->arch.config_lock); 2123 2124 /* 2125 * arm64_check_features() returns -E2BIG to indicate the register's 2126 * feature set is a superset of the maximally-allowed register value. 2127 * While it would be nice to precisely describe this to userspace, the 2128 * existing UAPI for KVM_SET_ONE_REG has it that invalid register 2129 * writes return -EINVAL. 2130 */ 2131 if (ret == -E2BIG) 2132 ret = -EINVAL; 2133 return ret; 2134 } 2135 2136 void kvm_set_vm_id_reg(struct kvm *kvm, u32 reg, u64 val) 2137 { 2138 u64 *p = __vm_id_reg(&kvm->arch, reg); 2139 2140 lockdep_assert_held(&kvm->arch.config_lock); 2141 2142 if (KVM_BUG_ON(kvm_vm_has_ran_once(kvm) || !p, kvm)) 2143 return; 2144 2145 *p = val; 2146 } 2147 2148 static int get_raz_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 2149 u64 *val) 2150 { 2151 *val = 0; 2152 return 0; 2153 } 2154 2155 static int set_wi_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 2156 u64 val) 2157 { 2158 return 0; 2159 } 2160 2161 static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2162 const struct sys_reg_desc *r) 2163 { 2164 if (p->is_write) 2165 return write_to_read_only(vcpu, p, r); 2166 2167 p->regval = kvm_read_vm_id_reg(vcpu->kvm, SYS_CTR_EL0); 2168 return true; 2169 } 2170 2171 static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2172 const struct sys_reg_desc *r) 2173 { 2174 if (p->is_write) 2175 return write_to_read_only(vcpu, p, r); 2176 2177 p->regval = __vcpu_sys_reg(vcpu, r->reg); 2178 return true; 2179 } 2180 2181 /* 2182 * Fabricate a CLIDR_EL1 value instead of using the real value, which can vary 2183 * by the physical CPU which the vcpu currently resides in. 2184 */ 2185 static u64 reset_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 2186 { 2187 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0); 2188 u64 clidr; 2189 u8 loc; 2190 2191 if ((ctr_el0 & CTR_EL0_IDC)) { 2192 /* 2193 * Data cache clean to the PoU is not required so LoUU and LoUIS 2194 * will not be set and a unified cache, which will be marked as 2195 * LoC, will be added. 2196 * 2197 * If not DIC, let the unified cache L2 so that an instruction 2198 * cache can be added as L1 later. 2199 */ 2200 loc = (ctr_el0 & CTR_EL0_DIC) ? 1 : 2; 2201 clidr = CACHE_TYPE_UNIFIED << CLIDR_CTYPE_SHIFT(loc); 2202 } else { 2203 /* 2204 * Data cache clean to the PoU is required so let L1 have a data 2205 * cache and mark it as LoUU and LoUIS. As L1 has a data cache, 2206 * it can be marked as LoC too. 2207 */ 2208 loc = 1; 2209 clidr = 1 << CLIDR_LOUU_SHIFT; 2210 clidr |= 1 << CLIDR_LOUIS_SHIFT; 2211 clidr |= CACHE_TYPE_DATA << CLIDR_CTYPE_SHIFT(1); 2212 } 2213 2214 /* 2215 * Instruction cache invalidation to the PoU is required so let L1 have 2216 * an instruction cache. If L1 already has a data cache, it will be 2217 * CACHE_TYPE_SEPARATE. 2218 */ 2219 if (!(ctr_el0 & CTR_EL0_DIC)) 2220 clidr |= CACHE_TYPE_INST << CLIDR_CTYPE_SHIFT(1); 2221 2222 clidr |= loc << CLIDR_LOC_SHIFT; 2223 2224 /* 2225 * Add tag cache unified to data cache. Allocation tags and data are 2226 * unified in a cache line so that it looks valid even if there is only 2227 * one cache line. 2228 */ 2229 if (kvm_has_mte(vcpu->kvm)) 2230 clidr |= 2ULL << CLIDR_TTYPE_SHIFT(loc); 2231 2232 __vcpu_assign_sys_reg(vcpu, r->reg, clidr); 2233 2234 return __vcpu_sys_reg(vcpu, r->reg); 2235 } 2236 2237 static int set_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 2238 u64 val) 2239 { 2240 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0); 2241 u64 idc = !CLIDR_LOC(val) || (!CLIDR_LOUIS(val) && !CLIDR_LOUU(val)); 2242 2243 if ((val & CLIDR_EL1_RES0) || (!(ctr_el0 & CTR_EL0_IDC) && idc)) 2244 return -EINVAL; 2245 2246 __vcpu_assign_sys_reg(vcpu, rd->reg, val); 2247 2248 return 0; 2249 } 2250 2251 static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2252 const struct sys_reg_desc *r) 2253 { 2254 int reg = r->reg; 2255 2256 if (p->is_write) 2257 vcpu_write_sys_reg(vcpu, p->regval, reg); 2258 else 2259 p->regval = vcpu_read_sys_reg(vcpu, reg); 2260 return true; 2261 } 2262 2263 static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2264 const struct sys_reg_desc *r) 2265 { 2266 u32 csselr; 2267 2268 if (p->is_write) 2269 return write_to_read_only(vcpu, p, r); 2270 2271 csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1); 2272 csselr &= CSSELR_EL1_Level | CSSELR_EL1_InD; 2273 if (csselr < CSSELR_MAX) 2274 p->regval = get_ccsidr(vcpu, csselr); 2275 2276 return true; 2277 } 2278 2279 static unsigned int mte_visibility(const struct kvm_vcpu *vcpu, 2280 const struct sys_reg_desc *rd) 2281 { 2282 if (kvm_has_mte(vcpu->kvm)) 2283 return 0; 2284 2285 return REG_HIDDEN; 2286 } 2287 2288 #define MTE_REG(name) { \ 2289 SYS_DESC(SYS_##name), \ 2290 .access = undef_access, \ 2291 .reset = reset_unknown, \ 2292 .reg = name, \ 2293 .visibility = mte_visibility, \ 2294 } 2295 2296 static unsigned int el2_visibility(const struct kvm_vcpu *vcpu, 2297 const struct sys_reg_desc *rd) 2298 { 2299 if (vcpu_has_nv(vcpu)) 2300 return 0; 2301 2302 return REG_HIDDEN; 2303 } 2304 2305 static bool bad_vncr_trap(struct kvm_vcpu *vcpu, 2306 struct sys_reg_params *p, 2307 const struct sys_reg_desc *r) 2308 { 2309 /* 2310 * We really shouldn't be here, and this is likely the result 2311 * of a misconfigured trap, as this register should target the 2312 * VNCR page, and nothing else. 2313 */ 2314 return bad_trap(vcpu, p, r, 2315 "trap of VNCR-backed register"); 2316 } 2317 2318 static bool bad_redir_trap(struct kvm_vcpu *vcpu, 2319 struct sys_reg_params *p, 2320 const struct sys_reg_desc *r) 2321 { 2322 /* 2323 * We really shouldn't be here, and this is likely the result 2324 * of a misconfigured trap, as this register should target the 2325 * corresponding EL1, and nothing else. 2326 */ 2327 return bad_trap(vcpu, p, r, 2328 "trap of EL2 register redirected to EL1"); 2329 } 2330 2331 #define EL2_REG_FILTERED(name, acc, rst, v, filter) { \ 2332 SYS_DESC(SYS_##name), \ 2333 .access = acc, \ 2334 .reset = rst, \ 2335 .reg = name, \ 2336 .visibility = filter, \ 2337 .val = v, \ 2338 } 2339 2340 #define EL2_REG(name, acc, rst, v) \ 2341 EL2_REG_FILTERED(name, acc, rst, v, el2_visibility) 2342 2343 #define EL2_REG_VNCR(name, rst, v) EL2_REG(name, bad_vncr_trap, rst, v) 2344 #define EL2_REG_VNCR_FILT(name, vis) \ 2345 EL2_REG_FILTERED(name, bad_vncr_trap, reset_val, 0, vis) 2346 #define EL2_REG_VNCR_GICv3(name) \ 2347 EL2_REG_VNCR_FILT(name, hidden_visibility) 2348 #define EL2_REG_REDIR(name, rst, v) EL2_REG(name, bad_redir_trap, rst, v) 2349 2350 /* 2351 * Since reset() callback and field val are not used for idregs, they will be 2352 * used for specific purposes for idregs. 2353 * The reset() would return KVM sanitised register value. The value would be the 2354 * same as the host kernel sanitised value if there is no KVM sanitisation. 2355 * The val would be used as a mask indicating writable fields for the idreg. 2356 * Only bits with 1 are writable from userspace. This mask might not be 2357 * necessary in the future whenever all ID registers are enabled as writable 2358 * from userspace. 2359 */ 2360 2361 #define ID_DESC_DEFAULT_CALLBACKS \ 2362 .access = access_id_reg, \ 2363 .get_user = get_id_reg, \ 2364 .set_user = set_id_reg, \ 2365 .visibility = id_visibility, \ 2366 .reset = kvm_read_sanitised_id_reg 2367 2368 #define ID_DESC(name) \ 2369 SYS_DESC(SYS_##name), \ 2370 ID_DESC_DEFAULT_CALLBACKS 2371 2372 /* sys_reg_desc initialiser for known cpufeature ID registers */ 2373 #define ID_SANITISED(name) { \ 2374 ID_DESC(name), \ 2375 .val = 0, \ 2376 } 2377 2378 /* sys_reg_desc initialiser for known cpufeature ID registers */ 2379 #define AA32_ID_SANITISED(name) { \ 2380 ID_DESC(name), \ 2381 .visibility = aa32_id_visibility, \ 2382 .val = 0, \ 2383 } 2384 2385 /* sys_reg_desc initialiser for writable ID registers */ 2386 #define ID_WRITABLE(name, mask) { \ 2387 ID_DESC(name), \ 2388 .val = mask, \ 2389 } 2390 2391 /* sys_reg_desc initialiser for cpufeature ID registers that need filtering */ 2392 #define ID_FILTERED(sysreg, name, mask) { \ 2393 ID_DESC(sysreg), \ 2394 .set_user = set_##name, \ 2395 .val = (mask), \ 2396 } 2397 2398 /* 2399 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID 2400 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2 2401 * (1 <= crm < 8, 0 <= Op2 < 8). 2402 */ 2403 #define ID_UNALLOCATED(crm, op2) { \ 2404 .name = "S3_0_0_" #crm "_" #op2, \ 2405 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \ 2406 ID_DESC_DEFAULT_CALLBACKS, \ 2407 .visibility = raz_visibility, \ 2408 .val = 0, \ 2409 } 2410 2411 /* 2412 * sys_reg_desc initialiser for known ID registers that we hide from guests. 2413 * For now, these are exposed just like unallocated ID regs: they appear 2414 * RAZ for the guest. 2415 */ 2416 #define ID_HIDDEN(name) { \ 2417 ID_DESC(name), \ 2418 .visibility = raz_visibility, \ 2419 .val = 0, \ 2420 } 2421 2422 static bool access_sp_el1(struct kvm_vcpu *vcpu, 2423 struct sys_reg_params *p, 2424 const struct sys_reg_desc *r) 2425 { 2426 if (p->is_write) 2427 __vcpu_assign_sys_reg(vcpu, SP_EL1, p->regval); 2428 else 2429 p->regval = __vcpu_sys_reg(vcpu, SP_EL1); 2430 2431 return true; 2432 } 2433 2434 static bool access_elr(struct kvm_vcpu *vcpu, 2435 struct sys_reg_params *p, 2436 const struct sys_reg_desc *r) 2437 { 2438 if (p->is_write) 2439 vcpu_write_sys_reg(vcpu, p->regval, ELR_EL1); 2440 else 2441 p->regval = vcpu_read_sys_reg(vcpu, ELR_EL1); 2442 2443 return true; 2444 } 2445 2446 static bool access_spsr(struct kvm_vcpu *vcpu, 2447 struct sys_reg_params *p, 2448 const struct sys_reg_desc *r) 2449 { 2450 if (p->is_write) 2451 __vcpu_assign_sys_reg(vcpu, SPSR_EL1, p->regval); 2452 else 2453 p->regval = __vcpu_sys_reg(vcpu, SPSR_EL1); 2454 2455 return true; 2456 } 2457 2458 static bool access_cntkctl_el12(struct kvm_vcpu *vcpu, 2459 struct sys_reg_params *p, 2460 const struct sys_reg_desc *r) 2461 { 2462 if (p->is_write) 2463 __vcpu_assign_sys_reg(vcpu, CNTKCTL_EL1, p->regval); 2464 else 2465 p->regval = __vcpu_sys_reg(vcpu, CNTKCTL_EL1); 2466 2467 return true; 2468 } 2469 2470 static u64 reset_hcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 2471 { 2472 u64 val = r->val; 2473 2474 if (!cpus_have_final_cap(ARM64_HAS_HCR_NV1)) 2475 val |= HCR_E2H; 2476 2477 __vcpu_assign_sys_reg(vcpu, r->reg, val); 2478 2479 return __vcpu_sys_reg(vcpu, r->reg); 2480 } 2481 2482 static unsigned int __el2_visibility(const struct kvm_vcpu *vcpu, 2483 const struct sys_reg_desc *rd, 2484 unsigned int (*fn)(const struct kvm_vcpu *, 2485 const struct sys_reg_desc *)) 2486 { 2487 return el2_visibility(vcpu, rd) ?: fn(vcpu, rd); 2488 } 2489 2490 static unsigned int sve_el2_visibility(const struct kvm_vcpu *vcpu, 2491 const struct sys_reg_desc *rd) 2492 { 2493 return __el2_visibility(vcpu, rd, sve_visibility); 2494 } 2495 2496 static unsigned int vncr_el2_visibility(const struct kvm_vcpu *vcpu, 2497 const struct sys_reg_desc *rd) 2498 { 2499 if (el2_visibility(vcpu, rd) == 0 && 2500 kvm_has_feat(vcpu->kvm, ID_AA64MMFR4_EL1, NV_frac, NV2_ONLY)) 2501 return 0; 2502 2503 return REG_HIDDEN; 2504 } 2505 2506 static unsigned int sctlr2_visibility(const struct kvm_vcpu *vcpu, 2507 const struct sys_reg_desc *rd) 2508 { 2509 if (kvm_has_sctlr2(vcpu->kvm)) 2510 return 0; 2511 2512 return REG_HIDDEN; 2513 } 2514 2515 static unsigned int sctlr2_el2_visibility(const struct kvm_vcpu *vcpu, 2516 const struct sys_reg_desc *rd) 2517 { 2518 return __el2_visibility(vcpu, rd, sctlr2_visibility); 2519 } 2520 2521 static bool access_zcr_el2(struct kvm_vcpu *vcpu, 2522 struct sys_reg_params *p, 2523 const struct sys_reg_desc *r) 2524 { 2525 unsigned int vq; 2526 2527 if (guest_hyp_sve_traps_enabled(vcpu)) { 2528 kvm_inject_nested_sve_trap(vcpu); 2529 return true; 2530 } 2531 2532 if (!p->is_write) { 2533 p->regval = vcpu_read_sys_reg(vcpu, ZCR_EL2); 2534 return true; 2535 } 2536 2537 vq = SYS_FIELD_GET(ZCR_ELx, LEN, p->regval) + 1; 2538 vq = min(vq, vcpu_sve_max_vq(vcpu)); 2539 vcpu_write_sys_reg(vcpu, vq - 1, ZCR_EL2); 2540 2541 return true; 2542 } 2543 2544 static bool access_gic_vtr(struct kvm_vcpu *vcpu, 2545 struct sys_reg_params *p, 2546 const struct sys_reg_desc *r) 2547 { 2548 if (p->is_write) 2549 return write_to_read_only(vcpu, p, r); 2550 2551 p->regval = kvm_get_guest_vtr_el2(); 2552 2553 return true; 2554 } 2555 2556 static bool access_gic_misr(struct kvm_vcpu *vcpu, 2557 struct sys_reg_params *p, 2558 const struct sys_reg_desc *r) 2559 { 2560 if (p->is_write) 2561 return write_to_read_only(vcpu, p, r); 2562 2563 p->regval = vgic_v3_get_misr(vcpu); 2564 2565 return true; 2566 } 2567 2568 static bool access_gic_eisr(struct kvm_vcpu *vcpu, 2569 struct sys_reg_params *p, 2570 const struct sys_reg_desc *r) 2571 { 2572 if (p->is_write) 2573 return write_to_read_only(vcpu, p, r); 2574 2575 p->regval = vgic_v3_get_eisr(vcpu); 2576 2577 return true; 2578 } 2579 2580 static bool access_gic_elrsr(struct kvm_vcpu *vcpu, 2581 struct sys_reg_params *p, 2582 const struct sys_reg_desc *r) 2583 { 2584 if (p->is_write) 2585 return write_to_read_only(vcpu, p, r); 2586 2587 p->regval = vgic_v3_get_elrsr(vcpu); 2588 2589 return true; 2590 } 2591 2592 static unsigned int s1poe_visibility(const struct kvm_vcpu *vcpu, 2593 const struct sys_reg_desc *rd) 2594 { 2595 if (kvm_has_s1poe(vcpu->kvm)) 2596 return 0; 2597 2598 return REG_HIDDEN; 2599 } 2600 2601 static unsigned int s1poe_el2_visibility(const struct kvm_vcpu *vcpu, 2602 const struct sys_reg_desc *rd) 2603 { 2604 return __el2_visibility(vcpu, rd, s1poe_visibility); 2605 } 2606 2607 static unsigned int tcr2_visibility(const struct kvm_vcpu *vcpu, 2608 const struct sys_reg_desc *rd) 2609 { 2610 if (kvm_has_tcr2(vcpu->kvm)) 2611 return 0; 2612 2613 return REG_HIDDEN; 2614 } 2615 2616 static unsigned int tcr2_el2_visibility(const struct kvm_vcpu *vcpu, 2617 const struct sys_reg_desc *rd) 2618 { 2619 return __el2_visibility(vcpu, rd, tcr2_visibility); 2620 } 2621 2622 static unsigned int fgt2_visibility(const struct kvm_vcpu *vcpu, 2623 const struct sys_reg_desc *rd) 2624 { 2625 if (el2_visibility(vcpu, rd) == 0 && 2626 kvm_has_feat(vcpu->kvm, ID_AA64MMFR0_EL1, FGT, FGT2)) 2627 return 0; 2628 2629 return REG_HIDDEN; 2630 } 2631 2632 static unsigned int fgt_visibility(const struct kvm_vcpu *vcpu, 2633 const struct sys_reg_desc *rd) 2634 { 2635 if (el2_visibility(vcpu, rd) == 0 && 2636 kvm_has_feat(vcpu->kvm, ID_AA64MMFR0_EL1, FGT, IMP)) 2637 return 0; 2638 2639 return REG_HIDDEN; 2640 } 2641 2642 static unsigned int s1pie_visibility(const struct kvm_vcpu *vcpu, 2643 const struct sys_reg_desc *rd) 2644 { 2645 if (kvm_has_s1pie(vcpu->kvm)) 2646 return 0; 2647 2648 return REG_HIDDEN; 2649 } 2650 2651 static unsigned int s1pie_el2_visibility(const struct kvm_vcpu *vcpu, 2652 const struct sys_reg_desc *rd) 2653 { 2654 return __el2_visibility(vcpu, rd, s1pie_visibility); 2655 } 2656 2657 static bool access_mdcr(struct kvm_vcpu *vcpu, 2658 struct sys_reg_params *p, 2659 const struct sys_reg_desc *r) 2660 { 2661 u64 hpmn, val, old = __vcpu_sys_reg(vcpu, MDCR_EL2); 2662 2663 if (!p->is_write) { 2664 p->regval = old; 2665 return true; 2666 } 2667 2668 val = p->regval; 2669 hpmn = FIELD_GET(MDCR_EL2_HPMN, val); 2670 2671 /* 2672 * If HPMN is out of bounds, limit it to what we actually 2673 * support. This matches the UNKNOWN definition of the field 2674 * in that case, and keeps the emulation simple. Sort of. 2675 */ 2676 if (hpmn > vcpu->kvm->arch.nr_pmu_counters) { 2677 hpmn = vcpu->kvm->arch.nr_pmu_counters; 2678 u64p_replace_bits(&val, hpmn, MDCR_EL2_HPMN); 2679 } 2680 2681 __vcpu_assign_sys_reg(vcpu, MDCR_EL2, val); 2682 2683 /* 2684 * Request a reload of the PMU to enable/disable the counters 2685 * affected by HPME. 2686 */ 2687 if ((old ^ val) & MDCR_EL2_HPME) 2688 kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu); 2689 2690 return true; 2691 } 2692 2693 static bool access_ras(struct kvm_vcpu *vcpu, 2694 struct sys_reg_params *p, 2695 const struct sys_reg_desc *r) 2696 { 2697 struct kvm *kvm = vcpu->kvm; 2698 2699 switch(reg_to_encoding(r)) { 2700 default: 2701 if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, RAS, IMP)) { 2702 kvm_inject_undefined(vcpu); 2703 return false; 2704 } 2705 } 2706 2707 return trap_raz_wi(vcpu, p, r); 2708 } 2709 2710 /* 2711 * For historical (ahem ABI) reasons, KVM treated MIDR_EL1, REVIDR_EL1, and 2712 * AIDR_EL1 as "invariant" registers, meaning userspace cannot change them. 2713 * The values made visible to userspace were the register values of the boot 2714 * CPU. 2715 * 2716 * At the same time, reads from these registers at EL1 previously were not 2717 * trapped, allowing the guest to read the actual hardware value. On big-little 2718 * machines, this means the VM can see different values depending on where a 2719 * given vCPU got scheduled. 2720 * 2721 * These registers are now trapped as collateral damage from SME, and what 2722 * follows attempts to give a user / guest view consistent with the existing 2723 * ABI. 2724 */ 2725 static bool access_imp_id_reg(struct kvm_vcpu *vcpu, 2726 struct sys_reg_params *p, 2727 const struct sys_reg_desc *r) 2728 { 2729 if (p->is_write) 2730 return write_to_read_only(vcpu, p, r); 2731 2732 /* 2733 * Return the VM-scoped implementation ID register values if userspace 2734 * has made them writable. 2735 */ 2736 if (test_bit(KVM_ARCH_FLAG_WRITABLE_IMP_ID_REGS, &vcpu->kvm->arch.flags)) 2737 return access_id_reg(vcpu, p, r); 2738 2739 /* 2740 * Otherwise, fall back to the old behavior of returning the value of 2741 * the current CPU. 2742 */ 2743 switch (reg_to_encoding(r)) { 2744 case SYS_REVIDR_EL1: 2745 p->regval = read_sysreg(revidr_el1); 2746 break; 2747 case SYS_AIDR_EL1: 2748 p->regval = read_sysreg(aidr_el1); 2749 break; 2750 default: 2751 WARN_ON_ONCE(1); 2752 } 2753 2754 return true; 2755 } 2756 2757 static u64 __ro_after_init boot_cpu_midr_val; 2758 static u64 __ro_after_init boot_cpu_revidr_val; 2759 static u64 __ro_after_init boot_cpu_aidr_val; 2760 2761 static void init_imp_id_regs(void) 2762 { 2763 boot_cpu_midr_val = read_sysreg(midr_el1); 2764 boot_cpu_revidr_val = read_sysreg(revidr_el1); 2765 boot_cpu_aidr_val = read_sysreg(aidr_el1); 2766 } 2767 2768 static u64 reset_imp_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 2769 { 2770 switch (reg_to_encoding(r)) { 2771 case SYS_MIDR_EL1: 2772 return boot_cpu_midr_val; 2773 case SYS_REVIDR_EL1: 2774 return boot_cpu_revidr_val; 2775 case SYS_AIDR_EL1: 2776 return boot_cpu_aidr_val; 2777 default: 2778 KVM_BUG_ON(1, vcpu->kvm); 2779 return 0; 2780 } 2781 } 2782 2783 static int set_imp_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 2784 u64 val) 2785 { 2786 struct kvm *kvm = vcpu->kvm; 2787 u64 expected; 2788 2789 guard(mutex)(&kvm->arch.config_lock); 2790 2791 expected = read_id_reg(vcpu, r); 2792 if (expected == val) 2793 return 0; 2794 2795 if (!test_bit(KVM_ARCH_FLAG_WRITABLE_IMP_ID_REGS, &kvm->arch.flags)) 2796 return -EINVAL; 2797 2798 /* 2799 * Once the VM has started the ID registers are immutable. Reject the 2800 * write if userspace tries to change it. 2801 */ 2802 if (kvm_vm_has_ran_once(kvm)) 2803 return -EBUSY; 2804 2805 /* 2806 * Any value is allowed for the implementation ID registers so long as 2807 * it is within the writable mask. 2808 */ 2809 if ((val & r->val) != val) 2810 return -EINVAL; 2811 2812 kvm_set_vm_id_reg(kvm, reg_to_encoding(r), val); 2813 return 0; 2814 } 2815 2816 #define IMPLEMENTATION_ID(reg, mask) { \ 2817 SYS_DESC(SYS_##reg), \ 2818 .access = access_imp_id_reg, \ 2819 .get_user = get_id_reg, \ 2820 .set_user = set_imp_id_reg, \ 2821 .reset = reset_imp_id_reg, \ 2822 .val = mask, \ 2823 } 2824 2825 static u64 reset_mdcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 2826 { 2827 __vcpu_assign_sys_reg(vcpu, r->reg, vcpu->kvm->arch.nr_pmu_counters); 2828 return vcpu->kvm->arch.nr_pmu_counters; 2829 } 2830 2831 /* 2832 * Architected system registers. 2833 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2 2834 * 2835 * Debug handling: We do trap most, if not all debug related system 2836 * registers. The implementation is good enough to ensure that a guest 2837 * can use these with minimal performance degradation. The drawback is 2838 * that we don't implement any of the external debug architecture. 2839 * This should be revisited if we ever encounter a more demanding 2840 * guest... 2841 */ 2842 static const struct sys_reg_desc sys_reg_descs[] = { 2843 DBG_BCR_BVR_WCR_WVR_EL1(0), 2844 DBG_BCR_BVR_WCR_WVR_EL1(1), 2845 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 }, 2846 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 }, 2847 DBG_BCR_BVR_WCR_WVR_EL1(2), 2848 DBG_BCR_BVR_WCR_WVR_EL1(3), 2849 DBG_BCR_BVR_WCR_WVR_EL1(4), 2850 DBG_BCR_BVR_WCR_WVR_EL1(5), 2851 DBG_BCR_BVR_WCR_WVR_EL1(6), 2852 DBG_BCR_BVR_WCR_WVR_EL1(7), 2853 DBG_BCR_BVR_WCR_WVR_EL1(8), 2854 DBG_BCR_BVR_WCR_WVR_EL1(9), 2855 DBG_BCR_BVR_WCR_WVR_EL1(10), 2856 DBG_BCR_BVR_WCR_WVR_EL1(11), 2857 DBG_BCR_BVR_WCR_WVR_EL1(12), 2858 DBG_BCR_BVR_WCR_WVR_EL1(13), 2859 DBG_BCR_BVR_WCR_WVR_EL1(14), 2860 DBG_BCR_BVR_WCR_WVR_EL1(15), 2861 2862 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi }, 2863 { SYS_DESC(SYS_OSLAR_EL1), trap_oslar_el1 }, 2864 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1, 2865 OSLSR_EL1_OSLM_IMPLEMENTED, .set_user = set_oslsr_el1, }, 2866 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi }, 2867 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi }, 2868 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi }, 2869 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi }, 2870 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 }, 2871 2872 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi }, 2873 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi }, 2874 // DBGDTR[TR]X_EL0 share the same encoding 2875 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi }, 2876 2877 { SYS_DESC(SYS_DBGVCR32_EL2), undef_access, reset_val, DBGVCR32_EL2, 0 }, 2878 2879 IMPLEMENTATION_ID(MIDR_EL1, GENMASK_ULL(31, 0)), 2880 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 }, 2881 IMPLEMENTATION_ID(REVIDR_EL1, GENMASK_ULL(63, 0)), 2882 2883 /* 2884 * ID regs: all ID_SANITISED() entries here must have corresponding 2885 * entries in arm64_ftr_regs[]. 2886 */ 2887 2888 /* AArch64 mappings of the AArch32 ID registers */ 2889 /* CRm=1 */ 2890 AA32_ID_SANITISED(ID_PFR0_EL1), 2891 AA32_ID_SANITISED(ID_PFR1_EL1), 2892 { SYS_DESC(SYS_ID_DFR0_EL1), 2893 .access = access_id_reg, 2894 .get_user = get_id_reg, 2895 .set_user = set_id_dfr0_el1, 2896 .visibility = aa32_id_visibility, 2897 .reset = read_sanitised_id_dfr0_el1, 2898 .val = ID_DFR0_EL1_PerfMon_MASK | 2899 ID_DFR0_EL1_CopDbg_MASK, }, 2900 ID_HIDDEN(ID_AFR0_EL1), 2901 AA32_ID_SANITISED(ID_MMFR0_EL1), 2902 AA32_ID_SANITISED(ID_MMFR1_EL1), 2903 AA32_ID_SANITISED(ID_MMFR2_EL1), 2904 AA32_ID_SANITISED(ID_MMFR3_EL1), 2905 2906 /* CRm=2 */ 2907 AA32_ID_SANITISED(ID_ISAR0_EL1), 2908 AA32_ID_SANITISED(ID_ISAR1_EL1), 2909 AA32_ID_SANITISED(ID_ISAR2_EL1), 2910 AA32_ID_SANITISED(ID_ISAR3_EL1), 2911 AA32_ID_SANITISED(ID_ISAR4_EL1), 2912 AA32_ID_SANITISED(ID_ISAR5_EL1), 2913 AA32_ID_SANITISED(ID_MMFR4_EL1), 2914 AA32_ID_SANITISED(ID_ISAR6_EL1), 2915 2916 /* CRm=3 */ 2917 AA32_ID_SANITISED(MVFR0_EL1), 2918 AA32_ID_SANITISED(MVFR1_EL1), 2919 AA32_ID_SANITISED(MVFR2_EL1), 2920 ID_UNALLOCATED(3,3), 2921 AA32_ID_SANITISED(ID_PFR2_EL1), 2922 ID_HIDDEN(ID_DFR1_EL1), 2923 AA32_ID_SANITISED(ID_MMFR5_EL1), 2924 ID_UNALLOCATED(3,7), 2925 2926 /* AArch64 ID registers */ 2927 /* CRm=4 */ 2928 ID_FILTERED(ID_AA64PFR0_EL1, id_aa64pfr0_el1, 2929 ~(ID_AA64PFR0_EL1_AMU | 2930 ID_AA64PFR0_EL1_MPAM | 2931 ID_AA64PFR0_EL1_SVE | 2932 ID_AA64PFR0_EL1_RAS | 2933 ID_AA64PFR0_EL1_AdvSIMD | 2934 ID_AA64PFR0_EL1_FP)), 2935 ID_FILTERED(ID_AA64PFR1_EL1, id_aa64pfr1_el1, 2936 ~(ID_AA64PFR1_EL1_PFAR | 2937 ID_AA64PFR1_EL1_MTEX | 2938 ID_AA64PFR1_EL1_THE | 2939 ID_AA64PFR1_EL1_GCS | 2940 ID_AA64PFR1_EL1_MTE_frac | 2941 ID_AA64PFR1_EL1_NMI | 2942 ID_AA64PFR1_EL1_RNDR_trap | 2943 ID_AA64PFR1_EL1_SME | 2944 ID_AA64PFR1_EL1_RES0 | 2945 ID_AA64PFR1_EL1_MPAM_frac | 2946 ID_AA64PFR1_EL1_RAS_frac | 2947 ID_AA64PFR1_EL1_MTE)), 2948 ID_WRITABLE(ID_AA64PFR2_EL1, 2949 ID_AA64PFR2_EL1_FPMR | 2950 ID_AA64PFR2_EL1_MTEFAR | 2951 ID_AA64PFR2_EL1_MTESTOREONLY), 2952 ID_UNALLOCATED(4,3), 2953 ID_WRITABLE(ID_AA64ZFR0_EL1, ~ID_AA64ZFR0_EL1_RES0), 2954 ID_HIDDEN(ID_AA64SMFR0_EL1), 2955 ID_UNALLOCATED(4,6), 2956 ID_WRITABLE(ID_AA64FPFR0_EL1, ~ID_AA64FPFR0_EL1_RES0), 2957 2958 /* CRm=5 */ 2959 /* 2960 * Prior to FEAT_Debugv8.9, the architecture defines context-aware 2961 * breakpoints (CTX_CMPs) as the highest numbered breakpoints (BRPs). 2962 * KVM does not trap + emulate the breakpoint registers, and as such 2963 * cannot support a layout that misaligns with the underlying hardware. 2964 * While it may be possible to describe a subset that aligns with 2965 * hardware, just prevent changes to BRPs and CTX_CMPs altogether for 2966 * simplicity. 2967 * 2968 * See DDI0487K.a, section D2.8.3 Breakpoint types and linking 2969 * of breakpoints for more details. 2970 */ 2971 ID_FILTERED(ID_AA64DFR0_EL1, id_aa64dfr0_el1, 2972 ID_AA64DFR0_EL1_DoubleLock_MASK | 2973 ID_AA64DFR0_EL1_WRPs_MASK | 2974 ID_AA64DFR0_EL1_PMUVer_MASK | 2975 ID_AA64DFR0_EL1_DebugVer_MASK), 2976 ID_SANITISED(ID_AA64DFR1_EL1), 2977 ID_UNALLOCATED(5,2), 2978 ID_UNALLOCATED(5,3), 2979 ID_HIDDEN(ID_AA64AFR0_EL1), 2980 ID_HIDDEN(ID_AA64AFR1_EL1), 2981 ID_UNALLOCATED(5,6), 2982 ID_UNALLOCATED(5,7), 2983 2984 /* CRm=6 */ 2985 ID_WRITABLE(ID_AA64ISAR0_EL1, ~ID_AA64ISAR0_EL1_RES0), 2986 ID_WRITABLE(ID_AA64ISAR1_EL1, ~(ID_AA64ISAR1_EL1_GPI | 2987 ID_AA64ISAR1_EL1_GPA | 2988 ID_AA64ISAR1_EL1_API | 2989 ID_AA64ISAR1_EL1_APA)), 2990 ID_WRITABLE(ID_AA64ISAR2_EL1, ~(ID_AA64ISAR2_EL1_RES0 | 2991 ID_AA64ISAR2_EL1_APA3 | 2992 ID_AA64ISAR2_EL1_GPA3)), 2993 ID_WRITABLE(ID_AA64ISAR3_EL1, (ID_AA64ISAR3_EL1_FPRCVT | 2994 ID_AA64ISAR3_EL1_FAMINMAX)), 2995 ID_UNALLOCATED(6,4), 2996 ID_UNALLOCATED(6,5), 2997 ID_UNALLOCATED(6,6), 2998 ID_UNALLOCATED(6,7), 2999 3000 /* CRm=7 */ 3001 ID_FILTERED(ID_AA64MMFR0_EL1, id_aa64mmfr0_el1, 3002 ~(ID_AA64MMFR0_EL1_RES0 | 3003 ID_AA64MMFR0_EL1_ASIDBITS)), 3004 ID_WRITABLE(ID_AA64MMFR1_EL1, ~(ID_AA64MMFR1_EL1_RES0 | 3005 ID_AA64MMFR1_EL1_HCX | 3006 ID_AA64MMFR1_EL1_TWED | 3007 ID_AA64MMFR1_EL1_XNX | 3008 ID_AA64MMFR1_EL1_VH | 3009 ID_AA64MMFR1_EL1_VMIDBits)), 3010 ID_FILTERED(ID_AA64MMFR2_EL1, 3011 id_aa64mmfr2_el1, ~(ID_AA64MMFR2_EL1_RES0 | 3012 ID_AA64MMFR2_EL1_EVT | 3013 ID_AA64MMFR2_EL1_FWB | 3014 ID_AA64MMFR2_EL1_IDS | 3015 ID_AA64MMFR2_EL1_NV | 3016 ID_AA64MMFR2_EL1_CCIDX)), 3017 ID_WRITABLE(ID_AA64MMFR3_EL1, (ID_AA64MMFR3_EL1_TCRX | 3018 ID_AA64MMFR3_EL1_SCTLRX | 3019 ID_AA64MMFR3_EL1_S1PIE | 3020 ID_AA64MMFR3_EL1_S1POE)), 3021 ID_WRITABLE(ID_AA64MMFR4_EL1, ID_AA64MMFR4_EL1_NV_frac), 3022 ID_UNALLOCATED(7,5), 3023 ID_UNALLOCATED(7,6), 3024 ID_UNALLOCATED(7,7), 3025 3026 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 }, 3027 { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 }, 3028 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 }, 3029 { SYS_DESC(SYS_SCTLR2_EL1), access_vm_reg, reset_val, SCTLR2_EL1, 0, 3030 .visibility = sctlr2_visibility }, 3031 3032 MTE_REG(RGSR_EL1), 3033 MTE_REG(GCR_EL1), 3034 3035 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility }, 3036 { SYS_DESC(SYS_TRFCR_EL1), undef_access }, 3037 { SYS_DESC(SYS_SMPRI_EL1), undef_access }, 3038 { SYS_DESC(SYS_SMCR_EL1), undef_access }, 3039 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 }, 3040 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 }, 3041 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 }, 3042 { SYS_DESC(SYS_TCR2_EL1), access_vm_reg, reset_val, TCR2_EL1, 0, 3043 .visibility = tcr2_visibility }, 3044 3045 PTRAUTH_KEY(APIA), 3046 PTRAUTH_KEY(APIB), 3047 PTRAUTH_KEY(APDA), 3048 PTRAUTH_KEY(APDB), 3049 PTRAUTH_KEY(APGA), 3050 3051 { SYS_DESC(SYS_SPSR_EL1), access_spsr}, 3052 { SYS_DESC(SYS_ELR_EL1), access_elr}, 3053 3054 { SYS_DESC(SYS_ICC_PMR_EL1), undef_access }, 3055 3056 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 }, 3057 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 }, 3058 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 }, 3059 3060 { SYS_DESC(SYS_ERRIDR_EL1), access_ras }, 3061 { SYS_DESC(SYS_ERRSELR_EL1), access_ras }, 3062 { SYS_DESC(SYS_ERXFR_EL1), access_ras }, 3063 { SYS_DESC(SYS_ERXCTLR_EL1), access_ras }, 3064 { SYS_DESC(SYS_ERXSTATUS_EL1), access_ras }, 3065 { SYS_DESC(SYS_ERXADDR_EL1), access_ras }, 3066 { SYS_DESC(SYS_ERXMISC0_EL1), access_ras }, 3067 { SYS_DESC(SYS_ERXMISC1_EL1), access_ras }, 3068 3069 MTE_REG(TFSR_EL1), 3070 MTE_REG(TFSRE0_EL1), 3071 3072 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 }, 3073 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 }, 3074 3075 { SYS_DESC(SYS_PMSCR_EL1), undef_access }, 3076 { SYS_DESC(SYS_PMSNEVFR_EL1), undef_access }, 3077 { SYS_DESC(SYS_PMSICR_EL1), undef_access }, 3078 { SYS_DESC(SYS_PMSIRR_EL1), undef_access }, 3079 { SYS_DESC(SYS_PMSFCR_EL1), undef_access }, 3080 { SYS_DESC(SYS_PMSEVFR_EL1), undef_access }, 3081 { SYS_DESC(SYS_PMSLATFR_EL1), undef_access }, 3082 { SYS_DESC(SYS_PMSIDR_EL1), undef_access }, 3083 { SYS_DESC(SYS_PMBLIMITR_EL1), undef_access }, 3084 { SYS_DESC(SYS_PMBPTR_EL1), undef_access }, 3085 { SYS_DESC(SYS_PMBSR_EL1), undef_access }, 3086 /* PMBIDR_EL1 is not trapped */ 3087 3088 { PMU_SYS_REG(PMINTENSET_EL1), 3089 .access = access_pminten, .reg = PMINTENSET_EL1, 3090 .get_user = get_pmreg, .set_user = set_pmreg }, 3091 { PMU_SYS_REG(PMINTENCLR_EL1), 3092 .access = access_pminten, .reg = PMINTENSET_EL1, 3093 .get_user = get_pmreg, .set_user = set_pmreg }, 3094 { SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi }, 3095 3096 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 }, 3097 { SYS_DESC(SYS_PIRE0_EL1), NULL, reset_unknown, PIRE0_EL1, 3098 .visibility = s1pie_visibility }, 3099 { SYS_DESC(SYS_PIR_EL1), NULL, reset_unknown, PIR_EL1, 3100 .visibility = s1pie_visibility }, 3101 { SYS_DESC(SYS_POR_EL1), NULL, reset_unknown, POR_EL1, 3102 .visibility = s1poe_visibility }, 3103 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 }, 3104 3105 { SYS_DESC(SYS_LORSA_EL1), trap_loregion }, 3106 { SYS_DESC(SYS_LOREA_EL1), trap_loregion }, 3107 { SYS_DESC(SYS_LORN_EL1), trap_loregion }, 3108 { SYS_DESC(SYS_LORC_EL1), trap_loregion }, 3109 { SYS_DESC(SYS_MPAMIDR_EL1), undef_access }, 3110 { SYS_DESC(SYS_LORID_EL1), trap_loregion }, 3111 3112 { SYS_DESC(SYS_MPAM1_EL1), undef_access }, 3113 { SYS_DESC(SYS_MPAM0_EL1), undef_access }, 3114 { SYS_DESC(SYS_VBAR_EL1), access_rw, reset_val, VBAR_EL1, 0 }, 3115 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 }, 3116 3117 { SYS_DESC(SYS_ICC_IAR0_EL1), undef_access }, 3118 { SYS_DESC(SYS_ICC_EOIR0_EL1), undef_access }, 3119 { SYS_DESC(SYS_ICC_HPPIR0_EL1), undef_access }, 3120 { SYS_DESC(SYS_ICC_BPR0_EL1), undef_access }, 3121 { SYS_DESC(SYS_ICC_AP0R0_EL1), undef_access }, 3122 { SYS_DESC(SYS_ICC_AP0R1_EL1), undef_access }, 3123 { SYS_DESC(SYS_ICC_AP0R2_EL1), undef_access }, 3124 { SYS_DESC(SYS_ICC_AP0R3_EL1), undef_access }, 3125 { SYS_DESC(SYS_ICC_AP1R0_EL1), undef_access }, 3126 { SYS_DESC(SYS_ICC_AP1R1_EL1), undef_access }, 3127 { SYS_DESC(SYS_ICC_AP1R2_EL1), undef_access }, 3128 { SYS_DESC(SYS_ICC_AP1R3_EL1), undef_access }, 3129 { SYS_DESC(SYS_ICC_DIR_EL1), undef_access }, 3130 { SYS_DESC(SYS_ICC_RPR_EL1), undef_access }, 3131 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi }, 3132 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi }, 3133 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi }, 3134 { SYS_DESC(SYS_ICC_IAR1_EL1), undef_access }, 3135 { SYS_DESC(SYS_ICC_EOIR1_EL1), undef_access }, 3136 { SYS_DESC(SYS_ICC_HPPIR1_EL1), undef_access }, 3137 { SYS_DESC(SYS_ICC_BPR1_EL1), undef_access }, 3138 { SYS_DESC(SYS_ICC_CTLR_EL1), undef_access }, 3139 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre }, 3140 { SYS_DESC(SYS_ICC_IGRPEN0_EL1), undef_access }, 3141 { SYS_DESC(SYS_ICC_IGRPEN1_EL1), undef_access }, 3142 3143 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 }, 3144 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 }, 3145 3146 { SYS_DESC(SYS_ACCDATA_EL1), undef_access }, 3147 3148 { SYS_DESC(SYS_SCXTNUM_EL1), undef_access }, 3149 3150 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0}, 3151 3152 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr }, 3153 { SYS_DESC(SYS_CLIDR_EL1), access_clidr, reset_clidr, CLIDR_EL1, 3154 .set_user = set_clidr, .val = ~CLIDR_EL1_RES0 }, 3155 { SYS_DESC(SYS_CCSIDR2_EL1), undef_access }, 3156 { SYS_DESC(SYS_SMIDR_EL1), undef_access }, 3157 IMPLEMENTATION_ID(AIDR_EL1, GENMASK_ULL(63, 0)), 3158 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, 3159 ID_FILTERED(CTR_EL0, ctr_el0, 3160 CTR_EL0_DIC_MASK | 3161 CTR_EL0_IDC_MASK | 3162 CTR_EL0_DminLine_MASK | 3163 CTR_EL0_L1Ip_MASK | 3164 CTR_EL0_IminLine_MASK), 3165 { SYS_DESC(SYS_SVCR), undef_access, reset_val, SVCR, 0, .visibility = sme_visibility }, 3166 { SYS_DESC(SYS_FPMR), undef_access, reset_val, FPMR, 0, .visibility = fp8_visibility }, 3167 3168 { PMU_SYS_REG(PMCR_EL0), .access = access_pmcr, .reset = reset_pmcr, 3169 .reg = PMCR_EL0, .get_user = get_pmcr, .set_user = set_pmcr }, 3170 { PMU_SYS_REG(PMCNTENSET_EL0), 3171 .access = access_pmcnten, .reg = PMCNTENSET_EL0, 3172 .get_user = get_pmreg, .set_user = set_pmreg }, 3173 { PMU_SYS_REG(PMCNTENCLR_EL0), 3174 .access = access_pmcnten, .reg = PMCNTENSET_EL0, 3175 .get_user = get_pmreg, .set_user = set_pmreg }, 3176 { PMU_SYS_REG(PMOVSCLR_EL0), 3177 .access = access_pmovs, .reg = PMOVSSET_EL0, 3178 .get_user = get_pmreg, .set_user = set_pmreg }, 3179 /* 3180 * PM_SWINC_EL0 is exposed to userspace as RAZ/WI, as it was 3181 * previously (and pointlessly) advertised in the past... 3182 */ 3183 { PMU_SYS_REG(PMSWINC_EL0), 3184 .get_user = get_raz_reg, .set_user = set_wi_reg, 3185 .access = access_pmswinc, .reset = NULL }, 3186 { PMU_SYS_REG(PMSELR_EL0), 3187 .access = access_pmselr, .reset = reset_pmselr, .reg = PMSELR_EL0 }, 3188 { PMU_SYS_REG(PMCEID0_EL0), 3189 .access = access_pmceid, .reset = NULL }, 3190 { PMU_SYS_REG(PMCEID1_EL0), 3191 .access = access_pmceid, .reset = NULL }, 3192 { PMU_SYS_REG(PMCCNTR_EL0), 3193 .access = access_pmu_evcntr, .reset = reset_unknown, 3194 .reg = PMCCNTR_EL0, .get_user = get_pmu_evcntr, 3195 .set_user = set_pmu_evcntr }, 3196 { PMU_SYS_REG(PMXEVTYPER_EL0), 3197 .access = access_pmu_evtyper, .reset = NULL }, 3198 { PMU_SYS_REG(PMXEVCNTR_EL0), 3199 .access = access_pmu_evcntr, .reset = NULL }, 3200 /* 3201 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero 3202 * in 32bit mode. Here we choose to reset it as zero for consistency. 3203 */ 3204 { PMU_SYS_REG(PMUSERENR_EL0), .access = access_pmuserenr, 3205 .reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 }, 3206 { PMU_SYS_REG(PMOVSSET_EL0), 3207 .access = access_pmovs, .reg = PMOVSSET_EL0, 3208 .get_user = get_pmreg, .set_user = set_pmreg }, 3209 3210 { SYS_DESC(SYS_POR_EL0), NULL, reset_unknown, POR_EL0, 3211 .visibility = s1poe_visibility }, 3212 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 }, 3213 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 }, 3214 { SYS_DESC(SYS_TPIDR2_EL0), undef_access }, 3215 3216 { SYS_DESC(SYS_SCXTNUM_EL0), undef_access }, 3217 3218 { SYS_DESC(SYS_AMCR_EL0), undef_access }, 3219 { SYS_DESC(SYS_AMCFGR_EL0), undef_access }, 3220 { SYS_DESC(SYS_AMCGCR_EL0), undef_access }, 3221 { SYS_DESC(SYS_AMUSERENR_EL0), undef_access }, 3222 { SYS_DESC(SYS_AMCNTENCLR0_EL0), undef_access }, 3223 { SYS_DESC(SYS_AMCNTENSET0_EL0), undef_access }, 3224 { SYS_DESC(SYS_AMCNTENCLR1_EL0), undef_access }, 3225 { SYS_DESC(SYS_AMCNTENSET1_EL0), undef_access }, 3226 AMU_AMEVCNTR0_EL0(0), 3227 AMU_AMEVCNTR0_EL0(1), 3228 AMU_AMEVCNTR0_EL0(2), 3229 AMU_AMEVCNTR0_EL0(3), 3230 AMU_AMEVCNTR0_EL0(4), 3231 AMU_AMEVCNTR0_EL0(5), 3232 AMU_AMEVCNTR0_EL0(6), 3233 AMU_AMEVCNTR0_EL0(7), 3234 AMU_AMEVCNTR0_EL0(8), 3235 AMU_AMEVCNTR0_EL0(9), 3236 AMU_AMEVCNTR0_EL0(10), 3237 AMU_AMEVCNTR0_EL0(11), 3238 AMU_AMEVCNTR0_EL0(12), 3239 AMU_AMEVCNTR0_EL0(13), 3240 AMU_AMEVCNTR0_EL0(14), 3241 AMU_AMEVCNTR0_EL0(15), 3242 AMU_AMEVTYPER0_EL0(0), 3243 AMU_AMEVTYPER0_EL0(1), 3244 AMU_AMEVTYPER0_EL0(2), 3245 AMU_AMEVTYPER0_EL0(3), 3246 AMU_AMEVTYPER0_EL0(4), 3247 AMU_AMEVTYPER0_EL0(5), 3248 AMU_AMEVTYPER0_EL0(6), 3249 AMU_AMEVTYPER0_EL0(7), 3250 AMU_AMEVTYPER0_EL0(8), 3251 AMU_AMEVTYPER0_EL0(9), 3252 AMU_AMEVTYPER0_EL0(10), 3253 AMU_AMEVTYPER0_EL0(11), 3254 AMU_AMEVTYPER0_EL0(12), 3255 AMU_AMEVTYPER0_EL0(13), 3256 AMU_AMEVTYPER0_EL0(14), 3257 AMU_AMEVTYPER0_EL0(15), 3258 AMU_AMEVCNTR1_EL0(0), 3259 AMU_AMEVCNTR1_EL0(1), 3260 AMU_AMEVCNTR1_EL0(2), 3261 AMU_AMEVCNTR1_EL0(3), 3262 AMU_AMEVCNTR1_EL0(4), 3263 AMU_AMEVCNTR1_EL0(5), 3264 AMU_AMEVCNTR1_EL0(6), 3265 AMU_AMEVCNTR1_EL0(7), 3266 AMU_AMEVCNTR1_EL0(8), 3267 AMU_AMEVCNTR1_EL0(9), 3268 AMU_AMEVCNTR1_EL0(10), 3269 AMU_AMEVCNTR1_EL0(11), 3270 AMU_AMEVCNTR1_EL0(12), 3271 AMU_AMEVCNTR1_EL0(13), 3272 AMU_AMEVCNTR1_EL0(14), 3273 AMU_AMEVCNTR1_EL0(15), 3274 AMU_AMEVTYPER1_EL0(0), 3275 AMU_AMEVTYPER1_EL0(1), 3276 AMU_AMEVTYPER1_EL0(2), 3277 AMU_AMEVTYPER1_EL0(3), 3278 AMU_AMEVTYPER1_EL0(4), 3279 AMU_AMEVTYPER1_EL0(5), 3280 AMU_AMEVTYPER1_EL0(6), 3281 AMU_AMEVTYPER1_EL0(7), 3282 AMU_AMEVTYPER1_EL0(8), 3283 AMU_AMEVTYPER1_EL0(9), 3284 AMU_AMEVTYPER1_EL0(10), 3285 AMU_AMEVTYPER1_EL0(11), 3286 AMU_AMEVTYPER1_EL0(12), 3287 AMU_AMEVTYPER1_EL0(13), 3288 AMU_AMEVTYPER1_EL0(14), 3289 AMU_AMEVTYPER1_EL0(15), 3290 3291 { SYS_DESC(SYS_CNTPCT_EL0), access_arch_timer }, 3292 { SYS_DESC(SYS_CNTVCT_EL0), access_arch_timer }, 3293 { SYS_DESC(SYS_CNTPCTSS_EL0), access_arch_timer }, 3294 { SYS_DESC(SYS_CNTVCTSS_EL0), access_arch_timer }, 3295 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer }, 3296 { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer }, 3297 { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer }, 3298 3299 { SYS_DESC(SYS_CNTV_TVAL_EL0), access_arch_timer }, 3300 { SYS_DESC(SYS_CNTV_CTL_EL0), access_arch_timer }, 3301 { SYS_DESC(SYS_CNTV_CVAL_EL0), access_arch_timer }, 3302 3303 /* PMEVCNTRn_EL0 */ 3304 PMU_PMEVCNTR_EL0(0), 3305 PMU_PMEVCNTR_EL0(1), 3306 PMU_PMEVCNTR_EL0(2), 3307 PMU_PMEVCNTR_EL0(3), 3308 PMU_PMEVCNTR_EL0(4), 3309 PMU_PMEVCNTR_EL0(5), 3310 PMU_PMEVCNTR_EL0(6), 3311 PMU_PMEVCNTR_EL0(7), 3312 PMU_PMEVCNTR_EL0(8), 3313 PMU_PMEVCNTR_EL0(9), 3314 PMU_PMEVCNTR_EL0(10), 3315 PMU_PMEVCNTR_EL0(11), 3316 PMU_PMEVCNTR_EL0(12), 3317 PMU_PMEVCNTR_EL0(13), 3318 PMU_PMEVCNTR_EL0(14), 3319 PMU_PMEVCNTR_EL0(15), 3320 PMU_PMEVCNTR_EL0(16), 3321 PMU_PMEVCNTR_EL0(17), 3322 PMU_PMEVCNTR_EL0(18), 3323 PMU_PMEVCNTR_EL0(19), 3324 PMU_PMEVCNTR_EL0(20), 3325 PMU_PMEVCNTR_EL0(21), 3326 PMU_PMEVCNTR_EL0(22), 3327 PMU_PMEVCNTR_EL0(23), 3328 PMU_PMEVCNTR_EL0(24), 3329 PMU_PMEVCNTR_EL0(25), 3330 PMU_PMEVCNTR_EL0(26), 3331 PMU_PMEVCNTR_EL0(27), 3332 PMU_PMEVCNTR_EL0(28), 3333 PMU_PMEVCNTR_EL0(29), 3334 PMU_PMEVCNTR_EL0(30), 3335 /* PMEVTYPERn_EL0 */ 3336 PMU_PMEVTYPER_EL0(0), 3337 PMU_PMEVTYPER_EL0(1), 3338 PMU_PMEVTYPER_EL0(2), 3339 PMU_PMEVTYPER_EL0(3), 3340 PMU_PMEVTYPER_EL0(4), 3341 PMU_PMEVTYPER_EL0(5), 3342 PMU_PMEVTYPER_EL0(6), 3343 PMU_PMEVTYPER_EL0(7), 3344 PMU_PMEVTYPER_EL0(8), 3345 PMU_PMEVTYPER_EL0(9), 3346 PMU_PMEVTYPER_EL0(10), 3347 PMU_PMEVTYPER_EL0(11), 3348 PMU_PMEVTYPER_EL0(12), 3349 PMU_PMEVTYPER_EL0(13), 3350 PMU_PMEVTYPER_EL0(14), 3351 PMU_PMEVTYPER_EL0(15), 3352 PMU_PMEVTYPER_EL0(16), 3353 PMU_PMEVTYPER_EL0(17), 3354 PMU_PMEVTYPER_EL0(18), 3355 PMU_PMEVTYPER_EL0(19), 3356 PMU_PMEVTYPER_EL0(20), 3357 PMU_PMEVTYPER_EL0(21), 3358 PMU_PMEVTYPER_EL0(22), 3359 PMU_PMEVTYPER_EL0(23), 3360 PMU_PMEVTYPER_EL0(24), 3361 PMU_PMEVTYPER_EL0(25), 3362 PMU_PMEVTYPER_EL0(26), 3363 PMU_PMEVTYPER_EL0(27), 3364 PMU_PMEVTYPER_EL0(28), 3365 PMU_PMEVTYPER_EL0(29), 3366 PMU_PMEVTYPER_EL0(30), 3367 /* 3368 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero 3369 * in 32bit mode. Here we choose to reset it as zero for consistency. 3370 */ 3371 { PMU_SYS_REG(PMCCFILTR_EL0), .access = access_pmu_evtyper, 3372 .reset = reset_val, .reg = PMCCFILTR_EL0, .val = 0 }, 3373 3374 EL2_REG_VNCR(VPIDR_EL2, reset_unknown, 0), 3375 EL2_REG_VNCR(VMPIDR_EL2, reset_unknown, 0), 3376 EL2_REG(SCTLR_EL2, access_rw, reset_val, SCTLR_EL2_RES1), 3377 EL2_REG(ACTLR_EL2, access_rw, reset_val, 0), 3378 EL2_REG_FILTERED(SCTLR2_EL2, access_vm_reg, reset_val, 0, 3379 sctlr2_el2_visibility), 3380 EL2_REG_VNCR(HCR_EL2, reset_hcr, 0), 3381 EL2_REG(MDCR_EL2, access_mdcr, reset_mdcr, 0), 3382 EL2_REG(CPTR_EL2, access_rw, reset_val, CPTR_NVHE_EL2_RES1), 3383 EL2_REG_VNCR(HSTR_EL2, reset_val, 0), 3384 EL2_REG_VNCR_FILT(HFGRTR_EL2, fgt_visibility), 3385 EL2_REG_VNCR_FILT(HFGWTR_EL2, fgt_visibility), 3386 EL2_REG_VNCR(HFGITR_EL2, reset_val, 0), 3387 EL2_REG_VNCR(HACR_EL2, reset_val, 0), 3388 3389 EL2_REG_FILTERED(ZCR_EL2, access_zcr_el2, reset_val, 0, 3390 sve_el2_visibility), 3391 3392 EL2_REG_VNCR(HCRX_EL2, reset_val, 0), 3393 3394 EL2_REG(TTBR0_EL2, access_rw, reset_val, 0), 3395 EL2_REG(TTBR1_EL2, access_rw, reset_val, 0), 3396 EL2_REG(TCR_EL2, access_rw, reset_val, TCR_EL2_RES1), 3397 EL2_REG_FILTERED(TCR2_EL2, access_rw, reset_val, TCR2_EL2_RES1, 3398 tcr2_el2_visibility), 3399 EL2_REG_VNCR(VTTBR_EL2, reset_val, 0), 3400 EL2_REG_VNCR(VTCR_EL2, reset_val, 0), 3401 EL2_REG_FILTERED(VNCR_EL2, bad_vncr_trap, reset_val, 0, 3402 vncr_el2_visibility), 3403 3404 { SYS_DESC(SYS_DACR32_EL2), undef_access, reset_unknown, DACR32_EL2 }, 3405 EL2_REG_VNCR_FILT(HDFGRTR2_EL2, fgt2_visibility), 3406 EL2_REG_VNCR_FILT(HDFGWTR2_EL2, fgt2_visibility), 3407 EL2_REG_VNCR_FILT(HFGRTR2_EL2, fgt2_visibility), 3408 EL2_REG_VNCR_FILT(HFGWTR2_EL2, fgt2_visibility), 3409 EL2_REG_VNCR_FILT(HDFGRTR_EL2, fgt_visibility), 3410 EL2_REG_VNCR_FILT(HDFGWTR_EL2, fgt_visibility), 3411 EL2_REG_VNCR_FILT(HAFGRTR_EL2, fgt_visibility), 3412 EL2_REG_VNCR_FILT(HFGITR2_EL2, fgt2_visibility), 3413 EL2_REG_REDIR(SPSR_EL2, reset_val, 0), 3414 EL2_REG_REDIR(ELR_EL2, reset_val, 0), 3415 { SYS_DESC(SYS_SP_EL1), access_sp_el1}, 3416 3417 /* AArch32 SPSR_* are RES0 if trapped from a NV guest */ 3418 { SYS_DESC(SYS_SPSR_irq), .access = trap_raz_wi }, 3419 { SYS_DESC(SYS_SPSR_abt), .access = trap_raz_wi }, 3420 { SYS_DESC(SYS_SPSR_und), .access = trap_raz_wi }, 3421 { SYS_DESC(SYS_SPSR_fiq), .access = trap_raz_wi }, 3422 3423 { SYS_DESC(SYS_IFSR32_EL2), undef_access, reset_unknown, IFSR32_EL2 }, 3424 EL2_REG(AFSR0_EL2, access_rw, reset_val, 0), 3425 EL2_REG(AFSR1_EL2, access_rw, reset_val, 0), 3426 EL2_REG_REDIR(ESR_EL2, reset_val, 0), 3427 EL2_REG_VNCR(VSESR_EL2, reset_unknown, 0), 3428 { SYS_DESC(SYS_FPEXC32_EL2), undef_access, reset_val, FPEXC32_EL2, 0x700 }, 3429 3430 EL2_REG_REDIR(FAR_EL2, reset_val, 0), 3431 EL2_REG(HPFAR_EL2, access_rw, reset_val, 0), 3432 3433 EL2_REG(MAIR_EL2, access_rw, reset_val, 0), 3434 EL2_REG_FILTERED(PIRE0_EL2, access_rw, reset_val, 0, 3435 s1pie_el2_visibility), 3436 EL2_REG_FILTERED(PIR_EL2, access_rw, reset_val, 0, 3437 s1pie_el2_visibility), 3438 EL2_REG_FILTERED(POR_EL2, access_rw, reset_val, 0, 3439 s1poe_el2_visibility), 3440 EL2_REG(AMAIR_EL2, access_rw, reset_val, 0), 3441 { SYS_DESC(SYS_MPAMHCR_EL2), undef_access }, 3442 { SYS_DESC(SYS_MPAMVPMV_EL2), undef_access }, 3443 { SYS_DESC(SYS_MPAM2_EL2), undef_access }, 3444 { SYS_DESC(SYS_MPAMVPM0_EL2), undef_access }, 3445 { SYS_DESC(SYS_MPAMVPM1_EL2), undef_access }, 3446 { SYS_DESC(SYS_MPAMVPM2_EL2), undef_access }, 3447 { SYS_DESC(SYS_MPAMVPM3_EL2), undef_access }, 3448 { SYS_DESC(SYS_MPAMVPM4_EL2), undef_access }, 3449 { SYS_DESC(SYS_MPAMVPM5_EL2), undef_access }, 3450 { SYS_DESC(SYS_MPAMVPM6_EL2), undef_access }, 3451 { SYS_DESC(SYS_MPAMVPM7_EL2), undef_access }, 3452 3453 EL2_REG(VBAR_EL2, access_rw, reset_val, 0), 3454 { SYS_DESC(SYS_RVBAR_EL2), undef_access }, 3455 { SYS_DESC(SYS_RMR_EL2), undef_access }, 3456 EL2_REG_VNCR(VDISR_EL2, reset_unknown, 0), 3457 3458 EL2_REG_VNCR_GICv3(ICH_AP0R0_EL2), 3459 EL2_REG_VNCR_GICv3(ICH_AP0R1_EL2), 3460 EL2_REG_VNCR_GICv3(ICH_AP0R2_EL2), 3461 EL2_REG_VNCR_GICv3(ICH_AP0R3_EL2), 3462 EL2_REG_VNCR_GICv3(ICH_AP1R0_EL2), 3463 EL2_REG_VNCR_GICv3(ICH_AP1R1_EL2), 3464 EL2_REG_VNCR_GICv3(ICH_AP1R2_EL2), 3465 EL2_REG_VNCR_GICv3(ICH_AP1R3_EL2), 3466 3467 { SYS_DESC(SYS_ICC_SRE_EL2), access_gic_sre }, 3468 3469 EL2_REG_VNCR_GICv3(ICH_HCR_EL2), 3470 { SYS_DESC(SYS_ICH_VTR_EL2), access_gic_vtr }, 3471 { SYS_DESC(SYS_ICH_MISR_EL2), access_gic_misr }, 3472 { SYS_DESC(SYS_ICH_EISR_EL2), access_gic_eisr }, 3473 { SYS_DESC(SYS_ICH_ELRSR_EL2), access_gic_elrsr }, 3474 EL2_REG_VNCR_GICv3(ICH_VMCR_EL2), 3475 3476 EL2_REG_VNCR_GICv3(ICH_LR0_EL2), 3477 EL2_REG_VNCR_GICv3(ICH_LR1_EL2), 3478 EL2_REG_VNCR_GICv3(ICH_LR2_EL2), 3479 EL2_REG_VNCR_GICv3(ICH_LR3_EL2), 3480 EL2_REG_VNCR_GICv3(ICH_LR4_EL2), 3481 EL2_REG_VNCR_GICv3(ICH_LR5_EL2), 3482 EL2_REG_VNCR_GICv3(ICH_LR6_EL2), 3483 EL2_REG_VNCR_GICv3(ICH_LR7_EL2), 3484 EL2_REG_VNCR_GICv3(ICH_LR8_EL2), 3485 EL2_REG_VNCR_GICv3(ICH_LR9_EL2), 3486 EL2_REG_VNCR_GICv3(ICH_LR10_EL2), 3487 EL2_REG_VNCR_GICv3(ICH_LR11_EL2), 3488 EL2_REG_VNCR_GICv3(ICH_LR12_EL2), 3489 EL2_REG_VNCR_GICv3(ICH_LR13_EL2), 3490 EL2_REG_VNCR_GICv3(ICH_LR14_EL2), 3491 EL2_REG_VNCR_GICv3(ICH_LR15_EL2), 3492 3493 EL2_REG(CONTEXTIDR_EL2, access_rw, reset_val, 0), 3494 EL2_REG(TPIDR_EL2, access_rw, reset_val, 0), 3495 3496 EL2_REG_VNCR(CNTVOFF_EL2, reset_val, 0), 3497 EL2_REG(CNTHCTL_EL2, access_rw, reset_val, 0), 3498 { SYS_DESC(SYS_CNTHP_TVAL_EL2), access_arch_timer }, 3499 EL2_REG(CNTHP_CTL_EL2, access_arch_timer, reset_val, 0), 3500 EL2_REG(CNTHP_CVAL_EL2, access_arch_timer, reset_val, 0), 3501 3502 { SYS_DESC(SYS_CNTHV_TVAL_EL2), access_hv_timer }, 3503 EL2_REG(CNTHV_CTL_EL2, access_hv_timer, reset_val, 0), 3504 EL2_REG(CNTHV_CVAL_EL2, access_hv_timer, reset_val, 0), 3505 3506 { SYS_DESC(SYS_CNTKCTL_EL12), access_cntkctl_el12 }, 3507 3508 { SYS_DESC(SYS_CNTP_TVAL_EL02), access_arch_timer }, 3509 { SYS_DESC(SYS_CNTP_CTL_EL02), access_arch_timer }, 3510 { SYS_DESC(SYS_CNTP_CVAL_EL02), access_arch_timer }, 3511 3512 { SYS_DESC(SYS_CNTV_TVAL_EL02), access_arch_timer }, 3513 { SYS_DESC(SYS_CNTV_CTL_EL02), access_arch_timer }, 3514 { SYS_DESC(SYS_CNTV_CVAL_EL02), access_arch_timer }, 3515 3516 EL2_REG(SP_EL2, NULL, reset_unknown, 0), 3517 }; 3518 3519 static bool handle_at_s1e01(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3520 const struct sys_reg_desc *r) 3521 { 3522 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3523 3524 __kvm_at_s1e01(vcpu, op, p->regval); 3525 3526 return true; 3527 } 3528 3529 static bool handle_at_s1e2(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3530 const struct sys_reg_desc *r) 3531 { 3532 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3533 3534 /* There is no FGT associated with AT S1E2A :-( */ 3535 if (op == OP_AT_S1E2A && 3536 !kvm_has_feat(vcpu->kvm, ID_AA64ISAR2_EL1, ATS1A, IMP)) { 3537 kvm_inject_undefined(vcpu); 3538 return false; 3539 } 3540 3541 __kvm_at_s1e2(vcpu, op, p->regval); 3542 3543 return true; 3544 } 3545 3546 static bool handle_at_s12(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3547 const struct sys_reg_desc *r) 3548 { 3549 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3550 3551 __kvm_at_s12(vcpu, op, p->regval); 3552 3553 return true; 3554 } 3555 3556 static bool kvm_supported_tlbi_s12_op(struct kvm_vcpu *vpcu, u32 instr) 3557 { 3558 struct kvm *kvm = vpcu->kvm; 3559 u8 CRm = sys_reg_CRm(instr); 3560 3561 if (sys_reg_CRn(instr) == TLBI_CRn_nXS && 3562 !kvm_has_feat(kvm, ID_AA64ISAR1_EL1, XS, IMP)) 3563 return false; 3564 3565 if (CRm == TLBI_CRm_nROS && 3566 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 3567 return false; 3568 3569 return true; 3570 } 3571 3572 static bool handle_alle1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3573 const struct sys_reg_desc *r) 3574 { 3575 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3576 3577 if (!kvm_supported_tlbi_s12_op(vcpu, sys_encoding)) 3578 return undef_access(vcpu, p, r); 3579 3580 write_lock(&vcpu->kvm->mmu_lock); 3581 3582 /* 3583 * Drop all shadow S2s, resulting in S1/S2 TLBIs for each of the 3584 * corresponding VMIDs. 3585 */ 3586 kvm_nested_s2_unmap(vcpu->kvm, true); 3587 3588 write_unlock(&vcpu->kvm->mmu_lock); 3589 3590 return true; 3591 } 3592 3593 static bool kvm_supported_tlbi_ipas2_op(struct kvm_vcpu *vpcu, u32 instr) 3594 { 3595 struct kvm *kvm = vpcu->kvm; 3596 u8 CRm = sys_reg_CRm(instr); 3597 u8 Op2 = sys_reg_Op2(instr); 3598 3599 if (sys_reg_CRn(instr) == TLBI_CRn_nXS && 3600 !kvm_has_feat(kvm, ID_AA64ISAR1_EL1, XS, IMP)) 3601 return false; 3602 3603 if (CRm == TLBI_CRm_IPAIS && (Op2 == 2 || Op2 == 6) && 3604 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE)) 3605 return false; 3606 3607 if (CRm == TLBI_CRm_IPAONS && (Op2 == 0 || Op2 == 4) && 3608 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 3609 return false; 3610 3611 if (CRm == TLBI_CRm_IPAONS && (Op2 == 3 || Op2 == 7) && 3612 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE)) 3613 return false; 3614 3615 return true; 3616 } 3617 3618 /* Only defined here as this is an internal "abstraction" */ 3619 union tlbi_info { 3620 struct { 3621 u64 start; 3622 u64 size; 3623 } range; 3624 3625 struct { 3626 u64 addr; 3627 } ipa; 3628 3629 struct { 3630 u64 addr; 3631 u32 encoding; 3632 } va; 3633 }; 3634 3635 static void s2_mmu_unmap_range(struct kvm_s2_mmu *mmu, 3636 const union tlbi_info *info) 3637 { 3638 /* 3639 * The unmap operation is allowed to drop the MMU lock and block, which 3640 * means that @mmu could be used for a different context than the one 3641 * currently being invalidated. 3642 * 3643 * This behavior is still safe, as: 3644 * 3645 * 1) The vCPU(s) that recycled the MMU are responsible for invalidating 3646 * the entire MMU before reusing it, which still honors the intent 3647 * of a TLBI. 3648 * 3649 * 2) Until the guest TLBI instruction is 'retired' (i.e. increment PC 3650 * and ERET to the guest), other vCPUs are allowed to use stale 3651 * translations. 3652 * 3653 * 3) Accidentally unmapping an unrelated MMU context is nonfatal, and 3654 * at worst may cause more aborts for shadow stage-2 fills. 3655 * 3656 * Dropping the MMU lock also implies that shadow stage-2 fills could 3657 * happen behind the back of the TLBI. This is still safe, though, as 3658 * the L1 needs to put its stage-2 in a consistent state before doing 3659 * the TLBI. 3660 */ 3661 kvm_stage2_unmap_range(mmu, info->range.start, info->range.size, true); 3662 } 3663 3664 static bool handle_vmalls12e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3665 const struct sys_reg_desc *r) 3666 { 3667 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3668 u64 limit, vttbr; 3669 3670 if (!kvm_supported_tlbi_s12_op(vcpu, sys_encoding)) 3671 return undef_access(vcpu, p, r); 3672 3673 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 3674 limit = BIT_ULL(kvm_get_pa_bits(vcpu->kvm)); 3675 3676 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 3677 &(union tlbi_info) { 3678 .range = { 3679 .start = 0, 3680 .size = limit, 3681 }, 3682 }, 3683 s2_mmu_unmap_range); 3684 3685 return true; 3686 } 3687 3688 static bool handle_ripas2e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3689 const struct sys_reg_desc *r) 3690 { 3691 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3692 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 3693 u64 base, range; 3694 3695 if (!kvm_supported_tlbi_ipas2_op(vcpu, sys_encoding)) 3696 return undef_access(vcpu, p, r); 3697 3698 /* 3699 * Because the shadow S2 structure doesn't necessarily reflect that 3700 * of the guest's S2 (different base granule size, for example), we 3701 * decide to ignore TTL and only use the described range. 3702 */ 3703 base = decode_range_tlbi(p->regval, &range, NULL); 3704 3705 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 3706 &(union tlbi_info) { 3707 .range = { 3708 .start = base, 3709 .size = range, 3710 }, 3711 }, 3712 s2_mmu_unmap_range); 3713 3714 return true; 3715 } 3716 3717 static void s2_mmu_unmap_ipa(struct kvm_s2_mmu *mmu, 3718 const union tlbi_info *info) 3719 { 3720 unsigned long max_size; 3721 u64 base_addr; 3722 3723 /* 3724 * We drop a number of things from the supplied value: 3725 * 3726 * - NS bit: we're non-secure only. 3727 * 3728 * - IPA[51:48]: We don't support 52bit IPA just yet... 3729 * 3730 * And of course, adjust the IPA to be on an actual address. 3731 */ 3732 base_addr = (info->ipa.addr & GENMASK_ULL(35, 0)) << 12; 3733 max_size = compute_tlb_inval_range(mmu, info->ipa.addr); 3734 base_addr &= ~(max_size - 1); 3735 3736 /* 3737 * See comment in s2_mmu_unmap_range() for why this is allowed to 3738 * reschedule. 3739 */ 3740 kvm_stage2_unmap_range(mmu, base_addr, max_size, true); 3741 } 3742 3743 static bool handle_ipas2e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3744 const struct sys_reg_desc *r) 3745 { 3746 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3747 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 3748 3749 if (!kvm_supported_tlbi_ipas2_op(vcpu, sys_encoding)) 3750 return undef_access(vcpu, p, r); 3751 3752 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 3753 &(union tlbi_info) { 3754 .ipa = { 3755 .addr = p->regval, 3756 }, 3757 }, 3758 s2_mmu_unmap_ipa); 3759 3760 return true; 3761 } 3762 3763 static void s2_mmu_tlbi_s1e1(struct kvm_s2_mmu *mmu, 3764 const union tlbi_info *info) 3765 { 3766 WARN_ON(__kvm_tlbi_s1e2(mmu, info->va.addr, info->va.encoding)); 3767 } 3768 3769 static bool handle_tlbi_el2(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3770 const struct sys_reg_desc *r) 3771 { 3772 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3773 3774 if (!kvm_supported_tlbi_s1e2_op(vcpu, sys_encoding)) 3775 return undef_access(vcpu, p, r); 3776 3777 kvm_handle_s1e2_tlbi(vcpu, sys_encoding, p->regval); 3778 return true; 3779 } 3780 3781 static bool handle_tlbi_el1(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3782 const struct sys_reg_desc *r) 3783 { 3784 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3785 3786 /* 3787 * If we're here, this is because we've trapped on a EL1 TLBI 3788 * instruction that affects the EL1 translation regime while 3789 * we're running in a context that doesn't allow us to let the 3790 * HW do its thing (aka vEL2): 3791 * 3792 * - HCR_EL2.E2H == 0 : a non-VHE guest 3793 * - HCR_EL2.{E2H,TGE} == { 1, 0 } : a VHE guest in guest mode 3794 * 3795 * Another possibility is that we are invalidating the EL2 context 3796 * using EL1 instructions, but that we landed here because we need 3797 * additional invalidation for structures that are not held in the 3798 * CPU TLBs (such as the VNCR pseudo-TLB and its EL2 mapping). In 3799 * that case, we are guaranteed that HCR_EL2.{E2H,TGE} == { 1, 1 } 3800 * as we don't allow an NV-capable L1 in a nVHE configuration. 3801 * 3802 * We don't expect these helpers to ever be called when running 3803 * in a vEL1 context. 3804 */ 3805 3806 WARN_ON(!vcpu_is_el2(vcpu)); 3807 3808 if (!kvm_supported_tlbi_s1e1_op(vcpu, sys_encoding)) 3809 return undef_access(vcpu, p, r); 3810 3811 if (vcpu_el2_e2h_is_set(vcpu) && vcpu_el2_tge_is_set(vcpu)) { 3812 kvm_handle_s1e2_tlbi(vcpu, sys_encoding, p->regval); 3813 return true; 3814 } 3815 3816 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, 3817 get_vmid(__vcpu_sys_reg(vcpu, VTTBR_EL2)), 3818 &(union tlbi_info) { 3819 .va = { 3820 .addr = p->regval, 3821 .encoding = sys_encoding, 3822 }, 3823 }, 3824 s2_mmu_tlbi_s1e1); 3825 3826 return true; 3827 } 3828 3829 #define SYS_INSN(insn, access_fn) \ 3830 { \ 3831 SYS_DESC(OP_##insn), \ 3832 .access = (access_fn), \ 3833 } 3834 3835 static struct sys_reg_desc sys_insn_descs[] = { 3836 { SYS_DESC(SYS_DC_ISW), access_dcsw }, 3837 { SYS_DESC(SYS_DC_IGSW), access_dcgsw }, 3838 { SYS_DESC(SYS_DC_IGDSW), access_dcgsw }, 3839 3840 SYS_INSN(AT_S1E1R, handle_at_s1e01), 3841 SYS_INSN(AT_S1E1W, handle_at_s1e01), 3842 SYS_INSN(AT_S1E0R, handle_at_s1e01), 3843 SYS_INSN(AT_S1E0W, handle_at_s1e01), 3844 SYS_INSN(AT_S1E1RP, handle_at_s1e01), 3845 SYS_INSN(AT_S1E1WP, handle_at_s1e01), 3846 3847 { SYS_DESC(SYS_DC_CSW), access_dcsw }, 3848 { SYS_DESC(SYS_DC_CGSW), access_dcgsw }, 3849 { SYS_DESC(SYS_DC_CGDSW), access_dcgsw }, 3850 { SYS_DESC(SYS_DC_CISW), access_dcsw }, 3851 { SYS_DESC(SYS_DC_CIGSW), access_dcgsw }, 3852 { SYS_DESC(SYS_DC_CIGDSW), access_dcgsw }, 3853 3854 SYS_INSN(TLBI_VMALLE1OS, handle_tlbi_el1), 3855 SYS_INSN(TLBI_VAE1OS, handle_tlbi_el1), 3856 SYS_INSN(TLBI_ASIDE1OS, handle_tlbi_el1), 3857 SYS_INSN(TLBI_VAAE1OS, handle_tlbi_el1), 3858 SYS_INSN(TLBI_VALE1OS, handle_tlbi_el1), 3859 SYS_INSN(TLBI_VAALE1OS, handle_tlbi_el1), 3860 3861 SYS_INSN(TLBI_RVAE1IS, handle_tlbi_el1), 3862 SYS_INSN(TLBI_RVAAE1IS, handle_tlbi_el1), 3863 SYS_INSN(TLBI_RVALE1IS, handle_tlbi_el1), 3864 SYS_INSN(TLBI_RVAALE1IS, handle_tlbi_el1), 3865 3866 SYS_INSN(TLBI_VMALLE1IS, handle_tlbi_el1), 3867 SYS_INSN(TLBI_VAE1IS, handle_tlbi_el1), 3868 SYS_INSN(TLBI_ASIDE1IS, handle_tlbi_el1), 3869 SYS_INSN(TLBI_VAAE1IS, handle_tlbi_el1), 3870 SYS_INSN(TLBI_VALE1IS, handle_tlbi_el1), 3871 SYS_INSN(TLBI_VAALE1IS, handle_tlbi_el1), 3872 3873 SYS_INSN(TLBI_RVAE1OS, handle_tlbi_el1), 3874 SYS_INSN(TLBI_RVAAE1OS, handle_tlbi_el1), 3875 SYS_INSN(TLBI_RVALE1OS, handle_tlbi_el1), 3876 SYS_INSN(TLBI_RVAALE1OS, handle_tlbi_el1), 3877 3878 SYS_INSN(TLBI_RVAE1, handle_tlbi_el1), 3879 SYS_INSN(TLBI_RVAAE1, handle_tlbi_el1), 3880 SYS_INSN(TLBI_RVALE1, handle_tlbi_el1), 3881 SYS_INSN(TLBI_RVAALE1, handle_tlbi_el1), 3882 3883 SYS_INSN(TLBI_VMALLE1, handle_tlbi_el1), 3884 SYS_INSN(TLBI_VAE1, handle_tlbi_el1), 3885 SYS_INSN(TLBI_ASIDE1, handle_tlbi_el1), 3886 SYS_INSN(TLBI_VAAE1, handle_tlbi_el1), 3887 SYS_INSN(TLBI_VALE1, handle_tlbi_el1), 3888 SYS_INSN(TLBI_VAALE1, handle_tlbi_el1), 3889 3890 SYS_INSN(TLBI_VMALLE1OSNXS, handle_tlbi_el1), 3891 SYS_INSN(TLBI_VAE1OSNXS, handle_tlbi_el1), 3892 SYS_INSN(TLBI_ASIDE1OSNXS, handle_tlbi_el1), 3893 SYS_INSN(TLBI_VAAE1OSNXS, handle_tlbi_el1), 3894 SYS_INSN(TLBI_VALE1OSNXS, handle_tlbi_el1), 3895 SYS_INSN(TLBI_VAALE1OSNXS, handle_tlbi_el1), 3896 3897 SYS_INSN(TLBI_RVAE1ISNXS, handle_tlbi_el1), 3898 SYS_INSN(TLBI_RVAAE1ISNXS, handle_tlbi_el1), 3899 SYS_INSN(TLBI_RVALE1ISNXS, handle_tlbi_el1), 3900 SYS_INSN(TLBI_RVAALE1ISNXS, handle_tlbi_el1), 3901 3902 SYS_INSN(TLBI_VMALLE1ISNXS, handle_tlbi_el1), 3903 SYS_INSN(TLBI_VAE1ISNXS, handle_tlbi_el1), 3904 SYS_INSN(TLBI_ASIDE1ISNXS, handle_tlbi_el1), 3905 SYS_INSN(TLBI_VAAE1ISNXS, handle_tlbi_el1), 3906 SYS_INSN(TLBI_VALE1ISNXS, handle_tlbi_el1), 3907 SYS_INSN(TLBI_VAALE1ISNXS, handle_tlbi_el1), 3908 3909 SYS_INSN(TLBI_RVAE1OSNXS, handle_tlbi_el1), 3910 SYS_INSN(TLBI_RVAAE1OSNXS, handle_tlbi_el1), 3911 SYS_INSN(TLBI_RVALE1OSNXS, handle_tlbi_el1), 3912 SYS_INSN(TLBI_RVAALE1OSNXS, handle_tlbi_el1), 3913 3914 SYS_INSN(TLBI_RVAE1NXS, handle_tlbi_el1), 3915 SYS_INSN(TLBI_RVAAE1NXS, handle_tlbi_el1), 3916 SYS_INSN(TLBI_RVALE1NXS, handle_tlbi_el1), 3917 SYS_INSN(TLBI_RVAALE1NXS, handle_tlbi_el1), 3918 3919 SYS_INSN(TLBI_VMALLE1NXS, handle_tlbi_el1), 3920 SYS_INSN(TLBI_VAE1NXS, handle_tlbi_el1), 3921 SYS_INSN(TLBI_ASIDE1NXS, handle_tlbi_el1), 3922 SYS_INSN(TLBI_VAAE1NXS, handle_tlbi_el1), 3923 SYS_INSN(TLBI_VALE1NXS, handle_tlbi_el1), 3924 SYS_INSN(TLBI_VAALE1NXS, handle_tlbi_el1), 3925 3926 SYS_INSN(AT_S1E2R, handle_at_s1e2), 3927 SYS_INSN(AT_S1E2W, handle_at_s1e2), 3928 SYS_INSN(AT_S12E1R, handle_at_s12), 3929 SYS_INSN(AT_S12E1W, handle_at_s12), 3930 SYS_INSN(AT_S12E0R, handle_at_s12), 3931 SYS_INSN(AT_S12E0W, handle_at_s12), 3932 SYS_INSN(AT_S1E2A, handle_at_s1e2), 3933 3934 SYS_INSN(TLBI_IPAS2E1IS, handle_ipas2e1is), 3935 SYS_INSN(TLBI_RIPAS2E1IS, handle_ripas2e1is), 3936 SYS_INSN(TLBI_IPAS2LE1IS, handle_ipas2e1is), 3937 SYS_INSN(TLBI_RIPAS2LE1IS, handle_ripas2e1is), 3938 3939 SYS_INSN(TLBI_ALLE2OS, handle_tlbi_el2), 3940 SYS_INSN(TLBI_VAE2OS, handle_tlbi_el2), 3941 SYS_INSN(TLBI_ALLE1OS, handle_alle1is), 3942 SYS_INSN(TLBI_VALE2OS, handle_tlbi_el2), 3943 SYS_INSN(TLBI_VMALLS12E1OS, handle_vmalls12e1is), 3944 3945 SYS_INSN(TLBI_RVAE2IS, handle_tlbi_el2), 3946 SYS_INSN(TLBI_RVALE2IS, handle_tlbi_el2), 3947 SYS_INSN(TLBI_ALLE2IS, handle_tlbi_el2), 3948 SYS_INSN(TLBI_VAE2IS, handle_tlbi_el2), 3949 3950 SYS_INSN(TLBI_ALLE1IS, handle_alle1is), 3951 3952 SYS_INSN(TLBI_VALE2IS, handle_tlbi_el2), 3953 3954 SYS_INSN(TLBI_VMALLS12E1IS, handle_vmalls12e1is), 3955 SYS_INSN(TLBI_IPAS2E1OS, handle_ipas2e1is), 3956 SYS_INSN(TLBI_IPAS2E1, handle_ipas2e1is), 3957 SYS_INSN(TLBI_RIPAS2E1, handle_ripas2e1is), 3958 SYS_INSN(TLBI_RIPAS2E1OS, handle_ripas2e1is), 3959 SYS_INSN(TLBI_IPAS2LE1OS, handle_ipas2e1is), 3960 SYS_INSN(TLBI_IPAS2LE1, handle_ipas2e1is), 3961 SYS_INSN(TLBI_RIPAS2LE1, handle_ripas2e1is), 3962 SYS_INSN(TLBI_RIPAS2LE1OS, handle_ripas2e1is), 3963 SYS_INSN(TLBI_RVAE2OS, handle_tlbi_el2), 3964 SYS_INSN(TLBI_RVALE2OS, handle_tlbi_el2), 3965 SYS_INSN(TLBI_RVAE2, handle_tlbi_el2), 3966 SYS_INSN(TLBI_RVALE2, handle_tlbi_el2), 3967 SYS_INSN(TLBI_ALLE2, handle_tlbi_el2), 3968 SYS_INSN(TLBI_VAE2, handle_tlbi_el2), 3969 3970 SYS_INSN(TLBI_ALLE1, handle_alle1is), 3971 3972 SYS_INSN(TLBI_VALE2, handle_tlbi_el2), 3973 3974 SYS_INSN(TLBI_VMALLS12E1, handle_vmalls12e1is), 3975 3976 SYS_INSN(TLBI_IPAS2E1ISNXS, handle_ipas2e1is), 3977 SYS_INSN(TLBI_RIPAS2E1ISNXS, handle_ripas2e1is), 3978 SYS_INSN(TLBI_IPAS2LE1ISNXS, handle_ipas2e1is), 3979 SYS_INSN(TLBI_RIPAS2LE1ISNXS, handle_ripas2e1is), 3980 3981 SYS_INSN(TLBI_ALLE2OSNXS, handle_tlbi_el2), 3982 SYS_INSN(TLBI_VAE2OSNXS, handle_tlbi_el2), 3983 SYS_INSN(TLBI_ALLE1OSNXS, handle_alle1is), 3984 SYS_INSN(TLBI_VALE2OSNXS, handle_tlbi_el2), 3985 SYS_INSN(TLBI_VMALLS12E1OSNXS, handle_vmalls12e1is), 3986 3987 SYS_INSN(TLBI_RVAE2ISNXS, handle_tlbi_el2), 3988 SYS_INSN(TLBI_RVALE2ISNXS, handle_tlbi_el2), 3989 SYS_INSN(TLBI_ALLE2ISNXS, handle_tlbi_el2), 3990 SYS_INSN(TLBI_VAE2ISNXS, handle_tlbi_el2), 3991 3992 SYS_INSN(TLBI_ALLE1ISNXS, handle_alle1is), 3993 SYS_INSN(TLBI_VALE2ISNXS, handle_tlbi_el2), 3994 SYS_INSN(TLBI_VMALLS12E1ISNXS, handle_vmalls12e1is), 3995 SYS_INSN(TLBI_IPAS2E1OSNXS, handle_ipas2e1is), 3996 SYS_INSN(TLBI_IPAS2E1NXS, handle_ipas2e1is), 3997 SYS_INSN(TLBI_RIPAS2E1NXS, handle_ripas2e1is), 3998 SYS_INSN(TLBI_RIPAS2E1OSNXS, handle_ripas2e1is), 3999 SYS_INSN(TLBI_IPAS2LE1OSNXS, handle_ipas2e1is), 4000 SYS_INSN(TLBI_IPAS2LE1NXS, handle_ipas2e1is), 4001 SYS_INSN(TLBI_RIPAS2LE1NXS, handle_ripas2e1is), 4002 SYS_INSN(TLBI_RIPAS2LE1OSNXS, handle_ripas2e1is), 4003 SYS_INSN(TLBI_RVAE2OSNXS, handle_tlbi_el2), 4004 SYS_INSN(TLBI_RVALE2OSNXS, handle_tlbi_el2), 4005 SYS_INSN(TLBI_RVAE2NXS, handle_tlbi_el2), 4006 SYS_INSN(TLBI_RVALE2NXS, handle_tlbi_el2), 4007 SYS_INSN(TLBI_ALLE2NXS, handle_tlbi_el2), 4008 SYS_INSN(TLBI_VAE2NXS, handle_tlbi_el2), 4009 SYS_INSN(TLBI_ALLE1NXS, handle_alle1is), 4010 SYS_INSN(TLBI_VALE2NXS, handle_tlbi_el2), 4011 SYS_INSN(TLBI_VMALLS12E1NXS, handle_vmalls12e1is), 4012 }; 4013 4014 static bool trap_dbgdidr(struct kvm_vcpu *vcpu, 4015 struct sys_reg_params *p, 4016 const struct sys_reg_desc *r) 4017 { 4018 if (p->is_write) { 4019 return ignore_write(vcpu, p); 4020 } else { 4021 u64 dfr = kvm_read_vm_id_reg(vcpu->kvm, SYS_ID_AA64DFR0_EL1); 4022 u32 el3 = kvm_has_feat(vcpu->kvm, ID_AA64PFR0_EL1, EL3, IMP); 4023 4024 p->regval = ((SYS_FIELD_GET(ID_AA64DFR0_EL1, WRPs, dfr) << 28) | 4025 (SYS_FIELD_GET(ID_AA64DFR0_EL1, BRPs, dfr) << 24) | 4026 (SYS_FIELD_GET(ID_AA64DFR0_EL1, CTX_CMPs, dfr) << 20) | 4027 (SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, dfr) << 16) | 4028 (1 << 15) | (el3 << 14) | (el3 << 12)); 4029 return true; 4030 } 4031 } 4032 4033 /* 4034 * AArch32 debug register mappings 4035 * 4036 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0] 4037 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32] 4038 * 4039 * None of the other registers share their location, so treat them as 4040 * if they were 64bit. 4041 */ 4042 #define DBG_BCR_BVR_WCR_WVR(n) \ 4043 /* DBGBVRn */ \ 4044 { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), \ 4045 trap_dbg_wb_reg, NULL, n }, \ 4046 /* DBGBCRn */ \ 4047 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_dbg_wb_reg, NULL, n }, \ 4048 /* DBGWVRn */ \ 4049 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_dbg_wb_reg, NULL, n }, \ 4050 /* DBGWCRn */ \ 4051 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_dbg_wb_reg, NULL, n } 4052 4053 #define DBGBXVR(n) \ 4054 { AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), \ 4055 trap_dbg_wb_reg, NULL, n } 4056 4057 /* 4058 * Trapped cp14 registers. We generally ignore most of the external 4059 * debug, on the principle that they don't really make sense to a 4060 * guest. Revisit this one day, would this principle change. 4061 */ 4062 static const struct sys_reg_desc cp14_regs[] = { 4063 /* DBGDIDR */ 4064 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgdidr }, 4065 /* DBGDTRRXext */ 4066 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi }, 4067 4068 DBG_BCR_BVR_WCR_WVR(0), 4069 /* DBGDSCRint */ 4070 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi }, 4071 DBG_BCR_BVR_WCR_WVR(1), 4072 /* DBGDCCINT */ 4073 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug_regs, NULL, MDCCINT_EL1 }, 4074 /* DBGDSCRext */ 4075 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug_regs, NULL, MDSCR_EL1 }, 4076 DBG_BCR_BVR_WCR_WVR(2), 4077 /* DBGDTR[RT]Xint */ 4078 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi }, 4079 /* DBGDTR[RT]Xext */ 4080 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi }, 4081 DBG_BCR_BVR_WCR_WVR(3), 4082 DBG_BCR_BVR_WCR_WVR(4), 4083 DBG_BCR_BVR_WCR_WVR(5), 4084 /* DBGWFAR */ 4085 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi }, 4086 /* DBGOSECCR */ 4087 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi }, 4088 DBG_BCR_BVR_WCR_WVR(6), 4089 /* DBGVCR */ 4090 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug_regs, NULL, DBGVCR32_EL2 }, 4091 DBG_BCR_BVR_WCR_WVR(7), 4092 DBG_BCR_BVR_WCR_WVR(8), 4093 DBG_BCR_BVR_WCR_WVR(9), 4094 DBG_BCR_BVR_WCR_WVR(10), 4095 DBG_BCR_BVR_WCR_WVR(11), 4096 DBG_BCR_BVR_WCR_WVR(12), 4097 DBG_BCR_BVR_WCR_WVR(13), 4098 DBG_BCR_BVR_WCR_WVR(14), 4099 DBG_BCR_BVR_WCR_WVR(15), 4100 4101 /* DBGDRAR (32bit) */ 4102 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi }, 4103 4104 DBGBXVR(0), 4105 /* DBGOSLAR */ 4106 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_oslar_el1 }, 4107 DBGBXVR(1), 4108 /* DBGOSLSR */ 4109 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1, NULL, OSLSR_EL1 }, 4110 DBGBXVR(2), 4111 DBGBXVR(3), 4112 /* DBGOSDLR */ 4113 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi }, 4114 DBGBXVR(4), 4115 /* DBGPRCR */ 4116 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi }, 4117 DBGBXVR(5), 4118 DBGBXVR(6), 4119 DBGBXVR(7), 4120 DBGBXVR(8), 4121 DBGBXVR(9), 4122 DBGBXVR(10), 4123 DBGBXVR(11), 4124 DBGBXVR(12), 4125 DBGBXVR(13), 4126 DBGBXVR(14), 4127 DBGBXVR(15), 4128 4129 /* DBGDSAR (32bit) */ 4130 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi }, 4131 4132 /* DBGDEVID2 */ 4133 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi }, 4134 /* DBGDEVID1 */ 4135 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi }, 4136 /* DBGDEVID */ 4137 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi }, 4138 /* DBGCLAIMSET */ 4139 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi }, 4140 /* DBGCLAIMCLR */ 4141 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi }, 4142 /* DBGAUTHSTATUS */ 4143 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 }, 4144 }; 4145 4146 /* Trapped cp14 64bit registers */ 4147 static const struct sys_reg_desc cp14_64_regs[] = { 4148 /* DBGDRAR (64bit) */ 4149 { Op1( 0), CRm( 1), .access = trap_raz_wi }, 4150 4151 /* DBGDSAR (64bit) */ 4152 { Op1( 0), CRm( 2), .access = trap_raz_wi }, 4153 }; 4154 4155 #define CP15_PMU_SYS_REG(_map, _Op1, _CRn, _CRm, _Op2) \ 4156 AA32(_map), \ 4157 Op1(_Op1), CRn(_CRn), CRm(_CRm), Op2(_Op2), \ 4158 .visibility = pmu_visibility 4159 4160 /* Macro to expand the PMEVCNTRn register */ 4161 #define PMU_PMEVCNTR(n) \ 4162 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \ 4163 (0b1000 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \ 4164 .access = access_pmu_evcntr } 4165 4166 /* Macro to expand the PMEVTYPERn register */ 4167 #define PMU_PMEVTYPER(n) \ 4168 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \ 4169 (0b1100 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \ 4170 .access = access_pmu_evtyper } 4171 /* 4172 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding, 4173 * depending on the way they are accessed (as a 32bit or a 64bit 4174 * register). 4175 */ 4176 static const struct sys_reg_desc cp15_regs[] = { 4177 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr }, 4178 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, SCTLR_EL1 }, 4179 /* ACTLR */ 4180 { AA32(LO), Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr, NULL, ACTLR_EL1 }, 4181 /* ACTLR2 */ 4182 { AA32(HI), Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr, NULL, ACTLR_EL1 }, 4183 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, 4184 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, TTBR1_EL1 }, 4185 /* TTBCR */ 4186 { AA32(LO), Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 }, 4187 /* TTBCR2 */ 4188 { AA32(HI), Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, TCR_EL1 }, 4189 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, DACR32_EL2 }, 4190 { CP15_SYS_DESC(SYS_ICC_PMR_EL1), undef_access }, 4191 /* DFSR */ 4192 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, ESR_EL1 }, 4193 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, IFSR32_EL2 }, 4194 /* ADFSR */ 4195 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, AFSR0_EL1 }, 4196 /* AIFSR */ 4197 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, AFSR1_EL1 }, 4198 /* DFAR */ 4199 { AA32(LO), Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, FAR_EL1 }, 4200 /* IFAR */ 4201 { AA32(HI), Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, FAR_EL1 }, 4202 4203 /* 4204 * DC{C,I,CI}SW operations: 4205 */ 4206 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw }, 4207 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw }, 4208 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw }, 4209 4210 /* PMU */ 4211 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 0), .access = access_pmcr }, 4212 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 1), .access = access_pmcnten }, 4213 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 2), .access = access_pmcnten }, 4214 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 3), .access = access_pmovs }, 4215 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 4), .access = access_pmswinc }, 4216 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 5), .access = access_pmselr }, 4217 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 6), .access = access_pmceid }, 4218 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 7), .access = access_pmceid }, 4219 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 0), .access = access_pmu_evcntr }, 4220 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 1), .access = access_pmu_evtyper }, 4221 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 2), .access = access_pmu_evcntr }, 4222 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 0), .access = access_pmuserenr }, 4223 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 1), .access = access_pminten }, 4224 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 2), .access = access_pminten }, 4225 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 3), .access = access_pmovs }, 4226 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 4), .access = access_pmceid }, 4227 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 5), .access = access_pmceid }, 4228 /* PMMIR */ 4229 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 6), .access = trap_raz_wi }, 4230 4231 /* PRRR/MAIR0 */ 4232 { AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 }, 4233 /* NMRR/MAIR1 */ 4234 { AA32(HI), Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, MAIR_EL1 }, 4235 /* AMAIR0 */ 4236 { AA32(LO), Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, AMAIR_EL1 }, 4237 /* AMAIR1 */ 4238 { AA32(HI), Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, AMAIR_EL1 }, 4239 4240 { CP15_SYS_DESC(SYS_ICC_IAR0_EL1), undef_access }, 4241 { CP15_SYS_DESC(SYS_ICC_EOIR0_EL1), undef_access }, 4242 { CP15_SYS_DESC(SYS_ICC_HPPIR0_EL1), undef_access }, 4243 { CP15_SYS_DESC(SYS_ICC_BPR0_EL1), undef_access }, 4244 { CP15_SYS_DESC(SYS_ICC_AP0R0_EL1), undef_access }, 4245 { CP15_SYS_DESC(SYS_ICC_AP0R1_EL1), undef_access }, 4246 { CP15_SYS_DESC(SYS_ICC_AP0R2_EL1), undef_access }, 4247 { CP15_SYS_DESC(SYS_ICC_AP0R3_EL1), undef_access }, 4248 { CP15_SYS_DESC(SYS_ICC_AP1R0_EL1), undef_access }, 4249 { CP15_SYS_DESC(SYS_ICC_AP1R1_EL1), undef_access }, 4250 { CP15_SYS_DESC(SYS_ICC_AP1R2_EL1), undef_access }, 4251 { CP15_SYS_DESC(SYS_ICC_AP1R3_EL1), undef_access }, 4252 { CP15_SYS_DESC(SYS_ICC_DIR_EL1), undef_access }, 4253 { CP15_SYS_DESC(SYS_ICC_RPR_EL1), undef_access }, 4254 { CP15_SYS_DESC(SYS_ICC_IAR1_EL1), undef_access }, 4255 { CP15_SYS_DESC(SYS_ICC_EOIR1_EL1), undef_access }, 4256 { CP15_SYS_DESC(SYS_ICC_HPPIR1_EL1), undef_access }, 4257 { CP15_SYS_DESC(SYS_ICC_BPR1_EL1), undef_access }, 4258 { CP15_SYS_DESC(SYS_ICC_CTLR_EL1), undef_access }, 4259 { CP15_SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre }, 4260 { CP15_SYS_DESC(SYS_ICC_IGRPEN0_EL1), undef_access }, 4261 { CP15_SYS_DESC(SYS_ICC_IGRPEN1_EL1), undef_access }, 4262 4263 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, CONTEXTIDR_EL1 }, 4264 4265 /* Arch Tmers */ 4266 { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer }, 4267 { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer }, 4268 4269 /* PMEVCNTRn */ 4270 PMU_PMEVCNTR(0), 4271 PMU_PMEVCNTR(1), 4272 PMU_PMEVCNTR(2), 4273 PMU_PMEVCNTR(3), 4274 PMU_PMEVCNTR(4), 4275 PMU_PMEVCNTR(5), 4276 PMU_PMEVCNTR(6), 4277 PMU_PMEVCNTR(7), 4278 PMU_PMEVCNTR(8), 4279 PMU_PMEVCNTR(9), 4280 PMU_PMEVCNTR(10), 4281 PMU_PMEVCNTR(11), 4282 PMU_PMEVCNTR(12), 4283 PMU_PMEVCNTR(13), 4284 PMU_PMEVCNTR(14), 4285 PMU_PMEVCNTR(15), 4286 PMU_PMEVCNTR(16), 4287 PMU_PMEVCNTR(17), 4288 PMU_PMEVCNTR(18), 4289 PMU_PMEVCNTR(19), 4290 PMU_PMEVCNTR(20), 4291 PMU_PMEVCNTR(21), 4292 PMU_PMEVCNTR(22), 4293 PMU_PMEVCNTR(23), 4294 PMU_PMEVCNTR(24), 4295 PMU_PMEVCNTR(25), 4296 PMU_PMEVCNTR(26), 4297 PMU_PMEVCNTR(27), 4298 PMU_PMEVCNTR(28), 4299 PMU_PMEVCNTR(29), 4300 PMU_PMEVCNTR(30), 4301 /* PMEVTYPERn */ 4302 PMU_PMEVTYPER(0), 4303 PMU_PMEVTYPER(1), 4304 PMU_PMEVTYPER(2), 4305 PMU_PMEVTYPER(3), 4306 PMU_PMEVTYPER(4), 4307 PMU_PMEVTYPER(5), 4308 PMU_PMEVTYPER(6), 4309 PMU_PMEVTYPER(7), 4310 PMU_PMEVTYPER(8), 4311 PMU_PMEVTYPER(9), 4312 PMU_PMEVTYPER(10), 4313 PMU_PMEVTYPER(11), 4314 PMU_PMEVTYPER(12), 4315 PMU_PMEVTYPER(13), 4316 PMU_PMEVTYPER(14), 4317 PMU_PMEVTYPER(15), 4318 PMU_PMEVTYPER(16), 4319 PMU_PMEVTYPER(17), 4320 PMU_PMEVTYPER(18), 4321 PMU_PMEVTYPER(19), 4322 PMU_PMEVTYPER(20), 4323 PMU_PMEVTYPER(21), 4324 PMU_PMEVTYPER(22), 4325 PMU_PMEVTYPER(23), 4326 PMU_PMEVTYPER(24), 4327 PMU_PMEVTYPER(25), 4328 PMU_PMEVTYPER(26), 4329 PMU_PMEVTYPER(27), 4330 PMU_PMEVTYPER(28), 4331 PMU_PMEVTYPER(29), 4332 PMU_PMEVTYPER(30), 4333 /* PMCCFILTR */ 4334 { CP15_PMU_SYS_REG(DIRECT, 0, 14, 15, 7), .access = access_pmu_evtyper }, 4335 4336 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr }, 4337 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr }, 4338 4339 /* CCSIDR2 */ 4340 { Op1(1), CRn( 0), CRm( 0), Op2(2), undef_access }, 4341 4342 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 }, 4343 }; 4344 4345 static const struct sys_reg_desc cp15_64_regs[] = { 4346 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, 4347 { CP15_PMU_SYS_REG(DIRECT, 0, 0, 9, 0), .access = access_pmu_evcntr }, 4348 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */ 4349 { SYS_DESC(SYS_AARCH32_CNTPCT), access_arch_timer }, 4350 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 }, 4351 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */ 4352 { SYS_DESC(SYS_AARCH32_CNTVCT), access_arch_timer }, 4353 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */ 4354 { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer }, 4355 { SYS_DESC(SYS_AARCH32_CNTPCTSS), access_arch_timer }, 4356 { SYS_DESC(SYS_AARCH32_CNTVCTSS), access_arch_timer }, 4357 }; 4358 4359 static bool check_sysreg_table(const struct sys_reg_desc *table, unsigned int n, 4360 bool reset_check) 4361 { 4362 unsigned int i; 4363 4364 for (i = 0; i < n; i++) { 4365 if (reset_check && table[i].reg && !table[i].reset) { 4366 kvm_err("sys_reg table %pS entry %d (%s) lacks reset\n", 4367 &table[i], i, table[i].name); 4368 return false; 4369 } 4370 4371 if (i && cmp_sys_reg(&table[i-1], &table[i]) >= 0) { 4372 kvm_err("sys_reg table %pS entry %d (%s -> %s) out of order\n", 4373 &table[i], i, table[i - 1].name, table[i].name); 4374 return false; 4375 } 4376 } 4377 4378 return true; 4379 } 4380 4381 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu) 4382 { 4383 kvm_inject_undefined(vcpu); 4384 return 1; 4385 } 4386 4387 static void perform_access(struct kvm_vcpu *vcpu, 4388 struct sys_reg_params *params, 4389 const struct sys_reg_desc *r) 4390 { 4391 trace_kvm_sys_access(*vcpu_pc(vcpu), params, r); 4392 4393 /* Check for regs disabled by runtime config */ 4394 if (sysreg_hidden(vcpu, r)) { 4395 kvm_inject_undefined(vcpu); 4396 return; 4397 } 4398 4399 /* 4400 * Not having an accessor means that we have configured a trap 4401 * that we don't know how to handle. This certainly qualifies 4402 * as a gross bug that should be fixed right away. 4403 */ 4404 BUG_ON(!r->access); 4405 4406 /* Skip instruction if instructed so */ 4407 if (likely(r->access(vcpu, params, r))) 4408 kvm_incr_pc(vcpu); 4409 } 4410 4411 /* 4412 * emulate_cp -- tries to match a sys_reg access in a handling table, and 4413 * call the corresponding trap handler. 4414 * 4415 * @params: pointer to the descriptor of the access 4416 * @table: array of trap descriptors 4417 * @num: size of the trap descriptor array 4418 * 4419 * Return true if the access has been handled, false if not. 4420 */ 4421 static bool emulate_cp(struct kvm_vcpu *vcpu, 4422 struct sys_reg_params *params, 4423 const struct sys_reg_desc *table, 4424 size_t num) 4425 { 4426 const struct sys_reg_desc *r; 4427 4428 if (!table) 4429 return false; /* Not handled */ 4430 4431 r = find_reg(params, table, num); 4432 4433 if (r) { 4434 perform_access(vcpu, params, r); 4435 return true; 4436 } 4437 4438 /* Not handled */ 4439 return false; 4440 } 4441 4442 static void unhandled_cp_access(struct kvm_vcpu *vcpu, 4443 struct sys_reg_params *params) 4444 { 4445 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu); 4446 int cp = -1; 4447 4448 switch (esr_ec) { 4449 case ESR_ELx_EC_CP15_32: 4450 case ESR_ELx_EC_CP15_64: 4451 cp = 15; 4452 break; 4453 case ESR_ELx_EC_CP14_MR: 4454 case ESR_ELx_EC_CP14_64: 4455 cp = 14; 4456 break; 4457 default: 4458 WARN_ON(1); 4459 } 4460 4461 print_sys_reg_msg(params, 4462 "Unsupported guest CP%d access at: %08lx [%08lx]\n", 4463 cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 4464 kvm_inject_undefined(vcpu); 4465 } 4466 4467 /** 4468 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access 4469 * @vcpu: The VCPU pointer 4470 * @global: &struct sys_reg_desc 4471 * @nr_global: size of the @global array 4472 */ 4473 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu, 4474 const struct sys_reg_desc *global, 4475 size_t nr_global) 4476 { 4477 struct sys_reg_params params; 4478 u64 esr = kvm_vcpu_get_esr(vcpu); 4479 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4480 int Rt2 = (esr >> 10) & 0x1f; 4481 4482 params.CRm = (esr >> 1) & 0xf; 4483 params.is_write = ((esr & 1) == 0); 4484 4485 params.Op0 = 0; 4486 params.Op1 = (esr >> 16) & 0xf; 4487 params.Op2 = 0; 4488 params.CRn = 0; 4489 4490 /* 4491 * Make a 64-bit value out of Rt and Rt2. As we use the same trap 4492 * backends between AArch32 and AArch64, we get away with it. 4493 */ 4494 if (params.is_write) { 4495 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff; 4496 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32; 4497 } 4498 4499 /* 4500 * If the table contains a handler, handle the 4501 * potential register operation in the case of a read and return 4502 * with success. 4503 */ 4504 if (emulate_cp(vcpu, ¶ms, global, nr_global)) { 4505 /* Split up the value between registers for the read side */ 4506 if (!params.is_write) { 4507 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval)); 4508 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval)); 4509 } 4510 4511 return 1; 4512 } 4513 4514 unhandled_cp_access(vcpu, ¶ms); 4515 return 1; 4516 } 4517 4518 static bool emulate_sys_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *params); 4519 4520 /* 4521 * The CP10 ID registers are architecturally mapped to AArch64 feature 4522 * registers. Abuse that fact so we can rely on the AArch64 handler for accesses 4523 * from AArch32. 4524 */ 4525 static bool kvm_esr_cp10_id_to_sys64(u64 esr, struct sys_reg_params *params) 4526 { 4527 u8 reg_id = (esr >> 10) & 0xf; 4528 bool valid; 4529 4530 params->is_write = ((esr & 1) == 0); 4531 params->Op0 = 3; 4532 params->Op1 = 0; 4533 params->CRn = 0; 4534 params->CRm = 3; 4535 4536 /* CP10 ID registers are read-only */ 4537 valid = !params->is_write; 4538 4539 switch (reg_id) { 4540 /* MVFR0 */ 4541 case 0b0111: 4542 params->Op2 = 0; 4543 break; 4544 /* MVFR1 */ 4545 case 0b0110: 4546 params->Op2 = 1; 4547 break; 4548 /* MVFR2 */ 4549 case 0b0101: 4550 params->Op2 = 2; 4551 break; 4552 default: 4553 valid = false; 4554 } 4555 4556 if (valid) 4557 return true; 4558 4559 kvm_pr_unimpl("Unhandled cp10 register %s: %u\n", 4560 str_write_read(params->is_write), reg_id); 4561 return false; 4562 } 4563 4564 /** 4565 * kvm_handle_cp10_id() - Handles a VMRS trap on guest access to a 'Media and 4566 * VFP Register' from AArch32. 4567 * @vcpu: The vCPU pointer 4568 * 4569 * MVFR{0-2} are architecturally mapped to the AArch64 MVFR{0-2}_EL1 registers. 4570 * Work out the correct AArch64 system register encoding and reroute to the 4571 * AArch64 system register emulation. 4572 */ 4573 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu) 4574 { 4575 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4576 u64 esr = kvm_vcpu_get_esr(vcpu); 4577 struct sys_reg_params params; 4578 4579 /* UNDEF on any unhandled register access */ 4580 if (!kvm_esr_cp10_id_to_sys64(esr, ¶ms)) { 4581 kvm_inject_undefined(vcpu); 4582 return 1; 4583 } 4584 4585 if (emulate_sys_reg(vcpu, ¶ms)) 4586 vcpu_set_reg(vcpu, Rt, params.regval); 4587 4588 return 1; 4589 } 4590 4591 /** 4592 * kvm_emulate_cp15_id_reg() - Handles an MRC trap on a guest CP15 access where 4593 * CRn=0, which corresponds to the AArch32 feature 4594 * registers. 4595 * @vcpu: the vCPU pointer 4596 * @params: the system register access parameters. 4597 * 4598 * Our cp15 system register tables do not enumerate the AArch32 feature 4599 * registers. Conveniently, our AArch64 table does, and the AArch32 system 4600 * register encoding can be trivially remapped into the AArch64 for the feature 4601 * registers: Append op0=3, leaving op1, CRn, CRm, and op2 the same. 4602 * 4603 * According to DDI0487G.b G7.3.1, paragraph "Behavior of VMSAv8-32 32-bit 4604 * System registers with (coproc=0b1111, CRn==c0)", read accesses from this 4605 * range are either UNKNOWN or RES0. Rerouting remains architectural as we 4606 * treat undefined registers in this range as RAZ. 4607 */ 4608 static int kvm_emulate_cp15_id_reg(struct kvm_vcpu *vcpu, 4609 struct sys_reg_params *params) 4610 { 4611 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4612 4613 /* Treat impossible writes to RO registers as UNDEFINED */ 4614 if (params->is_write) { 4615 unhandled_cp_access(vcpu, params); 4616 return 1; 4617 } 4618 4619 params->Op0 = 3; 4620 4621 /* 4622 * All registers where CRm > 3 are known to be UNKNOWN/RAZ from AArch32. 4623 * Avoid conflicting with future expansion of AArch64 feature registers 4624 * and simply treat them as RAZ here. 4625 */ 4626 if (params->CRm > 3) 4627 params->regval = 0; 4628 else if (!emulate_sys_reg(vcpu, params)) 4629 return 1; 4630 4631 vcpu_set_reg(vcpu, Rt, params->regval); 4632 return 1; 4633 } 4634 4635 /** 4636 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access 4637 * @vcpu: The VCPU pointer 4638 * @params: &struct sys_reg_params 4639 * @global: &struct sys_reg_desc 4640 * @nr_global: size of the @global array 4641 */ 4642 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu, 4643 struct sys_reg_params *params, 4644 const struct sys_reg_desc *global, 4645 size_t nr_global) 4646 { 4647 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4648 4649 params->regval = vcpu_get_reg(vcpu, Rt); 4650 4651 if (emulate_cp(vcpu, params, global, nr_global)) { 4652 if (!params->is_write) 4653 vcpu_set_reg(vcpu, Rt, params->regval); 4654 return 1; 4655 } 4656 4657 unhandled_cp_access(vcpu, params); 4658 return 1; 4659 } 4660 4661 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu) 4662 { 4663 return kvm_handle_cp_64(vcpu, cp15_64_regs, ARRAY_SIZE(cp15_64_regs)); 4664 } 4665 4666 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu) 4667 { 4668 struct sys_reg_params params; 4669 4670 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu)); 4671 4672 /* 4673 * Certain AArch32 ID registers are handled by rerouting to the AArch64 4674 * system register table. Registers in the ID range where CRm=0 are 4675 * excluded from this scheme as they do not trivially map into AArch64 4676 * system register encodings, except for AIDR/REVIDR. 4677 */ 4678 if (params.Op1 == 0 && params.CRn == 0 && 4679 (params.CRm || params.Op2 == 6 /* REVIDR */)) 4680 return kvm_emulate_cp15_id_reg(vcpu, ¶ms); 4681 if (params.Op1 == 1 && params.CRn == 0 && 4682 params.CRm == 0 && params.Op2 == 7 /* AIDR */) 4683 return kvm_emulate_cp15_id_reg(vcpu, ¶ms); 4684 4685 return kvm_handle_cp_32(vcpu, ¶ms, cp15_regs, ARRAY_SIZE(cp15_regs)); 4686 } 4687 4688 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu) 4689 { 4690 return kvm_handle_cp_64(vcpu, cp14_64_regs, ARRAY_SIZE(cp14_64_regs)); 4691 } 4692 4693 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu) 4694 { 4695 struct sys_reg_params params; 4696 4697 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu)); 4698 4699 return kvm_handle_cp_32(vcpu, ¶ms, cp14_regs, ARRAY_SIZE(cp14_regs)); 4700 } 4701 4702 /** 4703 * emulate_sys_reg - Emulate a guest access to an AArch64 system register 4704 * @vcpu: The VCPU pointer 4705 * @params: Decoded system register parameters 4706 * 4707 * Return: true if the system register access was successful, false otherwise. 4708 */ 4709 static bool emulate_sys_reg(struct kvm_vcpu *vcpu, 4710 struct sys_reg_params *params) 4711 { 4712 const struct sys_reg_desc *r; 4713 4714 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 4715 if (likely(r)) { 4716 perform_access(vcpu, params, r); 4717 return true; 4718 } 4719 4720 print_sys_reg_msg(params, 4721 "Unsupported guest sys_reg access at: %lx [%08lx]\n", 4722 *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 4723 kvm_inject_undefined(vcpu); 4724 4725 return false; 4726 } 4727 4728 static const struct sys_reg_desc *idregs_debug_find(struct kvm *kvm, u8 pos) 4729 { 4730 unsigned long i, idreg_idx = 0; 4731 4732 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { 4733 const struct sys_reg_desc *r = &sys_reg_descs[i]; 4734 4735 if (!is_vm_ftr_id_reg(reg_to_encoding(r))) 4736 continue; 4737 4738 if (idreg_idx == pos) 4739 return r; 4740 4741 idreg_idx++; 4742 } 4743 4744 return NULL; 4745 } 4746 4747 static void *idregs_debug_start(struct seq_file *s, loff_t *pos) 4748 { 4749 struct kvm *kvm = s->private; 4750 u8 *iter; 4751 4752 mutex_lock(&kvm->arch.config_lock); 4753 4754 iter = &kvm->arch.idreg_debugfs_iter; 4755 if (test_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags) && 4756 *iter == (u8)~0) { 4757 *iter = *pos; 4758 if (!idregs_debug_find(kvm, *iter)) 4759 iter = NULL; 4760 } else { 4761 iter = ERR_PTR(-EBUSY); 4762 } 4763 4764 mutex_unlock(&kvm->arch.config_lock); 4765 4766 return iter; 4767 } 4768 4769 static void *idregs_debug_next(struct seq_file *s, void *v, loff_t *pos) 4770 { 4771 struct kvm *kvm = s->private; 4772 4773 (*pos)++; 4774 4775 if (idregs_debug_find(kvm, kvm->arch.idreg_debugfs_iter + 1)) { 4776 kvm->arch.idreg_debugfs_iter++; 4777 4778 return &kvm->arch.idreg_debugfs_iter; 4779 } 4780 4781 return NULL; 4782 } 4783 4784 static void idregs_debug_stop(struct seq_file *s, void *v) 4785 { 4786 struct kvm *kvm = s->private; 4787 4788 if (IS_ERR(v)) 4789 return; 4790 4791 mutex_lock(&kvm->arch.config_lock); 4792 4793 kvm->arch.idreg_debugfs_iter = ~0; 4794 4795 mutex_unlock(&kvm->arch.config_lock); 4796 } 4797 4798 static int idregs_debug_show(struct seq_file *s, void *v) 4799 { 4800 const struct sys_reg_desc *desc; 4801 struct kvm *kvm = s->private; 4802 4803 desc = idregs_debug_find(kvm, kvm->arch.idreg_debugfs_iter); 4804 4805 if (!desc->name) 4806 return 0; 4807 4808 seq_printf(s, "%20s:\t%016llx\n", 4809 desc->name, kvm_read_vm_id_reg(kvm, reg_to_encoding(desc))); 4810 4811 return 0; 4812 } 4813 4814 static const struct seq_operations idregs_debug_sops = { 4815 .start = idregs_debug_start, 4816 .next = idregs_debug_next, 4817 .stop = idregs_debug_stop, 4818 .show = idregs_debug_show, 4819 }; 4820 4821 DEFINE_SEQ_ATTRIBUTE(idregs_debug); 4822 4823 void kvm_sys_regs_create_debugfs(struct kvm *kvm) 4824 { 4825 kvm->arch.idreg_debugfs_iter = ~0; 4826 4827 debugfs_create_file("idregs", 0444, kvm->debugfs_dentry, kvm, 4828 &idregs_debug_fops); 4829 } 4830 4831 static void reset_vm_ftr_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *reg) 4832 { 4833 u32 id = reg_to_encoding(reg); 4834 struct kvm *kvm = vcpu->kvm; 4835 4836 if (test_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags)) 4837 return; 4838 4839 kvm_set_vm_id_reg(kvm, id, reg->reset(vcpu, reg)); 4840 } 4841 4842 static void reset_vcpu_ftr_id_reg(struct kvm_vcpu *vcpu, 4843 const struct sys_reg_desc *reg) 4844 { 4845 if (kvm_vcpu_initialized(vcpu)) 4846 return; 4847 4848 reg->reset(vcpu, reg); 4849 } 4850 4851 /** 4852 * kvm_reset_sys_regs - sets system registers to reset value 4853 * @vcpu: The VCPU pointer 4854 * 4855 * This function finds the right table above and sets the registers on the 4856 * virtual CPU struct to their architecturally defined reset values. 4857 */ 4858 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu) 4859 { 4860 struct kvm *kvm = vcpu->kvm; 4861 unsigned long i; 4862 4863 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { 4864 const struct sys_reg_desc *r = &sys_reg_descs[i]; 4865 4866 if (!r->reset) 4867 continue; 4868 4869 if (is_vm_ftr_id_reg(reg_to_encoding(r))) 4870 reset_vm_ftr_id_reg(vcpu, r); 4871 else if (is_vcpu_ftr_id_reg(reg_to_encoding(r))) 4872 reset_vcpu_ftr_id_reg(vcpu, r); 4873 else 4874 r->reset(vcpu, r); 4875 4876 if (r->reg >= __SANITISED_REG_START__ && r->reg < NR_SYS_REGS) 4877 __vcpu_rmw_sys_reg(vcpu, r->reg, |=, 0); 4878 } 4879 4880 set_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags); 4881 4882 if (kvm_vcpu_has_pmu(vcpu)) 4883 kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu); 4884 } 4885 4886 /** 4887 * kvm_handle_sys_reg -- handles a system instruction or mrs/msr instruction 4888 * trap on a guest execution 4889 * @vcpu: The VCPU pointer 4890 */ 4891 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu) 4892 { 4893 const struct sys_reg_desc *desc = NULL; 4894 struct sys_reg_params params; 4895 unsigned long esr = kvm_vcpu_get_esr(vcpu); 4896 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4897 int sr_idx; 4898 4899 trace_kvm_handle_sys_reg(esr); 4900 4901 if (triage_sysreg_trap(vcpu, &sr_idx)) 4902 return 1; 4903 4904 params = esr_sys64_to_params(esr); 4905 params.regval = vcpu_get_reg(vcpu, Rt); 4906 4907 /* System registers have Op0=={2,3}, as per DDI487 J.a C5.1.2 */ 4908 if (params.Op0 == 2 || params.Op0 == 3) 4909 desc = &sys_reg_descs[sr_idx]; 4910 else 4911 desc = &sys_insn_descs[sr_idx]; 4912 4913 perform_access(vcpu, ¶ms, desc); 4914 4915 /* Read from system register? */ 4916 if (!params.is_write && 4917 (params.Op0 == 2 || params.Op0 == 3)) 4918 vcpu_set_reg(vcpu, Rt, params.regval); 4919 4920 return 1; 4921 } 4922 4923 /****************************************************************************** 4924 * Userspace API 4925 *****************************************************************************/ 4926 4927 static bool index_to_params(u64 id, struct sys_reg_params *params) 4928 { 4929 switch (id & KVM_REG_SIZE_MASK) { 4930 case KVM_REG_SIZE_U64: 4931 /* Any unused index bits means it's not valid. */ 4932 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK 4933 | KVM_REG_ARM_COPROC_MASK 4934 | KVM_REG_ARM64_SYSREG_OP0_MASK 4935 | KVM_REG_ARM64_SYSREG_OP1_MASK 4936 | KVM_REG_ARM64_SYSREG_CRN_MASK 4937 | KVM_REG_ARM64_SYSREG_CRM_MASK 4938 | KVM_REG_ARM64_SYSREG_OP2_MASK)) 4939 return false; 4940 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK) 4941 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT); 4942 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK) 4943 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT); 4944 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK) 4945 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT); 4946 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK) 4947 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT); 4948 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK) 4949 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT); 4950 return true; 4951 default: 4952 return false; 4953 } 4954 } 4955 4956 const struct sys_reg_desc *get_reg_by_id(u64 id, 4957 const struct sys_reg_desc table[], 4958 unsigned int num) 4959 { 4960 struct sys_reg_params params; 4961 4962 if (!index_to_params(id, ¶ms)) 4963 return NULL; 4964 4965 return find_reg(¶ms, table, num); 4966 } 4967 4968 /* Decode an index value, and find the sys_reg_desc entry. */ 4969 static const struct sys_reg_desc * 4970 id_to_sys_reg_desc(struct kvm_vcpu *vcpu, u64 id, 4971 const struct sys_reg_desc table[], unsigned int num) 4972 4973 { 4974 const struct sys_reg_desc *r; 4975 4976 /* We only do sys_reg for now. */ 4977 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG) 4978 return NULL; 4979 4980 r = get_reg_by_id(id, table, num); 4981 4982 /* Not saved in the sys_reg array and not otherwise accessible? */ 4983 if (r && (!(r->reg || r->get_user) || sysreg_hidden(vcpu, r))) 4984 r = NULL; 4985 4986 return r; 4987 } 4988 4989 static int demux_c15_get(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) 4990 { 4991 u32 val; 4992 u32 __user *uval = uaddr; 4993 4994 /* Fail if we have unknown bits set. */ 4995 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 4996 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 4997 return -ENOENT; 4998 4999 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 5000 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 5001 if (KVM_REG_SIZE(id) != 4) 5002 return -ENOENT; 5003 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 5004 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 5005 if (val >= CSSELR_MAX) 5006 return -ENOENT; 5007 5008 return put_user(get_ccsidr(vcpu, val), uval); 5009 default: 5010 return -ENOENT; 5011 } 5012 } 5013 5014 static int demux_c15_set(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) 5015 { 5016 u32 val, newval; 5017 u32 __user *uval = uaddr; 5018 5019 /* Fail if we have unknown bits set. */ 5020 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 5021 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 5022 return -ENOENT; 5023 5024 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 5025 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 5026 if (KVM_REG_SIZE(id) != 4) 5027 return -ENOENT; 5028 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 5029 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 5030 if (val >= CSSELR_MAX) 5031 return -ENOENT; 5032 5033 if (get_user(newval, uval)) 5034 return -EFAULT; 5035 5036 return set_ccsidr(vcpu, val, newval); 5037 default: 5038 return -ENOENT; 5039 } 5040 } 5041 5042 int kvm_sys_reg_get_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg, 5043 const struct sys_reg_desc table[], unsigned int num) 5044 { 5045 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr; 5046 const struct sys_reg_desc *r; 5047 u64 val; 5048 int ret; 5049 5050 r = id_to_sys_reg_desc(vcpu, reg->id, table, num); 5051 if (!r || sysreg_hidden(vcpu, r)) 5052 return -ENOENT; 5053 5054 if (r->get_user) { 5055 ret = (r->get_user)(vcpu, r, &val); 5056 } else { 5057 val = __vcpu_sys_reg(vcpu, r->reg); 5058 ret = 0; 5059 } 5060 5061 if (!ret) 5062 ret = put_user(val, uaddr); 5063 5064 return ret; 5065 } 5066 5067 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 5068 { 5069 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 5070 5071 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 5072 return demux_c15_get(vcpu, reg->id, uaddr); 5073 5074 return kvm_sys_reg_get_user(vcpu, reg, 5075 sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 5076 } 5077 5078 int kvm_sys_reg_set_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg, 5079 const struct sys_reg_desc table[], unsigned int num) 5080 { 5081 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr; 5082 const struct sys_reg_desc *r; 5083 u64 val; 5084 int ret; 5085 5086 if (get_user(val, uaddr)) 5087 return -EFAULT; 5088 5089 r = id_to_sys_reg_desc(vcpu, reg->id, table, num); 5090 if (!r || sysreg_hidden(vcpu, r)) 5091 return -ENOENT; 5092 5093 if (sysreg_user_write_ignore(vcpu, r)) 5094 return 0; 5095 5096 if (r->set_user) { 5097 ret = (r->set_user)(vcpu, r, val); 5098 } else { 5099 __vcpu_assign_sys_reg(vcpu, r->reg, val); 5100 ret = 0; 5101 } 5102 5103 return ret; 5104 } 5105 5106 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 5107 { 5108 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 5109 5110 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 5111 return demux_c15_set(vcpu, reg->id, uaddr); 5112 5113 return kvm_sys_reg_set_user(vcpu, reg, 5114 sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 5115 } 5116 5117 static unsigned int num_demux_regs(void) 5118 { 5119 return CSSELR_MAX; 5120 } 5121 5122 static int write_demux_regids(u64 __user *uindices) 5123 { 5124 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX; 5125 unsigned int i; 5126 5127 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR; 5128 for (i = 0; i < CSSELR_MAX; i++) { 5129 if (put_user(val | i, uindices)) 5130 return -EFAULT; 5131 uindices++; 5132 } 5133 return 0; 5134 } 5135 5136 static u64 sys_reg_to_index(const struct sys_reg_desc *reg) 5137 { 5138 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | 5139 KVM_REG_ARM64_SYSREG | 5140 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) | 5141 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) | 5142 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) | 5143 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) | 5144 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT)); 5145 } 5146 5147 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind) 5148 { 5149 if (!*uind) 5150 return true; 5151 5152 if (put_user(sys_reg_to_index(reg), *uind)) 5153 return false; 5154 5155 (*uind)++; 5156 return true; 5157 } 5158 5159 static int walk_one_sys_reg(const struct kvm_vcpu *vcpu, 5160 const struct sys_reg_desc *rd, 5161 u64 __user **uind, 5162 unsigned int *total) 5163 { 5164 /* 5165 * Ignore registers we trap but don't save, 5166 * and for which no custom user accessor is provided. 5167 */ 5168 if (!(rd->reg || rd->get_user)) 5169 return 0; 5170 5171 if (sysreg_hidden(vcpu, rd)) 5172 return 0; 5173 5174 if (!copy_reg_to_user(rd, uind)) 5175 return -EFAULT; 5176 5177 (*total)++; 5178 return 0; 5179 } 5180 5181 /* Assumed ordered tables, see kvm_sys_reg_table_init. */ 5182 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind) 5183 { 5184 const struct sys_reg_desc *i2, *end2; 5185 unsigned int total = 0; 5186 int err; 5187 5188 i2 = sys_reg_descs; 5189 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs); 5190 5191 while (i2 != end2) { 5192 err = walk_one_sys_reg(vcpu, i2++, &uind, &total); 5193 if (err) 5194 return err; 5195 } 5196 return total; 5197 } 5198 5199 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu) 5200 { 5201 return num_demux_regs() 5202 + walk_sys_regs(vcpu, (u64 __user *)NULL); 5203 } 5204 5205 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) 5206 { 5207 int err; 5208 5209 err = walk_sys_regs(vcpu, uindices); 5210 if (err < 0) 5211 return err; 5212 uindices += err; 5213 5214 return write_demux_regids(uindices); 5215 } 5216 5217 #define KVM_ARM_FEATURE_ID_RANGE_INDEX(r) \ 5218 KVM_ARM_FEATURE_ID_RANGE_IDX(sys_reg_Op0(r), \ 5219 sys_reg_Op1(r), \ 5220 sys_reg_CRn(r), \ 5221 sys_reg_CRm(r), \ 5222 sys_reg_Op2(r)) 5223 5224 int kvm_vm_ioctl_get_reg_writable_masks(struct kvm *kvm, struct reg_mask_range *range) 5225 { 5226 const void *zero_page = page_to_virt(ZERO_PAGE(0)); 5227 u64 __user *masks = (u64 __user *)range->addr; 5228 5229 /* Only feature id range is supported, reserved[13] must be zero. */ 5230 if (range->range || 5231 memcmp(range->reserved, zero_page, sizeof(range->reserved))) 5232 return -EINVAL; 5233 5234 /* Wipe the whole thing first */ 5235 if (clear_user(masks, KVM_ARM_FEATURE_ID_RANGE_SIZE * sizeof(__u64))) 5236 return -EFAULT; 5237 5238 for (int i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { 5239 const struct sys_reg_desc *reg = &sys_reg_descs[i]; 5240 u32 encoding = reg_to_encoding(reg); 5241 u64 val; 5242 5243 if (!is_feature_id_reg(encoding) || !reg->set_user) 5244 continue; 5245 5246 if (!reg->val || 5247 (is_aa32_id_reg(encoding) && !kvm_supports_32bit_el0())) { 5248 continue; 5249 } 5250 val = reg->val; 5251 5252 if (put_user(val, (masks + KVM_ARM_FEATURE_ID_RANGE_INDEX(encoding)))) 5253 return -EFAULT; 5254 } 5255 5256 return 0; 5257 } 5258 5259 static void vcpu_set_hcr(struct kvm_vcpu *vcpu) 5260 { 5261 struct kvm *kvm = vcpu->kvm; 5262 5263 if (has_vhe() || has_hvhe()) 5264 vcpu->arch.hcr_el2 |= HCR_E2H; 5265 if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN)) { 5266 /* route synchronous external abort exceptions to EL2 */ 5267 vcpu->arch.hcr_el2 |= HCR_TEA; 5268 /* trap error record accesses */ 5269 vcpu->arch.hcr_el2 |= HCR_TERR; 5270 } 5271 5272 if (cpus_have_final_cap(ARM64_HAS_STAGE2_FWB)) 5273 vcpu->arch.hcr_el2 |= HCR_FWB; 5274 5275 if (cpus_have_final_cap(ARM64_HAS_EVT) && 5276 !cpus_have_final_cap(ARM64_MISMATCHED_CACHE_TYPE) && 5277 kvm_read_vm_id_reg(kvm, SYS_CTR_EL0) == read_sanitised_ftr_reg(SYS_CTR_EL0)) 5278 vcpu->arch.hcr_el2 |= HCR_TID4; 5279 else 5280 vcpu->arch.hcr_el2 |= HCR_TID2; 5281 5282 if (vcpu_el1_is_32bit(vcpu)) 5283 vcpu->arch.hcr_el2 &= ~HCR_RW; 5284 5285 if (kvm_has_mte(vcpu->kvm)) 5286 vcpu->arch.hcr_el2 |= HCR_ATA; 5287 5288 /* 5289 * In the absence of FGT, we cannot independently trap TLBI 5290 * Range instructions. This isn't great, but trapping all 5291 * TLBIs would be far worse. Live with it... 5292 */ 5293 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 5294 vcpu->arch.hcr_el2 |= HCR_TTLBOS; 5295 } 5296 5297 void kvm_calculate_traps(struct kvm_vcpu *vcpu) 5298 { 5299 struct kvm *kvm = vcpu->kvm; 5300 5301 mutex_lock(&kvm->arch.config_lock); 5302 vcpu_set_hcr(vcpu); 5303 vcpu_set_ich_hcr(vcpu); 5304 vcpu_set_hcrx(vcpu); 5305 5306 if (test_bit(KVM_ARCH_FLAG_FGU_INITIALIZED, &kvm->arch.flags)) 5307 goto out; 5308 5309 compute_fgu(kvm, HFGRTR_GROUP); 5310 compute_fgu(kvm, HFGITR_GROUP); 5311 compute_fgu(kvm, HDFGRTR_GROUP); 5312 compute_fgu(kvm, HAFGRTR_GROUP); 5313 compute_fgu(kvm, HFGRTR2_GROUP); 5314 compute_fgu(kvm, HFGITR2_GROUP); 5315 compute_fgu(kvm, HDFGRTR2_GROUP); 5316 5317 set_bit(KVM_ARCH_FLAG_FGU_INITIALIZED, &kvm->arch.flags); 5318 out: 5319 mutex_unlock(&kvm->arch.config_lock); 5320 } 5321 5322 /* 5323 * Perform last adjustments to the ID registers that are implied by the 5324 * configuration outside of the ID regs themselves, as well as any 5325 * initialisation that directly depend on these ID registers (such as 5326 * RES0/RES1 behaviours). This is not the place to configure traps though. 5327 * 5328 * Because this can be called once per CPU, changes must be idempotent. 5329 */ 5330 int kvm_finalize_sys_regs(struct kvm_vcpu *vcpu) 5331 { 5332 struct kvm *kvm = vcpu->kvm; 5333 5334 guard(mutex)(&kvm->arch.config_lock); 5335 5336 if (!(static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif) && 5337 irqchip_in_kernel(kvm) && 5338 kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3)) { 5339 kvm->arch.id_regs[IDREG_IDX(SYS_ID_AA64PFR0_EL1)] &= ~ID_AA64PFR0_EL1_GIC_MASK; 5340 kvm->arch.id_regs[IDREG_IDX(SYS_ID_PFR1_EL1)] &= ~ID_PFR1_EL1_GIC_MASK; 5341 } 5342 5343 if (vcpu_has_nv(vcpu)) { 5344 int ret = kvm_init_nv_sysregs(vcpu); 5345 if (ret) 5346 return ret; 5347 } 5348 5349 return 0; 5350 } 5351 5352 int __init kvm_sys_reg_table_init(void) 5353 { 5354 const struct sys_reg_desc *gicv3_regs; 5355 bool valid = true; 5356 unsigned int i, sz; 5357 int ret = 0; 5358 5359 /* Make sure tables are unique and in order. */ 5360 valid &= check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), true); 5361 valid &= check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), false); 5362 valid &= check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), false); 5363 valid &= check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), false); 5364 valid &= check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), false); 5365 valid &= check_sysreg_table(sys_insn_descs, ARRAY_SIZE(sys_insn_descs), false); 5366 5367 gicv3_regs = vgic_v3_get_sysreg_table(&sz); 5368 valid &= check_sysreg_table(gicv3_regs, sz, false); 5369 5370 if (!valid) 5371 return -EINVAL; 5372 5373 init_imp_id_regs(); 5374 5375 ret = populate_nv_trap_config(); 5376 5377 check_feature_map(); 5378 5379 for (i = 0; !ret && i < ARRAY_SIZE(sys_reg_descs); i++) 5380 ret = populate_sysreg_config(sys_reg_descs + i, i); 5381 5382 for (i = 0; !ret && i < ARRAY_SIZE(sys_insn_descs); i++) 5383 ret = populate_sysreg_config(sys_insn_descs + i, i); 5384 5385 return ret; 5386 } 5387