1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/kvm/coproc.c: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Authors: Rusty Russell <rusty@rustcorp.com.au> 9 * Christoffer Dall <c.dall@virtualopensystems.com> 10 */ 11 12 #include <linux/bitfield.h> 13 #include <linux/bsearch.h> 14 #include <linux/cacheinfo.h> 15 #include <linux/debugfs.h> 16 #include <linux/kvm_host.h> 17 #include <linux/mm.h> 18 #include <linux/printk.h> 19 #include <linux/uaccess.h> 20 21 #include <asm/arm_pmuv3.h> 22 #include <asm/cacheflush.h> 23 #include <asm/cputype.h> 24 #include <asm/debug-monitors.h> 25 #include <asm/esr.h> 26 #include <asm/kvm_arm.h> 27 #include <asm/kvm_emulate.h> 28 #include <asm/kvm_hyp.h> 29 #include <asm/kvm_mmu.h> 30 #include <asm/kvm_nested.h> 31 #include <asm/perf_event.h> 32 #include <asm/sysreg.h> 33 34 #include <trace/events/kvm.h> 35 36 #include "sys_regs.h" 37 #include "vgic/vgic.h" 38 39 #include "trace.h" 40 41 /* 42 * For AArch32, we only take care of what is being trapped. Anything 43 * that has to do with init and userspace access has to go via the 44 * 64bit interface. 45 */ 46 47 static u64 sys_reg_to_index(const struct sys_reg_desc *reg); 48 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 49 u64 val); 50 51 static bool undef_access(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 52 const struct sys_reg_desc *r) 53 { 54 kvm_inject_undefined(vcpu); 55 return false; 56 } 57 58 static bool bad_trap(struct kvm_vcpu *vcpu, 59 struct sys_reg_params *params, 60 const struct sys_reg_desc *r, 61 const char *msg) 62 { 63 WARN_ONCE(1, "Unexpected %s\n", msg); 64 print_sys_reg_instr(params); 65 return undef_access(vcpu, params, r); 66 } 67 68 static bool read_from_write_only(struct kvm_vcpu *vcpu, 69 struct sys_reg_params *params, 70 const struct sys_reg_desc *r) 71 { 72 return bad_trap(vcpu, params, r, 73 "sys_reg read to write-only register"); 74 } 75 76 static bool write_to_read_only(struct kvm_vcpu *vcpu, 77 struct sys_reg_params *params, 78 const struct sys_reg_desc *r) 79 { 80 return bad_trap(vcpu, params, r, 81 "sys_reg write to read-only register"); 82 } 83 84 #define PURE_EL2_SYSREG(el2) \ 85 case el2: { \ 86 *el1r = el2; \ 87 return true; \ 88 } 89 90 #define MAPPED_EL2_SYSREG(el2, el1, fn) \ 91 case el2: { \ 92 *xlate = fn; \ 93 *el1r = el1; \ 94 return true; \ 95 } 96 97 static bool get_el2_to_el1_mapping(unsigned int reg, 98 unsigned int *el1r, u64 (**xlate)(u64)) 99 { 100 switch (reg) { 101 PURE_EL2_SYSREG( VPIDR_EL2 ); 102 PURE_EL2_SYSREG( VMPIDR_EL2 ); 103 PURE_EL2_SYSREG( ACTLR_EL2 ); 104 PURE_EL2_SYSREG( HCR_EL2 ); 105 PURE_EL2_SYSREG( MDCR_EL2 ); 106 PURE_EL2_SYSREG( HSTR_EL2 ); 107 PURE_EL2_SYSREG( HACR_EL2 ); 108 PURE_EL2_SYSREG( VTTBR_EL2 ); 109 PURE_EL2_SYSREG( VTCR_EL2 ); 110 PURE_EL2_SYSREG( RVBAR_EL2 ); 111 PURE_EL2_SYSREG( TPIDR_EL2 ); 112 PURE_EL2_SYSREG( HPFAR_EL2 ); 113 PURE_EL2_SYSREG( HCRX_EL2 ); 114 PURE_EL2_SYSREG( HFGRTR_EL2 ); 115 PURE_EL2_SYSREG( HFGWTR_EL2 ); 116 PURE_EL2_SYSREG( HFGITR_EL2 ); 117 PURE_EL2_SYSREG( HDFGRTR_EL2 ); 118 PURE_EL2_SYSREG( HDFGWTR_EL2 ); 119 PURE_EL2_SYSREG( HAFGRTR_EL2 ); 120 PURE_EL2_SYSREG( CNTVOFF_EL2 ); 121 PURE_EL2_SYSREG( CNTHCTL_EL2 ); 122 MAPPED_EL2_SYSREG(SCTLR_EL2, SCTLR_EL1, 123 translate_sctlr_el2_to_sctlr_el1 ); 124 MAPPED_EL2_SYSREG(CPTR_EL2, CPACR_EL1, 125 translate_cptr_el2_to_cpacr_el1 ); 126 MAPPED_EL2_SYSREG(TTBR0_EL2, TTBR0_EL1, 127 translate_ttbr0_el2_to_ttbr0_el1 ); 128 MAPPED_EL2_SYSREG(TTBR1_EL2, TTBR1_EL1, NULL ); 129 MAPPED_EL2_SYSREG(TCR_EL2, TCR_EL1, 130 translate_tcr_el2_to_tcr_el1 ); 131 MAPPED_EL2_SYSREG(VBAR_EL2, VBAR_EL1, NULL ); 132 MAPPED_EL2_SYSREG(AFSR0_EL2, AFSR0_EL1, NULL ); 133 MAPPED_EL2_SYSREG(AFSR1_EL2, AFSR1_EL1, NULL ); 134 MAPPED_EL2_SYSREG(ESR_EL2, ESR_EL1, NULL ); 135 MAPPED_EL2_SYSREG(FAR_EL2, FAR_EL1, NULL ); 136 MAPPED_EL2_SYSREG(MAIR_EL2, MAIR_EL1, NULL ); 137 MAPPED_EL2_SYSREG(TCR2_EL2, TCR2_EL1, NULL ); 138 MAPPED_EL2_SYSREG(PIR_EL2, PIR_EL1, NULL ); 139 MAPPED_EL2_SYSREG(PIRE0_EL2, PIRE0_EL1, NULL ); 140 MAPPED_EL2_SYSREG(AMAIR_EL2, AMAIR_EL1, NULL ); 141 MAPPED_EL2_SYSREG(ELR_EL2, ELR_EL1, NULL ); 142 MAPPED_EL2_SYSREG(SPSR_EL2, SPSR_EL1, NULL ); 143 MAPPED_EL2_SYSREG(ZCR_EL2, ZCR_EL1, NULL ); 144 MAPPED_EL2_SYSREG(CONTEXTIDR_EL2, CONTEXTIDR_EL1, NULL ); 145 default: 146 return false; 147 } 148 } 149 150 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg) 151 { 152 u64 val = 0x8badf00d8badf00d; 153 u64 (*xlate)(u64) = NULL; 154 unsigned int el1r; 155 156 if (!vcpu_get_flag(vcpu, SYSREGS_ON_CPU)) 157 goto memory_read; 158 159 if (unlikely(get_el2_to_el1_mapping(reg, &el1r, &xlate))) { 160 if (!is_hyp_ctxt(vcpu)) 161 goto memory_read; 162 163 /* 164 * CNTHCTL_EL2 requires some special treatment to 165 * account for the bits that can be set via CNTKCTL_EL1. 166 */ 167 switch (reg) { 168 case CNTHCTL_EL2: 169 if (vcpu_el2_e2h_is_set(vcpu)) { 170 val = read_sysreg_el1(SYS_CNTKCTL); 171 val &= CNTKCTL_VALID_BITS; 172 val |= __vcpu_sys_reg(vcpu, reg) & ~CNTKCTL_VALID_BITS; 173 return val; 174 } 175 break; 176 } 177 178 /* 179 * If this register does not have an EL1 counterpart, 180 * then read the stored EL2 version. 181 */ 182 if (reg == el1r) 183 goto memory_read; 184 185 /* 186 * If we have a non-VHE guest and that the sysreg 187 * requires translation to be used at EL1, use the 188 * in-memory copy instead. 189 */ 190 if (!vcpu_el2_e2h_is_set(vcpu) && xlate) 191 goto memory_read; 192 193 /* Get the current version of the EL1 counterpart. */ 194 WARN_ON(!__vcpu_read_sys_reg_from_cpu(el1r, &val)); 195 if (reg >= __SANITISED_REG_START__) 196 val = kvm_vcpu_apply_reg_masks(vcpu, reg, val); 197 198 return val; 199 } 200 201 /* EL1 register can't be on the CPU if the guest is in vEL2. */ 202 if (unlikely(is_hyp_ctxt(vcpu))) 203 goto memory_read; 204 205 if (__vcpu_read_sys_reg_from_cpu(reg, &val)) 206 return val; 207 208 memory_read: 209 return __vcpu_sys_reg(vcpu, reg); 210 } 211 212 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg) 213 { 214 u64 (*xlate)(u64) = NULL; 215 unsigned int el1r; 216 217 if (!vcpu_get_flag(vcpu, SYSREGS_ON_CPU)) 218 goto memory_write; 219 220 if (unlikely(get_el2_to_el1_mapping(reg, &el1r, &xlate))) { 221 if (!is_hyp_ctxt(vcpu)) 222 goto memory_write; 223 224 /* 225 * Always store a copy of the write to memory to avoid having 226 * to reverse-translate virtual EL2 system registers for a 227 * non-VHE guest hypervisor. 228 */ 229 __vcpu_sys_reg(vcpu, reg) = val; 230 231 switch (reg) { 232 case CNTHCTL_EL2: 233 /* 234 * If E2H=0, CNHTCTL_EL2 is a pure shadow register. 235 * Otherwise, some of the bits are backed by 236 * CNTKCTL_EL1, while the rest is kept in memory. 237 * Yes, this is fun stuff. 238 */ 239 if (vcpu_el2_e2h_is_set(vcpu)) 240 write_sysreg_el1(val, SYS_CNTKCTL); 241 return; 242 } 243 244 /* No EL1 counterpart? We're done here.? */ 245 if (reg == el1r) 246 return; 247 248 if (!vcpu_el2_e2h_is_set(vcpu) && xlate) 249 val = xlate(val); 250 251 /* Redirect this to the EL1 version of the register. */ 252 WARN_ON(!__vcpu_write_sys_reg_to_cpu(val, el1r)); 253 return; 254 } 255 256 /* EL1 register can't be on the CPU if the guest is in vEL2. */ 257 if (unlikely(is_hyp_ctxt(vcpu))) 258 goto memory_write; 259 260 if (__vcpu_write_sys_reg_to_cpu(val, reg)) 261 return; 262 263 memory_write: 264 __vcpu_sys_reg(vcpu, reg) = val; 265 } 266 267 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */ 268 #define CSSELR_MAX 14 269 270 /* 271 * Returns the minimum line size for the selected cache, expressed as 272 * Log2(bytes). 273 */ 274 static u8 get_min_cache_line_size(bool icache) 275 { 276 u64 ctr = read_sanitised_ftr_reg(SYS_CTR_EL0); 277 u8 field; 278 279 if (icache) 280 field = SYS_FIELD_GET(CTR_EL0, IminLine, ctr); 281 else 282 field = SYS_FIELD_GET(CTR_EL0, DminLine, ctr); 283 284 /* 285 * Cache line size is represented as Log2(words) in CTR_EL0. 286 * Log2(bytes) can be derived with the following: 287 * 288 * Log2(words) + 2 = Log2(bytes / 4) + 2 289 * = Log2(bytes) - 2 + 2 290 * = Log2(bytes) 291 */ 292 return field + 2; 293 } 294 295 /* Which cache CCSIDR represents depends on CSSELR value. */ 296 static u32 get_ccsidr(struct kvm_vcpu *vcpu, u32 csselr) 297 { 298 u8 line_size; 299 300 if (vcpu->arch.ccsidr) 301 return vcpu->arch.ccsidr[csselr]; 302 303 line_size = get_min_cache_line_size(csselr & CSSELR_EL1_InD); 304 305 /* 306 * Fabricate a CCSIDR value as the overriding value does not exist. 307 * The real CCSIDR value will not be used as it can vary by the 308 * physical CPU which the vcpu currently resides in. 309 * 310 * The line size is determined with get_min_cache_line_size(), which 311 * should be valid for all CPUs even if they have different cache 312 * configuration. 313 * 314 * The associativity bits are cleared, meaning the geometry of all data 315 * and unified caches (which are guaranteed to be PIPT and thus 316 * non-aliasing) are 1 set and 1 way. 317 * Guests should not be doing cache operations by set/way at all, and 318 * for this reason, we trap them and attempt to infer the intent, so 319 * that we can flush the entire guest's address space at the appropriate 320 * time. The exposed geometry minimizes the number of the traps. 321 * [If guests should attempt to infer aliasing properties from the 322 * geometry (which is not permitted by the architecture), they would 323 * only do so for virtually indexed caches.] 324 * 325 * We don't check if the cache level exists as it is allowed to return 326 * an UNKNOWN value if not. 327 */ 328 return SYS_FIELD_PREP(CCSIDR_EL1, LineSize, line_size - 4); 329 } 330 331 static int set_ccsidr(struct kvm_vcpu *vcpu, u32 csselr, u32 val) 332 { 333 u8 line_size = FIELD_GET(CCSIDR_EL1_LineSize, val) + 4; 334 u32 *ccsidr = vcpu->arch.ccsidr; 335 u32 i; 336 337 if ((val & CCSIDR_EL1_RES0) || 338 line_size < get_min_cache_line_size(csselr & CSSELR_EL1_InD)) 339 return -EINVAL; 340 341 if (!ccsidr) { 342 if (val == get_ccsidr(vcpu, csselr)) 343 return 0; 344 345 ccsidr = kmalloc_array(CSSELR_MAX, sizeof(u32), GFP_KERNEL_ACCOUNT); 346 if (!ccsidr) 347 return -ENOMEM; 348 349 for (i = 0; i < CSSELR_MAX; i++) 350 ccsidr[i] = get_ccsidr(vcpu, i); 351 352 vcpu->arch.ccsidr = ccsidr; 353 } 354 355 ccsidr[csselr] = val; 356 357 return 0; 358 } 359 360 static bool access_rw(struct kvm_vcpu *vcpu, 361 struct sys_reg_params *p, 362 const struct sys_reg_desc *r) 363 { 364 if (p->is_write) 365 vcpu_write_sys_reg(vcpu, p->regval, r->reg); 366 else 367 p->regval = vcpu_read_sys_reg(vcpu, r->reg); 368 369 return true; 370 } 371 372 /* 373 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized). 374 */ 375 static bool access_dcsw(struct kvm_vcpu *vcpu, 376 struct sys_reg_params *p, 377 const struct sys_reg_desc *r) 378 { 379 if (!p->is_write) 380 return read_from_write_only(vcpu, p, r); 381 382 /* 383 * Only track S/W ops if we don't have FWB. It still indicates 384 * that the guest is a bit broken (S/W operations should only 385 * be done by firmware, knowing that there is only a single 386 * CPU left in the system, and certainly not from non-secure 387 * software). 388 */ 389 if (!cpus_have_final_cap(ARM64_HAS_STAGE2_FWB)) 390 kvm_set_way_flush(vcpu); 391 392 return true; 393 } 394 395 static bool access_dcgsw(struct kvm_vcpu *vcpu, 396 struct sys_reg_params *p, 397 const struct sys_reg_desc *r) 398 { 399 if (!kvm_has_mte(vcpu->kvm)) 400 return undef_access(vcpu, p, r); 401 402 /* Treat MTE S/W ops as we treat the classic ones: with contempt */ 403 return access_dcsw(vcpu, p, r); 404 } 405 406 static void get_access_mask(const struct sys_reg_desc *r, u64 *mask, u64 *shift) 407 { 408 switch (r->aarch32_map) { 409 case AA32_LO: 410 *mask = GENMASK_ULL(31, 0); 411 *shift = 0; 412 break; 413 case AA32_HI: 414 *mask = GENMASK_ULL(63, 32); 415 *shift = 32; 416 break; 417 default: 418 *mask = GENMASK_ULL(63, 0); 419 *shift = 0; 420 break; 421 } 422 } 423 424 /* 425 * Generic accessor for VM registers. Only called as long as HCR_TVM 426 * is set. If the guest enables the MMU, we stop trapping the VM 427 * sys_regs and leave it in complete control of the caches. 428 */ 429 static bool access_vm_reg(struct kvm_vcpu *vcpu, 430 struct sys_reg_params *p, 431 const struct sys_reg_desc *r) 432 { 433 bool was_enabled = vcpu_has_cache_enabled(vcpu); 434 u64 val, mask, shift; 435 436 if (reg_to_encoding(r) == SYS_TCR2_EL1 && 437 !kvm_has_feat(vcpu->kvm, ID_AA64MMFR3_EL1, TCRX, IMP)) 438 return undef_access(vcpu, p, r); 439 440 BUG_ON(!p->is_write); 441 442 get_access_mask(r, &mask, &shift); 443 444 if (~mask) { 445 val = vcpu_read_sys_reg(vcpu, r->reg); 446 val &= ~mask; 447 } else { 448 val = 0; 449 } 450 451 val |= (p->regval & (mask >> shift)) << shift; 452 vcpu_write_sys_reg(vcpu, val, r->reg); 453 454 kvm_toggle_cache(vcpu, was_enabled); 455 return true; 456 } 457 458 static bool access_tcr2_el2(struct kvm_vcpu *vcpu, 459 struct sys_reg_params *p, 460 const struct sys_reg_desc *r) 461 { 462 if (!kvm_has_feat(vcpu->kvm, ID_AA64MMFR3_EL1, TCRX, IMP)) { 463 kvm_inject_undefined(vcpu); 464 return false; 465 } 466 467 return access_rw(vcpu, p, r); 468 } 469 470 static bool access_actlr(struct kvm_vcpu *vcpu, 471 struct sys_reg_params *p, 472 const struct sys_reg_desc *r) 473 { 474 u64 mask, shift; 475 476 if (p->is_write) 477 return ignore_write(vcpu, p); 478 479 get_access_mask(r, &mask, &shift); 480 p->regval = (vcpu_read_sys_reg(vcpu, r->reg) & mask) >> shift; 481 482 return true; 483 } 484 485 /* 486 * Trap handler for the GICv3 SGI generation system register. 487 * Forward the request to the VGIC emulation. 488 * The cp15_64 code makes sure this automatically works 489 * for both AArch64 and AArch32 accesses. 490 */ 491 static bool access_gic_sgi(struct kvm_vcpu *vcpu, 492 struct sys_reg_params *p, 493 const struct sys_reg_desc *r) 494 { 495 bool g1; 496 497 if (!kvm_has_gicv3(vcpu->kvm)) 498 return undef_access(vcpu, p, r); 499 500 if (!p->is_write) 501 return read_from_write_only(vcpu, p, r); 502 503 /* 504 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates 505 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group, 506 * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively 507 * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure 508 * group. 509 */ 510 if (p->Op0 == 0) { /* AArch32 */ 511 switch (p->Op1) { 512 default: /* Keep GCC quiet */ 513 case 0: /* ICC_SGI1R */ 514 g1 = true; 515 break; 516 case 1: /* ICC_ASGI1R */ 517 case 2: /* ICC_SGI0R */ 518 g1 = false; 519 break; 520 } 521 } else { /* AArch64 */ 522 switch (p->Op2) { 523 default: /* Keep GCC quiet */ 524 case 5: /* ICC_SGI1R_EL1 */ 525 g1 = true; 526 break; 527 case 6: /* ICC_ASGI1R_EL1 */ 528 case 7: /* ICC_SGI0R_EL1 */ 529 g1 = false; 530 break; 531 } 532 } 533 534 vgic_v3_dispatch_sgi(vcpu, p->regval, g1); 535 536 return true; 537 } 538 539 static bool access_gic_sre(struct kvm_vcpu *vcpu, 540 struct sys_reg_params *p, 541 const struct sys_reg_desc *r) 542 { 543 if (!kvm_has_gicv3(vcpu->kvm)) 544 return undef_access(vcpu, p, r); 545 546 if (p->is_write) 547 return ignore_write(vcpu, p); 548 549 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre; 550 return true; 551 } 552 553 static bool trap_raz_wi(struct kvm_vcpu *vcpu, 554 struct sys_reg_params *p, 555 const struct sys_reg_desc *r) 556 { 557 if (p->is_write) 558 return ignore_write(vcpu, p); 559 else 560 return read_zero(vcpu, p); 561 } 562 563 /* 564 * ARMv8.1 mandates at least a trivial LORegion implementation, where all the 565 * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0 566 * system, these registers should UNDEF. LORID_EL1 being a RO register, we 567 * treat it separately. 568 */ 569 static bool trap_loregion(struct kvm_vcpu *vcpu, 570 struct sys_reg_params *p, 571 const struct sys_reg_desc *r) 572 { 573 u32 sr = reg_to_encoding(r); 574 575 if (!kvm_has_feat(vcpu->kvm, ID_AA64MMFR1_EL1, LO, IMP)) 576 return undef_access(vcpu, p, r); 577 578 if (p->is_write && sr == SYS_LORID_EL1) 579 return write_to_read_only(vcpu, p, r); 580 581 return trap_raz_wi(vcpu, p, r); 582 } 583 584 static bool trap_oslar_el1(struct kvm_vcpu *vcpu, 585 struct sys_reg_params *p, 586 const struct sys_reg_desc *r) 587 { 588 u64 oslsr; 589 590 if (!p->is_write) 591 return read_from_write_only(vcpu, p, r); 592 593 /* Forward the OSLK bit to OSLSR */ 594 oslsr = __vcpu_sys_reg(vcpu, OSLSR_EL1) & ~OSLSR_EL1_OSLK; 595 if (p->regval & OSLAR_EL1_OSLK) 596 oslsr |= OSLSR_EL1_OSLK; 597 598 __vcpu_sys_reg(vcpu, OSLSR_EL1) = oslsr; 599 return true; 600 } 601 602 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu, 603 struct sys_reg_params *p, 604 const struct sys_reg_desc *r) 605 { 606 if (p->is_write) 607 return write_to_read_only(vcpu, p, r); 608 609 p->regval = __vcpu_sys_reg(vcpu, r->reg); 610 return true; 611 } 612 613 static int set_oslsr_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 614 u64 val) 615 { 616 /* 617 * The only modifiable bit is the OSLK bit. Refuse the write if 618 * userspace attempts to change any other bit in the register. 619 */ 620 if ((val ^ rd->val) & ~OSLSR_EL1_OSLK) 621 return -EINVAL; 622 623 __vcpu_sys_reg(vcpu, rd->reg) = val; 624 return 0; 625 } 626 627 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu, 628 struct sys_reg_params *p, 629 const struct sys_reg_desc *r) 630 { 631 if (p->is_write) { 632 return ignore_write(vcpu, p); 633 } else { 634 p->regval = read_sysreg(dbgauthstatus_el1); 635 return true; 636 } 637 } 638 639 /* 640 * We want to avoid world-switching all the DBG registers all the 641 * time: 642 * 643 * - If we've touched any debug register, it is likely that we're 644 * going to touch more of them. It then makes sense to disable the 645 * traps and start doing the save/restore dance 646 * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is 647 * then mandatory to save/restore the registers, as the guest 648 * depends on them. 649 * 650 * For this, we use a DIRTY bit, indicating the guest has modified the 651 * debug registers, used as follow: 652 * 653 * On guest entry: 654 * - If the dirty bit is set (because we're coming back from trapping), 655 * disable the traps, save host registers, restore guest registers. 656 * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), 657 * set the dirty bit, disable the traps, save host registers, 658 * restore guest registers. 659 * - Otherwise, enable the traps 660 * 661 * On guest exit: 662 * - If the dirty bit is set, save guest registers, restore host 663 * registers and clear the dirty bit. This ensure that the host can 664 * now use the debug registers. 665 */ 666 static bool trap_debug_regs(struct kvm_vcpu *vcpu, 667 struct sys_reg_params *p, 668 const struct sys_reg_desc *r) 669 { 670 access_rw(vcpu, p, r); 671 if (p->is_write) 672 vcpu_set_flag(vcpu, DEBUG_DIRTY); 673 674 trace_trap_reg(__func__, r->reg, p->is_write, p->regval); 675 676 return true; 677 } 678 679 /* 680 * reg_to_dbg/dbg_to_reg 681 * 682 * A 32 bit write to a debug register leave top bits alone 683 * A 32 bit read from a debug register only returns the bottom bits 684 * 685 * All writes will set the DEBUG_DIRTY flag to ensure the hyp code 686 * switches between host and guest values in future. 687 */ 688 static void reg_to_dbg(struct kvm_vcpu *vcpu, 689 struct sys_reg_params *p, 690 const struct sys_reg_desc *rd, 691 u64 *dbg_reg) 692 { 693 u64 mask, shift, val; 694 695 get_access_mask(rd, &mask, &shift); 696 697 val = *dbg_reg; 698 val &= ~mask; 699 val |= (p->regval & (mask >> shift)) << shift; 700 *dbg_reg = val; 701 702 vcpu_set_flag(vcpu, DEBUG_DIRTY); 703 } 704 705 static void dbg_to_reg(struct kvm_vcpu *vcpu, 706 struct sys_reg_params *p, 707 const struct sys_reg_desc *rd, 708 u64 *dbg_reg) 709 { 710 u64 mask, shift; 711 712 get_access_mask(rd, &mask, &shift); 713 p->regval = (*dbg_reg & mask) >> shift; 714 } 715 716 static bool trap_bvr(struct kvm_vcpu *vcpu, 717 struct sys_reg_params *p, 718 const struct sys_reg_desc *rd) 719 { 720 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm]; 721 722 if (p->is_write) 723 reg_to_dbg(vcpu, p, rd, dbg_reg); 724 else 725 dbg_to_reg(vcpu, p, rd, dbg_reg); 726 727 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); 728 729 return true; 730 } 731 732 static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 733 u64 val) 734 { 735 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = val; 736 return 0; 737 } 738 739 static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 740 u64 *val) 741 { 742 *val = vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm]; 743 return 0; 744 } 745 746 static u64 reset_bvr(struct kvm_vcpu *vcpu, 747 const struct sys_reg_desc *rd) 748 { 749 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = rd->val; 750 return rd->val; 751 } 752 753 static bool trap_bcr(struct kvm_vcpu *vcpu, 754 struct sys_reg_params *p, 755 const struct sys_reg_desc *rd) 756 { 757 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm]; 758 759 if (p->is_write) 760 reg_to_dbg(vcpu, p, rd, dbg_reg); 761 else 762 dbg_to_reg(vcpu, p, rd, dbg_reg); 763 764 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); 765 766 return true; 767 } 768 769 static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 770 u64 val) 771 { 772 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = val; 773 return 0; 774 } 775 776 static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 777 u64 *val) 778 { 779 *val = vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm]; 780 return 0; 781 } 782 783 static u64 reset_bcr(struct kvm_vcpu *vcpu, 784 const struct sys_reg_desc *rd) 785 { 786 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = rd->val; 787 return rd->val; 788 } 789 790 static bool trap_wvr(struct kvm_vcpu *vcpu, 791 struct sys_reg_params *p, 792 const struct sys_reg_desc *rd) 793 { 794 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]; 795 796 if (p->is_write) 797 reg_to_dbg(vcpu, p, rd, dbg_reg); 798 else 799 dbg_to_reg(vcpu, p, rd, dbg_reg); 800 801 trace_trap_reg(__func__, rd->CRm, p->is_write, 802 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]); 803 804 return true; 805 } 806 807 static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 808 u64 val) 809 { 810 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = val; 811 return 0; 812 } 813 814 static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 815 u64 *val) 816 { 817 *val = vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]; 818 return 0; 819 } 820 821 static u64 reset_wvr(struct kvm_vcpu *vcpu, 822 const struct sys_reg_desc *rd) 823 { 824 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = rd->val; 825 return rd->val; 826 } 827 828 static bool trap_wcr(struct kvm_vcpu *vcpu, 829 struct sys_reg_params *p, 830 const struct sys_reg_desc *rd) 831 { 832 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm]; 833 834 if (p->is_write) 835 reg_to_dbg(vcpu, p, rd, dbg_reg); 836 else 837 dbg_to_reg(vcpu, p, rd, dbg_reg); 838 839 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); 840 841 return true; 842 } 843 844 static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 845 u64 val) 846 { 847 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = val; 848 return 0; 849 } 850 851 static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 852 u64 *val) 853 { 854 *val = vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm]; 855 return 0; 856 } 857 858 static u64 reset_wcr(struct kvm_vcpu *vcpu, 859 const struct sys_reg_desc *rd) 860 { 861 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = rd->val; 862 return rd->val; 863 } 864 865 static u64 reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 866 { 867 u64 amair = read_sysreg(amair_el1); 868 vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1); 869 return amair; 870 } 871 872 static u64 reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 873 { 874 u64 actlr = read_sysreg(actlr_el1); 875 vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1); 876 return actlr; 877 } 878 879 static u64 reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 880 { 881 u64 mpidr; 882 883 /* 884 * Map the vcpu_id into the first three affinity level fields of 885 * the MPIDR. We limit the number of VCPUs in level 0 due to a 886 * limitation to 16 CPUs in that level in the ICC_SGIxR registers 887 * of the GICv3 to be able to address each CPU directly when 888 * sending IPIs. 889 */ 890 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0); 891 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1); 892 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2); 893 mpidr |= (1ULL << 31); 894 vcpu_write_sys_reg(vcpu, mpidr, MPIDR_EL1); 895 896 return mpidr; 897 } 898 899 static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu, 900 const struct sys_reg_desc *r) 901 { 902 if (kvm_vcpu_has_pmu(vcpu)) 903 return 0; 904 905 return REG_HIDDEN; 906 } 907 908 static u64 reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 909 { 910 u64 mask = BIT(ARMV8_PMU_CYCLE_IDX); 911 u8 n = vcpu->kvm->arch.pmcr_n; 912 913 if (n) 914 mask |= GENMASK(n - 1, 0); 915 916 reset_unknown(vcpu, r); 917 __vcpu_sys_reg(vcpu, r->reg) &= mask; 918 919 return __vcpu_sys_reg(vcpu, r->reg); 920 } 921 922 static u64 reset_pmevcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 923 { 924 reset_unknown(vcpu, r); 925 __vcpu_sys_reg(vcpu, r->reg) &= GENMASK(31, 0); 926 927 return __vcpu_sys_reg(vcpu, r->reg); 928 } 929 930 static u64 reset_pmevtyper(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 931 { 932 /* This thing will UNDEF, who cares about the reset value? */ 933 if (!kvm_vcpu_has_pmu(vcpu)) 934 return 0; 935 936 reset_unknown(vcpu, r); 937 __vcpu_sys_reg(vcpu, r->reg) &= kvm_pmu_evtyper_mask(vcpu->kvm); 938 939 return __vcpu_sys_reg(vcpu, r->reg); 940 } 941 942 static u64 reset_pmselr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 943 { 944 reset_unknown(vcpu, r); 945 __vcpu_sys_reg(vcpu, r->reg) &= PMSELR_EL0_SEL_MASK; 946 947 return __vcpu_sys_reg(vcpu, r->reg); 948 } 949 950 static u64 reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 951 { 952 u64 pmcr = 0; 953 954 if (!kvm_supports_32bit_el0()) 955 pmcr |= ARMV8_PMU_PMCR_LC; 956 957 /* 958 * The value of PMCR.N field is included when the 959 * vCPU register is read via kvm_vcpu_read_pmcr(). 960 */ 961 __vcpu_sys_reg(vcpu, r->reg) = pmcr; 962 963 return __vcpu_sys_reg(vcpu, r->reg); 964 } 965 966 static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags) 967 { 968 u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0); 969 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu); 970 971 if (!enabled) 972 kvm_inject_undefined(vcpu); 973 974 return !enabled; 975 } 976 977 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu) 978 { 979 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN); 980 } 981 982 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu) 983 { 984 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN); 985 } 986 987 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu) 988 { 989 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN); 990 } 991 992 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu) 993 { 994 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN); 995 } 996 997 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 998 const struct sys_reg_desc *r) 999 { 1000 u64 val; 1001 1002 if (pmu_access_el0_disabled(vcpu)) 1003 return false; 1004 1005 if (p->is_write) { 1006 /* 1007 * Only update writeable bits of PMCR (continuing into 1008 * kvm_pmu_handle_pmcr() as well) 1009 */ 1010 val = kvm_vcpu_read_pmcr(vcpu); 1011 val &= ~ARMV8_PMU_PMCR_MASK; 1012 val |= p->regval & ARMV8_PMU_PMCR_MASK; 1013 if (!kvm_supports_32bit_el0()) 1014 val |= ARMV8_PMU_PMCR_LC; 1015 kvm_pmu_handle_pmcr(vcpu, val); 1016 } else { 1017 /* PMCR.P & PMCR.C are RAZ */ 1018 val = kvm_vcpu_read_pmcr(vcpu) 1019 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C); 1020 p->regval = val; 1021 } 1022 1023 return true; 1024 } 1025 1026 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1027 const struct sys_reg_desc *r) 1028 { 1029 if (pmu_access_event_counter_el0_disabled(vcpu)) 1030 return false; 1031 1032 if (p->is_write) 1033 __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval; 1034 else 1035 /* return PMSELR.SEL field */ 1036 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0) 1037 & PMSELR_EL0_SEL_MASK; 1038 1039 return true; 1040 } 1041 1042 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1043 const struct sys_reg_desc *r) 1044 { 1045 u64 pmceid, mask, shift; 1046 1047 BUG_ON(p->is_write); 1048 1049 if (pmu_access_el0_disabled(vcpu)) 1050 return false; 1051 1052 get_access_mask(r, &mask, &shift); 1053 1054 pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1)); 1055 pmceid &= mask; 1056 pmceid >>= shift; 1057 1058 p->regval = pmceid; 1059 1060 return true; 1061 } 1062 1063 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx) 1064 { 1065 u64 pmcr, val; 1066 1067 pmcr = kvm_vcpu_read_pmcr(vcpu); 1068 val = FIELD_GET(ARMV8_PMU_PMCR_N, pmcr); 1069 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) { 1070 kvm_inject_undefined(vcpu); 1071 return false; 1072 } 1073 1074 return true; 1075 } 1076 1077 static int get_pmu_evcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 1078 u64 *val) 1079 { 1080 u64 idx; 1081 1082 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 0) 1083 /* PMCCNTR_EL0 */ 1084 idx = ARMV8_PMU_CYCLE_IDX; 1085 else 1086 /* PMEVCNTRn_EL0 */ 1087 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 1088 1089 *val = kvm_pmu_get_counter_value(vcpu, idx); 1090 return 0; 1091 } 1092 1093 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu, 1094 struct sys_reg_params *p, 1095 const struct sys_reg_desc *r) 1096 { 1097 u64 idx = ~0UL; 1098 1099 if (r->CRn == 9 && r->CRm == 13) { 1100 if (r->Op2 == 2) { 1101 /* PMXEVCNTR_EL0 */ 1102 if (pmu_access_event_counter_el0_disabled(vcpu)) 1103 return false; 1104 1105 idx = SYS_FIELD_GET(PMSELR_EL0, SEL, 1106 __vcpu_sys_reg(vcpu, PMSELR_EL0)); 1107 } else if (r->Op2 == 0) { 1108 /* PMCCNTR_EL0 */ 1109 if (pmu_access_cycle_counter_el0_disabled(vcpu)) 1110 return false; 1111 1112 idx = ARMV8_PMU_CYCLE_IDX; 1113 } 1114 } else if (r->CRn == 0 && r->CRm == 9) { 1115 /* PMCCNTR */ 1116 if (pmu_access_event_counter_el0_disabled(vcpu)) 1117 return false; 1118 1119 idx = ARMV8_PMU_CYCLE_IDX; 1120 } else if (r->CRn == 14 && (r->CRm & 12) == 8) { 1121 /* PMEVCNTRn_EL0 */ 1122 if (pmu_access_event_counter_el0_disabled(vcpu)) 1123 return false; 1124 1125 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 1126 } 1127 1128 /* Catch any decoding mistake */ 1129 WARN_ON(idx == ~0UL); 1130 1131 if (!pmu_counter_idx_valid(vcpu, idx)) 1132 return false; 1133 1134 if (p->is_write) { 1135 if (pmu_access_el0_disabled(vcpu)) 1136 return false; 1137 1138 kvm_pmu_set_counter_value(vcpu, idx, p->regval); 1139 } else { 1140 p->regval = kvm_pmu_get_counter_value(vcpu, idx); 1141 } 1142 1143 return true; 1144 } 1145 1146 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1147 const struct sys_reg_desc *r) 1148 { 1149 u64 idx, reg; 1150 1151 if (pmu_access_el0_disabled(vcpu)) 1152 return false; 1153 1154 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) { 1155 /* PMXEVTYPER_EL0 */ 1156 idx = SYS_FIELD_GET(PMSELR_EL0, SEL, __vcpu_sys_reg(vcpu, PMSELR_EL0)); 1157 reg = PMEVTYPER0_EL0 + idx; 1158 } else if (r->CRn == 14 && (r->CRm & 12) == 12) { 1159 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 1160 if (idx == ARMV8_PMU_CYCLE_IDX) 1161 reg = PMCCFILTR_EL0; 1162 else 1163 /* PMEVTYPERn_EL0 */ 1164 reg = PMEVTYPER0_EL0 + idx; 1165 } else { 1166 BUG(); 1167 } 1168 1169 if (!pmu_counter_idx_valid(vcpu, idx)) 1170 return false; 1171 1172 if (p->is_write) { 1173 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx); 1174 kvm_vcpu_pmu_restore_guest(vcpu); 1175 } else { 1176 p->regval = __vcpu_sys_reg(vcpu, reg); 1177 } 1178 1179 return true; 1180 } 1181 1182 static int set_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 val) 1183 { 1184 bool set; 1185 1186 val &= kvm_pmu_valid_counter_mask(vcpu); 1187 1188 switch (r->reg) { 1189 case PMOVSSET_EL0: 1190 /* CRm[1] being set indicates a SET register, and CLR otherwise */ 1191 set = r->CRm & 2; 1192 break; 1193 default: 1194 /* Op2[0] being set indicates a SET register, and CLR otherwise */ 1195 set = r->Op2 & 1; 1196 break; 1197 } 1198 1199 if (set) 1200 __vcpu_sys_reg(vcpu, r->reg) |= val; 1201 else 1202 __vcpu_sys_reg(vcpu, r->reg) &= ~val; 1203 1204 return 0; 1205 } 1206 1207 static int get_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 *val) 1208 { 1209 u64 mask = kvm_pmu_valid_counter_mask(vcpu); 1210 1211 *val = __vcpu_sys_reg(vcpu, r->reg) & mask; 1212 return 0; 1213 } 1214 1215 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1216 const struct sys_reg_desc *r) 1217 { 1218 u64 val, mask; 1219 1220 if (pmu_access_el0_disabled(vcpu)) 1221 return false; 1222 1223 mask = kvm_pmu_valid_counter_mask(vcpu); 1224 if (p->is_write) { 1225 val = p->regval & mask; 1226 if (r->Op2 & 0x1) { 1227 /* accessing PMCNTENSET_EL0 */ 1228 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val; 1229 kvm_pmu_enable_counter_mask(vcpu, val); 1230 kvm_vcpu_pmu_restore_guest(vcpu); 1231 } else { 1232 /* accessing PMCNTENCLR_EL0 */ 1233 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val; 1234 kvm_pmu_disable_counter_mask(vcpu, val); 1235 } 1236 } else { 1237 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0); 1238 } 1239 1240 return true; 1241 } 1242 1243 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1244 const struct sys_reg_desc *r) 1245 { 1246 u64 mask = kvm_pmu_valid_counter_mask(vcpu); 1247 1248 if (check_pmu_access_disabled(vcpu, 0)) 1249 return false; 1250 1251 if (p->is_write) { 1252 u64 val = p->regval & mask; 1253 1254 if (r->Op2 & 0x1) 1255 /* accessing PMINTENSET_EL1 */ 1256 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val; 1257 else 1258 /* accessing PMINTENCLR_EL1 */ 1259 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val; 1260 } else { 1261 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1); 1262 } 1263 1264 return true; 1265 } 1266 1267 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1268 const struct sys_reg_desc *r) 1269 { 1270 u64 mask = kvm_pmu_valid_counter_mask(vcpu); 1271 1272 if (pmu_access_el0_disabled(vcpu)) 1273 return false; 1274 1275 if (p->is_write) { 1276 if (r->CRm & 0x2) 1277 /* accessing PMOVSSET_EL0 */ 1278 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask); 1279 else 1280 /* accessing PMOVSCLR_EL0 */ 1281 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask); 1282 } else { 1283 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0); 1284 } 1285 1286 return true; 1287 } 1288 1289 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1290 const struct sys_reg_desc *r) 1291 { 1292 u64 mask; 1293 1294 if (!p->is_write) 1295 return read_from_write_only(vcpu, p, r); 1296 1297 if (pmu_write_swinc_el0_disabled(vcpu)) 1298 return false; 1299 1300 mask = kvm_pmu_valid_counter_mask(vcpu); 1301 kvm_pmu_software_increment(vcpu, p->regval & mask); 1302 return true; 1303 } 1304 1305 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1306 const struct sys_reg_desc *r) 1307 { 1308 if (p->is_write) { 1309 if (!vcpu_mode_priv(vcpu)) 1310 return undef_access(vcpu, p, r); 1311 1312 __vcpu_sys_reg(vcpu, PMUSERENR_EL0) = 1313 p->regval & ARMV8_PMU_USERENR_MASK; 1314 } else { 1315 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0) 1316 & ARMV8_PMU_USERENR_MASK; 1317 } 1318 1319 return true; 1320 } 1321 1322 static int get_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 1323 u64 *val) 1324 { 1325 *val = kvm_vcpu_read_pmcr(vcpu); 1326 return 0; 1327 } 1328 1329 static int set_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 1330 u64 val) 1331 { 1332 u8 new_n = FIELD_GET(ARMV8_PMU_PMCR_N, val); 1333 struct kvm *kvm = vcpu->kvm; 1334 1335 mutex_lock(&kvm->arch.config_lock); 1336 1337 /* 1338 * The vCPU can't have more counters than the PMU hardware 1339 * implements. Ignore this error to maintain compatibility 1340 * with the existing KVM behavior. 1341 */ 1342 if (!kvm_vm_has_ran_once(kvm) && 1343 new_n <= kvm_arm_pmu_get_max_counters(kvm)) 1344 kvm->arch.pmcr_n = new_n; 1345 1346 mutex_unlock(&kvm->arch.config_lock); 1347 1348 /* 1349 * Ignore writes to RES0 bits, read only bits that are cleared on 1350 * vCPU reset, and writable bits that KVM doesn't support yet. 1351 * (i.e. only PMCR.N and bits [7:0] are mutable from userspace) 1352 * The LP bit is RES0 when FEAT_PMUv3p5 is not supported on the vCPU. 1353 * But, we leave the bit as it is here, as the vCPU's PMUver might 1354 * be changed later (NOTE: the bit will be cleared on first vCPU run 1355 * if necessary). 1356 */ 1357 val &= ARMV8_PMU_PMCR_MASK; 1358 1359 /* The LC bit is RES1 when AArch32 is not supported */ 1360 if (!kvm_supports_32bit_el0()) 1361 val |= ARMV8_PMU_PMCR_LC; 1362 1363 __vcpu_sys_reg(vcpu, r->reg) = val; 1364 return 0; 1365 } 1366 1367 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */ 1368 #define DBG_BCR_BVR_WCR_WVR_EL1(n) \ 1369 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \ 1370 trap_bvr, reset_bvr, 0, 0, get_bvr, set_bvr }, \ 1371 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \ 1372 trap_bcr, reset_bcr, 0, 0, get_bcr, set_bcr }, \ 1373 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \ 1374 trap_wvr, reset_wvr, 0, 0, get_wvr, set_wvr }, \ 1375 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \ 1376 trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr } 1377 1378 #define PMU_SYS_REG(name) \ 1379 SYS_DESC(SYS_##name), .reset = reset_pmu_reg, \ 1380 .visibility = pmu_visibility 1381 1382 /* Macro to expand the PMEVCNTRn_EL0 register */ 1383 #define PMU_PMEVCNTR_EL0(n) \ 1384 { PMU_SYS_REG(PMEVCNTRn_EL0(n)), \ 1385 .reset = reset_pmevcntr, .get_user = get_pmu_evcntr, \ 1386 .access = access_pmu_evcntr, .reg = (PMEVCNTR0_EL0 + n), } 1387 1388 /* Macro to expand the PMEVTYPERn_EL0 register */ 1389 #define PMU_PMEVTYPER_EL0(n) \ 1390 { PMU_SYS_REG(PMEVTYPERn_EL0(n)), \ 1391 .reset = reset_pmevtyper, \ 1392 .access = access_pmu_evtyper, .reg = (PMEVTYPER0_EL0 + n), } 1393 1394 /* Macro to expand the AMU counter and type registers*/ 1395 #define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), undef_access } 1396 #define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), undef_access } 1397 #define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), undef_access } 1398 #define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), undef_access } 1399 1400 static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu, 1401 const struct sys_reg_desc *rd) 1402 { 1403 return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN; 1404 } 1405 1406 /* 1407 * If we land here on a PtrAuth access, that is because we didn't 1408 * fixup the access on exit by allowing the PtrAuth sysregs. The only 1409 * way this happens is when the guest does not have PtrAuth support 1410 * enabled. 1411 */ 1412 #define __PTRAUTH_KEY(k) \ 1413 { SYS_DESC(SYS_## k), undef_access, reset_unknown, k, \ 1414 .visibility = ptrauth_visibility} 1415 1416 #define PTRAUTH_KEY(k) \ 1417 __PTRAUTH_KEY(k ## KEYLO_EL1), \ 1418 __PTRAUTH_KEY(k ## KEYHI_EL1) 1419 1420 static bool access_arch_timer(struct kvm_vcpu *vcpu, 1421 struct sys_reg_params *p, 1422 const struct sys_reg_desc *r) 1423 { 1424 enum kvm_arch_timers tmr; 1425 enum kvm_arch_timer_regs treg; 1426 u64 reg = reg_to_encoding(r); 1427 1428 switch (reg) { 1429 case SYS_CNTP_TVAL_EL0: 1430 case SYS_AARCH32_CNTP_TVAL: 1431 tmr = TIMER_PTIMER; 1432 treg = TIMER_REG_TVAL; 1433 break; 1434 case SYS_CNTP_CTL_EL0: 1435 case SYS_AARCH32_CNTP_CTL: 1436 tmr = TIMER_PTIMER; 1437 treg = TIMER_REG_CTL; 1438 break; 1439 case SYS_CNTP_CVAL_EL0: 1440 case SYS_AARCH32_CNTP_CVAL: 1441 tmr = TIMER_PTIMER; 1442 treg = TIMER_REG_CVAL; 1443 break; 1444 case SYS_CNTPCT_EL0: 1445 case SYS_CNTPCTSS_EL0: 1446 case SYS_AARCH32_CNTPCT: 1447 tmr = TIMER_PTIMER; 1448 treg = TIMER_REG_CNT; 1449 break; 1450 default: 1451 print_sys_reg_msg(p, "%s", "Unhandled trapped timer register"); 1452 return undef_access(vcpu, p, r); 1453 } 1454 1455 if (p->is_write) 1456 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval); 1457 else 1458 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg); 1459 1460 return true; 1461 } 1462 1463 static s64 kvm_arm64_ftr_safe_value(u32 id, const struct arm64_ftr_bits *ftrp, 1464 s64 new, s64 cur) 1465 { 1466 struct arm64_ftr_bits kvm_ftr = *ftrp; 1467 1468 /* Some features have different safe value type in KVM than host features */ 1469 switch (id) { 1470 case SYS_ID_AA64DFR0_EL1: 1471 switch (kvm_ftr.shift) { 1472 case ID_AA64DFR0_EL1_PMUVer_SHIFT: 1473 kvm_ftr.type = FTR_LOWER_SAFE; 1474 break; 1475 case ID_AA64DFR0_EL1_DebugVer_SHIFT: 1476 kvm_ftr.type = FTR_LOWER_SAFE; 1477 break; 1478 } 1479 break; 1480 case SYS_ID_DFR0_EL1: 1481 if (kvm_ftr.shift == ID_DFR0_EL1_PerfMon_SHIFT) 1482 kvm_ftr.type = FTR_LOWER_SAFE; 1483 break; 1484 } 1485 1486 return arm64_ftr_safe_value(&kvm_ftr, new, cur); 1487 } 1488 1489 /* 1490 * arm64_check_features() - Check if a feature register value constitutes 1491 * a subset of features indicated by the idreg's KVM sanitised limit. 1492 * 1493 * This function will check if each feature field of @val is the "safe" value 1494 * against idreg's KVM sanitised limit return from reset() callback. 1495 * If a field value in @val is the same as the one in limit, it is always 1496 * considered the safe value regardless For register fields that are not in 1497 * writable, only the value in limit is considered the safe value. 1498 * 1499 * Return: 0 if all the fields are safe. Otherwise, return negative errno. 1500 */ 1501 static int arm64_check_features(struct kvm_vcpu *vcpu, 1502 const struct sys_reg_desc *rd, 1503 u64 val) 1504 { 1505 const struct arm64_ftr_reg *ftr_reg; 1506 const struct arm64_ftr_bits *ftrp = NULL; 1507 u32 id = reg_to_encoding(rd); 1508 u64 writable_mask = rd->val; 1509 u64 limit = rd->reset(vcpu, rd); 1510 u64 mask = 0; 1511 1512 /* 1513 * Hidden and unallocated ID registers may not have a corresponding 1514 * struct arm64_ftr_reg. Of course, if the register is RAZ we know the 1515 * only safe value is 0. 1516 */ 1517 if (sysreg_visible_as_raz(vcpu, rd)) 1518 return val ? -E2BIG : 0; 1519 1520 ftr_reg = get_arm64_ftr_reg(id); 1521 if (!ftr_reg) 1522 return -EINVAL; 1523 1524 ftrp = ftr_reg->ftr_bits; 1525 1526 for (; ftrp && ftrp->width; ftrp++) { 1527 s64 f_val, f_lim, safe_val; 1528 u64 ftr_mask; 1529 1530 ftr_mask = arm64_ftr_mask(ftrp); 1531 if ((ftr_mask & writable_mask) != ftr_mask) 1532 continue; 1533 1534 f_val = arm64_ftr_value(ftrp, val); 1535 f_lim = arm64_ftr_value(ftrp, limit); 1536 mask |= ftr_mask; 1537 1538 if (f_val == f_lim) 1539 safe_val = f_val; 1540 else 1541 safe_val = kvm_arm64_ftr_safe_value(id, ftrp, f_val, f_lim); 1542 1543 if (safe_val != f_val) 1544 return -E2BIG; 1545 } 1546 1547 /* For fields that are not writable, values in limit are the safe values. */ 1548 if ((val & ~mask) != (limit & ~mask)) 1549 return -E2BIG; 1550 1551 return 0; 1552 } 1553 1554 static u8 pmuver_to_perfmon(u8 pmuver) 1555 { 1556 switch (pmuver) { 1557 case ID_AA64DFR0_EL1_PMUVer_IMP: 1558 return ID_DFR0_EL1_PerfMon_PMUv3; 1559 case ID_AA64DFR0_EL1_PMUVer_IMP_DEF: 1560 return ID_DFR0_EL1_PerfMon_IMPDEF; 1561 default: 1562 /* Anything ARMv8.1+ and NI have the same value. For now. */ 1563 return pmuver; 1564 } 1565 } 1566 1567 /* Read a sanitised cpufeature ID register by sys_reg_desc */ 1568 static u64 __kvm_read_sanitised_id_reg(const struct kvm_vcpu *vcpu, 1569 const struct sys_reg_desc *r) 1570 { 1571 u32 id = reg_to_encoding(r); 1572 u64 val; 1573 1574 if (sysreg_visible_as_raz(vcpu, r)) 1575 return 0; 1576 1577 val = read_sanitised_ftr_reg(id); 1578 1579 switch (id) { 1580 case SYS_ID_AA64PFR1_EL1: 1581 if (!kvm_has_mte(vcpu->kvm)) 1582 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE); 1583 1584 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_SME); 1585 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_RNDR_trap); 1586 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_NMI); 1587 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE_frac); 1588 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_GCS); 1589 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_THE); 1590 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTEX); 1591 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_DF2); 1592 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_PFAR); 1593 break; 1594 case SYS_ID_AA64PFR2_EL1: 1595 /* We only expose FPMR */ 1596 val &= ID_AA64PFR2_EL1_FPMR; 1597 break; 1598 case SYS_ID_AA64ISAR1_EL1: 1599 if (!vcpu_has_ptrauth(vcpu)) 1600 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) | 1601 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) | 1602 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) | 1603 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI)); 1604 break; 1605 case SYS_ID_AA64ISAR2_EL1: 1606 if (!vcpu_has_ptrauth(vcpu)) 1607 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) | 1608 ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3)); 1609 if (!cpus_have_final_cap(ARM64_HAS_WFXT)) 1610 val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT); 1611 break; 1612 case SYS_ID_AA64MMFR2_EL1: 1613 val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK; 1614 break; 1615 case SYS_ID_AA64MMFR3_EL1: 1616 val &= ID_AA64MMFR3_EL1_TCRX | ID_AA64MMFR3_EL1_S1POE | 1617 ID_AA64MMFR3_EL1_S1PIE; 1618 break; 1619 case SYS_ID_MMFR4_EL1: 1620 val &= ~ARM64_FEATURE_MASK(ID_MMFR4_EL1_CCIDX); 1621 break; 1622 } 1623 1624 return val; 1625 } 1626 1627 static u64 kvm_read_sanitised_id_reg(struct kvm_vcpu *vcpu, 1628 const struct sys_reg_desc *r) 1629 { 1630 return __kvm_read_sanitised_id_reg(vcpu, r); 1631 } 1632 1633 static u64 read_id_reg(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 1634 { 1635 return kvm_read_vm_id_reg(vcpu->kvm, reg_to_encoding(r)); 1636 } 1637 1638 static bool is_feature_id_reg(u32 encoding) 1639 { 1640 return (sys_reg_Op0(encoding) == 3 && 1641 (sys_reg_Op1(encoding) < 2 || sys_reg_Op1(encoding) == 3) && 1642 sys_reg_CRn(encoding) == 0 && 1643 sys_reg_CRm(encoding) <= 7); 1644 } 1645 1646 /* 1647 * Return true if the register's (Op0, Op1, CRn, CRm, Op2) is 1648 * (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8, which is the range of ID 1649 * registers KVM maintains on a per-VM basis. 1650 */ 1651 static inline bool is_vm_ftr_id_reg(u32 id) 1652 { 1653 if (id == SYS_CTR_EL0) 1654 return true; 1655 1656 return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 && 1657 sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 && 1658 sys_reg_CRm(id) < 8); 1659 } 1660 1661 static inline bool is_vcpu_ftr_id_reg(u32 id) 1662 { 1663 return is_feature_id_reg(id) && !is_vm_ftr_id_reg(id); 1664 } 1665 1666 static inline bool is_aa32_id_reg(u32 id) 1667 { 1668 return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 && 1669 sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 && 1670 sys_reg_CRm(id) <= 3); 1671 } 1672 1673 static unsigned int id_visibility(const struct kvm_vcpu *vcpu, 1674 const struct sys_reg_desc *r) 1675 { 1676 u32 id = reg_to_encoding(r); 1677 1678 switch (id) { 1679 case SYS_ID_AA64ZFR0_EL1: 1680 if (!vcpu_has_sve(vcpu)) 1681 return REG_RAZ; 1682 break; 1683 } 1684 1685 return 0; 1686 } 1687 1688 static unsigned int aa32_id_visibility(const struct kvm_vcpu *vcpu, 1689 const struct sys_reg_desc *r) 1690 { 1691 /* 1692 * AArch32 ID registers are UNKNOWN if AArch32 isn't implemented at any 1693 * EL. Promote to RAZ/WI in order to guarantee consistency between 1694 * systems. 1695 */ 1696 if (!kvm_supports_32bit_el0()) 1697 return REG_RAZ | REG_USER_WI; 1698 1699 return id_visibility(vcpu, r); 1700 } 1701 1702 static unsigned int raz_visibility(const struct kvm_vcpu *vcpu, 1703 const struct sys_reg_desc *r) 1704 { 1705 return REG_RAZ; 1706 } 1707 1708 /* cpufeature ID register access trap handlers */ 1709 1710 static bool access_id_reg(struct kvm_vcpu *vcpu, 1711 struct sys_reg_params *p, 1712 const struct sys_reg_desc *r) 1713 { 1714 if (p->is_write) 1715 return write_to_read_only(vcpu, p, r); 1716 1717 p->regval = read_id_reg(vcpu, r); 1718 1719 return true; 1720 } 1721 1722 /* Visibility overrides for SVE-specific control registers */ 1723 static unsigned int sve_visibility(const struct kvm_vcpu *vcpu, 1724 const struct sys_reg_desc *rd) 1725 { 1726 if (vcpu_has_sve(vcpu)) 1727 return 0; 1728 1729 return REG_HIDDEN; 1730 } 1731 1732 static unsigned int sme_visibility(const struct kvm_vcpu *vcpu, 1733 const struct sys_reg_desc *rd) 1734 { 1735 if (kvm_has_feat(vcpu->kvm, ID_AA64PFR1_EL1, SME, IMP)) 1736 return 0; 1737 1738 return REG_HIDDEN; 1739 } 1740 1741 static unsigned int fp8_visibility(const struct kvm_vcpu *vcpu, 1742 const struct sys_reg_desc *rd) 1743 { 1744 if (kvm_has_fpmr(vcpu->kvm)) 1745 return 0; 1746 1747 return REG_HIDDEN; 1748 } 1749 1750 static u64 read_sanitised_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, 1751 const struct sys_reg_desc *rd) 1752 { 1753 u64 val = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1754 1755 if (!vcpu_has_sve(vcpu)) 1756 val &= ~ID_AA64PFR0_EL1_SVE_MASK; 1757 1758 /* 1759 * The default is to expose CSV2 == 1 if the HW isn't affected. 1760 * Although this is a per-CPU feature, we make it global because 1761 * asymmetric systems are just a nuisance. 1762 * 1763 * Userspace can override this as long as it doesn't promise 1764 * the impossible. 1765 */ 1766 if (arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED) { 1767 val &= ~ID_AA64PFR0_EL1_CSV2_MASK; 1768 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV2, IMP); 1769 } 1770 if (arm64_get_meltdown_state() == SPECTRE_UNAFFECTED) { 1771 val &= ~ID_AA64PFR0_EL1_CSV3_MASK; 1772 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV3, IMP); 1773 } 1774 1775 if (kvm_vgic_global_state.type == VGIC_V3) { 1776 val &= ~ID_AA64PFR0_EL1_GIC_MASK; 1777 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, GIC, IMP); 1778 } 1779 1780 val &= ~ID_AA64PFR0_EL1_AMU_MASK; 1781 1782 return val; 1783 } 1784 1785 #define ID_REG_LIMIT_FIELD_ENUM(val, reg, field, limit) \ 1786 ({ \ 1787 u64 __f_val = FIELD_GET(reg##_##field##_MASK, val); \ 1788 (val) &= ~reg##_##field##_MASK; \ 1789 (val) |= FIELD_PREP(reg##_##field##_MASK, \ 1790 min(__f_val, \ 1791 (u64)SYS_FIELD_VALUE(reg, field, limit))); \ 1792 (val); \ 1793 }) 1794 1795 static u64 read_sanitised_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, 1796 const struct sys_reg_desc *rd) 1797 { 1798 u64 val = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); 1799 1800 val = ID_REG_LIMIT_FIELD_ENUM(val, ID_AA64DFR0_EL1, DebugVer, V8P8); 1801 1802 /* 1803 * Only initialize the PMU version if the vCPU was configured with one. 1804 */ 1805 val &= ~ID_AA64DFR0_EL1_PMUVer_MASK; 1806 if (kvm_vcpu_has_pmu(vcpu)) 1807 val |= SYS_FIELD_PREP(ID_AA64DFR0_EL1, PMUVer, 1808 kvm_arm_pmu_get_pmuver_limit()); 1809 1810 /* Hide SPE from guests */ 1811 val &= ~ID_AA64DFR0_EL1_PMSVer_MASK; 1812 1813 return val; 1814 } 1815 1816 static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, 1817 const struct sys_reg_desc *rd, 1818 u64 val) 1819 { 1820 u8 debugver = SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, val); 1821 u8 pmuver = SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, val); 1822 1823 /* 1824 * Prior to commit 3d0dba5764b9 ("KVM: arm64: PMU: Move the 1825 * ID_AA64DFR0_EL1.PMUver limit to VM creation"), KVM erroneously 1826 * exposed an IMP_DEF PMU to userspace and the guest on systems w/ 1827 * non-architectural PMUs. Of course, PMUv3 is the only game in town for 1828 * PMU virtualization, so the IMP_DEF value was rather user-hostile. 1829 * 1830 * At minimum, we're on the hook to allow values that were given to 1831 * userspace by KVM. Cover our tracks here and replace the IMP_DEF value 1832 * with a more sensible NI. The value of an ID register changing under 1833 * the nose of the guest is unfortunate, but is certainly no more 1834 * surprising than an ill-guided PMU driver poking at impdef system 1835 * registers that end in an UNDEF... 1836 */ 1837 if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF) 1838 val &= ~ID_AA64DFR0_EL1_PMUVer_MASK; 1839 1840 /* 1841 * ID_AA64DFR0_EL1.DebugVer is one of those awkward fields with a 1842 * nonzero minimum safe value. 1843 */ 1844 if (debugver < ID_AA64DFR0_EL1_DebugVer_IMP) 1845 return -EINVAL; 1846 1847 return set_id_reg(vcpu, rd, val); 1848 } 1849 1850 static u64 read_sanitised_id_dfr0_el1(struct kvm_vcpu *vcpu, 1851 const struct sys_reg_desc *rd) 1852 { 1853 u8 perfmon = pmuver_to_perfmon(kvm_arm_pmu_get_pmuver_limit()); 1854 u64 val = read_sanitised_ftr_reg(SYS_ID_DFR0_EL1); 1855 1856 val &= ~ID_DFR0_EL1_PerfMon_MASK; 1857 if (kvm_vcpu_has_pmu(vcpu)) 1858 val |= SYS_FIELD_PREP(ID_DFR0_EL1, PerfMon, perfmon); 1859 1860 val = ID_REG_LIMIT_FIELD_ENUM(val, ID_DFR0_EL1, CopDbg, Debugv8p8); 1861 1862 return val; 1863 } 1864 1865 static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, 1866 const struct sys_reg_desc *rd, 1867 u64 val) 1868 { 1869 u8 perfmon = SYS_FIELD_GET(ID_DFR0_EL1, PerfMon, val); 1870 u8 copdbg = SYS_FIELD_GET(ID_DFR0_EL1, CopDbg, val); 1871 1872 if (perfmon == ID_DFR0_EL1_PerfMon_IMPDEF) { 1873 val &= ~ID_DFR0_EL1_PerfMon_MASK; 1874 perfmon = 0; 1875 } 1876 1877 /* 1878 * Allow DFR0_EL1.PerfMon to be set from userspace as long as 1879 * it doesn't promise more than what the HW gives us on the 1880 * AArch64 side (as everything is emulated with that), and 1881 * that this is a PMUv3. 1882 */ 1883 if (perfmon != 0 && perfmon < ID_DFR0_EL1_PerfMon_PMUv3) 1884 return -EINVAL; 1885 1886 if (copdbg < ID_DFR0_EL1_CopDbg_Armv8) 1887 return -EINVAL; 1888 1889 return set_id_reg(vcpu, rd, val); 1890 } 1891 1892 /* 1893 * cpufeature ID register user accessors 1894 * 1895 * For now, these registers are immutable for userspace, so no values 1896 * are stored, and for set_id_reg() we don't allow the effective value 1897 * to be changed. 1898 */ 1899 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1900 u64 *val) 1901 { 1902 /* 1903 * Avoid locking if the VM has already started, as the ID registers are 1904 * guaranteed to be invariant at that point. 1905 */ 1906 if (kvm_vm_has_ran_once(vcpu->kvm)) { 1907 *val = read_id_reg(vcpu, rd); 1908 return 0; 1909 } 1910 1911 mutex_lock(&vcpu->kvm->arch.config_lock); 1912 *val = read_id_reg(vcpu, rd); 1913 mutex_unlock(&vcpu->kvm->arch.config_lock); 1914 1915 return 0; 1916 } 1917 1918 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1919 u64 val) 1920 { 1921 u32 id = reg_to_encoding(rd); 1922 int ret; 1923 1924 mutex_lock(&vcpu->kvm->arch.config_lock); 1925 1926 /* 1927 * Once the VM has started the ID registers are immutable. Reject any 1928 * write that does not match the final register value. 1929 */ 1930 if (kvm_vm_has_ran_once(vcpu->kvm)) { 1931 if (val != read_id_reg(vcpu, rd)) 1932 ret = -EBUSY; 1933 else 1934 ret = 0; 1935 1936 mutex_unlock(&vcpu->kvm->arch.config_lock); 1937 return ret; 1938 } 1939 1940 ret = arm64_check_features(vcpu, rd, val); 1941 if (!ret) 1942 kvm_set_vm_id_reg(vcpu->kvm, id, val); 1943 1944 mutex_unlock(&vcpu->kvm->arch.config_lock); 1945 1946 /* 1947 * arm64_check_features() returns -E2BIG to indicate the register's 1948 * feature set is a superset of the maximally-allowed register value. 1949 * While it would be nice to precisely describe this to userspace, the 1950 * existing UAPI for KVM_SET_ONE_REG has it that invalid register 1951 * writes return -EINVAL. 1952 */ 1953 if (ret == -E2BIG) 1954 ret = -EINVAL; 1955 return ret; 1956 } 1957 1958 void kvm_set_vm_id_reg(struct kvm *kvm, u32 reg, u64 val) 1959 { 1960 u64 *p = __vm_id_reg(&kvm->arch, reg); 1961 1962 lockdep_assert_held(&kvm->arch.config_lock); 1963 1964 if (KVM_BUG_ON(kvm_vm_has_ran_once(kvm) || !p, kvm)) 1965 return; 1966 1967 *p = val; 1968 } 1969 1970 static int get_raz_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1971 u64 *val) 1972 { 1973 *val = 0; 1974 return 0; 1975 } 1976 1977 static int set_wi_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1978 u64 val) 1979 { 1980 return 0; 1981 } 1982 1983 static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1984 const struct sys_reg_desc *r) 1985 { 1986 if (p->is_write) 1987 return write_to_read_only(vcpu, p, r); 1988 1989 p->regval = kvm_read_vm_id_reg(vcpu->kvm, SYS_CTR_EL0); 1990 return true; 1991 } 1992 1993 static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1994 const struct sys_reg_desc *r) 1995 { 1996 if (p->is_write) 1997 return write_to_read_only(vcpu, p, r); 1998 1999 p->regval = __vcpu_sys_reg(vcpu, r->reg); 2000 return true; 2001 } 2002 2003 /* 2004 * Fabricate a CLIDR_EL1 value instead of using the real value, which can vary 2005 * by the physical CPU which the vcpu currently resides in. 2006 */ 2007 static u64 reset_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 2008 { 2009 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0); 2010 u64 clidr; 2011 u8 loc; 2012 2013 if ((ctr_el0 & CTR_EL0_IDC)) { 2014 /* 2015 * Data cache clean to the PoU is not required so LoUU and LoUIS 2016 * will not be set and a unified cache, which will be marked as 2017 * LoC, will be added. 2018 * 2019 * If not DIC, let the unified cache L2 so that an instruction 2020 * cache can be added as L1 later. 2021 */ 2022 loc = (ctr_el0 & CTR_EL0_DIC) ? 1 : 2; 2023 clidr = CACHE_TYPE_UNIFIED << CLIDR_CTYPE_SHIFT(loc); 2024 } else { 2025 /* 2026 * Data cache clean to the PoU is required so let L1 have a data 2027 * cache and mark it as LoUU and LoUIS. As L1 has a data cache, 2028 * it can be marked as LoC too. 2029 */ 2030 loc = 1; 2031 clidr = 1 << CLIDR_LOUU_SHIFT; 2032 clidr |= 1 << CLIDR_LOUIS_SHIFT; 2033 clidr |= CACHE_TYPE_DATA << CLIDR_CTYPE_SHIFT(1); 2034 } 2035 2036 /* 2037 * Instruction cache invalidation to the PoU is required so let L1 have 2038 * an instruction cache. If L1 already has a data cache, it will be 2039 * CACHE_TYPE_SEPARATE. 2040 */ 2041 if (!(ctr_el0 & CTR_EL0_DIC)) 2042 clidr |= CACHE_TYPE_INST << CLIDR_CTYPE_SHIFT(1); 2043 2044 clidr |= loc << CLIDR_LOC_SHIFT; 2045 2046 /* 2047 * Add tag cache unified to data cache. Allocation tags and data are 2048 * unified in a cache line so that it looks valid even if there is only 2049 * one cache line. 2050 */ 2051 if (kvm_has_mte(vcpu->kvm)) 2052 clidr |= 2ULL << CLIDR_TTYPE_SHIFT(loc); 2053 2054 __vcpu_sys_reg(vcpu, r->reg) = clidr; 2055 2056 return __vcpu_sys_reg(vcpu, r->reg); 2057 } 2058 2059 static int set_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 2060 u64 val) 2061 { 2062 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0); 2063 u64 idc = !CLIDR_LOC(val) || (!CLIDR_LOUIS(val) && !CLIDR_LOUU(val)); 2064 2065 if ((val & CLIDR_EL1_RES0) || (!(ctr_el0 & CTR_EL0_IDC) && idc)) 2066 return -EINVAL; 2067 2068 __vcpu_sys_reg(vcpu, rd->reg) = val; 2069 2070 return 0; 2071 } 2072 2073 static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2074 const struct sys_reg_desc *r) 2075 { 2076 int reg = r->reg; 2077 2078 if (p->is_write) 2079 vcpu_write_sys_reg(vcpu, p->regval, reg); 2080 else 2081 p->regval = vcpu_read_sys_reg(vcpu, reg); 2082 return true; 2083 } 2084 2085 static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2086 const struct sys_reg_desc *r) 2087 { 2088 u32 csselr; 2089 2090 if (p->is_write) 2091 return write_to_read_only(vcpu, p, r); 2092 2093 csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1); 2094 csselr &= CSSELR_EL1_Level | CSSELR_EL1_InD; 2095 if (csselr < CSSELR_MAX) 2096 p->regval = get_ccsidr(vcpu, csselr); 2097 2098 return true; 2099 } 2100 2101 static unsigned int mte_visibility(const struct kvm_vcpu *vcpu, 2102 const struct sys_reg_desc *rd) 2103 { 2104 if (kvm_has_mte(vcpu->kvm)) 2105 return 0; 2106 2107 return REG_HIDDEN; 2108 } 2109 2110 #define MTE_REG(name) { \ 2111 SYS_DESC(SYS_##name), \ 2112 .access = undef_access, \ 2113 .reset = reset_unknown, \ 2114 .reg = name, \ 2115 .visibility = mte_visibility, \ 2116 } 2117 2118 static unsigned int el2_visibility(const struct kvm_vcpu *vcpu, 2119 const struct sys_reg_desc *rd) 2120 { 2121 if (vcpu_has_nv(vcpu)) 2122 return 0; 2123 2124 return REG_HIDDEN; 2125 } 2126 2127 static bool bad_vncr_trap(struct kvm_vcpu *vcpu, 2128 struct sys_reg_params *p, 2129 const struct sys_reg_desc *r) 2130 { 2131 /* 2132 * We really shouldn't be here, and this is likely the result 2133 * of a misconfigured trap, as this register should target the 2134 * VNCR page, and nothing else. 2135 */ 2136 return bad_trap(vcpu, p, r, 2137 "trap of VNCR-backed register"); 2138 } 2139 2140 static bool bad_redir_trap(struct kvm_vcpu *vcpu, 2141 struct sys_reg_params *p, 2142 const struct sys_reg_desc *r) 2143 { 2144 /* 2145 * We really shouldn't be here, and this is likely the result 2146 * of a misconfigured trap, as this register should target the 2147 * corresponding EL1, and nothing else. 2148 */ 2149 return bad_trap(vcpu, p, r, 2150 "trap of EL2 register redirected to EL1"); 2151 } 2152 2153 #define EL2_REG(name, acc, rst, v) { \ 2154 SYS_DESC(SYS_##name), \ 2155 .access = acc, \ 2156 .reset = rst, \ 2157 .reg = name, \ 2158 .visibility = el2_visibility, \ 2159 .val = v, \ 2160 } 2161 2162 #define EL2_REG_VNCR(name, rst, v) EL2_REG(name, bad_vncr_trap, rst, v) 2163 #define EL2_REG_REDIR(name, rst, v) EL2_REG(name, bad_redir_trap, rst, v) 2164 2165 /* 2166 * Since reset() callback and field val are not used for idregs, they will be 2167 * used for specific purposes for idregs. 2168 * The reset() would return KVM sanitised register value. The value would be the 2169 * same as the host kernel sanitised value if there is no KVM sanitisation. 2170 * The val would be used as a mask indicating writable fields for the idreg. 2171 * Only bits with 1 are writable from userspace. This mask might not be 2172 * necessary in the future whenever all ID registers are enabled as writable 2173 * from userspace. 2174 */ 2175 2176 #define ID_DESC(name) \ 2177 SYS_DESC(SYS_##name), \ 2178 .access = access_id_reg, \ 2179 .get_user = get_id_reg \ 2180 2181 /* sys_reg_desc initialiser for known cpufeature ID registers */ 2182 #define ID_SANITISED(name) { \ 2183 ID_DESC(name), \ 2184 .set_user = set_id_reg, \ 2185 .visibility = id_visibility, \ 2186 .reset = kvm_read_sanitised_id_reg, \ 2187 .val = 0, \ 2188 } 2189 2190 /* sys_reg_desc initialiser for known cpufeature ID registers */ 2191 #define AA32_ID_SANITISED(name) { \ 2192 ID_DESC(name), \ 2193 .set_user = set_id_reg, \ 2194 .visibility = aa32_id_visibility, \ 2195 .reset = kvm_read_sanitised_id_reg, \ 2196 .val = 0, \ 2197 } 2198 2199 /* sys_reg_desc initialiser for writable ID registers */ 2200 #define ID_WRITABLE(name, mask) { \ 2201 ID_DESC(name), \ 2202 .set_user = set_id_reg, \ 2203 .visibility = id_visibility, \ 2204 .reset = kvm_read_sanitised_id_reg, \ 2205 .val = mask, \ 2206 } 2207 2208 /* 2209 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID 2210 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2 2211 * (1 <= crm < 8, 0 <= Op2 < 8). 2212 */ 2213 #define ID_UNALLOCATED(crm, op2) { \ 2214 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \ 2215 .access = access_id_reg, \ 2216 .get_user = get_id_reg, \ 2217 .set_user = set_id_reg, \ 2218 .visibility = raz_visibility, \ 2219 .reset = kvm_read_sanitised_id_reg, \ 2220 .val = 0, \ 2221 } 2222 2223 /* 2224 * sys_reg_desc initialiser for known ID registers that we hide from guests. 2225 * For now, these are exposed just like unallocated ID regs: they appear 2226 * RAZ for the guest. 2227 */ 2228 #define ID_HIDDEN(name) { \ 2229 ID_DESC(name), \ 2230 .set_user = set_id_reg, \ 2231 .visibility = raz_visibility, \ 2232 .reset = kvm_read_sanitised_id_reg, \ 2233 .val = 0, \ 2234 } 2235 2236 static bool access_sp_el1(struct kvm_vcpu *vcpu, 2237 struct sys_reg_params *p, 2238 const struct sys_reg_desc *r) 2239 { 2240 if (p->is_write) 2241 __vcpu_sys_reg(vcpu, SP_EL1) = p->regval; 2242 else 2243 p->regval = __vcpu_sys_reg(vcpu, SP_EL1); 2244 2245 return true; 2246 } 2247 2248 static bool access_elr(struct kvm_vcpu *vcpu, 2249 struct sys_reg_params *p, 2250 const struct sys_reg_desc *r) 2251 { 2252 if (p->is_write) 2253 vcpu_write_sys_reg(vcpu, p->regval, ELR_EL1); 2254 else 2255 p->regval = vcpu_read_sys_reg(vcpu, ELR_EL1); 2256 2257 return true; 2258 } 2259 2260 static bool access_spsr(struct kvm_vcpu *vcpu, 2261 struct sys_reg_params *p, 2262 const struct sys_reg_desc *r) 2263 { 2264 if (p->is_write) 2265 __vcpu_sys_reg(vcpu, SPSR_EL1) = p->regval; 2266 else 2267 p->regval = __vcpu_sys_reg(vcpu, SPSR_EL1); 2268 2269 return true; 2270 } 2271 2272 static bool access_cntkctl_el12(struct kvm_vcpu *vcpu, 2273 struct sys_reg_params *p, 2274 const struct sys_reg_desc *r) 2275 { 2276 if (p->is_write) 2277 __vcpu_sys_reg(vcpu, CNTKCTL_EL1) = p->regval; 2278 else 2279 p->regval = __vcpu_sys_reg(vcpu, CNTKCTL_EL1); 2280 2281 return true; 2282 } 2283 2284 static u64 reset_hcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 2285 { 2286 u64 val = r->val; 2287 2288 if (!cpus_have_final_cap(ARM64_HAS_HCR_NV1)) 2289 val |= HCR_E2H; 2290 2291 return __vcpu_sys_reg(vcpu, r->reg) = val; 2292 } 2293 2294 static unsigned int sve_el2_visibility(const struct kvm_vcpu *vcpu, 2295 const struct sys_reg_desc *rd) 2296 { 2297 unsigned int r; 2298 2299 r = el2_visibility(vcpu, rd); 2300 if (r) 2301 return r; 2302 2303 return sve_visibility(vcpu, rd); 2304 } 2305 2306 static bool access_zcr_el2(struct kvm_vcpu *vcpu, 2307 struct sys_reg_params *p, 2308 const struct sys_reg_desc *r) 2309 { 2310 unsigned int vq; 2311 2312 if (guest_hyp_sve_traps_enabled(vcpu)) { 2313 kvm_inject_nested_sve_trap(vcpu); 2314 return true; 2315 } 2316 2317 if (!p->is_write) { 2318 p->regval = vcpu_read_sys_reg(vcpu, ZCR_EL2); 2319 return true; 2320 } 2321 2322 vq = SYS_FIELD_GET(ZCR_ELx, LEN, p->regval) + 1; 2323 vq = min(vq, vcpu_sve_max_vq(vcpu)); 2324 vcpu_write_sys_reg(vcpu, vq - 1, ZCR_EL2); 2325 return true; 2326 } 2327 2328 static unsigned int s1poe_visibility(const struct kvm_vcpu *vcpu, 2329 const struct sys_reg_desc *rd) 2330 { 2331 if (kvm_has_feat(vcpu->kvm, ID_AA64MMFR3_EL1, S1POE, IMP)) 2332 return 0; 2333 2334 return REG_HIDDEN; 2335 } 2336 2337 /* 2338 * Architected system registers. 2339 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2 2340 * 2341 * Debug handling: We do trap most, if not all debug related system 2342 * registers. The implementation is good enough to ensure that a guest 2343 * can use these with minimal performance degradation. The drawback is 2344 * that we don't implement any of the external debug architecture. 2345 * This should be revisited if we ever encounter a more demanding 2346 * guest... 2347 */ 2348 static const struct sys_reg_desc sys_reg_descs[] = { 2349 DBG_BCR_BVR_WCR_WVR_EL1(0), 2350 DBG_BCR_BVR_WCR_WVR_EL1(1), 2351 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 }, 2352 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 }, 2353 DBG_BCR_BVR_WCR_WVR_EL1(2), 2354 DBG_BCR_BVR_WCR_WVR_EL1(3), 2355 DBG_BCR_BVR_WCR_WVR_EL1(4), 2356 DBG_BCR_BVR_WCR_WVR_EL1(5), 2357 DBG_BCR_BVR_WCR_WVR_EL1(6), 2358 DBG_BCR_BVR_WCR_WVR_EL1(7), 2359 DBG_BCR_BVR_WCR_WVR_EL1(8), 2360 DBG_BCR_BVR_WCR_WVR_EL1(9), 2361 DBG_BCR_BVR_WCR_WVR_EL1(10), 2362 DBG_BCR_BVR_WCR_WVR_EL1(11), 2363 DBG_BCR_BVR_WCR_WVR_EL1(12), 2364 DBG_BCR_BVR_WCR_WVR_EL1(13), 2365 DBG_BCR_BVR_WCR_WVR_EL1(14), 2366 DBG_BCR_BVR_WCR_WVR_EL1(15), 2367 2368 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi }, 2369 { SYS_DESC(SYS_OSLAR_EL1), trap_oslar_el1 }, 2370 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1, 2371 OSLSR_EL1_OSLM_IMPLEMENTED, .set_user = set_oslsr_el1, }, 2372 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi }, 2373 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi }, 2374 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi }, 2375 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi }, 2376 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 }, 2377 2378 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi }, 2379 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi }, 2380 // DBGDTR[TR]X_EL0 share the same encoding 2381 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi }, 2382 2383 { SYS_DESC(SYS_DBGVCR32_EL2), undef_access, reset_val, DBGVCR32_EL2, 0 }, 2384 2385 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 }, 2386 2387 /* 2388 * ID regs: all ID_SANITISED() entries here must have corresponding 2389 * entries in arm64_ftr_regs[]. 2390 */ 2391 2392 /* AArch64 mappings of the AArch32 ID registers */ 2393 /* CRm=1 */ 2394 AA32_ID_SANITISED(ID_PFR0_EL1), 2395 AA32_ID_SANITISED(ID_PFR1_EL1), 2396 { SYS_DESC(SYS_ID_DFR0_EL1), 2397 .access = access_id_reg, 2398 .get_user = get_id_reg, 2399 .set_user = set_id_dfr0_el1, 2400 .visibility = aa32_id_visibility, 2401 .reset = read_sanitised_id_dfr0_el1, 2402 .val = ID_DFR0_EL1_PerfMon_MASK | 2403 ID_DFR0_EL1_CopDbg_MASK, }, 2404 ID_HIDDEN(ID_AFR0_EL1), 2405 AA32_ID_SANITISED(ID_MMFR0_EL1), 2406 AA32_ID_SANITISED(ID_MMFR1_EL1), 2407 AA32_ID_SANITISED(ID_MMFR2_EL1), 2408 AA32_ID_SANITISED(ID_MMFR3_EL1), 2409 2410 /* CRm=2 */ 2411 AA32_ID_SANITISED(ID_ISAR0_EL1), 2412 AA32_ID_SANITISED(ID_ISAR1_EL1), 2413 AA32_ID_SANITISED(ID_ISAR2_EL1), 2414 AA32_ID_SANITISED(ID_ISAR3_EL1), 2415 AA32_ID_SANITISED(ID_ISAR4_EL1), 2416 AA32_ID_SANITISED(ID_ISAR5_EL1), 2417 AA32_ID_SANITISED(ID_MMFR4_EL1), 2418 AA32_ID_SANITISED(ID_ISAR6_EL1), 2419 2420 /* CRm=3 */ 2421 AA32_ID_SANITISED(MVFR0_EL1), 2422 AA32_ID_SANITISED(MVFR1_EL1), 2423 AA32_ID_SANITISED(MVFR2_EL1), 2424 ID_UNALLOCATED(3,3), 2425 AA32_ID_SANITISED(ID_PFR2_EL1), 2426 ID_HIDDEN(ID_DFR1_EL1), 2427 AA32_ID_SANITISED(ID_MMFR5_EL1), 2428 ID_UNALLOCATED(3,7), 2429 2430 /* AArch64 ID registers */ 2431 /* CRm=4 */ 2432 { SYS_DESC(SYS_ID_AA64PFR0_EL1), 2433 .access = access_id_reg, 2434 .get_user = get_id_reg, 2435 .set_user = set_id_reg, 2436 .reset = read_sanitised_id_aa64pfr0_el1, 2437 .val = ~(ID_AA64PFR0_EL1_AMU | 2438 ID_AA64PFR0_EL1_MPAM | 2439 ID_AA64PFR0_EL1_SVE | 2440 ID_AA64PFR0_EL1_RAS | 2441 ID_AA64PFR0_EL1_AdvSIMD | 2442 ID_AA64PFR0_EL1_FP), }, 2443 ID_WRITABLE(ID_AA64PFR1_EL1, ~(ID_AA64PFR1_EL1_PFAR | 2444 ID_AA64PFR1_EL1_DF2 | 2445 ID_AA64PFR1_EL1_MTEX | 2446 ID_AA64PFR1_EL1_THE | 2447 ID_AA64PFR1_EL1_GCS | 2448 ID_AA64PFR1_EL1_MTE_frac | 2449 ID_AA64PFR1_EL1_NMI | 2450 ID_AA64PFR1_EL1_RNDR_trap | 2451 ID_AA64PFR1_EL1_SME | 2452 ID_AA64PFR1_EL1_RES0 | 2453 ID_AA64PFR1_EL1_MPAM_frac | 2454 ID_AA64PFR1_EL1_RAS_frac | 2455 ID_AA64PFR1_EL1_MTE)), 2456 ID_WRITABLE(ID_AA64PFR2_EL1, ID_AA64PFR2_EL1_FPMR), 2457 ID_UNALLOCATED(4,3), 2458 ID_WRITABLE(ID_AA64ZFR0_EL1, ~ID_AA64ZFR0_EL1_RES0), 2459 ID_HIDDEN(ID_AA64SMFR0_EL1), 2460 ID_UNALLOCATED(4,6), 2461 ID_WRITABLE(ID_AA64FPFR0_EL1, ~ID_AA64FPFR0_EL1_RES0), 2462 2463 /* CRm=5 */ 2464 { SYS_DESC(SYS_ID_AA64DFR0_EL1), 2465 .access = access_id_reg, 2466 .get_user = get_id_reg, 2467 .set_user = set_id_aa64dfr0_el1, 2468 .reset = read_sanitised_id_aa64dfr0_el1, 2469 /* 2470 * Prior to FEAT_Debugv8.9, the architecture defines context-aware 2471 * breakpoints (CTX_CMPs) as the highest numbered breakpoints (BRPs). 2472 * KVM does not trap + emulate the breakpoint registers, and as such 2473 * cannot support a layout that misaligns with the underlying hardware. 2474 * While it may be possible to describe a subset that aligns with 2475 * hardware, just prevent changes to BRPs and CTX_CMPs altogether for 2476 * simplicity. 2477 * 2478 * See DDI0487K.a, section D2.8.3 Breakpoint types and linking 2479 * of breakpoints for more details. 2480 */ 2481 .val = ID_AA64DFR0_EL1_DoubleLock_MASK | 2482 ID_AA64DFR0_EL1_WRPs_MASK | 2483 ID_AA64DFR0_EL1_PMUVer_MASK | 2484 ID_AA64DFR0_EL1_DebugVer_MASK, }, 2485 ID_SANITISED(ID_AA64DFR1_EL1), 2486 ID_UNALLOCATED(5,2), 2487 ID_UNALLOCATED(5,3), 2488 ID_HIDDEN(ID_AA64AFR0_EL1), 2489 ID_HIDDEN(ID_AA64AFR1_EL1), 2490 ID_UNALLOCATED(5,6), 2491 ID_UNALLOCATED(5,7), 2492 2493 /* CRm=6 */ 2494 ID_WRITABLE(ID_AA64ISAR0_EL1, ~ID_AA64ISAR0_EL1_RES0), 2495 ID_WRITABLE(ID_AA64ISAR1_EL1, ~(ID_AA64ISAR1_EL1_GPI | 2496 ID_AA64ISAR1_EL1_GPA | 2497 ID_AA64ISAR1_EL1_API | 2498 ID_AA64ISAR1_EL1_APA)), 2499 ID_WRITABLE(ID_AA64ISAR2_EL1, ~(ID_AA64ISAR2_EL1_RES0 | 2500 ID_AA64ISAR2_EL1_APA3 | 2501 ID_AA64ISAR2_EL1_GPA3)), 2502 ID_UNALLOCATED(6,3), 2503 ID_UNALLOCATED(6,4), 2504 ID_UNALLOCATED(6,5), 2505 ID_UNALLOCATED(6,6), 2506 ID_UNALLOCATED(6,7), 2507 2508 /* CRm=7 */ 2509 ID_WRITABLE(ID_AA64MMFR0_EL1, ~(ID_AA64MMFR0_EL1_RES0 | 2510 ID_AA64MMFR0_EL1_TGRAN4_2 | 2511 ID_AA64MMFR0_EL1_TGRAN64_2 | 2512 ID_AA64MMFR0_EL1_TGRAN16_2)), 2513 ID_WRITABLE(ID_AA64MMFR1_EL1, ~(ID_AA64MMFR1_EL1_RES0 | 2514 ID_AA64MMFR1_EL1_HCX | 2515 ID_AA64MMFR1_EL1_TWED | 2516 ID_AA64MMFR1_EL1_XNX | 2517 ID_AA64MMFR1_EL1_VH | 2518 ID_AA64MMFR1_EL1_VMIDBits)), 2519 ID_WRITABLE(ID_AA64MMFR2_EL1, ~(ID_AA64MMFR2_EL1_RES0 | 2520 ID_AA64MMFR2_EL1_EVT | 2521 ID_AA64MMFR2_EL1_FWB | 2522 ID_AA64MMFR2_EL1_IDS | 2523 ID_AA64MMFR2_EL1_NV | 2524 ID_AA64MMFR2_EL1_CCIDX)), 2525 ID_WRITABLE(ID_AA64MMFR3_EL1, (ID_AA64MMFR3_EL1_TCRX | 2526 ID_AA64MMFR3_EL1_S1PIE | 2527 ID_AA64MMFR3_EL1_S1POE)), 2528 ID_SANITISED(ID_AA64MMFR4_EL1), 2529 ID_UNALLOCATED(7,5), 2530 ID_UNALLOCATED(7,6), 2531 ID_UNALLOCATED(7,7), 2532 2533 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 }, 2534 { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 }, 2535 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 }, 2536 2537 MTE_REG(RGSR_EL1), 2538 MTE_REG(GCR_EL1), 2539 2540 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility }, 2541 { SYS_DESC(SYS_TRFCR_EL1), undef_access }, 2542 { SYS_DESC(SYS_SMPRI_EL1), undef_access }, 2543 { SYS_DESC(SYS_SMCR_EL1), undef_access }, 2544 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 }, 2545 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 }, 2546 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 }, 2547 { SYS_DESC(SYS_TCR2_EL1), access_vm_reg, reset_val, TCR2_EL1, 0 }, 2548 2549 PTRAUTH_KEY(APIA), 2550 PTRAUTH_KEY(APIB), 2551 PTRAUTH_KEY(APDA), 2552 PTRAUTH_KEY(APDB), 2553 PTRAUTH_KEY(APGA), 2554 2555 { SYS_DESC(SYS_SPSR_EL1), access_spsr}, 2556 { SYS_DESC(SYS_ELR_EL1), access_elr}, 2557 2558 { SYS_DESC(SYS_ICC_PMR_EL1), undef_access }, 2559 2560 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 }, 2561 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 }, 2562 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 }, 2563 2564 { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi }, 2565 { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi }, 2566 { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi }, 2567 { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi }, 2568 { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi }, 2569 { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi }, 2570 { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi }, 2571 { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi }, 2572 2573 MTE_REG(TFSR_EL1), 2574 MTE_REG(TFSRE0_EL1), 2575 2576 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 }, 2577 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 }, 2578 2579 { SYS_DESC(SYS_PMSCR_EL1), undef_access }, 2580 { SYS_DESC(SYS_PMSNEVFR_EL1), undef_access }, 2581 { SYS_DESC(SYS_PMSICR_EL1), undef_access }, 2582 { SYS_DESC(SYS_PMSIRR_EL1), undef_access }, 2583 { SYS_DESC(SYS_PMSFCR_EL1), undef_access }, 2584 { SYS_DESC(SYS_PMSEVFR_EL1), undef_access }, 2585 { SYS_DESC(SYS_PMSLATFR_EL1), undef_access }, 2586 { SYS_DESC(SYS_PMSIDR_EL1), undef_access }, 2587 { SYS_DESC(SYS_PMBLIMITR_EL1), undef_access }, 2588 { SYS_DESC(SYS_PMBPTR_EL1), undef_access }, 2589 { SYS_DESC(SYS_PMBSR_EL1), undef_access }, 2590 /* PMBIDR_EL1 is not trapped */ 2591 2592 { PMU_SYS_REG(PMINTENSET_EL1), 2593 .access = access_pminten, .reg = PMINTENSET_EL1, 2594 .get_user = get_pmreg, .set_user = set_pmreg }, 2595 { PMU_SYS_REG(PMINTENCLR_EL1), 2596 .access = access_pminten, .reg = PMINTENSET_EL1, 2597 .get_user = get_pmreg, .set_user = set_pmreg }, 2598 { SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi }, 2599 2600 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 }, 2601 { SYS_DESC(SYS_PIRE0_EL1), NULL, reset_unknown, PIRE0_EL1 }, 2602 { SYS_DESC(SYS_PIR_EL1), NULL, reset_unknown, PIR_EL1 }, 2603 { SYS_DESC(SYS_POR_EL1), NULL, reset_unknown, POR_EL1, 2604 .visibility = s1poe_visibility }, 2605 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 }, 2606 2607 { SYS_DESC(SYS_LORSA_EL1), trap_loregion }, 2608 { SYS_DESC(SYS_LOREA_EL1), trap_loregion }, 2609 { SYS_DESC(SYS_LORN_EL1), trap_loregion }, 2610 { SYS_DESC(SYS_LORC_EL1), trap_loregion }, 2611 { SYS_DESC(SYS_LORID_EL1), trap_loregion }, 2612 2613 { SYS_DESC(SYS_VBAR_EL1), access_rw, reset_val, VBAR_EL1, 0 }, 2614 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 }, 2615 2616 { SYS_DESC(SYS_ICC_IAR0_EL1), undef_access }, 2617 { SYS_DESC(SYS_ICC_EOIR0_EL1), undef_access }, 2618 { SYS_DESC(SYS_ICC_HPPIR0_EL1), undef_access }, 2619 { SYS_DESC(SYS_ICC_BPR0_EL1), undef_access }, 2620 { SYS_DESC(SYS_ICC_AP0R0_EL1), undef_access }, 2621 { SYS_DESC(SYS_ICC_AP0R1_EL1), undef_access }, 2622 { SYS_DESC(SYS_ICC_AP0R2_EL1), undef_access }, 2623 { SYS_DESC(SYS_ICC_AP0R3_EL1), undef_access }, 2624 { SYS_DESC(SYS_ICC_AP1R0_EL1), undef_access }, 2625 { SYS_DESC(SYS_ICC_AP1R1_EL1), undef_access }, 2626 { SYS_DESC(SYS_ICC_AP1R2_EL1), undef_access }, 2627 { SYS_DESC(SYS_ICC_AP1R3_EL1), undef_access }, 2628 { SYS_DESC(SYS_ICC_DIR_EL1), undef_access }, 2629 { SYS_DESC(SYS_ICC_RPR_EL1), undef_access }, 2630 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi }, 2631 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi }, 2632 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi }, 2633 { SYS_DESC(SYS_ICC_IAR1_EL1), undef_access }, 2634 { SYS_DESC(SYS_ICC_EOIR1_EL1), undef_access }, 2635 { SYS_DESC(SYS_ICC_HPPIR1_EL1), undef_access }, 2636 { SYS_DESC(SYS_ICC_BPR1_EL1), undef_access }, 2637 { SYS_DESC(SYS_ICC_CTLR_EL1), undef_access }, 2638 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre }, 2639 { SYS_DESC(SYS_ICC_IGRPEN0_EL1), undef_access }, 2640 { SYS_DESC(SYS_ICC_IGRPEN1_EL1), undef_access }, 2641 2642 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 }, 2643 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 }, 2644 2645 { SYS_DESC(SYS_ACCDATA_EL1), undef_access }, 2646 2647 { SYS_DESC(SYS_SCXTNUM_EL1), undef_access }, 2648 2649 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0}, 2650 2651 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr }, 2652 { SYS_DESC(SYS_CLIDR_EL1), access_clidr, reset_clidr, CLIDR_EL1, 2653 .set_user = set_clidr, .val = ~CLIDR_EL1_RES0 }, 2654 { SYS_DESC(SYS_CCSIDR2_EL1), undef_access }, 2655 { SYS_DESC(SYS_SMIDR_EL1), undef_access }, 2656 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, 2657 ID_WRITABLE(CTR_EL0, CTR_EL0_DIC_MASK | 2658 CTR_EL0_IDC_MASK | 2659 CTR_EL0_DminLine_MASK | 2660 CTR_EL0_IminLine_MASK), 2661 { SYS_DESC(SYS_SVCR), undef_access, reset_val, SVCR, 0, .visibility = sme_visibility }, 2662 { SYS_DESC(SYS_FPMR), undef_access, reset_val, FPMR, 0, .visibility = fp8_visibility }, 2663 2664 { PMU_SYS_REG(PMCR_EL0), .access = access_pmcr, .reset = reset_pmcr, 2665 .reg = PMCR_EL0, .get_user = get_pmcr, .set_user = set_pmcr }, 2666 { PMU_SYS_REG(PMCNTENSET_EL0), 2667 .access = access_pmcnten, .reg = PMCNTENSET_EL0, 2668 .get_user = get_pmreg, .set_user = set_pmreg }, 2669 { PMU_SYS_REG(PMCNTENCLR_EL0), 2670 .access = access_pmcnten, .reg = PMCNTENSET_EL0, 2671 .get_user = get_pmreg, .set_user = set_pmreg }, 2672 { PMU_SYS_REG(PMOVSCLR_EL0), 2673 .access = access_pmovs, .reg = PMOVSSET_EL0, 2674 .get_user = get_pmreg, .set_user = set_pmreg }, 2675 /* 2676 * PM_SWINC_EL0 is exposed to userspace as RAZ/WI, as it was 2677 * previously (and pointlessly) advertised in the past... 2678 */ 2679 { PMU_SYS_REG(PMSWINC_EL0), 2680 .get_user = get_raz_reg, .set_user = set_wi_reg, 2681 .access = access_pmswinc, .reset = NULL }, 2682 { PMU_SYS_REG(PMSELR_EL0), 2683 .access = access_pmselr, .reset = reset_pmselr, .reg = PMSELR_EL0 }, 2684 { PMU_SYS_REG(PMCEID0_EL0), 2685 .access = access_pmceid, .reset = NULL }, 2686 { PMU_SYS_REG(PMCEID1_EL0), 2687 .access = access_pmceid, .reset = NULL }, 2688 { PMU_SYS_REG(PMCCNTR_EL0), 2689 .access = access_pmu_evcntr, .reset = reset_unknown, 2690 .reg = PMCCNTR_EL0, .get_user = get_pmu_evcntr}, 2691 { PMU_SYS_REG(PMXEVTYPER_EL0), 2692 .access = access_pmu_evtyper, .reset = NULL }, 2693 { PMU_SYS_REG(PMXEVCNTR_EL0), 2694 .access = access_pmu_evcntr, .reset = NULL }, 2695 /* 2696 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero 2697 * in 32bit mode. Here we choose to reset it as zero for consistency. 2698 */ 2699 { PMU_SYS_REG(PMUSERENR_EL0), .access = access_pmuserenr, 2700 .reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 }, 2701 { PMU_SYS_REG(PMOVSSET_EL0), 2702 .access = access_pmovs, .reg = PMOVSSET_EL0, 2703 .get_user = get_pmreg, .set_user = set_pmreg }, 2704 2705 { SYS_DESC(SYS_POR_EL0), NULL, reset_unknown, POR_EL0, 2706 .visibility = s1poe_visibility }, 2707 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 }, 2708 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 }, 2709 { SYS_DESC(SYS_TPIDR2_EL0), undef_access }, 2710 2711 { SYS_DESC(SYS_SCXTNUM_EL0), undef_access }, 2712 2713 { SYS_DESC(SYS_AMCR_EL0), undef_access }, 2714 { SYS_DESC(SYS_AMCFGR_EL0), undef_access }, 2715 { SYS_DESC(SYS_AMCGCR_EL0), undef_access }, 2716 { SYS_DESC(SYS_AMUSERENR_EL0), undef_access }, 2717 { SYS_DESC(SYS_AMCNTENCLR0_EL0), undef_access }, 2718 { SYS_DESC(SYS_AMCNTENSET0_EL0), undef_access }, 2719 { SYS_DESC(SYS_AMCNTENCLR1_EL0), undef_access }, 2720 { SYS_DESC(SYS_AMCNTENSET1_EL0), undef_access }, 2721 AMU_AMEVCNTR0_EL0(0), 2722 AMU_AMEVCNTR0_EL0(1), 2723 AMU_AMEVCNTR0_EL0(2), 2724 AMU_AMEVCNTR0_EL0(3), 2725 AMU_AMEVCNTR0_EL0(4), 2726 AMU_AMEVCNTR0_EL0(5), 2727 AMU_AMEVCNTR0_EL0(6), 2728 AMU_AMEVCNTR0_EL0(7), 2729 AMU_AMEVCNTR0_EL0(8), 2730 AMU_AMEVCNTR0_EL0(9), 2731 AMU_AMEVCNTR0_EL0(10), 2732 AMU_AMEVCNTR0_EL0(11), 2733 AMU_AMEVCNTR0_EL0(12), 2734 AMU_AMEVCNTR0_EL0(13), 2735 AMU_AMEVCNTR0_EL0(14), 2736 AMU_AMEVCNTR0_EL0(15), 2737 AMU_AMEVTYPER0_EL0(0), 2738 AMU_AMEVTYPER0_EL0(1), 2739 AMU_AMEVTYPER0_EL0(2), 2740 AMU_AMEVTYPER0_EL0(3), 2741 AMU_AMEVTYPER0_EL0(4), 2742 AMU_AMEVTYPER0_EL0(5), 2743 AMU_AMEVTYPER0_EL0(6), 2744 AMU_AMEVTYPER0_EL0(7), 2745 AMU_AMEVTYPER0_EL0(8), 2746 AMU_AMEVTYPER0_EL0(9), 2747 AMU_AMEVTYPER0_EL0(10), 2748 AMU_AMEVTYPER0_EL0(11), 2749 AMU_AMEVTYPER0_EL0(12), 2750 AMU_AMEVTYPER0_EL0(13), 2751 AMU_AMEVTYPER0_EL0(14), 2752 AMU_AMEVTYPER0_EL0(15), 2753 AMU_AMEVCNTR1_EL0(0), 2754 AMU_AMEVCNTR1_EL0(1), 2755 AMU_AMEVCNTR1_EL0(2), 2756 AMU_AMEVCNTR1_EL0(3), 2757 AMU_AMEVCNTR1_EL0(4), 2758 AMU_AMEVCNTR1_EL0(5), 2759 AMU_AMEVCNTR1_EL0(6), 2760 AMU_AMEVCNTR1_EL0(7), 2761 AMU_AMEVCNTR1_EL0(8), 2762 AMU_AMEVCNTR1_EL0(9), 2763 AMU_AMEVCNTR1_EL0(10), 2764 AMU_AMEVCNTR1_EL0(11), 2765 AMU_AMEVCNTR1_EL0(12), 2766 AMU_AMEVCNTR1_EL0(13), 2767 AMU_AMEVCNTR1_EL0(14), 2768 AMU_AMEVCNTR1_EL0(15), 2769 AMU_AMEVTYPER1_EL0(0), 2770 AMU_AMEVTYPER1_EL0(1), 2771 AMU_AMEVTYPER1_EL0(2), 2772 AMU_AMEVTYPER1_EL0(3), 2773 AMU_AMEVTYPER1_EL0(4), 2774 AMU_AMEVTYPER1_EL0(5), 2775 AMU_AMEVTYPER1_EL0(6), 2776 AMU_AMEVTYPER1_EL0(7), 2777 AMU_AMEVTYPER1_EL0(8), 2778 AMU_AMEVTYPER1_EL0(9), 2779 AMU_AMEVTYPER1_EL0(10), 2780 AMU_AMEVTYPER1_EL0(11), 2781 AMU_AMEVTYPER1_EL0(12), 2782 AMU_AMEVTYPER1_EL0(13), 2783 AMU_AMEVTYPER1_EL0(14), 2784 AMU_AMEVTYPER1_EL0(15), 2785 2786 { SYS_DESC(SYS_CNTPCT_EL0), access_arch_timer }, 2787 { SYS_DESC(SYS_CNTPCTSS_EL0), access_arch_timer }, 2788 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer }, 2789 { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer }, 2790 { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer }, 2791 2792 /* PMEVCNTRn_EL0 */ 2793 PMU_PMEVCNTR_EL0(0), 2794 PMU_PMEVCNTR_EL0(1), 2795 PMU_PMEVCNTR_EL0(2), 2796 PMU_PMEVCNTR_EL0(3), 2797 PMU_PMEVCNTR_EL0(4), 2798 PMU_PMEVCNTR_EL0(5), 2799 PMU_PMEVCNTR_EL0(6), 2800 PMU_PMEVCNTR_EL0(7), 2801 PMU_PMEVCNTR_EL0(8), 2802 PMU_PMEVCNTR_EL0(9), 2803 PMU_PMEVCNTR_EL0(10), 2804 PMU_PMEVCNTR_EL0(11), 2805 PMU_PMEVCNTR_EL0(12), 2806 PMU_PMEVCNTR_EL0(13), 2807 PMU_PMEVCNTR_EL0(14), 2808 PMU_PMEVCNTR_EL0(15), 2809 PMU_PMEVCNTR_EL0(16), 2810 PMU_PMEVCNTR_EL0(17), 2811 PMU_PMEVCNTR_EL0(18), 2812 PMU_PMEVCNTR_EL0(19), 2813 PMU_PMEVCNTR_EL0(20), 2814 PMU_PMEVCNTR_EL0(21), 2815 PMU_PMEVCNTR_EL0(22), 2816 PMU_PMEVCNTR_EL0(23), 2817 PMU_PMEVCNTR_EL0(24), 2818 PMU_PMEVCNTR_EL0(25), 2819 PMU_PMEVCNTR_EL0(26), 2820 PMU_PMEVCNTR_EL0(27), 2821 PMU_PMEVCNTR_EL0(28), 2822 PMU_PMEVCNTR_EL0(29), 2823 PMU_PMEVCNTR_EL0(30), 2824 /* PMEVTYPERn_EL0 */ 2825 PMU_PMEVTYPER_EL0(0), 2826 PMU_PMEVTYPER_EL0(1), 2827 PMU_PMEVTYPER_EL0(2), 2828 PMU_PMEVTYPER_EL0(3), 2829 PMU_PMEVTYPER_EL0(4), 2830 PMU_PMEVTYPER_EL0(5), 2831 PMU_PMEVTYPER_EL0(6), 2832 PMU_PMEVTYPER_EL0(7), 2833 PMU_PMEVTYPER_EL0(8), 2834 PMU_PMEVTYPER_EL0(9), 2835 PMU_PMEVTYPER_EL0(10), 2836 PMU_PMEVTYPER_EL0(11), 2837 PMU_PMEVTYPER_EL0(12), 2838 PMU_PMEVTYPER_EL0(13), 2839 PMU_PMEVTYPER_EL0(14), 2840 PMU_PMEVTYPER_EL0(15), 2841 PMU_PMEVTYPER_EL0(16), 2842 PMU_PMEVTYPER_EL0(17), 2843 PMU_PMEVTYPER_EL0(18), 2844 PMU_PMEVTYPER_EL0(19), 2845 PMU_PMEVTYPER_EL0(20), 2846 PMU_PMEVTYPER_EL0(21), 2847 PMU_PMEVTYPER_EL0(22), 2848 PMU_PMEVTYPER_EL0(23), 2849 PMU_PMEVTYPER_EL0(24), 2850 PMU_PMEVTYPER_EL0(25), 2851 PMU_PMEVTYPER_EL0(26), 2852 PMU_PMEVTYPER_EL0(27), 2853 PMU_PMEVTYPER_EL0(28), 2854 PMU_PMEVTYPER_EL0(29), 2855 PMU_PMEVTYPER_EL0(30), 2856 /* 2857 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero 2858 * in 32bit mode. Here we choose to reset it as zero for consistency. 2859 */ 2860 { PMU_SYS_REG(PMCCFILTR_EL0), .access = access_pmu_evtyper, 2861 .reset = reset_val, .reg = PMCCFILTR_EL0, .val = 0 }, 2862 2863 EL2_REG_VNCR(VPIDR_EL2, reset_unknown, 0), 2864 EL2_REG_VNCR(VMPIDR_EL2, reset_unknown, 0), 2865 EL2_REG(SCTLR_EL2, access_rw, reset_val, SCTLR_EL2_RES1), 2866 EL2_REG(ACTLR_EL2, access_rw, reset_val, 0), 2867 EL2_REG_VNCR(HCR_EL2, reset_hcr, 0), 2868 EL2_REG(MDCR_EL2, access_rw, reset_val, 0), 2869 EL2_REG(CPTR_EL2, access_rw, reset_val, CPTR_NVHE_EL2_RES1), 2870 EL2_REG_VNCR(HSTR_EL2, reset_val, 0), 2871 EL2_REG_VNCR(HFGRTR_EL2, reset_val, 0), 2872 EL2_REG_VNCR(HFGWTR_EL2, reset_val, 0), 2873 EL2_REG_VNCR(HFGITR_EL2, reset_val, 0), 2874 EL2_REG_VNCR(HACR_EL2, reset_val, 0), 2875 2876 { SYS_DESC(SYS_ZCR_EL2), .access = access_zcr_el2, .reset = reset_val, 2877 .visibility = sve_el2_visibility, .reg = ZCR_EL2 }, 2878 2879 EL2_REG_VNCR(HCRX_EL2, reset_val, 0), 2880 2881 EL2_REG(TTBR0_EL2, access_rw, reset_val, 0), 2882 EL2_REG(TTBR1_EL2, access_rw, reset_val, 0), 2883 EL2_REG(TCR_EL2, access_rw, reset_val, TCR_EL2_RES1), 2884 EL2_REG(TCR2_EL2, access_tcr2_el2, reset_val, TCR2_EL2_RES1), 2885 EL2_REG_VNCR(VTTBR_EL2, reset_val, 0), 2886 EL2_REG_VNCR(VTCR_EL2, reset_val, 0), 2887 2888 { SYS_DESC(SYS_DACR32_EL2), undef_access, reset_unknown, DACR32_EL2 }, 2889 EL2_REG_VNCR(HDFGRTR_EL2, reset_val, 0), 2890 EL2_REG_VNCR(HDFGWTR_EL2, reset_val, 0), 2891 EL2_REG_VNCR(HAFGRTR_EL2, reset_val, 0), 2892 EL2_REG_REDIR(SPSR_EL2, reset_val, 0), 2893 EL2_REG_REDIR(ELR_EL2, reset_val, 0), 2894 { SYS_DESC(SYS_SP_EL1), access_sp_el1}, 2895 2896 /* AArch32 SPSR_* are RES0 if trapped from a NV guest */ 2897 { SYS_DESC(SYS_SPSR_irq), .access = trap_raz_wi }, 2898 { SYS_DESC(SYS_SPSR_abt), .access = trap_raz_wi }, 2899 { SYS_DESC(SYS_SPSR_und), .access = trap_raz_wi }, 2900 { SYS_DESC(SYS_SPSR_fiq), .access = trap_raz_wi }, 2901 2902 { SYS_DESC(SYS_IFSR32_EL2), undef_access, reset_unknown, IFSR32_EL2 }, 2903 EL2_REG(AFSR0_EL2, access_rw, reset_val, 0), 2904 EL2_REG(AFSR1_EL2, access_rw, reset_val, 0), 2905 EL2_REG_REDIR(ESR_EL2, reset_val, 0), 2906 { SYS_DESC(SYS_FPEXC32_EL2), undef_access, reset_val, FPEXC32_EL2, 0x700 }, 2907 2908 EL2_REG_REDIR(FAR_EL2, reset_val, 0), 2909 EL2_REG(HPFAR_EL2, access_rw, reset_val, 0), 2910 2911 EL2_REG(MAIR_EL2, access_rw, reset_val, 0), 2912 EL2_REG(AMAIR_EL2, access_rw, reset_val, 0), 2913 2914 EL2_REG(VBAR_EL2, access_rw, reset_val, 0), 2915 EL2_REG(RVBAR_EL2, access_rw, reset_val, 0), 2916 { SYS_DESC(SYS_RMR_EL2), undef_access }, 2917 2918 EL2_REG_VNCR(ICH_HCR_EL2, reset_val, 0), 2919 2920 EL2_REG(CONTEXTIDR_EL2, access_rw, reset_val, 0), 2921 EL2_REG(TPIDR_EL2, access_rw, reset_val, 0), 2922 2923 EL2_REG_VNCR(CNTVOFF_EL2, reset_val, 0), 2924 EL2_REG(CNTHCTL_EL2, access_rw, reset_val, 0), 2925 2926 { SYS_DESC(SYS_CNTKCTL_EL12), access_cntkctl_el12 }, 2927 2928 EL2_REG(SP_EL2, NULL, reset_unknown, 0), 2929 }; 2930 2931 static bool handle_at_s1e01(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2932 const struct sys_reg_desc *r) 2933 { 2934 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 2935 2936 __kvm_at_s1e01(vcpu, op, p->regval); 2937 2938 return true; 2939 } 2940 2941 static bool handle_at_s1e2(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2942 const struct sys_reg_desc *r) 2943 { 2944 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 2945 2946 /* There is no FGT associated with AT S1E2A :-( */ 2947 if (op == OP_AT_S1E2A && 2948 !kvm_has_feat(vcpu->kvm, ID_AA64ISAR2_EL1, ATS1A, IMP)) { 2949 kvm_inject_undefined(vcpu); 2950 return false; 2951 } 2952 2953 __kvm_at_s1e2(vcpu, op, p->regval); 2954 2955 return true; 2956 } 2957 2958 static bool handle_at_s12(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2959 const struct sys_reg_desc *r) 2960 { 2961 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 2962 2963 __kvm_at_s12(vcpu, op, p->regval); 2964 2965 return true; 2966 } 2967 2968 static bool kvm_supported_tlbi_s12_op(struct kvm_vcpu *vpcu, u32 instr) 2969 { 2970 struct kvm *kvm = vpcu->kvm; 2971 u8 CRm = sys_reg_CRm(instr); 2972 2973 if (sys_reg_CRn(instr) == TLBI_CRn_nXS && 2974 !kvm_has_feat(kvm, ID_AA64ISAR1_EL1, XS, IMP)) 2975 return false; 2976 2977 if (CRm == TLBI_CRm_nROS && 2978 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 2979 return false; 2980 2981 return true; 2982 } 2983 2984 static bool handle_alle1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2985 const struct sys_reg_desc *r) 2986 { 2987 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 2988 2989 if (!kvm_supported_tlbi_s12_op(vcpu, sys_encoding)) 2990 return undef_access(vcpu, p, r); 2991 2992 write_lock(&vcpu->kvm->mmu_lock); 2993 2994 /* 2995 * Drop all shadow S2s, resulting in S1/S2 TLBIs for each of the 2996 * corresponding VMIDs. 2997 */ 2998 kvm_nested_s2_unmap(vcpu->kvm, true); 2999 3000 write_unlock(&vcpu->kvm->mmu_lock); 3001 3002 return true; 3003 } 3004 3005 static bool kvm_supported_tlbi_ipas2_op(struct kvm_vcpu *vpcu, u32 instr) 3006 { 3007 struct kvm *kvm = vpcu->kvm; 3008 u8 CRm = sys_reg_CRm(instr); 3009 u8 Op2 = sys_reg_Op2(instr); 3010 3011 if (sys_reg_CRn(instr) == TLBI_CRn_nXS && 3012 !kvm_has_feat(kvm, ID_AA64ISAR1_EL1, XS, IMP)) 3013 return false; 3014 3015 if (CRm == TLBI_CRm_IPAIS && (Op2 == 2 || Op2 == 6) && 3016 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE)) 3017 return false; 3018 3019 if (CRm == TLBI_CRm_IPAONS && (Op2 == 0 || Op2 == 4) && 3020 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 3021 return false; 3022 3023 if (CRm == TLBI_CRm_IPAONS && (Op2 == 3 || Op2 == 7) && 3024 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE)) 3025 return false; 3026 3027 return true; 3028 } 3029 3030 /* Only defined here as this is an internal "abstraction" */ 3031 union tlbi_info { 3032 struct { 3033 u64 start; 3034 u64 size; 3035 } range; 3036 3037 struct { 3038 u64 addr; 3039 } ipa; 3040 3041 struct { 3042 u64 addr; 3043 u32 encoding; 3044 } va; 3045 }; 3046 3047 static void s2_mmu_unmap_range(struct kvm_s2_mmu *mmu, 3048 const union tlbi_info *info) 3049 { 3050 /* 3051 * The unmap operation is allowed to drop the MMU lock and block, which 3052 * means that @mmu could be used for a different context than the one 3053 * currently being invalidated. 3054 * 3055 * This behavior is still safe, as: 3056 * 3057 * 1) The vCPU(s) that recycled the MMU are responsible for invalidating 3058 * the entire MMU before reusing it, which still honors the intent 3059 * of a TLBI. 3060 * 3061 * 2) Until the guest TLBI instruction is 'retired' (i.e. increment PC 3062 * and ERET to the guest), other vCPUs are allowed to use stale 3063 * translations. 3064 * 3065 * 3) Accidentally unmapping an unrelated MMU context is nonfatal, and 3066 * at worst may cause more aborts for shadow stage-2 fills. 3067 * 3068 * Dropping the MMU lock also implies that shadow stage-2 fills could 3069 * happen behind the back of the TLBI. This is still safe, though, as 3070 * the L1 needs to put its stage-2 in a consistent state before doing 3071 * the TLBI. 3072 */ 3073 kvm_stage2_unmap_range(mmu, info->range.start, info->range.size, true); 3074 } 3075 3076 static bool handle_vmalls12e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3077 const struct sys_reg_desc *r) 3078 { 3079 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3080 u64 limit, vttbr; 3081 3082 if (!kvm_supported_tlbi_s12_op(vcpu, sys_encoding)) 3083 return undef_access(vcpu, p, r); 3084 3085 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 3086 limit = BIT_ULL(kvm_get_pa_bits(vcpu->kvm)); 3087 3088 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 3089 &(union tlbi_info) { 3090 .range = { 3091 .start = 0, 3092 .size = limit, 3093 }, 3094 }, 3095 s2_mmu_unmap_range); 3096 3097 return true; 3098 } 3099 3100 static bool handle_ripas2e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3101 const struct sys_reg_desc *r) 3102 { 3103 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3104 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 3105 u64 base, range, tg, num, scale; 3106 int shift; 3107 3108 if (!kvm_supported_tlbi_ipas2_op(vcpu, sys_encoding)) 3109 return undef_access(vcpu, p, r); 3110 3111 /* 3112 * Because the shadow S2 structure doesn't necessarily reflect that 3113 * of the guest's S2 (different base granule size, for example), we 3114 * decide to ignore TTL and only use the described range. 3115 */ 3116 tg = FIELD_GET(GENMASK(47, 46), p->regval); 3117 scale = FIELD_GET(GENMASK(45, 44), p->regval); 3118 num = FIELD_GET(GENMASK(43, 39), p->regval); 3119 base = p->regval & GENMASK(36, 0); 3120 3121 switch(tg) { 3122 case 1: 3123 shift = 12; 3124 break; 3125 case 2: 3126 shift = 14; 3127 break; 3128 case 3: 3129 default: /* IMPDEF: handle tg==0 as 64k */ 3130 shift = 16; 3131 break; 3132 } 3133 3134 base <<= shift; 3135 range = __TLBI_RANGE_PAGES(num, scale) << shift; 3136 3137 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 3138 &(union tlbi_info) { 3139 .range = { 3140 .start = base, 3141 .size = range, 3142 }, 3143 }, 3144 s2_mmu_unmap_range); 3145 3146 return true; 3147 } 3148 3149 static void s2_mmu_unmap_ipa(struct kvm_s2_mmu *mmu, 3150 const union tlbi_info *info) 3151 { 3152 unsigned long max_size; 3153 u64 base_addr; 3154 3155 /* 3156 * We drop a number of things from the supplied value: 3157 * 3158 * - NS bit: we're non-secure only. 3159 * 3160 * - IPA[51:48]: We don't support 52bit IPA just yet... 3161 * 3162 * And of course, adjust the IPA to be on an actual address. 3163 */ 3164 base_addr = (info->ipa.addr & GENMASK_ULL(35, 0)) << 12; 3165 max_size = compute_tlb_inval_range(mmu, info->ipa.addr); 3166 base_addr &= ~(max_size - 1); 3167 3168 /* 3169 * See comment in s2_mmu_unmap_range() for why this is allowed to 3170 * reschedule. 3171 */ 3172 kvm_stage2_unmap_range(mmu, base_addr, max_size, true); 3173 } 3174 3175 static bool handle_ipas2e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3176 const struct sys_reg_desc *r) 3177 { 3178 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3179 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 3180 3181 if (!kvm_supported_tlbi_ipas2_op(vcpu, sys_encoding)) 3182 return undef_access(vcpu, p, r); 3183 3184 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 3185 &(union tlbi_info) { 3186 .ipa = { 3187 .addr = p->regval, 3188 }, 3189 }, 3190 s2_mmu_unmap_ipa); 3191 3192 return true; 3193 } 3194 3195 static void s2_mmu_tlbi_s1e1(struct kvm_s2_mmu *mmu, 3196 const union tlbi_info *info) 3197 { 3198 WARN_ON(__kvm_tlbi_s1e2(mmu, info->va.addr, info->va.encoding)); 3199 } 3200 3201 static bool handle_tlbi_el1(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3202 const struct sys_reg_desc *r) 3203 { 3204 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3205 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 3206 3207 /* 3208 * If we're here, this is because we've trapped on a EL1 TLBI 3209 * instruction that affects the EL1 translation regime while 3210 * we're running in a context that doesn't allow us to let the 3211 * HW do its thing (aka vEL2): 3212 * 3213 * - HCR_EL2.E2H == 0 : a non-VHE guest 3214 * - HCR_EL2.{E2H,TGE} == { 1, 0 } : a VHE guest in guest mode 3215 * 3216 * We don't expect these helpers to ever be called when running 3217 * in a vEL1 context. 3218 */ 3219 3220 WARN_ON(!vcpu_is_el2(vcpu)); 3221 3222 if (!kvm_supported_tlbi_s1e1_op(vcpu, sys_encoding)) 3223 return undef_access(vcpu, p, r); 3224 3225 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 3226 &(union tlbi_info) { 3227 .va = { 3228 .addr = p->regval, 3229 .encoding = sys_encoding, 3230 }, 3231 }, 3232 s2_mmu_tlbi_s1e1); 3233 3234 return true; 3235 } 3236 3237 #define SYS_INSN(insn, access_fn) \ 3238 { \ 3239 SYS_DESC(OP_##insn), \ 3240 .access = (access_fn), \ 3241 } 3242 3243 static struct sys_reg_desc sys_insn_descs[] = { 3244 { SYS_DESC(SYS_DC_ISW), access_dcsw }, 3245 { SYS_DESC(SYS_DC_IGSW), access_dcgsw }, 3246 { SYS_DESC(SYS_DC_IGDSW), access_dcgsw }, 3247 3248 SYS_INSN(AT_S1E1R, handle_at_s1e01), 3249 SYS_INSN(AT_S1E1W, handle_at_s1e01), 3250 SYS_INSN(AT_S1E0R, handle_at_s1e01), 3251 SYS_INSN(AT_S1E0W, handle_at_s1e01), 3252 SYS_INSN(AT_S1E1RP, handle_at_s1e01), 3253 SYS_INSN(AT_S1E1WP, handle_at_s1e01), 3254 3255 { SYS_DESC(SYS_DC_CSW), access_dcsw }, 3256 { SYS_DESC(SYS_DC_CGSW), access_dcgsw }, 3257 { SYS_DESC(SYS_DC_CGDSW), access_dcgsw }, 3258 { SYS_DESC(SYS_DC_CISW), access_dcsw }, 3259 { SYS_DESC(SYS_DC_CIGSW), access_dcgsw }, 3260 { SYS_DESC(SYS_DC_CIGDSW), access_dcgsw }, 3261 3262 SYS_INSN(TLBI_VMALLE1OS, handle_tlbi_el1), 3263 SYS_INSN(TLBI_VAE1OS, handle_tlbi_el1), 3264 SYS_INSN(TLBI_ASIDE1OS, handle_tlbi_el1), 3265 SYS_INSN(TLBI_VAAE1OS, handle_tlbi_el1), 3266 SYS_INSN(TLBI_VALE1OS, handle_tlbi_el1), 3267 SYS_INSN(TLBI_VAALE1OS, handle_tlbi_el1), 3268 3269 SYS_INSN(TLBI_RVAE1IS, handle_tlbi_el1), 3270 SYS_INSN(TLBI_RVAAE1IS, handle_tlbi_el1), 3271 SYS_INSN(TLBI_RVALE1IS, handle_tlbi_el1), 3272 SYS_INSN(TLBI_RVAALE1IS, handle_tlbi_el1), 3273 3274 SYS_INSN(TLBI_VMALLE1IS, handle_tlbi_el1), 3275 SYS_INSN(TLBI_VAE1IS, handle_tlbi_el1), 3276 SYS_INSN(TLBI_ASIDE1IS, handle_tlbi_el1), 3277 SYS_INSN(TLBI_VAAE1IS, handle_tlbi_el1), 3278 SYS_INSN(TLBI_VALE1IS, handle_tlbi_el1), 3279 SYS_INSN(TLBI_VAALE1IS, handle_tlbi_el1), 3280 3281 SYS_INSN(TLBI_RVAE1OS, handle_tlbi_el1), 3282 SYS_INSN(TLBI_RVAAE1OS, handle_tlbi_el1), 3283 SYS_INSN(TLBI_RVALE1OS, handle_tlbi_el1), 3284 SYS_INSN(TLBI_RVAALE1OS, handle_tlbi_el1), 3285 3286 SYS_INSN(TLBI_RVAE1, handle_tlbi_el1), 3287 SYS_INSN(TLBI_RVAAE1, handle_tlbi_el1), 3288 SYS_INSN(TLBI_RVALE1, handle_tlbi_el1), 3289 SYS_INSN(TLBI_RVAALE1, handle_tlbi_el1), 3290 3291 SYS_INSN(TLBI_VMALLE1, handle_tlbi_el1), 3292 SYS_INSN(TLBI_VAE1, handle_tlbi_el1), 3293 SYS_INSN(TLBI_ASIDE1, handle_tlbi_el1), 3294 SYS_INSN(TLBI_VAAE1, handle_tlbi_el1), 3295 SYS_INSN(TLBI_VALE1, handle_tlbi_el1), 3296 SYS_INSN(TLBI_VAALE1, handle_tlbi_el1), 3297 3298 SYS_INSN(TLBI_VMALLE1OSNXS, handle_tlbi_el1), 3299 SYS_INSN(TLBI_VAE1OSNXS, handle_tlbi_el1), 3300 SYS_INSN(TLBI_ASIDE1OSNXS, handle_tlbi_el1), 3301 SYS_INSN(TLBI_VAAE1OSNXS, handle_tlbi_el1), 3302 SYS_INSN(TLBI_VALE1OSNXS, handle_tlbi_el1), 3303 SYS_INSN(TLBI_VAALE1OSNXS, handle_tlbi_el1), 3304 3305 SYS_INSN(TLBI_RVAE1ISNXS, handle_tlbi_el1), 3306 SYS_INSN(TLBI_RVAAE1ISNXS, handle_tlbi_el1), 3307 SYS_INSN(TLBI_RVALE1ISNXS, handle_tlbi_el1), 3308 SYS_INSN(TLBI_RVAALE1ISNXS, handle_tlbi_el1), 3309 3310 SYS_INSN(TLBI_VMALLE1ISNXS, handle_tlbi_el1), 3311 SYS_INSN(TLBI_VAE1ISNXS, handle_tlbi_el1), 3312 SYS_INSN(TLBI_ASIDE1ISNXS, handle_tlbi_el1), 3313 SYS_INSN(TLBI_VAAE1ISNXS, handle_tlbi_el1), 3314 SYS_INSN(TLBI_VALE1ISNXS, handle_tlbi_el1), 3315 SYS_INSN(TLBI_VAALE1ISNXS, handle_tlbi_el1), 3316 3317 SYS_INSN(TLBI_RVAE1OSNXS, handle_tlbi_el1), 3318 SYS_INSN(TLBI_RVAAE1OSNXS, handle_tlbi_el1), 3319 SYS_INSN(TLBI_RVALE1OSNXS, handle_tlbi_el1), 3320 SYS_INSN(TLBI_RVAALE1OSNXS, handle_tlbi_el1), 3321 3322 SYS_INSN(TLBI_RVAE1NXS, handle_tlbi_el1), 3323 SYS_INSN(TLBI_RVAAE1NXS, handle_tlbi_el1), 3324 SYS_INSN(TLBI_RVALE1NXS, handle_tlbi_el1), 3325 SYS_INSN(TLBI_RVAALE1NXS, handle_tlbi_el1), 3326 3327 SYS_INSN(TLBI_VMALLE1NXS, handle_tlbi_el1), 3328 SYS_INSN(TLBI_VAE1NXS, handle_tlbi_el1), 3329 SYS_INSN(TLBI_ASIDE1NXS, handle_tlbi_el1), 3330 SYS_INSN(TLBI_VAAE1NXS, handle_tlbi_el1), 3331 SYS_INSN(TLBI_VALE1NXS, handle_tlbi_el1), 3332 SYS_INSN(TLBI_VAALE1NXS, handle_tlbi_el1), 3333 3334 SYS_INSN(AT_S1E2R, handle_at_s1e2), 3335 SYS_INSN(AT_S1E2W, handle_at_s1e2), 3336 SYS_INSN(AT_S12E1R, handle_at_s12), 3337 SYS_INSN(AT_S12E1W, handle_at_s12), 3338 SYS_INSN(AT_S12E0R, handle_at_s12), 3339 SYS_INSN(AT_S12E0W, handle_at_s12), 3340 SYS_INSN(AT_S1E2A, handle_at_s1e2), 3341 3342 SYS_INSN(TLBI_IPAS2E1IS, handle_ipas2e1is), 3343 SYS_INSN(TLBI_RIPAS2E1IS, handle_ripas2e1is), 3344 SYS_INSN(TLBI_IPAS2LE1IS, handle_ipas2e1is), 3345 SYS_INSN(TLBI_RIPAS2LE1IS, handle_ripas2e1is), 3346 3347 SYS_INSN(TLBI_ALLE2OS, undef_access), 3348 SYS_INSN(TLBI_VAE2OS, undef_access), 3349 SYS_INSN(TLBI_ALLE1OS, handle_alle1is), 3350 SYS_INSN(TLBI_VALE2OS, undef_access), 3351 SYS_INSN(TLBI_VMALLS12E1OS, handle_vmalls12e1is), 3352 3353 SYS_INSN(TLBI_RVAE2IS, undef_access), 3354 SYS_INSN(TLBI_RVALE2IS, undef_access), 3355 3356 SYS_INSN(TLBI_ALLE1IS, handle_alle1is), 3357 SYS_INSN(TLBI_VMALLS12E1IS, handle_vmalls12e1is), 3358 SYS_INSN(TLBI_IPAS2E1OS, handle_ipas2e1is), 3359 SYS_INSN(TLBI_IPAS2E1, handle_ipas2e1is), 3360 SYS_INSN(TLBI_RIPAS2E1, handle_ripas2e1is), 3361 SYS_INSN(TLBI_RIPAS2E1OS, handle_ripas2e1is), 3362 SYS_INSN(TLBI_IPAS2LE1OS, handle_ipas2e1is), 3363 SYS_INSN(TLBI_IPAS2LE1, handle_ipas2e1is), 3364 SYS_INSN(TLBI_RIPAS2LE1, handle_ripas2e1is), 3365 SYS_INSN(TLBI_RIPAS2LE1OS, handle_ripas2e1is), 3366 SYS_INSN(TLBI_RVAE2OS, undef_access), 3367 SYS_INSN(TLBI_RVALE2OS, undef_access), 3368 SYS_INSN(TLBI_RVAE2, undef_access), 3369 SYS_INSN(TLBI_RVALE2, undef_access), 3370 SYS_INSN(TLBI_ALLE1, handle_alle1is), 3371 SYS_INSN(TLBI_VMALLS12E1, handle_vmalls12e1is), 3372 3373 SYS_INSN(TLBI_IPAS2E1ISNXS, handle_ipas2e1is), 3374 SYS_INSN(TLBI_RIPAS2E1ISNXS, handle_ripas2e1is), 3375 SYS_INSN(TLBI_IPAS2LE1ISNXS, handle_ipas2e1is), 3376 SYS_INSN(TLBI_RIPAS2LE1ISNXS, handle_ripas2e1is), 3377 3378 SYS_INSN(TLBI_ALLE2OSNXS, undef_access), 3379 SYS_INSN(TLBI_VAE2OSNXS, undef_access), 3380 SYS_INSN(TLBI_ALLE1OSNXS, handle_alle1is), 3381 SYS_INSN(TLBI_VALE2OSNXS, undef_access), 3382 SYS_INSN(TLBI_VMALLS12E1OSNXS, handle_vmalls12e1is), 3383 3384 SYS_INSN(TLBI_RVAE2ISNXS, undef_access), 3385 SYS_INSN(TLBI_RVALE2ISNXS, undef_access), 3386 SYS_INSN(TLBI_ALLE2ISNXS, undef_access), 3387 SYS_INSN(TLBI_VAE2ISNXS, undef_access), 3388 3389 SYS_INSN(TLBI_ALLE1ISNXS, handle_alle1is), 3390 SYS_INSN(TLBI_VALE2ISNXS, undef_access), 3391 SYS_INSN(TLBI_VMALLS12E1ISNXS, handle_vmalls12e1is), 3392 SYS_INSN(TLBI_IPAS2E1OSNXS, handle_ipas2e1is), 3393 SYS_INSN(TLBI_IPAS2E1NXS, handle_ipas2e1is), 3394 SYS_INSN(TLBI_RIPAS2E1NXS, handle_ripas2e1is), 3395 SYS_INSN(TLBI_RIPAS2E1OSNXS, handle_ripas2e1is), 3396 SYS_INSN(TLBI_IPAS2LE1OSNXS, handle_ipas2e1is), 3397 SYS_INSN(TLBI_IPAS2LE1NXS, handle_ipas2e1is), 3398 SYS_INSN(TLBI_RIPAS2LE1NXS, handle_ripas2e1is), 3399 SYS_INSN(TLBI_RIPAS2LE1OSNXS, handle_ripas2e1is), 3400 SYS_INSN(TLBI_RVAE2OSNXS, undef_access), 3401 SYS_INSN(TLBI_RVALE2OSNXS, undef_access), 3402 SYS_INSN(TLBI_RVAE2NXS, undef_access), 3403 SYS_INSN(TLBI_RVALE2NXS, undef_access), 3404 SYS_INSN(TLBI_ALLE2NXS, undef_access), 3405 SYS_INSN(TLBI_VAE2NXS, undef_access), 3406 SYS_INSN(TLBI_ALLE1NXS, handle_alle1is), 3407 SYS_INSN(TLBI_VALE2NXS, undef_access), 3408 SYS_INSN(TLBI_VMALLS12E1NXS, handle_vmalls12e1is), 3409 }; 3410 3411 static bool trap_dbgdidr(struct kvm_vcpu *vcpu, 3412 struct sys_reg_params *p, 3413 const struct sys_reg_desc *r) 3414 { 3415 if (p->is_write) { 3416 return ignore_write(vcpu, p); 3417 } else { 3418 u64 dfr = kvm_read_vm_id_reg(vcpu->kvm, SYS_ID_AA64DFR0_EL1); 3419 u32 el3 = kvm_has_feat(vcpu->kvm, ID_AA64PFR0_EL1, EL3, IMP); 3420 3421 p->regval = ((SYS_FIELD_GET(ID_AA64DFR0_EL1, WRPs, dfr) << 28) | 3422 (SYS_FIELD_GET(ID_AA64DFR0_EL1, BRPs, dfr) << 24) | 3423 (SYS_FIELD_GET(ID_AA64DFR0_EL1, CTX_CMPs, dfr) << 20) | 3424 (SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, dfr) << 16) | 3425 (1 << 15) | (el3 << 14) | (el3 << 12)); 3426 return true; 3427 } 3428 } 3429 3430 /* 3431 * AArch32 debug register mappings 3432 * 3433 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0] 3434 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32] 3435 * 3436 * None of the other registers share their location, so treat them as 3437 * if they were 64bit. 3438 */ 3439 #define DBG_BCR_BVR_WCR_WVR(n) \ 3440 /* DBGBVRn */ \ 3441 { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \ 3442 /* DBGBCRn */ \ 3443 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \ 3444 /* DBGWVRn */ \ 3445 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \ 3446 /* DBGWCRn */ \ 3447 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n } 3448 3449 #define DBGBXVR(n) \ 3450 { AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_bvr, NULL, n } 3451 3452 /* 3453 * Trapped cp14 registers. We generally ignore most of the external 3454 * debug, on the principle that they don't really make sense to a 3455 * guest. Revisit this one day, would this principle change. 3456 */ 3457 static const struct sys_reg_desc cp14_regs[] = { 3458 /* DBGDIDR */ 3459 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgdidr }, 3460 /* DBGDTRRXext */ 3461 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi }, 3462 3463 DBG_BCR_BVR_WCR_WVR(0), 3464 /* DBGDSCRint */ 3465 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi }, 3466 DBG_BCR_BVR_WCR_WVR(1), 3467 /* DBGDCCINT */ 3468 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug_regs, NULL, MDCCINT_EL1 }, 3469 /* DBGDSCRext */ 3470 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug_regs, NULL, MDSCR_EL1 }, 3471 DBG_BCR_BVR_WCR_WVR(2), 3472 /* DBGDTR[RT]Xint */ 3473 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi }, 3474 /* DBGDTR[RT]Xext */ 3475 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi }, 3476 DBG_BCR_BVR_WCR_WVR(3), 3477 DBG_BCR_BVR_WCR_WVR(4), 3478 DBG_BCR_BVR_WCR_WVR(5), 3479 /* DBGWFAR */ 3480 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi }, 3481 /* DBGOSECCR */ 3482 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi }, 3483 DBG_BCR_BVR_WCR_WVR(6), 3484 /* DBGVCR */ 3485 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug_regs, NULL, DBGVCR32_EL2 }, 3486 DBG_BCR_BVR_WCR_WVR(7), 3487 DBG_BCR_BVR_WCR_WVR(8), 3488 DBG_BCR_BVR_WCR_WVR(9), 3489 DBG_BCR_BVR_WCR_WVR(10), 3490 DBG_BCR_BVR_WCR_WVR(11), 3491 DBG_BCR_BVR_WCR_WVR(12), 3492 DBG_BCR_BVR_WCR_WVR(13), 3493 DBG_BCR_BVR_WCR_WVR(14), 3494 DBG_BCR_BVR_WCR_WVR(15), 3495 3496 /* DBGDRAR (32bit) */ 3497 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi }, 3498 3499 DBGBXVR(0), 3500 /* DBGOSLAR */ 3501 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_oslar_el1 }, 3502 DBGBXVR(1), 3503 /* DBGOSLSR */ 3504 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1, NULL, OSLSR_EL1 }, 3505 DBGBXVR(2), 3506 DBGBXVR(3), 3507 /* DBGOSDLR */ 3508 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi }, 3509 DBGBXVR(4), 3510 /* DBGPRCR */ 3511 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi }, 3512 DBGBXVR(5), 3513 DBGBXVR(6), 3514 DBGBXVR(7), 3515 DBGBXVR(8), 3516 DBGBXVR(9), 3517 DBGBXVR(10), 3518 DBGBXVR(11), 3519 DBGBXVR(12), 3520 DBGBXVR(13), 3521 DBGBXVR(14), 3522 DBGBXVR(15), 3523 3524 /* DBGDSAR (32bit) */ 3525 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi }, 3526 3527 /* DBGDEVID2 */ 3528 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi }, 3529 /* DBGDEVID1 */ 3530 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi }, 3531 /* DBGDEVID */ 3532 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi }, 3533 /* DBGCLAIMSET */ 3534 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi }, 3535 /* DBGCLAIMCLR */ 3536 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi }, 3537 /* DBGAUTHSTATUS */ 3538 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 }, 3539 }; 3540 3541 /* Trapped cp14 64bit registers */ 3542 static const struct sys_reg_desc cp14_64_regs[] = { 3543 /* DBGDRAR (64bit) */ 3544 { Op1( 0), CRm( 1), .access = trap_raz_wi }, 3545 3546 /* DBGDSAR (64bit) */ 3547 { Op1( 0), CRm( 2), .access = trap_raz_wi }, 3548 }; 3549 3550 #define CP15_PMU_SYS_REG(_map, _Op1, _CRn, _CRm, _Op2) \ 3551 AA32(_map), \ 3552 Op1(_Op1), CRn(_CRn), CRm(_CRm), Op2(_Op2), \ 3553 .visibility = pmu_visibility 3554 3555 /* Macro to expand the PMEVCNTRn register */ 3556 #define PMU_PMEVCNTR(n) \ 3557 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \ 3558 (0b1000 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \ 3559 .access = access_pmu_evcntr } 3560 3561 /* Macro to expand the PMEVTYPERn register */ 3562 #define PMU_PMEVTYPER(n) \ 3563 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \ 3564 (0b1100 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \ 3565 .access = access_pmu_evtyper } 3566 /* 3567 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding, 3568 * depending on the way they are accessed (as a 32bit or a 64bit 3569 * register). 3570 */ 3571 static const struct sys_reg_desc cp15_regs[] = { 3572 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr }, 3573 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, SCTLR_EL1 }, 3574 /* ACTLR */ 3575 { AA32(LO), Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr, NULL, ACTLR_EL1 }, 3576 /* ACTLR2 */ 3577 { AA32(HI), Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr, NULL, ACTLR_EL1 }, 3578 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, 3579 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, TTBR1_EL1 }, 3580 /* TTBCR */ 3581 { AA32(LO), Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 }, 3582 /* TTBCR2 */ 3583 { AA32(HI), Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, TCR_EL1 }, 3584 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, DACR32_EL2 }, 3585 { CP15_SYS_DESC(SYS_ICC_PMR_EL1), undef_access }, 3586 /* DFSR */ 3587 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, ESR_EL1 }, 3588 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, IFSR32_EL2 }, 3589 /* ADFSR */ 3590 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, AFSR0_EL1 }, 3591 /* AIFSR */ 3592 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, AFSR1_EL1 }, 3593 /* DFAR */ 3594 { AA32(LO), Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, FAR_EL1 }, 3595 /* IFAR */ 3596 { AA32(HI), Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, FAR_EL1 }, 3597 3598 /* 3599 * DC{C,I,CI}SW operations: 3600 */ 3601 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw }, 3602 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw }, 3603 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw }, 3604 3605 /* PMU */ 3606 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 0), .access = access_pmcr }, 3607 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 1), .access = access_pmcnten }, 3608 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 2), .access = access_pmcnten }, 3609 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 3), .access = access_pmovs }, 3610 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 4), .access = access_pmswinc }, 3611 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 5), .access = access_pmselr }, 3612 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 6), .access = access_pmceid }, 3613 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 7), .access = access_pmceid }, 3614 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 0), .access = access_pmu_evcntr }, 3615 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 1), .access = access_pmu_evtyper }, 3616 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 2), .access = access_pmu_evcntr }, 3617 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 0), .access = access_pmuserenr }, 3618 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 1), .access = access_pminten }, 3619 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 2), .access = access_pminten }, 3620 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 3), .access = access_pmovs }, 3621 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 4), .access = access_pmceid }, 3622 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 5), .access = access_pmceid }, 3623 /* PMMIR */ 3624 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 6), .access = trap_raz_wi }, 3625 3626 /* PRRR/MAIR0 */ 3627 { AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 }, 3628 /* NMRR/MAIR1 */ 3629 { AA32(HI), Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, MAIR_EL1 }, 3630 /* AMAIR0 */ 3631 { AA32(LO), Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, AMAIR_EL1 }, 3632 /* AMAIR1 */ 3633 { AA32(HI), Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, AMAIR_EL1 }, 3634 3635 { CP15_SYS_DESC(SYS_ICC_IAR0_EL1), undef_access }, 3636 { CP15_SYS_DESC(SYS_ICC_EOIR0_EL1), undef_access }, 3637 { CP15_SYS_DESC(SYS_ICC_HPPIR0_EL1), undef_access }, 3638 { CP15_SYS_DESC(SYS_ICC_BPR0_EL1), undef_access }, 3639 { CP15_SYS_DESC(SYS_ICC_AP0R0_EL1), undef_access }, 3640 { CP15_SYS_DESC(SYS_ICC_AP0R1_EL1), undef_access }, 3641 { CP15_SYS_DESC(SYS_ICC_AP0R2_EL1), undef_access }, 3642 { CP15_SYS_DESC(SYS_ICC_AP0R3_EL1), undef_access }, 3643 { CP15_SYS_DESC(SYS_ICC_AP1R0_EL1), undef_access }, 3644 { CP15_SYS_DESC(SYS_ICC_AP1R1_EL1), undef_access }, 3645 { CP15_SYS_DESC(SYS_ICC_AP1R2_EL1), undef_access }, 3646 { CP15_SYS_DESC(SYS_ICC_AP1R3_EL1), undef_access }, 3647 { CP15_SYS_DESC(SYS_ICC_DIR_EL1), undef_access }, 3648 { CP15_SYS_DESC(SYS_ICC_RPR_EL1), undef_access }, 3649 { CP15_SYS_DESC(SYS_ICC_IAR1_EL1), undef_access }, 3650 { CP15_SYS_DESC(SYS_ICC_EOIR1_EL1), undef_access }, 3651 { CP15_SYS_DESC(SYS_ICC_HPPIR1_EL1), undef_access }, 3652 { CP15_SYS_DESC(SYS_ICC_BPR1_EL1), undef_access }, 3653 { CP15_SYS_DESC(SYS_ICC_CTLR_EL1), undef_access }, 3654 { CP15_SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre }, 3655 { CP15_SYS_DESC(SYS_ICC_IGRPEN0_EL1), undef_access }, 3656 { CP15_SYS_DESC(SYS_ICC_IGRPEN1_EL1), undef_access }, 3657 3658 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, CONTEXTIDR_EL1 }, 3659 3660 /* Arch Tmers */ 3661 { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer }, 3662 { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer }, 3663 3664 /* PMEVCNTRn */ 3665 PMU_PMEVCNTR(0), 3666 PMU_PMEVCNTR(1), 3667 PMU_PMEVCNTR(2), 3668 PMU_PMEVCNTR(3), 3669 PMU_PMEVCNTR(4), 3670 PMU_PMEVCNTR(5), 3671 PMU_PMEVCNTR(6), 3672 PMU_PMEVCNTR(7), 3673 PMU_PMEVCNTR(8), 3674 PMU_PMEVCNTR(9), 3675 PMU_PMEVCNTR(10), 3676 PMU_PMEVCNTR(11), 3677 PMU_PMEVCNTR(12), 3678 PMU_PMEVCNTR(13), 3679 PMU_PMEVCNTR(14), 3680 PMU_PMEVCNTR(15), 3681 PMU_PMEVCNTR(16), 3682 PMU_PMEVCNTR(17), 3683 PMU_PMEVCNTR(18), 3684 PMU_PMEVCNTR(19), 3685 PMU_PMEVCNTR(20), 3686 PMU_PMEVCNTR(21), 3687 PMU_PMEVCNTR(22), 3688 PMU_PMEVCNTR(23), 3689 PMU_PMEVCNTR(24), 3690 PMU_PMEVCNTR(25), 3691 PMU_PMEVCNTR(26), 3692 PMU_PMEVCNTR(27), 3693 PMU_PMEVCNTR(28), 3694 PMU_PMEVCNTR(29), 3695 PMU_PMEVCNTR(30), 3696 /* PMEVTYPERn */ 3697 PMU_PMEVTYPER(0), 3698 PMU_PMEVTYPER(1), 3699 PMU_PMEVTYPER(2), 3700 PMU_PMEVTYPER(3), 3701 PMU_PMEVTYPER(4), 3702 PMU_PMEVTYPER(5), 3703 PMU_PMEVTYPER(6), 3704 PMU_PMEVTYPER(7), 3705 PMU_PMEVTYPER(8), 3706 PMU_PMEVTYPER(9), 3707 PMU_PMEVTYPER(10), 3708 PMU_PMEVTYPER(11), 3709 PMU_PMEVTYPER(12), 3710 PMU_PMEVTYPER(13), 3711 PMU_PMEVTYPER(14), 3712 PMU_PMEVTYPER(15), 3713 PMU_PMEVTYPER(16), 3714 PMU_PMEVTYPER(17), 3715 PMU_PMEVTYPER(18), 3716 PMU_PMEVTYPER(19), 3717 PMU_PMEVTYPER(20), 3718 PMU_PMEVTYPER(21), 3719 PMU_PMEVTYPER(22), 3720 PMU_PMEVTYPER(23), 3721 PMU_PMEVTYPER(24), 3722 PMU_PMEVTYPER(25), 3723 PMU_PMEVTYPER(26), 3724 PMU_PMEVTYPER(27), 3725 PMU_PMEVTYPER(28), 3726 PMU_PMEVTYPER(29), 3727 PMU_PMEVTYPER(30), 3728 /* PMCCFILTR */ 3729 { CP15_PMU_SYS_REG(DIRECT, 0, 14, 15, 7), .access = access_pmu_evtyper }, 3730 3731 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr }, 3732 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr }, 3733 3734 /* CCSIDR2 */ 3735 { Op1(1), CRn( 0), CRm( 0), Op2(2), undef_access }, 3736 3737 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 }, 3738 }; 3739 3740 static const struct sys_reg_desc cp15_64_regs[] = { 3741 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, 3742 { CP15_PMU_SYS_REG(DIRECT, 0, 0, 9, 0), .access = access_pmu_evcntr }, 3743 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */ 3744 { SYS_DESC(SYS_AARCH32_CNTPCT), access_arch_timer }, 3745 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 }, 3746 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */ 3747 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */ 3748 { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer }, 3749 { SYS_DESC(SYS_AARCH32_CNTPCTSS), access_arch_timer }, 3750 }; 3751 3752 static bool check_sysreg_table(const struct sys_reg_desc *table, unsigned int n, 3753 bool is_32) 3754 { 3755 unsigned int i; 3756 3757 for (i = 0; i < n; i++) { 3758 if (!is_32 && table[i].reg && !table[i].reset) { 3759 kvm_err("sys_reg table %pS entry %d (%s) lacks reset\n", 3760 &table[i], i, table[i].name); 3761 return false; 3762 } 3763 3764 if (i && cmp_sys_reg(&table[i-1], &table[i]) >= 0) { 3765 kvm_err("sys_reg table %pS entry %d (%s -> %s) out of order\n", 3766 &table[i], i, table[i - 1].name, table[i].name); 3767 return false; 3768 } 3769 } 3770 3771 return true; 3772 } 3773 3774 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu) 3775 { 3776 kvm_inject_undefined(vcpu); 3777 return 1; 3778 } 3779 3780 static void perform_access(struct kvm_vcpu *vcpu, 3781 struct sys_reg_params *params, 3782 const struct sys_reg_desc *r) 3783 { 3784 trace_kvm_sys_access(*vcpu_pc(vcpu), params, r); 3785 3786 /* Check for regs disabled by runtime config */ 3787 if (sysreg_hidden(vcpu, r)) { 3788 kvm_inject_undefined(vcpu); 3789 return; 3790 } 3791 3792 /* 3793 * Not having an accessor means that we have configured a trap 3794 * that we don't know how to handle. This certainly qualifies 3795 * as a gross bug that should be fixed right away. 3796 */ 3797 BUG_ON(!r->access); 3798 3799 /* Skip instruction if instructed so */ 3800 if (likely(r->access(vcpu, params, r))) 3801 kvm_incr_pc(vcpu); 3802 } 3803 3804 /* 3805 * emulate_cp -- tries to match a sys_reg access in a handling table, and 3806 * call the corresponding trap handler. 3807 * 3808 * @params: pointer to the descriptor of the access 3809 * @table: array of trap descriptors 3810 * @num: size of the trap descriptor array 3811 * 3812 * Return true if the access has been handled, false if not. 3813 */ 3814 static bool emulate_cp(struct kvm_vcpu *vcpu, 3815 struct sys_reg_params *params, 3816 const struct sys_reg_desc *table, 3817 size_t num) 3818 { 3819 const struct sys_reg_desc *r; 3820 3821 if (!table) 3822 return false; /* Not handled */ 3823 3824 r = find_reg(params, table, num); 3825 3826 if (r) { 3827 perform_access(vcpu, params, r); 3828 return true; 3829 } 3830 3831 /* Not handled */ 3832 return false; 3833 } 3834 3835 static void unhandled_cp_access(struct kvm_vcpu *vcpu, 3836 struct sys_reg_params *params) 3837 { 3838 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu); 3839 int cp = -1; 3840 3841 switch (esr_ec) { 3842 case ESR_ELx_EC_CP15_32: 3843 case ESR_ELx_EC_CP15_64: 3844 cp = 15; 3845 break; 3846 case ESR_ELx_EC_CP14_MR: 3847 case ESR_ELx_EC_CP14_64: 3848 cp = 14; 3849 break; 3850 default: 3851 WARN_ON(1); 3852 } 3853 3854 print_sys_reg_msg(params, 3855 "Unsupported guest CP%d access at: %08lx [%08lx]\n", 3856 cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 3857 kvm_inject_undefined(vcpu); 3858 } 3859 3860 /** 3861 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access 3862 * @vcpu: The VCPU pointer 3863 * @global: &struct sys_reg_desc 3864 * @nr_global: size of the @global array 3865 */ 3866 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu, 3867 const struct sys_reg_desc *global, 3868 size_t nr_global) 3869 { 3870 struct sys_reg_params params; 3871 u64 esr = kvm_vcpu_get_esr(vcpu); 3872 int Rt = kvm_vcpu_sys_get_rt(vcpu); 3873 int Rt2 = (esr >> 10) & 0x1f; 3874 3875 params.CRm = (esr >> 1) & 0xf; 3876 params.is_write = ((esr & 1) == 0); 3877 3878 params.Op0 = 0; 3879 params.Op1 = (esr >> 16) & 0xf; 3880 params.Op2 = 0; 3881 params.CRn = 0; 3882 3883 /* 3884 * Make a 64-bit value out of Rt and Rt2. As we use the same trap 3885 * backends between AArch32 and AArch64, we get away with it. 3886 */ 3887 if (params.is_write) { 3888 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff; 3889 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32; 3890 } 3891 3892 /* 3893 * If the table contains a handler, handle the 3894 * potential register operation in the case of a read and return 3895 * with success. 3896 */ 3897 if (emulate_cp(vcpu, ¶ms, global, nr_global)) { 3898 /* Split up the value between registers for the read side */ 3899 if (!params.is_write) { 3900 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval)); 3901 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval)); 3902 } 3903 3904 return 1; 3905 } 3906 3907 unhandled_cp_access(vcpu, ¶ms); 3908 return 1; 3909 } 3910 3911 static bool emulate_sys_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *params); 3912 3913 /* 3914 * The CP10 ID registers are architecturally mapped to AArch64 feature 3915 * registers. Abuse that fact so we can rely on the AArch64 handler for accesses 3916 * from AArch32. 3917 */ 3918 static bool kvm_esr_cp10_id_to_sys64(u64 esr, struct sys_reg_params *params) 3919 { 3920 u8 reg_id = (esr >> 10) & 0xf; 3921 bool valid; 3922 3923 params->is_write = ((esr & 1) == 0); 3924 params->Op0 = 3; 3925 params->Op1 = 0; 3926 params->CRn = 0; 3927 params->CRm = 3; 3928 3929 /* CP10 ID registers are read-only */ 3930 valid = !params->is_write; 3931 3932 switch (reg_id) { 3933 /* MVFR0 */ 3934 case 0b0111: 3935 params->Op2 = 0; 3936 break; 3937 /* MVFR1 */ 3938 case 0b0110: 3939 params->Op2 = 1; 3940 break; 3941 /* MVFR2 */ 3942 case 0b0101: 3943 params->Op2 = 2; 3944 break; 3945 default: 3946 valid = false; 3947 } 3948 3949 if (valid) 3950 return true; 3951 3952 kvm_pr_unimpl("Unhandled cp10 register %s: %u\n", 3953 params->is_write ? "write" : "read", reg_id); 3954 return false; 3955 } 3956 3957 /** 3958 * kvm_handle_cp10_id() - Handles a VMRS trap on guest access to a 'Media and 3959 * VFP Register' from AArch32. 3960 * @vcpu: The vCPU pointer 3961 * 3962 * MVFR{0-2} are architecturally mapped to the AArch64 MVFR{0-2}_EL1 registers. 3963 * Work out the correct AArch64 system register encoding and reroute to the 3964 * AArch64 system register emulation. 3965 */ 3966 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu) 3967 { 3968 int Rt = kvm_vcpu_sys_get_rt(vcpu); 3969 u64 esr = kvm_vcpu_get_esr(vcpu); 3970 struct sys_reg_params params; 3971 3972 /* UNDEF on any unhandled register access */ 3973 if (!kvm_esr_cp10_id_to_sys64(esr, ¶ms)) { 3974 kvm_inject_undefined(vcpu); 3975 return 1; 3976 } 3977 3978 if (emulate_sys_reg(vcpu, ¶ms)) 3979 vcpu_set_reg(vcpu, Rt, params.regval); 3980 3981 return 1; 3982 } 3983 3984 /** 3985 * kvm_emulate_cp15_id_reg() - Handles an MRC trap on a guest CP15 access where 3986 * CRn=0, which corresponds to the AArch32 feature 3987 * registers. 3988 * @vcpu: the vCPU pointer 3989 * @params: the system register access parameters. 3990 * 3991 * Our cp15 system register tables do not enumerate the AArch32 feature 3992 * registers. Conveniently, our AArch64 table does, and the AArch32 system 3993 * register encoding can be trivially remapped into the AArch64 for the feature 3994 * registers: Append op0=3, leaving op1, CRn, CRm, and op2 the same. 3995 * 3996 * According to DDI0487G.b G7.3.1, paragraph "Behavior of VMSAv8-32 32-bit 3997 * System registers with (coproc=0b1111, CRn==c0)", read accesses from this 3998 * range are either UNKNOWN or RES0. Rerouting remains architectural as we 3999 * treat undefined registers in this range as RAZ. 4000 */ 4001 static int kvm_emulate_cp15_id_reg(struct kvm_vcpu *vcpu, 4002 struct sys_reg_params *params) 4003 { 4004 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4005 4006 /* Treat impossible writes to RO registers as UNDEFINED */ 4007 if (params->is_write) { 4008 unhandled_cp_access(vcpu, params); 4009 return 1; 4010 } 4011 4012 params->Op0 = 3; 4013 4014 /* 4015 * All registers where CRm > 3 are known to be UNKNOWN/RAZ from AArch32. 4016 * Avoid conflicting with future expansion of AArch64 feature registers 4017 * and simply treat them as RAZ here. 4018 */ 4019 if (params->CRm > 3) 4020 params->regval = 0; 4021 else if (!emulate_sys_reg(vcpu, params)) 4022 return 1; 4023 4024 vcpu_set_reg(vcpu, Rt, params->regval); 4025 return 1; 4026 } 4027 4028 /** 4029 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access 4030 * @vcpu: The VCPU pointer 4031 * @params: &struct sys_reg_params 4032 * @global: &struct sys_reg_desc 4033 * @nr_global: size of the @global array 4034 */ 4035 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu, 4036 struct sys_reg_params *params, 4037 const struct sys_reg_desc *global, 4038 size_t nr_global) 4039 { 4040 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4041 4042 params->regval = vcpu_get_reg(vcpu, Rt); 4043 4044 if (emulate_cp(vcpu, params, global, nr_global)) { 4045 if (!params->is_write) 4046 vcpu_set_reg(vcpu, Rt, params->regval); 4047 return 1; 4048 } 4049 4050 unhandled_cp_access(vcpu, params); 4051 return 1; 4052 } 4053 4054 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu) 4055 { 4056 return kvm_handle_cp_64(vcpu, cp15_64_regs, ARRAY_SIZE(cp15_64_regs)); 4057 } 4058 4059 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu) 4060 { 4061 struct sys_reg_params params; 4062 4063 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu)); 4064 4065 /* 4066 * Certain AArch32 ID registers are handled by rerouting to the AArch64 4067 * system register table. Registers in the ID range where CRm=0 are 4068 * excluded from this scheme as they do not trivially map into AArch64 4069 * system register encodings. 4070 */ 4071 if (params.Op1 == 0 && params.CRn == 0 && params.CRm) 4072 return kvm_emulate_cp15_id_reg(vcpu, ¶ms); 4073 4074 return kvm_handle_cp_32(vcpu, ¶ms, cp15_regs, ARRAY_SIZE(cp15_regs)); 4075 } 4076 4077 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu) 4078 { 4079 return kvm_handle_cp_64(vcpu, cp14_64_regs, ARRAY_SIZE(cp14_64_regs)); 4080 } 4081 4082 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu) 4083 { 4084 struct sys_reg_params params; 4085 4086 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu)); 4087 4088 return kvm_handle_cp_32(vcpu, ¶ms, cp14_regs, ARRAY_SIZE(cp14_regs)); 4089 } 4090 4091 /** 4092 * emulate_sys_reg - Emulate a guest access to an AArch64 system register 4093 * @vcpu: The VCPU pointer 4094 * @params: Decoded system register parameters 4095 * 4096 * Return: true if the system register access was successful, false otherwise. 4097 */ 4098 static bool emulate_sys_reg(struct kvm_vcpu *vcpu, 4099 struct sys_reg_params *params) 4100 { 4101 const struct sys_reg_desc *r; 4102 4103 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 4104 if (likely(r)) { 4105 perform_access(vcpu, params, r); 4106 return true; 4107 } 4108 4109 print_sys_reg_msg(params, 4110 "Unsupported guest sys_reg access at: %lx [%08lx]\n", 4111 *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 4112 kvm_inject_undefined(vcpu); 4113 4114 return false; 4115 } 4116 4117 static const struct sys_reg_desc *idregs_debug_find(struct kvm *kvm, u8 pos) 4118 { 4119 unsigned long i, idreg_idx = 0; 4120 4121 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { 4122 const struct sys_reg_desc *r = &sys_reg_descs[i]; 4123 4124 if (!is_vm_ftr_id_reg(reg_to_encoding(r))) 4125 continue; 4126 4127 if (idreg_idx == pos) 4128 return r; 4129 4130 idreg_idx++; 4131 } 4132 4133 return NULL; 4134 } 4135 4136 static void *idregs_debug_start(struct seq_file *s, loff_t *pos) 4137 { 4138 struct kvm *kvm = s->private; 4139 u8 *iter; 4140 4141 mutex_lock(&kvm->arch.config_lock); 4142 4143 iter = &kvm->arch.idreg_debugfs_iter; 4144 if (test_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags) && 4145 *iter == (u8)~0) { 4146 *iter = *pos; 4147 if (!idregs_debug_find(kvm, *iter)) 4148 iter = NULL; 4149 } else { 4150 iter = ERR_PTR(-EBUSY); 4151 } 4152 4153 mutex_unlock(&kvm->arch.config_lock); 4154 4155 return iter; 4156 } 4157 4158 static void *idregs_debug_next(struct seq_file *s, void *v, loff_t *pos) 4159 { 4160 struct kvm *kvm = s->private; 4161 4162 (*pos)++; 4163 4164 if (idregs_debug_find(kvm, kvm->arch.idreg_debugfs_iter + 1)) { 4165 kvm->arch.idreg_debugfs_iter++; 4166 4167 return &kvm->arch.idreg_debugfs_iter; 4168 } 4169 4170 return NULL; 4171 } 4172 4173 static void idregs_debug_stop(struct seq_file *s, void *v) 4174 { 4175 struct kvm *kvm = s->private; 4176 4177 if (IS_ERR(v)) 4178 return; 4179 4180 mutex_lock(&kvm->arch.config_lock); 4181 4182 kvm->arch.idreg_debugfs_iter = ~0; 4183 4184 mutex_unlock(&kvm->arch.config_lock); 4185 } 4186 4187 static int idregs_debug_show(struct seq_file *s, void *v) 4188 { 4189 const struct sys_reg_desc *desc; 4190 struct kvm *kvm = s->private; 4191 4192 desc = idregs_debug_find(kvm, kvm->arch.idreg_debugfs_iter); 4193 4194 if (!desc->name) 4195 return 0; 4196 4197 seq_printf(s, "%20s:\t%016llx\n", 4198 desc->name, kvm_read_vm_id_reg(kvm, reg_to_encoding(desc))); 4199 4200 return 0; 4201 } 4202 4203 static const struct seq_operations idregs_debug_sops = { 4204 .start = idregs_debug_start, 4205 .next = idregs_debug_next, 4206 .stop = idregs_debug_stop, 4207 .show = idregs_debug_show, 4208 }; 4209 4210 DEFINE_SEQ_ATTRIBUTE(idregs_debug); 4211 4212 void kvm_sys_regs_create_debugfs(struct kvm *kvm) 4213 { 4214 kvm->arch.idreg_debugfs_iter = ~0; 4215 4216 debugfs_create_file("idregs", 0444, kvm->debugfs_dentry, kvm, 4217 &idregs_debug_fops); 4218 } 4219 4220 static void reset_vm_ftr_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *reg) 4221 { 4222 u32 id = reg_to_encoding(reg); 4223 struct kvm *kvm = vcpu->kvm; 4224 4225 if (test_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags)) 4226 return; 4227 4228 kvm_set_vm_id_reg(kvm, id, reg->reset(vcpu, reg)); 4229 } 4230 4231 static void reset_vcpu_ftr_id_reg(struct kvm_vcpu *vcpu, 4232 const struct sys_reg_desc *reg) 4233 { 4234 if (kvm_vcpu_initialized(vcpu)) 4235 return; 4236 4237 reg->reset(vcpu, reg); 4238 } 4239 4240 /** 4241 * kvm_reset_sys_regs - sets system registers to reset value 4242 * @vcpu: The VCPU pointer 4243 * 4244 * This function finds the right table above and sets the registers on the 4245 * virtual CPU struct to their architecturally defined reset values. 4246 */ 4247 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu) 4248 { 4249 struct kvm *kvm = vcpu->kvm; 4250 unsigned long i; 4251 4252 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { 4253 const struct sys_reg_desc *r = &sys_reg_descs[i]; 4254 4255 if (!r->reset) 4256 continue; 4257 4258 if (is_vm_ftr_id_reg(reg_to_encoding(r))) 4259 reset_vm_ftr_id_reg(vcpu, r); 4260 else if (is_vcpu_ftr_id_reg(reg_to_encoding(r))) 4261 reset_vcpu_ftr_id_reg(vcpu, r); 4262 else 4263 r->reset(vcpu, r); 4264 } 4265 4266 set_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags); 4267 } 4268 4269 /** 4270 * kvm_handle_sys_reg -- handles a system instruction or mrs/msr instruction 4271 * trap on a guest execution 4272 * @vcpu: The VCPU pointer 4273 */ 4274 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu) 4275 { 4276 const struct sys_reg_desc *desc = NULL; 4277 struct sys_reg_params params; 4278 unsigned long esr = kvm_vcpu_get_esr(vcpu); 4279 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4280 int sr_idx; 4281 4282 trace_kvm_handle_sys_reg(esr); 4283 4284 if (triage_sysreg_trap(vcpu, &sr_idx)) 4285 return 1; 4286 4287 params = esr_sys64_to_params(esr); 4288 params.regval = vcpu_get_reg(vcpu, Rt); 4289 4290 /* System registers have Op0=={2,3}, as per DDI487 J.a C5.1.2 */ 4291 if (params.Op0 == 2 || params.Op0 == 3) 4292 desc = &sys_reg_descs[sr_idx]; 4293 else 4294 desc = &sys_insn_descs[sr_idx]; 4295 4296 perform_access(vcpu, ¶ms, desc); 4297 4298 /* Read from system register? */ 4299 if (!params.is_write && 4300 (params.Op0 == 2 || params.Op0 == 3)) 4301 vcpu_set_reg(vcpu, Rt, params.regval); 4302 4303 return 1; 4304 } 4305 4306 /****************************************************************************** 4307 * Userspace API 4308 *****************************************************************************/ 4309 4310 static bool index_to_params(u64 id, struct sys_reg_params *params) 4311 { 4312 switch (id & KVM_REG_SIZE_MASK) { 4313 case KVM_REG_SIZE_U64: 4314 /* Any unused index bits means it's not valid. */ 4315 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK 4316 | KVM_REG_ARM_COPROC_MASK 4317 | KVM_REG_ARM64_SYSREG_OP0_MASK 4318 | KVM_REG_ARM64_SYSREG_OP1_MASK 4319 | KVM_REG_ARM64_SYSREG_CRN_MASK 4320 | KVM_REG_ARM64_SYSREG_CRM_MASK 4321 | KVM_REG_ARM64_SYSREG_OP2_MASK)) 4322 return false; 4323 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK) 4324 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT); 4325 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK) 4326 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT); 4327 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK) 4328 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT); 4329 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK) 4330 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT); 4331 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK) 4332 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT); 4333 return true; 4334 default: 4335 return false; 4336 } 4337 } 4338 4339 const struct sys_reg_desc *get_reg_by_id(u64 id, 4340 const struct sys_reg_desc table[], 4341 unsigned int num) 4342 { 4343 struct sys_reg_params params; 4344 4345 if (!index_to_params(id, ¶ms)) 4346 return NULL; 4347 4348 return find_reg(¶ms, table, num); 4349 } 4350 4351 /* Decode an index value, and find the sys_reg_desc entry. */ 4352 static const struct sys_reg_desc * 4353 id_to_sys_reg_desc(struct kvm_vcpu *vcpu, u64 id, 4354 const struct sys_reg_desc table[], unsigned int num) 4355 4356 { 4357 const struct sys_reg_desc *r; 4358 4359 /* We only do sys_reg for now. */ 4360 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG) 4361 return NULL; 4362 4363 r = get_reg_by_id(id, table, num); 4364 4365 /* Not saved in the sys_reg array and not otherwise accessible? */ 4366 if (r && (!(r->reg || r->get_user) || sysreg_hidden(vcpu, r))) 4367 r = NULL; 4368 4369 return r; 4370 } 4371 4372 /* 4373 * These are the invariant sys_reg registers: we let the guest see the 4374 * host versions of these, so they're part of the guest state. 4375 * 4376 * A future CPU may provide a mechanism to present different values to 4377 * the guest, or a future kvm may trap them. 4378 */ 4379 4380 #define FUNCTION_INVARIANT(reg) \ 4381 static u64 reset_##reg(struct kvm_vcpu *v, \ 4382 const struct sys_reg_desc *r) \ 4383 { \ 4384 ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \ 4385 return ((struct sys_reg_desc *)r)->val; \ 4386 } 4387 4388 FUNCTION_INVARIANT(midr_el1) 4389 FUNCTION_INVARIANT(revidr_el1) 4390 FUNCTION_INVARIANT(aidr_el1) 4391 4392 /* ->val is filled in by kvm_sys_reg_table_init() */ 4393 static struct sys_reg_desc invariant_sys_regs[] __ro_after_init = { 4394 { SYS_DESC(SYS_MIDR_EL1), NULL, reset_midr_el1 }, 4395 { SYS_DESC(SYS_REVIDR_EL1), NULL, reset_revidr_el1 }, 4396 { SYS_DESC(SYS_AIDR_EL1), NULL, reset_aidr_el1 }, 4397 }; 4398 4399 static int get_invariant_sys_reg(u64 id, u64 __user *uaddr) 4400 { 4401 const struct sys_reg_desc *r; 4402 4403 r = get_reg_by_id(id, invariant_sys_regs, 4404 ARRAY_SIZE(invariant_sys_regs)); 4405 if (!r) 4406 return -ENOENT; 4407 4408 return put_user(r->val, uaddr); 4409 } 4410 4411 static int set_invariant_sys_reg(u64 id, u64 __user *uaddr) 4412 { 4413 const struct sys_reg_desc *r; 4414 u64 val; 4415 4416 r = get_reg_by_id(id, invariant_sys_regs, 4417 ARRAY_SIZE(invariant_sys_regs)); 4418 if (!r) 4419 return -ENOENT; 4420 4421 if (get_user(val, uaddr)) 4422 return -EFAULT; 4423 4424 /* This is what we mean by invariant: you can't change it. */ 4425 if (r->val != val) 4426 return -EINVAL; 4427 4428 return 0; 4429 } 4430 4431 static int demux_c15_get(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) 4432 { 4433 u32 val; 4434 u32 __user *uval = uaddr; 4435 4436 /* Fail if we have unknown bits set. */ 4437 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 4438 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 4439 return -ENOENT; 4440 4441 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 4442 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 4443 if (KVM_REG_SIZE(id) != 4) 4444 return -ENOENT; 4445 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 4446 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 4447 if (val >= CSSELR_MAX) 4448 return -ENOENT; 4449 4450 return put_user(get_ccsidr(vcpu, val), uval); 4451 default: 4452 return -ENOENT; 4453 } 4454 } 4455 4456 static int demux_c15_set(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) 4457 { 4458 u32 val, newval; 4459 u32 __user *uval = uaddr; 4460 4461 /* Fail if we have unknown bits set. */ 4462 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 4463 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 4464 return -ENOENT; 4465 4466 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 4467 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 4468 if (KVM_REG_SIZE(id) != 4) 4469 return -ENOENT; 4470 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 4471 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 4472 if (val >= CSSELR_MAX) 4473 return -ENOENT; 4474 4475 if (get_user(newval, uval)) 4476 return -EFAULT; 4477 4478 return set_ccsidr(vcpu, val, newval); 4479 default: 4480 return -ENOENT; 4481 } 4482 } 4483 4484 int kvm_sys_reg_get_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg, 4485 const struct sys_reg_desc table[], unsigned int num) 4486 { 4487 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr; 4488 const struct sys_reg_desc *r; 4489 u64 val; 4490 int ret; 4491 4492 r = id_to_sys_reg_desc(vcpu, reg->id, table, num); 4493 if (!r || sysreg_hidden(vcpu, r)) 4494 return -ENOENT; 4495 4496 if (r->get_user) { 4497 ret = (r->get_user)(vcpu, r, &val); 4498 } else { 4499 val = __vcpu_sys_reg(vcpu, r->reg); 4500 ret = 0; 4501 } 4502 4503 if (!ret) 4504 ret = put_user(val, uaddr); 4505 4506 return ret; 4507 } 4508 4509 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 4510 { 4511 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 4512 int err; 4513 4514 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 4515 return demux_c15_get(vcpu, reg->id, uaddr); 4516 4517 err = get_invariant_sys_reg(reg->id, uaddr); 4518 if (err != -ENOENT) 4519 return err; 4520 4521 return kvm_sys_reg_get_user(vcpu, reg, 4522 sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 4523 } 4524 4525 int kvm_sys_reg_set_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg, 4526 const struct sys_reg_desc table[], unsigned int num) 4527 { 4528 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr; 4529 const struct sys_reg_desc *r; 4530 u64 val; 4531 int ret; 4532 4533 if (get_user(val, uaddr)) 4534 return -EFAULT; 4535 4536 r = id_to_sys_reg_desc(vcpu, reg->id, table, num); 4537 if (!r || sysreg_hidden(vcpu, r)) 4538 return -ENOENT; 4539 4540 if (sysreg_user_write_ignore(vcpu, r)) 4541 return 0; 4542 4543 if (r->set_user) { 4544 ret = (r->set_user)(vcpu, r, val); 4545 } else { 4546 __vcpu_sys_reg(vcpu, r->reg) = val; 4547 ret = 0; 4548 } 4549 4550 return ret; 4551 } 4552 4553 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 4554 { 4555 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 4556 int err; 4557 4558 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 4559 return demux_c15_set(vcpu, reg->id, uaddr); 4560 4561 err = set_invariant_sys_reg(reg->id, uaddr); 4562 if (err != -ENOENT) 4563 return err; 4564 4565 return kvm_sys_reg_set_user(vcpu, reg, 4566 sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 4567 } 4568 4569 static unsigned int num_demux_regs(void) 4570 { 4571 return CSSELR_MAX; 4572 } 4573 4574 static int write_demux_regids(u64 __user *uindices) 4575 { 4576 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX; 4577 unsigned int i; 4578 4579 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR; 4580 for (i = 0; i < CSSELR_MAX; i++) { 4581 if (put_user(val | i, uindices)) 4582 return -EFAULT; 4583 uindices++; 4584 } 4585 return 0; 4586 } 4587 4588 static u64 sys_reg_to_index(const struct sys_reg_desc *reg) 4589 { 4590 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | 4591 KVM_REG_ARM64_SYSREG | 4592 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) | 4593 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) | 4594 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) | 4595 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) | 4596 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT)); 4597 } 4598 4599 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind) 4600 { 4601 if (!*uind) 4602 return true; 4603 4604 if (put_user(sys_reg_to_index(reg), *uind)) 4605 return false; 4606 4607 (*uind)++; 4608 return true; 4609 } 4610 4611 static int walk_one_sys_reg(const struct kvm_vcpu *vcpu, 4612 const struct sys_reg_desc *rd, 4613 u64 __user **uind, 4614 unsigned int *total) 4615 { 4616 /* 4617 * Ignore registers we trap but don't save, 4618 * and for which no custom user accessor is provided. 4619 */ 4620 if (!(rd->reg || rd->get_user)) 4621 return 0; 4622 4623 if (sysreg_hidden(vcpu, rd)) 4624 return 0; 4625 4626 if (!copy_reg_to_user(rd, uind)) 4627 return -EFAULT; 4628 4629 (*total)++; 4630 return 0; 4631 } 4632 4633 /* Assumed ordered tables, see kvm_sys_reg_table_init. */ 4634 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind) 4635 { 4636 const struct sys_reg_desc *i2, *end2; 4637 unsigned int total = 0; 4638 int err; 4639 4640 i2 = sys_reg_descs; 4641 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs); 4642 4643 while (i2 != end2) { 4644 err = walk_one_sys_reg(vcpu, i2++, &uind, &total); 4645 if (err) 4646 return err; 4647 } 4648 return total; 4649 } 4650 4651 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu) 4652 { 4653 return ARRAY_SIZE(invariant_sys_regs) 4654 + num_demux_regs() 4655 + walk_sys_regs(vcpu, (u64 __user *)NULL); 4656 } 4657 4658 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) 4659 { 4660 unsigned int i; 4661 int err; 4662 4663 /* Then give them all the invariant registers' indices. */ 4664 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) { 4665 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices)) 4666 return -EFAULT; 4667 uindices++; 4668 } 4669 4670 err = walk_sys_regs(vcpu, uindices); 4671 if (err < 0) 4672 return err; 4673 uindices += err; 4674 4675 return write_demux_regids(uindices); 4676 } 4677 4678 #define KVM_ARM_FEATURE_ID_RANGE_INDEX(r) \ 4679 KVM_ARM_FEATURE_ID_RANGE_IDX(sys_reg_Op0(r), \ 4680 sys_reg_Op1(r), \ 4681 sys_reg_CRn(r), \ 4682 sys_reg_CRm(r), \ 4683 sys_reg_Op2(r)) 4684 4685 int kvm_vm_ioctl_get_reg_writable_masks(struct kvm *kvm, struct reg_mask_range *range) 4686 { 4687 const void *zero_page = page_to_virt(ZERO_PAGE(0)); 4688 u64 __user *masks = (u64 __user *)range->addr; 4689 4690 /* Only feature id range is supported, reserved[13] must be zero. */ 4691 if (range->range || 4692 memcmp(range->reserved, zero_page, sizeof(range->reserved))) 4693 return -EINVAL; 4694 4695 /* Wipe the whole thing first */ 4696 if (clear_user(masks, KVM_ARM_FEATURE_ID_RANGE_SIZE * sizeof(__u64))) 4697 return -EFAULT; 4698 4699 for (int i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { 4700 const struct sys_reg_desc *reg = &sys_reg_descs[i]; 4701 u32 encoding = reg_to_encoding(reg); 4702 u64 val; 4703 4704 if (!is_feature_id_reg(encoding) || !reg->set_user) 4705 continue; 4706 4707 if (!reg->val || 4708 (is_aa32_id_reg(encoding) && !kvm_supports_32bit_el0())) { 4709 continue; 4710 } 4711 val = reg->val; 4712 4713 if (put_user(val, (masks + KVM_ARM_FEATURE_ID_RANGE_INDEX(encoding)))) 4714 return -EFAULT; 4715 } 4716 4717 return 0; 4718 } 4719 4720 static void vcpu_set_hcr(struct kvm_vcpu *vcpu) 4721 { 4722 struct kvm *kvm = vcpu->kvm; 4723 4724 if (has_vhe() || has_hvhe()) 4725 vcpu->arch.hcr_el2 |= HCR_E2H; 4726 if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN)) { 4727 /* route synchronous external abort exceptions to EL2 */ 4728 vcpu->arch.hcr_el2 |= HCR_TEA; 4729 /* trap error record accesses */ 4730 vcpu->arch.hcr_el2 |= HCR_TERR; 4731 } 4732 4733 if (cpus_have_final_cap(ARM64_HAS_STAGE2_FWB)) 4734 vcpu->arch.hcr_el2 |= HCR_FWB; 4735 4736 if (cpus_have_final_cap(ARM64_HAS_EVT) && 4737 !cpus_have_final_cap(ARM64_MISMATCHED_CACHE_TYPE) && 4738 kvm_read_vm_id_reg(kvm, SYS_CTR_EL0) == read_sanitised_ftr_reg(SYS_CTR_EL0)) 4739 vcpu->arch.hcr_el2 |= HCR_TID4; 4740 else 4741 vcpu->arch.hcr_el2 |= HCR_TID2; 4742 4743 if (vcpu_el1_is_32bit(vcpu)) 4744 vcpu->arch.hcr_el2 &= ~HCR_RW; 4745 4746 if (kvm_has_mte(vcpu->kvm)) 4747 vcpu->arch.hcr_el2 |= HCR_ATA; 4748 4749 /* 4750 * In the absence of FGT, we cannot independently trap TLBI 4751 * Range instructions. This isn't great, but trapping all 4752 * TLBIs would be far worse. Live with it... 4753 */ 4754 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 4755 vcpu->arch.hcr_el2 |= HCR_TTLBOS; 4756 } 4757 4758 void kvm_calculate_traps(struct kvm_vcpu *vcpu) 4759 { 4760 struct kvm *kvm = vcpu->kvm; 4761 4762 mutex_lock(&kvm->arch.config_lock); 4763 vcpu_set_hcr(vcpu); 4764 vcpu_set_ich_hcr(vcpu); 4765 4766 if (cpus_have_final_cap(ARM64_HAS_HCX)) { 4767 /* 4768 * In general, all HCRX_EL2 bits are gated by a feature. 4769 * The only reason we can set SMPME without checking any 4770 * feature is that its effects are not directly observable 4771 * from the guest. 4772 */ 4773 vcpu->arch.hcrx_el2 = HCRX_EL2_SMPME; 4774 4775 if (kvm_has_feat(kvm, ID_AA64ISAR2_EL1, MOPS, IMP)) 4776 vcpu->arch.hcrx_el2 |= (HCRX_EL2_MSCEn | HCRX_EL2_MCE2); 4777 4778 if (kvm_has_feat(kvm, ID_AA64MMFR3_EL1, TCRX, IMP)) 4779 vcpu->arch.hcrx_el2 |= HCRX_EL2_TCR2En; 4780 4781 if (kvm_has_fpmr(kvm)) 4782 vcpu->arch.hcrx_el2 |= HCRX_EL2_EnFPM; 4783 } 4784 4785 if (test_bit(KVM_ARCH_FLAG_FGU_INITIALIZED, &kvm->arch.flags)) 4786 goto out; 4787 4788 kvm->arch.fgu[HFGxTR_GROUP] = (HFGxTR_EL2_nAMAIR2_EL1 | 4789 HFGxTR_EL2_nMAIR2_EL1 | 4790 HFGxTR_EL2_nS2POR_EL1 | 4791 HFGxTR_EL2_nACCDATA_EL1 | 4792 HFGxTR_EL2_nSMPRI_EL1_MASK | 4793 HFGxTR_EL2_nTPIDR2_EL0_MASK); 4794 4795 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 4796 kvm->arch.fgu[HFGITR_GROUP] |= (HFGITR_EL2_TLBIRVAALE1OS| 4797 HFGITR_EL2_TLBIRVALE1OS | 4798 HFGITR_EL2_TLBIRVAAE1OS | 4799 HFGITR_EL2_TLBIRVAE1OS | 4800 HFGITR_EL2_TLBIVAALE1OS | 4801 HFGITR_EL2_TLBIVALE1OS | 4802 HFGITR_EL2_TLBIVAAE1OS | 4803 HFGITR_EL2_TLBIASIDE1OS | 4804 HFGITR_EL2_TLBIVAE1OS | 4805 HFGITR_EL2_TLBIVMALLE1OS); 4806 4807 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE)) 4808 kvm->arch.fgu[HFGITR_GROUP] |= (HFGITR_EL2_TLBIRVAALE1 | 4809 HFGITR_EL2_TLBIRVALE1 | 4810 HFGITR_EL2_TLBIRVAAE1 | 4811 HFGITR_EL2_TLBIRVAE1 | 4812 HFGITR_EL2_TLBIRVAALE1IS| 4813 HFGITR_EL2_TLBIRVALE1IS | 4814 HFGITR_EL2_TLBIRVAAE1IS | 4815 HFGITR_EL2_TLBIRVAE1IS | 4816 HFGITR_EL2_TLBIRVAALE1OS| 4817 HFGITR_EL2_TLBIRVALE1OS | 4818 HFGITR_EL2_TLBIRVAAE1OS | 4819 HFGITR_EL2_TLBIRVAE1OS); 4820 4821 if (!kvm_has_feat(kvm, ID_AA64ISAR2_EL1, ATS1A, IMP)) 4822 kvm->arch.fgu[HFGITR_GROUP] |= HFGITR_EL2_ATS1E1A; 4823 4824 if (!kvm_has_feat(kvm, ID_AA64MMFR1_EL1, PAN, PAN2)) 4825 kvm->arch.fgu[HFGITR_GROUP] |= (HFGITR_EL2_ATS1E1RP | 4826 HFGITR_EL2_ATS1E1WP); 4827 4828 if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, S1PIE, IMP)) 4829 kvm->arch.fgu[HFGxTR_GROUP] |= (HFGxTR_EL2_nPIRE0_EL1 | 4830 HFGxTR_EL2_nPIR_EL1); 4831 4832 if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, S1POE, IMP)) 4833 kvm->arch.fgu[HFGxTR_GROUP] |= (HFGxTR_EL2_nPOR_EL1 | 4834 HFGxTR_EL2_nPOR_EL0); 4835 4836 if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, AMU, IMP)) 4837 kvm->arch.fgu[HAFGRTR_GROUP] |= ~(HAFGRTR_EL2_RES0 | 4838 HAFGRTR_EL2_RES1); 4839 4840 set_bit(KVM_ARCH_FLAG_FGU_INITIALIZED, &kvm->arch.flags); 4841 out: 4842 mutex_unlock(&kvm->arch.config_lock); 4843 } 4844 4845 /* 4846 * Perform last adjustments to the ID registers that are implied by the 4847 * configuration outside of the ID regs themselves, as well as any 4848 * initialisation that directly depend on these ID registers (such as 4849 * RES0/RES1 behaviours). This is not the place to configure traps though. 4850 * 4851 * Because this can be called once per CPU, changes must be idempotent. 4852 */ 4853 int kvm_finalize_sys_regs(struct kvm_vcpu *vcpu) 4854 { 4855 struct kvm *kvm = vcpu->kvm; 4856 4857 guard(mutex)(&kvm->arch.config_lock); 4858 4859 if (!(static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif) && 4860 irqchip_in_kernel(kvm) && 4861 kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3)) { 4862 kvm->arch.id_regs[IDREG_IDX(SYS_ID_AA64PFR0_EL1)] &= ~ID_AA64PFR0_EL1_GIC_MASK; 4863 kvm->arch.id_regs[IDREG_IDX(SYS_ID_PFR1_EL1)] &= ~ID_PFR1_EL1_GIC_MASK; 4864 } 4865 4866 if (vcpu_has_nv(vcpu)) { 4867 int ret = kvm_init_nv_sysregs(kvm); 4868 if (ret) 4869 return ret; 4870 } 4871 4872 return 0; 4873 } 4874 4875 int __init kvm_sys_reg_table_init(void) 4876 { 4877 bool valid = true; 4878 unsigned int i; 4879 int ret = 0; 4880 4881 /* Make sure tables are unique and in order. */ 4882 valid &= check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), false); 4883 valid &= check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), true); 4884 valid &= check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), true); 4885 valid &= check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), true); 4886 valid &= check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), true); 4887 valid &= check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs), false); 4888 valid &= check_sysreg_table(sys_insn_descs, ARRAY_SIZE(sys_insn_descs), false); 4889 4890 if (!valid) 4891 return -EINVAL; 4892 4893 /* We abuse the reset function to overwrite the table itself. */ 4894 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) 4895 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]); 4896 4897 ret = populate_nv_trap_config(); 4898 4899 for (i = 0; !ret && i < ARRAY_SIZE(sys_reg_descs); i++) 4900 ret = populate_sysreg_config(sys_reg_descs + i, i); 4901 4902 for (i = 0; !ret && i < ARRAY_SIZE(sys_insn_descs); i++) 4903 ret = populate_sysreg_config(sys_insn_descs + i, i); 4904 4905 return ret; 4906 } 4907