1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/kvm/coproc.c: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Authors: Rusty Russell <rusty@rustcorp.com.au> 9 * Christoffer Dall <c.dall@virtualopensystems.com> 10 */ 11 12 #include <linux/bitfield.h> 13 #include <linux/bsearch.h> 14 #include <linux/cacheinfo.h> 15 #include <linux/debugfs.h> 16 #include <linux/kvm_host.h> 17 #include <linux/mm.h> 18 #include <linux/printk.h> 19 #include <linux/uaccess.h> 20 21 #include <asm/arm_pmuv3.h> 22 #include <asm/cacheflush.h> 23 #include <asm/cputype.h> 24 #include <asm/debug-monitors.h> 25 #include <asm/esr.h> 26 #include <asm/kvm_arm.h> 27 #include <asm/kvm_emulate.h> 28 #include <asm/kvm_hyp.h> 29 #include <asm/kvm_mmu.h> 30 #include <asm/kvm_nested.h> 31 #include <asm/perf_event.h> 32 #include <asm/sysreg.h> 33 34 #include <trace/events/kvm.h> 35 36 #include "sys_regs.h" 37 #include "vgic/vgic.h" 38 39 #include "trace.h" 40 41 /* 42 * For AArch32, we only take care of what is being trapped. Anything 43 * that has to do with init and userspace access has to go via the 44 * 64bit interface. 45 */ 46 47 static u64 sys_reg_to_index(const struct sys_reg_desc *reg); 48 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 49 u64 val); 50 51 static bool undef_access(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 52 const struct sys_reg_desc *r) 53 { 54 kvm_inject_undefined(vcpu); 55 return false; 56 } 57 58 static bool bad_trap(struct kvm_vcpu *vcpu, 59 struct sys_reg_params *params, 60 const struct sys_reg_desc *r, 61 const char *msg) 62 { 63 WARN_ONCE(1, "Unexpected %s\n", msg); 64 print_sys_reg_instr(params); 65 return undef_access(vcpu, params, r); 66 } 67 68 static bool read_from_write_only(struct kvm_vcpu *vcpu, 69 struct sys_reg_params *params, 70 const struct sys_reg_desc *r) 71 { 72 return bad_trap(vcpu, params, r, 73 "sys_reg read to write-only register"); 74 } 75 76 static bool write_to_read_only(struct kvm_vcpu *vcpu, 77 struct sys_reg_params *params, 78 const struct sys_reg_desc *r) 79 { 80 return bad_trap(vcpu, params, r, 81 "sys_reg write to read-only register"); 82 } 83 84 #define PURE_EL2_SYSREG(el2) \ 85 case el2: { \ 86 *el1r = el2; \ 87 return true; \ 88 } 89 90 #define MAPPED_EL2_SYSREG(el2, el1, fn) \ 91 case el2: { \ 92 *xlate = fn; \ 93 *el1r = el1; \ 94 return true; \ 95 } 96 97 static bool get_el2_to_el1_mapping(unsigned int reg, 98 unsigned int *el1r, u64 (**xlate)(u64)) 99 { 100 switch (reg) { 101 PURE_EL2_SYSREG( VPIDR_EL2 ); 102 PURE_EL2_SYSREG( VMPIDR_EL2 ); 103 PURE_EL2_SYSREG( ACTLR_EL2 ); 104 PURE_EL2_SYSREG( HCR_EL2 ); 105 PURE_EL2_SYSREG( MDCR_EL2 ); 106 PURE_EL2_SYSREG( HSTR_EL2 ); 107 PURE_EL2_SYSREG( HACR_EL2 ); 108 PURE_EL2_SYSREG( VTTBR_EL2 ); 109 PURE_EL2_SYSREG( VTCR_EL2 ); 110 PURE_EL2_SYSREG( RVBAR_EL2 ); 111 PURE_EL2_SYSREG( TPIDR_EL2 ); 112 PURE_EL2_SYSREG( HPFAR_EL2 ); 113 PURE_EL2_SYSREG( HCRX_EL2 ); 114 PURE_EL2_SYSREG( HFGRTR_EL2 ); 115 PURE_EL2_SYSREG( HFGWTR_EL2 ); 116 PURE_EL2_SYSREG( HFGITR_EL2 ); 117 PURE_EL2_SYSREG( HDFGRTR_EL2 ); 118 PURE_EL2_SYSREG( HDFGWTR_EL2 ); 119 PURE_EL2_SYSREG( HAFGRTR_EL2 ); 120 PURE_EL2_SYSREG( CNTVOFF_EL2 ); 121 PURE_EL2_SYSREG( CNTHCTL_EL2 ); 122 MAPPED_EL2_SYSREG(SCTLR_EL2, SCTLR_EL1, 123 translate_sctlr_el2_to_sctlr_el1 ); 124 MAPPED_EL2_SYSREG(CPTR_EL2, CPACR_EL1, 125 translate_cptr_el2_to_cpacr_el1 ); 126 MAPPED_EL2_SYSREG(TTBR0_EL2, TTBR0_EL1, 127 translate_ttbr0_el2_to_ttbr0_el1 ); 128 MAPPED_EL2_SYSREG(TTBR1_EL2, TTBR1_EL1, NULL ); 129 MAPPED_EL2_SYSREG(TCR_EL2, TCR_EL1, 130 translate_tcr_el2_to_tcr_el1 ); 131 MAPPED_EL2_SYSREG(VBAR_EL2, VBAR_EL1, NULL ); 132 MAPPED_EL2_SYSREG(AFSR0_EL2, AFSR0_EL1, NULL ); 133 MAPPED_EL2_SYSREG(AFSR1_EL2, AFSR1_EL1, NULL ); 134 MAPPED_EL2_SYSREG(ESR_EL2, ESR_EL1, NULL ); 135 MAPPED_EL2_SYSREG(FAR_EL2, FAR_EL1, NULL ); 136 MAPPED_EL2_SYSREG(MAIR_EL2, MAIR_EL1, NULL ); 137 MAPPED_EL2_SYSREG(TCR2_EL2, TCR2_EL1, NULL ); 138 MAPPED_EL2_SYSREG(PIR_EL2, PIR_EL1, NULL ); 139 MAPPED_EL2_SYSREG(PIRE0_EL2, PIRE0_EL1, NULL ); 140 MAPPED_EL2_SYSREG(POR_EL2, POR_EL1, NULL ); 141 MAPPED_EL2_SYSREG(AMAIR_EL2, AMAIR_EL1, NULL ); 142 MAPPED_EL2_SYSREG(ELR_EL2, ELR_EL1, NULL ); 143 MAPPED_EL2_SYSREG(SPSR_EL2, SPSR_EL1, NULL ); 144 MAPPED_EL2_SYSREG(ZCR_EL2, ZCR_EL1, NULL ); 145 MAPPED_EL2_SYSREG(CONTEXTIDR_EL2, CONTEXTIDR_EL1, NULL ); 146 default: 147 return false; 148 } 149 } 150 151 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg) 152 { 153 u64 val = 0x8badf00d8badf00d; 154 u64 (*xlate)(u64) = NULL; 155 unsigned int el1r; 156 157 if (!vcpu_get_flag(vcpu, SYSREGS_ON_CPU)) 158 goto memory_read; 159 160 if (unlikely(get_el2_to_el1_mapping(reg, &el1r, &xlate))) { 161 if (!is_hyp_ctxt(vcpu)) 162 goto memory_read; 163 164 /* 165 * CNTHCTL_EL2 requires some special treatment to 166 * account for the bits that can be set via CNTKCTL_EL1. 167 */ 168 switch (reg) { 169 case CNTHCTL_EL2: 170 if (vcpu_el2_e2h_is_set(vcpu)) { 171 val = read_sysreg_el1(SYS_CNTKCTL); 172 val &= CNTKCTL_VALID_BITS; 173 val |= __vcpu_sys_reg(vcpu, reg) & ~CNTKCTL_VALID_BITS; 174 return val; 175 } 176 break; 177 } 178 179 /* 180 * If this register does not have an EL1 counterpart, 181 * then read the stored EL2 version. 182 */ 183 if (reg == el1r) 184 goto memory_read; 185 186 /* 187 * If we have a non-VHE guest and that the sysreg 188 * requires translation to be used at EL1, use the 189 * in-memory copy instead. 190 */ 191 if (!vcpu_el2_e2h_is_set(vcpu) && xlate) 192 goto memory_read; 193 194 /* Get the current version of the EL1 counterpart. */ 195 WARN_ON(!__vcpu_read_sys_reg_from_cpu(el1r, &val)); 196 if (reg >= __SANITISED_REG_START__) 197 val = kvm_vcpu_apply_reg_masks(vcpu, reg, val); 198 199 return val; 200 } 201 202 /* EL1 register can't be on the CPU if the guest is in vEL2. */ 203 if (unlikely(is_hyp_ctxt(vcpu))) 204 goto memory_read; 205 206 if (__vcpu_read_sys_reg_from_cpu(reg, &val)) 207 return val; 208 209 memory_read: 210 return __vcpu_sys_reg(vcpu, reg); 211 } 212 213 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg) 214 { 215 u64 (*xlate)(u64) = NULL; 216 unsigned int el1r; 217 218 if (!vcpu_get_flag(vcpu, SYSREGS_ON_CPU)) 219 goto memory_write; 220 221 if (unlikely(get_el2_to_el1_mapping(reg, &el1r, &xlate))) { 222 if (!is_hyp_ctxt(vcpu)) 223 goto memory_write; 224 225 /* 226 * Always store a copy of the write to memory to avoid having 227 * to reverse-translate virtual EL2 system registers for a 228 * non-VHE guest hypervisor. 229 */ 230 __vcpu_sys_reg(vcpu, reg) = val; 231 232 switch (reg) { 233 case CNTHCTL_EL2: 234 /* 235 * If E2H=0, CNHTCTL_EL2 is a pure shadow register. 236 * Otherwise, some of the bits are backed by 237 * CNTKCTL_EL1, while the rest is kept in memory. 238 * Yes, this is fun stuff. 239 */ 240 if (vcpu_el2_e2h_is_set(vcpu)) 241 write_sysreg_el1(val, SYS_CNTKCTL); 242 return; 243 } 244 245 /* No EL1 counterpart? We're done here.? */ 246 if (reg == el1r) 247 return; 248 249 if (!vcpu_el2_e2h_is_set(vcpu) && xlate) 250 val = xlate(val); 251 252 /* Redirect this to the EL1 version of the register. */ 253 WARN_ON(!__vcpu_write_sys_reg_to_cpu(val, el1r)); 254 return; 255 } 256 257 /* EL1 register can't be on the CPU if the guest is in vEL2. */ 258 if (unlikely(is_hyp_ctxt(vcpu))) 259 goto memory_write; 260 261 if (__vcpu_write_sys_reg_to_cpu(val, reg)) 262 return; 263 264 memory_write: 265 __vcpu_sys_reg(vcpu, reg) = val; 266 } 267 268 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */ 269 #define CSSELR_MAX 14 270 271 /* 272 * Returns the minimum line size for the selected cache, expressed as 273 * Log2(bytes). 274 */ 275 static u8 get_min_cache_line_size(bool icache) 276 { 277 u64 ctr = read_sanitised_ftr_reg(SYS_CTR_EL0); 278 u8 field; 279 280 if (icache) 281 field = SYS_FIELD_GET(CTR_EL0, IminLine, ctr); 282 else 283 field = SYS_FIELD_GET(CTR_EL0, DminLine, ctr); 284 285 /* 286 * Cache line size is represented as Log2(words) in CTR_EL0. 287 * Log2(bytes) can be derived with the following: 288 * 289 * Log2(words) + 2 = Log2(bytes / 4) + 2 290 * = Log2(bytes) - 2 + 2 291 * = Log2(bytes) 292 */ 293 return field + 2; 294 } 295 296 /* Which cache CCSIDR represents depends on CSSELR value. */ 297 static u32 get_ccsidr(struct kvm_vcpu *vcpu, u32 csselr) 298 { 299 u8 line_size; 300 301 if (vcpu->arch.ccsidr) 302 return vcpu->arch.ccsidr[csselr]; 303 304 line_size = get_min_cache_line_size(csselr & CSSELR_EL1_InD); 305 306 /* 307 * Fabricate a CCSIDR value as the overriding value does not exist. 308 * The real CCSIDR value will not be used as it can vary by the 309 * physical CPU which the vcpu currently resides in. 310 * 311 * The line size is determined with get_min_cache_line_size(), which 312 * should be valid for all CPUs even if they have different cache 313 * configuration. 314 * 315 * The associativity bits are cleared, meaning the geometry of all data 316 * and unified caches (which are guaranteed to be PIPT and thus 317 * non-aliasing) are 1 set and 1 way. 318 * Guests should not be doing cache operations by set/way at all, and 319 * for this reason, we trap them and attempt to infer the intent, so 320 * that we can flush the entire guest's address space at the appropriate 321 * time. The exposed geometry minimizes the number of the traps. 322 * [If guests should attempt to infer aliasing properties from the 323 * geometry (which is not permitted by the architecture), they would 324 * only do so for virtually indexed caches.] 325 * 326 * We don't check if the cache level exists as it is allowed to return 327 * an UNKNOWN value if not. 328 */ 329 return SYS_FIELD_PREP(CCSIDR_EL1, LineSize, line_size - 4); 330 } 331 332 static int set_ccsidr(struct kvm_vcpu *vcpu, u32 csselr, u32 val) 333 { 334 u8 line_size = FIELD_GET(CCSIDR_EL1_LineSize, val) + 4; 335 u32 *ccsidr = vcpu->arch.ccsidr; 336 u32 i; 337 338 if ((val & CCSIDR_EL1_RES0) || 339 line_size < get_min_cache_line_size(csselr & CSSELR_EL1_InD)) 340 return -EINVAL; 341 342 if (!ccsidr) { 343 if (val == get_ccsidr(vcpu, csselr)) 344 return 0; 345 346 ccsidr = kmalloc_array(CSSELR_MAX, sizeof(u32), GFP_KERNEL_ACCOUNT); 347 if (!ccsidr) 348 return -ENOMEM; 349 350 for (i = 0; i < CSSELR_MAX; i++) 351 ccsidr[i] = get_ccsidr(vcpu, i); 352 353 vcpu->arch.ccsidr = ccsidr; 354 } 355 356 ccsidr[csselr] = val; 357 358 return 0; 359 } 360 361 static bool access_rw(struct kvm_vcpu *vcpu, 362 struct sys_reg_params *p, 363 const struct sys_reg_desc *r) 364 { 365 if (p->is_write) 366 vcpu_write_sys_reg(vcpu, p->regval, r->reg); 367 else 368 p->regval = vcpu_read_sys_reg(vcpu, r->reg); 369 370 return true; 371 } 372 373 /* 374 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized). 375 */ 376 static bool access_dcsw(struct kvm_vcpu *vcpu, 377 struct sys_reg_params *p, 378 const struct sys_reg_desc *r) 379 { 380 if (!p->is_write) 381 return read_from_write_only(vcpu, p, r); 382 383 /* 384 * Only track S/W ops if we don't have FWB. It still indicates 385 * that the guest is a bit broken (S/W operations should only 386 * be done by firmware, knowing that there is only a single 387 * CPU left in the system, and certainly not from non-secure 388 * software). 389 */ 390 if (!cpus_have_final_cap(ARM64_HAS_STAGE2_FWB)) 391 kvm_set_way_flush(vcpu); 392 393 return true; 394 } 395 396 static bool access_dcgsw(struct kvm_vcpu *vcpu, 397 struct sys_reg_params *p, 398 const struct sys_reg_desc *r) 399 { 400 if (!kvm_has_mte(vcpu->kvm)) 401 return undef_access(vcpu, p, r); 402 403 /* Treat MTE S/W ops as we treat the classic ones: with contempt */ 404 return access_dcsw(vcpu, p, r); 405 } 406 407 static void get_access_mask(const struct sys_reg_desc *r, u64 *mask, u64 *shift) 408 { 409 switch (r->aarch32_map) { 410 case AA32_LO: 411 *mask = GENMASK_ULL(31, 0); 412 *shift = 0; 413 break; 414 case AA32_HI: 415 *mask = GENMASK_ULL(63, 32); 416 *shift = 32; 417 break; 418 default: 419 *mask = GENMASK_ULL(63, 0); 420 *shift = 0; 421 break; 422 } 423 } 424 425 /* 426 * Generic accessor for VM registers. Only called as long as HCR_TVM 427 * is set. If the guest enables the MMU, we stop trapping the VM 428 * sys_regs and leave it in complete control of the caches. 429 */ 430 static bool access_vm_reg(struct kvm_vcpu *vcpu, 431 struct sys_reg_params *p, 432 const struct sys_reg_desc *r) 433 { 434 bool was_enabled = vcpu_has_cache_enabled(vcpu); 435 u64 val, mask, shift; 436 437 BUG_ON(!p->is_write); 438 439 get_access_mask(r, &mask, &shift); 440 441 if (~mask) { 442 val = vcpu_read_sys_reg(vcpu, r->reg); 443 val &= ~mask; 444 } else { 445 val = 0; 446 } 447 448 val |= (p->regval & (mask >> shift)) << shift; 449 vcpu_write_sys_reg(vcpu, val, r->reg); 450 451 kvm_toggle_cache(vcpu, was_enabled); 452 return true; 453 } 454 455 static bool access_actlr(struct kvm_vcpu *vcpu, 456 struct sys_reg_params *p, 457 const struct sys_reg_desc *r) 458 { 459 u64 mask, shift; 460 461 if (p->is_write) 462 return ignore_write(vcpu, p); 463 464 get_access_mask(r, &mask, &shift); 465 p->regval = (vcpu_read_sys_reg(vcpu, r->reg) & mask) >> shift; 466 467 return true; 468 } 469 470 /* 471 * Trap handler for the GICv3 SGI generation system register. 472 * Forward the request to the VGIC emulation. 473 * The cp15_64 code makes sure this automatically works 474 * for both AArch64 and AArch32 accesses. 475 */ 476 static bool access_gic_sgi(struct kvm_vcpu *vcpu, 477 struct sys_reg_params *p, 478 const struct sys_reg_desc *r) 479 { 480 bool g1; 481 482 if (!kvm_has_gicv3(vcpu->kvm)) 483 return undef_access(vcpu, p, r); 484 485 if (!p->is_write) 486 return read_from_write_only(vcpu, p, r); 487 488 /* 489 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates 490 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group, 491 * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively 492 * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure 493 * group. 494 */ 495 if (p->Op0 == 0) { /* AArch32 */ 496 switch (p->Op1) { 497 default: /* Keep GCC quiet */ 498 case 0: /* ICC_SGI1R */ 499 g1 = true; 500 break; 501 case 1: /* ICC_ASGI1R */ 502 case 2: /* ICC_SGI0R */ 503 g1 = false; 504 break; 505 } 506 } else { /* AArch64 */ 507 switch (p->Op2) { 508 default: /* Keep GCC quiet */ 509 case 5: /* ICC_SGI1R_EL1 */ 510 g1 = true; 511 break; 512 case 6: /* ICC_ASGI1R_EL1 */ 513 case 7: /* ICC_SGI0R_EL1 */ 514 g1 = false; 515 break; 516 } 517 } 518 519 vgic_v3_dispatch_sgi(vcpu, p->regval, g1); 520 521 return true; 522 } 523 524 static bool access_gic_sre(struct kvm_vcpu *vcpu, 525 struct sys_reg_params *p, 526 const struct sys_reg_desc *r) 527 { 528 if (!kvm_has_gicv3(vcpu->kvm)) 529 return undef_access(vcpu, p, r); 530 531 if (p->is_write) 532 return ignore_write(vcpu, p); 533 534 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre; 535 return true; 536 } 537 538 static bool trap_raz_wi(struct kvm_vcpu *vcpu, 539 struct sys_reg_params *p, 540 const struct sys_reg_desc *r) 541 { 542 if (p->is_write) 543 return ignore_write(vcpu, p); 544 else 545 return read_zero(vcpu, p); 546 } 547 548 /* 549 * ARMv8.1 mandates at least a trivial LORegion implementation, where all the 550 * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0 551 * system, these registers should UNDEF. LORID_EL1 being a RO register, we 552 * treat it separately. 553 */ 554 static bool trap_loregion(struct kvm_vcpu *vcpu, 555 struct sys_reg_params *p, 556 const struct sys_reg_desc *r) 557 { 558 u32 sr = reg_to_encoding(r); 559 560 if (!kvm_has_feat(vcpu->kvm, ID_AA64MMFR1_EL1, LO, IMP)) 561 return undef_access(vcpu, p, r); 562 563 if (p->is_write && sr == SYS_LORID_EL1) 564 return write_to_read_only(vcpu, p, r); 565 566 return trap_raz_wi(vcpu, p, r); 567 } 568 569 static bool trap_oslar_el1(struct kvm_vcpu *vcpu, 570 struct sys_reg_params *p, 571 const struct sys_reg_desc *r) 572 { 573 u64 oslsr; 574 575 if (!p->is_write) 576 return read_from_write_only(vcpu, p, r); 577 578 /* Forward the OSLK bit to OSLSR */ 579 oslsr = __vcpu_sys_reg(vcpu, OSLSR_EL1) & ~OSLSR_EL1_OSLK; 580 if (p->regval & OSLAR_EL1_OSLK) 581 oslsr |= OSLSR_EL1_OSLK; 582 583 __vcpu_sys_reg(vcpu, OSLSR_EL1) = oslsr; 584 return true; 585 } 586 587 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu, 588 struct sys_reg_params *p, 589 const struct sys_reg_desc *r) 590 { 591 if (p->is_write) 592 return write_to_read_only(vcpu, p, r); 593 594 p->regval = __vcpu_sys_reg(vcpu, r->reg); 595 return true; 596 } 597 598 static int set_oslsr_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 599 u64 val) 600 { 601 /* 602 * The only modifiable bit is the OSLK bit. Refuse the write if 603 * userspace attempts to change any other bit in the register. 604 */ 605 if ((val ^ rd->val) & ~OSLSR_EL1_OSLK) 606 return -EINVAL; 607 608 __vcpu_sys_reg(vcpu, rd->reg) = val; 609 return 0; 610 } 611 612 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu, 613 struct sys_reg_params *p, 614 const struct sys_reg_desc *r) 615 { 616 if (p->is_write) { 617 return ignore_write(vcpu, p); 618 } else { 619 p->regval = read_sysreg(dbgauthstatus_el1); 620 return true; 621 } 622 } 623 624 /* 625 * We want to avoid world-switching all the DBG registers all the 626 * time: 627 * 628 * - If we've touched any debug register, it is likely that we're 629 * going to touch more of them. It then makes sense to disable the 630 * traps and start doing the save/restore dance 631 * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is 632 * then mandatory to save/restore the registers, as the guest 633 * depends on them. 634 * 635 * For this, we use a DIRTY bit, indicating the guest has modified the 636 * debug registers, used as follow: 637 * 638 * On guest entry: 639 * - If the dirty bit is set (because we're coming back from trapping), 640 * disable the traps, save host registers, restore guest registers. 641 * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), 642 * set the dirty bit, disable the traps, save host registers, 643 * restore guest registers. 644 * - Otherwise, enable the traps 645 * 646 * On guest exit: 647 * - If the dirty bit is set, save guest registers, restore host 648 * registers and clear the dirty bit. This ensure that the host can 649 * now use the debug registers. 650 */ 651 static bool trap_debug_regs(struct kvm_vcpu *vcpu, 652 struct sys_reg_params *p, 653 const struct sys_reg_desc *r) 654 { 655 access_rw(vcpu, p, r); 656 if (p->is_write) 657 vcpu_set_flag(vcpu, DEBUG_DIRTY); 658 659 trace_trap_reg(__func__, r->reg, p->is_write, p->regval); 660 661 return true; 662 } 663 664 /* 665 * reg_to_dbg/dbg_to_reg 666 * 667 * A 32 bit write to a debug register leave top bits alone 668 * A 32 bit read from a debug register only returns the bottom bits 669 * 670 * All writes will set the DEBUG_DIRTY flag to ensure the hyp code 671 * switches between host and guest values in future. 672 */ 673 static void reg_to_dbg(struct kvm_vcpu *vcpu, 674 struct sys_reg_params *p, 675 const struct sys_reg_desc *rd, 676 u64 *dbg_reg) 677 { 678 u64 mask, shift, val; 679 680 get_access_mask(rd, &mask, &shift); 681 682 val = *dbg_reg; 683 val &= ~mask; 684 val |= (p->regval & (mask >> shift)) << shift; 685 *dbg_reg = val; 686 687 vcpu_set_flag(vcpu, DEBUG_DIRTY); 688 } 689 690 static void dbg_to_reg(struct kvm_vcpu *vcpu, 691 struct sys_reg_params *p, 692 const struct sys_reg_desc *rd, 693 u64 *dbg_reg) 694 { 695 u64 mask, shift; 696 697 get_access_mask(rd, &mask, &shift); 698 p->regval = (*dbg_reg & mask) >> shift; 699 } 700 701 static bool trap_bvr(struct kvm_vcpu *vcpu, 702 struct sys_reg_params *p, 703 const struct sys_reg_desc *rd) 704 { 705 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm]; 706 707 if (p->is_write) 708 reg_to_dbg(vcpu, p, rd, dbg_reg); 709 else 710 dbg_to_reg(vcpu, p, rd, dbg_reg); 711 712 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); 713 714 return true; 715 } 716 717 static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 718 u64 val) 719 { 720 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = val; 721 return 0; 722 } 723 724 static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 725 u64 *val) 726 { 727 *val = vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm]; 728 return 0; 729 } 730 731 static u64 reset_bvr(struct kvm_vcpu *vcpu, 732 const struct sys_reg_desc *rd) 733 { 734 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = rd->val; 735 return rd->val; 736 } 737 738 static bool trap_bcr(struct kvm_vcpu *vcpu, 739 struct sys_reg_params *p, 740 const struct sys_reg_desc *rd) 741 { 742 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm]; 743 744 if (p->is_write) 745 reg_to_dbg(vcpu, p, rd, dbg_reg); 746 else 747 dbg_to_reg(vcpu, p, rd, dbg_reg); 748 749 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); 750 751 return true; 752 } 753 754 static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 755 u64 val) 756 { 757 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = val; 758 return 0; 759 } 760 761 static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 762 u64 *val) 763 { 764 *val = vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm]; 765 return 0; 766 } 767 768 static u64 reset_bcr(struct kvm_vcpu *vcpu, 769 const struct sys_reg_desc *rd) 770 { 771 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = rd->val; 772 return rd->val; 773 } 774 775 static bool trap_wvr(struct kvm_vcpu *vcpu, 776 struct sys_reg_params *p, 777 const struct sys_reg_desc *rd) 778 { 779 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]; 780 781 if (p->is_write) 782 reg_to_dbg(vcpu, p, rd, dbg_reg); 783 else 784 dbg_to_reg(vcpu, p, rd, dbg_reg); 785 786 trace_trap_reg(__func__, rd->CRm, p->is_write, 787 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]); 788 789 return true; 790 } 791 792 static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 793 u64 val) 794 { 795 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = val; 796 return 0; 797 } 798 799 static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 800 u64 *val) 801 { 802 *val = vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]; 803 return 0; 804 } 805 806 static u64 reset_wvr(struct kvm_vcpu *vcpu, 807 const struct sys_reg_desc *rd) 808 { 809 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = rd->val; 810 return rd->val; 811 } 812 813 static bool trap_wcr(struct kvm_vcpu *vcpu, 814 struct sys_reg_params *p, 815 const struct sys_reg_desc *rd) 816 { 817 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm]; 818 819 if (p->is_write) 820 reg_to_dbg(vcpu, p, rd, dbg_reg); 821 else 822 dbg_to_reg(vcpu, p, rd, dbg_reg); 823 824 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); 825 826 return true; 827 } 828 829 static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 830 u64 val) 831 { 832 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = val; 833 return 0; 834 } 835 836 static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 837 u64 *val) 838 { 839 *val = vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm]; 840 return 0; 841 } 842 843 static u64 reset_wcr(struct kvm_vcpu *vcpu, 844 const struct sys_reg_desc *rd) 845 { 846 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = rd->val; 847 return rd->val; 848 } 849 850 static u64 reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 851 { 852 u64 amair = read_sysreg(amair_el1); 853 vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1); 854 return amair; 855 } 856 857 static u64 reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 858 { 859 u64 actlr = read_sysreg(actlr_el1); 860 vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1); 861 return actlr; 862 } 863 864 static u64 reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 865 { 866 u64 mpidr; 867 868 /* 869 * Map the vcpu_id into the first three affinity level fields of 870 * the MPIDR. We limit the number of VCPUs in level 0 due to a 871 * limitation to 16 CPUs in that level in the ICC_SGIxR registers 872 * of the GICv3 to be able to address each CPU directly when 873 * sending IPIs. 874 */ 875 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0); 876 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1); 877 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2); 878 mpidr |= (1ULL << 31); 879 vcpu_write_sys_reg(vcpu, mpidr, MPIDR_EL1); 880 881 return mpidr; 882 } 883 884 static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu, 885 const struct sys_reg_desc *r) 886 { 887 if (kvm_vcpu_has_pmu(vcpu)) 888 return 0; 889 890 return REG_HIDDEN; 891 } 892 893 static u64 reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 894 { 895 u64 mask = BIT(ARMV8_PMU_CYCLE_IDX); 896 u8 n = vcpu->kvm->arch.pmcr_n; 897 898 if (n) 899 mask |= GENMASK(n - 1, 0); 900 901 reset_unknown(vcpu, r); 902 __vcpu_sys_reg(vcpu, r->reg) &= mask; 903 904 return __vcpu_sys_reg(vcpu, r->reg); 905 } 906 907 static u64 reset_pmevcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 908 { 909 reset_unknown(vcpu, r); 910 __vcpu_sys_reg(vcpu, r->reg) &= GENMASK(31, 0); 911 912 return __vcpu_sys_reg(vcpu, r->reg); 913 } 914 915 static u64 reset_pmevtyper(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 916 { 917 /* This thing will UNDEF, who cares about the reset value? */ 918 if (!kvm_vcpu_has_pmu(vcpu)) 919 return 0; 920 921 reset_unknown(vcpu, r); 922 __vcpu_sys_reg(vcpu, r->reg) &= kvm_pmu_evtyper_mask(vcpu->kvm); 923 924 return __vcpu_sys_reg(vcpu, r->reg); 925 } 926 927 static u64 reset_pmselr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 928 { 929 reset_unknown(vcpu, r); 930 __vcpu_sys_reg(vcpu, r->reg) &= PMSELR_EL0_SEL_MASK; 931 932 return __vcpu_sys_reg(vcpu, r->reg); 933 } 934 935 static u64 reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 936 { 937 u64 pmcr = 0; 938 939 if (!kvm_supports_32bit_el0()) 940 pmcr |= ARMV8_PMU_PMCR_LC; 941 942 /* 943 * The value of PMCR.N field is included when the 944 * vCPU register is read via kvm_vcpu_read_pmcr(). 945 */ 946 __vcpu_sys_reg(vcpu, r->reg) = pmcr; 947 948 return __vcpu_sys_reg(vcpu, r->reg); 949 } 950 951 static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags) 952 { 953 u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0); 954 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu); 955 956 if (!enabled) 957 kvm_inject_undefined(vcpu); 958 959 return !enabled; 960 } 961 962 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu) 963 { 964 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN); 965 } 966 967 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu) 968 { 969 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN); 970 } 971 972 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu) 973 { 974 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN); 975 } 976 977 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu) 978 { 979 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN); 980 } 981 982 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 983 const struct sys_reg_desc *r) 984 { 985 u64 val; 986 987 if (pmu_access_el0_disabled(vcpu)) 988 return false; 989 990 if (p->is_write) { 991 /* 992 * Only update writeable bits of PMCR (continuing into 993 * kvm_pmu_handle_pmcr() as well) 994 */ 995 val = kvm_vcpu_read_pmcr(vcpu); 996 val &= ~ARMV8_PMU_PMCR_MASK; 997 val |= p->regval & ARMV8_PMU_PMCR_MASK; 998 if (!kvm_supports_32bit_el0()) 999 val |= ARMV8_PMU_PMCR_LC; 1000 kvm_pmu_handle_pmcr(vcpu, val); 1001 } else { 1002 /* PMCR.P & PMCR.C are RAZ */ 1003 val = kvm_vcpu_read_pmcr(vcpu) 1004 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C); 1005 p->regval = val; 1006 } 1007 1008 return true; 1009 } 1010 1011 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1012 const struct sys_reg_desc *r) 1013 { 1014 if (pmu_access_event_counter_el0_disabled(vcpu)) 1015 return false; 1016 1017 if (p->is_write) 1018 __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval; 1019 else 1020 /* return PMSELR.SEL field */ 1021 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0) 1022 & PMSELR_EL0_SEL_MASK; 1023 1024 return true; 1025 } 1026 1027 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1028 const struct sys_reg_desc *r) 1029 { 1030 u64 pmceid, mask, shift; 1031 1032 BUG_ON(p->is_write); 1033 1034 if (pmu_access_el0_disabled(vcpu)) 1035 return false; 1036 1037 get_access_mask(r, &mask, &shift); 1038 1039 pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1)); 1040 pmceid &= mask; 1041 pmceid >>= shift; 1042 1043 p->regval = pmceid; 1044 1045 return true; 1046 } 1047 1048 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx) 1049 { 1050 u64 pmcr, val; 1051 1052 pmcr = kvm_vcpu_read_pmcr(vcpu); 1053 val = FIELD_GET(ARMV8_PMU_PMCR_N, pmcr); 1054 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) { 1055 kvm_inject_undefined(vcpu); 1056 return false; 1057 } 1058 1059 return true; 1060 } 1061 1062 static int get_pmu_evcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 1063 u64 *val) 1064 { 1065 u64 idx; 1066 1067 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 0) 1068 /* PMCCNTR_EL0 */ 1069 idx = ARMV8_PMU_CYCLE_IDX; 1070 else 1071 /* PMEVCNTRn_EL0 */ 1072 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 1073 1074 *val = kvm_pmu_get_counter_value(vcpu, idx); 1075 return 0; 1076 } 1077 1078 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu, 1079 struct sys_reg_params *p, 1080 const struct sys_reg_desc *r) 1081 { 1082 u64 idx = ~0UL; 1083 1084 if (r->CRn == 9 && r->CRm == 13) { 1085 if (r->Op2 == 2) { 1086 /* PMXEVCNTR_EL0 */ 1087 if (pmu_access_event_counter_el0_disabled(vcpu)) 1088 return false; 1089 1090 idx = SYS_FIELD_GET(PMSELR_EL0, SEL, 1091 __vcpu_sys_reg(vcpu, PMSELR_EL0)); 1092 } else if (r->Op2 == 0) { 1093 /* PMCCNTR_EL0 */ 1094 if (pmu_access_cycle_counter_el0_disabled(vcpu)) 1095 return false; 1096 1097 idx = ARMV8_PMU_CYCLE_IDX; 1098 } 1099 } else if (r->CRn == 0 && r->CRm == 9) { 1100 /* PMCCNTR */ 1101 if (pmu_access_event_counter_el0_disabled(vcpu)) 1102 return false; 1103 1104 idx = ARMV8_PMU_CYCLE_IDX; 1105 } else if (r->CRn == 14 && (r->CRm & 12) == 8) { 1106 /* PMEVCNTRn_EL0 */ 1107 if (pmu_access_event_counter_el0_disabled(vcpu)) 1108 return false; 1109 1110 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 1111 } 1112 1113 /* Catch any decoding mistake */ 1114 WARN_ON(idx == ~0UL); 1115 1116 if (!pmu_counter_idx_valid(vcpu, idx)) 1117 return false; 1118 1119 if (p->is_write) { 1120 if (pmu_access_el0_disabled(vcpu)) 1121 return false; 1122 1123 kvm_pmu_set_counter_value(vcpu, idx, p->regval); 1124 } else { 1125 p->regval = kvm_pmu_get_counter_value(vcpu, idx); 1126 } 1127 1128 return true; 1129 } 1130 1131 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1132 const struct sys_reg_desc *r) 1133 { 1134 u64 idx, reg; 1135 1136 if (pmu_access_el0_disabled(vcpu)) 1137 return false; 1138 1139 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) { 1140 /* PMXEVTYPER_EL0 */ 1141 idx = SYS_FIELD_GET(PMSELR_EL0, SEL, __vcpu_sys_reg(vcpu, PMSELR_EL0)); 1142 reg = PMEVTYPER0_EL0 + idx; 1143 } else if (r->CRn == 14 && (r->CRm & 12) == 12) { 1144 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 1145 if (idx == ARMV8_PMU_CYCLE_IDX) 1146 reg = PMCCFILTR_EL0; 1147 else 1148 /* PMEVTYPERn_EL0 */ 1149 reg = PMEVTYPER0_EL0 + idx; 1150 } else { 1151 BUG(); 1152 } 1153 1154 if (!pmu_counter_idx_valid(vcpu, idx)) 1155 return false; 1156 1157 if (p->is_write) { 1158 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx); 1159 kvm_vcpu_pmu_restore_guest(vcpu); 1160 } else { 1161 p->regval = __vcpu_sys_reg(vcpu, reg); 1162 } 1163 1164 return true; 1165 } 1166 1167 static int set_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 val) 1168 { 1169 bool set; 1170 1171 val &= kvm_pmu_accessible_counter_mask(vcpu); 1172 1173 switch (r->reg) { 1174 case PMOVSSET_EL0: 1175 /* CRm[1] being set indicates a SET register, and CLR otherwise */ 1176 set = r->CRm & 2; 1177 break; 1178 default: 1179 /* Op2[0] being set indicates a SET register, and CLR otherwise */ 1180 set = r->Op2 & 1; 1181 break; 1182 } 1183 1184 if (set) 1185 __vcpu_sys_reg(vcpu, r->reg) |= val; 1186 else 1187 __vcpu_sys_reg(vcpu, r->reg) &= ~val; 1188 1189 return 0; 1190 } 1191 1192 static int get_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 *val) 1193 { 1194 u64 mask = kvm_pmu_accessible_counter_mask(vcpu); 1195 1196 *val = __vcpu_sys_reg(vcpu, r->reg) & mask; 1197 return 0; 1198 } 1199 1200 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1201 const struct sys_reg_desc *r) 1202 { 1203 u64 val, mask; 1204 1205 if (pmu_access_el0_disabled(vcpu)) 1206 return false; 1207 1208 mask = kvm_pmu_accessible_counter_mask(vcpu); 1209 if (p->is_write) { 1210 val = p->regval & mask; 1211 if (r->Op2 & 0x1) 1212 /* accessing PMCNTENSET_EL0 */ 1213 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val; 1214 else 1215 /* accessing PMCNTENCLR_EL0 */ 1216 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val; 1217 1218 kvm_pmu_reprogram_counter_mask(vcpu, val); 1219 } else { 1220 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0); 1221 } 1222 1223 return true; 1224 } 1225 1226 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1227 const struct sys_reg_desc *r) 1228 { 1229 u64 mask = kvm_pmu_accessible_counter_mask(vcpu); 1230 1231 if (check_pmu_access_disabled(vcpu, 0)) 1232 return false; 1233 1234 if (p->is_write) { 1235 u64 val = p->regval & mask; 1236 1237 if (r->Op2 & 0x1) 1238 /* accessing PMINTENSET_EL1 */ 1239 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val; 1240 else 1241 /* accessing PMINTENCLR_EL1 */ 1242 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val; 1243 } else { 1244 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1); 1245 } 1246 1247 return true; 1248 } 1249 1250 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1251 const struct sys_reg_desc *r) 1252 { 1253 u64 mask = kvm_pmu_accessible_counter_mask(vcpu); 1254 1255 if (pmu_access_el0_disabled(vcpu)) 1256 return false; 1257 1258 if (p->is_write) { 1259 if (r->CRm & 0x2) 1260 /* accessing PMOVSSET_EL0 */ 1261 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask); 1262 else 1263 /* accessing PMOVSCLR_EL0 */ 1264 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask); 1265 } else { 1266 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0); 1267 } 1268 1269 return true; 1270 } 1271 1272 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1273 const struct sys_reg_desc *r) 1274 { 1275 u64 mask; 1276 1277 if (!p->is_write) 1278 return read_from_write_only(vcpu, p, r); 1279 1280 if (pmu_write_swinc_el0_disabled(vcpu)) 1281 return false; 1282 1283 mask = kvm_pmu_accessible_counter_mask(vcpu); 1284 kvm_pmu_software_increment(vcpu, p->regval & mask); 1285 return true; 1286 } 1287 1288 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1289 const struct sys_reg_desc *r) 1290 { 1291 if (p->is_write) { 1292 if (!vcpu_mode_priv(vcpu)) 1293 return undef_access(vcpu, p, r); 1294 1295 __vcpu_sys_reg(vcpu, PMUSERENR_EL0) = 1296 p->regval & ARMV8_PMU_USERENR_MASK; 1297 } else { 1298 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0) 1299 & ARMV8_PMU_USERENR_MASK; 1300 } 1301 1302 return true; 1303 } 1304 1305 static int get_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 1306 u64 *val) 1307 { 1308 *val = kvm_vcpu_read_pmcr(vcpu); 1309 return 0; 1310 } 1311 1312 static int set_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 1313 u64 val) 1314 { 1315 u8 new_n = FIELD_GET(ARMV8_PMU_PMCR_N, val); 1316 struct kvm *kvm = vcpu->kvm; 1317 1318 mutex_lock(&kvm->arch.config_lock); 1319 1320 /* 1321 * The vCPU can't have more counters than the PMU hardware 1322 * implements. Ignore this error to maintain compatibility 1323 * with the existing KVM behavior. 1324 */ 1325 if (!kvm_vm_has_ran_once(kvm) && 1326 new_n <= kvm_arm_pmu_get_max_counters(kvm)) 1327 kvm->arch.pmcr_n = new_n; 1328 1329 mutex_unlock(&kvm->arch.config_lock); 1330 1331 /* 1332 * Ignore writes to RES0 bits, read only bits that are cleared on 1333 * vCPU reset, and writable bits that KVM doesn't support yet. 1334 * (i.e. only PMCR.N and bits [7:0] are mutable from userspace) 1335 * The LP bit is RES0 when FEAT_PMUv3p5 is not supported on the vCPU. 1336 * But, we leave the bit as it is here, as the vCPU's PMUver might 1337 * be changed later (NOTE: the bit will be cleared on first vCPU run 1338 * if necessary). 1339 */ 1340 val &= ARMV8_PMU_PMCR_MASK; 1341 1342 /* The LC bit is RES1 when AArch32 is not supported */ 1343 if (!kvm_supports_32bit_el0()) 1344 val |= ARMV8_PMU_PMCR_LC; 1345 1346 __vcpu_sys_reg(vcpu, r->reg) = val; 1347 return 0; 1348 } 1349 1350 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */ 1351 #define DBG_BCR_BVR_WCR_WVR_EL1(n) \ 1352 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \ 1353 trap_bvr, reset_bvr, 0, 0, get_bvr, set_bvr }, \ 1354 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \ 1355 trap_bcr, reset_bcr, 0, 0, get_bcr, set_bcr }, \ 1356 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \ 1357 trap_wvr, reset_wvr, 0, 0, get_wvr, set_wvr }, \ 1358 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \ 1359 trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr } 1360 1361 #define PMU_SYS_REG(name) \ 1362 SYS_DESC(SYS_##name), .reset = reset_pmu_reg, \ 1363 .visibility = pmu_visibility 1364 1365 /* Macro to expand the PMEVCNTRn_EL0 register */ 1366 #define PMU_PMEVCNTR_EL0(n) \ 1367 { PMU_SYS_REG(PMEVCNTRn_EL0(n)), \ 1368 .reset = reset_pmevcntr, .get_user = get_pmu_evcntr, \ 1369 .access = access_pmu_evcntr, .reg = (PMEVCNTR0_EL0 + n), } 1370 1371 /* Macro to expand the PMEVTYPERn_EL0 register */ 1372 #define PMU_PMEVTYPER_EL0(n) \ 1373 { PMU_SYS_REG(PMEVTYPERn_EL0(n)), \ 1374 .reset = reset_pmevtyper, \ 1375 .access = access_pmu_evtyper, .reg = (PMEVTYPER0_EL0 + n), } 1376 1377 /* Macro to expand the AMU counter and type registers*/ 1378 #define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), undef_access } 1379 #define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), undef_access } 1380 #define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), undef_access } 1381 #define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), undef_access } 1382 1383 static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu, 1384 const struct sys_reg_desc *rd) 1385 { 1386 return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN; 1387 } 1388 1389 /* 1390 * If we land here on a PtrAuth access, that is because we didn't 1391 * fixup the access on exit by allowing the PtrAuth sysregs. The only 1392 * way this happens is when the guest does not have PtrAuth support 1393 * enabled. 1394 */ 1395 #define __PTRAUTH_KEY(k) \ 1396 { SYS_DESC(SYS_## k), undef_access, reset_unknown, k, \ 1397 .visibility = ptrauth_visibility} 1398 1399 #define PTRAUTH_KEY(k) \ 1400 __PTRAUTH_KEY(k ## KEYLO_EL1), \ 1401 __PTRAUTH_KEY(k ## KEYHI_EL1) 1402 1403 static bool access_arch_timer(struct kvm_vcpu *vcpu, 1404 struct sys_reg_params *p, 1405 const struct sys_reg_desc *r) 1406 { 1407 enum kvm_arch_timers tmr; 1408 enum kvm_arch_timer_regs treg; 1409 u64 reg = reg_to_encoding(r); 1410 1411 switch (reg) { 1412 case SYS_CNTP_TVAL_EL0: 1413 case SYS_AARCH32_CNTP_TVAL: 1414 tmr = TIMER_PTIMER; 1415 treg = TIMER_REG_TVAL; 1416 break; 1417 case SYS_CNTP_CTL_EL0: 1418 case SYS_AARCH32_CNTP_CTL: 1419 tmr = TIMER_PTIMER; 1420 treg = TIMER_REG_CTL; 1421 break; 1422 case SYS_CNTP_CVAL_EL0: 1423 case SYS_AARCH32_CNTP_CVAL: 1424 tmr = TIMER_PTIMER; 1425 treg = TIMER_REG_CVAL; 1426 break; 1427 case SYS_CNTPCT_EL0: 1428 case SYS_CNTPCTSS_EL0: 1429 case SYS_AARCH32_CNTPCT: 1430 tmr = TIMER_PTIMER; 1431 treg = TIMER_REG_CNT; 1432 break; 1433 default: 1434 print_sys_reg_msg(p, "%s", "Unhandled trapped timer register"); 1435 return undef_access(vcpu, p, r); 1436 } 1437 1438 if (p->is_write) 1439 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval); 1440 else 1441 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg); 1442 1443 return true; 1444 } 1445 1446 static s64 kvm_arm64_ftr_safe_value(u32 id, const struct arm64_ftr_bits *ftrp, 1447 s64 new, s64 cur) 1448 { 1449 struct arm64_ftr_bits kvm_ftr = *ftrp; 1450 1451 /* Some features have different safe value type in KVM than host features */ 1452 switch (id) { 1453 case SYS_ID_AA64DFR0_EL1: 1454 switch (kvm_ftr.shift) { 1455 case ID_AA64DFR0_EL1_PMUVer_SHIFT: 1456 kvm_ftr.type = FTR_LOWER_SAFE; 1457 break; 1458 case ID_AA64DFR0_EL1_DebugVer_SHIFT: 1459 kvm_ftr.type = FTR_LOWER_SAFE; 1460 break; 1461 } 1462 break; 1463 case SYS_ID_DFR0_EL1: 1464 if (kvm_ftr.shift == ID_DFR0_EL1_PerfMon_SHIFT) 1465 kvm_ftr.type = FTR_LOWER_SAFE; 1466 break; 1467 } 1468 1469 return arm64_ftr_safe_value(&kvm_ftr, new, cur); 1470 } 1471 1472 /* 1473 * arm64_check_features() - Check if a feature register value constitutes 1474 * a subset of features indicated by the idreg's KVM sanitised limit. 1475 * 1476 * This function will check if each feature field of @val is the "safe" value 1477 * against idreg's KVM sanitised limit return from reset() callback. 1478 * If a field value in @val is the same as the one in limit, it is always 1479 * considered the safe value regardless For register fields that are not in 1480 * writable, only the value in limit is considered the safe value. 1481 * 1482 * Return: 0 if all the fields are safe. Otherwise, return negative errno. 1483 */ 1484 static int arm64_check_features(struct kvm_vcpu *vcpu, 1485 const struct sys_reg_desc *rd, 1486 u64 val) 1487 { 1488 const struct arm64_ftr_reg *ftr_reg; 1489 const struct arm64_ftr_bits *ftrp = NULL; 1490 u32 id = reg_to_encoding(rd); 1491 u64 writable_mask = rd->val; 1492 u64 limit = rd->reset(vcpu, rd); 1493 u64 mask = 0; 1494 1495 /* 1496 * Hidden and unallocated ID registers may not have a corresponding 1497 * struct arm64_ftr_reg. Of course, if the register is RAZ we know the 1498 * only safe value is 0. 1499 */ 1500 if (sysreg_visible_as_raz(vcpu, rd)) 1501 return val ? -E2BIG : 0; 1502 1503 ftr_reg = get_arm64_ftr_reg(id); 1504 if (!ftr_reg) 1505 return -EINVAL; 1506 1507 ftrp = ftr_reg->ftr_bits; 1508 1509 for (; ftrp && ftrp->width; ftrp++) { 1510 s64 f_val, f_lim, safe_val; 1511 u64 ftr_mask; 1512 1513 ftr_mask = arm64_ftr_mask(ftrp); 1514 if ((ftr_mask & writable_mask) != ftr_mask) 1515 continue; 1516 1517 f_val = arm64_ftr_value(ftrp, val); 1518 f_lim = arm64_ftr_value(ftrp, limit); 1519 mask |= ftr_mask; 1520 1521 if (f_val == f_lim) 1522 safe_val = f_val; 1523 else 1524 safe_val = kvm_arm64_ftr_safe_value(id, ftrp, f_val, f_lim); 1525 1526 if (safe_val != f_val) 1527 return -E2BIG; 1528 } 1529 1530 /* For fields that are not writable, values in limit are the safe values. */ 1531 if ((val & ~mask) != (limit & ~mask)) 1532 return -E2BIG; 1533 1534 return 0; 1535 } 1536 1537 static u8 pmuver_to_perfmon(u8 pmuver) 1538 { 1539 switch (pmuver) { 1540 case ID_AA64DFR0_EL1_PMUVer_IMP: 1541 return ID_DFR0_EL1_PerfMon_PMUv3; 1542 case ID_AA64DFR0_EL1_PMUVer_IMP_DEF: 1543 return ID_DFR0_EL1_PerfMon_IMPDEF; 1544 default: 1545 /* Anything ARMv8.1+ and NI have the same value. For now. */ 1546 return pmuver; 1547 } 1548 } 1549 1550 static u64 sanitise_id_aa64pfr0_el1(const struct kvm_vcpu *vcpu, u64 val); 1551 static u64 sanitise_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, u64 val); 1552 1553 /* Read a sanitised cpufeature ID register by sys_reg_desc */ 1554 static u64 __kvm_read_sanitised_id_reg(const struct kvm_vcpu *vcpu, 1555 const struct sys_reg_desc *r) 1556 { 1557 u32 id = reg_to_encoding(r); 1558 u64 val; 1559 1560 if (sysreg_visible_as_raz(vcpu, r)) 1561 return 0; 1562 1563 val = read_sanitised_ftr_reg(id); 1564 1565 switch (id) { 1566 case SYS_ID_AA64DFR0_EL1: 1567 val = sanitise_id_aa64dfr0_el1(vcpu, val); 1568 break; 1569 case SYS_ID_AA64PFR0_EL1: 1570 val = sanitise_id_aa64pfr0_el1(vcpu, val); 1571 break; 1572 case SYS_ID_AA64PFR1_EL1: 1573 if (!kvm_has_mte(vcpu->kvm)) 1574 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE); 1575 1576 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_SME); 1577 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_RNDR_trap); 1578 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_NMI); 1579 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE_frac); 1580 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_GCS); 1581 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_THE); 1582 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTEX); 1583 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_DF2); 1584 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_PFAR); 1585 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MPAM_frac); 1586 break; 1587 case SYS_ID_AA64PFR2_EL1: 1588 /* We only expose FPMR */ 1589 val &= ID_AA64PFR2_EL1_FPMR; 1590 break; 1591 case SYS_ID_AA64ISAR1_EL1: 1592 if (!vcpu_has_ptrauth(vcpu)) 1593 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) | 1594 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) | 1595 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) | 1596 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI)); 1597 break; 1598 case SYS_ID_AA64ISAR2_EL1: 1599 if (!vcpu_has_ptrauth(vcpu)) 1600 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) | 1601 ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3)); 1602 if (!cpus_have_final_cap(ARM64_HAS_WFXT)) 1603 val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT); 1604 break; 1605 case SYS_ID_AA64MMFR2_EL1: 1606 val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK; 1607 break; 1608 case SYS_ID_AA64MMFR3_EL1: 1609 val &= ID_AA64MMFR3_EL1_TCRX | ID_AA64MMFR3_EL1_S1POE | 1610 ID_AA64MMFR3_EL1_S1PIE; 1611 break; 1612 case SYS_ID_MMFR4_EL1: 1613 val &= ~ARM64_FEATURE_MASK(ID_MMFR4_EL1_CCIDX); 1614 break; 1615 } 1616 1617 return val; 1618 } 1619 1620 static u64 kvm_read_sanitised_id_reg(struct kvm_vcpu *vcpu, 1621 const struct sys_reg_desc *r) 1622 { 1623 return __kvm_read_sanitised_id_reg(vcpu, r); 1624 } 1625 1626 static u64 read_id_reg(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 1627 { 1628 return kvm_read_vm_id_reg(vcpu->kvm, reg_to_encoding(r)); 1629 } 1630 1631 static bool is_feature_id_reg(u32 encoding) 1632 { 1633 return (sys_reg_Op0(encoding) == 3 && 1634 (sys_reg_Op1(encoding) < 2 || sys_reg_Op1(encoding) == 3) && 1635 sys_reg_CRn(encoding) == 0 && 1636 sys_reg_CRm(encoding) <= 7); 1637 } 1638 1639 /* 1640 * Return true if the register's (Op0, Op1, CRn, CRm, Op2) is 1641 * (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8, which is the range of ID 1642 * registers KVM maintains on a per-VM basis. 1643 */ 1644 static inline bool is_vm_ftr_id_reg(u32 id) 1645 { 1646 if (id == SYS_CTR_EL0) 1647 return true; 1648 1649 return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 && 1650 sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 && 1651 sys_reg_CRm(id) < 8); 1652 } 1653 1654 static inline bool is_vcpu_ftr_id_reg(u32 id) 1655 { 1656 return is_feature_id_reg(id) && !is_vm_ftr_id_reg(id); 1657 } 1658 1659 static inline bool is_aa32_id_reg(u32 id) 1660 { 1661 return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 && 1662 sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 && 1663 sys_reg_CRm(id) <= 3); 1664 } 1665 1666 static unsigned int id_visibility(const struct kvm_vcpu *vcpu, 1667 const struct sys_reg_desc *r) 1668 { 1669 u32 id = reg_to_encoding(r); 1670 1671 switch (id) { 1672 case SYS_ID_AA64ZFR0_EL1: 1673 if (!vcpu_has_sve(vcpu)) 1674 return REG_RAZ; 1675 break; 1676 } 1677 1678 return 0; 1679 } 1680 1681 static unsigned int aa32_id_visibility(const struct kvm_vcpu *vcpu, 1682 const struct sys_reg_desc *r) 1683 { 1684 /* 1685 * AArch32 ID registers are UNKNOWN if AArch32 isn't implemented at any 1686 * EL. Promote to RAZ/WI in order to guarantee consistency between 1687 * systems. 1688 */ 1689 if (!kvm_supports_32bit_el0()) 1690 return REG_RAZ | REG_USER_WI; 1691 1692 return id_visibility(vcpu, r); 1693 } 1694 1695 static unsigned int raz_visibility(const struct kvm_vcpu *vcpu, 1696 const struct sys_reg_desc *r) 1697 { 1698 return REG_RAZ; 1699 } 1700 1701 /* cpufeature ID register access trap handlers */ 1702 1703 static bool access_id_reg(struct kvm_vcpu *vcpu, 1704 struct sys_reg_params *p, 1705 const struct sys_reg_desc *r) 1706 { 1707 if (p->is_write) 1708 return write_to_read_only(vcpu, p, r); 1709 1710 p->regval = read_id_reg(vcpu, r); 1711 1712 return true; 1713 } 1714 1715 /* Visibility overrides for SVE-specific control registers */ 1716 static unsigned int sve_visibility(const struct kvm_vcpu *vcpu, 1717 const struct sys_reg_desc *rd) 1718 { 1719 if (vcpu_has_sve(vcpu)) 1720 return 0; 1721 1722 return REG_HIDDEN; 1723 } 1724 1725 static unsigned int sme_visibility(const struct kvm_vcpu *vcpu, 1726 const struct sys_reg_desc *rd) 1727 { 1728 if (kvm_has_feat(vcpu->kvm, ID_AA64PFR1_EL1, SME, IMP)) 1729 return 0; 1730 1731 return REG_HIDDEN; 1732 } 1733 1734 static unsigned int fp8_visibility(const struct kvm_vcpu *vcpu, 1735 const struct sys_reg_desc *rd) 1736 { 1737 if (kvm_has_fpmr(vcpu->kvm)) 1738 return 0; 1739 1740 return REG_HIDDEN; 1741 } 1742 1743 static u64 sanitise_id_aa64pfr0_el1(const struct kvm_vcpu *vcpu, u64 val) 1744 { 1745 if (!vcpu_has_sve(vcpu)) 1746 val &= ~ID_AA64PFR0_EL1_SVE_MASK; 1747 1748 /* 1749 * The default is to expose CSV2 == 1 if the HW isn't affected. 1750 * Although this is a per-CPU feature, we make it global because 1751 * asymmetric systems are just a nuisance. 1752 * 1753 * Userspace can override this as long as it doesn't promise 1754 * the impossible. 1755 */ 1756 if (arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED) { 1757 val &= ~ID_AA64PFR0_EL1_CSV2_MASK; 1758 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV2, IMP); 1759 } 1760 if (arm64_get_meltdown_state() == SPECTRE_UNAFFECTED) { 1761 val &= ~ID_AA64PFR0_EL1_CSV3_MASK; 1762 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV3, IMP); 1763 } 1764 1765 if (kvm_vgic_global_state.type == VGIC_V3) { 1766 val &= ~ID_AA64PFR0_EL1_GIC_MASK; 1767 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, GIC, IMP); 1768 } 1769 1770 val &= ~ID_AA64PFR0_EL1_AMU_MASK; 1771 1772 /* 1773 * MPAM is disabled by default as KVM also needs a set of PARTID to 1774 * program the MPAMVPMx_EL2 PARTID remapping registers with. But some 1775 * older kernels let the guest see the ID bit. 1776 */ 1777 val &= ~ID_AA64PFR0_EL1_MPAM_MASK; 1778 1779 return val; 1780 } 1781 1782 #define ID_REG_LIMIT_FIELD_ENUM(val, reg, field, limit) \ 1783 ({ \ 1784 u64 __f_val = FIELD_GET(reg##_##field##_MASK, val); \ 1785 (val) &= ~reg##_##field##_MASK; \ 1786 (val) |= FIELD_PREP(reg##_##field##_MASK, \ 1787 min(__f_val, \ 1788 (u64)SYS_FIELD_VALUE(reg, field, limit))); \ 1789 (val); \ 1790 }) 1791 1792 static u64 sanitise_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, u64 val) 1793 { 1794 val = ID_REG_LIMIT_FIELD_ENUM(val, ID_AA64DFR0_EL1, DebugVer, V8P8); 1795 1796 /* 1797 * Only initialize the PMU version if the vCPU was configured with one. 1798 */ 1799 val &= ~ID_AA64DFR0_EL1_PMUVer_MASK; 1800 if (kvm_vcpu_has_pmu(vcpu)) 1801 val |= SYS_FIELD_PREP(ID_AA64DFR0_EL1, PMUVer, 1802 kvm_arm_pmu_get_pmuver_limit()); 1803 1804 /* Hide SPE from guests */ 1805 val &= ~ID_AA64DFR0_EL1_PMSVer_MASK; 1806 1807 return val; 1808 } 1809 1810 static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, 1811 const struct sys_reg_desc *rd, 1812 u64 val) 1813 { 1814 u8 debugver = SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, val); 1815 u8 pmuver = SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, val); 1816 1817 /* 1818 * Prior to commit 3d0dba5764b9 ("KVM: arm64: PMU: Move the 1819 * ID_AA64DFR0_EL1.PMUver limit to VM creation"), KVM erroneously 1820 * exposed an IMP_DEF PMU to userspace and the guest on systems w/ 1821 * non-architectural PMUs. Of course, PMUv3 is the only game in town for 1822 * PMU virtualization, so the IMP_DEF value was rather user-hostile. 1823 * 1824 * At minimum, we're on the hook to allow values that were given to 1825 * userspace by KVM. Cover our tracks here and replace the IMP_DEF value 1826 * with a more sensible NI. The value of an ID register changing under 1827 * the nose of the guest is unfortunate, but is certainly no more 1828 * surprising than an ill-guided PMU driver poking at impdef system 1829 * registers that end in an UNDEF... 1830 */ 1831 if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF) 1832 val &= ~ID_AA64DFR0_EL1_PMUVer_MASK; 1833 1834 /* 1835 * ID_AA64DFR0_EL1.DebugVer is one of those awkward fields with a 1836 * nonzero minimum safe value. 1837 */ 1838 if (debugver < ID_AA64DFR0_EL1_DebugVer_IMP) 1839 return -EINVAL; 1840 1841 return set_id_reg(vcpu, rd, val); 1842 } 1843 1844 static u64 read_sanitised_id_dfr0_el1(struct kvm_vcpu *vcpu, 1845 const struct sys_reg_desc *rd) 1846 { 1847 u8 perfmon = pmuver_to_perfmon(kvm_arm_pmu_get_pmuver_limit()); 1848 u64 val = read_sanitised_ftr_reg(SYS_ID_DFR0_EL1); 1849 1850 val &= ~ID_DFR0_EL1_PerfMon_MASK; 1851 if (kvm_vcpu_has_pmu(vcpu)) 1852 val |= SYS_FIELD_PREP(ID_DFR0_EL1, PerfMon, perfmon); 1853 1854 val = ID_REG_LIMIT_FIELD_ENUM(val, ID_DFR0_EL1, CopDbg, Debugv8p8); 1855 1856 return val; 1857 } 1858 1859 static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, 1860 const struct sys_reg_desc *rd, 1861 u64 val) 1862 { 1863 u8 perfmon = SYS_FIELD_GET(ID_DFR0_EL1, PerfMon, val); 1864 u8 copdbg = SYS_FIELD_GET(ID_DFR0_EL1, CopDbg, val); 1865 1866 if (perfmon == ID_DFR0_EL1_PerfMon_IMPDEF) { 1867 val &= ~ID_DFR0_EL1_PerfMon_MASK; 1868 perfmon = 0; 1869 } 1870 1871 /* 1872 * Allow DFR0_EL1.PerfMon to be set from userspace as long as 1873 * it doesn't promise more than what the HW gives us on the 1874 * AArch64 side (as everything is emulated with that), and 1875 * that this is a PMUv3. 1876 */ 1877 if (perfmon != 0 && perfmon < ID_DFR0_EL1_PerfMon_PMUv3) 1878 return -EINVAL; 1879 1880 if (copdbg < ID_DFR0_EL1_CopDbg_Armv8) 1881 return -EINVAL; 1882 1883 return set_id_reg(vcpu, rd, val); 1884 } 1885 1886 static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, 1887 const struct sys_reg_desc *rd, u64 user_val) 1888 { 1889 u64 hw_val = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1890 u64 mpam_mask = ID_AA64PFR0_EL1_MPAM_MASK; 1891 1892 /* 1893 * Commit 011e5f5bf529f ("arm64/cpufeature: Add remaining feature bits 1894 * in ID_AA64PFR0 register") exposed the MPAM field of AA64PFR0_EL1 to 1895 * guests, but didn't add trap handling. KVM doesn't support MPAM and 1896 * always returns an UNDEF for these registers. The guest must see 0 1897 * for this field. 1898 * 1899 * But KVM must also accept values from user-space that were provided 1900 * by KVM. On CPUs that support MPAM, permit user-space to write 1901 * the sanitizied value to ID_AA64PFR0_EL1.MPAM, but ignore this field. 1902 */ 1903 if ((hw_val & mpam_mask) == (user_val & mpam_mask)) 1904 user_val &= ~ID_AA64PFR0_EL1_MPAM_MASK; 1905 1906 return set_id_reg(vcpu, rd, user_val); 1907 } 1908 1909 static int set_id_aa64pfr1_el1(struct kvm_vcpu *vcpu, 1910 const struct sys_reg_desc *rd, u64 user_val) 1911 { 1912 u64 hw_val = read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1); 1913 u64 mpam_mask = ID_AA64PFR1_EL1_MPAM_frac_MASK; 1914 1915 /* See set_id_aa64pfr0_el1 for comment about MPAM */ 1916 if ((hw_val & mpam_mask) == (user_val & mpam_mask)) 1917 user_val &= ~ID_AA64PFR1_EL1_MPAM_frac_MASK; 1918 1919 return set_id_reg(vcpu, rd, user_val); 1920 } 1921 1922 static int set_ctr_el0(struct kvm_vcpu *vcpu, 1923 const struct sys_reg_desc *rd, u64 user_val) 1924 { 1925 u8 user_L1Ip = SYS_FIELD_GET(CTR_EL0, L1Ip, user_val); 1926 1927 /* 1928 * Both AIVIVT (0b01) and VPIPT (0b00) are documented as reserved. 1929 * Hence only allow to set VIPT(0b10) or PIPT(0b11) for L1Ip based 1930 * on what hardware reports. 1931 * 1932 * Using a VIPT software model on PIPT will lead to over invalidation, 1933 * but still correct. Hence, we can allow downgrading PIPT to VIPT, 1934 * but not the other way around. This is handled via arm64_ftr_safe_value() 1935 * as CTR_EL0 ftr_bits has L1Ip field with type FTR_EXACT and safe value 1936 * set as VIPT. 1937 */ 1938 switch (user_L1Ip) { 1939 case CTR_EL0_L1Ip_RESERVED_VPIPT: 1940 case CTR_EL0_L1Ip_RESERVED_AIVIVT: 1941 return -EINVAL; 1942 case CTR_EL0_L1Ip_VIPT: 1943 case CTR_EL0_L1Ip_PIPT: 1944 return set_id_reg(vcpu, rd, user_val); 1945 default: 1946 return -ENOENT; 1947 } 1948 } 1949 1950 /* 1951 * cpufeature ID register user accessors 1952 * 1953 * For now, these registers are immutable for userspace, so no values 1954 * are stored, and for set_id_reg() we don't allow the effective value 1955 * to be changed. 1956 */ 1957 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1958 u64 *val) 1959 { 1960 /* 1961 * Avoid locking if the VM has already started, as the ID registers are 1962 * guaranteed to be invariant at that point. 1963 */ 1964 if (kvm_vm_has_ran_once(vcpu->kvm)) { 1965 *val = read_id_reg(vcpu, rd); 1966 return 0; 1967 } 1968 1969 mutex_lock(&vcpu->kvm->arch.config_lock); 1970 *val = read_id_reg(vcpu, rd); 1971 mutex_unlock(&vcpu->kvm->arch.config_lock); 1972 1973 return 0; 1974 } 1975 1976 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1977 u64 val) 1978 { 1979 u32 id = reg_to_encoding(rd); 1980 int ret; 1981 1982 mutex_lock(&vcpu->kvm->arch.config_lock); 1983 1984 /* 1985 * Once the VM has started the ID registers are immutable. Reject any 1986 * write that does not match the final register value. 1987 */ 1988 if (kvm_vm_has_ran_once(vcpu->kvm)) { 1989 if (val != read_id_reg(vcpu, rd)) 1990 ret = -EBUSY; 1991 else 1992 ret = 0; 1993 1994 mutex_unlock(&vcpu->kvm->arch.config_lock); 1995 return ret; 1996 } 1997 1998 ret = arm64_check_features(vcpu, rd, val); 1999 if (!ret) 2000 kvm_set_vm_id_reg(vcpu->kvm, id, val); 2001 2002 mutex_unlock(&vcpu->kvm->arch.config_lock); 2003 2004 /* 2005 * arm64_check_features() returns -E2BIG to indicate the register's 2006 * feature set is a superset of the maximally-allowed register value. 2007 * While it would be nice to precisely describe this to userspace, the 2008 * existing UAPI for KVM_SET_ONE_REG has it that invalid register 2009 * writes return -EINVAL. 2010 */ 2011 if (ret == -E2BIG) 2012 ret = -EINVAL; 2013 return ret; 2014 } 2015 2016 void kvm_set_vm_id_reg(struct kvm *kvm, u32 reg, u64 val) 2017 { 2018 u64 *p = __vm_id_reg(&kvm->arch, reg); 2019 2020 lockdep_assert_held(&kvm->arch.config_lock); 2021 2022 if (KVM_BUG_ON(kvm_vm_has_ran_once(kvm) || !p, kvm)) 2023 return; 2024 2025 *p = val; 2026 } 2027 2028 static int get_raz_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 2029 u64 *val) 2030 { 2031 *val = 0; 2032 return 0; 2033 } 2034 2035 static int set_wi_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 2036 u64 val) 2037 { 2038 return 0; 2039 } 2040 2041 static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2042 const struct sys_reg_desc *r) 2043 { 2044 if (p->is_write) 2045 return write_to_read_only(vcpu, p, r); 2046 2047 p->regval = kvm_read_vm_id_reg(vcpu->kvm, SYS_CTR_EL0); 2048 return true; 2049 } 2050 2051 static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2052 const struct sys_reg_desc *r) 2053 { 2054 if (p->is_write) 2055 return write_to_read_only(vcpu, p, r); 2056 2057 p->regval = __vcpu_sys_reg(vcpu, r->reg); 2058 return true; 2059 } 2060 2061 /* 2062 * Fabricate a CLIDR_EL1 value instead of using the real value, which can vary 2063 * by the physical CPU which the vcpu currently resides in. 2064 */ 2065 static u64 reset_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 2066 { 2067 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0); 2068 u64 clidr; 2069 u8 loc; 2070 2071 if ((ctr_el0 & CTR_EL0_IDC)) { 2072 /* 2073 * Data cache clean to the PoU is not required so LoUU and LoUIS 2074 * will not be set and a unified cache, which will be marked as 2075 * LoC, will be added. 2076 * 2077 * If not DIC, let the unified cache L2 so that an instruction 2078 * cache can be added as L1 later. 2079 */ 2080 loc = (ctr_el0 & CTR_EL0_DIC) ? 1 : 2; 2081 clidr = CACHE_TYPE_UNIFIED << CLIDR_CTYPE_SHIFT(loc); 2082 } else { 2083 /* 2084 * Data cache clean to the PoU is required so let L1 have a data 2085 * cache and mark it as LoUU and LoUIS. As L1 has a data cache, 2086 * it can be marked as LoC too. 2087 */ 2088 loc = 1; 2089 clidr = 1 << CLIDR_LOUU_SHIFT; 2090 clidr |= 1 << CLIDR_LOUIS_SHIFT; 2091 clidr |= CACHE_TYPE_DATA << CLIDR_CTYPE_SHIFT(1); 2092 } 2093 2094 /* 2095 * Instruction cache invalidation to the PoU is required so let L1 have 2096 * an instruction cache. If L1 already has a data cache, it will be 2097 * CACHE_TYPE_SEPARATE. 2098 */ 2099 if (!(ctr_el0 & CTR_EL0_DIC)) 2100 clidr |= CACHE_TYPE_INST << CLIDR_CTYPE_SHIFT(1); 2101 2102 clidr |= loc << CLIDR_LOC_SHIFT; 2103 2104 /* 2105 * Add tag cache unified to data cache. Allocation tags and data are 2106 * unified in a cache line so that it looks valid even if there is only 2107 * one cache line. 2108 */ 2109 if (kvm_has_mte(vcpu->kvm)) 2110 clidr |= 2ULL << CLIDR_TTYPE_SHIFT(loc); 2111 2112 __vcpu_sys_reg(vcpu, r->reg) = clidr; 2113 2114 return __vcpu_sys_reg(vcpu, r->reg); 2115 } 2116 2117 static int set_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 2118 u64 val) 2119 { 2120 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0); 2121 u64 idc = !CLIDR_LOC(val) || (!CLIDR_LOUIS(val) && !CLIDR_LOUU(val)); 2122 2123 if ((val & CLIDR_EL1_RES0) || (!(ctr_el0 & CTR_EL0_IDC) && idc)) 2124 return -EINVAL; 2125 2126 __vcpu_sys_reg(vcpu, rd->reg) = val; 2127 2128 return 0; 2129 } 2130 2131 static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2132 const struct sys_reg_desc *r) 2133 { 2134 int reg = r->reg; 2135 2136 if (p->is_write) 2137 vcpu_write_sys_reg(vcpu, p->regval, reg); 2138 else 2139 p->regval = vcpu_read_sys_reg(vcpu, reg); 2140 return true; 2141 } 2142 2143 static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2144 const struct sys_reg_desc *r) 2145 { 2146 u32 csselr; 2147 2148 if (p->is_write) 2149 return write_to_read_only(vcpu, p, r); 2150 2151 csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1); 2152 csselr &= CSSELR_EL1_Level | CSSELR_EL1_InD; 2153 if (csselr < CSSELR_MAX) 2154 p->regval = get_ccsidr(vcpu, csselr); 2155 2156 return true; 2157 } 2158 2159 static unsigned int mte_visibility(const struct kvm_vcpu *vcpu, 2160 const struct sys_reg_desc *rd) 2161 { 2162 if (kvm_has_mte(vcpu->kvm)) 2163 return 0; 2164 2165 return REG_HIDDEN; 2166 } 2167 2168 #define MTE_REG(name) { \ 2169 SYS_DESC(SYS_##name), \ 2170 .access = undef_access, \ 2171 .reset = reset_unknown, \ 2172 .reg = name, \ 2173 .visibility = mte_visibility, \ 2174 } 2175 2176 static unsigned int el2_visibility(const struct kvm_vcpu *vcpu, 2177 const struct sys_reg_desc *rd) 2178 { 2179 if (vcpu_has_nv(vcpu)) 2180 return 0; 2181 2182 return REG_HIDDEN; 2183 } 2184 2185 static bool bad_vncr_trap(struct kvm_vcpu *vcpu, 2186 struct sys_reg_params *p, 2187 const struct sys_reg_desc *r) 2188 { 2189 /* 2190 * We really shouldn't be here, and this is likely the result 2191 * of a misconfigured trap, as this register should target the 2192 * VNCR page, and nothing else. 2193 */ 2194 return bad_trap(vcpu, p, r, 2195 "trap of VNCR-backed register"); 2196 } 2197 2198 static bool bad_redir_trap(struct kvm_vcpu *vcpu, 2199 struct sys_reg_params *p, 2200 const struct sys_reg_desc *r) 2201 { 2202 /* 2203 * We really shouldn't be here, and this is likely the result 2204 * of a misconfigured trap, as this register should target the 2205 * corresponding EL1, and nothing else. 2206 */ 2207 return bad_trap(vcpu, p, r, 2208 "trap of EL2 register redirected to EL1"); 2209 } 2210 2211 #define EL2_REG(name, acc, rst, v) { \ 2212 SYS_DESC(SYS_##name), \ 2213 .access = acc, \ 2214 .reset = rst, \ 2215 .reg = name, \ 2216 .visibility = el2_visibility, \ 2217 .val = v, \ 2218 } 2219 2220 #define EL2_REG_FILTERED(name, acc, rst, v, filter) { \ 2221 SYS_DESC(SYS_##name), \ 2222 .access = acc, \ 2223 .reset = rst, \ 2224 .reg = name, \ 2225 .visibility = filter, \ 2226 .val = v, \ 2227 } 2228 2229 #define EL2_REG_VNCR(name, rst, v) EL2_REG(name, bad_vncr_trap, rst, v) 2230 #define EL2_REG_REDIR(name, rst, v) EL2_REG(name, bad_redir_trap, rst, v) 2231 2232 /* 2233 * Since reset() callback and field val are not used for idregs, they will be 2234 * used for specific purposes for idregs. 2235 * The reset() would return KVM sanitised register value. The value would be the 2236 * same as the host kernel sanitised value if there is no KVM sanitisation. 2237 * The val would be used as a mask indicating writable fields for the idreg. 2238 * Only bits with 1 are writable from userspace. This mask might not be 2239 * necessary in the future whenever all ID registers are enabled as writable 2240 * from userspace. 2241 */ 2242 2243 #define ID_DESC(name) \ 2244 SYS_DESC(SYS_##name), \ 2245 .access = access_id_reg, \ 2246 .get_user = get_id_reg \ 2247 2248 /* sys_reg_desc initialiser for known cpufeature ID registers */ 2249 #define ID_SANITISED(name) { \ 2250 ID_DESC(name), \ 2251 .set_user = set_id_reg, \ 2252 .visibility = id_visibility, \ 2253 .reset = kvm_read_sanitised_id_reg, \ 2254 .val = 0, \ 2255 } 2256 2257 /* sys_reg_desc initialiser for known cpufeature ID registers */ 2258 #define AA32_ID_SANITISED(name) { \ 2259 ID_DESC(name), \ 2260 .set_user = set_id_reg, \ 2261 .visibility = aa32_id_visibility, \ 2262 .reset = kvm_read_sanitised_id_reg, \ 2263 .val = 0, \ 2264 } 2265 2266 /* sys_reg_desc initialiser for writable ID registers */ 2267 #define ID_WRITABLE(name, mask) { \ 2268 ID_DESC(name), \ 2269 .set_user = set_id_reg, \ 2270 .visibility = id_visibility, \ 2271 .reset = kvm_read_sanitised_id_reg, \ 2272 .val = mask, \ 2273 } 2274 2275 /* sys_reg_desc initialiser for cpufeature ID registers that need filtering */ 2276 #define ID_FILTERED(sysreg, name, mask) { \ 2277 ID_DESC(sysreg), \ 2278 .set_user = set_##name, \ 2279 .visibility = id_visibility, \ 2280 .reset = kvm_read_sanitised_id_reg, \ 2281 .val = (mask), \ 2282 } 2283 2284 /* 2285 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID 2286 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2 2287 * (1 <= crm < 8, 0 <= Op2 < 8). 2288 */ 2289 #define ID_UNALLOCATED(crm, op2) { \ 2290 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \ 2291 .access = access_id_reg, \ 2292 .get_user = get_id_reg, \ 2293 .set_user = set_id_reg, \ 2294 .visibility = raz_visibility, \ 2295 .reset = kvm_read_sanitised_id_reg, \ 2296 .val = 0, \ 2297 } 2298 2299 /* 2300 * sys_reg_desc initialiser for known ID registers that we hide from guests. 2301 * For now, these are exposed just like unallocated ID regs: they appear 2302 * RAZ for the guest. 2303 */ 2304 #define ID_HIDDEN(name) { \ 2305 ID_DESC(name), \ 2306 .set_user = set_id_reg, \ 2307 .visibility = raz_visibility, \ 2308 .reset = kvm_read_sanitised_id_reg, \ 2309 .val = 0, \ 2310 } 2311 2312 static bool access_sp_el1(struct kvm_vcpu *vcpu, 2313 struct sys_reg_params *p, 2314 const struct sys_reg_desc *r) 2315 { 2316 if (p->is_write) 2317 __vcpu_sys_reg(vcpu, SP_EL1) = p->regval; 2318 else 2319 p->regval = __vcpu_sys_reg(vcpu, SP_EL1); 2320 2321 return true; 2322 } 2323 2324 static bool access_elr(struct kvm_vcpu *vcpu, 2325 struct sys_reg_params *p, 2326 const struct sys_reg_desc *r) 2327 { 2328 if (p->is_write) 2329 vcpu_write_sys_reg(vcpu, p->regval, ELR_EL1); 2330 else 2331 p->regval = vcpu_read_sys_reg(vcpu, ELR_EL1); 2332 2333 return true; 2334 } 2335 2336 static bool access_spsr(struct kvm_vcpu *vcpu, 2337 struct sys_reg_params *p, 2338 const struct sys_reg_desc *r) 2339 { 2340 if (p->is_write) 2341 __vcpu_sys_reg(vcpu, SPSR_EL1) = p->regval; 2342 else 2343 p->regval = __vcpu_sys_reg(vcpu, SPSR_EL1); 2344 2345 return true; 2346 } 2347 2348 static bool access_cntkctl_el12(struct kvm_vcpu *vcpu, 2349 struct sys_reg_params *p, 2350 const struct sys_reg_desc *r) 2351 { 2352 if (p->is_write) 2353 __vcpu_sys_reg(vcpu, CNTKCTL_EL1) = p->regval; 2354 else 2355 p->regval = __vcpu_sys_reg(vcpu, CNTKCTL_EL1); 2356 2357 return true; 2358 } 2359 2360 static u64 reset_hcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 2361 { 2362 u64 val = r->val; 2363 2364 if (!cpus_have_final_cap(ARM64_HAS_HCR_NV1)) 2365 val |= HCR_E2H; 2366 2367 return __vcpu_sys_reg(vcpu, r->reg) = val; 2368 } 2369 2370 static unsigned int __el2_visibility(const struct kvm_vcpu *vcpu, 2371 const struct sys_reg_desc *rd, 2372 unsigned int (*fn)(const struct kvm_vcpu *, 2373 const struct sys_reg_desc *)) 2374 { 2375 return el2_visibility(vcpu, rd) ?: fn(vcpu, rd); 2376 } 2377 2378 static unsigned int sve_el2_visibility(const struct kvm_vcpu *vcpu, 2379 const struct sys_reg_desc *rd) 2380 { 2381 return __el2_visibility(vcpu, rd, sve_visibility); 2382 } 2383 2384 static bool access_zcr_el2(struct kvm_vcpu *vcpu, 2385 struct sys_reg_params *p, 2386 const struct sys_reg_desc *r) 2387 { 2388 unsigned int vq; 2389 2390 if (guest_hyp_sve_traps_enabled(vcpu)) { 2391 kvm_inject_nested_sve_trap(vcpu); 2392 return true; 2393 } 2394 2395 if (!p->is_write) { 2396 p->regval = vcpu_read_sys_reg(vcpu, ZCR_EL2); 2397 return true; 2398 } 2399 2400 vq = SYS_FIELD_GET(ZCR_ELx, LEN, p->regval) + 1; 2401 vq = min(vq, vcpu_sve_max_vq(vcpu)); 2402 vcpu_write_sys_reg(vcpu, vq - 1, ZCR_EL2); 2403 return true; 2404 } 2405 2406 static unsigned int s1poe_visibility(const struct kvm_vcpu *vcpu, 2407 const struct sys_reg_desc *rd) 2408 { 2409 if (kvm_has_s1poe(vcpu->kvm)) 2410 return 0; 2411 2412 return REG_HIDDEN; 2413 } 2414 2415 static unsigned int s1poe_el2_visibility(const struct kvm_vcpu *vcpu, 2416 const struct sys_reg_desc *rd) 2417 { 2418 return __el2_visibility(vcpu, rd, s1poe_visibility); 2419 } 2420 2421 static unsigned int tcr2_visibility(const struct kvm_vcpu *vcpu, 2422 const struct sys_reg_desc *rd) 2423 { 2424 if (kvm_has_tcr2(vcpu->kvm)) 2425 return 0; 2426 2427 return REG_HIDDEN; 2428 } 2429 2430 static unsigned int tcr2_el2_visibility(const struct kvm_vcpu *vcpu, 2431 const struct sys_reg_desc *rd) 2432 { 2433 return __el2_visibility(vcpu, rd, tcr2_visibility); 2434 } 2435 2436 static unsigned int s1pie_visibility(const struct kvm_vcpu *vcpu, 2437 const struct sys_reg_desc *rd) 2438 { 2439 if (kvm_has_s1pie(vcpu->kvm)) 2440 return 0; 2441 2442 return REG_HIDDEN; 2443 } 2444 2445 static unsigned int s1pie_el2_visibility(const struct kvm_vcpu *vcpu, 2446 const struct sys_reg_desc *rd) 2447 { 2448 return __el2_visibility(vcpu, rd, s1pie_visibility); 2449 } 2450 2451 static bool access_mdcr(struct kvm_vcpu *vcpu, 2452 struct sys_reg_params *p, 2453 const struct sys_reg_desc *r) 2454 { 2455 u64 old = __vcpu_sys_reg(vcpu, MDCR_EL2); 2456 2457 if (!access_rw(vcpu, p, r)) 2458 return false; 2459 2460 /* 2461 * Request a reload of the PMU to enable/disable the counters affected 2462 * by HPME. 2463 */ 2464 if ((old ^ __vcpu_sys_reg(vcpu, MDCR_EL2)) & MDCR_EL2_HPME) 2465 kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu); 2466 2467 return true; 2468 } 2469 2470 2471 /* 2472 * Architected system registers. 2473 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2 2474 * 2475 * Debug handling: We do trap most, if not all debug related system 2476 * registers. The implementation is good enough to ensure that a guest 2477 * can use these with minimal performance degradation. The drawback is 2478 * that we don't implement any of the external debug architecture. 2479 * This should be revisited if we ever encounter a more demanding 2480 * guest... 2481 */ 2482 static const struct sys_reg_desc sys_reg_descs[] = { 2483 DBG_BCR_BVR_WCR_WVR_EL1(0), 2484 DBG_BCR_BVR_WCR_WVR_EL1(1), 2485 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 }, 2486 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 }, 2487 DBG_BCR_BVR_WCR_WVR_EL1(2), 2488 DBG_BCR_BVR_WCR_WVR_EL1(3), 2489 DBG_BCR_BVR_WCR_WVR_EL1(4), 2490 DBG_BCR_BVR_WCR_WVR_EL1(5), 2491 DBG_BCR_BVR_WCR_WVR_EL1(6), 2492 DBG_BCR_BVR_WCR_WVR_EL1(7), 2493 DBG_BCR_BVR_WCR_WVR_EL1(8), 2494 DBG_BCR_BVR_WCR_WVR_EL1(9), 2495 DBG_BCR_BVR_WCR_WVR_EL1(10), 2496 DBG_BCR_BVR_WCR_WVR_EL1(11), 2497 DBG_BCR_BVR_WCR_WVR_EL1(12), 2498 DBG_BCR_BVR_WCR_WVR_EL1(13), 2499 DBG_BCR_BVR_WCR_WVR_EL1(14), 2500 DBG_BCR_BVR_WCR_WVR_EL1(15), 2501 2502 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi }, 2503 { SYS_DESC(SYS_OSLAR_EL1), trap_oslar_el1 }, 2504 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1, 2505 OSLSR_EL1_OSLM_IMPLEMENTED, .set_user = set_oslsr_el1, }, 2506 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi }, 2507 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi }, 2508 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi }, 2509 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi }, 2510 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 }, 2511 2512 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi }, 2513 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi }, 2514 // DBGDTR[TR]X_EL0 share the same encoding 2515 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi }, 2516 2517 { SYS_DESC(SYS_DBGVCR32_EL2), undef_access, reset_val, DBGVCR32_EL2, 0 }, 2518 2519 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 }, 2520 2521 /* 2522 * ID regs: all ID_SANITISED() entries here must have corresponding 2523 * entries in arm64_ftr_regs[]. 2524 */ 2525 2526 /* AArch64 mappings of the AArch32 ID registers */ 2527 /* CRm=1 */ 2528 AA32_ID_SANITISED(ID_PFR0_EL1), 2529 AA32_ID_SANITISED(ID_PFR1_EL1), 2530 { SYS_DESC(SYS_ID_DFR0_EL1), 2531 .access = access_id_reg, 2532 .get_user = get_id_reg, 2533 .set_user = set_id_dfr0_el1, 2534 .visibility = aa32_id_visibility, 2535 .reset = read_sanitised_id_dfr0_el1, 2536 .val = ID_DFR0_EL1_PerfMon_MASK | 2537 ID_DFR0_EL1_CopDbg_MASK, }, 2538 ID_HIDDEN(ID_AFR0_EL1), 2539 AA32_ID_SANITISED(ID_MMFR0_EL1), 2540 AA32_ID_SANITISED(ID_MMFR1_EL1), 2541 AA32_ID_SANITISED(ID_MMFR2_EL1), 2542 AA32_ID_SANITISED(ID_MMFR3_EL1), 2543 2544 /* CRm=2 */ 2545 AA32_ID_SANITISED(ID_ISAR0_EL1), 2546 AA32_ID_SANITISED(ID_ISAR1_EL1), 2547 AA32_ID_SANITISED(ID_ISAR2_EL1), 2548 AA32_ID_SANITISED(ID_ISAR3_EL1), 2549 AA32_ID_SANITISED(ID_ISAR4_EL1), 2550 AA32_ID_SANITISED(ID_ISAR5_EL1), 2551 AA32_ID_SANITISED(ID_MMFR4_EL1), 2552 AA32_ID_SANITISED(ID_ISAR6_EL1), 2553 2554 /* CRm=3 */ 2555 AA32_ID_SANITISED(MVFR0_EL1), 2556 AA32_ID_SANITISED(MVFR1_EL1), 2557 AA32_ID_SANITISED(MVFR2_EL1), 2558 ID_UNALLOCATED(3,3), 2559 AA32_ID_SANITISED(ID_PFR2_EL1), 2560 ID_HIDDEN(ID_DFR1_EL1), 2561 AA32_ID_SANITISED(ID_MMFR5_EL1), 2562 ID_UNALLOCATED(3,7), 2563 2564 /* AArch64 ID registers */ 2565 /* CRm=4 */ 2566 ID_FILTERED(ID_AA64PFR0_EL1, id_aa64pfr0_el1, 2567 ~(ID_AA64PFR0_EL1_AMU | 2568 ID_AA64PFR0_EL1_MPAM | 2569 ID_AA64PFR0_EL1_SVE | 2570 ID_AA64PFR0_EL1_RAS | 2571 ID_AA64PFR0_EL1_AdvSIMD | 2572 ID_AA64PFR0_EL1_FP)), 2573 ID_FILTERED(ID_AA64PFR1_EL1, id_aa64pfr1_el1, 2574 ~(ID_AA64PFR1_EL1_PFAR | 2575 ID_AA64PFR1_EL1_DF2 | 2576 ID_AA64PFR1_EL1_MTEX | 2577 ID_AA64PFR1_EL1_THE | 2578 ID_AA64PFR1_EL1_GCS | 2579 ID_AA64PFR1_EL1_MTE_frac | 2580 ID_AA64PFR1_EL1_NMI | 2581 ID_AA64PFR1_EL1_RNDR_trap | 2582 ID_AA64PFR1_EL1_SME | 2583 ID_AA64PFR1_EL1_RES0 | 2584 ID_AA64PFR1_EL1_MPAM_frac | 2585 ID_AA64PFR1_EL1_RAS_frac | 2586 ID_AA64PFR1_EL1_MTE)), 2587 ID_WRITABLE(ID_AA64PFR2_EL1, ID_AA64PFR2_EL1_FPMR), 2588 ID_UNALLOCATED(4,3), 2589 ID_WRITABLE(ID_AA64ZFR0_EL1, ~ID_AA64ZFR0_EL1_RES0), 2590 ID_HIDDEN(ID_AA64SMFR0_EL1), 2591 ID_UNALLOCATED(4,6), 2592 ID_WRITABLE(ID_AA64FPFR0_EL1, ~ID_AA64FPFR0_EL1_RES0), 2593 2594 /* CRm=5 */ 2595 /* 2596 * Prior to FEAT_Debugv8.9, the architecture defines context-aware 2597 * breakpoints (CTX_CMPs) as the highest numbered breakpoints (BRPs). 2598 * KVM does not trap + emulate the breakpoint registers, and as such 2599 * cannot support a layout that misaligns with the underlying hardware. 2600 * While it may be possible to describe a subset that aligns with 2601 * hardware, just prevent changes to BRPs and CTX_CMPs altogether for 2602 * simplicity. 2603 * 2604 * See DDI0487K.a, section D2.8.3 Breakpoint types and linking 2605 * of breakpoints for more details. 2606 */ 2607 ID_FILTERED(ID_AA64DFR0_EL1, id_aa64dfr0_el1, 2608 ID_AA64DFR0_EL1_DoubleLock_MASK | 2609 ID_AA64DFR0_EL1_WRPs_MASK | 2610 ID_AA64DFR0_EL1_PMUVer_MASK | 2611 ID_AA64DFR0_EL1_DebugVer_MASK), 2612 ID_SANITISED(ID_AA64DFR1_EL1), 2613 ID_UNALLOCATED(5,2), 2614 ID_UNALLOCATED(5,3), 2615 ID_HIDDEN(ID_AA64AFR0_EL1), 2616 ID_HIDDEN(ID_AA64AFR1_EL1), 2617 ID_UNALLOCATED(5,6), 2618 ID_UNALLOCATED(5,7), 2619 2620 /* CRm=6 */ 2621 ID_WRITABLE(ID_AA64ISAR0_EL1, ~ID_AA64ISAR0_EL1_RES0), 2622 ID_WRITABLE(ID_AA64ISAR1_EL1, ~(ID_AA64ISAR1_EL1_GPI | 2623 ID_AA64ISAR1_EL1_GPA | 2624 ID_AA64ISAR1_EL1_API | 2625 ID_AA64ISAR1_EL1_APA)), 2626 ID_WRITABLE(ID_AA64ISAR2_EL1, ~(ID_AA64ISAR2_EL1_RES0 | 2627 ID_AA64ISAR2_EL1_APA3 | 2628 ID_AA64ISAR2_EL1_GPA3)), 2629 ID_UNALLOCATED(6,3), 2630 ID_UNALLOCATED(6,4), 2631 ID_UNALLOCATED(6,5), 2632 ID_UNALLOCATED(6,6), 2633 ID_UNALLOCATED(6,7), 2634 2635 /* CRm=7 */ 2636 ID_WRITABLE(ID_AA64MMFR0_EL1, ~(ID_AA64MMFR0_EL1_RES0 | 2637 ID_AA64MMFR0_EL1_TGRAN4_2 | 2638 ID_AA64MMFR0_EL1_TGRAN64_2 | 2639 ID_AA64MMFR0_EL1_TGRAN16_2 | 2640 ID_AA64MMFR0_EL1_ASIDBITS)), 2641 ID_WRITABLE(ID_AA64MMFR1_EL1, ~(ID_AA64MMFR1_EL1_RES0 | 2642 ID_AA64MMFR1_EL1_HCX | 2643 ID_AA64MMFR1_EL1_TWED | 2644 ID_AA64MMFR1_EL1_XNX | 2645 ID_AA64MMFR1_EL1_VH | 2646 ID_AA64MMFR1_EL1_VMIDBits)), 2647 ID_WRITABLE(ID_AA64MMFR2_EL1, ~(ID_AA64MMFR2_EL1_RES0 | 2648 ID_AA64MMFR2_EL1_EVT | 2649 ID_AA64MMFR2_EL1_FWB | 2650 ID_AA64MMFR2_EL1_IDS | 2651 ID_AA64MMFR2_EL1_NV | 2652 ID_AA64MMFR2_EL1_CCIDX)), 2653 ID_WRITABLE(ID_AA64MMFR3_EL1, (ID_AA64MMFR3_EL1_TCRX | 2654 ID_AA64MMFR3_EL1_S1PIE | 2655 ID_AA64MMFR3_EL1_S1POE)), 2656 ID_SANITISED(ID_AA64MMFR4_EL1), 2657 ID_UNALLOCATED(7,5), 2658 ID_UNALLOCATED(7,6), 2659 ID_UNALLOCATED(7,7), 2660 2661 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 }, 2662 { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 }, 2663 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 }, 2664 2665 MTE_REG(RGSR_EL1), 2666 MTE_REG(GCR_EL1), 2667 2668 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility }, 2669 { SYS_DESC(SYS_TRFCR_EL1), undef_access }, 2670 { SYS_DESC(SYS_SMPRI_EL1), undef_access }, 2671 { SYS_DESC(SYS_SMCR_EL1), undef_access }, 2672 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 }, 2673 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 }, 2674 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 }, 2675 { SYS_DESC(SYS_TCR2_EL1), access_vm_reg, reset_val, TCR2_EL1, 0, 2676 .visibility = tcr2_visibility }, 2677 2678 PTRAUTH_KEY(APIA), 2679 PTRAUTH_KEY(APIB), 2680 PTRAUTH_KEY(APDA), 2681 PTRAUTH_KEY(APDB), 2682 PTRAUTH_KEY(APGA), 2683 2684 { SYS_DESC(SYS_SPSR_EL1), access_spsr}, 2685 { SYS_DESC(SYS_ELR_EL1), access_elr}, 2686 2687 { SYS_DESC(SYS_ICC_PMR_EL1), undef_access }, 2688 2689 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 }, 2690 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 }, 2691 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 }, 2692 2693 { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi }, 2694 { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi }, 2695 { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi }, 2696 { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi }, 2697 { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi }, 2698 { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi }, 2699 { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi }, 2700 { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi }, 2701 2702 MTE_REG(TFSR_EL1), 2703 MTE_REG(TFSRE0_EL1), 2704 2705 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 }, 2706 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 }, 2707 2708 { SYS_DESC(SYS_PMSCR_EL1), undef_access }, 2709 { SYS_DESC(SYS_PMSNEVFR_EL1), undef_access }, 2710 { SYS_DESC(SYS_PMSICR_EL1), undef_access }, 2711 { SYS_DESC(SYS_PMSIRR_EL1), undef_access }, 2712 { SYS_DESC(SYS_PMSFCR_EL1), undef_access }, 2713 { SYS_DESC(SYS_PMSEVFR_EL1), undef_access }, 2714 { SYS_DESC(SYS_PMSLATFR_EL1), undef_access }, 2715 { SYS_DESC(SYS_PMSIDR_EL1), undef_access }, 2716 { SYS_DESC(SYS_PMBLIMITR_EL1), undef_access }, 2717 { SYS_DESC(SYS_PMBPTR_EL1), undef_access }, 2718 { SYS_DESC(SYS_PMBSR_EL1), undef_access }, 2719 /* PMBIDR_EL1 is not trapped */ 2720 2721 { PMU_SYS_REG(PMINTENSET_EL1), 2722 .access = access_pminten, .reg = PMINTENSET_EL1, 2723 .get_user = get_pmreg, .set_user = set_pmreg }, 2724 { PMU_SYS_REG(PMINTENCLR_EL1), 2725 .access = access_pminten, .reg = PMINTENSET_EL1, 2726 .get_user = get_pmreg, .set_user = set_pmreg }, 2727 { SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi }, 2728 2729 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 }, 2730 { SYS_DESC(SYS_PIRE0_EL1), NULL, reset_unknown, PIRE0_EL1, 2731 .visibility = s1pie_visibility }, 2732 { SYS_DESC(SYS_PIR_EL1), NULL, reset_unknown, PIR_EL1, 2733 .visibility = s1pie_visibility }, 2734 { SYS_DESC(SYS_POR_EL1), NULL, reset_unknown, POR_EL1, 2735 .visibility = s1poe_visibility }, 2736 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 }, 2737 2738 { SYS_DESC(SYS_LORSA_EL1), trap_loregion }, 2739 { SYS_DESC(SYS_LOREA_EL1), trap_loregion }, 2740 { SYS_DESC(SYS_LORN_EL1), trap_loregion }, 2741 { SYS_DESC(SYS_LORC_EL1), trap_loregion }, 2742 { SYS_DESC(SYS_MPAMIDR_EL1), undef_access }, 2743 { SYS_DESC(SYS_LORID_EL1), trap_loregion }, 2744 2745 { SYS_DESC(SYS_MPAM1_EL1), undef_access }, 2746 { SYS_DESC(SYS_MPAM0_EL1), undef_access }, 2747 { SYS_DESC(SYS_VBAR_EL1), access_rw, reset_val, VBAR_EL1, 0 }, 2748 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 }, 2749 2750 { SYS_DESC(SYS_ICC_IAR0_EL1), undef_access }, 2751 { SYS_DESC(SYS_ICC_EOIR0_EL1), undef_access }, 2752 { SYS_DESC(SYS_ICC_HPPIR0_EL1), undef_access }, 2753 { SYS_DESC(SYS_ICC_BPR0_EL1), undef_access }, 2754 { SYS_DESC(SYS_ICC_AP0R0_EL1), undef_access }, 2755 { SYS_DESC(SYS_ICC_AP0R1_EL1), undef_access }, 2756 { SYS_DESC(SYS_ICC_AP0R2_EL1), undef_access }, 2757 { SYS_DESC(SYS_ICC_AP0R3_EL1), undef_access }, 2758 { SYS_DESC(SYS_ICC_AP1R0_EL1), undef_access }, 2759 { SYS_DESC(SYS_ICC_AP1R1_EL1), undef_access }, 2760 { SYS_DESC(SYS_ICC_AP1R2_EL1), undef_access }, 2761 { SYS_DESC(SYS_ICC_AP1R3_EL1), undef_access }, 2762 { SYS_DESC(SYS_ICC_DIR_EL1), undef_access }, 2763 { SYS_DESC(SYS_ICC_RPR_EL1), undef_access }, 2764 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi }, 2765 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi }, 2766 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi }, 2767 { SYS_DESC(SYS_ICC_IAR1_EL1), undef_access }, 2768 { SYS_DESC(SYS_ICC_EOIR1_EL1), undef_access }, 2769 { SYS_DESC(SYS_ICC_HPPIR1_EL1), undef_access }, 2770 { SYS_DESC(SYS_ICC_BPR1_EL1), undef_access }, 2771 { SYS_DESC(SYS_ICC_CTLR_EL1), undef_access }, 2772 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre }, 2773 { SYS_DESC(SYS_ICC_IGRPEN0_EL1), undef_access }, 2774 { SYS_DESC(SYS_ICC_IGRPEN1_EL1), undef_access }, 2775 2776 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 }, 2777 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 }, 2778 2779 { SYS_DESC(SYS_ACCDATA_EL1), undef_access }, 2780 2781 { SYS_DESC(SYS_SCXTNUM_EL1), undef_access }, 2782 2783 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0}, 2784 2785 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr }, 2786 { SYS_DESC(SYS_CLIDR_EL1), access_clidr, reset_clidr, CLIDR_EL1, 2787 .set_user = set_clidr, .val = ~CLIDR_EL1_RES0 }, 2788 { SYS_DESC(SYS_CCSIDR2_EL1), undef_access }, 2789 { SYS_DESC(SYS_SMIDR_EL1), undef_access }, 2790 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, 2791 ID_FILTERED(CTR_EL0, ctr_el0, 2792 CTR_EL0_DIC_MASK | 2793 CTR_EL0_IDC_MASK | 2794 CTR_EL0_DminLine_MASK | 2795 CTR_EL0_L1Ip_MASK | 2796 CTR_EL0_IminLine_MASK), 2797 { SYS_DESC(SYS_SVCR), undef_access, reset_val, SVCR, 0, .visibility = sme_visibility }, 2798 { SYS_DESC(SYS_FPMR), undef_access, reset_val, FPMR, 0, .visibility = fp8_visibility }, 2799 2800 { PMU_SYS_REG(PMCR_EL0), .access = access_pmcr, .reset = reset_pmcr, 2801 .reg = PMCR_EL0, .get_user = get_pmcr, .set_user = set_pmcr }, 2802 { PMU_SYS_REG(PMCNTENSET_EL0), 2803 .access = access_pmcnten, .reg = PMCNTENSET_EL0, 2804 .get_user = get_pmreg, .set_user = set_pmreg }, 2805 { PMU_SYS_REG(PMCNTENCLR_EL0), 2806 .access = access_pmcnten, .reg = PMCNTENSET_EL0, 2807 .get_user = get_pmreg, .set_user = set_pmreg }, 2808 { PMU_SYS_REG(PMOVSCLR_EL0), 2809 .access = access_pmovs, .reg = PMOVSSET_EL0, 2810 .get_user = get_pmreg, .set_user = set_pmreg }, 2811 /* 2812 * PM_SWINC_EL0 is exposed to userspace as RAZ/WI, as it was 2813 * previously (and pointlessly) advertised in the past... 2814 */ 2815 { PMU_SYS_REG(PMSWINC_EL0), 2816 .get_user = get_raz_reg, .set_user = set_wi_reg, 2817 .access = access_pmswinc, .reset = NULL }, 2818 { PMU_SYS_REG(PMSELR_EL0), 2819 .access = access_pmselr, .reset = reset_pmselr, .reg = PMSELR_EL0 }, 2820 { PMU_SYS_REG(PMCEID0_EL0), 2821 .access = access_pmceid, .reset = NULL }, 2822 { PMU_SYS_REG(PMCEID1_EL0), 2823 .access = access_pmceid, .reset = NULL }, 2824 { PMU_SYS_REG(PMCCNTR_EL0), 2825 .access = access_pmu_evcntr, .reset = reset_unknown, 2826 .reg = PMCCNTR_EL0, .get_user = get_pmu_evcntr}, 2827 { PMU_SYS_REG(PMXEVTYPER_EL0), 2828 .access = access_pmu_evtyper, .reset = NULL }, 2829 { PMU_SYS_REG(PMXEVCNTR_EL0), 2830 .access = access_pmu_evcntr, .reset = NULL }, 2831 /* 2832 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero 2833 * in 32bit mode. Here we choose to reset it as zero for consistency. 2834 */ 2835 { PMU_SYS_REG(PMUSERENR_EL0), .access = access_pmuserenr, 2836 .reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 }, 2837 { PMU_SYS_REG(PMOVSSET_EL0), 2838 .access = access_pmovs, .reg = PMOVSSET_EL0, 2839 .get_user = get_pmreg, .set_user = set_pmreg }, 2840 2841 { SYS_DESC(SYS_POR_EL0), NULL, reset_unknown, POR_EL0, 2842 .visibility = s1poe_visibility }, 2843 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 }, 2844 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 }, 2845 { SYS_DESC(SYS_TPIDR2_EL0), undef_access }, 2846 2847 { SYS_DESC(SYS_SCXTNUM_EL0), undef_access }, 2848 2849 { SYS_DESC(SYS_AMCR_EL0), undef_access }, 2850 { SYS_DESC(SYS_AMCFGR_EL0), undef_access }, 2851 { SYS_DESC(SYS_AMCGCR_EL0), undef_access }, 2852 { SYS_DESC(SYS_AMUSERENR_EL0), undef_access }, 2853 { SYS_DESC(SYS_AMCNTENCLR0_EL0), undef_access }, 2854 { SYS_DESC(SYS_AMCNTENSET0_EL0), undef_access }, 2855 { SYS_DESC(SYS_AMCNTENCLR1_EL0), undef_access }, 2856 { SYS_DESC(SYS_AMCNTENSET1_EL0), undef_access }, 2857 AMU_AMEVCNTR0_EL0(0), 2858 AMU_AMEVCNTR0_EL0(1), 2859 AMU_AMEVCNTR0_EL0(2), 2860 AMU_AMEVCNTR0_EL0(3), 2861 AMU_AMEVCNTR0_EL0(4), 2862 AMU_AMEVCNTR0_EL0(5), 2863 AMU_AMEVCNTR0_EL0(6), 2864 AMU_AMEVCNTR0_EL0(7), 2865 AMU_AMEVCNTR0_EL0(8), 2866 AMU_AMEVCNTR0_EL0(9), 2867 AMU_AMEVCNTR0_EL0(10), 2868 AMU_AMEVCNTR0_EL0(11), 2869 AMU_AMEVCNTR0_EL0(12), 2870 AMU_AMEVCNTR0_EL0(13), 2871 AMU_AMEVCNTR0_EL0(14), 2872 AMU_AMEVCNTR0_EL0(15), 2873 AMU_AMEVTYPER0_EL0(0), 2874 AMU_AMEVTYPER0_EL0(1), 2875 AMU_AMEVTYPER0_EL0(2), 2876 AMU_AMEVTYPER0_EL0(3), 2877 AMU_AMEVTYPER0_EL0(4), 2878 AMU_AMEVTYPER0_EL0(5), 2879 AMU_AMEVTYPER0_EL0(6), 2880 AMU_AMEVTYPER0_EL0(7), 2881 AMU_AMEVTYPER0_EL0(8), 2882 AMU_AMEVTYPER0_EL0(9), 2883 AMU_AMEVTYPER0_EL0(10), 2884 AMU_AMEVTYPER0_EL0(11), 2885 AMU_AMEVTYPER0_EL0(12), 2886 AMU_AMEVTYPER0_EL0(13), 2887 AMU_AMEVTYPER0_EL0(14), 2888 AMU_AMEVTYPER0_EL0(15), 2889 AMU_AMEVCNTR1_EL0(0), 2890 AMU_AMEVCNTR1_EL0(1), 2891 AMU_AMEVCNTR1_EL0(2), 2892 AMU_AMEVCNTR1_EL0(3), 2893 AMU_AMEVCNTR1_EL0(4), 2894 AMU_AMEVCNTR1_EL0(5), 2895 AMU_AMEVCNTR1_EL0(6), 2896 AMU_AMEVCNTR1_EL0(7), 2897 AMU_AMEVCNTR1_EL0(8), 2898 AMU_AMEVCNTR1_EL0(9), 2899 AMU_AMEVCNTR1_EL0(10), 2900 AMU_AMEVCNTR1_EL0(11), 2901 AMU_AMEVCNTR1_EL0(12), 2902 AMU_AMEVCNTR1_EL0(13), 2903 AMU_AMEVCNTR1_EL0(14), 2904 AMU_AMEVCNTR1_EL0(15), 2905 AMU_AMEVTYPER1_EL0(0), 2906 AMU_AMEVTYPER1_EL0(1), 2907 AMU_AMEVTYPER1_EL0(2), 2908 AMU_AMEVTYPER1_EL0(3), 2909 AMU_AMEVTYPER1_EL0(4), 2910 AMU_AMEVTYPER1_EL0(5), 2911 AMU_AMEVTYPER1_EL0(6), 2912 AMU_AMEVTYPER1_EL0(7), 2913 AMU_AMEVTYPER1_EL0(8), 2914 AMU_AMEVTYPER1_EL0(9), 2915 AMU_AMEVTYPER1_EL0(10), 2916 AMU_AMEVTYPER1_EL0(11), 2917 AMU_AMEVTYPER1_EL0(12), 2918 AMU_AMEVTYPER1_EL0(13), 2919 AMU_AMEVTYPER1_EL0(14), 2920 AMU_AMEVTYPER1_EL0(15), 2921 2922 { SYS_DESC(SYS_CNTPCT_EL0), access_arch_timer }, 2923 { SYS_DESC(SYS_CNTPCTSS_EL0), access_arch_timer }, 2924 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer }, 2925 { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer }, 2926 { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer }, 2927 2928 /* PMEVCNTRn_EL0 */ 2929 PMU_PMEVCNTR_EL0(0), 2930 PMU_PMEVCNTR_EL0(1), 2931 PMU_PMEVCNTR_EL0(2), 2932 PMU_PMEVCNTR_EL0(3), 2933 PMU_PMEVCNTR_EL0(4), 2934 PMU_PMEVCNTR_EL0(5), 2935 PMU_PMEVCNTR_EL0(6), 2936 PMU_PMEVCNTR_EL0(7), 2937 PMU_PMEVCNTR_EL0(8), 2938 PMU_PMEVCNTR_EL0(9), 2939 PMU_PMEVCNTR_EL0(10), 2940 PMU_PMEVCNTR_EL0(11), 2941 PMU_PMEVCNTR_EL0(12), 2942 PMU_PMEVCNTR_EL0(13), 2943 PMU_PMEVCNTR_EL0(14), 2944 PMU_PMEVCNTR_EL0(15), 2945 PMU_PMEVCNTR_EL0(16), 2946 PMU_PMEVCNTR_EL0(17), 2947 PMU_PMEVCNTR_EL0(18), 2948 PMU_PMEVCNTR_EL0(19), 2949 PMU_PMEVCNTR_EL0(20), 2950 PMU_PMEVCNTR_EL0(21), 2951 PMU_PMEVCNTR_EL0(22), 2952 PMU_PMEVCNTR_EL0(23), 2953 PMU_PMEVCNTR_EL0(24), 2954 PMU_PMEVCNTR_EL0(25), 2955 PMU_PMEVCNTR_EL0(26), 2956 PMU_PMEVCNTR_EL0(27), 2957 PMU_PMEVCNTR_EL0(28), 2958 PMU_PMEVCNTR_EL0(29), 2959 PMU_PMEVCNTR_EL0(30), 2960 /* PMEVTYPERn_EL0 */ 2961 PMU_PMEVTYPER_EL0(0), 2962 PMU_PMEVTYPER_EL0(1), 2963 PMU_PMEVTYPER_EL0(2), 2964 PMU_PMEVTYPER_EL0(3), 2965 PMU_PMEVTYPER_EL0(4), 2966 PMU_PMEVTYPER_EL0(5), 2967 PMU_PMEVTYPER_EL0(6), 2968 PMU_PMEVTYPER_EL0(7), 2969 PMU_PMEVTYPER_EL0(8), 2970 PMU_PMEVTYPER_EL0(9), 2971 PMU_PMEVTYPER_EL0(10), 2972 PMU_PMEVTYPER_EL0(11), 2973 PMU_PMEVTYPER_EL0(12), 2974 PMU_PMEVTYPER_EL0(13), 2975 PMU_PMEVTYPER_EL0(14), 2976 PMU_PMEVTYPER_EL0(15), 2977 PMU_PMEVTYPER_EL0(16), 2978 PMU_PMEVTYPER_EL0(17), 2979 PMU_PMEVTYPER_EL0(18), 2980 PMU_PMEVTYPER_EL0(19), 2981 PMU_PMEVTYPER_EL0(20), 2982 PMU_PMEVTYPER_EL0(21), 2983 PMU_PMEVTYPER_EL0(22), 2984 PMU_PMEVTYPER_EL0(23), 2985 PMU_PMEVTYPER_EL0(24), 2986 PMU_PMEVTYPER_EL0(25), 2987 PMU_PMEVTYPER_EL0(26), 2988 PMU_PMEVTYPER_EL0(27), 2989 PMU_PMEVTYPER_EL0(28), 2990 PMU_PMEVTYPER_EL0(29), 2991 PMU_PMEVTYPER_EL0(30), 2992 /* 2993 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero 2994 * in 32bit mode. Here we choose to reset it as zero for consistency. 2995 */ 2996 { PMU_SYS_REG(PMCCFILTR_EL0), .access = access_pmu_evtyper, 2997 .reset = reset_val, .reg = PMCCFILTR_EL0, .val = 0 }, 2998 2999 EL2_REG_VNCR(VPIDR_EL2, reset_unknown, 0), 3000 EL2_REG_VNCR(VMPIDR_EL2, reset_unknown, 0), 3001 EL2_REG(SCTLR_EL2, access_rw, reset_val, SCTLR_EL2_RES1), 3002 EL2_REG(ACTLR_EL2, access_rw, reset_val, 0), 3003 EL2_REG_VNCR(HCR_EL2, reset_hcr, 0), 3004 EL2_REG(MDCR_EL2, access_mdcr, reset_val, 0), 3005 EL2_REG(CPTR_EL2, access_rw, reset_val, CPTR_NVHE_EL2_RES1), 3006 EL2_REG_VNCR(HSTR_EL2, reset_val, 0), 3007 EL2_REG_VNCR(HFGRTR_EL2, reset_val, 0), 3008 EL2_REG_VNCR(HFGWTR_EL2, reset_val, 0), 3009 EL2_REG_VNCR(HFGITR_EL2, reset_val, 0), 3010 EL2_REG_VNCR(HACR_EL2, reset_val, 0), 3011 3012 EL2_REG_FILTERED(ZCR_EL2, access_zcr_el2, reset_val, 0, 3013 sve_el2_visibility), 3014 3015 EL2_REG_VNCR(HCRX_EL2, reset_val, 0), 3016 3017 EL2_REG(TTBR0_EL2, access_rw, reset_val, 0), 3018 EL2_REG(TTBR1_EL2, access_rw, reset_val, 0), 3019 EL2_REG(TCR_EL2, access_rw, reset_val, TCR_EL2_RES1), 3020 EL2_REG_FILTERED(TCR2_EL2, access_rw, reset_val, TCR2_EL2_RES1, 3021 tcr2_el2_visibility), 3022 EL2_REG_VNCR(VTTBR_EL2, reset_val, 0), 3023 EL2_REG_VNCR(VTCR_EL2, reset_val, 0), 3024 3025 { SYS_DESC(SYS_DACR32_EL2), undef_access, reset_unknown, DACR32_EL2 }, 3026 EL2_REG_VNCR(HDFGRTR_EL2, reset_val, 0), 3027 EL2_REG_VNCR(HDFGWTR_EL2, reset_val, 0), 3028 EL2_REG_VNCR(HAFGRTR_EL2, reset_val, 0), 3029 EL2_REG_REDIR(SPSR_EL2, reset_val, 0), 3030 EL2_REG_REDIR(ELR_EL2, reset_val, 0), 3031 { SYS_DESC(SYS_SP_EL1), access_sp_el1}, 3032 3033 /* AArch32 SPSR_* are RES0 if trapped from a NV guest */ 3034 { SYS_DESC(SYS_SPSR_irq), .access = trap_raz_wi }, 3035 { SYS_DESC(SYS_SPSR_abt), .access = trap_raz_wi }, 3036 { SYS_DESC(SYS_SPSR_und), .access = trap_raz_wi }, 3037 { SYS_DESC(SYS_SPSR_fiq), .access = trap_raz_wi }, 3038 3039 { SYS_DESC(SYS_IFSR32_EL2), undef_access, reset_unknown, IFSR32_EL2 }, 3040 EL2_REG(AFSR0_EL2, access_rw, reset_val, 0), 3041 EL2_REG(AFSR1_EL2, access_rw, reset_val, 0), 3042 EL2_REG_REDIR(ESR_EL2, reset_val, 0), 3043 { SYS_DESC(SYS_FPEXC32_EL2), undef_access, reset_val, FPEXC32_EL2, 0x700 }, 3044 3045 EL2_REG_REDIR(FAR_EL2, reset_val, 0), 3046 EL2_REG(HPFAR_EL2, access_rw, reset_val, 0), 3047 3048 EL2_REG(MAIR_EL2, access_rw, reset_val, 0), 3049 EL2_REG_FILTERED(PIRE0_EL2, access_rw, reset_val, 0, 3050 s1pie_el2_visibility), 3051 EL2_REG_FILTERED(PIR_EL2, access_rw, reset_val, 0, 3052 s1pie_el2_visibility), 3053 EL2_REG_FILTERED(POR_EL2, access_rw, reset_val, 0, 3054 s1poe_el2_visibility), 3055 EL2_REG(AMAIR_EL2, access_rw, reset_val, 0), 3056 { SYS_DESC(SYS_MPAMHCR_EL2), undef_access }, 3057 { SYS_DESC(SYS_MPAMVPMV_EL2), undef_access }, 3058 { SYS_DESC(SYS_MPAM2_EL2), undef_access }, 3059 { SYS_DESC(SYS_MPAMVPM0_EL2), undef_access }, 3060 { SYS_DESC(SYS_MPAMVPM1_EL2), undef_access }, 3061 { SYS_DESC(SYS_MPAMVPM2_EL2), undef_access }, 3062 { SYS_DESC(SYS_MPAMVPM3_EL2), undef_access }, 3063 { SYS_DESC(SYS_MPAMVPM4_EL2), undef_access }, 3064 { SYS_DESC(SYS_MPAMVPM5_EL2), undef_access }, 3065 { SYS_DESC(SYS_MPAMVPM6_EL2), undef_access }, 3066 { SYS_DESC(SYS_MPAMVPM7_EL2), undef_access }, 3067 3068 EL2_REG(VBAR_EL2, access_rw, reset_val, 0), 3069 EL2_REG(RVBAR_EL2, access_rw, reset_val, 0), 3070 { SYS_DESC(SYS_RMR_EL2), undef_access }, 3071 3072 EL2_REG_VNCR(ICH_HCR_EL2, reset_val, 0), 3073 3074 EL2_REG(CONTEXTIDR_EL2, access_rw, reset_val, 0), 3075 EL2_REG(TPIDR_EL2, access_rw, reset_val, 0), 3076 3077 EL2_REG_VNCR(CNTVOFF_EL2, reset_val, 0), 3078 EL2_REG(CNTHCTL_EL2, access_rw, reset_val, 0), 3079 3080 { SYS_DESC(SYS_CNTKCTL_EL12), access_cntkctl_el12 }, 3081 3082 EL2_REG(SP_EL2, NULL, reset_unknown, 0), 3083 }; 3084 3085 static bool handle_at_s1e01(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3086 const struct sys_reg_desc *r) 3087 { 3088 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3089 3090 __kvm_at_s1e01(vcpu, op, p->regval); 3091 3092 return true; 3093 } 3094 3095 static bool handle_at_s1e2(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3096 const struct sys_reg_desc *r) 3097 { 3098 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3099 3100 /* There is no FGT associated with AT S1E2A :-( */ 3101 if (op == OP_AT_S1E2A && 3102 !kvm_has_feat(vcpu->kvm, ID_AA64ISAR2_EL1, ATS1A, IMP)) { 3103 kvm_inject_undefined(vcpu); 3104 return false; 3105 } 3106 3107 __kvm_at_s1e2(vcpu, op, p->regval); 3108 3109 return true; 3110 } 3111 3112 static bool handle_at_s12(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3113 const struct sys_reg_desc *r) 3114 { 3115 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3116 3117 __kvm_at_s12(vcpu, op, p->regval); 3118 3119 return true; 3120 } 3121 3122 static bool kvm_supported_tlbi_s12_op(struct kvm_vcpu *vpcu, u32 instr) 3123 { 3124 struct kvm *kvm = vpcu->kvm; 3125 u8 CRm = sys_reg_CRm(instr); 3126 3127 if (sys_reg_CRn(instr) == TLBI_CRn_nXS && 3128 !kvm_has_feat(kvm, ID_AA64ISAR1_EL1, XS, IMP)) 3129 return false; 3130 3131 if (CRm == TLBI_CRm_nROS && 3132 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 3133 return false; 3134 3135 return true; 3136 } 3137 3138 static bool handle_alle1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3139 const struct sys_reg_desc *r) 3140 { 3141 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3142 3143 if (!kvm_supported_tlbi_s12_op(vcpu, sys_encoding)) 3144 return undef_access(vcpu, p, r); 3145 3146 write_lock(&vcpu->kvm->mmu_lock); 3147 3148 /* 3149 * Drop all shadow S2s, resulting in S1/S2 TLBIs for each of the 3150 * corresponding VMIDs. 3151 */ 3152 kvm_nested_s2_unmap(vcpu->kvm, true); 3153 3154 write_unlock(&vcpu->kvm->mmu_lock); 3155 3156 return true; 3157 } 3158 3159 static bool kvm_supported_tlbi_ipas2_op(struct kvm_vcpu *vpcu, u32 instr) 3160 { 3161 struct kvm *kvm = vpcu->kvm; 3162 u8 CRm = sys_reg_CRm(instr); 3163 u8 Op2 = sys_reg_Op2(instr); 3164 3165 if (sys_reg_CRn(instr) == TLBI_CRn_nXS && 3166 !kvm_has_feat(kvm, ID_AA64ISAR1_EL1, XS, IMP)) 3167 return false; 3168 3169 if (CRm == TLBI_CRm_IPAIS && (Op2 == 2 || Op2 == 6) && 3170 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE)) 3171 return false; 3172 3173 if (CRm == TLBI_CRm_IPAONS && (Op2 == 0 || Op2 == 4) && 3174 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 3175 return false; 3176 3177 if (CRm == TLBI_CRm_IPAONS && (Op2 == 3 || Op2 == 7) && 3178 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE)) 3179 return false; 3180 3181 return true; 3182 } 3183 3184 /* Only defined here as this is an internal "abstraction" */ 3185 union tlbi_info { 3186 struct { 3187 u64 start; 3188 u64 size; 3189 } range; 3190 3191 struct { 3192 u64 addr; 3193 } ipa; 3194 3195 struct { 3196 u64 addr; 3197 u32 encoding; 3198 } va; 3199 }; 3200 3201 static void s2_mmu_unmap_range(struct kvm_s2_mmu *mmu, 3202 const union tlbi_info *info) 3203 { 3204 /* 3205 * The unmap operation is allowed to drop the MMU lock and block, which 3206 * means that @mmu could be used for a different context than the one 3207 * currently being invalidated. 3208 * 3209 * This behavior is still safe, as: 3210 * 3211 * 1) The vCPU(s) that recycled the MMU are responsible for invalidating 3212 * the entire MMU before reusing it, which still honors the intent 3213 * of a TLBI. 3214 * 3215 * 2) Until the guest TLBI instruction is 'retired' (i.e. increment PC 3216 * and ERET to the guest), other vCPUs are allowed to use stale 3217 * translations. 3218 * 3219 * 3) Accidentally unmapping an unrelated MMU context is nonfatal, and 3220 * at worst may cause more aborts for shadow stage-2 fills. 3221 * 3222 * Dropping the MMU lock also implies that shadow stage-2 fills could 3223 * happen behind the back of the TLBI. This is still safe, though, as 3224 * the L1 needs to put its stage-2 in a consistent state before doing 3225 * the TLBI. 3226 */ 3227 kvm_stage2_unmap_range(mmu, info->range.start, info->range.size, true); 3228 } 3229 3230 static bool handle_vmalls12e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3231 const struct sys_reg_desc *r) 3232 { 3233 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3234 u64 limit, vttbr; 3235 3236 if (!kvm_supported_tlbi_s12_op(vcpu, sys_encoding)) 3237 return undef_access(vcpu, p, r); 3238 3239 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 3240 limit = BIT_ULL(kvm_get_pa_bits(vcpu->kvm)); 3241 3242 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 3243 &(union tlbi_info) { 3244 .range = { 3245 .start = 0, 3246 .size = limit, 3247 }, 3248 }, 3249 s2_mmu_unmap_range); 3250 3251 return true; 3252 } 3253 3254 static bool handle_ripas2e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3255 const struct sys_reg_desc *r) 3256 { 3257 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3258 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 3259 u64 base, range, tg, num, scale; 3260 int shift; 3261 3262 if (!kvm_supported_tlbi_ipas2_op(vcpu, sys_encoding)) 3263 return undef_access(vcpu, p, r); 3264 3265 /* 3266 * Because the shadow S2 structure doesn't necessarily reflect that 3267 * of the guest's S2 (different base granule size, for example), we 3268 * decide to ignore TTL and only use the described range. 3269 */ 3270 tg = FIELD_GET(GENMASK(47, 46), p->regval); 3271 scale = FIELD_GET(GENMASK(45, 44), p->regval); 3272 num = FIELD_GET(GENMASK(43, 39), p->regval); 3273 base = p->regval & GENMASK(36, 0); 3274 3275 switch(tg) { 3276 case 1: 3277 shift = 12; 3278 break; 3279 case 2: 3280 shift = 14; 3281 break; 3282 case 3: 3283 default: /* IMPDEF: handle tg==0 as 64k */ 3284 shift = 16; 3285 break; 3286 } 3287 3288 base <<= shift; 3289 range = __TLBI_RANGE_PAGES(num, scale) << shift; 3290 3291 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 3292 &(union tlbi_info) { 3293 .range = { 3294 .start = base, 3295 .size = range, 3296 }, 3297 }, 3298 s2_mmu_unmap_range); 3299 3300 return true; 3301 } 3302 3303 static void s2_mmu_unmap_ipa(struct kvm_s2_mmu *mmu, 3304 const union tlbi_info *info) 3305 { 3306 unsigned long max_size; 3307 u64 base_addr; 3308 3309 /* 3310 * We drop a number of things from the supplied value: 3311 * 3312 * - NS bit: we're non-secure only. 3313 * 3314 * - IPA[51:48]: We don't support 52bit IPA just yet... 3315 * 3316 * And of course, adjust the IPA to be on an actual address. 3317 */ 3318 base_addr = (info->ipa.addr & GENMASK_ULL(35, 0)) << 12; 3319 max_size = compute_tlb_inval_range(mmu, info->ipa.addr); 3320 base_addr &= ~(max_size - 1); 3321 3322 /* 3323 * See comment in s2_mmu_unmap_range() for why this is allowed to 3324 * reschedule. 3325 */ 3326 kvm_stage2_unmap_range(mmu, base_addr, max_size, true); 3327 } 3328 3329 static bool handle_ipas2e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3330 const struct sys_reg_desc *r) 3331 { 3332 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3333 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 3334 3335 if (!kvm_supported_tlbi_ipas2_op(vcpu, sys_encoding)) 3336 return undef_access(vcpu, p, r); 3337 3338 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 3339 &(union tlbi_info) { 3340 .ipa = { 3341 .addr = p->regval, 3342 }, 3343 }, 3344 s2_mmu_unmap_ipa); 3345 3346 return true; 3347 } 3348 3349 static void s2_mmu_tlbi_s1e1(struct kvm_s2_mmu *mmu, 3350 const union tlbi_info *info) 3351 { 3352 WARN_ON(__kvm_tlbi_s1e2(mmu, info->va.addr, info->va.encoding)); 3353 } 3354 3355 static bool handle_tlbi_el1(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3356 const struct sys_reg_desc *r) 3357 { 3358 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3359 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 3360 3361 /* 3362 * If we're here, this is because we've trapped on a EL1 TLBI 3363 * instruction that affects the EL1 translation regime while 3364 * we're running in a context that doesn't allow us to let the 3365 * HW do its thing (aka vEL2): 3366 * 3367 * - HCR_EL2.E2H == 0 : a non-VHE guest 3368 * - HCR_EL2.{E2H,TGE} == { 1, 0 } : a VHE guest in guest mode 3369 * 3370 * We don't expect these helpers to ever be called when running 3371 * in a vEL1 context. 3372 */ 3373 3374 WARN_ON(!vcpu_is_el2(vcpu)); 3375 3376 if (!kvm_supported_tlbi_s1e1_op(vcpu, sys_encoding)) 3377 return undef_access(vcpu, p, r); 3378 3379 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 3380 &(union tlbi_info) { 3381 .va = { 3382 .addr = p->regval, 3383 .encoding = sys_encoding, 3384 }, 3385 }, 3386 s2_mmu_tlbi_s1e1); 3387 3388 return true; 3389 } 3390 3391 #define SYS_INSN(insn, access_fn) \ 3392 { \ 3393 SYS_DESC(OP_##insn), \ 3394 .access = (access_fn), \ 3395 } 3396 3397 static struct sys_reg_desc sys_insn_descs[] = { 3398 { SYS_DESC(SYS_DC_ISW), access_dcsw }, 3399 { SYS_DESC(SYS_DC_IGSW), access_dcgsw }, 3400 { SYS_DESC(SYS_DC_IGDSW), access_dcgsw }, 3401 3402 SYS_INSN(AT_S1E1R, handle_at_s1e01), 3403 SYS_INSN(AT_S1E1W, handle_at_s1e01), 3404 SYS_INSN(AT_S1E0R, handle_at_s1e01), 3405 SYS_INSN(AT_S1E0W, handle_at_s1e01), 3406 SYS_INSN(AT_S1E1RP, handle_at_s1e01), 3407 SYS_INSN(AT_S1E1WP, handle_at_s1e01), 3408 3409 { SYS_DESC(SYS_DC_CSW), access_dcsw }, 3410 { SYS_DESC(SYS_DC_CGSW), access_dcgsw }, 3411 { SYS_DESC(SYS_DC_CGDSW), access_dcgsw }, 3412 { SYS_DESC(SYS_DC_CISW), access_dcsw }, 3413 { SYS_DESC(SYS_DC_CIGSW), access_dcgsw }, 3414 { SYS_DESC(SYS_DC_CIGDSW), access_dcgsw }, 3415 3416 SYS_INSN(TLBI_VMALLE1OS, handle_tlbi_el1), 3417 SYS_INSN(TLBI_VAE1OS, handle_tlbi_el1), 3418 SYS_INSN(TLBI_ASIDE1OS, handle_tlbi_el1), 3419 SYS_INSN(TLBI_VAAE1OS, handle_tlbi_el1), 3420 SYS_INSN(TLBI_VALE1OS, handle_tlbi_el1), 3421 SYS_INSN(TLBI_VAALE1OS, handle_tlbi_el1), 3422 3423 SYS_INSN(TLBI_RVAE1IS, handle_tlbi_el1), 3424 SYS_INSN(TLBI_RVAAE1IS, handle_tlbi_el1), 3425 SYS_INSN(TLBI_RVALE1IS, handle_tlbi_el1), 3426 SYS_INSN(TLBI_RVAALE1IS, handle_tlbi_el1), 3427 3428 SYS_INSN(TLBI_VMALLE1IS, handle_tlbi_el1), 3429 SYS_INSN(TLBI_VAE1IS, handle_tlbi_el1), 3430 SYS_INSN(TLBI_ASIDE1IS, handle_tlbi_el1), 3431 SYS_INSN(TLBI_VAAE1IS, handle_tlbi_el1), 3432 SYS_INSN(TLBI_VALE1IS, handle_tlbi_el1), 3433 SYS_INSN(TLBI_VAALE1IS, handle_tlbi_el1), 3434 3435 SYS_INSN(TLBI_RVAE1OS, handle_tlbi_el1), 3436 SYS_INSN(TLBI_RVAAE1OS, handle_tlbi_el1), 3437 SYS_INSN(TLBI_RVALE1OS, handle_tlbi_el1), 3438 SYS_INSN(TLBI_RVAALE1OS, handle_tlbi_el1), 3439 3440 SYS_INSN(TLBI_RVAE1, handle_tlbi_el1), 3441 SYS_INSN(TLBI_RVAAE1, handle_tlbi_el1), 3442 SYS_INSN(TLBI_RVALE1, handle_tlbi_el1), 3443 SYS_INSN(TLBI_RVAALE1, handle_tlbi_el1), 3444 3445 SYS_INSN(TLBI_VMALLE1, handle_tlbi_el1), 3446 SYS_INSN(TLBI_VAE1, handle_tlbi_el1), 3447 SYS_INSN(TLBI_ASIDE1, handle_tlbi_el1), 3448 SYS_INSN(TLBI_VAAE1, handle_tlbi_el1), 3449 SYS_INSN(TLBI_VALE1, handle_tlbi_el1), 3450 SYS_INSN(TLBI_VAALE1, handle_tlbi_el1), 3451 3452 SYS_INSN(TLBI_VMALLE1OSNXS, handle_tlbi_el1), 3453 SYS_INSN(TLBI_VAE1OSNXS, handle_tlbi_el1), 3454 SYS_INSN(TLBI_ASIDE1OSNXS, handle_tlbi_el1), 3455 SYS_INSN(TLBI_VAAE1OSNXS, handle_tlbi_el1), 3456 SYS_INSN(TLBI_VALE1OSNXS, handle_tlbi_el1), 3457 SYS_INSN(TLBI_VAALE1OSNXS, handle_tlbi_el1), 3458 3459 SYS_INSN(TLBI_RVAE1ISNXS, handle_tlbi_el1), 3460 SYS_INSN(TLBI_RVAAE1ISNXS, handle_tlbi_el1), 3461 SYS_INSN(TLBI_RVALE1ISNXS, handle_tlbi_el1), 3462 SYS_INSN(TLBI_RVAALE1ISNXS, handle_tlbi_el1), 3463 3464 SYS_INSN(TLBI_VMALLE1ISNXS, handle_tlbi_el1), 3465 SYS_INSN(TLBI_VAE1ISNXS, handle_tlbi_el1), 3466 SYS_INSN(TLBI_ASIDE1ISNXS, handle_tlbi_el1), 3467 SYS_INSN(TLBI_VAAE1ISNXS, handle_tlbi_el1), 3468 SYS_INSN(TLBI_VALE1ISNXS, handle_tlbi_el1), 3469 SYS_INSN(TLBI_VAALE1ISNXS, handle_tlbi_el1), 3470 3471 SYS_INSN(TLBI_RVAE1OSNXS, handle_tlbi_el1), 3472 SYS_INSN(TLBI_RVAAE1OSNXS, handle_tlbi_el1), 3473 SYS_INSN(TLBI_RVALE1OSNXS, handle_tlbi_el1), 3474 SYS_INSN(TLBI_RVAALE1OSNXS, handle_tlbi_el1), 3475 3476 SYS_INSN(TLBI_RVAE1NXS, handle_tlbi_el1), 3477 SYS_INSN(TLBI_RVAAE1NXS, handle_tlbi_el1), 3478 SYS_INSN(TLBI_RVALE1NXS, handle_tlbi_el1), 3479 SYS_INSN(TLBI_RVAALE1NXS, handle_tlbi_el1), 3480 3481 SYS_INSN(TLBI_VMALLE1NXS, handle_tlbi_el1), 3482 SYS_INSN(TLBI_VAE1NXS, handle_tlbi_el1), 3483 SYS_INSN(TLBI_ASIDE1NXS, handle_tlbi_el1), 3484 SYS_INSN(TLBI_VAAE1NXS, handle_tlbi_el1), 3485 SYS_INSN(TLBI_VALE1NXS, handle_tlbi_el1), 3486 SYS_INSN(TLBI_VAALE1NXS, handle_tlbi_el1), 3487 3488 SYS_INSN(AT_S1E2R, handle_at_s1e2), 3489 SYS_INSN(AT_S1E2W, handle_at_s1e2), 3490 SYS_INSN(AT_S12E1R, handle_at_s12), 3491 SYS_INSN(AT_S12E1W, handle_at_s12), 3492 SYS_INSN(AT_S12E0R, handle_at_s12), 3493 SYS_INSN(AT_S12E0W, handle_at_s12), 3494 SYS_INSN(AT_S1E2A, handle_at_s1e2), 3495 3496 SYS_INSN(TLBI_IPAS2E1IS, handle_ipas2e1is), 3497 SYS_INSN(TLBI_RIPAS2E1IS, handle_ripas2e1is), 3498 SYS_INSN(TLBI_IPAS2LE1IS, handle_ipas2e1is), 3499 SYS_INSN(TLBI_RIPAS2LE1IS, handle_ripas2e1is), 3500 3501 SYS_INSN(TLBI_ALLE2OS, undef_access), 3502 SYS_INSN(TLBI_VAE2OS, undef_access), 3503 SYS_INSN(TLBI_ALLE1OS, handle_alle1is), 3504 SYS_INSN(TLBI_VALE2OS, undef_access), 3505 SYS_INSN(TLBI_VMALLS12E1OS, handle_vmalls12e1is), 3506 3507 SYS_INSN(TLBI_RVAE2IS, undef_access), 3508 SYS_INSN(TLBI_RVALE2IS, undef_access), 3509 3510 SYS_INSN(TLBI_ALLE1IS, handle_alle1is), 3511 SYS_INSN(TLBI_VMALLS12E1IS, handle_vmalls12e1is), 3512 SYS_INSN(TLBI_IPAS2E1OS, handle_ipas2e1is), 3513 SYS_INSN(TLBI_IPAS2E1, handle_ipas2e1is), 3514 SYS_INSN(TLBI_RIPAS2E1, handle_ripas2e1is), 3515 SYS_INSN(TLBI_RIPAS2E1OS, handle_ripas2e1is), 3516 SYS_INSN(TLBI_IPAS2LE1OS, handle_ipas2e1is), 3517 SYS_INSN(TLBI_IPAS2LE1, handle_ipas2e1is), 3518 SYS_INSN(TLBI_RIPAS2LE1, handle_ripas2e1is), 3519 SYS_INSN(TLBI_RIPAS2LE1OS, handle_ripas2e1is), 3520 SYS_INSN(TLBI_RVAE2OS, undef_access), 3521 SYS_INSN(TLBI_RVALE2OS, undef_access), 3522 SYS_INSN(TLBI_RVAE2, undef_access), 3523 SYS_INSN(TLBI_RVALE2, undef_access), 3524 SYS_INSN(TLBI_ALLE1, handle_alle1is), 3525 SYS_INSN(TLBI_VMALLS12E1, handle_vmalls12e1is), 3526 3527 SYS_INSN(TLBI_IPAS2E1ISNXS, handle_ipas2e1is), 3528 SYS_INSN(TLBI_RIPAS2E1ISNXS, handle_ripas2e1is), 3529 SYS_INSN(TLBI_IPAS2LE1ISNXS, handle_ipas2e1is), 3530 SYS_INSN(TLBI_RIPAS2LE1ISNXS, handle_ripas2e1is), 3531 3532 SYS_INSN(TLBI_ALLE2OSNXS, undef_access), 3533 SYS_INSN(TLBI_VAE2OSNXS, undef_access), 3534 SYS_INSN(TLBI_ALLE1OSNXS, handle_alle1is), 3535 SYS_INSN(TLBI_VALE2OSNXS, undef_access), 3536 SYS_INSN(TLBI_VMALLS12E1OSNXS, handle_vmalls12e1is), 3537 3538 SYS_INSN(TLBI_RVAE2ISNXS, undef_access), 3539 SYS_INSN(TLBI_RVALE2ISNXS, undef_access), 3540 SYS_INSN(TLBI_ALLE2ISNXS, undef_access), 3541 SYS_INSN(TLBI_VAE2ISNXS, undef_access), 3542 3543 SYS_INSN(TLBI_ALLE1ISNXS, handle_alle1is), 3544 SYS_INSN(TLBI_VALE2ISNXS, undef_access), 3545 SYS_INSN(TLBI_VMALLS12E1ISNXS, handle_vmalls12e1is), 3546 SYS_INSN(TLBI_IPAS2E1OSNXS, handle_ipas2e1is), 3547 SYS_INSN(TLBI_IPAS2E1NXS, handle_ipas2e1is), 3548 SYS_INSN(TLBI_RIPAS2E1NXS, handle_ripas2e1is), 3549 SYS_INSN(TLBI_RIPAS2E1OSNXS, handle_ripas2e1is), 3550 SYS_INSN(TLBI_IPAS2LE1OSNXS, handle_ipas2e1is), 3551 SYS_INSN(TLBI_IPAS2LE1NXS, handle_ipas2e1is), 3552 SYS_INSN(TLBI_RIPAS2LE1NXS, handle_ripas2e1is), 3553 SYS_INSN(TLBI_RIPAS2LE1OSNXS, handle_ripas2e1is), 3554 SYS_INSN(TLBI_RVAE2OSNXS, undef_access), 3555 SYS_INSN(TLBI_RVALE2OSNXS, undef_access), 3556 SYS_INSN(TLBI_RVAE2NXS, undef_access), 3557 SYS_INSN(TLBI_RVALE2NXS, undef_access), 3558 SYS_INSN(TLBI_ALLE2NXS, undef_access), 3559 SYS_INSN(TLBI_VAE2NXS, undef_access), 3560 SYS_INSN(TLBI_ALLE1NXS, handle_alle1is), 3561 SYS_INSN(TLBI_VALE2NXS, undef_access), 3562 SYS_INSN(TLBI_VMALLS12E1NXS, handle_vmalls12e1is), 3563 }; 3564 3565 static bool trap_dbgdidr(struct kvm_vcpu *vcpu, 3566 struct sys_reg_params *p, 3567 const struct sys_reg_desc *r) 3568 { 3569 if (p->is_write) { 3570 return ignore_write(vcpu, p); 3571 } else { 3572 u64 dfr = kvm_read_vm_id_reg(vcpu->kvm, SYS_ID_AA64DFR0_EL1); 3573 u32 el3 = kvm_has_feat(vcpu->kvm, ID_AA64PFR0_EL1, EL3, IMP); 3574 3575 p->regval = ((SYS_FIELD_GET(ID_AA64DFR0_EL1, WRPs, dfr) << 28) | 3576 (SYS_FIELD_GET(ID_AA64DFR0_EL1, BRPs, dfr) << 24) | 3577 (SYS_FIELD_GET(ID_AA64DFR0_EL1, CTX_CMPs, dfr) << 20) | 3578 (SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, dfr) << 16) | 3579 (1 << 15) | (el3 << 14) | (el3 << 12)); 3580 return true; 3581 } 3582 } 3583 3584 /* 3585 * AArch32 debug register mappings 3586 * 3587 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0] 3588 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32] 3589 * 3590 * None of the other registers share their location, so treat them as 3591 * if they were 64bit. 3592 */ 3593 #define DBG_BCR_BVR_WCR_WVR(n) \ 3594 /* DBGBVRn */ \ 3595 { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \ 3596 /* DBGBCRn */ \ 3597 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \ 3598 /* DBGWVRn */ \ 3599 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \ 3600 /* DBGWCRn */ \ 3601 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n } 3602 3603 #define DBGBXVR(n) \ 3604 { AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_bvr, NULL, n } 3605 3606 /* 3607 * Trapped cp14 registers. We generally ignore most of the external 3608 * debug, on the principle that they don't really make sense to a 3609 * guest. Revisit this one day, would this principle change. 3610 */ 3611 static const struct sys_reg_desc cp14_regs[] = { 3612 /* DBGDIDR */ 3613 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgdidr }, 3614 /* DBGDTRRXext */ 3615 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi }, 3616 3617 DBG_BCR_BVR_WCR_WVR(0), 3618 /* DBGDSCRint */ 3619 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi }, 3620 DBG_BCR_BVR_WCR_WVR(1), 3621 /* DBGDCCINT */ 3622 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug_regs, NULL, MDCCINT_EL1 }, 3623 /* DBGDSCRext */ 3624 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug_regs, NULL, MDSCR_EL1 }, 3625 DBG_BCR_BVR_WCR_WVR(2), 3626 /* DBGDTR[RT]Xint */ 3627 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi }, 3628 /* DBGDTR[RT]Xext */ 3629 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi }, 3630 DBG_BCR_BVR_WCR_WVR(3), 3631 DBG_BCR_BVR_WCR_WVR(4), 3632 DBG_BCR_BVR_WCR_WVR(5), 3633 /* DBGWFAR */ 3634 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi }, 3635 /* DBGOSECCR */ 3636 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi }, 3637 DBG_BCR_BVR_WCR_WVR(6), 3638 /* DBGVCR */ 3639 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug_regs, NULL, DBGVCR32_EL2 }, 3640 DBG_BCR_BVR_WCR_WVR(7), 3641 DBG_BCR_BVR_WCR_WVR(8), 3642 DBG_BCR_BVR_WCR_WVR(9), 3643 DBG_BCR_BVR_WCR_WVR(10), 3644 DBG_BCR_BVR_WCR_WVR(11), 3645 DBG_BCR_BVR_WCR_WVR(12), 3646 DBG_BCR_BVR_WCR_WVR(13), 3647 DBG_BCR_BVR_WCR_WVR(14), 3648 DBG_BCR_BVR_WCR_WVR(15), 3649 3650 /* DBGDRAR (32bit) */ 3651 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi }, 3652 3653 DBGBXVR(0), 3654 /* DBGOSLAR */ 3655 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_oslar_el1 }, 3656 DBGBXVR(1), 3657 /* DBGOSLSR */ 3658 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1, NULL, OSLSR_EL1 }, 3659 DBGBXVR(2), 3660 DBGBXVR(3), 3661 /* DBGOSDLR */ 3662 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi }, 3663 DBGBXVR(4), 3664 /* DBGPRCR */ 3665 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi }, 3666 DBGBXVR(5), 3667 DBGBXVR(6), 3668 DBGBXVR(7), 3669 DBGBXVR(8), 3670 DBGBXVR(9), 3671 DBGBXVR(10), 3672 DBGBXVR(11), 3673 DBGBXVR(12), 3674 DBGBXVR(13), 3675 DBGBXVR(14), 3676 DBGBXVR(15), 3677 3678 /* DBGDSAR (32bit) */ 3679 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi }, 3680 3681 /* DBGDEVID2 */ 3682 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi }, 3683 /* DBGDEVID1 */ 3684 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi }, 3685 /* DBGDEVID */ 3686 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi }, 3687 /* DBGCLAIMSET */ 3688 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi }, 3689 /* DBGCLAIMCLR */ 3690 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi }, 3691 /* DBGAUTHSTATUS */ 3692 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 }, 3693 }; 3694 3695 /* Trapped cp14 64bit registers */ 3696 static const struct sys_reg_desc cp14_64_regs[] = { 3697 /* DBGDRAR (64bit) */ 3698 { Op1( 0), CRm( 1), .access = trap_raz_wi }, 3699 3700 /* DBGDSAR (64bit) */ 3701 { Op1( 0), CRm( 2), .access = trap_raz_wi }, 3702 }; 3703 3704 #define CP15_PMU_SYS_REG(_map, _Op1, _CRn, _CRm, _Op2) \ 3705 AA32(_map), \ 3706 Op1(_Op1), CRn(_CRn), CRm(_CRm), Op2(_Op2), \ 3707 .visibility = pmu_visibility 3708 3709 /* Macro to expand the PMEVCNTRn register */ 3710 #define PMU_PMEVCNTR(n) \ 3711 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \ 3712 (0b1000 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \ 3713 .access = access_pmu_evcntr } 3714 3715 /* Macro to expand the PMEVTYPERn register */ 3716 #define PMU_PMEVTYPER(n) \ 3717 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \ 3718 (0b1100 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \ 3719 .access = access_pmu_evtyper } 3720 /* 3721 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding, 3722 * depending on the way they are accessed (as a 32bit or a 64bit 3723 * register). 3724 */ 3725 static const struct sys_reg_desc cp15_regs[] = { 3726 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr }, 3727 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, SCTLR_EL1 }, 3728 /* ACTLR */ 3729 { AA32(LO), Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr, NULL, ACTLR_EL1 }, 3730 /* ACTLR2 */ 3731 { AA32(HI), Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr, NULL, ACTLR_EL1 }, 3732 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, 3733 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, TTBR1_EL1 }, 3734 /* TTBCR */ 3735 { AA32(LO), Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 }, 3736 /* TTBCR2 */ 3737 { AA32(HI), Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, TCR_EL1 }, 3738 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, DACR32_EL2 }, 3739 { CP15_SYS_DESC(SYS_ICC_PMR_EL1), undef_access }, 3740 /* DFSR */ 3741 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, ESR_EL1 }, 3742 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, IFSR32_EL2 }, 3743 /* ADFSR */ 3744 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, AFSR0_EL1 }, 3745 /* AIFSR */ 3746 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, AFSR1_EL1 }, 3747 /* DFAR */ 3748 { AA32(LO), Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, FAR_EL1 }, 3749 /* IFAR */ 3750 { AA32(HI), Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, FAR_EL1 }, 3751 3752 /* 3753 * DC{C,I,CI}SW operations: 3754 */ 3755 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw }, 3756 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw }, 3757 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw }, 3758 3759 /* PMU */ 3760 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 0), .access = access_pmcr }, 3761 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 1), .access = access_pmcnten }, 3762 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 2), .access = access_pmcnten }, 3763 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 3), .access = access_pmovs }, 3764 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 4), .access = access_pmswinc }, 3765 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 5), .access = access_pmselr }, 3766 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 6), .access = access_pmceid }, 3767 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 7), .access = access_pmceid }, 3768 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 0), .access = access_pmu_evcntr }, 3769 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 1), .access = access_pmu_evtyper }, 3770 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 2), .access = access_pmu_evcntr }, 3771 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 0), .access = access_pmuserenr }, 3772 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 1), .access = access_pminten }, 3773 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 2), .access = access_pminten }, 3774 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 3), .access = access_pmovs }, 3775 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 4), .access = access_pmceid }, 3776 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 5), .access = access_pmceid }, 3777 /* PMMIR */ 3778 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 6), .access = trap_raz_wi }, 3779 3780 /* PRRR/MAIR0 */ 3781 { AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 }, 3782 /* NMRR/MAIR1 */ 3783 { AA32(HI), Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, MAIR_EL1 }, 3784 /* AMAIR0 */ 3785 { AA32(LO), Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, AMAIR_EL1 }, 3786 /* AMAIR1 */ 3787 { AA32(HI), Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, AMAIR_EL1 }, 3788 3789 { CP15_SYS_DESC(SYS_ICC_IAR0_EL1), undef_access }, 3790 { CP15_SYS_DESC(SYS_ICC_EOIR0_EL1), undef_access }, 3791 { CP15_SYS_DESC(SYS_ICC_HPPIR0_EL1), undef_access }, 3792 { CP15_SYS_DESC(SYS_ICC_BPR0_EL1), undef_access }, 3793 { CP15_SYS_DESC(SYS_ICC_AP0R0_EL1), undef_access }, 3794 { CP15_SYS_DESC(SYS_ICC_AP0R1_EL1), undef_access }, 3795 { CP15_SYS_DESC(SYS_ICC_AP0R2_EL1), undef_access }, 3796 { CP15_SYS_DESC(SYS_ICC_AP0R3_EL1), undef_access }, 3797 { CP15_SYS_DESC(SYS_ICC_AP1R0_EL1), undef_access }, 3798 { CP15_SYS_DESC(SYS_ICC_AP1R1_EL1), undef_access }, 3799 { CP15_SYS_DESC(SYS_ICC_AP1R2_EL1), undef_access }, 3800 { CP15_SYS_DESC(SYS_ICC_AP1R3_EL1), undef_access }, 3801 { CP15_SYS_DESC(SYS_ICC_DIR_EL1), undef_access }, 3802 { CP15_SYS_DESC(SYS_ICC_RPR_EL1), undef_access }, 3803 { CP15_SYS_DESC(SYS_ICC_IAR1_EL1), undef_access }, 3804 { CP15_SYS_DESC(SYS_ICC_EOIR1_EL1), undef_access }, 3805 { CP15_SYS_DESC(SYS_ICC_HPPIR1_EL1), undef_access }, 3806 { CP15_SYS_DESC(SYS_ICC_BPR1_EL1), undef_access }, 3807 { CP15_SYS_DESC(SYS_ICC_CTLR_EL1), undef_access }, 3808 { CP15_SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre }, 3809 { CP15_SYS_DESC(SYS_ICC_IGRPEN0_EL1), undef_access }, 3810 { CP15_SYS_DESC(SYS_ICC_IGRPEN1_EL1), undef_access }, 3811 3812 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, CONTEXTIDR_EL1 }, 3813 3814 /* Arch Tmers */ 3815 { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer }, 3816 { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer }, 3817 3818 /* PMEVCNTRn */ 3819 PMU_PMEVCNTR(0), 3820 PMU_PMEVCNTR(1), 3821 PMU_PMEVCNTR(2), 3822 PMU_PMEVCNTR(3), 3823 PMU_PMEVCNTR(4), 3824 PMU_PMEVCNTR(5), 3825 PMU_PMEVCNTR(6), 3826 PMU_PMEVCNTR(7), 3827 PMU_PMEVCNTR(8), 3828 PMU_PMEVCNTR(9), 3829 PMU_PMEVCNTR(10), 3830 PMU_PMEVCNTR(11), 3831 PMU_PMEVCNTR(12), 3832 PMU_PMEVCNTR(13), 3833 PMU_PMEVCNTR(14), 3834 PMU_PMEVCNTR(15), 3835 PMU_PMEVCNTR(16), 3836 PMU_PMEVCNTR(17), 3837 PMU_PMEVCNTR(18), 3838 PMU_PMEVCNTR(19), 3839 PMU_PMEVCNTR(20), 3840 PMU_PMEVCNTR(21), 3841 PMU_PMEVCNTR(22), 3842 PMU_PMEVCNTR(23), 3843 PMU_PMEVCNTR(24), 3844 PMU_PMEVCNTR(25), 3845 PMU_PMEVCNTR(26), 3846 PMU_PMEVCNTR(27), 3847 PMU_PMEVCNTR(28), 3848 PMU_PMEVCNTR(29), 3849 PMU_PMEVCNTR(30), 3850 /* PMEVTYPERn */ 3851 PMU_PMEVTYPER(0), 3852 PMU_PMEVTYPER(1), 3853 PMU_PMEVTYPER(2), 3854 PMU_PMEVTYPER(3), 3855 PMU_PMEVTYPER(4), 3856 PMU_PMEVTYPER(5), 3857 PMU_PMEVTYPER(6), 3858 PMU_PMEVTYPER(7), 3859 PMU_PMEVTYPER(8), 3860 PMU_PMEVTYPER(9), 3861 PMU_PMEVTYPER(10), 3862 PMU_PMEVTYPER(11), 3863 PMU_PMEVTYPER(12), 3864 PMU_PMEVTYPER(13), 3865 PMU_PMEVTYPER(14), 3866 PMU_PMEVTYPER(15), 3867 PMU_PMEVTYPER(16), 3868 PMU_PMEVTYPER(17), 3869 PMU_PMEVTYPER(18), 3870 PMU_PMEVTYPER(19), 3871 PMU_PMEVTYPER(20), 3872 PMU_PMEVTYPER(21), 3873 PMU_PMEVTYPER(22), 3874 PMU_PMEVTYPER(23), 3875 PMU_PMEVTYPER(24), 3876 PMU_PMEVTYPER(25), 3877 PMU_PMEVTYPER(26), 3878 PMU_PMEVTYPER(27), 3879 PMU_PMEVTYPER(28), 3880 PMU_PMEVTYPER(29), 3881 PMU_PMEVTYPER(30), 3882 /* PMCCFILTR */ 3883 { CP15_PMU_SYS_REG(DIRECT, 0, 14, 15, 7), .access = access_pmu_evtyper }, 3884 3885 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr }, 3886 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr }, 3887 3888 /* CCSIDR2 */ 3889 { Op1(1), CRn( 0), CRm( 0), Op2(2), undef_access }, 3890 3891 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 }, 3892 }; 3893 3894 static const struct sys_reg_desc cp15_64_regs[] = { 3895 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, 3896 { CP15_PMU_SYS_REG(DIRECT, 0, 0, 9, 0), .access = access_pmu_evcntr }, 3897 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */ 3898 { SYS_DESC(SYS_AARCH32_CNTPCT), access_arch_timer }, 3899 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 }, 3900 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */ 3901 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */ 3902 { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer }, 3903 { SYS_DESC(SYS_AARCH32_CNTPCTSS), access_arch_timer }, 3904 }; 3905 3906 static bool check_sysreg_table(const struct sys_reg_desc *table, unsigned int n, 3907 bool is_32) 3908 { 3909 unsigned int i; 3910 3911 for (i = 0; i < n; i++) { 3912 if (!is_32 && table[i].reg && !table[i].reset) { 3913 kvm_err("sys_reg table %pS entry %d (%s) lacks reset\n", 3914 &table[i], i, table[i].name); 3915 return false; 3916 } 3917 3918 if (i && cmp_sys_reg(&table[i-1], &table[i]) >= 0) { 3919 kvm_err("sys_reg table %pS entry %d (%s -> %s) out of order\n", 3920 &table[i], i, table[i - 1].name, table[i].name); 3921 return false; 3922 } 3923 } 3924 3925 return true; 3926 } 3927 3928 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu) 3929 { 3930 kvm_inject_undefined(vcpu); 3931 return 1; 3932 } 3933 3934 static void perform_access(struct kvm_vcpu *vcpu, 3935 struct sys_reg_params *params, 3936 const struct sys_reg_desc *r) 3937 { 3938 trace_kvm_sys_access(*vcpu_pc(vcpu), params, r); 3939 3940 /* Check for regs disabled by runtime config */ 3941 if (sysreg_hidden(vcpu, r)) { 3942 kvm_inject_undefined(vcpu); 3943 return; 3944 } 3945 3946 /* 3947 * Not having an accessor means that we have configured a trap 3948 * that we don't know how to handle. This certainly qualifies 3949 * as a gross bug that should be fixed right away. 3950 */ 3951 BUG_ON(!r->access); 3952 3953 /* Skip instruction if instructed so */ 3954 if (likely(r->access(vcpu, params, r))) 3955 kvm_incr_pc(vcpu); 3956 } 3957 3958 /* 3959 * emulate_cp -- tries to match a sys_reg access in a handling table, and 3960 * call the corresponding trap handler. 3961 * 3962 * @params: pointer to the descriptor of the access 3963 * @table: array of trap descriptors 3964 * @num: size of the trap descriptor array 3965 * 3966 * Return true if the access has been handled, false if not. 3967 */ 3968 static bool emulate_cp(struct kvm_vcpu *vcpu, 3969 struct sys_reg_params *params, 3970 const struct sys_reg_desc *table, 3971 size_t num) 3972 { 3973 const struct sys_reg_desc *r; 3974 3975 if (!table) 3976 return false; /* Not handled */ 3977 3978 r = find_reg(params, table, num); 3979 3980 if (r) { 3981 perform_access(vcpu, params, r); 3982 return true; 3983 } 3984 3985 /* Not handled */ 3986 return false; 3987 } 3988 3989 static void unhandled_cp_access(struct kvm_vcpu *vcpu, 3990 struct sys_reg_params *params) 3991 { 3992 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu); 3993 int cp = -1; 3994 3995 switch (esr_ec) { 3996 case ESR_ELx_EC_CP15_32: 3997 case ESR_ELx_EC_CP15_64: 3998 cp = 15; 3999 break; 4000 case ESR_ELx_EC_CP14_MR: 4001 case ESR_ELx_EC_CP14_64: 4002 cp = 14; 4003 break; 4004 default: 4005 WARN_ON(1); 4006 } 4007 4008 print_sys_reg_msg(params, 4009 "Unsupported guest CP%d access at: %08lx [%08lx]\n", 4010 cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 4011 kvm_inject_undefined(vcpu); 4012 } 4013 4014 /** 4015 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access 4016 * @vcpu: The VCPU pointer 4017 * @global: &struct sys_reg_desc 4018 * @nr_global: size of the @global array 4019 */ 4020 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu, 4021 const struct sys_reg_desc *global, 4022 size_t nr_global) 4023 { 4024 struct sys_reg_params params; 4025 u64 esr = kvm_vcpu_get_esr(vcpu); 4026 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4027 int Rt2 = (esr >> 10) & 0x1f; 4028 4029 params.CRm = (esr >> 1) & 0xf; 4030 params.is_write = ((esr & 1) == 0); 4031 4032 params.Op0 = 0; 4033 params.Op1 = (esr >> 16) & 0xf; 4034 params.Op2 = 0; 4035 params.CRn = 0; 4036 4037 /* 4038 * Make a 64-bit value out of Rt and Rt2. As we use the same trap 4039 * backends between AArch32 and AArch64, we get away with it. 4040 */ 4041 if (params.is_write) { 4042 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff; 4043 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32; 4044 } 4045 4046 /* 4047 * If the table contains a handler, handle the 4048 * potential register operation in the case of a read and return 4049 * with success. 4050 */ 4051 if (emulate_cp(vcpu, ¶ms, global, nr_global)) { 4052 /* Split up the value between registers for the read side */ 4053 if (!params.is_write) { 4054 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval)); 4055 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval)); 4056 } 4057 4058 return 1; 4059 } 4060 4061 unhandled_cp_access(vcpu, ¶ms); 4062 return 1; 4063 } 4064 4065 static bool emulate_sys_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *params); 4066 4067 /* 4068 * The CP10 ID registers are architecturally mapped to AArch64 feature 4069 * registers. Abuse that fact so we can rely on the AArch64 handler for accesses 4070 * from AArch32. 4071 */ 4072 static bool kvm_esr_cp10_id_to_sys64(u64 esr, struct sys_reg_params *params) 4073 { 4074 u8 reg_id = (esr >> 10) & 0xf; 4075 bool valid; 4076 4077 params->is_write = ((esr & 1) == 0); 4078 params->Op0 = 3; 4079 params->Op1 = 0; 4080 params->CRn = 0; 4081 params->CRm = 3; 4082 4083 /* CP10 ID registers are read-only */ 4084 valid = !params->is_write; 4085 4086 switch (reg_id) { 4087 /* MVFR0 */ 4088 case 0b0111: 4089 params->Op2 = 0; 4090 break; 4091 /* MVFR1 */ 4092 case 0b0110: 4093 params->Op2 = 1; 4094 break; 4095 /* MVFR2 */ 4096 case 0b0101: 4097 params->Op2 = 2; 4098 break; 4099 default: 4100 valid = false; 4101 } 4102 4103 if (valid) 4104 return true; 4105 4106 kvm_pr_unimpl("Unhandled cp10 register %s: %u\n", 4107 params->is_write ? "write" : "read", reg_id); 4108 return false; 4109 } 4110 4111 /** 4112 * kvm_handle_cp10_id() - Handles a VMRS trap on guest access to a 'Media and 4113 * VFP Register' from AArch32. 4114 * @vcpu: The vCPU pointer 4115 * 4116 * MVFR{0-2} are architecturally mapped to the AArch64 MVFR{0-2}_EL1 registers. 4117 * Work out the correct AArch64 system register encoding and reroute to the 4118 * AArch64 system register emulation. 4119 */ 4120 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu) 4121 { 4122 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4123 u64 esr = kvm_vcpu_get_esr(vcpu); 4124 struct sys_reg_params params; 4125 4126 /* UNDEF on any unhandled register access */ 4127 if (!kvm_esr_cp10_id_to_sys64(esr, ¶ms)) { 4128 kvm_inject_undefined(vcpu); 4129 return 1; 4130 } 4131 4132 if (emulate_sys_reg(vcpu, ¶ms)) 4133 vcpu_set_reg(vcpu, Rt, params.regval); 4134 4135 return 1; 4136 } 4137 4138 /** 4139 * kvm_emulate_cp15_id_reg() - Handles an MRC trap on a guest CP15 access where 4140 * CRn=0, which corresponds to the AArch32 feature 4141 * registers. 4142 * @vcpu: the vCPU pointer 4143 * @params: the system register access parameters. 4144 * 4145 * Our cp15 system register tables do not enumerate the AArch32 feature 4146 * registers. Conveniently, our AArch64 table does, and the AArch32 system 4147 * register encoding can be trivially remapped into the AArch64 for the feature 4148 * registers: Append op0=3, leaving op1, CRn, CRm, and op2 the same. 4149 * 4150 * According to DDI0487G.b G7.3.1, paragraph "Behavior of VMSAv8-32 32-bit 4151 * System registers with (coproc=0b1111, CRn==c0)", read accesses from this 4152 * range are either UNKNOWN or RES0. Rerouting remains architectural as we 4153 * treat undefined registers in this range as RAZ. 4154 */ 4155 static int kvm_emulate_cp15_id_reg(struct kvm_vcpu *vcpu, 4156 struct sys_reg_params *params) 4157 { 4158 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4159 4160 /* Treat impossible writes to RO registers as UNDEFINED */ 4161 if (params->is_write) { 4162 unhandled_cp_access(vcpu, params); 4163 return 1; 4164 } 4165 4166 params->Op0 = 3; 4167 4168 /* 4169 * All registers where CRm > 3 are known to be UNKNOWN/RAZ from AArch32. 4170 * Avoid conflicting with future expansion of AArch64 feature registers 4171 * and simply treat them as RAZ here. 4172 */ 4173 if (params->CRm > 3) 4174 params->regval = 0; 4175 else if (!emulate_sys_reg(vcpu, params)) 4176 return 1; 4177 4178 vcpu_set_reg(vcpu, Rt, params->regval); 4179 return 1; 4180 } 4181 4182 /** 4183 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access 4184 * @vcpu: The VCPU pointer 4185 * @params: &struct sys_reg_params 4186 * @global: &struct sys_reg_desc 4187 * @nr_global: size of the @global array 4188 */ 4189 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu, 4190 struct sys_reg_params *params, 4191 const struct sys_reg_desc *global, 4192 size_t nr_global) 4193 { 4194 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4195 4196 params->regval = vcpu_get_reg(vcpu, Rt); 4197 4198 if (emulate_cp(vcpu, params, global, nr_global)) { 4199 if (!params->is_write) 4200 vcpu_set_reg(vcpu, Rt, params->regval); 4201 return 1; 4202 } 4203 4204 unhandled_cp_access(vcpu, params); 4205 return 1; 4206 } 4207 4208 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu) 4209 { 4210 return kvm_handle_cp_64(vcpu, cp15_64_regs, ARRAY_SIZE(cp15_64_regs)); 4211 } 4212 4213 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu) 4214 { 4215 struct sys_reg_params params; 4216 4217 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu)); 4218 4219 /* 4220 * Certain AArch32 ID registers are handled by rerouting to the AArch64 4221 * system register table. Registers in the ID range where CRm=0 are 4222 * excluded from this scheme as they do not trivially map into AArch64 4223 * system register encodings. 4224 */ 4225 if (params.Op1 == 0 && params.CRn == 0 && params.CRm) 4226 return kvm_emulate_cp15_id_reg(vcpu, ¶ms); 4227 4228 return kvm_handle_cp_32(vcpu, ¶ms, cp15_regs, ARRAY_SIZE(cp15_regs)); 4229 } 4230 4231 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu) 4232 { 4233 return kvm_handle_cp_64(vcpu, cp14_64_regs, ARRAY_SIZE(cp14_64_regs)); 4234 } 4235 4236 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu) 4237 { 4238 struct sys_reg_params params; 4239 4240 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu)); 4241 4242 return kvm_handle_cp_32(vcpu, ¶ms, cp14_regs, ARRAY_SIZE(cp14_regs)); 4243 } 4244 4245 /** 4246 * emulate_sys_reg - Emulate a guest access to an AArch64 system register 4247 * @vcpu: The VCPU pointer 4248 * @params: Decoded system register parameters 4249 * 4250 * Return: true if the system register access was successful, false otherwise. 4251 */ 4252 static bool emulate_sys_reg(struct kvm_vcpu *vcpu, 4253 struct sys_reg_params *params) 4254 { 4255 const struct sys_reg_desc *r; 4256 4257 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 4258 if (likely(r)) { 4259 perform_access(vcpu, params, r); 4260 return true; 4261 } 4262 4263 print_sys_reg_msg(params, 4264 "Unsupported guest sys_reg access at: %lx [%08lx]\n", 4265 *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 4266 kvm_inject_undefined(vcpu); 4267 4268 return false; 4269 } 4270 4271 static const struct sys_reg_desc *idregs_debug_find(struct kvm *kvm, u8 pos) 4272 { 4273 unsigned long i, idreg_idx = 0; 4274 4275 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { 4276 const struct sys_reg_desc *r = &sys_reg_descs[i]; 4277 4278 if (!is_vm_ftr_id_reg(reg_to_encoding(r))) 4279 continue; 4280 4281 if (idreg_idx == pos) 4282 return r; 4283 4284 idreg_idx++; 4285 } 4286 4287 return NULL; 4288 } 4289 4290 static void *idregs_debug_start(struct seq_file *s, loff_t *pos) 4291 { 4292 struct kvm *kvm = s->private; 4293 u8 *iter; 4294 4295 mutex_lock(&kvm->arch.config_lock); 4296 4297 iter = &kvm->arch.idreg_debugfs_iter; 4298 if (test_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags) && 4299 *iter == (u8)~0) { 4300 *iter = *pos; 4301 if (!idregs_debug_find(kvm, *iter)) 4302 iter = NULL; 4303 } else { 4304 iter = ERR_PTR(-EBUSY); 4305 } 4306 4307 mutex_unlock(&kvm->arch.config_lock); 4308 4309 return iter; 4310 } 4311 4312 static void *idregs_debug_next(struct seq_file *s, void *v, loff_t *pos) 4313 { 4314 struct kvm *kvm = s->private; 4315 4316 (*pos)++; 4317 4318 if (idregs_debug_find(kvm, kvm->arch.idreg_debugfs_iter + 1)) { 4319 kvm->arch.idreg_debugfs_iter++; 4320 4321 return &kvm->arch.idreg_debugfs_iter; 4322 } 4323 4324 return NULL; 4325 } 4326 4327 static void idregs_debug_stop(struct seq_file *s, void *v) 4328 { 4329 struct kvm *kvm = s->private; 4330 4331 if (IS_ERR(v)) 4332 return; 4333 4334 mutex_lock(&kvm->arch.config_lock); 4335 4336 kvm->arch.idreg_debugfs_iter = ~0; 4337 4338 mutex_unlock(&kvm->arch.config_lock); 4339 } 4340 4341 static int idregs_debug_show(struct seq_file *s, void *v) 4342 { 4343 const struct sys_reg_desc *desc; 4344 struct kvm *kvm = s->private; 4345 4346 desc = idregs_debug_find(kvm, kvm->arch.idreg_debugfs_iter); 4347 4348 if (!desc->name) 4349 return 0; 4350 4351 seq_printf(s, "%20s:\t%016llx\n", 4352 desc->name, kvm_read_vm_id_reg(kvm, reg_to_encoding(desc))); 4353 4354 return 0; 4355 } 4356 4357 static const struct seq_operations idregs_debug_sops = { 4358 .start = idregs_debug_start, 4359 .next = idregs_debug_next, 4360 .stop = idregs_debug_stop, 4361 .show = idregs_debug_show, 4362 }; 4363 4364 DEFINE_SEQ_ATTRIBUTE(idregs_debug); 4365 4366 void kvm_sys_regs_create_debugfs(struct kvm *kvm) 4367 { 4368 kvm->arch.idreg_debugfs_iter = ~0; 4369 4370 debugfs_create_file("idregs", 0444, kvm->debugfs_dentry, kvm, 4371 &idregs_debug_fops); 4372 } 4373 4374 static void reset_vm_ftr_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *reg) 4375 { 4376 u32 id = reg_to_encoding(reg); 4377 struct kvm *kvm = vcpu->kvm; 4378 4379 if (test_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags)) 4380 return; 4381 4382 kvm_set_vm_id_reg(kvm, id, reg->reset(vcpu, reg)); 4383 } 4384 4385 static void reset_vcpu_ftr_id_reg(struct kvm_vcpu *vcpu, 4386 const struct sys_reg_desc *reg) 4387 { 4388 if (kvm_vcpu_initialized(vcpu)) 4389 return; 4390 4391 reg->reset(vcpu, reg); 4392 } 4393 4394 /** 4395 * kvm_reset_sys_regs - sets system registers to reset value 4396 * @vcpu: The VCPU pointer 4397 * 4398 * This function finds the right table above and sets the registers on the 4399 * virtual CPU struct to their architecturally defined reset values. 4400 */ 4401 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu) 4402 { 4403 struct kvm *kvm = vcpu->kvm; 4404 unsigned long i; 4405 4406 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { 4407 const struct sys_reg_desc *r = &sys_reg_descs[i]; 4408 4409 if (!r->reset) 4410 continue; 4411 4412 if (is_vm_ftr_id_reg(reg_to_encoding(r))) 4413 reset_vm_ftr_id_reg(vcpu, r); 4414 else if (is_vcpu_ftr_id_reg(reg_to_encoding(r))) 4415 reset_vcpu_ftr_id_reg(vcpu, r); 4416 else 4417 r->reset(vcpu, r); 4418 } 4419 4420 set_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags); 4421 } 4422 4423 /** 4424 * kvm_handle_sys_reg -- handles a system instruction or mrs/msr instruction 4425 * trap on a guest execution 4426 * @vcpu: The VCPU pointer 4427 */ 4428 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu) 4429 { 4430 const struct sys_reg_desc *desc = NULL; 4431 struct sys_reg_params params; 4432 unsigned long esr = kvm_vcpu_get_esr(vcpu); 4433 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4434 int sr_idx; 4435 4436 trace_kvm_handle_sys_reg(esr); 4437 4438 if (triage_sysreg_trap(vcpu, &sr_idx)) 4439 return 1; 4440 4441 params = esr_sys64_to_params(esr); 4442 params.regval = vcpu_get_reg(vcpu, Rt); 4443 4444 /* System registers have Op0=={2,3}, as per DDI487 J.a C5.1.2 */ 4445 if (params.Op0 == 2 || params.Op0 == 3) 4446 desc = &sys_reg_descs[sr_idx]; 4447 else 4448 desc = &sys_insn_descs[sr_idx]; 4449 4450 perform_access(vcpu, ¶ms, desc); 4451 4452 /* Read from system register? */ 4453 if (!params.is_write && 4454 (params.Op0 == 2 || params.Op0 == 3)) 4455 vcpu_set_reg(vcpu, Rt, params.regval); 4456 4457 return 1; 4458 } 4459 4460 /****************************************************************************** 4461 * Userspace API 4462 *****************************************************************************/ 4463 4464 static bool index_to_params(u64 id, struct sys_reg_params *params) 4465 { 4466 switch (id & KVM_REG_SIZE_MASK) { 4467 case KVM_REG_SIZE_U64: 4468 /* Any unused index bits means it's not valid. */ 4469 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK 4470 | KVM_REG_ARM_COPROC_MASK 4471 | KVM_REG_ARM64_SYSREG_OP0_MASK 4472 | KVM_REG_ARM64_SYSREG_OP1_MASK 4473 | KVM_REG_ARM64_SYSREG_CRN_MASK 4474 | KVM_REG_ARM64_SYSREG_CRM_MASK 4475 | KVM_REG_ARM64_SYSREG_OP2_MASK)) 4476 return false; 4477 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK) 4478 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT); 4479 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK) 4480 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT); 4481 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK) 4482 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT); 4483 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK) 4484 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT); 4485 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK) 4486 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT); 4487 return true; 4488 default: 4489 return false; 4490 } 4491 } 4492 4493 const struct sys_reg_desc *get_reg_by_id(u64 id, 4494 const struct sys_reg_desc table[], 4495 unsigned int num) 4496 { 4497 struct sys_reg_params params; 4498 4499 if (!index_to_params(id, ¶ms)) 4500 return NULL; 4501 4502 return find_reg(¶ms, table, num); 4503 } 4504 4505 /* Decode an index value, and find the sys_reg_desc entry. */ 4506 static const struct sys_reg_desc * 4507 id_to_sys_reg_desc(struct kvm_vcpu *vcpu, u64 id, 4508 const struct sys_reg_desc table[], unsigned int num) 4509 4510 { 4511 const struct sys_reg_desc *r; 4512 4513 /* We only do sys_reg for now. */ 4514 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG) 4515 return NULL; 4516 4517 r = get_reg_by_id(id, table, num); 4518 4519 /* Not saved in the sys_reg array and not otherwise accessible? */ 4520 if (r && (!(r->reg || r->get_user) || sysreg_hidden(vcpu, r))) 4521 r = NULL; 4522 4523 return r; 4524 } 4525 4526 /* 4527 * These are the invariant sys_reg registers: we let the guest see the 4528 * host versions of these, so they're part of the guest state. 4529 * 4530 * A future CPU may provide a mechanism to present different values to 4531 * the guest, or a future kvm may trap them. 4532 */ 4533 4534 #define FUNCTION_INVARIANT(reg) \ 4535 static u64 reset_##reg(struct kvm_vcpu *v, \ 4536 const struct sys_reg_desc *r) \ 4537 { \ 4538 ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \ 4539 return ((struct sys_reg_desc *)r)->val; \ 4540 } 4541 4542 FUNCTION_INVARIANT(midr_el1) 4543 FUNCTION_INVARIANT(revidr_el1) 4544 FUNCTION_INVARIANT(aidr_el1) 4545 4546 /* ->val is filled in by kvm_sys_reg_table_init() */ 4547 static struct sys_reg_desc invariant_sys_regs[] __ro_after_init = { 4548 { SYS_DESC(SYS_MIDR_EL1), NULL, reset_midr_el1 }, 4549 { SYS_DESC(SYS_REVIDR_EL1), NULL, reset_revidr_el1 }, 4550 { SYS_DESC(SYS_AIDR_EL1), NULL, reset_aidr_el1 }, 4551 }; 4552 4553 static int get_invariant_sys_reg(u64 id, u64 __user *uaddr) 4554 { 4555 const struct sys_reg_desc *r; 4556 4557 r = get_reg_by_id(id, invariant_sys_regs, 4558 ARRAY_SIZE(invariant_sys_regs)); 4559 if (!r) 4560 return -ENOENT; 4561 4562 return put_user(r->val, uaddr); 4563 } 4564 4565 static int set_invariant_sys_reg(u64 id, u64 __user *uaddr) 4566 { 4567 const struct sys_reg_desc *r; 4568 u64 val; 4569 4570 r = get_reg_by_id(id, invariant_sys_regs, 4571 ARRAY_SIZE(invariant_sys_regs)); 4572 if (!r) 4573 return -ENOENT; 4574 4575 if (get_user(val, uaddr)) 4576 return -EFAULT; 4577 4578 /* This is what we mean by invariant: you can't change it. */ 4579 if (r->val != val) 4580 return -EINVAL; 4581 4582 return 0; 4583 } 4584 4585 static int demux_c15_get(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) 4586 { 4587 u32 val; 4588 u32 __user *uval = uaddr; 4589 4590 /* Fail if we have unknown bits set. */ 4591 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 4592 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 4593 return -ENOENT; 4594 4595 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 4596 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 4597 if (KVM_REG_SIZE(id) != 4) 4598 return -ENOENT; 4599 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 4600 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 4601 if (val >= CSSELR_MAX) 4602 return -ENOENT; 4603 4604 return put_user(get_ccsidr(vcpu, val), uval); 4605 default: 4606 return -ENOENT; 4607 } 4608 } 4609 4610 static int demux_c15_set(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) 4611 { 4612 u32 val, newval; 4613 u32 __user *uval = uaddr; 4614 4615 /* Fail if we have unknown bits set. */ 4616 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 4617 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 4618 return -ENOENT; 4619 4620 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 4621 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 4622 if (KVM_REG_SIZE(id) != 4) 4623 return -ENOENT; 4624 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 4625 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 4626 if (val >= CSSELR_MAX) 4627 return -ENOENT; 4628 4629 if (get_user(newval, uval)) 4630 return -EFAULT; 4631 4632 return set_ccsidr(vcpu, val, newval); 4633 default: 4634 return -ENOENT; 4635 } 4636 } 4637 4638 int kvm_sys_reg_get_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg, 4639 const struct sys_reg_desc table[], unsigned int num) 4640 { 4641 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr; 4642 const struct sys_reg_desc *r; 4643 u64 val; 4644 int ret; 4645 4646 r = id_to_sys_reg_desc(vcpu, reg->id, table, num); 4647 if (!r || sysreg_hidden(vcpu, r)) 4648 return -ENOENT; 4649 4650 if (r->get_user) { 4651 ret = (r->get_user)(vcpu, r, &val); 4652 } else { 4653 val = __vcpu_sys_reg(vcpu, r->reg); 4654 ret = 0; 4655 } 4656 4657 if (!ret) 4658 ret = put_user(val, uaddr); 4659 4660 return ret; 4661 } 4662 4663 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 4664 { 4665 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 4666 int err; 4667 4668 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 4669 return demux_c15_get(vcpu, reg->id, uaddr); 4670 4671 err = get_invariant_sys_reg(reg->id, uaddr); 4672 if (err != -ENOENT) 4673 return err; 4674 4675 return kvm_sys_reg_get_user(vcpu, reg, 4676 sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 4677 } 4678 4679 int kvm_sys_reg_set_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg, 4680 const struct sys_reg_desc table[], unsigned int num) 4681 { 4682 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr; 4683 const struct sys_reg_desc *r; 4684 u64 val; 4685 int ret; 4686 4687 if (get_user(val, uaddr)) 4688 return -EFAULT; 4689 4690 r = id_to_sys_reg_desc(vcpu, reg->id, table, num); 4691 if (!r || sysreg_hidden(vcpu, r)) 4692 return -ENOENT; 4693 4694 if (sysreg_user_write_ignore(vcpu, r)) 4695 return 0; 4696 4697 if (r->set_user) { 4698 ret = (r->set_user)(vcpu, r, val); 4699 } else { 4700 __vcpu_sys_reg(vcpu, r->reg) = val; 4701 ret = 0; 4702 } 4703 4704 return ret; 4705 } 4706 4707 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 4708 { 4709 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 4710 int err; 4711 4712 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 4713 return demux_c15_set(vcpu, reg->id, uaddr); 4714 4715 err = set_invariant_sys_reg(reg->id, uaddr); 4716 if (err != -ENOENT) 4717 return err; 4718 4719 return kvm_sys_reg_set_user(vcpu, reg, 4720 sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 4721 } 4722 4723 static unsigned int num_demux_regs(void) 4724 { 4725 return CSSELR_MAX; 4726 } 4727 4728 static int write_demux_regids(u64 __user *uindices) 4729 { 4730 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX; 4731 unsigned int i; 4732 4733 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR; 4734 for (i = 0; i < CSSELR_MAX; i++) { 4735 if (put_user(val | i, uindices)) 4736 return -EFAULT; 4737 uindices++; 4738 } 4739 return 0; 4740 } 4741 4742 static u64 sys_reg_to_index(const struct sys_reg_desc *reg) 4743 { 4744 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | 4745 KVM_REG_ARM64_SYSREG | 4746 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) | 4747 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) | 4748 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) | 4749 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) | 4750 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT)); 4751 } 4752 4753 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind) 4754 { 4755 if (!*uind) 4756 return true; 4757 4758 if (put_user(sys_reg_to_index(reg), *uind)) 4759 return false; 4760 4761 (*uind)++; 4762 return true; 4763 } 4764 4765 static int walk_one_sys_reg(const struct kvm_vcpu *vcpu, 4766 const struct sys_reg_desc *rd, 4767 u64 __user **uind, 4768 unsigned int *total) 4769 { 4770 /* 4771 * Ignore registers we trap but don't save, 4772 * and for which no custom user accessor is provided. 4773 */ 4774 if (!(rd->reg || rd->get_user)) 4775 return 0; 4776 4777 if (sysreg_hidden(vcpu, rd)) 4778 return 0; 4779 4780 if (!copy_reg_to_user(rd, uind)) 4781 return -EFAULT; 4782 4783 (*total)++; 4784 return 0; 4785 } 4786 4787 /* Assumed ordered tables, see kvm_sys_reg_table_init. */ 4788 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind) 4789 { 4790 const struct sys_reg_desc *i2, *end2; 4791 unsigned int total = 0; 4792 int err; 4793 4794 i2 = sys_reg_descs; 4795 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs); 4796 4797 while (i2 != end2) { 4798 err = walk_one_sys_reg(vcpu, i2++, &uind, &total); 4799 if (err) 4800 return err; 4801 } 4802 return total; 4803 } 4804 4805 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu) 4806 { 4807 return ARRAY_SIZE(invariant_sys_regs) 4808 + num_demux_regs() 4809 + walk_sys_regs(vcpu, (u64 __user *)NULL); 4810 } 4811 4812 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) 4813 { 4814 unsigned int i; 4815 int err; 4816 4817 /* Then give them all the invariant registers' indices. */ 4818 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) { 4819 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices)) 4820 return -EFAULT; 4821 uindices++; 4822 } 4823 4824 err = walk_sys_regs(vcpu, uindices); 4825 if (err < 0) 4826 return err; 4827 uindices += err; 4828 4829 return write_demux_regids(uindices); 4830 } 4831 4832 #define KVM_ARM_FEATURE_ID_RANGE_INDEX(r) \ 4833 KVM_ARM_FEATURE_ID_RANGE_IDX(sys_reg_Op0(r), \ 4834 sys_reg_Op1(r), \ 4835 sys_reg_CRn(r), \ 4836 sys_reg_CRm(r), \ 4837 sys_reg_Op2(r)) 4838 4839 int kvm_vm_ioctl_get_reg_writable_masks(struct kvm *kvm, struct reg_mask_range *range) 4840 { 4841 const void *zero_page = page_to_virt(ZERO_PAGE(0)); 4842 u64 __user *masks = (u64 __user *)range->addr; 4843 4844 /* Only feature id range is supported, reserved[13] must be zero. */ 4845 if (range->range || 4846 memcmp(range->reserved, zero_page, sizeof(range->reserved))) 4847 return -EINVAL; 4848 4849 /* Wipe the whole thing first */ 4850 if (clear_user(masks, KVM_ARM_FEATURE_ID_RANGE_SIZE * sizeof(__u64))) 4851 return -EFAULT; 4852 4853 for (int i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { 4854 const struct sys_reg_desc *reg = &sys_reg_descs[i]; 4855 u32 encoding = reg_to_encoding(reg); 4856 u64 val; 4857 4858 if (!is_feature_id_reg(encoding) || !reg->set_user) 4859 continue; 4860 4861 if (!reg->val || 4862 (is_aa32_id_reg(encoding) && !kvm_supports_32bit_el0())) { 4863 continue; 4864 } 4865 val = reg->val; 4866 4867 if (put_user(val, (masks + KVM_ARM_FEATURE_ID_RANGE_INDEX(encoding)))) 4868 return -EFAULT; 4869 } 4870 4871 return 0; 4872 } 4873 4874 static void vcpu_set_hcr(struct kvm_vcpu *vcpu) 4875 { 4876 struct kvm *kvm = vcpu->kvm; 4877 4878 if (has_vhe() || has_hvhe()) 4879 vcpu->arch.hcr_el2 |= HCR_E2H; 4880 if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN)) { 4881 /* route synchronous external abort exceptions to EL2 */ 4882 vcpu->arch.hcr_el2 |= HCR_TEA; 4883 /* trap error record accesses */ 4884 vcpu->arch.hcr_el2 |= HCR_TERR; 4885 } 4886 4887 if (cpus_have_final_cap(ARM64_HAS_STAGE2_FWB)) 4888 vcpu->arch.hcr_el2 |= HCR_FWB; 4889 4890 if (cpus_have_final_cap(ARM64_HAS_EVT) && 4891 !cpus_have_final_cap(ARM64_MISMATCHED_CACHE_TYPE) && 4892 kvm_read_vm_id_reg(kvm, SYS_CTR_EL0) == read_sanitised_ftr_reg(SYS_CTR_EL0)) 4893 vcpu->arch.hcr_el2 |= HCR_TID4; 4894 else 4895 vcpu->arch.hcr_el2 |= HCR_TID2; 4896 4897 if (vcpu_el1_is_32bit(vcpu)) 4898 vcpu->arch.hcr_el2 &= ~HCR_RW; 4899 4900 if (kvm_has_mte(vcpu->kvm)) 4901 vcpu->arch.hcr_el2 |= HCR_ATA; 4902 4903 /* 4904 * In the absence of FGT, we cannot independently trap TLBI 4905 * Range instructions. This isn't great, but trapping all 4906 * TLBIs would be far worse. Live with it... 4907 */ 4908 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 4909 vcpu->arch.hcr_el2 |= HCR_TTLBOS; 4910 } 4911 4912 void kvm_calculate_traps(struct kvm_vcpu *vcpu) 4913 { 4914 struct kvm *kvm = vcpu->kvm; 4915 4916 mutex_lock(&kvm->arch.config_lock); 4917 vcpu_set_hcr(vcpu); 4918 vcpu_set_ich_hcr(vcpu); 4919 4920 if (cpus_have_final_cap(ARM64_HAS_HCX)) { 4921 /* 4922 * In general, all HCRX_EL2 bits are gated by a feature. 4923 * The only reason we can set SMPME without checking any 4924 * feature is that its effects are not directly observable 4925 * from the guest. 4926 */ 4927 vcpu->arch.hcrx_el2 = HCRX_EL2_SMPME; 4928 4929 if (kvm_has_feat(kvm, ID_AA64ISAR2_EL1, MOPS, IMP)) 4930 vcpu->arch.hcrx_el2 |= (HCRX_EL2_MSCEn | HCRX_EL2_MCE2); 4931 4932 if (kvm_has_tcr2(kvm)) 4933 vcpu->arch.hcrx_el2 |= HCRX_EL2_TCR2En; 4934 4935 if (kvm_has_fpmr(kvm)) 4936 vcpu->arch.hcrx_el2 |= HCRX_EL2_EnFPM; 4937 } 4938 4939 if (test_bit(KVM_ARCH_FLAG_FGU_INITIALIZED, &kvm->arch.flags)) 4940 goto out; 4941 4942 kvm->arch.fgu[HFGxTR_GROUP] = (HFGxTR_EL2_nAMAIR2_EL1 | 4943 HFGxTR_EL2_nMAIR2_EL1 | 4944 HFGxTR_EL2_nS2POR_EL1 | 4945 HFGxTR_EL2_nACCDATA_EL1 | 4946 HFGxTR_EL2_nSMPRI_EL1_MASK | 4947 HFGxTR_EL2_nTPIDR2_EL0_MASK); 4948 4949 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 4950 kvm->arch.fgu[HFGITR_GROUP] |= (HFGITR_EL2_TLBIRVAALE1OS| 4951 HFGITR_EL2_TLBIRVALE1OS | 4952 HFGITR_EL2_TLBIRVAAE1OS | 4953 HFGITR_EL2_TLBIRVAE1OS | 4954 HFGITR_EL2_TLBIVAALE1OS | 4955 HFGITR_EL2_TLBIVALE1OS | 4956 HFGITR_EL2_TLBIVAAE1OS | 4957 HFGITR_EL2_TLBIASIDE1OS | 4958 HFGITR_EL2_TLBIVAE1OS | 4959 HFGITR_EL2_TLBIVMALLE1OS); 4960 4961 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE)) 4962 kvm->arch.fgu[HFGITR_GROUP] |= (HFGITR_EL2_TLBIRVAALE1 | 4963 HFGITR_EL2_TLBIRVALE1 | 4964 HFGITR_EL2_TLBIRVAAE1 | 4965 HFGITR_EL2_TLBIRVAE1 | 4966 HFGITR_EL2_TLBIRVAALE1IS| 4967 HFGITR_EL2_TLBIRVALE1IS | 4968 HFGITR_EL2_TLBIRVAAE1IS | 4969 HFGITR_EL2_TLBIRVAE1IS | 4970 HFGITR_EL2_TLBIRVAALE1OS| 4971 HFGITR_EL2_TLBIRVALE1OS | 4972 HFGITR_EL2_TLBIRVAAE1OS | 4973 HFGITR_EL2_TLBIRVAE1OS); 4974 4975 if (!kvm_has_feat(kvm, ID_AA64ISAR2_EL1, ATS1A, IMP)) 4976 kvm->arch.fgu[HFGITR_GROUP] |= HFGITR_EL2_ATS1E1A; 4977 4978 if (!kvm_has_feat(kvm, ID_AA64MMFR1_EL1, PAN, PAN2)) 4979 kvm->arch.fgu[HFGITR_GROUP] |= (HFGITR_EL2_ATS1E1RP | 4980 HFGITR_EL2_ATS1E1WP); 4981 4982 if (!kvm_has_s1pie(kvm)) 4983 kvm->arch.fgu[HFGxTR_GROUP] |= (HFGxTR_EL2_nPIRE0_EL1 | 4984 HFGxTR_EL2_nPIR_EL1); 4985 4986 if (!kvm_has_s1poe(kvm)) 4987 kvm->arch.fgu[HFGxTR_GROUP] |= (HFGxTR_EL2_nPOR_EL1 | 4988 HFGxTR_EL2_nPOR_EL0); 4989 4990 if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, AMU, IMP)) 4991 kvm->arch.fgu[HAFGRTR_GROUP] |= ~(HAFGRTR_EL2_RES0 | 4992 HAFGRTR_EL2_RES1); 4993 4994 set_bit(KVM_ARCH_FLAG_FGU_INITIALIZED, &kvm->arch.flags); 4995 out: 4996 mutex_unlock(&kvm->arch.config_lock); 4997 } 4998 4999 /* 5000 * Perform last adjustments to the ID registers that are implied by the 5001 * configuration outside of the ID regs themselves, as well as any 5002 * initialisation that directly depend on these ID registers (such as 5003 * RES0/RES1 behaviours). This is not the place to configure traps though. 5004 * 5005 * Because this can be called once per CPU, changes must be idempotent. 5006 */ 5007 int kvm_finalize_sys_regs(struct kvm_vcpu *vcpu) 5008 { 5009 struct kvm *kvm = vcpu->kvm; 5010 5011 guard(mutex)(&kvm->arch.config_lock); 5012 5013 if (!(static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif) && 5014 irqchip_in_kernel(kvm) && 5015 kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3)) { 5016 kvm->arch.id_regs[IDREG_IDX(SYS_ID_AA64PFR0_EL1)] &= ~ID_AA64PFR0_EL1_GIC_MASK; 5017 kvm->arch.id_regs[IDREG_IDX(SYS_ID_PFR1_EL1)] &= ~ID_PFR1_EL1_GIC_MASK; 5018 } 5019 5020 if (vcpu_has_nv(vcpu)) { 5021 int ret = kvm_init_nv_sysregs(kvm); 5022 if (ret) 5023 return ret; 5024 } 5025 5026 return 0; 5027 } 5028 5029 int __init kvm_sys_reg_table_init(void) 5030 { 5031 bool valid = true; 5032 unsigned int i; 5033 int ret = 0; 5034 5035 /* Make sure tables are unique and in order. */ 5036 valid &= check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), false); 5037 valid &= check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), true); 5038 valid &= check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), true); 5039 valid &= check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), true); 5040 valid &= check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), true); 5041 valid &= check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs), false); 5042 valid &= check_sysreg_table(sys_insn_descs, ARRAY_SIZE(sys_insn_descs), false); 5043 5044 if (!valid) 5045 return -EINVAL; 5046 5047 /* We abuse the reset function to overwrite the table itself. */ 5048 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) 5049 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]); 5050 5051 ret = populate_nv_trap_config(); 5052 5053 for (i = 0; !ret && i < ARRAY_SIZE(sys_reg_descs); i++) 5054 ret = populate_sysreg_config(sys_reg_descs + i, i); 5055 5056 for (i = 0; !ret && i < ARRAY_SIZE(sys_insn_descs); i++) 5057 ret = populate_sysreg_config(sys_insn_descs + i, i); 5058 5059 return ret; 5060 } 5061