1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/kvm/coproc.c: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Authors: Rusty Russell <rusty@rustcorp.com.au> 9 * Christoffer Dall <c.dall@virtualopensystems.com> 10 */ 11 12 #include <linux/bitfield.h> 13 #include <linux/bsearch.h> 14 #include <linux/cacheinfo.h> 15 #include <linux/debugfs.h> 16 #include <linux/kvm_host.h> 17 #include <linux/mm.h> 18 #include <linux/printk.h> 19 #include <linux/uaccess.h> 20 #include <linux/irqchip/arm-gic-v3.h> 21 22 #include <asm/arm_pmuv3.h> 23 #include <asm/cacheflush.h> 24 #include <asm/cputype.h> 25 #include <asm/debug-monitors.h> 26 #include <asm/esr.h> 27 #include <asm/kvm_arm.h> 28 #include <asm/kvm_emulate.h> 29 #include <asm/kvm_hyp.h> 30 #include <asm/kvm_mmu.h> 31 #include <asm/kvm_nested.h> 32 #include <asm/perf_event.h> 33 #include <asm/sysreg.h> 34 35 #include <trace/events/kvm.h> 36 37 #include "sys_regs.h" 38 #include "vgic/vgic.h" 39 40 #include "trace.h" 41 42 /* 43 * For AArch32, we only take care of what is being trapped. Anything 44 * that has to do with init and userspace access has to go via the 45 * 64bit interface. 46 */ 47 48 static u64 sys_reg_to_index(const struct sys_reg_desc *reg); 49 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 50 u64 val); 51 52 static bool undef_access(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 53 const struct sys_reg_desc *r) 54 { 55 kvm_inject_undefined(vcpu); 56 return false; 57 } 58 59 static bool bad_trap(struct kvm_vcpu *vcpu, 60 struct sys_reg_params *params, 61 const struct sys_reg_desc *r, 62 const char *msg) 63 { 64 WARN_ONCE(1, "Unexpected %s\n", msg); 65 print_sys_reg_instr(params); 66 return undef_access(vcpu, params, r); 67 } 68 69 static bool read_from_write_only(struct kvm_vcpu *vcpu, 70 struct sys_reg_params *params, 71 const struct sys_reg_desc *r) 72 { 73 return bad_trap(vcpu, params, r, 74 "sys_reg read to write-only register"); 75 } 76 77 static bool write_to_read_only(struct kvm_vcpu *vcpu, 78 struct sys_reg_params *params, 79 const struct sys_reg_desc *r) 80 { 81 return bad_trap(vcpu, params, r, 82 "sys_reg write to read-only register"); 83 } 84 85 #define PURE_EL2_SYSREG(el2) \ 86 case el2: { \ 87 *el1r = el2; \ 88 return true; \ 89 } 90 91 #define MAPPED_EL2_SYSREG(el2, el1, fn) \ 92 case el2: { \ 93 *xlate = fn; \ 94 *el1r = el1; \ 95 return true; \ 96 } 97 98 static bool get_el2_to_el1_mapping(unsigned int reg, 99 unsigned int *el1r, u64 (**xlate)(u64)) 100 { 101 switch (reg) { 102 PURE_EL2_SYSREG( VPIDR_EL2 ); 103 PURE_EL2_SYSREG( VMPIDR_EL2 ); 104 PURE_EL2_SYSREG( ACTLR_EL2 ); 105 PURE_EL2_SYSREG( HCR_EL2 ); 106 PURE_EL2_SYSREG( MDCR_EL2 ); 107 PURE_EL2_SYSREG( HSTR_EL2 ); 108 PURE_EL2_SYSREG( HACR_EL2 ); 109 PURE_EL2_SYSREG( VTTBR_EL2 ); 110 PURE_EL2_SYSREG( VTCR_EL2 ); 111 PURE_EL2_SYSREG( RVBAR_EL2 ); 112 PURE_EL2_SYSREG( TPIDR_EL2 ); 113 PURE_EL2_SYSREG( HPFAR_EL2 ); 114 PURE_EL2_SYSREG( HCRX_EL2 ); 115 PURE_EL2_SYSREG( HFGRTR_EL2 ); 116 PURE_EL2_SYSREG( HFGWTR_EL2 ); 117 PURE_EL2_SYSREG( HFGITR_EL2 ); 118 PURE_EL2_SYSREG( HDFGRTR_EL2 ); 119 PURE_EL2_SYSREG( HDFGWTR_EL2 ); 120 PURE_EL2_SYSREG( HAFGRTR_EL2 ); 121 PURE_EL2_SYSREG( CNTVOFF_EL2 ); 122 PURE_EL2_SYSREG( CNTHCTL_EL2 ); 123 MAPPED_EL2_SYSREG(SCTLR_EL2, SCTLR_EL1, 124 translate_sctlr_el2_to_sctlr_el1 ); 125 MAPPED_EL2_SYSREG(CPTR_EL2, CPACR_EL1, 126 translate_cptr_el2_to_cpacr_el1 ); 127 MAPPED_EL2_SYSREG(TTBR0_EL2, TTBR0_EL1, 128 translate_ttbr0_el2_to_ttbr0_el1 ); 129 MAPPED_EL2_SYSREG(TTBR1_EL2, TTBR1_EL1, NULL ); 130 MAPPED_EL2_SYSREG(TCR_EL2, TCR_EL1, 131 translate_tcr_el2_to_tcr_el1 ); 132 MAPPED_EL2_SYSREG(VBAR_EL2, VBAR_EL1, NULL ); 133 MAPPED_EL2_SYSREG(AFSR0_EL2, AFSR0_EL1, NULL ); 134 MAPPED_EL2_SYSREG(AFSR1_EL2, AFSR1_EL1, NULL ); 135 MAPPED_EL2_SYSREG(ESR_EL2, ESR_EL1, NULL ); 136 MAPPED_EL2_SYSREG(FAR_EL2, FAR_EL1, NULL ); 137 MAPPED_EL2_SYSREG(MAIR_EL2, MAIR_EL1, NULL ); 138 MAPPED_EL2_SYSREG(TCR2_EL2, TCR2_EL1, NULL ); 139 MAPPED_EL2_SYSREG(PIR_EL2, PIR_EL1, NULL ); 140 MAPPED_EL2_SYSREG(PIRE0_EL2, PIRE0_EL1, NULL ); 141 MAPPED_EL2_SYSREG(POR_EL2, POR_EL1, NULL ); 142 MAPPED_EL2_SYSREG(AMAIR_EL2, AMAIR_EL1, NULL ); 143 MAPPED_EL2_SYSREG(ELR_EL2, ELR_EL1, NULL ); 144 MAPPED_EL2_SYSREG(SPSR_EL2, SPSR_EL1, NULL ); 145 MAPPED_EL2_SYSREG(ZCR_EL2, ZCR_EL1, NULL ); 146 MAPPED_EL2_SYSREG(CONTEXTIDR_EL2, CONTEXTIDR_EL1, NULL ); 147 default: 148 return false; 149 } 150 } 151 152 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg) 153 { 154 u64 val = 0x8badf00d8badf00d; 155 u64 (*xlate)(u64) = NULL; 156 unsigned int el1r; 157 158 if (!vcpu_get_flag(vcpu, SYSREGS_ON_CPU)) 159 goto memory_read; 160 161 if (unlikely(get_el2_to_el1_mapping(reg, &el1r, &xlate))) { 162 if (!is_hyp_ctxt(vcpu)) 163 goto memory_read; 164 165 /* 166 * CNTHCTL_EL2 requires some special treatment to 167 * account for the bits that can be set via CNTKCTL_EL1. 168 */ 169 switch (reg) { 170 case CNTHCTL_EL2: 171 if (vcpu_el2_e2h_is_set(vcpu)) { 172 val = read_sysreg_el1(SYS_CNTKCTL); 173 val &= CNTKCTL_VALID_BITS; 174 val |= __vcpu_sys_reg(vcpu, reg) & ~CNTKCTL_VALID_BITS; 175 return val; 176 } 177 break; 178 } 179 180 /* 181 * If this register does not have an EL1 counterpart, 182 * then read the stored EL2 version. 183 */ 184 if (reg == el1r) 185 goto memory_read; 186 187 /* 188 * If we have a non-VHE guest and that the sysreg 189 * requires translation to be used at EL1, use the 190 * in-memory copy instead. 191 */ 192 if (!vcpu_el2_e2h_is_set(vcpu) && xlate) 193 goto memory_read; 194 195 /* Get the current version of the EL1 counterpart. */ 196 WARN_ON(!__vcpu_read_sys_reg_from_cpu(el1r, &val)); 197 if (reg >= __SANITISED_REG_START__) 198 val = kvm_vcpu_apply_reg_masks(vcpu, reg, val); 199 200 return val; 201 } 202 203 /* EL1 register can't be on the CPU if the guest is in vEL2. */ 204 if (unlikely(is_hyp_ctxt(vcpu))) 205 goto memory_read; 206 207 if (__vcpu_read_sys_reg_from_cpu(reg, &val)) 208 return val; 209 210 memory_read: 211 return __vcpu_sys_reg(vcpu, reg); 212 } 213 214 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg) 215 { 216 u64 (*xlate)(u64) = NULL; 217 unsigned int el1r; 218 219 if (!vcpu_get_flag(vcpu, SYSREGS_ON_CPU)) 220 goto memory_write; 221 222 if (unlikely(get_el2_to_el1_mapping(reg, &el1r, &xlate))) { 223 if (!is_hyp_ctxt(vcpu)) 224 goto memory_write; 225 226 /* 227 * Always store a copy of the write to memory to avoid having 228 * to reverse-translate virtual EL2 system registers for a 229 * non-VHE guest hypervisor. 230 */ 231 __vcpu_sys_reg(vcpu, reg) = val; 232 233 switch (reg) { 234 case CNTHCTL_EL2: 235 /* 236 * If E2H=0, CNHTCTL_EL2 is a pure shadow register. 237 * Otherwise, some of the bits are backed by 238 * CNTKCTL_EL1, while the rest is kept in memory. 239 * Yes, this is fun stuff. 240 */ 241 if (vcpu_el2_e2h_is_set(vcpu)) 242 write_sysreg_el1(val, SYS_CNTKCTL); 243 return; 244 } 245 246 /* No EL1 counterpart? We're done here.? */ 247 if (reg == el1r) 248 return; 249 250 if (!vcpu_el2_e2h_is_set(vcpu) && xlate) 251 val = xlate(val); 252 253 /* Redirect this to the EL1 version of the register. */ 254 WARN_ON(!__vcpu_write_sys_reg_to_cpu(val, el1r)); 255 return; 256 } 257 258 /* EL1 register can't be on the CPU if the guest is in vEL2. */ 259 if (unlikely(is_hyp_ctxt(vcpu))) 260 goto memory_write; 261 262 if (__vcpu_write_sys_reg_to_cpu(val, reg)) 263 return; 264 265 memory_write: 266 __vcpu_sys_reg(vcpu, reg) = val; 267 } 268 269 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */ 270 #define CSSELR_MAX 14 271 272 /* 273 * Returns the minimum line size for the selected cache, expressed as 274 * Log2(bytes). 275 */ 276 static u8 get_min_cache_line_size(bool icache) 277 { 278 u64 ctr = read_sanitised_ftr_reg(SYS_CTR_EL0); 279 u8 field; 280 281 if (icache) 282 field = SYS_FIELD_GET(CTR_EL0, IminLine, ctr); 283 else 284 field = SYS_FIELD_GET(CTR_EL0, DminLine, ctr); 285 286 /* 287 * Cache line size is represented as Log2(words) in CTR_EL0. 288 * Log2(bytes) can be derived with the following: 289 * 290 * Log2(words) + 2 = Log2(bytes / 4) + 2 291 * = Log2(bytes) - 2 + 2 292 * = Log2(bytes) 293 */ 294 return field + 2; 295 } 296 297 /* Which cache CCSIDR represents depends on CSSELR value. */ 298 static u32 get_ccsidr(struct kvm_vcpu *vcpu, u32 csselr) 299 { 300 u8 line_size; 301 302 if (vcpu->arch.ccsidr) 303 return vcpu->arch.ccsidr[csselr]; 304 305 line_size = get_min_cache_line_size(csselr & CSSELR_EL1_InD); 306 307 /* 308 * Fabricate a CCSIDR value as the overriding value does not exist. 309 * The real CCSIDR value will not be used as it can vary by the 310 * physical CPU which the vcpu currently resides in. 311 * 312 * The line size is determined with get_min_cache_line_size(), which 313 * should be valid for all CPUs even if they have different cache 314 * configuration. 315 * 316 * The associativity bits are cleared, meaning the geometry of all data 317 * and unified caches (which are guaranteed to be PIPT and thus 318 * non-aliasing) are 1 set and 1 way. 319 * Guests should not be doing cache operations by set/way at all, and 320 * for this reason, we trap them and attempt to infer the intent, so 321 * that we can flush the entire guest's address space at the appropriate 322 * time. The exposed geometry minimizes the number of the traps. 323 * [If guests should attempt to infer aliasing properties from the 324 * geometry (which is not permitted by the architecture), they would 325 * only do so for virtually indexed caches.] 326 * 327 * We don't check if the cache level exists as it is allowed to return 328 * an UNKNOWN value if not. 329 */ 330 return SYS_FIELD_PREP(CCSIDR_EL1, LineSize, line_size - 4); 331 } 332 333 static int set_ccsidr(struct kvm_vcpu *vcpu, u32 csselr, u32 val) 334 { 335 u8 line_size = FIELD_GET(CCSIDR_EL1_LineSize, val) + 4; 336 u32 *ccsidr = vcpu->arch.ccsidr; 337 u32 i; 338 339 if ((val & CCSIDR_EL1_RES0) || 340 line_size < get_min_cache_line_size(csselr & CSSELR_EL1_InD)) 341 return -EINVAL; 342 343 if (!ccsidr) { 344 if (val == get_ccsidr(vcpu, csselr)) 345 return 0; 346 347 ccsidr = kmalloc_array(CSSELR_MAX, sizeof(u32), GFP_KERNEL_ACCOUNT); 348 if (!ccsidr) 349 return -ENOMEM; 350 351 for (i = 0; i < CSSELR_MAX; i++) 352 ccsidr[i] = get_ccsidr(vcpu, i); 353 354 vcpu->arch.ccsidr = ccsidr; 355 } 356 357 ccsidr[csselr] = val; 358 359 return 0; 360 } 361 362 static bool access_rw(struct kvm_vcpu *vcpu, 363 struct sys_reg_params *p, 364 const struct sys_reg_desc *r) 365 { 366 if (p->is_write) 367 vcpu_write_sys_reg(vcpu, p->regval, r->reg); 368 else 369 p->regval = vcpu_read_sys_reg(vcpu, r->reg); 370 371 return true; 372 } 373 374 /* 375 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized). 376 */ 377 static bool access_dcsw(struct kvm_vcpu *vcpu, 378 struct sys_reg_params *p, 379 const struct sys_reg_desc *r) 380 { 381 if (!p->is_write) 382 return read_from_write_only(vcpu, p, r); 383 384 /* 385 * Only track S/W ops if we don't have FWB. It still indicates 386 * that the guest is a bit broken (S/W operations should only 387 * be done by firmware, knowing that there is only a single 388 * CPU left in the system, and certainly not from non-secure 389 * software). 390 */ 391 if (!cpus_have_final_cap(ARM64_HAS_STAGE2_FWB)) 392 kvm_set_way_flush(vcpu); 393 394 return true; 395 } 396 397 static bool access_dcgsw(struct kvm_vcpu *vcpu, 398 struct sys_reg_params *p, 399 const struct sys_reg_desc *r) 400 { 401 if (!kvm_has_mte(vcpu->kvm)) 402 return undef_access(vcpu, p, r); 403 404 /* Treat MTE S/W ops as we treat the classic ones: with contempt */ 405 return access_dcsw(vcpu, p, r); 406 } 407 408 static void get_access_mask(const struct sys_reg_desc *r, u64 *mask, u64 *shift) 409 { 410 switch (r->aarch32_map) { 411 case AA32_LO: 412 *mask = GENMASK_ULL(31, 0); 413 *shift = 0; 414 break; 415 case AA32_HI: 416 *mask = GENMASK_ULL(63, 32); 417 *shift = 32; 418 break; 419 default: 420 *mask = GENMASK_ULL(63, 0); 421 *shift = 0; 422 break; 423 } 424 } 425 426 /* 427 * Generic accessor for VM registers. Only called as long as HCR_TVM 428 * is set. If the guest enables the MMU, we stop trapping the VM 429 * sys_regs and leave it in complete control of the caches. 430 */ 431 static bool access_vm_reg(struct kvm_vcpu *vcpu, 432 struct sys_reg_params *p, 433 const struct sys_reg_desc *r) 434 { 435 bool was_enabled = vcpu_has_cache_enabled(vcpu); 436 u64 val, mask, shift; 437 438 BUG_ON(!p->is_write); 439 440 get_access_mask(r, &mask, &shift); 441 442 if (~mask) { 443 val = vcpu_read_sys_reg(vcpu, r->reg); 444 val &= ~mask; 445 } else { 446 val = 0; 447 } 448 449 val |= (p->regval & (mask >> shift)) << shift; 450 vcpu_write_sys_reg(vcpu, val, r->reg); 451 452 kvm_toggle_cache(vcpu, was_enabled); 453 return true; 454 } 455 456 static bool access_actlr(struct kvm_vcpu *vcpu, 457 struct sys_reg_params *p, 458 const struct sys_reg_desc *r) 459 { 460 u64 mask, shift; 461 462 if (p->is_write) 463 return ignore_write(vcpu, p); 464 465 get_access_mask(r, &mask, &shift); 466 p->regval = (vcpu_read_sys_reg(vcpu, r->reg) & mask) >> shift; 467 468 return true; 469 } 470 471 /* 472 * Trap handler for the GICv3 SGI generation system register. 473 * Forward the request to the VGIC emulation. 474 * The cp15_64 code makes sure this automatically works 475 * for both AArch64 and AArch32 accesses. 476 */ 477 static bool access_gic_sgi(struct kvm_vcpu *vcpu, 478 struct sys_reg_params *p, 479 const struct sys_reg_desc *r) 480 { 481 bool g1; 482 483 if (!kvm_has_gicv3(vcpu->kvm)) 484 return undef_access(vcpu, p, r); 485 486 if (!p->is_write) 487 return read_from_write_only(vcpu, p, r); 488 489 /* 490 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates 491 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group, 492 * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively 493 * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure 494 * group. 495 */ 496 if (p->Op0 == 0) { /* AArch32 */ 497 switch (p->Op1) { 498 default: /* Keep GCC quiet */ 499 case 0: /* ICC_SGI1R */ 500 g1 = true; 501 break; 502 case 1: /* ICC_ASGI1R */ 503 case 2: /* ICC_SGI0R */ 504 g1 = false; 505 break; 506 } 507 } else { /* AArch64 */ 508 switch (p->Op2) { 509 default: /* Keep GCC quiet */ 510 case 5: /* ICC_SGI1R_EL1 */ 511 g1 = true; 512 break; 513 case 6: /* ICC_ASGI1R_EL1 */ 514 case 7: /* ICC_SGI0R_EL1 */ 515 g1 = false; 516 break; 517 } 518 } 519 520 vgic_v3_dispatch_sgi(vcpu, p->regval, g1); 521 522 return true; 523 } 524 525 static bool access_gic_sre(struct kvm_vcpu *vcpu, 526 struct sys_reg_params *p, 527 const struct sys_reg_desc *r) 528 { 529 if (!kvm_has_gicv3(vcpu->kvm)) 530 return undef_access(vcpu, p, r); 531 532 if (p->is_write) 533 return ignore_write(vcpu, p); 534 535 if (p->Op1 == 4) { /* ICC_SRE_EL2 */ 536 p->regval = (ICC_SRE_EL2_ENABLE | ICC_SRE_EL2_SRE | 537 ICC_SRE_EL1_DIB | ICC_SRE_EL1_DFB); 538 } else { /* ICC_SRE_EL1 */ 539 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre; 540 } 541 542 return true; 543 } 544 545 static bool trap_raz_wi(struct kvm_vcpu *vcpu, 546 struct sys_reg_params *p, 547 const struct sys_reg_desc *r) 548 { 549 if (p->is_write) 550 return ignore_write(vcpu, p); 551 else 552 return read_zero(vcpu, p); 553 } 554 555 /* 556 * ARMv8.1 mandates at least a trivial LORegion implementation, where all the 557 * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0 558 * system, these registers should UNDEF. LORID_EL1 being a RO register, we 559 * treat it separately. 560 */ 561 static bool trap_loregion(struct kvm_vcpu *vcpu, 562 struct sys_reg_params *p, 563 const struct sys_reg_desc *r) 564 { 565 u32 sr = reg_to_encoding(r); 566 567 if (!kvm_has_feat(vcpu->kvm, ID_AA64MMFR1_EL1, LO, IMP)) 568 return undef_access(vcpu, p, r); 569 570 if (p->is_write && sr == SYS_LORID_EL1) 571 return write_to_read_only(vcpu, p, r); 572 573 return trap_raz_wi(vcpu, p, r); 574 } 575 576 static bool trap_oslar_el1(struct kvm_vcpu *vcpu, 577 struct sys_reg_params *p, 578 const struct sys_reg_desc *r) 579 { 580 if (!p->is_write) 581 return read_from_write_only(vcpu, p, r); 582 583 kvm_debug_handle_oslar(vcpu, p->regval); 584 return true; 585 } 586 587 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu, 588 struct sys_reg_params *p, 589 const struct sys_reg_desc *r) 590 { 591 if (p->is_write) 592 return write_to_read_only(vcpu, p, r); 593 594 p->regval = __vcpu_sys_reg(vcpu, r->reg); 595 return true; 596 } 597 598 static int set_oslsr_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 599 u64 val) 600 { 601 /* 602 * The only modifiable bit is the OSLK bit. Refuse the write if 603 * userspace attempts to change any other bit in the register. 604 */ 605 if ((val ^ rd->val) & ~OSLSR_EL1_OSLK) 606 return -EINVAL; 607 608 __vcpu_sys_reg(vcpu, rd->reg) = val; 609 return 0; 610 } 611 612 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu, 613 struct sys_reg_params *p, 614 const struct sys_reg_desc *r) 615 { 616 if (p->is_write) { 617 return ignore_write(vcpu, p); 618 } else { 619 p->regval = read_sysreg(dbgauthstatus_el1); 620 return true; 621 } 622 } 623 624 static bool trap_debug_regs(struct kvm_vcpu *vcpu, 625 struct sys_reg_params *p, 626 const struct sys_reg_desc *r) 627 { 628 access_rw(vcpu, p, r); 629 630 kvm_debug_set_guest_ownership(vcpu); 631 return true; 632 } 633 634 /* 635 * reg_to_dbg/dbg_to_reg 636 * 637 * A 32 bit write to a debug register leave top bits alone 638 * A 32 bit read from a debug register only returns the bottom bits 639 */ 640 static void reg_to_dbg(struct kvm_vcpu *vcpu, 641 struct sys_reg_params *p, 642 const struct sys_reg_desc *rd, 643 u64 *dbg_reg) 644 { 645 u64 mask, shift, val; 646 647 get_access_mask(rd, &mask, &shift); 648 649 val = *dbg_reg; 650 val &= ~mask; 651 val |= (p->regval & (mask >> shift)) << shift; 652 *dbg_reg = val; 653 } 654 655 static void dbg_to_reg(struct kvm_vcpu *vcpu, 656 struct sys_reg_params *p, 657 const struct sys_reg_desc *rd, 658 u64 *dbg_reg) 659 { 660 u64 mask, shift; 661 662 get_access_mask(rd, &mask, &shift); 663 p->regval = (*dbg_reg & mask) >> shift; 664 } 665 666 static u64 *demux_wb_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd) 667 { 668 struct kvm_guest_debug_arch *dbg = &vcpu->arch.vcpu_debug_state; 669 670 switch (rd->Op2) { 671 case 0b100: 672 return &dbg->dbg_bvr[rd->CRm]; 673 case 0b101: 674 return &dbg->dbg_bcr[rd->CRm]; 675 case 0b110: 676 return &dbg->dbg_wvr[rd->CRm]; 677 case 0b111: 678 return &dbg->dbg_wcr[rd->CRm]; 679 default: 680 KVM_BUG_ON(1, vcpu->kvm); 681 return NULL; 682 } 683 } 684 685 static bool trap_dbg_wb_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 686 const struct sys_reg_desc *rd) 687 { 688 u64 *reg = demux_wb_reg(vcpu, rd); 689 690 if (!reg) 691 return false; 692 693 if (p->is_write) 694 reg_to_dbg(vcpu, p, rd, reg); 695 else 696 dbg_to_reg(vcpu, p, rd, reg); 697 698 kvm_debug_set_guest_ownership(vcpu); 699 return true; 700 } 701 702 static int set_dbg_wb_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 703 u64 val) 704 { 705 u64 *reg = demux_wb_reg(vcpu, rd); 706 707 if (!reg) 708 return -EINVAL; 709 710 *reg = val; 711 return 0; 712 } 713 714 static int get_dbg_wb_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 715 u64 *val) 716 { 717 u64 *reg = demux_wb_reg(vcpu, rd); 718 719 if (!reg) 720 return -EINVAL; 721 722 *val = *reg; 723 return 0; 724 } 725 726 static u64 reset_dbg_wb_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd) 727 { 728 u64 *reg = demux_wb_reg(vcpu, rd); 729 730 /* 731 * Bail early if we couldn't find storage for the register, the 732 * KVM_BUG_ON() in demux_wb_reg() will prevent this VM from ever 733 * being run. 734 */ 735 if (!reg) 736 return 0; 737 738 *reg = rd->val; 739 return rd->val; 740 } 741 742 static u64 reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 743 { 744 u64 amair = read_sysreg(amair_el1); 745 vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1); 746 return amair; 747 } 748 749 static u64 reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 750 { 751 u64 actlr = read_sysreg(actlr_el1); 752 vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1); 753 return actlr; 754 } 755 756 static u64 reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 757 { 758 u64 mpidr; 759 760 /* 761 * Map the vcpu_id into the first three affinity level fields of 762 * the MPIDR. We limit the number of VCPUs in level 0 due to a 763 * limitation to 16 CPUs in that level in the ICC_SGIxR registers 764 * of the GICv3 to be able to address each CPU directly when 765 * sending IPIs. 766 */ 767 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0); 768 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1); 769 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2); 770 mpidr |= (1ULL << 31); 771 vcpu_write_sys_reg(vcpu, mpidr, MPIDR_EL1); 772 773 return mpidr; 774 } 775 776 static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu, 777 const struct sys_reg_desc *r) 778 { 779 if (kvm_vcpu_has_pmu(vcpu)) 780 return 0; 781 782 return REG_HIDDEN; 783 } 784 785 static u64 reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 786 { 787 u64 mask = BIT(ARMV8_PMU_CYCLE_IDX); 788 u8 n = vcpu->kvm->arch.nr_pmu_counters; 789 790 if (n) 791 mask |= GENMASK(n - 1, 0); 792 793 reset_unknown(vcpu, r); 794 __vcpu_sys_reg(vcpu, r->reg) &= mask; 795 796 return __vcpu_sys_reg(vcpu, r->reg); 797 } 798 799 static u64 reset_pmevcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 800 { 801 reset_unknown(vcpu, r); 802 __vcpu_sys_reg(vcpu, r->reg) &= GENMASK(31, 0); 803 804 return __vcpu_sys_reg(vcpu, r->reg); 805 } 806 807 static u64 reset_pmevtyper(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 808 { 809 /* This thing will UNDEF, who cares about the reset value? */ 810 if (!kvm_vcpu_has_pmu(vcpu)) 811 return 0; 812 813 reset_unknown(vcpu, r); 814 __vcpu_sys_reg(vcpu, r->reg) &= kvm_pmu_evtyper_mask(vcpu->kvm); 815 816 return __vcpu_sys_reg(vcpu, r->reg); 817 } 818 819 static u64 reset_pmselr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 820 { 821 reset_unknown(vcpu, r); 822 __vcpu_sys_reg(vcpu, r->reg) &= PMSELR_EL0_SEL_MASK; 823 824 return __vcpu_sys_reg(vcpu, r->reg); 825 } 826 827 static u64 reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 828 { 829 u64 pmcr = 0; 830 831 if (!kvm_supports_32bit_el0()) 832 pmcr |= ARMV8_PMU_PMCR_LC; 833 834 /* 835 * The value of PMCR.N field is included when the 836 * vCPU register is read via kvm_vcpu_read_pmcr(). 837 */ 838 __vcpu_sys_reg(vcpu, r->reg) = pmcr; 839 840 return __vcpu_sys_reg(vcpu, r->reg); 841 } 842 843 static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags) 844 { 845 u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0); 846 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu); 847 848 if (!enabled) 849 kvm_inject_undefined(vcpu); 850 851 return !enabled; 852 } 853 854 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu) 855 { 856 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN); 857 } 858 859 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu) 860 { 861 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN); 862 } 863 864 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu) 865 { 866 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN); 867 } 868 869 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu) 870 { 871 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN); 872 } 873 874 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 875 const struct sys_reg_desc *r) 876 { 877 u64 val; 878 879 if (pmu_access_el0_disabled(vcpu)) 880 return false; 881 882 if (p->is_write) { 883 /* 884 * Only update writeable bits of PMCR (continuing into 885 * kvm_pmu_handle_pmcr() as well) 886 */ 887 val = kvm_vcpu_read_pmcr(vcpu); 888 val &= ~ARMV8_PMU_PMCR_MASK; 889 val |= p->regval & ARMV8_PMU_PMCR_MASK; 890 if (!kvm_supports_32bit_el0()) 891 val |= ARMV8_PMU_PMCR_LC; 892 kvm_pmu_handle_pmcr(vcpu, val); 893 } else { 894 /* PMCR.P & PMCR.C are RAZ */ 895 val = kvm_vcpu_read_pmcr(vcpu) 896 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C); 897 p->regval = val; 898 } 899 900 return true; 901 } 902 903 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 904 const struct sys_reg_desc *r) 905 { 906 if (pmu_access_event_counter_el0_disabled(vcpu)) 907 return false; 908 909 if (p->is_write) 910 __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval; 911 else 912 /* return PMSELR.SEL field */ 913 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0) 914 & PMSELR_EL0_SEL_MASK; 915 916 return true; 917 } 918 919 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 920 const struct sys_reg_desc *r) 921 { 922 u64 pmceid, mask, shift; 923 924 BUG_ON(p->is_write); 925 926 if (pmu_access_el0_disabled(vcpu)) 927 return false; 928 929 get_access_mask(r, &mask, &shift); 930 931 pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1)); 932 pmceid &= mask; 933 pmceid >>= shift; 934 935 p->regval = pmceid; 936 937 return true; 938 } 939 940 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx) 941 { 942 u64 pmcr, val; 943 944 pmcr = kvm_vcpu_read_pmcr(vcpu); 945 val = FIELD_GET(ARMV8_PMU_PMCR_N, pmcr); 946 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) { 947 kvm_inject_undefined(vcpu); 948 return false; 949 } 950 951 return true; 952 } 953 954 static int get_pmu_evcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 955 u64 *val) 956 { 957 u64 idx; 958 959 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 0) 960 /* PMCCNTR_EL0 */ 961 idx = ARMV8_PMU_CYCLE_IDX; 962 else 963 /* PMEVCNTRn_EL0 */ 964 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 965 966 *val = kvm_pmu_get_counter_value(vcpu, idx); 967 return 0; 968 } 969 970 static int set_pmu_evcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 971 u64 val) 972 { 973 u64 idx; 974 975 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 0) 976 /* PMCCNTR_EL0 */ 977 idx = ARMV8_PMU_CYCLE_IDX; 978 else 979 /* PMEVCNTRn_EL0 */ 980 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 981 982 kvm_pmu_set_counter_value_user(vcpu, idx, val); 983 return 0; 984 } 985 986 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu, 987 struct sys_reg_params *p, 988 const struct sys_reg_desc *r) 989 { 990 u64 idx = ~0UL; 991 992 if (r->CRn == 9 && r->CRm == 13) { 993 if (r->Op2 == 2) { 994 /* PMXEVCNTR_EL0 */ 995 if (pmu_access_event_counter_el0_disabled(vcpu)) 996 return false; 997 998 idx = SYS_FIELD_GET(PMSELR_EL0, SEL, 999 __vcpu_sys_reg(vcpu, PMSELR_EL0)); 1000 } else if (r->Op2 == 0) { 1001 /* PMCCNTR_EL0 */ 1002 if (pmu_access_cycle_counter_el0_disabled(vcpu)) 1003 return false; 1004 1005 idx = ARMV8_PMU_CYCLE_IDX; 1006 } 1007 } else if (r->CRn == 0 && r->CRm == 9) { 1008 /* PMCCNTR */ 1009 if (pmu_access_event_counter_el0_disabled(vcpu)) 1010 return false; 1011 1012 idx = ARMV8_PMU_CYCLE_IDX; 1013 } else if (r->CRn == 14 && (r->CRm & 12) == 8) { 1014 /* PMEVCNTRn_EL0 */ 1015 if (pmu_access_event_counter_el0_disabled(vcpu)) 1016 return false; 1017 1018 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 1019 } 1020 1021 /* Catch any decoding mistake */ 1022 WARN_ON(idx == ~0UL); 1023 1024 if (!pmu_counter_idx_valid(vcpu, idx)) 1025 return false; 1026 1027 if (p->is_write) { 1028 if (pmu_access_el0_disabled(vcpu)) 1029 return false; 1030 1031 kvm_pmu_set_counter_value(vcpu, idx, p->regval); 1032 } else { 1033 p->regval = kvm_pmu_get_counter_value(vcpu, idx); 1034 } 1035 1036 return true; 1037 } 1038 1039 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1040 const struct sys_reg_desc *r) 1041 { 1042 u64 idx, reg; 1043 1044 if (pmu_access_el0_disabled(vcpu)) 1045 return false; 1046 1047 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) { 1048 /* PMXEVTYPER_EL0 */ 1049 idx = SYS_FIELD_GET(PMSELR_EL0, SEL, __vcpu_sys_reg(vcpu, PMSELR_EL0)); 1050 reg = PMEVTYPER0_EL0 + idx; 1051 } else if (r->CRn == 14 && (r->CRm & 12) == 12) { 1052 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 1053 if (idx == ARMV8_PMU_CYCLE_IDX) 1054 reg = PMCCFILTR_EL0; 1055 else 1056 /* PMEVTYPERn_EL0 */ 1057 reg = PMEVTYPER0_EL0 + idx; 1058 } else { 1059 BUG(); 1060 } 1061 1062 if (!pmu_counter_idx_valid(vcpu, idx)) 1063 return false; 1064 1065 if (p->is_write) { 1066 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx); 1067 kvm_vcpu_pmu_restore_guest(vcpu); 1068 } else { 1069 p->regval = __vcpu_sys_reg(vcpu, reg); 1070 } 1071 1072 return true; 1073 } 1074 1075 static int set_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 val) 1076 { 1077 u64 mask = kvm_pmu_accessible_counter_mask(vcpu); 1078 1079 __vcpu_sys_reg(vcpu, r->reg) = val & mask; 1080 kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu); 1081 1082 return 0; 1083 } 1084 1085 static int get_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 *val) 1086 { 1087 u64 mask = kvm_pmu_accessible_counter_mask(vcpu); 1088 1089 *val = __vcpu_sys_reg(vcpu, r->reg) & mask; 1090 return 0; 1091 } 1092 1093 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1094 const struct sys_reg_desc *r) 1095 { 1096 u64 val, mask; 1097 1098 if (pmu_access_el0_disabled(vcpu)) 1099 return false; 1100 1101 mask = kvm_pmu_accessible_counter_mask(vcpu); 1102 if (p->is_write) { 1103 val = p->regval & mask; 1104 if (r->Op2 & 0x1) 1105 /* accessing PMCNTENSET_EL0 */ 1106 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val; 1107 else 1108 /* accessing PMCNTENCLR_EL0 */ 1109 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val; 1110 1111 kvm_pmu_reprogram_counter_mask(vcpu, val); 1112 } else { 1113 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0); 1114 } 1115 1116 return true; 1117 } 1118 1119 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1120 const struct sys_reg_desc *r) 1121 { 1122 u64 mask = kvm_pmu_accessible_counter_mask(vcpu); 1123 1124 if (check_pmu_access_disabled(vcpu, 0)) 1125 return false; 1126 1127 if (p->is_write) { 1128 u64 val = p->regval & mask; 1129 1130 if (r->Op2 & 0x1) 1131 /* accessing PMINTENSET_EL1 */ 1132 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val; 1133 else 1134 /* accessing PMINTENCLR_EL1 */ 1135 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val; 1136 } else { 1137 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1); 1138 } 1139 1140 return true; 1141 } 1142 1143 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1144 const struct sys_reg_desc *r) 1145 { 1146 u64 mask = kvm_pmu_accessible_counter_mask(vcpu); 1147 1148 if (pmu_access_el0_disabled(vcpu)) 1149 return false; 1150 1151 if (p->is_write) { 1152 if (r->CRm & 0x2) 1153 /* accessing PMOVSSET_EL0 */ 1154 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask); 1155 else 1156 /* accessing PMOVSCLR_EL0 */ 1157 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask); 1158 } else { 1159 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0); 1160 } 1161 1162 return true; 1163 } 1164 1165 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1166 const struct sys_reg_desc *r) 1167 { 1168 u64 mask; 1169 1170 if (!p->is_write) 1171 return read_from_write_only(vcpu, p, r); 1172 1173 if (pmu_write_swinc_el0_disabled(vcpu)) 1174 return false; 1175 1176 mask = kvm_pmu_accessible_counter_mask(vcpu); 1177 kvm_pmu_software_increment(vcpu, p->regval & mask); 1178 return true; 1179 } 1180 1181 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1182 const struct sys_reg_desc *r) 1183 { 1184 if (p->is_write) { 1185 if (!vcpu_mode_priv(vcpu)) 1186 return undef_access(vcpu, p, r); 1187 1188 __vcpu_sys_reg(vcpu, PMUSERENR_EL0) = 1189 p->regval & ARMV8_PMU_USERENR_MASK; 1190 } else { 1191 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0) 1192 & ARMV8_PMU_USERENR_MASK; 1193 } 1194 1195 return true; 1196 } 1197 1198 static int get_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 1199 u64 *val) 1200 { 1201 *val = kvm_vcpu_read_pmcr(vcpu); 1202 return 0; 1203 } 1204 1205 static int set_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 1206 u64 val) 1207 { 1208 u8 new_n = FIELD_GET(ARMV8_PMU_PMCR_N, val); 1209 struct kvm *kvm = vcpu->kvm; 1210 1211 mutex_lock(&kvm->arch.config_lock); 1212 1213 /* 1214 * The vCPU can't have more counters than the PMU hardware 1215 * implements. Ignore this error to maintain compatibility 1216 * with the existing KVM behavior. 1217 */ 1218 if (!kvm_vm_has_ran_once(kvm) && 1219 !vcpu_has_nv(vcpu) && 1220 new_n <= kvm_arm_pmu_get_max_counters(kvm)) 1221 kvm->arch.nr_pmu_counters = new_n; 1222 1223 mutex_unlock(&kvm->arch.config_lock); 1224 1225 /* 1226 * Ignore writes to RES0 bits, read only bits that are cleared on 1227 * vCPU reset, and writable bits that KVM doesn't support yet. 1228 * (i.e. only PMCR.N and bits [7:0] are mutable from userspace) 1229 * The LP bit is RES0 when FEAT_PMUv3p5 is not supported on the vCPU. 1230 * But, we leave the bit as it is here, as the vCPU's PMUver might 1231 * be changed later (NOTE: the bit will be cleared on first vCPU run 1232 * if necessary). 1233 */ 1234 val &= ARMV8_PMU_PMCR_MASK; 1235 1236 /* The LC bit is RES1 when AArch32 is not supported */ 1237 if (!kvm_supports_32bit_el0()) 1238 val |= ARMV8_PMU_PMCR_LC; 1239 1240 __vcpu_sys_reg(vcpu, r->reg) = val; 1241 kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu); 1242 1243 return 0; 1244 } 1245 1246 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */ 1247 #define DBG_BCR_BVR_WCR_WVR_EL1(n) \ 1248 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \ 1249 trap_dbg_wb_reg, reset_dbg_wb_reg, 0, 0, \ 1250 get_dbg_wb_reg, set_dbg_wb_reg }, \ 1251 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \ 1252 trap_dbg_wb_reg, reset_dbg_wb_reg, 0, 0, \ 1253 get_dbg_wb_reg, set_dbg_wb_reg }, \ 1254 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \ 1255 trap_dbg_wb_reg, reset_dbg_wb_reg, 0, 0, \ 1256 get_dbg_wb_reg, set_dbg_wb_reg }, \ 1257 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \ 1258 trap_dbg_wb_reg, reset_dbg_wb_reg, 0, 0, \ 1259 get_dbg_wb_reg, set_dbg_wb_reg } 1260 1261 #define PMU_SYS_REG(name) \ 1262 SYS_DESC(SYS_##name), .reset = reset_pmu_reg, \ 1263 .visibility = pmu_visibility 1264 1265 /* Macro to expand the PMEVCNTRn_EL0 register */ 1266 #define PMU_PMEVCNTR_EL0(n) \ 1267 { PMU_SYS_REG(PMEVCNTRn_EL0(n)), \ 1268 .reset = reset_pmevcntr, .get_user = get_pmu_evcntr, \ 1269 .set_user = set_pmu_evcntr, \ 1270 .access = access_pmu_evcntr, .reg = (PMEVCNTR0_EL0 + n), } 1271 1272 /* Macro to expand the PMEVTYPERn_EL0 register */ 1273 #define PMU_PMEVTYPER_EL0(n) \ 1274 { PMU_SYS_REG(PMEVTYPERn_EL0(n)), \ 1275 .reset = reset_pmevtyper, \ 1276 .access = access_pmu_evtyper, .reg = (PMEVTYPER0_EL0 + n), } 1277 1278 /* Macro to expand the AMU counter and type registers*/ 1279 #define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), undef_access } 1280 #define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), undef_access } 1281 #define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), undef_access } 1282 #define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), undef_access } 1283 1284 static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu, 1285 const struct sys_reg_desc *rd) 1286 { 1287 return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN; 1288 } 1289 1290 /* 1291 * If we land here on a PtrAuth access, that is because we didn't 1292 * fixup the access on exit by allowing the PtrAuth sysregs. The only 1293 * way this happens is when the guest does not have PtrAuth support 1294 * enabled. 1295 */ 1296 #define __PTRAUTH_KEY(k) \ 1297 { SYS_DESC(SYS_## k), undef_access, reset_unknown, k, \ 1298 .visibility = ptrauth_visibility} 1299 1300 #define PTRAUTH_KEY(k) \ 1301 __PTRAUTH_KEY(k ## KEYLO_EL1), \ 1302 __PTRAUTH_KEY(k ## KEYHI_EL1) 1303 1304 static bool access_arch_timer(struct kvm_vcpu *vcpu, 1305 struct sys_reg_params *p, 1306 const struct sys_reg_desc *r) 1307 { 1308 enum kvm_arch_timers tmr; 1309 enum kvm_arch_timer_regs treg; 1310 u64 reg = reg_to_encoding(r); 1311 1312 switch (reg) { 1313 case SYS_CNTP_TVAL_EL0: 1314 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) 1315 tmr = TIMER_HPTIMER; 1316 else 1317 tmr = TIMER_PTIMER; 1318 treg = TIMER_REG_TVAL; 1319 break; 1320 1321 case SYS_CNTV_TVAL_EL0: 1322 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) 1323 tmr = TIMER_HVTIMER; 1324 else 1325 tmr = TIMER_VTIMER; 1326 treg = TIMER_REG_TVAL; 1327 break; 1328 1329 case SYS_AARCH32_CNTP_TVAL: 1330 case SYS_CNTP_TVAL_EL02: 1331 tmr = TIMER_PTIMER; 1332 treg = TIMER_REG_TVAL; 1333 break; 1334 1335 case SYS_CNTV_TVAL_EL02: 1336 tmr = TIMER_VTIMER; 1337 treg = TIMER_REG_TVAL; 1338 break; 1339 1340 case SYS_CNTHP_TVAL_EL2: 1341 tmr = TIMER_HPTIMER; 1342 treg = TIMER_REG_TVAL; 1343 break; 1344 1345 case SYS_CNTHV_TVAL_EL2: 1346 tmr = TIMER_HVTIMER; 1347 treg = TIMER_REG_TVAL; 1348 break; 1349 1350 case SYS_CNTP_CTL_EL0: 1351 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) 1352 tmr = TIMER_HPTIMER; 1353 else 1354 tmr = TIMER_PTIMER; 1355 treg = TIMER_REG_CTL; 1356 break; 1357 1358 case SYS_CNTV_CTL_EL0: 1359 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) 1360 tmr = TIMER_HVTIMER; 1361 else 1362 tmr = TIMER_VTIMER; 1363 treg = TIMER_REG_CTL; 1364 break; 1365 1366 case SYS_AARCH32_CNTP_CTL: 1367 case SYS_CNTP_CTL_EL02: 1368 tmr = TIMER_PTIMER; 1369 treg = TIMER_REG_CTL; 1370 break; 1371 1372 case SYS_CNTV_CTL_EL02: 1373 tmr = TIMER_VTIMER; 1374 treg = TIMER_REG_CTL; 1375 break; 1376 1377 case SYS_CNTHP_CTL_EL2: 1378 tmr = TIMER_HPTIMER; 1379 treg = TIMER_REG_CTL; 1380 break; 1381 1382 case SYS_CNTHV_CTL_EL2: 1383 tmr = TIMER_HVTIMER; 1384 treg = TIMER_REG_CTL; 1385 break; 1386 1387 case SYS_CNTP_CVAL_EL0: 1388 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) 1389 tmr = TIMER_HPTIMER; 1390 else 1391 tmr = TIMER_PTIMER; 1392 treg = TIMER_REG_CVAL; 1393 break; 1394 1395 case SYS_CNTV_CVAL_EL0: 1396 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) 1397 tmr = TIMER_HVTIMER; 1398 else 1399 tmr = TIMER_VTIMER; 1400 treg = TIMER_REG_CVAL; 1401 break; 1402 1403 case SYS_AARCH32_CNTP_CVAL: 1404 case SYS_CNTP_CVAL_EL02: 1405 tmr = TIMER_PTIMER; 1406 treg = TIMER_REG_CVAL; 1407 break; 1408 1409 case SYS_CNTV_CVAL_EL02: 1410 tmr = TIMER_VTIMER; 1411 treg = TIMER_REG_CVAL; 1412 break; 1413 1414 case SYS_CNTHP_CVAL_EL2: 1415 tmr = TIMER_HPTIMER; 1416 treg = TIMER_REG_CVAL; 1417 break; 1418 1419 case SYS_CNTHV_CVAL_EL2: 1420 tmr = TIMER_HVTIMER; 1421 treg = TIMER_REG_CVAL; 1422 break; 1423 1424 case SYS_CNTPCT_EL0: 1425 case SYS_CNTPCTSS_EL0: 1426 if (is_hyp_ctxt(vcpu)) 1427 tmr = TIMER_HPTIMER; 1428 else 1429 tmr = TIMER_PTIMER; 1430 treg = TIMER_REG_CNT; 1431 break; 1432 1433 case SYS_AARCH32_CNTPCT: 1434 case SYS_AARCH32_CNTPCTSS: 1435 tmr = TIMER_PTIMER; 1436 treg = TIMER_REG_CNT; 1437 break; 1438 1439 case SYS_CNTVCT_EL0: 1440 case SYS_CNTVCTSS_EL0: 1441 if (is_hyp_ctxt(vcpu)) 1442 tmr = TIMER_HVTIMER; 1443 else 1444 tmr = TIMER_VTIMER; 1445 treg = TIMER_REG_CNT; 1446 break; 1447 1448 case SYS_AARCH32_CNTVCT: 1449 case SYS_AARCH32_CNTVCTSS: 1450 tmr = TIMER_VTIMER; 1451 treg = TIMER_REG_CNT; 1452 break; 1453 1454 default: 1455 print_sys_reg_msg(p, "%s", "Unhandled trapped timer register"); 1456 return undef_access(vcpu, p, r); 1457 } 1458 1459 if (p->is_write) 1460 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval); 1461 else 1462 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg); 1463 1464 return true; 1465 } 1466 1467 static bool access_hv_timer(struct kvm_vcpu *vcpu, 1468 struct sys_reg_params *p, 1469 const struct sys_reg_desc *r) 1470 { 1471 if (!vcpu_el2_e2h_is_set(vcpu)) 1472 return undef_access(vcpu, p, r); 1473 1474 return access_arch_timer(vcpu, p, r); 1475 } 1476 1477 static s64 kvm_arm64_ftr_safe_value(u32 id, const struct arm64_ftr_bits *ftrp, 1478 s64 new, s64 cur) 1479 { 1480 struct arm64_ftr_bits kvm_ftr = *ftrp; 1481 1482 /* Some features have different safe value type in KVM than host features */ 1483 switch (id) { 1484 case SYS_ID_AA64DFR0_EL1: 1485 switch (kvm_ftr.shift) { 1486 case ID_AA64DFR0_EL1_PMUVer_SHIFT: 1487 kvm_ftr.type = FTR_LOWER_SAFE; 1488 break; 1489 case ID_AA64DFR0_EL1_DebugVer_SHIFT: 1490 kvm_ftr.type = FTR_LOWER_SAFE; 1491 break; 1492 } 1493 break; 1494 case SYS_ID_DFR0_EL1: 1495 if (kvm_ftr.shift == ID_DFR0_EL1_PerfMon_SHIFT) 1496 kvm_ftr.type = FTR_LOWER_SAFE; 1497 break; 1498 } 1499 1500 return arm64_ftr_safe_value(&kvm_ftr, new, cur); 1501 } 1502 1503 /* 1504 * arm64_check_features() - Check if a feature register value constitutes 1505 * a subset of features indicated by the idreg's KVM sanitised limit. 1506 * 1507 * This function will check if each feature field of @val is the "safe" value 1508 * against idreg's KVM sanitised limit return from reset() callback. 1509 * If a field value in @val is the same as the one in limit, it is always 1510 * considered the safe value regardless For register fields that are not in 1511 * writable, only the value in limit is considered the safe value. 1512 * 1513 * Return: 0 if all the fields are safe. Otherwise, return negative errno. 1514 */ 1515 static int arm64_check_features(struct kvm_vcpu *vcpu, 1516 const struct sys_reg_desc *rd, 1517 u64 val) 1518 { 1519 const struct arm64_ftr_reg *ftr_reg; 1520 const struct arm64_ftr_bits *ftrp = NULL; 1521 u32 id = reg_to_encoding(rd); 1522 u64 writable_mask = rd->val; 1523 u64 limit = rd->reset(vcpu, rd); 1524 u64 mask = 0; 1525 1526 /* 1527 * Hidden and unallocated ID registers may not have a corresponding 1528 * struct arm64_ftr_reg. Of course, if the register is RAZ we know the 1529 * only safe value is 0. 1530 */ 1531 if (sysreg_visible_as_raz(vcpu, rd)) 1532 return val ? -E2BIG : 0; 1533 1534 ftr_reg = get_arm64_ftr_reg(id); 1535 if (!ftr_reg) 1536 return -EINVAL; 1537 1538 ftrp = ftr_reg->ftr_bits; 1539 1540 for (; ftrp && ftrp->width; ftrp++) { 1541 s64 f_val, f_lim, safe_val; 1542 u64 ftr_mask; 1543 1544 ftr_mask = arm64_ftr_mask(ftrp); 1545 if ((ftr_mask & writable_mask) != ftr_mask) 1546 continue; 1547 1548 f_val = arm64_ftr_value(ftrp, val); 1549 f_lim = arm64_ftr_value(ftrp, limit); 1550 mask |= ftr_mask; 1551 1552 if (f_val == f_lim) 1553 safe_val = f_val; 1554 else 1555 safe_val = kvm_arm64_ftr_safe_value(id, ftrp, f_val, f_lim); 1556 1557 if (safe_val != f_val) 1558 return -E2BIG; 1559 } 1560 1561 /* For fields that are not writable, values in limit are the safe values. */ 1562 if ((val & ~mask) != (limit & ~mask)) 1563 return -E2BIG; 1564 1565 return 0; 1566 } 1567 1568 static u8 pmuver_to_perfmon(u8 pmuver) 1569 { 1570 switch (pmuver) { 1571 case ID_AA64DFR0_EL1_PMUVer_IMP: 1572 return ID_DFR0_EL1_PerfMon_PMUv3; 1573 case ID_AA64DFR0_EL1_PMUVer_IMP_DEF: 1574 return ID_DFR0_EL1_PerfMon_IMPDEF; 1575 default: 1576 /* Anything ARMv8.1+ and NI have the same value. For now. */ 1577 return pmuver; 1578 } 1579 } 1580 1581 static u64 sanitise_id_aa64pfr0_el1(const struct kvm_vcpu *vcpu, u64 val); 1582 static u64 sanitise_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, u64 val); 1583 1584 /* Read a sanitised cpufeature ID register by sys_reg_desc */ 1585 static u64 __kvm_read_sanitised_id_reg(const struct kvm_vcpu *vcpu, 1586 const struct sys_reg_desc *r) 1587 { 1588 u32 id = reg_to_encoding(r); 1589 u64 val; 1590 1591 if (sysreg_visible_as_raz(vcpu, r)) 1592 return 0; 1593 1594 val = read_sanitised_ftr_reg(id); 1595 1596 switch (id) { 1597 case SYS_ID_AA64DFR0_EL1: 1598 val = sanitise_id_aa64dfr0_el1(vcpu, val); 1599 break; 1600 case SYS_ID_AA64PFR0_EL1: 1601 val = sanitise_id_aa64pfr0_el1(vcpu, val); 1602 break; 1603 case SYS_ID_AA64PFR1_EL1: 1604 if (!kvm_has_mte(vcpu->kvm)) { 1605 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE); 1606 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE_frac); 1607 } 1608 1609 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_SME); 1610 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_RNDR_trap); 1611 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_NMI); 1612 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_GCS); 1613 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_THE); 1614 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTEX); 1615 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_DF2); 1616 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_PFAR); 1617 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MPAM_frac); 1618 break; 1619 case SYS_ID_AA64PFR2_EL1: 1620 val &= ID_AA64PFR2_EL1_FPMR | 1621 (kvm_has_mte(vcpu->kvm) ? 1622 ID_AA64PFR2_EL1_MTEFAR | ID_AA64PFR2_EL1_MTESTOREONLY : 1623 0); 1624 break; 1625 case SYS_ID_AA64ISAR1_EL1: 1626 if (!vcpu_has_ptrauth(vcpu)) 1627 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) | 1628 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) | 1629 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) | 1630 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI)); 1631 break; 1632 case SYS_ID_AA64ISAR2_EL1: 1633 if (!vcpu_has_ptrauth(vcpu)) 1634 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) | 1635 ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3)); 1636 if (!cpus_have_final_cap(ARM64_HAS_WFXT) || 1637 has_broken_cntvoff()) 1638 val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT); 1639 break; 1640 case SYS_ID_AA64ISAR3_EL1: 1641 val &= ID_AA64ISAR3_EL1_FPRCVT | ID_AA64ISAR3_EL1_FAMINMAX; 1642 break; 1643 case SYS_ID_AA64MMFR2_EL1: 1644 val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK; 1645 val &= ~ID_AA64MMFR2_EL1_NV; 1646 break; 1647 case SYS_ID_AA64MMFR3_EL1: 1648 val &= ID_AA64MMFR3_EL1_TCRX | ID_AA64MMFR3_EL1_S1POE | 1649 ID_AA64MMFR3_EL1_S1PIE; 1650 break; 1651 case SYS_ID_MMFR4_EL1: 1652 val &= ~ARM64_FEATURE_MASK(ID_MMFR4_EL1_CCIDX); 1653 break; 1654 } 1655 1656 if (vcpu_has_nv(vcpu)) 1657 val = limit_nv_id_reg(vcpu->kvm, id, val); 1658 1659 return val; 1660 } 1661 1662 static u64 kvm_read_sanitised_id_reg(struct kvm_vcpu *vcpu, 1663 const struct sys_reg_desc *r) 1664 { 1665 return __kvm_read_sanitised_id_reg(vcpu, r); 1666 } 1667 1668 static u64 read_id_reg(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 1669 { 1670 return kvm_read_vm_id_reg(vcpu->kvm, reg_to_encoding(r)); 1671 } 1672 1673 static bool is_feature_id_reg(u32 encoding) 1674 { 1675 return (sys_reg_Op0(encoding) == 3 && 1676 (sys_reg_Op1(encoding) < 2 || sys_reg_Op1(encoding) == 3) && 1677 sys_reg_CRn(encoding) == 0 && 1678 sys_reg_CRm(encoding) <= 7); 1679 } 1680 1681 /* 1682 * Return true if the register's (Op0, Op1, CRn, CRm, Op2) is 1683 * (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8, which is the range of ID 1684 * registers KVM maintains on a per-VM basis. 1685 * 1686 * Additionally, the implementation ID registers and CTR_EL0 are handled as 1687 * per-VM registers. 1688 */ 1689 static inline bool is_vm_ftr_id_reg(u32 id) 1690 { 1691 switch (id) { 1692 case SYS_CTR_EL0: 1693 case SYS_MIDR_EL1: 1694 case SYS_REVIDR_EL1: 1695 case SYS_AIDR_EL1: 1696 return true; 1697 default: 1698 return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 && 1699 sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 && 1700 sys_reg_CRm(id) < 8); 1701 1702 } 1703 } 1704 1705 static inline bool is_vcpu_ftr_id_reg(u32 id) 1706 { 1707 return is_feature_id_reg(id) && !is_vm_ftr_id_reg(id); 1708 } 1709 1710 static inline bool is_aa32_id_reg(u32 id) 1711 { 1712 return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 && 1713 sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 && 1714 sys_reg_CRm(id) <= 3); 1715 } 1716 1717 static unsigned int id_visibility(const struct kvm_vcpu *vcpu, 1718 const struct sys_reg_desc *r) 1719 { 1720 u32 id = reg_to_encoding(r); 1721 1722 switch (id) { 1723 case SYS_ID_AA64ZFR0_EL1: 1724 if (!vcpu_has_sve(vcpu)) 1725 return REG_RAZ; 1726 break; 1727 } 1728 1729 return 0; 1730 } 1731 1732 static unsigned int aa32_id_visibility(const struct kvm_vcpu *vcpu, 1733 const struct sys_reg_desc *r) 1734 { 1735 /* 1736 * AArch32 ID registers are UNKNOWN if AArch32 isn't implemented at any 1737 * EL. Promote to RAZ/WI in order to guarantee consistency between 1738 * systems. 1739 */ 1740 if (!kvm_supports_32bit_el0()) 1741 return REG_RAZ | REG_USER_WI; 1742 1743 return id_visibility(vcpu, r); 1744 } 1745 1746 static unsigned int raz_visibility(const struct kvm_vcpu *vcpu, 1747 const struct sys_reg_desc *r) 1748 { 1749 return REG_RAZ; 1750 } 1751 1752 /* cpufeature ID register access trap handlers */ 1753 1754 static bool access_id_reg(struct kvm_vcpu *vcpu, 1755 struct sys_reg_params *p, 1756 const struct sys_reg_desc *r) 1757 { 1758 if (p->is_write) 1759 return write_to_read_only(vcpu, p, r); 1760 1761 p->regval = read_id_reg(vcpu, r); 1762 1763 return true; 1764 } 1765 1766 /* Visibility overrides for SVE-specific control registers */ 1767 static unsigned int sve_visibility(const struct kvm_vcpu *vcpu, 1768 const struct sys_reg_desc *rd) 1769 { 1770 if (vcpu_has_sve(vcpu)) 1771 return 0; 1772 1773 return REG_HIDDEN; 1774 } 1775 1776 static unsigned int sme_visibility(const struct kvm_vcpu *vcpu, 1777 const struct sys_reg_desc *rd) 1778 { 1779 if (kvm_has_feat(vcpu->kvm, ID_AA64PFR1_EL1, SME, IMP)) 1780 return 0; 1781 1782 return REG_HIDDEN; 1783 } 1784 1785 static unsigned int fp8_visibility(const struct kvm_vcpu *vcpu, 1786 const struct sys_reg_desc *rd) 1787 { 1788 if (kvm_has_fpmr(vcpu->kvm)) 1789 return 0; 1790 1791 return REG_HIDDEN; 1792 } 1793 1794 static u64 sanitise_id_aa64pfr0_el1(const struct kvm_vcpu *vcpu, u64 val) 1795 { 1796 if (!vcpu_has_sve(vcpu)) 1797 val &= ~ID_AA64PFR0_EL1_SVE_MASK; 1798 1799 /* 1800 * The default is to expose CSV2 == 1 if the HW isn't affected. 1801 * Although this is a per-CPU feature, we make it global because 1802 * asymmetric systems are just a nuisance. 1803 * 1804 * Userspace can override this as long as it doesn't promise 1805 * the impossible. 1806 */ 1807 if (arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED) { 1808 val &= ~ID_AA64PFR0_EL1_CSV2_MASK; 1809 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV2, IMP); 1810 } 1811 if (arm64_get_meltdown_state() == SPECTRE_UNAFFECTED) { 1812 val &= ~ID_AA64PFR0_EL1_CSV3_MASK; 1813 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV3, IMP); 1814 } 1815 1816 if (kvm_vgic_global_state.type == VGIC_V3) { 1817 val &= ~ID_AA64PFR0_EL1_GIC_MASK; 1818 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, GIC, IMP); 1819 } 1820 1821 val &= ~ID_AA64PFR0_EL1_AMU_MASK; 1822 1823 /* 1824 * MPAM is disabled by default as KVM also needs a set of PARTID to 1825 * program the MPAMVPMx_EL2 PARTID remapping registers with. But some 1826 * older kernels let the guest see the ID bit. 1827 */ 1828 val &= ~ID_AA64PFR0_EL1_MPAM_MASK; 1829 1830 return val; 1831 } 1832 1833 static u64 sanitise_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, u64 val) 1834 { 1835 val = ID_REG_LIMIT_FIELD_ENUM(val, ID_AA64DFR0_EL1, DebugVer, V8P8); 1836 1837 /* 1838 * Only initialize the PMU version if the vCPU was configured with one. 1839 */ 1840 val &= ~ID_AA64DFR0_EL1_PMUVer_MASK; 1841 if (kvm_vcpu_has_pmu(vcpu)) 1842 val |= SYS_FIELD_PREP(ID_AA64DFR0_EL1, PMUVer, 1843 kvm_arm_pmu_get_pmuver_limit()); 1844 1845 /* Hide SPE from guests */ 1846 val &= ~ID_AA64DFR0_EL1_PMSVer_MASK; 1847 1848 /* Hide BRBE from guests */ 1849 val &= ~ID_AA64DFR0_EL1_BRBE_MASK; 1850 1851 return val; 1852 } 1853 1854 static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, 1855 const struct sys_reg_desc *rd, 1856 u64 val) 1857 { 1858 u8 debugver = SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, val); 1859 u8 pmuver = SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, val); 1860 1861 /* 1862 * Prior to commit 3d0dba5764b9 ("KVM: arm64: PMU: Move the 1863 * ID_AA64DFR0_EL1.PMUver limit to VM creation"), KVM erroneously 1864 * exposed an IMP_DEF PMU to userspace and the guest on systems w/ 1865 * non-architectural PMUs. Of course, PMUv3 is the only game in town for 1866 * PMU virtualization, so the IMP_DEF value was rather user-hostile. 1867 * 1868 * At minimum, we're on the hook to allow values that were given to 1869 * userspace by KVM. Cover our tracks here and replace the IMP_DEF value 1870 * with a more sensible NI. The value of an ID register changing under 1871 * the nose of the guest is unfortunate, but is certainly no more 1872 * surprising than an ill-guided PMU driver poking at impdef system 1873 * registers that end in an UNDEF... 1874 */ 1875 if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF) 1876 val &= ~ID_AA64DFR0_EL1_PMUVer_MASK; 1877 1878 /* 1879 * ID_AA64DFR0_EL1.DebugVer is one of those awkward fields with a 1880 * nonzero minimum safe value. 1881 */ 1882 if (debugver < ID_AA64DFR0_EL1_DebugVer_IMP) 1883 return -EINVAL; 1884 1885 return set_id_reg(vcpu, rd, val); 1886 } 1887 1888 static u64 read_sanitised_id_dfr0_el1(struct kvm_vcpu *vcpu, 1889 const struct sys_reg_desc *rd) 1890 { 1891 u8 perfmon; 1892 u64 val = read_sanitised_ftr_reg(SYS_ID_DFR0_EL1); 1893 1894 val &= ~ID_DFR0_EL1_PerfMon_MASK; 1895 if (kvm_vcpu_has_pmu(vcpu)) { 1896 perfmon = pmuver_to_perfmon(kvm_arm_pmu_get_pmuver_limit()); 1897 val |= SYS_FIELD_PREP(ID_DFR0_EL1, PerfMon, perfmon); 1898 } 1899 1900 val = ID_REG_LIMIT_FIELD_ENUM(val, ID_DFR0_EL1, CopDbg, Debugv8p8); 1901 1902 return val; 1903 } 1904 1905 static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, 1906 const struct sys_reg_desc *rd, 1907 u64 val) 1908 { 1909 u8 perfmon = SYS_FIELD_GET(ID_DFR0_EL1, PerfMon, val); 1910 u8 copdbg = SYS_FIELD_GET(ID_DFR0_EL1, CopDbg, val); 1911 1912 if (perfmon == ID_DFR0_EL1_PerfMon_IMPDEF) { 1913 val &= ~ID_DFR0_EL1_PerfMon_MASK; 1914 perfmon = 0; 1915 } 1916 1917 /* 1918 * Allow DFR0_EL1.PerfMon to be set from userspace as long as 1919 * it doesn't promise more than what the HW gives us on the 1920 * AArch64 side (as everything is emulated with that), and 1921 * that this is a PMUv3. 1922 */ 1923 if (perfmon != 0 && perfmon < ID_DFR0_EL1_PerfMon_PMUv3) 1924 return -EINVAL; 1925 1926 if (copdbg < ID_DFR0_EL1_CopDbg_Armv8) 1927 return -EINVAL; 1928 1929 return set_id_reg(vcpu, rd, val); 1930 } 1931 1932 static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, 1933 const struct sys_reg_desc *rd, u64 user_val) 1934 { 1935 u64 hw_val = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1936 u64 mpam_mask = ID_AA64PFR0_EL1_MPAM_MASK; 1937 1938 /* 1939 * Commit 011e5f5bf529f ("arm64/cpufeature: Add remaining feature bits 1940 * in ID_AA64PFR0 register") exposed the MPAM field of AA64PFR0_EL1 to 1941 * guests, but didn't add trap handling. KVM doesn't support MPAM and 1942 * always returns an UNDEF for these registers. The guest must see 0 1943 * for this field. 1944 * 1945 * But KVM must also accept values from user-space that were provided 1946 * by KVM. On CPUs that support MPAM, permit user-space to write 1947 * the sanitizied value to ID_AA64PFR0_EL1.MPAM, but ignore this field. 1948 */ 1949 if ((hw_val & mpam_mask) == (user_val & mpam_mask)) 1950 user_val &= ~ID_AA64PFR0_EL1_MPAM_MASK; 1951 1952 /* Fail the guest's request to disable the AA64 ISA at EL{0,1,2} */ 1953 if (!FIELD_GET(ID_AA64PFR0_EL1_EL0, user_val) || 1954 !FIELD_GET(ID_AA64PFR0_EL1_EL1, user_val) || 1955 (vcpu_has_nv(vcpu) && !FIELD_GET(ID_AA64PFR0_EL1_EL2, user_val))) 1956 return -EINVAL; 1957 1958 return set_id_reg(vcpu, rd, user_val); 1959 } 1960 1961 static int set_id_aa64pfr1_el1(struct kvm_vcpu *vcpu, 1962 const struct sys_reg_desc *rd, u64 user_val) 1963 { 1964 u64 hw_val = read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1); 1965 u64 mpam_mask = ID_AA64PFR1_EL1_MPAM_frac_MASK; 1966 u8 mte = SYS_FIELD_GET(ID_AA64PFR1_EL1, MTE, hw_val); 1967 u8 user_mte_frac = SYS_FIELD_GET(ID_AA64PFR1_EL1, MTE_frac, user_val); 1968 u8 hw_mte_frac = SYS_FIELD_GET(ID_AA64PFR1_EL1, MTE_frac, hw_val); 1969 1970 /* See set_id_aa64pfr0_el1 for comment about MPAM */ 1971 if ((hw_val & mpam_mask) == (user_val & mpam_mask)) 1972 user_val &= ~ID_AA64PFR1_EL1_MPAM_frac_MASK; 1973 1974 /* 1975 * Previously MTE_frac was hidden from guest. However, if the 1976 * hardware supports MTE2 but not MTE_ASYM_FAULT then a value 1977 * of 0 for this field indicates that the hardware supports 1978 * MTE_ASYNC. Whereas, 0xf indicates MTE_ASYNC is not supported. 1979 * 1980 * As KVM must accept values from KVM provided by user-space, 1981 * when ID_AA64PFR1_EL1.MTE is 2 allow user-space to set 1982 * ID_AA64PFR1_EL1.MTE_frac to 0. However, ignore it to avoid 1983 * incorrectly claiming hardware support for MTE_ASYNC in the 1984 * guest. 1985 */ 1986 1987 if (mte == ID_AA64PFR1_EL1_MTE_MTE2 && 1988 hw_mte_frac == ID_AA64PFR1_EL1_MTE_frac_NI && 1989 user_mte_frac == ID_AA64PFR1_EL1_MTE_frac_ASYNC) { 1990 user_val &= ~ID_AA64PFR1_EL1_MTE_frac_MASK; 1991 user_val |= hw_val & ID_AA64PFR1_EL1_MTE_frac_MASK; 1992 } 1993 1994 return set_id_reg(vcpu, rd, user_val); 1995 } 1996 1997 static int set_id_aa64mmfr0_el1(struct kvm_vcpu *vcpu, 1998 const struct sys_reg_desc *rd, u64 user_val) 1999 { 2000 u64 sanitized_val = kvm_read_sanitised_id_reg(vcpu, rd); 2001 u64 tgran2_mask = ID_AA64MMFR0_EL1_TGRAN4_2_MASK | 2002 ID_AA64MMFR0_EL1_TGRAN16_2_MASK | 2003 ID_AA64MMFR0_EL1_TGRAN64_2_MASK; 2004 2005 if (vcpu_has_nv(vcpu) && 2006 ((sanitized_val & tgran2_mask) != (user_val & tgran2_mask))) 2007 return -EINVAL; 2008 2009 return set_id_reg(vcpu, rd, user_val); 2010 } 2011 2012 static int set_id_aa64mmfr2_el1(struct kvm_vcpu *vcpu, 2013 const struct sys_reg_desc *rd, u64 user_val) 2014 { 2015 u64 hw_val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR2_EL1); 2016 u64 nv_mask = ID_AA64MMFR2_EL1_NV_MASK; 2017 2018 /* 2019 * We made the mistake to expose the now deprecated NV field, 2020 * so allow userspace to write it, but silently ignore it. 2021 */ 2022 if ((hw_val & nv_mask) == (user_val & nv_mask)) 2023 user_val &= ~nv_mask; 2024 2025 return set_id_reg(vcpu, rd, user_val); 2026 } 2027 2028 static int set_ctr_el0(struct kvm_vcpu *vcpu, 2029 const struct sys_reg_desc *rd, u64 user_val) 2030 { 2031 u8 user_L1Ip = SYS_FIELD_GET(CTR_EL0, L1Ip, user_val); 2032 2033 /* 2034 * Both AIVIVT (0b01) and VPIPT (0b00) are documented as reserved. 2035 * Hence only allow to set VIPT(0b10) or PIPT(0b11) for L1Ip based 2036 * on what hardware reports. 2037 * 2038 * Using a VIPT software model on PIPT will lead to over invalidation, 2039 * but still correct. Hence, we can allow downgrading PIPT to VIPT, 2040 * but not the other way around. This is handled via arm64_ftr_safe_value() 2041 * as CTR_EL0 ftr_bits has L1Ip field with type FTR_EXACT and safe value 2042 * set as VIPT. 2043 */ 2044 switch (user_L1Ip) { 2045 case CTR_EL0_L1Ip_RESERVED_VPIPT: 2046 case CTR_EL0_L1Ip_RESERVED_AIVIVT: 2047 return -EINVAL; 2048 case CTR_EL0_L1Ip_VIPT: 2049 case CTR_EL0_L1Ip_PIPT: 2050 return set_id_reg(vcpu, rd, user_val); 2051 default: 2052 return -ENOENT; 2053 } 2054 } 2055 2056 /* 2057 * cpufeature ID register user accessors 2058 * 2059 * For now, these registers are immutable for userspace, so no values 2060 * are stored, and for set_id_reg() we don't allow the effective value 2061 * to be changed. 2062 */ 2063 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 2064 u64 *val) 2065 { 2066 /* 2067 * Avoid locking if the VM has already started, as the ID registers are 2068 * guaranteed to be invariant at that point. 2069 */ 2070 if (kvm_vm_has_ran_once(vcpu->kvm)) { 2071 *val = read_id_reg(vcpu, rd); 2072 return 0; 2073 } 2074 2075 mutex_lock(&vcpu->kvm->arch.config_lock); 2076 *val = read_id_reg(vcpu, rd); 2077 mutex_unlock(&vcpu->kvm->arch.config_lock); 2078 2079 return 0; 2080 } 2081 2082 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 2083 u64 val) 2084 { 2085 u32 id = reg_to_encoding(rd); 2086 int ret; 2087 2088 mutex_lock(&vcpu->kvm->arch.config_lock); 2089 2090 /* 2091 * Once the VM has started the ID registers are immutable. Reject any 2092 * write that does not match the final register value. 2093 */ 2094 if (kvm_vm_has_ran_once(vcpu->kvm)) { 2095 if (val != read_id_reg(vcpu, rd)) 2096 ret = -EBUSY; 2097 else 2098 ret = 0; 2099 2100 mutex_unlock(&vcpu->kvm->arch.config_lock); 2101 return ret; 2102 } 2103 2104 ret = arm64_check_features(vcpu, rd, val); 2105 if (!ret) 2106 kvm_set_vm_id_reg(vcpu->kvm, id, val); 2107 2108 mutex_unlock(&vcpu->kvm->arch.config_lock); 2109 2110 /* 2111 * arm64_check_features() returns -E2BIG to indicate the register's 2112 * feature set is a superset of the maximally-allowed register value. 2113 * While it would be nice to precisely describe this to userspace, the 2114 * existing UAPI for KVM_SET_ONE_REG has it that invalid register 2115 * writes return -EINVAL. 2116 */ 2117 if (ret == -E2BIG) 2118 ret = -EINVAL; 2119 return ret; 2120 } 2121 2122 void kvm_set_vm_id_reg(struct kvm *kvm, u32 reg, u64 val) 2123 { 2124 u64 *p = __vm_id_reg(&kvm->arch, reg); 2125 2126 lockdep_assert_held(&kvm->arch.config_lock); 2127 2128 if (KVM_BUG_ON(kvm_vm_has_ran_once(kvm) || !p, kvm)) 2129 return; 2130 2131 *p = val; 2132 } 2133 2134 static int get_raz_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 2135 u64 *val) 2136 { 2137 *val = 0; 2138 return 0; 2139 } 2140 2141 static int set_wi_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 2142 u64 val) 2143 { 2144 return 0; 2145 } 2146 2147 static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2148 const struct sys_reg_desc *r) 2149 { 2150 if (p->is_write) 2151 return write_to_read_only(vcpu, p, r); 2152 2153 p->regval = kvm_read_vm_id_reg(vcpu->kvm, SYS_CTR_EL0); 2154 return true; 2155 } 2156 2157 static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2158 const struct sys_reg_desc *r) 2159 { 2160 if (p->is_write) 2161 return write_to_read_only(vcpu, p, r); 2162 2163 p->regval = __vcpu_sys_reg(vcpu, r->reg); 2164 return true; 2165 } 2166 2167 /* 2168 * Fabricate a CLIDR_EL1 value instead of using the real value, which can vary 2169 * by the physical CPU which the vcpu currently resides in. 2170 */ 2171 static u64 reset_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 2172 { 2173 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0); 2174 u64 clidr; 2175 u8 loc; 2176 2177 if ((ctr_el0 & CTR_EL0_IDC)) { 2178 /* 2179 * Data cache clean to the PoU is not required so LoUU and LoUIS 2180 * will not be set and a unified cache, which will be marked as 2181 * LoC, will be added. 2182 * 2183 * If not DIC, let the unified cache L2 so that an instruction 2184 * cache can be added as L1 later. 2185 */ 2186 loc = (ctr_el0 & CTR_EL0_DIC) ? 1 : 2; 2187 clidr = CACHE_TYPE_UNIFIED << CLIDR_CTYPE_SHIFT(loc); 2188 } else { 2189 /* 2190 * Data cache clean to the PoU is required so let L1 have a data 2191 * cache and mark it as LoUU and LoUIS. As L1 has a data cache, 2192 * it can be marked as LoC too. 2193 */ 2194 loc = 1; 2195 clidr = 1 << CLIDR_LOUU_SHIFT; 2196 clidr |= 1 << CLIDR_LOUIS_SHIFT; 2197 clidr |= CACHE_TYPE_DATA << CLIDR_CTYPE_SHIFT(1); 2198 } 2199 2200 /* 2201 * Instruction cache invalidation to the PoU is required so let L1 have 2202 * an instruction cache. If L1 already has a data cache, it will be 2203 * CACHE_TYPE_SEPARATE. 2204 */ 2205 if (!(ctr_el0 & CTR_EL0_DIC)) 2206 clidr |= CACHE_TYPE_INST << CLIDR_CTYPE_SHIFT(1); 2207 2208 clidr |= loc << CLIDR_LOC_SHIFT; 2209 2210 /* 2211 * Add tag cache unified to data cache. Allocation tags and data are 2212 * unified in a cache line so that it looks valid even if there is only 2213 * one cache line. 2214 */ 2215 if (kvm_has_mte(vcpu->kvm)) 2216 clidr |= 2ULL << CLIDR_TTYPE_SHIFT(loc); 2217 2218 __vcpu_sys_reg(vcpu, r->reg) = clidr; 2219 2220 return __vcpu_sys_reg(vcpu, r->reg); 2221 } 2222 2223 static int set_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 2224 u64 val) 2225 { 2226 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0); 2227 u64 idc = !CLIDR_LOC(val) || (!CLIDR_LOUIS(val) && !CLIDR_LOUU(val)); 2228 2229 if ((val & CLIDR_EL1_RES0) || (!(ctr_el0 & CTR_EL0_IDC) && idc)) 2230 return -EINVAL; 2231 2232 __vcpu_sys_reg(vcpu, rd->reg) = val; 2233 2234 return 0; 2235 } 2236 2237 static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2238 const struct sys_reg_desc *r) 2239 { 2240 int reg = r->reg; 2241 2242 if (p->is_write) 2243 vcpu_write_sys_reg(vcpu, p->regval, reg); 2244 else 2245 p->regval = vcpu_read_sys_reg(vcpu, reg); 2246 return true; 2247 } 2248 2249 static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2250 const struct sys_reg_desc *r) 2251 { 2252 u32 csselr; 2253 2254 if (p->is_write) 2255 return write_to_read_only(vcpu, p, r); 2256 2257 csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1); 2258 csselr &= CSSELR_EL1_Level | CSSELR_EL1_InD; 2259 if (csselr < CSSELR_MAX) 2260 p->regval = get_ccsidr(vcpu, csselr); 2261 2262 return true; 2263 } 2264 2265 static unsigned int mte_visibility(const struct kvm_vcpu *vcpu, 2266 const struct sys_reg_desc *rd) 2267 { 2268 if (kvm_has_mte(vcpu->kvm)) 2269 return 0; 2270 2271 return REG_HIDDEN; 2272 } 2273 2274 #define MTE_REG(name) { \ 2275 SYS_DESC(SYS_##name), \ 2276 .access = undef_access, \ 2277 .reset = reset_unknown, \ 2278 .reg = name, \ 2279 .visibility = mte_visibility, \ 2280 } 2281 2282 static unsigned int el2_visibility(const struct kvm_vcpu *vcpu, 2283 const struct sys_reg_desc *rd) 2284 { 2285 if (vcpu_has_nv(vcpu)) 2286 return 0; 2287 2288 return REG_HIDDEN; 2289 } 2290 2291 static bool bad_vncr_trap(struct kvm_vcpu *vcpu, 2292 struct sys_reg_params *p, 2293 const struct sys_reg_desc *r) 2294 { 2295 /* 2296 * We really shouldn't be here, and this is likely the result 2297 * of a misconfigured trap, as this register should target the 2298 * VNCR page, and nothing else. 2299 */ 2300 return bad_trap(vcpu, p, r, 2301 "trap of VNCR-backed register"); 2302 } 2303 2304 static bool bad_redir_trap(struct kvm_vcpu *vcpu, 2305 struct sys_reg_params *p, 2306 const struct sys_reg_desc *r) 2307 { 2308 /* 2309 * We really shouldn't be here, and this is likely the result 2310 * of a misconfigured trap, as this register should target the 2311 * corresponding EL1, and nothing else. 2312 */ 2313 return bad_trap(vcpu, p, r, 2314 "trap of EL2 register redirected to EL1"); 2315 } 2316 2317 #define EL2_REG_FILTERED(name, acc, rst, v, filter) { \ 2318 SYS_DESC(SYS_##name), \ 2319 .access = acc, \ 2320 .reset = rst, \ 2321 .reg = name, \ 2322 .visibility = filter, \ 2323 .val = v, \ 2324 } 2325 2326 #define EL2_REG(name, acc, rst, v) \ 2327 EL2_REG_FILTERED(name, acc, rst, v, el2_visibility) 2328 2329 #define EL2_REG_VNCR(name, rst, v) EL2_REG(name, bad_vncr_trap, rst, v) 2330 #define EL2_REG_REDIR(name, rst, v) EL2_REG(name, bad_redir_trap, rst, v) 2331 2332 /* 2333 * Since reset() callback and field val are not used for idregs, they will be 2334 * used for specific purposes for idregs. 2335 * The reset() would return KVM sanitised register value. The value would be the 2336 * same as the host kernel sanitised value if there is no KVM sanitisation. 2337 * The val would be used as a mask indicating writable fields for the idreg. 2338 * Only bits with 1 are writable from userspace. This mask might not be 2339 * necessary in the future whenever all ID registers are enabled as writable 2340 * from userspace. 2341 */ 2342 2343 #define ID_DESC_DEFAULT_CALLBACKS \ 2344 .access = access_id_reg, \ 2345 .get_user = get_id_reg, \ 2346 .set_user = set_id_reg, \ 2347 .visibility = id_visibility, \ 2348 .reset = kvm_read_sanitised_id_reg 2349 2350 #define ID_DESC(name) \ 2351 SYS_DESC(SYS_##name), \ 2352 ID_DESC_DEFAULT_CALLBACKS 2353 2354 /* sys_reg_desc initialiser for known cpufeature ID registers */ 2355 #define ID_SANITISED(name) { \ 2356 ID_DESC(name), \ 2357 .val = 0, \ 2358 } 2359 2360 /* sys_reg_desc initialiser for known cpufeature ID registers */ 2361 #define AA32_ID_SANITISED(name) { \ 2362 ID_DESC(name), \ 2363 .visibility = aa32_id_visibility, \ 2364 .val = 0, \ 2365 } 2366 2367 /* sys_reg_desc initialiser for writable ID registers */ 2368 #define ID_WRITABLE(name, mask) { \ 2369 ID_DESC(name), \ 2370 .val = mask, \ 2371 } 2372 2373 /* sys_reg_desc initialiser for cpufeature ID registers that need filtering */ 2374 #define ID_FILTERED(sysreg, name, mask) { \ 2375 ID_DESC(sysreg), \ 2376 .set_user = set_##name, \ 2377 .val = (mask), \ 2378 } 2379 2380 /* 2381 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID 2382 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2 2383 * (1 <= crm < 8, 0 <= Op2 < 8). 2384 */ 2385 #define ID_UNALLOCATED(crm, op2) { \ 2386 .name = "S3_0_0_" #crm "_" #op2, \ 2387 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \ 2388 ID_DESC_DEFAULT_CALLBACKS, \ 2389 .visibility = raz_visibility, \ 2390 .val = 0, \ 2391 } 2392 2393 /* 2394 * sys_reg_desc initialiser for known ID registers that we hide from guests. 2395 * For now, these are exposed just like unallocated ID regs: they appear 2396 * RAZ for the guest. 2397 */ 2398 #define ID_HIDDEN(name) { \ 2399 ID_DESC(name), \ 2400 .visibility = raz_visibility, \ 2401 .val = 0, \ 2402 } 2403 2404 static bool access_sp_el1(struct kvm_vcpu *vcpu, 2405 struct sys_reg_params *p, 2406 const struct sys_reg_desc *r) 2407 { 2408 if (p->is_write) 2409 __vcpu_sys_reg(vcpu, SP_EL1) = p->regval; 2410 else 2411 p->regval = __vcpu_sys_reg(vcpu, SP_EL1); 2412 2413 return true; 2414 } 2415 2416 static bool access_elr(struct kvm_vcpu *vcpu, 2417 struct sys_reg_params *p, 2418 const struct sys_reg_desc *r) 2419 { 2420 if (p->is_write) 2421 vcpu_write_sys_reg(vcpu, p->regval, ELR_EL1); 2422 else 2423 p->regval = vcpu_read_sys_reg(vcpu, ELR_EL1); 2424 2425 return true; 2426 } 2427 2428 static bool access_spsr(struct kvm_vcpu *vcpu, 2429 struct sys_reg_params *p, 2430 const struct sys_reg_desc *r) 2431 { 2432 if (p->is_write) 2433 __vcpu_sys_reg(vcpu, SPSR_EL1) = p->regval; 2434 else 2435 p->regval = __vcpu_sys_reg(vcpu, SPSR_EL1); 2436 2437 return true; 2438 } 2439 2440 static bool access_cntkctl_el12(struct kvm_vcpu *vcpu, 2441 struct sys_reg_params *p, 2442 const struct sys_reg_desc *r) 2443 { 2444 if (p->is_write) 2445 __vcpu_sys_reg(vcpu, CNTKCTL_EL1) = p->regval; 2446 else 2447 p->regval = __vcpu_sys_reg(vcpu, CNTKCTL_EL1); 2448 2449 return true; 2450 } 2451 2452 static u64 reset_hcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 2453 { 2454 u64 val = r->val; 2455 2456 if (!cpus_have_final_cap(ARM64_HAS_HCR_NV1)) 2457 val |= HCR_E2H; 2458 2459 return __vcpu_sys_reg(vcpu, r->reg) = val; 2460 } 2461 2462 static unsigned int __el2_visibility(const struct kvm_vcpu *vcpu, 2463 const struct sys_reg_desc *rd, 2464 unsigned int (*fn)(const struct kvm_vcpu *, 2465 const struct sys_reg_desc *)) 2466 { 2467 return el2_visibility(vcpu, rd) ?: fn(vcpu, rd); 2468 } 2469 2470 static unsigned int sve_el2_visibility(const struct kvm_vcpu *vcpu, 2471 const struct sys_reg_desc *rd) 2472 { 2473 return __el2_visibility(vcpu, rd, sve_visibility); 2474 } 2475 2476 static unsigned int vncr_el2_visibility(const struct kvm_vcpu *vcpu, 2477 const struct sys_reg_desc *rd) 2478 { 2479 if (el2_visibility(vcpu, rd) == 0 && 2480 kvm_has_feat(vcpu->kvm, ID_AA64MMFR4_EL1, NV_frac, NV2_ONLY)) 2481 return 0; 2482 2483 return REG_HIDDEN; 2484 } 2485 2486 static bool access_zcr_el2(struct kvm_vcpu *vcpu, 2487 struct sys_reg_params *p, 2488 const struct sys_reg_desc *r) 2489 { 2490 unsigned int vq; 2491 2492 if (guest_hyp_sve_traps_enabled(vcpu)) { 2493 kvm_inject_nested_sve_trap(vcpu); 2494 return true; 2495 } 2496 2497 if (!p->is_write) { 2498 p->regval = vcpu_read_sys_reg(vcpu, ZCR_EL2); 2499 return true; 2500 } 2501 2502 vq = SYS_FIELD_GET(ZCR_ELx, LEN, p->regval) + 1; 2503 vq = min(vq, vcpu_sve_max_vq(vcpu)); 2504 vcpu_write_sys_reg(vcpu, vq - 1, ZCR_EL2); 2505 2506 return true; 2507 } 2508 2509 static bool access_gic_vtr(struct kvm_vcpu *vcpu, 2510 struct sys_reg_params *p, 2511 const struct sys_reg_desc *r) 2512 { 2513 if (p->is_write) 2514 return write_to_read_only(vcpu, p, r); 2515 2516 p->regval = kvm_vgic_global_state.ich_vtr_el2; 2517 p->regval &= ~(ICH_VTR_EL2_DVIM | 2518 ICH_VTR_EL2_A3V | 2519 ICH_VTR_EL2_IDbits); 2520 p->regval |= ICH_VTR_EL2_nV4; 2521 2522 return true; 2523 } 2524 2525 static bool access_gic_misr(struct kvm_vcpu *vcpu, 2526 struct sys_reg_params *p, 2527 const struct sys_reg_desc *r) 2528 { 2529 if (p->is_write) 2530 return write_to_read_only(vcpu, p, r); 2531 2532 p->regval = vgic_v3_get_misr(vcpu); 2533 2534 return true; 2535 } 2536 2537 static bool access_gic_eisr(struct kvm_vcpu *vcpu, 2538 struct sys_reg_params *p, 2539 const struct sys_reg_desc *r) 2540 { 2541 if (p->is_write) 2542 return write_to_read_only(vcpu, p, r); 2543 2544 p->regval = vgic_v3_get_eisr(vcpu); 2545 2546 return true; 2547 } 2548 2549 static bool access_gic_elrsr(struct kvm_vcpu *vcpu, 2550 struct sys_reg_params *p, 2551 const struct sys_reg_desc *r) 2552 { 2553 if (p->is_write) 2554 return write_to_read_only(vcpu, p, r); 2555 2556 p->regval = vgic_v3_get_elrsr(vcpu); 2557 2558 return true; 2559 } 2560 2561 static unsigned int s1poe_visibility(const struct kvm_vcpu *vcpu, 2562 const struct sys_reg_desc *rd) 2563 { 2564 if (kvm_has_s1poe(vcpu->kvm)) 2565 return 0; 2566 2567 return REG_HIDDEN; 2568 } 2569 2570 static unsigned int s1poe_el2_visibility(const struct kvm_vcpu *vcpu, 2571 const struct sys_reg_desc *rd) 2572 { 2573 return __el2_visibility(vcpu, rd, s1poe_visibility); 2574 } 2575 2576 static unsigned int tcr2_visibility(const struct kvm_vcpu *vcpu, 2577 const struct sys_reg_desc *rd) 2578 { 2579 if (kvm_has_tcr2(vcpu->kvm)) 2580 return 0; 2581 2582 return REG_HIDDEN; 2583 } 2584 2585 static unsigned int tcr2_el2_visibility(const struct kvm_vcpu *vcpu, 2586 const struct sys_reg_desc *rd) 2587 { 2588 return __el2_visibility(vcpu, rd, tcr2_visibility); 2589 } 2590 2591 static unsigned int s1pie_visibility(const struct kvm_vcpu *vcpu, 2592 const struct sys_reg_desc *rd) 2593 { 2594 if (kvm_has_s1pie(vcpu->kvm)) 2595 return 0; 2596 2597 return REG_HIDDEN; 2598 } 2599 2600 static unsigned int s1pie_el2_visibility(const struct kvm_vcpu *vcpu, 2601 const struct sys_reg_desc *rd) 2602 { 2603 return __el2_visibility(vcpu, rd, s1pie_visibility); 2604 } 2605 2606 static bool access_mdcr(struct kvm_vcpu *vcpu, 2607 struct sys_reg_params *p, 2608 const struct sys_reg_desc *r) 2609 { 2610 u64 hpmn, val, old = __vcpu_sys_reg(vcpu, MDCR_EL2); 2611 2612 if (!p->is_write) { 2613 p->regval = old; 2614 return true; 2615 } 2616 2617 val = p->regval; 2618 hpmn = FIELD_GET(MDCR_EL2_HPMN, val); 2619 2620 /* 2621 * If HPMN is out of bounds, limit it to what we actually 2622 * support. This matches the UNKNOWN definition of the field 2623 * in that case, and keeps the emulation simple. Sort of. 2624 */ 2625 if (hpmn > vcpu->kvm->arch.nr_pmu_counters) { 2626 hpmn = vcpu->kvm->arch.nr_pmu_counters; 2627 u64_replace_bits(val, hpmn, MDCR_EL2_HPMN); 2628 } 2629 2630 __vcpu_sys_reg(vcpu, MDCR_EL2) = val; 2631 2632 /* 2633 * Request a reload of the PMU to enable/disable the counters 2634 * affected by HPME. 2635 */ 2636 if ((old ^ val) & MDCR_EL2_HPME) 2637 kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu); 2638 2639 return true; 2640 } 2641 2642 /* 2643 * For historical (ahem ABI) reasons, KVM treated MIDR_EL1, REVIDR_EL1, and 2644 * AIDR_EL1 as "invariant" registers, meaning userspace cannot change them. 2645 * The values made visible to userspace were the register values of the boot 2646 * CPU. 2647 * 2648 * At the same time, reads from these registers at EL1 previously were not 2649 * trapped, allowing the guest to read the actual hardware value. On big-little 2650 * machines, this means the VM can see different values depending on where a 2651 * given vCPU got scheduled. 2652 * 2653 * These registers are now trapped as collateral damage from SME, and what 2654 * follows attempts to give a user / guest view consistent with the existing 2655 * ABI. 2656 */ 2657 static bool access_imp_id_reg(struct kvm_vcpu *vcpu, 2658 struct sys_reg_params *p, 2659 const struct sys_reg_desc *r) 2660 { 2661 if (p->is_write) 2662 return write_to_read_only(vcpu, p, r); 2663 2664 /* 2665 * Return the VM-scoped implementation ID register values if userspace 2666 * has made them writable. 2667 */ 2668 if (test_bit(KVM_ARCH_FLAG_WRITABLE_IMP_ID_REGS, &vcpu->kvm->arch.flags)) 2669 return access_id_reg(vcpu, p, r); 2670 2671 /* 2672 * Otherwise, fall back to the old behavior of returning the value of 2673 * the current CPU. 2674 */ 2675 switch (reg_to_encoding(r)) { 2676 case SYS_REVIDR_EL1: 2677 p->regval = read_sysreg(revidr_el1); 2678 break; 2679 case SYS_AIDR_EL1: 2680 p->regval = read_sysreg(aidr_el1); 2681 break; 2682 default: 2683 WARN_ON_ONCE(1); 2684 } 2685 2686 return true; 2687 } 2688 2689 static u64 __ro_after_init boot_cpu_midr_val; 2690 static u64 __ro_after_init boot_cpu_revidr_val; 2691 static u64 __ro_after_init boot_cpu_aidr_val; 2692 2693 static void init_imp_id_regs(void) 2694 { 2695 boot_cpu_midr_val = read_sysreg(midr_el1); 2696 boot_cpu_revidr_val = read_sysreg(revidr_el1); 2697 boot_cpu_aidr_val = read_sysreg(aidr_el1); 2698 } 2699 2700 static u64 reset_imp_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 2701 { 2702 switch (reg_to_encoding(r)) { 2703 case SYS_MIDR_EL1: 2704 return boot_cpu_midr_val; 2705 case SYS_REVIDR_EL1: 2706 return boot_cpu_revidr_val; 2707 case SYS_AIDR_EL1: 2708 return boot_cpu_aidr_val; 2709 default: 2710 KVM_BUG_ON(1, vcpu->kvm); 2711 return 0; 2712 } 2713 } 2714 2715 static int set_imp_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 2716 u64 val) 2717 { 2718 struct kvm *kvm = vcpu->kvm; 2719 u64 expected; 2720 2721 guard(mutex)(&kvm->arch.config_lock); 2722 2723 expected = read_id_reg(vcpu, r); 2724 if (expected == val) 2725 return 0; 2726 2727 if (!test_bit(KVM_ARCH_FLAG_WRITABLE_IMP_ID_REGS, &kvm->arch.flags)) 2728 return -EINVAL; 2729 2730 /* 2731 * Once the VM has started the ID registers are immutable. Reject the 2732 * write if userspace tries to change it. 2733 */ 2734 if (kvm_vm_has_ran_once(kvm)) 2735 return -EBUSY; 2736 2737 /* 2738 * Any value is allowed for the implementation ID registers so long as 2739 * it is within the writable mask. 2740 */ 2741 if ((val & r->val) != val) 2742 return -EINVAL; 2743 2744 kvm_set_vm_id_reg(kvm, reg_to_encoding(r), val); 2745 return 0; 2746 } 2747 2748 #define IMPLEMENTATION_ID(reg, mask) { \ 2749 SYS_DESC(SYS_##reg), \ 2750 .access = access_imp_id_reg, \ 2751 .get_user = get_id_reg, \ 2752 .set_user = set_imp_id_reg, \ 2753 .reset = reset_imp_id_reg, \ 2754 .val = mask, \ 2755 } 2756 2757 static u64 reset_mdcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 2758 { 2759 __vcpu_sys_reg(vcpu, r->reg) = vcpu->kvm->arch.nr_pmu_counters; 2760 return vcpu->kvm->arch.nr_pmu_counters; 2761 } 2762 2763 /* 2764 * Architected system registers. 2765 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2 2766 * 2767 * Debug handling: We do trap most, if not all debug related system 2768 * registers. The implementation is good enough to ensure that a guest 2769 * can use these with minimal performance degradation. The drawback is 2770 * that we don't implement any of the external debug architecture. 2771 * This should be revisited if we ever encounter a more demanding 2772 * guest... 2773 */ 2774 static const struct sys_reg_desc sys_reg_descs[] = { 2775 DBG_BCR_BVR_WCR_WVR_EL1(0), 2776 DBG_BCR_BVR_WCR_WVR_EL1(1), 2777 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 }, 2778 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 }, 2779 DBG_BCR_BVR_WCR_WVR_EL1(2), 2780 DBG_BCR_BVR_WCR_WVR_EL1(3), 2781 DBG_BCR_BVR_WCR_WVR_EL1(4), 2782 DBG_BCR_BVR_WCR_WVR_EL1(5), 2783 DBG_BCR_BVR_WCR_WVR_EL1(6), 2784 DBG_BCR_BVR_WCR_WVR_EL1(7), 2785 DBG_BCR_BVR_WCR_WVR_EL1(8), 2786 DBG_BCR_BVR_WCR_WVR_EL1(9), 2787 DBG_BCR_BVR_WCR_WVR_EL1(10), 2788 DBG_BCR_BVR_WCR_WVR_EL1(11), 2789 DBG_BCR_BVR_WCR_WVR_EL1(12), 2790 DBG_BCR_BVR_WCR_WVR_EL1(13), 2791 DBG_BCR_BVR_WCR_WVR_EL1(14), 2792 DBG_BCR_BVR_WCR_WVR_EL1(15), 2793 2794 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi }, 2795 { SYS_DESC(SYS_OSLAR_EL1), trap_oslar_el1 }, 2796 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1, 2797 OSLSR_EL1_OSLM_IMPLEMENTED, .set_user = set_oslsr_el1, }, 2798 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi }, 2799 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi }, 2800 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi }, 2801 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi }, 2802 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 }, 2803 2804 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi }, 2805 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi }, 2806 // DBGDTR[TR]X_EL0 share the same encoding 2807 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi }, 2808 2809 { SYS_DESC(SYS_DBGVCR32_EL2), undef_access, reset_val, DBGVCR32_EL2, 0 }, 2810 2811 IMPLEMENTATION_ID(MIDR_EL1, GENMASK_ULL(31, 0)), 2812 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 }, 2813 IMPLEMENTATION_ID(REVIDR_EL1, GENMASK_ULL(63, 0)), 2814 2815 /* 2816 * ID regs: all ID_SANITISED() entries here must have corresponding 2817 * entries in arm64_ftr_regs[]. 2818 */ 2819 2820 /* AArch64 mappings of the AArch32 ID registers */ 2821 /* CRm=1 */ 2822 AA32_ID_SANITISED(ID_PFR0_EL1), 2823 AA32_ID_SANITISED(ID_PFR1_EL1), 2824 { SYS_DESC(SYS_ID_DFR0_EL1), 2825 .access = access_id_reg, 2826 .get_user = get_id_reg, 2827 .set_user = set_id_dfr0_el1, 2828 .visibility = aa32_id_visibility, 2829 .reset = read_sanitised_id_dfr0_el1, 2830 .val = ID_DFR0_EL1_PerfMon_MASK | 2831 ID_DFR0_EL1_CopDbg_MASK, }, 2832 ID_HIDDEN(ID_AFR0_EL1), 2833 AA32_ID_SANITISED(ID_MMFR0_EL1), 2834 AA32_ID_SANITISED(ID_MMFR1_EL1), 2835 AA32_ID_SANITISED(ID_MMFR2_EL1), 2836 AA32_ID_SANITISED(ID_MMFR3_EL1), 2837 2838 /* CRm=2 */ 2839 AA32_ID_SANITISED(ID_ISAR0_EL1), 2840 AA32_ID_SANITISED(ID_ISAR1_EL1), 2841 AA32_ID_SANITISED(ID_ISAR2_EL1), 2842 AA32_ID_SANITISED(ID_ISAR3_EL1), 2843 AA32_ID_SANITISED(ID_ISAR4_EL1), 2844 AA32_ID_SANITISED(ID_ISAR5_EL1), 2845 AA32_ID_SANITISED(ID_MMFR4_EL1), 2846 AA32_ID_SANITISED(ID_ISAR6_EL1), 2847 2848 /* CRm=3 */ 2849 AA32_ID_SANITISED(MVFR0_EL1), 2850 AA32_ID_SANITISED(MVFR1_EL1), 2851 AA32_ID_SANITISED(MVFR2_EL1), 2852 ID_UNALLOCATED(3,3), 2853 AA32_ID_SANITISED(ID_PFR2_EL1), 2854 ID_HIDDEN(ID_DFR1_EL1), 2855 AA32_ID_SANITISED(ID_MMFR5_EL1), 2856 ID_UNALLOCATED(3,7), 2857 2858 /* AArch64 ID registers */ 2859 /* CRm=4 */ 2860 ID_FILTERED(ID_AA64PFR0_EL1, id_aa64pfr0_el1, 2861 ~(ID_AA64PFR0_EL1_AMU | 2862 ID_AA64PFR0_EL1_MPAM | 2863 ID_AA64PFR0_EL1_SVE | 2864 ID_AA64PFR0_EL1_RAS | 2865 ID_AA64PFR0_EL1_AdvSIMD | 2866 ID_AA64PFR0_EL1_FP)), 2867 ID_FILTERED(ID_AA64PFR1_EL1, id_aa64pfr1_el1, 2868 ~(ID_AA64PFR1_EL1_PFAR | 2869 ID_AA64PFR1_EL1_DF2 | 2870 ID_AA64PFR1_EL1_MTEX | 2871 ID_AA64PFR1_EL1_THE | 2872 ID_AA64PFR1_EL1_GCS | 2873 ID_AA64PFR1_EL1_MTE_frac | 2874 ID_AA64PFR1_EL1_NMI | 2875 ID_AA64PFR1_EL1_RNDR_trap | 2876 ID_AA64PFR1_EL1_SME | 2877 ID_AA64PFR1_EL1_RES0 | 2878 ID_AA64PFR1_EL1_MPAM_frac | 2879 ID_AA64PFR1_EL1_RAS_frac | 2880 ID_AA64PFR1_EL1_MTE)), 2881 ID_WRITABLE(ID_AA64PFR2_EL1, 2882 ID_AA64PFR2_EL1_FPMR | 2883 ID_AA64PFR2_EL1_MTEFAR | 2884 ID_AA64PFR2_EL1_MTESTOREONLY), 2885 ID_UNALLOCATED(4,3), 2886 ID_WRITABLE(ID_AA64ZFR0_EL1, ~ID_AA64ZFR0_EL1_RES0), 2887 ID_HIDDEN(ID_AA64SMFR0_EL1), 2888 ID_UNALLOCATED(4,6), 2889 ID_WRITABLE(ID_AA64FPFR0_EL1, ~ID_AA64FPFR0_EL1_RES0), 2890 2891 /* CRm=5 */ 2892 /* 2893 * Prior to FEAT_Debugv8.9, the architecture defines context-aware 2894 * breakpoints (CTX_CMPs) as the highest numbered breakpoints (BRPs). 2895 * KVM does not trap + emulate the breakpoint registers, and as such 2896 * cannot support a layout that misaligns with the underlying hardware. 2897 * While it may be possible to describe a subset that aligns with 2898 * hardware, just prevent changes to BRPs and CTX_CMPs altogether for 2899 * simplicity. 2900 * 2901 * See DDI0487K.a, section D2.8.3 Breakpoint types and linking 2902 * of breakpoints for more details. 2903 */ 2904 ID_FILTERED(ID_AA64DFR0_EL1, id_aa64dfr0_el1, 2905 ID_AA64DFR0_EL1_DoubleLock_MASK | 2906 ID_AA64DFR0_EL1_WRPs_MASK | 2907 ID_AA64DFR0_EL1_PMUVer_MASK | 2908 ID_AA64DFR0_EL1_DebugVer_MASK), 2909 ID_SANITISED(ID_AA64DFR1_EL1), 2910 ID_UNALLOCATED(5,2), 2911 ID_UNALLOCATED(5,3), 2912 ID_HIDDEN(ID_AA64AFR0_EL1), 2913 ID_HIDDEN(ID_AA64AFR1_EL1), 2914 ID_UNALLOCATED(5,6), 2915 ID_UNALLOCATED(5,7), 2916 2917 /* CRm=6 */ 2918 ID_WRITABLE(ID_AA64ISAR0_EL1, ~ID_AA64ISAR0_EL1_RES0), 2919 ID_WRITABLE(ID_AA64ISAR1_EL1, ~(ID_AA64ISAR1_EL1_GPI | 2920 ID_AA64ISAR1_EL1_GPA | 2921 ID_AA64ISAR1_EL1_API | 2922 ID_AA64ISAR1_EL1_APA)), 2923 ID_WRITABLE(ID_AA64ISAR2_EL1, ~(ID_AA64ISAR2_EL1_RES0 | 2924 ID_AA64ISAR2_EL1_APA3 | 2925 ID_AA64ISAR2_EL1_GPA3)), 2926 ID_WRITABLE(ID_AA64ISAR3_EL1, (ID_AA64ISAR3_EL1_FPRCVT | 2927 ID_AA64ISAR3_EL1_FAMINMAX)), 2928 ID_UNALLOCATED(6,4), 2929 ID_UNALLOCATED(6,5), 2930 ID_UNALLOCATED(6,6), 2931 ID_UNALLOCATED(6,7), 2932 2933 /* CRm=7 */ 2934 ID_FILTERED(ID_AA64MMFR0_EL1, id_aa64mmfr0_el1, 2935 ~(ID_AA64MMFR0_EL1_RES0 | 2936 ID_AA64MMFR0_EL1_ASIDBITS)), 2937 ID_WRITABLE(ID_AA64MMFR1_EL1, ~(ID_AA64MMFR1_EL1_RES0 | 2938 ID_AA64MMFR1_EL1_HCX | 2939 ID_AA64MMFR1_EL1_TWED | 2940 ID_AA64MMFR1_EL1_XNX | 2941 ID_AA64MMFR1_EL1_VH | 2942 ID_AA64MMFR1_EL1_VMIDBits)), 2943 ID_FILTERED(ID_AA64MMFR2_EL1, 2944 id_aa64mmfr2_el1, ~(ID_AA64MMFR2_EL1_RES0 | 2945 ID_AA64MMFR2_EL1_EVT | 2946 ID_AA64MMFR2_EL1_FWB | 2947 ID_AA64MMFR2_EL1_IDS | 2948 ID_AA64MMFR2_EL1_NV | 2949 ID_AA64MMFR2_EL1_CCIDX)), 2950 ID_WRITABLE(ID_AA64MMFR3_EL1, (ID_AA64MMFR3_EL1_TCRX | 2951 ID_AA64MMFR3_EL1_S1PIE | 2952 ID_AA64MMFR3_EL1_S1POE)), 2953 ID_WRITABLE(ID_AA64MMFR4_EL1, ID_AA64MMFR4_EL1_NV_frac), 2954 ID_UNALLOCATED(7,5), 2955 ID_UNALLOCATED(7,6), 2956 ID_UNALLOCATED(7,7), 2957 2958 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 }, 2959 { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 }, 2960 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 }, 2961 2962 MTE_REG(RGSR_EL1), 2963 MTE_REG(GCR_EL1), 2964 2965 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility }, 2966 { SYS_DESC(SYS_TRFCR_EL1), undef_access }, 2967 { SYS_DESC(SYS_SMPRI_EL1), undef_access }, 2968 { SYS_DESC(SYS_SMCR_EL1), undef_access }, 2969 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 }, 2970 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 }, 2971 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 }, 2972 { SYS_DESC(SYS_TCR2_EL1), access_vm_reg, reset_val, TCR2_EL1, 0, 2973 .visibility = tcr2_visibility }, 2974 2975 PTRAUTH_KEY(APIA), 2976 PTRAUTH_KEY(APIB), 2977 PTRAUTH_KEY(APDA), 2978 PTRAUTH_KEY(APDB), 2979 PTRAUTH_KEY(APGA), 2980 2981 { SYS_DESC(SYS_SPSR_EL1), access_spsr}, 2982 { SYS_DESC(SYS_ELR_EL1), access_elr}, 2983 2984 { SYS_DESC(SYS_ICC_PMR_EL1), undef_access }, 2985 2986 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 }, 2987 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 }, 2988 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 }, 2989 2990 { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi }, 2991 { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi }, 2992 { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi }, 2993 { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi }, 2994 { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi }, 2995 { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi }, 2996 { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi }, 2997 { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi }, 2998 2999 MTE_REG(TFSR_EL1), 3000 MTE_REG(TFSRE0_EL1), 3001 3002 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 }, 3003 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 }, 3004 3005 { SYS_DESC(SYS_PMSCR_EL1), undef_access }, 3006 { SYS_DESC(SYS_PMSNEVFR_EL1), undef_access }, 3007 { SYS_DESC(SYS_PMSICR_EL1), undef_access }, 3008 { SYS_DESC(SYS_PMSIRR_EL1), undef_access }, 3009 { SYS_DESC(SYS_PMSFCR_EL1), undef_access }, 3010 { SYS_DESC(SYS_PMSEVFR_EL1), undef_access }, 3011 { SYS_DESC(SYS_PMSLATFR_EL1), undef_access }, 3012 { SYS_DESC(SYS_PMSIDR_EL1), undef_access }, 3013 { SYS_DESC(SYS_PMBLIMITR_EL1), undef_access }, 3014 { SYS_DESC(SYS_PMBPTR_EL1), undef_access }, 3015 { SYS_DESC(SYS_PMBSR_EL1), undef_access }, 3016 /* PMBIDR_EL1 is not trapped */ 3017 3018 { PMU_SYS_REG(PMINTENSET_EL1), 3019 .access = access_pminten, .reg = PMINTENSET_EL1, 3020 .get_user = get_pmreg, .set_user = set_pmreg }, 3021 { PMU_SYS_REG(PMINTENCLR_EL1), 3022 .access = access_pminten, .reg = PMINTENSET_EL1, 3023 .get_user = get_pmreg, .set_user = set_pmreg }, 3024 { SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi }, 3025 3026 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 }, 3027 { SYS_DESC(SYS_PIRE0_EL1), NULL, reset_unknown, PIRE0_EL1, 3028 .visibility = s1pie_visibility }, 3029 { SYS_DESC(SYS_PIR_EL1), NULL, reset_unknown, PIR_EL1, 3030 .visibility = s1pie_visibility }, 3031 { SYS_DESC(SYS_POR_EL1), NULL, reset_unknown, POR_EL1, 3032 .visibility = s1poe_visibility }, 3033 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 }, 3034 3035 { SYS_DESC(SYS_LORSA_EL1), trap_loregion }, 3036 { SYS_DESC(SYS_LOREA_EL1), trap_loregion }, 3037 { SYS_DESC(SYS_LORN_EL1), trap_loregion }, 3038 { SYS_DESC(SYS_LORC_EL1), trap_loregion }, 3039 { SYS_DESC(SYS_MPAMIDR_EL1), undef_access }, 3040 { SYS_DESC(SYS_LORID_EL1), trap_loregion }, 3041 3042 { SYS_DESC(SYS_MPAM1_EL1), undef_access }, 3043 { SYS_DESC(SYS_MPAM0_EL1), undef_access }, 3044 { SYS_DESC(SYS_VBAR_EL1), access_rw, reset_val, VBAR_EL1, 0 }, 3045 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 }, 3046 3047 { SYS_DESC(SYS_ICC_IAR0_EL1), undef_access }, 3048 { SYS_DESC(SYS_ICC_EOIR0_EL1), undef_access }, 3049 { SYS_DESC(SYS_ICC_HPPIR0_EL1), undef_access }, 3050 { SYS_DESC(SYS_ICC_BPR0_EL1), undef_access }, 3051 { SYS_DESC(SYS_ICC_AP0R0_EL1), undef_access }, 3052 { SYS_DESC(SYS_ICC_AP0R1_EL1), undef_access }, 3053 { SYS_DESC(SYS_ICC_AP0R2_EL1), undef_access }, 3054 { SYS_DESC(SYS_ICC_AP0R3_EL1), undef_access }, 3055 { SYS_DESC(SYS_ICC_AP1R0_EL1), undef_access }, 3056 { SYS_DESC(SYS_ICC_AP1R1_EL1), undef_access }, 3057 { SYS_DESC(SYS_ICC_AP1R2_EL1), undef_access }, 3058 { SYS_DESC(SYS_ICC_AP1R3_EL1), undef_access }, 3059 { SYS_DESC(SYS_ICC_DIR_EL1), undef_access }, 3060 { SYS_DESC(SYS_ICC_RPR_EL1), undef_access }, 3061 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi }, 3062 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi }, 3063 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi }, 3064 { SYS_DESC(SYS_ICC_IAR1_EL1), undef_access }, 3065 { SYS_DESC(SYS_ICC_EOIR1_EL1), undef_access }, 3066 { SYS_DESC(SYS_ICC_HPPIR1_EL1), undef_access }, 3067 { SYS_DESC(SYS_ICC_BPR1_EL1), undef_access }, 3068 { SYS_DESC(SYS_ICC_CTLR_EL1), undef_access }, 3069 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre }, 3070 { SYS_DESC(SYS_ICC_IGRPEN0_EL1), undef_access }, 3071 { SYS_DESC(SYS_ICC_IGRPEN1_EL1), undef_access }, 3072 3073 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 }, 3074 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 }, 3075 3076 { SYS_DESC(SYS_ACCDATA_EL1), undef_access }, 3077 3078 { SYS_DESC(SYS_SCXTNUM_EL1), undef_access }, 3079 3080 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0}, 3081 3082 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr }, 3083 { SYS_DESC(SYS_CLIDR_EL1), access_clidr, reset_clidr, CLIDR_EL1, 3084 .set_user = set_clidr, .val = ~CLIDR_EL1_RES0 }, 3085 { SYS_DESC(SYS_CCSIDR2_EL1), undef_access }, 3086 { SYS_DESC(SYS_SMIDR_EL1), undef_access }, 3087 IMPLEMENTATION_ID(AIDR_EL1, GENMASK_ULL(63, 0)), 3088 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, 3089 ID_FILTERED(CTR_EL0, ctr_el0, 3090 CTR_EL0_DIC_MASK | 3091 CTR_EL0_IDC_MASK | 3092 CTR_EL0_DminLine_MASK | 3093 CTR_EL0_L1Ip_MASK | 3094 CTR_EL0_IminLine_MASK), 3095 { SYS_DESC(SYS_SVCR), undef_access, reset_val, SVCR, 0, .visibility = sme_visibility }, 3096 { SYS_DESC(SYS_FPMR), undef_access, reset_val, FPMR, 0, .visibility = fp8_visibility }, 3097 3098 { PMU_SYS_REG(PMCR_EL0), .access = access_pmcr, .reset = reset_pmcr, 3099 .reg = PMCR_EL0, .get_user = get_pmcr, .set_user = set_pmcr }, 3100 { PMU_SYS_REG(PMCNTENSET_EL0), 3101 .access = access_pmcnten, .reg = PMCNTENSET_EL0, 3102 .get_user = get_pmreg, .set_user = set_pmreg }, 3103 { PMU_SYS_REG(PMCNTENCLR_EL0), 3104 .access = access_pmcnten, .reg = PMCNTENSET_EL0, 3105 .get_user = get_pmreg, .set_user = set_pmreg }, 3106 { PMU_SYS_REG(PMOVSCLR_EL0), 3107 .access = access_pmovs, .reg = PMOVSSET_EL0, 3108 .get_user = get_pmreg, .set_user = set_pmreg }, 3109 /* 3110 * PM_SWINC_EL0 is exposed to userspace as RAZ/WI, as it was 3111 * previously (and pointlessly) advertised in the past... 3112 */ 3113 { PMU_SYS_REG(PMSWINC_EL0), 3114 .get_user = get_raz_reg, .set_user = set_wi_reg, 3115 .access = access_pmswinc, .reset = NULL }, 3116 { PMU_SYS_REG(PMSELR_EL0), 3117 .access = access_pmselr, .reset = reset_pmselr, .reg = PMSELR_EL0 }, 3118 { PMU_SYS_REG(PMCEID0_EL0), 3119 .access = access_pmceid, .reset = NULL }, 3120 { PMU_SYS_REG(PMCEID1_EL0), 3121 .access = access_pmceid, .reset = NULL }, 3122 { PMU_SYS_REG(PMCCNTR_EL0), 3123 .access = access_pmu_evcntr, .reset = reset_unknown, 3124 .reg = PMCCNTR_EL0, .get_user = get_pmu_evcntr, 3125 .set_user = set_pmu_evcntr }, 3126 { PMU_SYS_REG(PMXEVTYPER_EL0), 3127 .access = access_pmu_evtyper, .reset = NULL }, 3128 { PMU_SYS_REG(PMXEVCNTR_EL0), 3129 .access = access_pmu_evcntr, .reset = NULL }, 3130 /* 3131 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero 3132 * in 32bit mode. Here we choose to reset it as zero for consistency. 3133 */ 3134 { PMU_SYS_REG(PMUSERENR_EL0), .access = access_pmuserenr, 3135 .reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 }, 3136 { PMU_SYS_REG(PMOVSSET_EL0), 3137 .access = access_pmovs, .reg = PMOVSSET_EL0, 3138 .get_user = get_pmreg, .set_user = set_pmreg }, 3139 3140 { SYS_DESC(SYS_POR_EL0), NULL, reset_unknown, POR_EL0, 3141 .visibility = s1poe_visibility }, 3142 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 }, 3143 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 }, 3144 { SYS_DESC(SYS_TPIDR2_EL0), undef_access }, 3145 3146 { SYS_DESC(SYS_SCXTNUM_EL0), undef_access }, 3147 3148 { SYS_DESC(SYS_AMCR_EL0), undef_access }, 3149 { SYS_DESC(SYS_AMCFGR_EL0), undef_access }, 3150 { SYS_DESC(SYS_AMCGCR_EL0), undef_access }, 3151 { SYS_DESC(SYS_AMUSERENR_EL0), undef_access }, 3152 { SYS_DESC(SYS_AMCNTENCLR0_EL0), undef_access }, 3153 { SYS_DESC(SYS_AMCNTENSET0_EL0), undef_access }, 3154 { SYS_DESC(SYS_AMCNTENCLR1_EL0), undef_access }, 3155 { SYS_DESC(SYS_AMCNTENSET1_EL0), undef_access }, 3156 AMU_AMEVCNTR0_EL0(0), 3157 AMU_AMEVCNTR0_EL0(1), 3158 AMU_AMEVCNTR0_EL0(2), 3159 AMU_AMEVCNTR0_EL0(3), 3160 AMU_AMEVCNTR0_EL0(4), 3161 AMU_AMEVCNTR0_EL0(5), 3162 AMU_AMEVCNTR0_EL0(6), 3163 AMU_AMEVCNTR0_EL0(7), 3164 AMU_AMEVCNTR0_EL0(8), 3165 AMU_AMEVCNTR0_EL0(9), 3166 AMU_AMEVCNTR0_EL0(10), 3167 AMU_AMEVCNTR0_EL0(11), 3168 AMU_AMEVCNTR0_EL0(12), 3169 AMU_AMEVCNTR0_EL0(13), 3170 AMU_AMEVCNTR0_EL0(14), 3171 AMU_AMEVCNTR0_EL0(15), 3172 AMU_AMEVTYPER0_EL0(0), 3173 AMU_AMEVTYPER0_EL0(1), 3174 AMU_AMEVTYPER0_EL0(2), 3175 AMU_AMEVTYPER0_EL0(3), 3176 AMU_AMEVTYPER0_EL0(4), 3177 AMU_AMEVTYPER0_EL0(5), 3178 AMU_AMEVTYPER0_EL0(6), 3179 AMU_AMEVTYPER0_EL0(7), 3180 AMU_AMEVTYPER0_EL0(8), 3181 AMU_AMEVTYPER0_EL0(9), 3182 AMU_AMEVTYPER0_EL0(10), 3183 AMU_AMEVTYPER0_EL0(11), 3184 AMU_AMEVTYPER0_EL0(12), 3185 AMU_AMEVTYPER0_EL0(13), 3186 AMU_AMEVTYPER0_EL0(14), 3187 AMU_AMEVTYPER0_EL0(15), 3188 AMU_AMEVCNTR1_EL0(0), 3189 AMU_AMEVCNTR1_EL0(1), 3190 AMU_AMEVCNTR1_EL0(2), 3191 AMU_AMEVCNTR1_EL0(3), 3192 AMU_AMEVCNTR1_EL0(4), 3193 AMU_AMEVCNTR1_EL0(5), 3194 AMU_AMEVCNTR1_EL0(6), 3195 AMU_AMEVCNTR1_EL0(7), 3196 AMU_AMEVCNTR1_EL0(8), 3197 AMU_AMEVCNTR1_EL0(9), 3198 AMU_AMEVCNTR1_EL0(10), 3199 AMU_AMEVCNTR1_EL0(11), 3200 AMU_AMEVCNTR1_EL0(12), 3201 AMU_AMEVCNTR1_EL0(13), 3202 AMU_AMEVCNTR1_EL0(14), 3203 AMU_AMEVCNTR1_EL0(15), 3204 AMU_AMEVTYPER1_EL0(0), 3205 AMU_AMEVTYPER1_EL0(1), 3206 AMU_AMEVTYPER1_EL0(2), 3207 AMU_AMEVTYPER1_EL0(3), 3208 AMU_AMEVTYPER1_EL0(4), 3209 AMU_AMEVTYPER1_EL0(5), 3210 AMU_AMEVTYPER1_EL0(6), 3211 AMU_AMEVTYPER1_EL0(7), 3212 AMU_AMEVTYPER1_EL0(8), 3213 AMU_AMEVTYPER1_EL0(9), 3214 AMU_AMEVTYPER1_EL0(10), 3215 AMU_AMEVTYPER1_EL0(11), 3216 AMU_AMEVTYPER1_EL0(12), 3217 AMU_AMEVTYPER1_EL0(13), 3218 AMU_AMEVTYPER1_EL0(14), 3219 AMU_AMEVTYPER1_EL0(15), 3220 3221 { SYS_DESC(SYS_CNTPCT_EL0), access_arch_timer }, 3222 { SYS_DESC(SYS_CNTVCT_EL0), access_arch_timer }, 3223 { SYS_DESC(SYS_CNTPCTSS_EL0), access_arch_timer }, 3224 { SYS_DESC(SYS_CNTVCTSS_EL0), access_arch_timer }, 3225 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer }, 3226 { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer }, 3227 { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer }, 3228 3229 { SYS_DESC(SYS_CNTV_TVAL_EL0), access_arch_timer }, 3230 { SYS_DESC(SYS_CNTV_CTL_EL0), access_arch_timer }, 3231 { SYS_DESC(SYS_CNTV_CVAL_EL0), access_arch_timer }, 3232 3233 /* PMEVCNTRn_EL0 */ 3234 PMU_PMEVCNTR_EL0(0), 3235 PMU_PMEVCNTR_EL0(1), 3236 PMU_PMEVCNTR_EL0(2), 3237 PMU_PMEVCNTR_EL0(3), 3238 PMU_PMEVCNTR_EL0(4), 3239 PMU_PMEVCNTR_EL0(5), 3240 PMU_PMEVCNTR_EL0(6), 3241 PMU_PMEVCNTR_EL0(7), 3242 PMU_PMEVCNTR_EL0(8), 3243 PMU_PMEVCNTR_EL0(9), 3244 PMU_PMEVCNTR_EL0(10), 3245 PMU_PMEVCNTR_EL0(11), 3246 PMU_PMEVCNTR_EL0(12), 3247 PMU_PMEVCNTR_EL0(13), 3248 PMU_PMEVCNTR_EL0(14), 3249 PMU_PMEVCNTR_EL0(15), 3250 PMU_PMEVCNTR_EL0(16), 3251 PMU_PMEVCNTR_EL0(17), 3252 PMU_PMEVCNTR_EL0(18), 3253 PMU_PMEVCNTR_EL0(19), 3254 PMU_PMEVCNTR_EL0(20), 3255 PMU_PMEVCNTR_EL0(21), 3256 PMU_PMEVCNTR_EL0(22), 3257 PMU_PMEVCNTR_EL0(23), 3258 PMU_PMEVCNTR_EL0(24), 3259 PMU_PMEVCNTR_EL0(25), 3260 PMU_PMEVCNTR_EL0(26), 3261 PMU_PMEVCNTR_EL0(27), 3262 PMU_PMEVCNTR_EL0(28), 3263 PMU_PMEVCNTR_EL0(29), 3264 PMU_PMEVCNTR_EL0(30), 3265 /* PMEVTYPERn_EL0 */ 3266 PMU_PMEVTYPER_EL0(0), 3267 PMU_PMEVTYPER_EL0(1), 3268 PMU_PMEVTYPER_EL0(2), 3269 PMU_PMEVTYPER_EL0(3), 3270 PMU_PMEVTYPER_EL0(4), 3271 PMU_PMEVTYPER_EL0(5), 3272 PMU_PMEVTYPER_EL0(6), 3273 PMU_PMEVTYPER_EL0(7), 3274 PMU_PMEVTYPER_EL0(8), 3275 PMU_PMEVTYPER_EL0(9), 3276 PMU_PMEVTYPER_EL0(10), 3277 PMU_PMEVTYPER_EL0(11), 3278 PMU_PMEVTYPER_EL0(12), 3279 PMU_PMEVTYPER_EL0(13), 3280 PMU_PMEVTYPER_EL0(14), 3281 PMU_PMEVTYPER_EL0(15), 3282 PMU_PMEVTYPER_EL0(16), 3283 PMU_PMEVTYPER_EL0(17), 3284 PMU_PMEVTYPER_EL0(18), 3285 PMU_PMEVTYPER_EL0(19), 3286 PMU_PMEVTYPER_EL0(20), 3287 PMU_PMEVTYPER_EL0(21), 3288 PMU_PMEVTYPER_EL0(22), 3289 PMU_PMEVTYPER_EL0(23), 3290 PMU_PMEVTYPER_EL0(24), 3291 PMU_PMEVTYPER_EL0(25), 3292 PMU_PMEVTYPER_EL0(26), 3293 PMU_PMEVTYPER_EL0(27), 3294 PMU_PMEVTYPER_EL0(28), 3295 PMU_PMEVTYPER_EL0(29), 3296 PMU_PMEVTYPER_EL0(30), 3297 /* 3298 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero 3299 * in 32bit mode. Here we choose to reset it as zero for consistency. 3300 */ 3301 { PMU_SYS_REG(PMCCFILTR_EL0), .access = access_pmu_evtyper, 3302 .reset = reset_val, .reg = PMCCFILTR_EL0, .val = 0 }, 3303 3304 EL2_REG_VNCR(VPIDR_EL2, reset_unknown, 0), 3305 EL2_REG_VNCR(VMPIDR_EL2, reset_unknown, 0), 3306 EL2_REG(SCTLR_EL2, access_rw, reset_val, SCTLR_EL2_RES1), 3307 EL2_REG(ACTLR_EL2, access_rw, reset_val, 0), 3308 EL2_REG_VNCR(HCR_EL2, reset_hcr, 0), 3309 EL2_REG(MDCR_EL2, access_mdcr, reset_mdcr, 0), 3310 EL2_REG(CPTR_EL2, access_rw, reset_val, CPTR_NVHE_EL2_RES1), 3311 EL2_REG_VNCR(HSTR_EL2, reset_val, 0), 3312 EL2_REG_VNCR(HFGRTR_EL2, reset_val, 0), 3313 EL2_REG_VNCR(HFGWTR_EL2, reset_val, 0), 3314 EL2_REG_VNCR(HFGITR_EL2, reset_val, 0), 3315 EL2_REG_VNCR(HACR_EL2, reset_val, 0), 3316 3317 EL2_REG_FILTERED(ZCR_EL2, access_zcr_el2, reset_val, 0, 3318 sve_el2_visibility), 3319 3320 EL2_REG_VNCR(HCRX_EL2, reset_val, 0), 3321 3322 EL2_REG(TTBR0_EL2, access_rw, reset_val, 0), 3323 EL2_REG(TTBR1_EL2, access_rw, reset_val, 0), 3324 EL2_REG(TCR_EL2, access_rw, reset_val, TCR_EL2_RES1), 3325 EL2_REG_FILTERED(TCR2_EL2, access_rw, reset_val, TCR2_EL2_RES1, 3326 tcr2_el2_visibility), 3327 EL2_REG_VNCR(VTTBR_EL2, reset_val, 0), 3328 EL2_REG_VNCR(VTCR_EL2, reset_val, 0), 3329 EL2_REG_FILTERED(VNCR_EL2, bad_vncr_trap, reset_val, 0, 3330 vncr_el2_visibility), 3331 3332 { SYS_DESC(SYS_DACR32_EL2), undef_access, reset_unknown, DACR32_EL2 }, 3333 EL2_REG_VNCR(HDFGRTR_EL2, reset_val, 0), 3334 EL2_REG_VNCR(HDFGWTR_EL2, reset_val, 0), 3335 EL2_REG_VNCR(HAFGRTR_EL2, reset_val, 0), 3336 EL2_REG_REDIR(SPSR_EL2, reset_val, 0), 3337 EL2_REG_REDIR(ELR_EL2, reset_val, 0), 3338 { SYS_DESC(SYS_SP_EL1), access_sp_el1}, 3339 3340 /* AArch32 SPSR_* are RES0 if trapped from a NV guest */ 3341 { SYS_DESC(SYS_SPSR_irq), .access = trap_raz_wi }, 3342 { SYS_DESC(SYS_SPSR_abt), .access = trap_raz_wi }, 3343 { SYS_DESC(SYS_SPSR_und), .access = trap_raz_wi }, 3344 { SYS_DESC(SYS_SPSR_fiq), .access = trap_raz_wi }, 3345 3346 { SYS_DESC(SYS_IFSR32_EL2), undef_access, reset_unknown, IFSR32_EL2 }, 3347 EL2_REG(AFSR0_EL2, access_rw, reset_val, 0), 3348 EL2_REG(AFSR1_EL2, access_rw, reset_val, 0), 3349 EL2_REG_REDIR(ESR_EL2, reset_val, 0), 3350 { SYS_DESC(SYS_FPEXC32_EL2), undef_access, reset_val, FPEXC32_EL2, 0x700 }, 3351 3352 EL2_REG_REDIR(FAR_EL2, reset_val, 0), 3353 EL2_REG(HPFAR_EL2, access_rw, reset_val, 0), 3354 3355 EL2_REG(MAIR_EL2, access_rw, reset_val, 0), 3356 EL2_REG_FILTERED(PIRE0_EL2, access_rw, reset_val, 0, 3357 s1pie_el2_visibility), 3358 EL2_REG_FILTERED(PIR_EL2, access_rw, reset_val, 0, 3359 s1pie_el2_visibility), 3360 EL2_REG_FILTERED(POR_EL2, access_rw, reset_val, 0, 3361 s1poe_el2_visibility), 3362 EL2_REG(AMAIR_EL2, access_rw, reset_val, 0), 3363 { SYS_DESC(SYS_MPAMHCR_EL2), undef_access }, 3364 { SYS_DESC(SYS_MPAMVPMV_EL2), undef_access }, 3365 { SYS_DESC(SYS_MPAM2_EL2), undef_access }, 3366 { SYS_DESC(SYS_MPAMVPM0_EL2), undef_access }, 3367 { SYS_DESC(SYS_MPAMVPM1_EL2), undef_access }, 3368 { SYS_DESC(SYS_MPAMVPM2_EL2), undef_access }, 3369 { SYS_DESC(SYS_MPAMVPM3_EL2), undef_access }, 3370 { SYS_DESC(SYS_MPAMVPM4_EL2), undef_access }, 3371 { SYS_DESC(SYS_MPAMVPM5_EL2), undef_access }, 3372 { SYS_DESC(SYS_MPAMVPM6_EL2), undef_access }, 3373 { SYS_DESC(SYS_MPAMVPM7_EL2), undef_access }, 3374 3375 EL2_REG(VBAR_EL2, access_rw, reset_val, 0), 3376 EL2_REG(RVBAR_EL2, access_rw, reset_val, 0), 3377 { SYS_DESC(SYS_RMR_EL2), undef_access }, 3378 3379 EL2_REG_VNCR(ICH_AP0R0_EL2, reset_val, 0), 3380 EL2_REG_VNCR(ICH_AP0R1_EL2, reset_val, 0), 3381 EL2_REG_VNCR(ICH_AP0R2_EL2, reset_val, 0), 3382 EL2_REG_VNCR(ICH_AP0R3_EL2, reset_val, 0), 3383 EL2_REG_VNCR(ICH_AP1R0_EL2, reset_val, 0), 3384 EL2_REG_VNCR(ICH_AP1R1_EL2, reset_val, 0), 3385 EL2_REG_VNCR(ICH_AP1R2_EL2, reset_val, 0), 3386 EL2_REG_VNCR(ICH_AP1R3_EL2, reset_val, 0), 3387 3388 { SYS_DESC(SYS_ICC_SRE_EL2), access_gic_sre }, 3389 3390 EL2_REG_VNCR(ICH_HCR_EL2, reset_val, 0), 3391 { SYS_DESC(SYS_ICH_VTR_EL2), access_gic_vtr }, 3392 { SYS_DESC(SYS_ICH_MISR_EL2), access_gic_misr }, 3393 { SYS_DESC(SYS_ICH_EISR_EL2), access_gic_eisr }, 3394 { SYS_DESC(SYS_ICH_ELRSR_EL2), access_gic_elrsr }, 3395 EL2_REG_VNCR(ICH_VMCR_EL2, reset_val, 0), 3396 3397 EL2_REG_VNCR(ICH_LR0_EL2, reset_val, 0), 3398 EL2_REG_VNCR(ICH_LR1_EL2, reset_val, 0), 3399 EL2_REG_VNCR(ICH_LR2_EL2, reset_val, 0), 3400 EL2_REG_VNCR(ICH_LR3_EL2, reset_val, 0), 3401 EL2_REG_VNCR(ICH_LR4_EL2, reset_val, 0), 3402 EL2_REG_VNCR(ICH_LR5_EL2, reset_val, 0), 3403 EL2_REG_VNCR(ICH_LR6_EL2, reset_val, 0), 3404 EL2_REG_VNCR(ICH_LR7_EL2, reset_val, 0), 3405 EL2_REG_VNCR(ICH_LR8_EL2, reset_val, 0), 3406 EL2_REG_VNCR(ICH_LR9_EL2, reset_val, 0), 3407 EL2_REG_VNCR(ICH_LR10_EL2, reset_val, 0), 3408 EL2_REG_VNCR(ICH_LR11_EL2, reset_val, 0), 3409 EL2_REG_VNCR(ICH_LR12_EL2, reset_val, 0), 3410 EL2_REG_VNCR(ICH_LR13_EL2, reset_val, 0), 3411 EL2_REG_VNCR(ICH_LR14_EL2, reset_val, 0), 3412 EL2_REG_VNCR(ICH_LR15_EL2, reset_val, 0), 3413 3414 EL2_REG(CONTEXTIDR_EL2, access_rw, reset_val, 0), 3415 EL2_REG(TPIDR_EL2, access_rw, reset_val, 0), 3416 3417 EL2_REG_VNCR(CNTVOFF_EL2, reset_val, 0), 3418 EL2_REG(CNTHCTL_EL2, access_rw, reset_val, 0), 3419 { SYS_DESC(SYS_CNTHP_TVAL_EL2), access_arch_timer }, 3420 EL2_REG(CNTHP_CTL_EL2, access_arch_timer, reset_val, 0), 3421 EL2_REG(CNTHP_CVAL_EL2, access_arch_timer, reset_val, 0), 3422 3423 { SYS_DESC(SYS_CNTHV_TVAL_EL2), access_hv_timer }, 3424 EL2_REG(CNTHV_CTL_EL2, access_hv_timer, reset_val, 0), 3425 EL2_REG(CNTHV_CVAL_EL2, access_hv_timer, reset_val, 0), 3426 3427 { SYS_DESC(SYS_CNTKCTL_EL12), access_cntkctl_el12 }, 3428 3429 { SYS_DESC(SYS_CNTP_TVAL_EL02), access_arch_timer }, 3430 { SYS_DESC(SYS_CNTP_CTL_EL02), access_arch_timer }, 3431 { SYS_DESC(SYS_CNTP_CVAL_EL02), access_arch_timer }, 3432 3433 { SYS_DESC(SYS_CNTV_TVAL_EL02), access_arch_timer }, 3434 { SYS_DESC(SYS_CNTV_CTL_EL02), access_arch_timer }, 3435 { SYS_DESC(SYS_CNTV_CVAL_EL02), access_arch_timer }, 3436 3437 EL2_REG(SP_EL2, NULL, reset_unknown, 0), 3438 }; 3439 3440 static bool handle_at_s1e01(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3441 const struct sys_reg_desc *r) 3442 { 3443 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3444 3445 __kvm_at_s1e01(vcpu, op, p->regval); 3446 3447 return true; 3448 } 3449 3450 static bool handle_at_s1e2(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3451 const struct sys_reg_desc *r) 3452 { 3453 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3454 3455 /* There is no FGT associated with AT S1E2A :-( */ 3456 if (op == OP_AT_S1E2A && 3457 !kvm_has_feat(vcpu->kvm, ID_AA64ISAR2_EL1, ATS1A, IMP)) { 3458 kvm_inject_undefined(vcpu); 3459 return false; 3460 } 3461 3462 __kvm_at_s1e2(vcpu, op, p->regval); 3463 3464 return true; 3465 } 3466 3467 static bool handle_at_s12(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3468 const struct sys_reg_desc *r) 3469 { 3470 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3471 3472 __kvm_at_s12(vcpu, op, p->regval); 3473 3474 return true; 3475 } 3476 3477 static bool kvm_supported_tlbi_s12_op(struct kvm_vcpu *vpcu, u32 instr) 3478 { 3479 struct kvm *kvm = vpcu->kvm; 3480 u8 CRm = sys_reg_CRm(instr); 3481 3482 if (sys_reg_CRn(instr) == TLBI_CRn_nXS && 3483 !kvm_has_feat(kvm, ID_AA64ISAR1_EL1, XS, IMP)) 3484 return false; 3485 3486 if (CRm == TLBI_CRm_nROS && 3487 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 3488 return false; 3489 3490 return true; 3491 } 3492 3493 static bool handle_alle1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3494 const struct sys_reg_desc *r) 3495 { 3496 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3497 3498 if (!kvm_supported_tlbi_s12_op(vcpu, sys_encoding)) 3499 return undef_access(vcpu, p, r); 3500 3501 write_lock(&vcpu->kvm->mmu_lock); 3502 3503 /* 3504 * Drop all shadow S2s, resulting in S1/S2 TLBIs for each of the 3505 * corresponding VMIDs. 3506 */ 3507 kvm_nested_s2_unmap(vcpu->kvm, true); 3508 3509 write_unlock(&vcpu->kvm->mmu_lock); 3510 3511 return true; 3512 } 3513 3514 static bool kvm_supported_tlbi_ipas2_op(struct kvm_vcpu *vpcu, u32 instr) 3515 { 3516 struct kvm *kvm = vpcu->kvm; 3517 u8 CRm = sys_reg_CRm(instr); 3518 u8 Op2 = sys_reg_Op2(instr); 3519 3520 if (sys_reg_CRn(instr) == TLBI_CRn_nXS && 3521 !kvm_has_feat(kvm, ID_AA64ISAR1_EL1, XS, IMP)) 3522 return false; 3523 3524 if (CRm == TLBI_CRm_IPAIS && (Op2 == 2 || Op2 == 6) && 3525 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE)) 3526 return false; 3527 3528 if (CRm == TLBI_CRm_IPAONS && (Op2 == 0 || Op2 == 4) && 3529 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 3530 return false; 3531 3532 if (CRm == TLBI_CRm_IPAONS && (Op2 == 3 || Op2 == 7) && 3533 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE)) 3534 return false; 3535 3536 return true; 3537 } 3538 3539 /* Only defined here as this is an internal "abstraction" */ 3540 union tlbi_info { 3541 struct { 3542 u64 start; 3543 u64 size; 3544 } range; 3545 3546 struct { 3547 u64 addr; 3548 } ipa; 3549 3550 struct { 3551 u64 addr; 3552 u32 encoding; 3553 } va; 3554 }; 3555 3556 static void s2_mmu_unmap_range(struct kvm_s2_mmu *mmu, 3557 const union tlbi_info *info) 3558 { 3559 /* 3560 * The unmap operation is allowed to drop the MMU lock and block, which 3561 * means that @mmu could be used for a different context than the one 3562 * currently being invalidated. 3563 * 3564 * This behavior is still safe, as: 3565 * 3566 * 1) The vCPU(s) that recycled the MMU are responsible for invalidating 3567 * the entire MMU before reusing it, which still honors the intent 3568 * of a TLBI. 3569 * 3570 * 2) Until the guest TLBI instruction is 'retired' (i.e. increment PC 3571 * and ERET to the guest), other vCPUs are allowed to use stale 3572 * translations. 3573 * 3574 * 3) Accidentally unmapping an unrelated MMU context is nonfatal, and 3575 * at worst may cause more aborts for shadow stage-2 fills. 3576 * 3577 * Dropping the MMU lock also implies that shadow stage-2 fills could 3578 * happen behind the back of the TLBI. This is still safe, though, as 3579 * the L1 needs to put its stage-2 in a consistent state before doing 3580 * the TLBI. 3581 */ 3582 kvm_stage2_unmap_range(mmu, info->range.start, info->range.size, true); 3583 } 3584 3585 static bool handle_vmalls12e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3586 const struct sys_reg_desc *r) 3587 { 3588 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3589 u64 limit, vttbr; 3590 3591 if (!kvm_supported_tlbi_s12_op(vcpu, sys_encoding)) 3592 return undef_access(vcpu, p, r); 3593 3594 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 3595 limit = BIT_ULL(kvm_get_pa_bits(vcpu->kvm)); 3596 3597 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 3598 &(union tlbi_info) { 3599 .range = { 3600 .start = 0, 3601 .size = limit, 3602 }, 3603 }, 3604 s2_mmu_unmap_range); 3605 3606 return true; 3607 } 3608 3609 static bool handle_ripas2e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3610 const struct sys_reg_desc *r) 3611 { 3612 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3613 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 3614 u64 base, range; 3615 3616 if (!kvm_supported_tlbi_ipas2_op(vcpu, sys_encoding)) 3617 return undef_access(vcpu, p, r); 3618 3619 /* 3620 * Because the shadow S2 structure doesn't necessarily reflect that 3621 * of the guest's S2 (different base granule size, for example), we 3622 * decide to ignore TTL and only use the described range. 3623 */ 3624 base = decode_range_tlbi(p->regval, &range, NULL); 3625 3626 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 3627 &(union tlbi_info) { 3628 .range = { 3629 .start = base, 3630 .size = range, 3631 }, 3632 }, 3633 s2_mmu_unmap_range); 3634 3635 return true; 3636 } 3637 3638 static void s2_mmu_unmap_ipa(struct kvm_s2_mmu *mmu, 3639 const union tlbi_info *info) 3640 { 3641 unsigned long max_size; 3642 u64 base_addr; 3643 3644 /* 3645 * We drop a number of things from the supplied value: 3646 * 3647 * - NS bit: we're non-secure only. 3648 * 3649 * - IPA[51:48]: We don't support 52bit IPA just yet... 3650 * 3651 * And of course, adjust the IPA to be on an actual address. 3652 */ 3653 base_addr = (info->ipa.addr & GENMASK_ULL(35, 0)) << 12; 3654 max_size = compute_tlb_inval_range(mmu, info->ipa.addr); 3655 base_addr &= ~(max_size - 1); 3656 3657 /* 3658 * See comment in s2_mmu_unmap_range() for why this is allowed to 3659 * reschedule. 3660 */ 3661 kvm_stage2_unmap_range(mmu, base_addr, max_size, true); 3662 } 3663 3664 static bool handle_ipas2e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3665 const struct sys_reg_desc *r) 3666 { 3667 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3668 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 3669 3670 if (!kvm_supported_tlbi_ipas2_op(vcpu, sys_encoding)) 3671 return undef_access(vcpu, p, r); 3672 3673 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 3674 &(union tlbi_info) { 3675 .ipa = { 3676 .addr = p->regval, 3677 }, 3678 }, 3679 s2_mmu_unmap_ipa); 3680 3681 return true; 3682 } 3683 3684 static void s2_mmu_tlbi_s1e1(struct kvm_s2_mmu *mmu, 3685 const union tlbi_info *info) 3686 { 3687 WARN_ON(__kvm_tlbi_s1e2(mmu, info->va.addr, info->va.encoding)); 3688 } 3689 3690 static bool handle_tlbi_el2(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3691 const struct sys_reg_desc *r) 3692 { 3693 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3694 3695 if (!kvm_supported_tlbi_s1e2_op(vcpu, sys_encoding)) 3696 return undef_access(vcpu, p, r); 3697 3698 kvm_handle_s1e2_tlbi(vcpu, sys_encoding, p->regval); 3699 return true; 3700 } 3701 3702 static bool handle_tlbi_el1(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3703 const struct sys_reg_desc *r) 3704 { 3705 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3706 3707 /* 3708 * If we're here, this is because we've trapped on a EL1 TLBI 3709 * instruction that affects the EL1 translation regime while 3710 * we're running in a context that doesn't allow us to let the 3711 * HW do its thing (aka vEL2): 3712 * 3713 * - HCR_EL2.E2H == 0 : a non-VHE guest 3714 * - HCR_EL2.{E2H,TGE} == { 1, 0 } : a VHE guest in guest mode 3715 * 3716 * Another possibility is that we are invalidating the EL2 context 3717 * using EL1 instructions, but that we landed here because we need 3718 * additional invalidation for structures that are not held in the 3719 * CPU TLBs (such as the VNCR pseudo-TLB and its EL2 mapping). In 3720 * that case, we are guaranteed that HCR_EL2.{E2H,TGE} == { 1, 1 } 3721 * as we don't allow an NV-capable L1 in a nVHE configuration. 3722 * 3723 * We don't expect these helpers to ever be called when running 3724 * in a vEL1 context. 3725 */ 3726 3727 WARN_ON(!vcpu_is_el2(vcpu)); 3728 3729 if (!kvm_supported_tlbi_s1e1_op(vcpu, sys_encoding)) 3730 return undef_access(vcpu, p, r); 3731 3732 if (vcpu_el2_e2h_is_set(vcpu) && vcpu_el2_tge_is_set(vcpu)) { 3733 kvm_handle_s1e2_tlbi(vcpu, sys_encoding, p->regval); 3734 return true; 3735 } 3736 3737 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, 3738 get_vmid(__vcpu_sys_reg(vcpu, VTTBR_EL2)), 3739 &(union tlbi_info) { 3740 .va = { 3741 .addr = p->regval, 3742 .encoding = sys_encoding, 3743 }, 3744 }, 3745 s2_mmu_tlbi_s1e1); 3746 3747 return true; 3748 } 3749 3750 #define SYS_INSN(insn, access_fn) \ 3751 { \ 3752 SYS_DESC(OP_##insn), \ 3753 .access = (access_fn), \ 3754 } 3755 3756 static struct sys_reg_desc sys_insn_descs[] = { 3757 { SYS_DESC(SYS_DC_ISW), access_dcsw }, 3758 { SYS_DESC(SYS_DC_IGSW), access_dcgsw }, 3759 { SYS_DESC(SYS_DC_IGDSW), access_dcgsw }, 3760 3761 SYS_INSN(AT_S1E1R, handle_at_s1e01), 3762 SYS_INSN(AT_S1E1W, handle_at_s1e01), 3763 SYS_INSN(AT_S1E0R, handle_at_s1e01), 3764 SYS_INSN(AT_S1E0W, handle_at_s1e01), 3765 SYS_INSN(AT_S1E1RP, handle_at_s1e01), 3766 SYS_INSN(AT_S1E1WP, handle_at_s1e01), 3767 3768 { SYS_DESC(SYS_DC_CSW), access_dcsw }, 3769 { SYS_DESC(SYS_DC_CGSW), access_dcgsw }, 3770 { SYS_DESC(SYS_DC_CGDSW), access_dcgsw }, 3771 { SYS_DESC(SYS_DC_CISW), access_dcsw }, 3772 { SYS_DESC(SYS_DC_CIGSW), access_dcgsw }, 3773 { SYS_DESC(SYS_DC_CIGDSW), access_dcgsw }, 3774 3775 SYS_INSN(TLBI_VMALLE1OS, handle_tlbi_el1), 3776 SYS_INSN(TLBI_VAE1OS, handle_tlbi_el1), 3777 SYS_INSN(TLBI_ASIDE1OS, handle_tlbi_el1), 3778 SYS_INSN(TLBI_VAAE1OS, handle_tlbi_el1), 3779 SYS_INSN(TLBI_VALE1OS, handle_tlbi_el1), 3780 SYS_INSN(TLBI_VAALE1OS, handle_tlbi_el1), 3781 3782 SYS_INSN(TLBI_RVAE1IS, handle_tlbi_el1), 3783 SYS_INSN(TLBI_RVAAE1IS, handle_tlbi_el1), 3784 SYS_INSN(TLBI_RVALE1IS, handle_tlbi_el1), 3785 SYS_INSN(TLBI_RVAALE1IS, handle_tlbi_el1), 3786 3787 SYS_INSN(TLBI_VMALLE1IS, handle_tlbi_el1), 3788 SYS_INSN(TLBI_VAE1IS, handle_tlbi_el1), 3789 SYS_INSN(TLBI_ASIDE1IS, handle_tlbi_el1), 3790 SYS_INSN(TLBI_VAAE1IS, handle_tlbi_el1), 3791 SYS_INSN(TLBI_VALE1IS, handle_tlbi_el1), 3792 SYS_INSN(TLBI_VAALE1IS, handle_tlbi_el1), 3793 3794 SYS_INSN(TLBI_RVAE1OS, handle_tlbi_el1), 3795 SYS_INSN(TLBI_RVAAE1OS, handle_tlbi_el1), 3796 SYS_INSN(TLBI_RVALE1OS, handle_tlbi_el1), 3797 SYS_INSN(TLBI_RVAALE1OS, handle_tlbi_el1), 3798 3799 SYS_INSN(TLBI_RVAE1, handle_tlbi_el1), 3800 SYS_INSN(TLBI_RVAAE1, handle_tlbi_el1), 3801 SYS_INSN(TLBI_RVALE1, handle_tlbi_el1), 3802 SYS_INSN(TLBI_RVAALE1, handle_tlbi_el1), 3803 3804 SYS_INSN(TLBI_VMALLE1, handle_tlbi_el1), 3805 SYS_INSN(TLBI_VAE1, handle_tlbi_el1), 3806 SYS_INSN(TLBI_ASIDE1, handle_tlbi_el1), 3807 SYS_INSN(TLBI_VAAE1, handle_tlbi_el1), 3808 SYS_INSN(TLBI_VALE1, handle_tlbi_el1), 3809 SYS_INSN(TLBI_VAALE1, handle_tlbi_el1), 3810 3811 SYS_INSN(TLBI_VMALLE1OSNXS, handle_tlbi_el1), 3812 SYS_INSN(TLBI_VAE1OSNXS, handle_tlbi_el1), 3813 SYS_INSN(TLBI_ASIDE1OSNXS, handle_tlbi_el1), 3814 SYS_INSN(TLBI_VAAE1OSNXS, handle_tlbi_el1), 3815 SYS_INSN(TLBI_VALE1OSNXS, handle_tlbi_el1), 3816 SYS_INSN(TLBI_VAALE1OSNXS, handle_tlbi_el1), 3817 3818 SYS_INSN(TLBI_RVAE1ISNXS, handle_tlbi_el1), 3819 SYS_INSN(TLBI_RVAAE1ISNXS, handle_tlbi_el1), 3820 SYS_INSN(TLBI_RVALE1ISNXS, handle_tlbi_el1), 3821 SYS_INSN(TLBI_RVAALE1ISNXS, handle_tlbi_el1), 3822 3823 SYS_INSN(TLBI_VMALLE1ISNXS, handle_tlbi_el1), 3824 SYS_INSN(TLBI_VAE1ISNXS, handle_tlbi_el1), 3825 SYS_INSN(TLBI_ASIDE1ISNXS, handle_tlbi_el1), 3826 SYS_INSN(TLBI_VAAE1ISNXS, handle_tlbi_el1), 3827 SYS_INSN(TLBI_VALE1ISNXS, handle_tlbi_el1), 3828 SYS_INSN(TLBI_VAALE1ISNXS, handle_tlbi_el1), 3829 3830 SYS_INSN(TLBI_RVAE1OSNXS, handle_tlbi_el1), 3831 SYS_INSN(TLBI_RVAAE1OSNXS, handle_tlbi_el1), 3832 SYS_INSN(TLBI_RVALE1OSNXS, handle_tlbi_el1), 3833 SYS_INSN(TLBI_RVAALE1OSNXS, handle_tlbi_el1), 3834 3835 SYS_INSN(TLBI_RVAE1NXS, handle_tlbi_el1), 3836 SYS_INSN(TLBI_RVAAE1NXS, handle_tlbi_el1), 3837 SYS_INSN(TLBI_RVALE1NXS, handle_tlbi_el1), 3838 SYS_INSN(TLBI_RVAALE1NXS, handle_tlbi_el1), 3839 3840 SYS_INSN(TLBI_VMALLE1NXS, handle_tlbi_el1), 3841 SYS_INSN(TLBI_VAE1NXS, handle_tlbi_el1), 3842 SYS_INSN(TLBI_ASIDE1NXS, handle_tlbi_el1), 3843 SYS_INSN(TLBI_VAAE1NXS, handle_tlbi_el1), 3844 SYS_INSN(TLBI_VALE1NXS, handle_tlbi_el1), 3845 SYS_INSN(TLBI_VAALE1NXS, handle_tlbi_el1), 3846 3847 SYS_INSN(AT_S1E2R, handle_at_s1e2), 3848 SYS_INSN(AT_S1E2W, handle_at_s1e2), 3849 SYS_INSN(AT_S12E1R, handle_at_s12), 3850 SYS_INSN(AT_S12E1W, handle_at_s12), 3851 SYS_INSN(AT_S12E0R, handle_at_s12), 3852 SYS_INSN(AT_S12E0W, handle_at_s12), 3853 SYS_INSN(AT_S1E2A, handle_at_s1e2), 3854 3855 SYS_INSN(TLBI_IPAS2E1IS, handle_ipas2e1is), 3856 SYS_INSN(TLBI_RIPAS2E1IS, handle_ripas2e1is), 3857 SYS_INSN(TLBI_IPAS2LE1IS, handle_ipas2e1is), 3858 SYS_INSN(TLBI_RIPAS2LE1IS, handle_ripas2e1is), 3859 3860 SYS_INSN(TLBI_ALLE2OS, handle_tlbi_el2), 3861 SYS_INSN(TLBI_VAE2OS, handle_tlbi_el2), 3862 SYS_INSN(TLBI_ALLE1OS, handle_alle1is), 3863 SYS_INSN(TLBI_VALE2OS, handle_tlbi_el2), 3864 SYS_INSN(TLBI_VMALLS12E1OS, handle_vmalls12e1is), 3865 3866 SYS_INSN(TLBI_RVAE2IS, handle_tlbi_el2), 3867 SYS_INSN(TLBI_RVALE2IS, handle_tlbi_el2), 3868 SYS_INSN(TLBI_ALLE2IS, handle_tlbi_el2), 3869 SYS_INSN(TLBI_VAE2IS, handle_tlbi_el2), 3870 3871 SYS_INSN(TLBI_ALLE1IS, handle_alle1is), 3872 3873 SYS_INSN(TLBI_VALE2IS, handle_tlbi_el2), 3874 3875 SYS_INSN(TLBI_VMALLS12E1IS, handle_vmalls12e1is), 3876 SYS_INSN(TLBI_IPAS2E1OS, handle_ipas2e1is), 3877 SYS_INSN(TLBI_IPAS2E1, handle_ipas2e1is), 3878 SYS_INSN(TLBI_RIPAS2E1, handle_ripas2e1is), 3879 SYS_INSN(TLBI_RIPAS2E1OS, handle_ripas2e1is), 3880 SYS_INSN(TLBI_IPAS2LE1OS, handle_ipas2e1is), 3881 SYS_INSN(TLBI_IPAS2LE1, handle_ipas2e1is), 3882 SYS_INSN(TLBI_RIPAS2LE1, handle_ripas2e1is), 3883 SYS_INSN(TLBI_RIPAS2LE1OS, handle_ripas2e1is), 3884 SYS_INSN(TLBI_RVAE2OS, handle_tlbi_el2), 3885 SYS_INSN(TLBI_RVALE2OS, handle_tlbi_el2), 3886 SYS_INSN(TLBI_RVAE2, handle_tlbi_el2), 3887 SYS_INSN(TLBI_RVALE2, handle_tlbi_el2), 3888 SYS_INSN(TLBI_ALLE2, handle_tlbi_el2), 3889 SYS_INSN(TLBI_VAE2, handle_tlbi_el2), 3890 3891 SYS_INSN(TLBI_ALLE1, handle_alle1is), 3892 3893 SYS_INSN(TLBI_VALE2, handle_tlbi_el2), 3894 3895 SYS_INSN(TLBI_VMALLS12E1, handle_vmalls12e1is), 3896 3897 SYS_INSN(TLBI_IPAS2E1ISNXS, handle_ipas2e1is), 3898 SYS_INSN(TLBI_RIPAS2E1ISNXS, handle_ripas2e1is), 3899 SYS_INSN(TLBI_IPAS2LE1ISNXS, handle_ipas2e1is), 3900 SYS_INSN(TLBI_RIPAS2LE1ISNXS, handle_ripas2e1is), 3901 3902 SYS_INSN(TLBI_ALLE2OSNXS, handle_tlbi_el2), 3903 SYS_INSN(TLBI_VAE2OSNXS, handle_tlbi_el2), 3904 SYS_INSN(TLBI_ALLE1OSNXS, handle_alle1is), 3905 SYS_INSN(TLBI_VALE2OSNXS, handle_tlbi_el2), 3906 SYS_INSN(TLBI_VMALLS12E1OSNXS, handle_vmalls12e1is), 3907 3908 SYS_INSN(TLBI_RVAE2ISNXS, handle_tlbi_el2), 3909 SYS_INSN(TLBI_RVALE2ISNXS, handle_tlbi_el2), 3910 SYS_INSN(TLBI_ALLE2ISNXS, handle_tlbi_el2), 3911 SYS_INSN(TLBI_VAE2ISNXS, handle_tlbi_el2), 3912 3913 SYS_INSN(TLBI_ALLE1ISNXS, handle_alle1is), 3914 SYS_INSN(TLBI_VALE2ISNXS, handle_tlbi_el2), 3915 SYS_INSN(TLBI_VMALLS12E1ISNXS, handle_vmalls12e1is), 3916 SYS_INSN(TLBI_IPAS2E1OSNXS, handle_ipas2e1is), 3917 SYS_INSN(TLBI_IPAS2E1NXS, handle_ipas2e1is), 3918 SYS_INSN(TLBI_RIPAS2E1NXS, handle_ripas2e1is), 3919 SYS_INSN(TLBI_RIPAS2E1OSNXS, handle_ripas2e1is), 3920 SYS_INSN(TLBI_IPAS2LE1OSNXS, handle_ipas2e1is), 3921 SYS_INSN(TLBI_IPAS2LE1NXS, handle_ipas2e1is), 3922 SYS_INSN(TLBI_RIPAS2LE1NXS, handle_ripas2e1is), 3923 SYS_INSN(TLBI_RIPAS2LE1OSNXS, handle_ripas2e1is), 3924 SYS_INSN(TLBI_RVAE2OSNXS, handle_tlbi_el2), 3925 SYS_INSN(TLBI_RVALE2OSNXS, handle_tlbi_el2), 3926 SYS_INSN(TLBI_RVAE2NXS, handle_tlbi_el2), 3927 SYS_INSN(TLBI_RVALE2NXS, handle_tlbi_el2), 3928 SYS_INSN(TLBI_ALLE2NXS, handle_tlbi_el2), 3929 SYS_INSN(TLBI_VAE2NXS, handle_tlbi_el2), 3930 SYS_INSN(TLBI_ALLE1NXS, handle_alle1is), 3931 SYS_INSN(TLBI_VALE2NXS, handle_tlbi_el2), 3932 SYS_INSN(TLBI_VMALLS12E1NXS, handle_vmalls12e1is), 3933 }; 3934 3935 static bool trap_dbgdidr(struct kvm_vcpu *vcpu, 3936 struct sys_reg_params *p, 3937 const struct sys_reg_desc *r) 3938 { 3939 if (p->is_write) { 3940 return ignore_write(vcpu, p); 3941 } else { 3942 u64 dfr = kvm_read_vm_id_reg(vcpu->kvm, SYS_ID_AA64DFR0_EL1); 3943 u32 el3 = kvm_has_feat(vcpu->kvm, ID_AA64PFR0_EL1, EL3, IMP); 3944 3945 p->regval = ((SYS_FIELD_GET(ID_AA64DFR0_EL1, WRPs, dfr) << 28) | 3946 (SYS_FIELD_GET(ID_AA64DFR0_EL1, BRPs, dfr) << 24) | 3947 (SYS_FIELD_GET(ID_AA64DFR0_EL1, CTX_CMPs, dfr) << 20) | 3948 (SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, dfr) << 16) | 3949 (1 << 15) | (el3 << 14) | (el3 << 12)); 3950 return true; 3951 } 3952 } 3953 3954 /* 3955 * AArch32 debug register mappings 3956 * 3957 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0] 3958 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32] 3959 * 3960 * None of the other registers share their location, so treat them as 3961 * if they were 64bit. 3962 */ 3963 #define DBG_BCR_BVR_WCR_WVR(n) \ 3964 /* DBGBVRn */ \ 3965 { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), \ 3966 trap_dbg_wb_reg, NULL, n }, \ 3967 /* DBGBCRn */ \ 3968 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_dbg_wb_reg, NULL, n }, \ 3969 /* DBGWVRn */ \ 3970 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_dbg_wb_reg, NULL, n }, \ 3971 /* DBGWCRn */ \ 3972 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_dbg_wb_reg, NULL, n } 3973 3974 #define DBGBXVR(n) \ 3975 { AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), \ 3976 trap_dbg_wb_reg, NULL, n } 3977 3978 /* 3979 * Trapped cp14 registers. We generally ignore most of the external 3980 * debug, on the principle that they don't really make sense to a 3981 * guest. Revisit this one day, would this principle change. 3982 */ 3983 static const struct sys_reg_desc cp14_regs[] = { 3984 /* DBGDIDR */ 3985 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgdidr }, 3986 /* DBGDTRRXext */ 3987 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi }, 3988 3989 DBG_BCR_BVR_WCR_WVR(0), 3990 /* DBGDSCRint */ 3991 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi }, 3992 DBG_BCR_BVR_WCR_WVR(1), 3993 /* DBGDCCINT */ 3994 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug_regs, NULL, MDCCINT_EL1 }, 3995 /* DBGDSCRext */ 3996 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug_regs, NULL, MDSCR_EL1 }, 3997 DBG_BCR_BVR_WCR_WVR(2), 3998 /* DBGDTR[RT]Xint */ 3999 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi }, 4000 /* DBGDTR[RT]Xext */ 4001 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi }, 4002 DBG_BCR_BVR_WCR_WVR(3), 4003 DBG_BCR_BVR_WCR_WVR(4), 4004 DBG_BCR_BVR_WCR_WVR(5), 4005 /* DBGWFAR */ 4006 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi }, 4007 /* DBGOSECCR */ 4008 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi }, 4009 DBG_BCR_BVR_WCR_WVR(6), 4010 /* DBGVCR */ 4011 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug_regs, NULL, DBGVCR32_EL2 }, 4012 DBG_BCR_BVR_WCR_WVR(7), 4013 DBG_BCR_BVR_WCR_WVR(8), 4014 DBG_BCR_BVR_WCR_WVR(9), 4015 DBG_BCR_BVR_WCR_WVR(10), 4016 DBG_BCR_BVR_WCR_WVR(11), 4017 DBG_BCR_BVR_WCR_WVR(12), 4018 DBG_BCR_BVR_WCR_WVR(13), 4019 DBG_BCR_BVR_WCR_WVR(14), 4020 DBG_BCR_BVR_WCR_WVR(15), 4021 4022 /* DBGDRAR (32bit) */ 4023 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi }, 4024 4025 DBGBXVR(0), 4026 /* DBGOSLAR */ 4027 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_oslar_el1 }, 4028 DBGBXVR(1), 4029 /* DBGOSLSR */ 4030 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1, NULL, OSLSR_EL1 }, 4031 DBGBXVR(2), 4032 DBGBXVR(3), 4033 /* DBGOSDLR */ 4034 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi }, 4035 DBGBXVR(4), 4036 /* DBGPRCR */ 4037 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi }, 4038 DBGBXVR(5), 4039 DBGBXVR(6), 4040 DBGBXVR(7), 4041 DBGBXVR(8), 4042 DBGBXVR(9), 4043 DBGBXVR(10), 4044 DBGBXVR(11), 4045 DBGBXVR(12), 4046 DBGBXVR(13), 4047 DBGBXVR(14), 4048 DBGBXVR(15), 4049 4050 /* DBGDSAR (32bit) */ 4051 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi }, 4052 4053 /* DBGDEVID2 */ 4054 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi }, 4055 /* DBGDEVID1 */ 4056 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi }, 4057 /* DBGDEVID */ 4058 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi }, 4059 /* DBGCLAIMSET */ 4060 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi }, 4061 /* DBGCLAIMCLR */ 4062 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi }, 4063 /* DBGAUTHSTATUS */ 4064 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 }, 4065 }; 4066 4067 /* Trapped cp14 64bit registers */ 4068 static const struct sys_reg_desc cp14_64_regs[] = { 4069 /* DBGDRAR (64bit) */ 4070 { Op1( 0), CRm( 1), .access = trap_raz_wi }, 4071 4072 /* DBGDSAR (64bit) */ 4073 { Op1( 0), CRm( 2), .access = trap_raz_wi }, 4074 }; 4075 4076 #define CP15_PMU_SYS_REG(_map, _Op1, _CRn, _CRm, _Op2) \ 4077 AA32(_map), \ 4078 Op1(_Op1), CRn(_CRn), CRm(_CRm), Op2(_Op2), \ 4079 .visibility = pmu_visibility 4080 4081 /* Macro to expand the PMEVCNTRn register */ 4082 #define PMU_PMEVCNTR(n) \ 4083 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \ 4084 (0b1000 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \ 4085 .access = access_pmu_evcntr } 4086 4087 /* Macro to expand the PMEVTYPERn register */ 4088 #define PMU_PMEVTYPER(n) \ 4089 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \ 4090 (0b1100 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \ 4091 .access = access_pmu_evtyper } 4092 /* 4093 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding, 4094 * depending on the way they are accessed (as a 32bit or a 64bit 4095 * register). 4096 */ 4097 static const struct sys_reg_desc cp15_regs[] = { 4098 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr }, 4099 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, SCTLR_EL1 }, 4100 /* ACTLR */ 4101 { AA32(LO), Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr, NULL, ACTLR_EL1 }, 4102 /* ACTLR2 */ 4103 { AA32(HI), Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr, NULL, ACTLR_EL1 }, 4104 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, 4105 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, TTBR1_EL1 }, 4106 /* TTBCR */ 4107 { AA32(LO), Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 }, 4108 /* TTBCR2 */ 4109 { AA32(HI), Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, TCR_EL1 }, 4110 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, DACR32_EL2 }, 4111 { CP15_SYS_DESC(SYS_ICC_PMR_EL1), undef_access }, 4112 /* DFSR */ 4113 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, ESR_EL1 }, 4114 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, IFSR32_EL2 }, 4115 /* ADFSR */ 4116 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, AFSR0_EL1 }, 4117 /* AIFSR */ 4118 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, AFSR1_EL1 }, 4119 /* DFAR */ 4120 { AA32(LO), Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, FAR_EL1 }, 4121 /* IFAR */ 4122 { AA32(HI), Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, FAR_EL1 }, 4123 4124 /* 4125 * DC{C,I,CI}SW operations: 4126 */ 4127 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw }, 4128 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw }, 4129 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw }, 4130 4131 /* PMU */ 4132 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 0), .access = access_pmcr }, 4133 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 1), .access = access_pmcnten }, 4134 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 2), .access = access_pmcnten }, 4135 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 3), .access = access_pmovs }, 4136 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 4), .access = access_pmswinc }, 4137 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 5), .access = access_pmselr }, 4138 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 6), .access = access_pmceid }, 4139 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 7), .access = access_pmceid }, 4140 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 0), .access = access_pmu_evcntr }, 4141 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 1), .access = access_pmu_evtyper }, 4142 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 2), .access = access_pmu_evcntr }, 4143 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 0), .access = access_pmuserenr }, 4144 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 1), .access = access_pminten }, 4145 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 2), .access = access_pminten }, 4146 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 3), .access = access_pmovs }, 4147 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 4), .access = access_pmceid }, 4148 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 5), .access = access_pmceid }, 4149 /* PMMIR */ 4150 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 6), .access = trap_raz_wi }, 4151 4152 /* PRRR/MAIR0 */ 4153 { AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 }, 4154 /* NMRR/MAIR1 */ 4155 { AA32(HI), Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, MAIR_EL1 }, 4156 /* AMAIR0 */ 4157 { AA32(LO), Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, AMAIR_EL1 }, 4158 /* AMAIR1 */ 4159 { AA32(HI), Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, AMAIR_EL1 }, 4160 4161 { CP15_SYS_DESC(SYS_ICC_IAR0_EL1), undef_access }, 4162 { CP15_SYS_DESC(SYS_ICC_EOIR0_EL1), undef_access }, 4163 { CP15_SYS_DESC(SYS_ICC_HPPIR0_EL1), undef_access }, 4164 { CP15_SYS_DESC(SYS_ICC_BPR0_EL1), undef_access }, 4165 { CP15_SYS_DESC(SYS_ICC_AP0R0_EL1), undef_access }, 4166 { CP15_SYS_DESC(SYS_ICC_AP0R1_EL1), undef_access }, 4167 { CP15_SYS_DESC(SYS_ICC_AP0R2_EL1), undef_access }, 4168 { CP15_SYS_DESC(SYS_ICC_AP0R3_EL1), undef_access }, 4169 { CP15_SYS_DESC(SYS_ICC_AP1R0_EL1), undef_access }, 4170 { CP15_SYS_DESC(SYS_ICC_AP1R1_EL1), undef_access }, 4171 { CP15_SYS_DESC(SYS_ICC_AP1R2_EL1), undef_access }, 4172 { CP15_SYS_DESC(SYS_ICC_AP1R3_EL1), undef_access }, 4173 { CP15_SYS_DESC(SYS_ICC_DIR_EL1), undef_access }, 4174 { CP15_SYS_DESC(SYS_ICC_RPR_EL1), undef_access }, 4175 { CP15_SYS_DESC(SYS_ICC_IAR1_EL1), undef_access }, 4176 { CP15_SYS_DESC(SYS_ICC_EOIR1_EL1), undef_access }, 4177 { CP15_SYS_DESC(SYS_ICC_HPPIR1_EL1), undef_access }, 4178 { CP15_SYS_DESC(SYS_ICC_BPR1_EL1), undef_access }, 4179 { CP15_SYS_DESC(SYS_ICC_CTLR_EL1), undef_access }, 4180 { CP15_SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre }, 4181 { CP15_SYS_DESC(SYS_ICC_IGRPEN0_EL1), undef_access }, 4182 { CP15_SYS_DESC(SYS_ICC_IGRPEN1_EL1), undef_access }, 4183 4184 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, CONTEXTIDR_EL1 }, 4185 4186 /* Arch Tmers */ 4187 { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer }, 4188 { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer }, 4189 4190 /* PMEVCNTRn */ 4191 PMU_PMEVCNTR(0), 4192 PMU_PMEVCNTR(1), 4193 PMU_PMEVCNTR(2), 4194 PMU_PMEVCNTR(3), 4195 PMU_PMEVCNTR(4), 4196 PMU_PMEVCNTR(5), 4197 PMU_PMEVCNTR(6), 4198 PMU_PMEVCNTR(7), 4199 PMU_PMEVCNTR(8), 4200 PMU_PMEVCNTR(9), 4201 PMU_PMEVCNTR(10), 4202 PMU_PMEVCNTR(11), 4203 PMU_PMEVCNTR(12), 4204 PMU_PMEVCNTR(13), 4205 PMU_PMEVCNTR(14), 4206 PMU_PMEVCNTR(15), 4207 PMU_PMEVCNTR(16), 4208 PMU_PMEVCNTR(17), 4209 PMU_PMEVCNTR(18), 4210 PMU_PMEVCNTR(19), 4211 PMU_PMEVCNTR(20), 4212 PMU_PMEVCNTR(21), 4213 PMU_PMEVCNTR(22), 4214 PMU_PMEVCNTR(23), 4215 PMU_PMEVCNTR(24), 4216 PMU_PMEVCNTR(25), 4217 PMU_PMEVCNTR(26), 4218 PMU_PMEVCNTR(27), 4219 PMU_PMEVCNTR(28), 4220 PMU_PMEVCNTR(29), 4221 PMU_PMEVCNTR(30), 4222 /* PMEVTYPERn */ 4223 PMU_PMEVTYPER(0), 4224 PMU_PMEVTYPER(1), 4225 PMU_PMEVTYPER(2), 4226 PMU_PMEVTYPER(3), 4227 PMU_PMEVTYPER(4), 4228 PMU_PMEVTYPER(5), 4229 PMU_PMEVTYPER(6), 4230 PMU_PMEVTYPER(7), 4231 PMU_PMEVTYPER(8), 4232 PMU_PMEVTYPER(9), 4233 PMU_PMEVTYPER(10), 4234 PMU_PMEVTYPER(11), 4235 PMU_PMEVTYPER(12), 4236 PMU_PMEVTYPER(13), 4237 PMU_PMEVTYPER(14), 4238 PMU_PMEVTYPER(15), 4239 PMU_PMEVTYPER(16), 4240 PMU_PMEVTYPER(17), 4241 PMU_PMEVTYPER(18), 4242 PMU_PMEVTYPER(19), 4243 PMU_PMEVTYPER(20), 4244 PMU_PMEVTYPER(21), 4245 PMU_PMEVTYPER(22), 4246 PMU_PMEVTYPER(23), 4247 PMU_PMEVTYPER(24), 4248 PMU_PMEVTYPER(25), 4249 PMU_PMEVTYPER(26), 4250 PMU_PMEVTYPER(27), 4251 PMU_PMEVTYPER(28), 4252 PMU_PMEVTYPER(29), 4253 PMU_PMEVTYPER(30), 4254 /* PMCCFILTR */ 4255 { CP15_PMU_SYS_REG(DIRECT, 0, 14, 15, 7), .access = access_pmu_evtyper }, 4256 4257 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr }, 4258 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr }, 4259 4260 /* CCSIDR2 */ 4261 { Op1(1), CRn( 0), CRm( 0), Op2(2), undef_access }, 4262 4263 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 }, 4264 }; 4265 4266 static const struct sys_reg_desc cp15_64_regs[] = { 4267 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, 4268 { CP15_PMU_SYS_REG(DIRECT, 0, 0, 9, 0), .access = access_pmu_evcntr }, 4269 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */ 4270 { SYS_DESC(SYS_AARCH32_CNTPCT), access_arch_timer }, 4271 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 }, 4272 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */ 4273 { SYS_DESC(SYS_AARCH32_CNTVCT), access_arch_timer }, 4274 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */ 4275 { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer }, 4276 { SYS_DESC(SYS_AARCH32_CNTPCTSS), access_arch_timer }, 4277 { SYS_DESC(SYS_AARCH32_CNTVCTSS), access_arch_timer }, 4278 }; 4279 4280 static bool check_sysreg_table(const struct sys_reg_desc *table, unsigned int n, 4281 bool is_32) 4282 { 4283 unsigned int i; 4284 4285 for (i = 0; i < n; i++) { 4286 if (!is_32 && table[i].reg && !table[i].reset) { 4287 kvm_err("sys_reg table %pS entry %d (%s) lacks reset\n", 4288 &table[i], i, table[i].name); 4289 return false; 4290 } 4291 4292 if (i && cmp_sys_reg(&table[i-1], &table[i]) >= 0) { 4293 kvm_err("sys_reg table %pS entry %d (%s -> %s) out of order\n", 4294 &table[i], i, table[i - 1].name, table[i].name); 4295 return false; 4296 } 4297 } 4298 4299 return true; 4300 } 4301 4302 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu) 4303 { 4304 kvm_inject_undefined(vcpu); 4305 return 1; 4306 } 4307 4308 static void perform_access(struct kvm_vcpu *vcpu, 4309 struct sys_reg_params *params, 4310 const struct sys_reg_desc *r) 4311 { 4312 trace_kvm_sys_access(*vcpu_pc(vcpu), params, r); 4313 4314 /* Check for regs disabled by runtime config */ 4315 if (sysreg_hidden(vcpu, r)) { 4316 kvm_inject_undefined(vcpu); 4317 return; 4318 } 4319 4320 /* 4321 * Not having an accessor means that we have configured a trap 4322 * that we don't know how to handle. This certainly qualifies 4323 * as a gross bug that should be fixed right away. 4324 */ 4325 BUG_ON(!r->access); 4326 4327 /* Skip instruction if instructed so */ 4328 if (likely(r->access(vcpu, params, r))) 4329 kvm_incr_pc(vcpu); 4330 } 4331 4332 /* 4333 * emulate_cp -- tries to match a sys_reg access in a handling table, and 4334 * call the corresponding trap handler. 4335 * 4336 * @params: pointer to the descriptor of the access 4337 * @table: array of trap descriptors 4338 * @num: size of the trap descriptor array 4339 * 4340 * Return true if the access has been handled, false if not. 4341 */ 4342 static bool emulate_cp(struct kvm_vcpu *vcpu, 4343 struct sys_reg_params *params, 4344 const struct sys_reg_desc *table, 4345 size_t num) 4346 { 4347 const struct sys_reg_desc *r; 4348 4349 if (!table) 4350 return false; /* Not handled */ 4351 4352 r = find_reg(params, table, num); 4353 4354 if (r) { 4355 perform_access(vcpu, params, r); 4356 return true; 4357 } 4358 4359 /* Not handled */ 4360 return false; 4361 } 4362 4363 static void unhandled_cp_access(struct kvm_vcpu *vcpu, 4364 struct sys_reg_params *params) 4365 { 4366 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu); 4367 int cp = -1; 4368 4369 switch (esr_ec) { 4370 case ESR_ELx_EC_CP15_32: 4371 case ESR_ELx_EC_CP15_64: 4372 cp = 15; 4373 break; 4374 case ESR_ELx_EC_CP14_MR: 4375 case ESR_ELx_EC_CP14_64: 4376 cp = 14; 4377 break; 4378 default: 4379 WARN_ON(1); 4380 } 4381 4382 print_sys_reg_msg(params, 4383 "Unsupported guest CP%d access at: %08lx [%08lx]\n", 4384 cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 4385 kvm_inject_undefined(vcpu); 4386 } 4387 4388 /** 4389 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access 4390 * @vcpu: The VCPU pointer 4391 * @global: &struct sys_reg_desc 4392 * @nr_global: size of the @global array 4393 */ 4394 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu, 4395 const struct sys_reg_desc *global, 4396 size_t nr_global) 4397 { 4398 struct sys_reg_params params; 4399 u64 esr = kvm_vcpu_get_esr(vcpu); 4400 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4401 int Rt2 = (esr >> 10) & 0x1f; 4402 4403 params.CRm = (esr >> 1) & 0xf; 4404 params.is_write = ((esr & 1) == 0); 4405 4406 params.Op0 = 0; 4407 params.Op1 = (esr >> 16) & 0xf; 4408 params.Op2 = 0; 4409 params.CRn = 0; 4410 4411 /* 4412 * Make a 64-bit value out of Rt and Rt2. As we use the same trap 4413 * backends between AArch32 and AArch64, we get away with it. 4414 */ 4415 if (params.is_write) { 4416 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff; 4417 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32; 4418 } 4419 4420 /* 4421 * If the table contains a handler, handle the 4422 * potential register operation in the case of a read and return 4423 * with success. 4424 */ 4425 if (emulate_cp(vcpu, ¶ms, global, nr_global)) { 4426 /* Split up the value between registers for the read side */ 4427 if (!params.is_write) { 4428 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval)); 4429 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval)); 4430 } 4431 4432 return 1; 4433 } 4434 4435 unhandled_cp_access(vcpu, ¶ms); 4436 return 1; 4437 } 4438 4439 static bool emulate_sys_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *params); 4440 4441 /* 4442 * The CP10 ID registers are architecturally mapped to AArch64 feature 4443 * registers. Abuse that fact so we can rely on the AArch64 handler for accesses 4444 * from AArch32. 4445 */ 4446 static bool kvm_esr_cp10_id_to_sys64(u64 esr, struct sys_reg_params *params) 4447 { 4448 u8 reg_id = (esr >> 10) & 0xf; 4449 bool valid; 4450 4451 params->is_write = ((esr & 1) == 0); 4452 params->Op0 = 3; 4453 params->Op1 = 0; 4454 params->CRn = 0; 4455 params->CRm = 3; 4456 4457 /* CP10 ID registers are read-only */ 4458 valid = !params->is_write; 4459 4460 switch (reg_id) { 4461 /* MVFR0 */ 4462 case 0b0111: 4463 params->Op2 = 0; 4464 break; 4465 /* MVFR1 */ 4466 case 0b0110: 4467 params->Op2 = 1; 4468 break; 4469 /* MVFR2 */ 4470 case 0b0101: 4471 params->Op2 = 2; 4472 break; 4473 default: 4474 valid = false; 4475 } 4476 4477 if (valid) 4478 return true; 4479 4480 kvm_pr_unimpl("Unhandled cp10 register %s: %u\n", 4481 params->is_write ? "write" : "read", reg_id); 4482 return false; 4483 } 4484 4485 /** 4486 * kvm_handle_cp10_id() - Handles a VMRS trap on guest access to a 'Media and 4487 * VFP Register' from AArch32. 4488 * @vcpu: The vCPU pointer 4489 * 4490 * MVFR{0-2} are architecturally mapped to the AArch64 MVFR{0-2}_EL1 registers. 4491 * Work out the correct AArch64 system register encoding and reroute to the 4492 * AArch64 system register emulation. 4493 */ 4494 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu) 4495 { 4496 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4497 u64 esr = kvm_vcpu_get_esr(vcpu); 4498 struct sys_reg_params params; 4499 4500 /* UNDEF on any unhandled register access */ 4501 if (!kvm_esr_cp10_id_to_sys64(esr, ¶ms)) { 4502 kvm_inject_undefined(vcpu); 4503 return 1; 4504 } 4505 4506 if (emulate_sys_reg(vcpu, ¶ms)) 4507 vcpu_set_reg(vcpu, Rt, params.regval); 4508 4509 return 1; 4510 } 4511 4512 /** 4513 * kvm_emulate_cp15_id_reg() - Handles an MRC trap on a guest CP15 access where 4514 * CRn=0, which corresponds to the AArch32 feature 4515 * registers. 4516 * @vcpu: the vCPU pointer 4517 * @params: the system register access parameters. 4518 * 4519 * Our cp15 system register tables do not enumerate the AArch32 feature 4520 * registers. Conveniently, our AArch64 table does, and the AArch32 system 4521 * register encoding can be trivially remapped into the AArch64 for the feature 4522 * registers: Append op0=3, leaving op1, CRn, CRm, and op2 the same. 4523 * 4524 * According to DDI0487G.b G7.3.1, paragraph "Behavior of VMSAv8-32 32-bit 4525 * System registers with (coproc=0b1111, CRn==c0)", read accesses from this 4526 * range are either UNKNOWN or RES0. Rerouting remains architectural as we 4527 * treat undefined registers in this range as RAZ. 4528 */ 4529 static int kvm_emulate_cp15_id_reg(struct kvm_vcpu *vcpu, 4530 struct sys_reg_params *params) 4531 { 4532 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4533 4534 /* Treat impossible writes to RO registers as UNDEFINED */ 4535 if (params->is_write) { 4536 unhandled_cp_access(vcpu, params); 4537 return 1; 4538 } 4539 4540 params->Op0 = 3; 4541 4542 /* 4543 * All registers where CRm > 3 are known to be UNKNOWN/RAZ from AArch32. 4544 * Avoid conflicting with future expansion of AArch64 feature registers 4545 * and simply treat them as RAZ here. 4546 */ 4547 if (params->CRm > 3) 4548 params->regval = 0; 4549 else if (!emulate_sys_reg(vcpu, params)) 4550 return 1; 4551 4552 vcpu_set_reg(vcpu, Rt, params->regval); 4553 return 1; 4554 } 4555 4556 /** 4557 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access 4558 * @vcpu: The VCPU pointer 4559 * @params: &struct sys_reg_params 4560 * @global: &struct sys_reg_desc 4561 * @nr_global: size of the @global array 4562 */ 4563 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu, 4564 struct sys_reg_params *params, 4565 const struct sys_reg_desc *global, 4566 size_t nr_global) 4567 { 4568 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4569 4570 params->regval = vcpu_get_reg(vcpu, Rt); 4571 4572 if (emulate_cp(vcpu, params, global, nr_global)) { 4573 if (!params->is_write) 4574 vcpu_set_reg(vcpu, Rt, params->regval); 4575 return 1; 4576 } 4577 4578 unhandled_cp_access(vcpu, params); 4579 return 1; 4580 } 4581 4582 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu) 4583 { 4584 return kvm_handle_cp_64(vcpu, cp15_64_regs, ARRAY_SIZE(cp15_64_regs)); 4585 } 4586 4587 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu) 4588 { 4589 struct sys_reg_params params; 4590 4591 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu)); 4592 4593 /* 4594 * Certain AArch32 ID registers are handled by rerouting to the AArch64 4595 * system register table. Registers in the ID range where CRm=0 are 4596 * excluded from this scheme as they do not trivially map into AArch64 4597 * system register encodings, except for AIDR/REVIDR. 4598 */ 4599 if (params.Op1 == 0 && params.CRn == 0 && 4600 (params.CRm || params.Op2 == 6 /* REVIDR */)) 4601 return kvm_emulate_cp15_id_reg(vcpu, ¶ms); 4602 if (params.Op1 == 1 && params.CRn == 0 && 4603 params.CRm == 0 && params.Op2 == 7 /* AIDR */) 4604 return kvm_emulate_cp15_id_reg(vcpu, ¶ms); 4605 4606 return kvm_handle_cp_32(vcpu, ¶ms, cp15_regs, ARRAY_SIZE(cp15_regs)); 4607 } 4608 4609 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu) 4610 { 4611 return kvm_handle_cp_64(vcpu, cp14_64_regs, ARRAY_SIZE(cp14_64_regs)); 4612 } 4613 4614 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu) 4615 { 4616 struct sys_reg_params params; 4617 4618 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu)); 4619 4620 return kvm_handle_cp_32(vcpu, ¶ms, cp14_regs, ARRAY_SIZE(cp14_regs)); 4621 } 4622 4623 /** 4624 * emulate_sys_reg - Emulate a guest access to an AArch64 system register 4625 * @vcpu: The VCPU pointer 4626 * @params: Decoded system register parameters 4627 * 4628 * Return: true if the system register access was successful, false otherwise. 4629 */ 4630 static bool emulate_sys_reg(struct kvm_vcpu *vcpu, 4631 struct sys_reg_params *params) 4632 { 4633 const struct sys_reg_desc *r; 4634 4635 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 4636 if (likely(r)) { 4637 perform_access(vcpu, params, r); 4638 return true; 4639 } 4640 4641 print_sys_reg_msg(params, 4642 "Unsupported guest sys_reg access at: %lx [%08lx]\n", 4643 *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 4644 kvm_inject_undefined(vcpu); 4645 4646 return false; 4647 } 4648 4649 static const struct sys_reg_desc *idregs_debug_find(struct kvm *kvm, u8 pos) 4650 { 4651 unsigned long i, idreg_idx = 0; 4652 4653 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { 4654 const struct sys_reg_desc *r = &sys_reg_descs[i]; 4655 4656 if (!is_vm_ftr_id_reg(reg_to_encoding(r))) 4657 continue; 4658 4659 if (idreg_idx == pos) 4660 return r; 4661 4662 idreg_idx++; 4663 } 4664 4665 return NULL; 4666 } 4667 4668 static void *idregs_debug_start(struct seq_file *s, loff_t *pos) 4669 { 4670 struct kvm *kvm = s->private; 4671 u8 *iter; 4672 4673 mutex_lock(&kvm->arch.config_lock); 4674 4675 iter = &kvm->arch.idreg_debugfs_iter; 4676 if (test_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags) && 4677 *iter == (u8)~0) { 4678 *iter = *pos; 4679 if (!idregs_debug_find(kvm, *iter)) 4680 iter = NULL; 4681 } else { 4682 iter = ERR_PTR(-EBUSY); 4683 } 4684 4685 mutex_unlock(&kvm->arch.config_lock); 4686 4687 return iter; 4688 } 4689 4690 static void *idregs_debug_next(struct seq_file *s, void *v, loff_t *pos) 4691 { 4692 struct kvm *kvm = s->private; 4693 4694 (*pos)++; 4695 4696 if (idregs_debug_find(kvm, kvm->arch.idreg_debugfs_iter + 1)) { 4697 kvm->arch.idreg_debugfs_iter++; 4698 4699 return &kvm->arch.idreg_debugfs_iter; 4700 } 4701 4702 return NULL; 4703 } 4704 4705 static void idregs_debug_stop(struct seq_file *s, void *v) 4706 { 4707 struct kvm *kvm = s->private; 4708 4709 if (IS_ERR(v)) 4710 return; 4711 4712 mutex_lock(&kvm->arch.config_lock); 4713 4714 kvm->arch.idreg_debugfs_iter = ~0; 4715 4716 mutex_unlock(&kvm->arch.config_lock); 4717 } 4718 4719 static int idregs_debug_show(struct seq_file *s, void *v) 4720 { 4721 const struct sys_reg_desc *desc; 4722 struct kvm *kvm = s->private; 4723 4724 desc = idregs_debug_find(kvm, kvm->arch.idreg_debugfs_iter); 4725 4726 if (!desc->name) 4727 return 0; 4728 4729 seq_printf(s, "%20s:\t%016llx\n", 4730 desc->name, kvm_read_vm_id_reg(kvm, reg_to_encoding(desc))); 4731 4732 return 0; 4733 } 4734 4735 static const struct seq_operations idregs_debug_sops = { 4736 .start = idregs_debug_start, 4737 .next = idregs_debug_next, 4738 .stop = idregs_debug_stop, 4739 .show = idregs_debug_show, 4740 }; 4741 4742 DEFINE_SEQ_ATTRIBUTE(idregs_debug); 4743 4744 void kvm_sys_regs_create_debugfs(struct kvm *kvm) 4745 { 4746 kvm->arch.idreg_debugfs_iter = ~0; 4747 4748 debugfs_create_file("idregs", 0444, kvm->debugfs_dentry, kvm, 4749 &idregs_debug_fops); 4750 } 4751 4752 static void reset_vm_ftr_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *reg) 4753 { 4754 u32 id = reg_to_encoding(reg); 4755 struct kvm *kvm = vcpu->kvm; 4756 4757 if (test_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags)) 4758 return; 4759 4760 kvm_set_vm_id_reg(kvm, id, reg->reset(vcpu, reg)); 4761 } 4762 4763 static void reset_vcpu_ftr_id_reg(struct kvm_vcpu *vcpu, 4764 const struct sys_reg_desc *reg) 4765 { 4766 if (kvm_vcpu_initialized(vcpu)) 4767 return; 4768 4769 reg->reset(vcpu, reg); 4770 } 4771 4772 /** 4773 * kvm_reset_sys_regs - sets system registers to reset value 4774 * @vcpu: The VCPU pointer 4775 * 4776 * This function finds the right table above and sets the registers on the 4777 * virtual CPU struct to their architecturally defined reset values. 4778 */ 4779 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu) 4780 { 4781 struct kvm *kvm = vcpu->kvm; 4782 unsigned long i; 4783 4784 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { 4785 const struct sys_reg_desc *r = &sys_reg_descs[i]; 4786 4787 if (!r->reset) 4788 continue; 4789 4790 if (is_vm_ftr_id_reg(reg_to_encoding(r))) 4791 reset_vm_ftr_id_reg(vcpu, r); 4792 else if (is_vcpu_ftr_id_reg(reg_to_encoding(r))) 4793 reset_vcpu_ftr_id_reg(vcpu, r); 4794 else 4795 r->reset(vcpu, r); 4796 4797 if (r->reg >= __SANITISED_REG_START__ && r->reg < NR_SYS_REGS) 4798 (void)__vcpu_sys_reg(vcpu, r->reg); 4799 } 4800 4801 set_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags); 4802 4803 if (kvm_vcpu_has_pmu(vcpu)) 4804 kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu); 4805 } 4806 4807 /** 4808 * kvm_handle_sys_reg -- handles a system instruction or mrs/msr instruction 4809 * trap on a guest execution 4810 * @vcpu: The VCPU pointer 4811 */ 4812 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu) 4813 { 4814 const struct sys_reg_desc *desc = NULL; 4815 struct sys_reg_params params; 4816 unsigned long esr = kvm_vcpu_get_esr(vcpu); 4817 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4818 int sr_idx; 4819 4820 trace_kvm_handle_sys_reg(esr); 4821 4822 if (triage_sysreg_trap(vcpu, &sr_idx)) 4823 return 1; 4824 4825 params = esr_sys64_to_params(esr); 4826 params.regval = vcpu_get_reg(vcpu, Rt); 4827 4828 /* System registers have Op0=={2,3}, as per DDI487 J.a C5.1.2 */ 4829 if (params.Op0 == 2 || params.Op0 == 3) 4830 desc = &sys_reg_descs[sr_idx]; 4831 else 4832 desc = &sys_insn_descs[sr_idx]; 4833 4834 perform_access(vcpu, ¶ms, desc); 4835 4836 /* Read from system register? */ 4837 if (!params.is_write && 4838 (params.Op0 == 2 || params.Op0 == 3)) 4839 vcpu_set_reg(vcpu, Rt, params.regval); 4840 4841 return 1; 4842 } 4843 4844 /****************************************************************************** 4845 * Userspace API 4846 *****************************************************************************/ 4847 4848 static bool index_to_params(u64 id, struct sys_reg_params *params) 4849 { 4850 switch (id & KVM_REG_SIZE_MASK) { 4851 case KVM_REG_SIZE_U64: 4852 /* Any unused index bits means it's not valid. */ 4853 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK 4854 | KVM_REG_ARM_COPROC_MASK 4855 | KVM_REG_ARM64_SYSREG_OP0_MASK 4856 | KVM_REG_ARM64_SYSREG_OP1_MASK 4857 | KVM_REG_ARM64_SYSREG_CRN_MASK 4858 | KVM_REG_ARM64_SYSREG_CRM_MASK 4859 | KVM_REG_ARM64_SYSREG_OP2_MASK)) 4860 return false; 4861 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK) 4862 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT); 4863 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK) 4864 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT); 4865 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK) 4866 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT); 4867 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK) 4868 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT); 4869 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK) 4870 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT); 4871 return true; 4872 default: 4873 return false; 4874 } 4875 } 4876 4877 const struct sys_reg_desc *get_reg_by_id(u64 id, 4878 const struct sys_reg_desc table[], 4879 unsigned int num) 4880 { 4881 struct sys_reg_params params; 4882 4883 if (!index_to_params(id, ¶ms)) 4884 return NULL; 4885 4886 return find_reg(¶ms, table, num); 4887 } 4888 4889 /* Decode an index value, and find the sys_reg_desc entry. */ 4890 static const struct sys_reg_desc * 4891 id_to_sys_reg_desc(struct kvm_vcpu *vcpu, u64 id, 4892 const struct sys_reg_desc table[], unsigned int num) 4893 4894 { 4895 const struct sys_reg_desc *r; 4896 4897 /* We only do sys_reg for now. */ 4898 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG) 4899 return NULL; 4900 4901 r = get_reg_by_id(id, table, num); 4902 4903 /* Not saved in the sys_reg array and not otherwise accessible? */ 4904 if (r && (!(r->reg || r->get_user) || sysreg_hidden(vcpu, r))) 4905 r = NULL; 4906 4907 return r; 4908 } 4909 4910 static int demux_c15_get(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) 4911 { 4912 u32 val; 4913 u32 __user *uval = uaddr; 4914 4915 /* Fail if we have unknown bits set. */ 4916 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 4917 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 4918 return -ENOENT; 4919 4920 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 4921 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 4922 if (KVM_REG_SIZE(id) != 4) 4923 return -ENOENT; 4924 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 4925 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 4926 if (val >= CSSELR_MAX) 4927 return -ENOENT; 4928 4929 return put_user(get_ccsidr(vcpu, val), uval); 4930 default: 4931 return -ENOENT; 4932 } 4933 } 4934 4935 static int demux_c15_set(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) 4936 { 4937 u32 val, newval; 4938 u32 __user *uval = uaddr; 4939 4940 /* Fail if we have unknown bits set. */ 4941 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 4942 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 4943 return -ENOENT; 4944 4945 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 4946 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 4947 if (KVM_REG_SIZE(id) != 4) 4948 return -ENOENT; 4949 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 4950 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 4951 if (val >= CSSELR_MAX) 4952 return -ENOENT; 4953 4954 if (get_user(newval, uval)) 4955 return -EFAULT; 4956 4957 return set_ccsidr(vcpu, val, newval); 4958 default: 4959 return -ENOENT; 4960 } 4961 } 4962 4963 int kvm_sys_reg_get_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg, 4964 const struct sys_reg_desc table[], unsigned int num) 4965 { 4966 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr; 4967 const struct sys_reg_desc *r; 4968 u64 val; 4969 int ret; 4970 4971 r = id_to_sys_reg_desc(vcpu, reg->id, table, num); 4972 if (!r || sysreg_hidden(vcpu, r)) 4973 return -ENOENT; 4974 4975 if (r->get_user) { 4976 ret = (r->get_user)(vcpu, r, &val); 4977 } else { 4978 val = __vcpu_sys_reg(vcpu, r->reg); 4979 ret = 0; 4980 } 4981 4982 if (!ret) 4983 ret = put_user(val, uaddr); 4984 4985 return ret; 4986 } 4987 4988 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 4989 { 4990 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 4991 4992 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 4993 return demux_c15_get(vcpu, reg->id, uaddr); 4994 4995 return kvm_sys_reg_get_user(vcpu, reg, 4996 sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 4997 } 4998 4999 int kvm_sys_reg_set_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg, 5000 const struct sys_reg_desc table[], unsigned int num) 5001 { 5002 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr; 5003 const struct sys_reg_desc *r; 5004 u64 val; 5005 int ret; 5006 5007 if (get_user(val, uaddr)) 5008 return -EFAULT; 5009 5010 r = id_to_sys_reg_desc(vcpu, reg->id, table, num); 5011 if (!r || sysreg_hidden(vcpu, r)) 5012 return -ENOENT; 5013 5014 if (sysreg_user_write_ignore(vcpu, r)) 5015 return 0; 5016 5017 if (r->set_user) { 5018 ret = (r->set_user)(vcpu, r, val); 5019 } else { 5020 __vcpu_sys_reg(vcpu, r->reg) = val; 5021 ret = 0; 5022 } 5023 5024 return ret; 5025 } 5026 5027 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 5028 { 5029 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 5030 5031 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 5032 return demux_c15_set(vcpu, reg->id, uaddr); 5033 5034 return kvm_sys_reg_set_user(vcpu, reg, 5035 sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 5036 } 5037 5038 static unsigned int num_demux_regs(void) 5039 { 5040 return CSSELR_MAX; 5041 } 5042 5043 static int write_demux_regids(u64 __user *uindices) 5044 { 5045 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX; 5046 unsigned int i; 5047 5048 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR; 5049 for (i = 0; i < CSSELR_MAX; i++) { 5050 if (put_user(val | i, uindices)) 5051 return -EFAULT; 5052 uindices++; 5053 } 5054 return 0; 5055 } 5056 5057 static u64 sys_reg_to_index(const struct sys_reg_desc *reg) 5058 { 5059 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | 5060 KVM_REG_ARM64_SYSREG | 5061 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) | 5062 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) | 5063 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) | 5064 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) | 5065 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT)); 5066 } 5067 5068 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind) 5069 { 5070 if (!*uind) 5071 return true; 5072 5073 if (put_user(sys_reg_to_index(reg), *uind)) 5074 return false; 5075 5076 (*uind)++; 5077 return true; 5078 } 5079 5080 static int walk_one_sys_reg(const struct kvm_vcpu *vcpu, 5081 const struct sys_reg_desc *rd, 5082 u64 __user **uind, 5083 unsigned int *total) 5084 { 5085 /* 5086 * Ignore registers we trap but don't save, 5087 * and for which no custom user accessor is provided. 5088 */ 5089 if (!(rd->reg || rd->get_user)) 5090 return 0; 5091 5092 if (sysreg_hidden(vcpu, rd)) 5093 return 0; 5094 5095 if (!copy_reg_to_user(rd, uind)) 5096 return -EFAULT; 5097 5098 (*total)++; 5099 return 0; 5100 } 5101 5102 /* Assumed ordered tables, see kvm_sys_reg_table_init. */ 5103 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind) 5104 { 5105 const struct sys_reg_desc *i2, *end2; 5106 unsigned int total = 0; 5107 int err; 5108 5109 i2 = sys_reg_descs; 5110 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs); 5111 5112 while (i2 != end2) { 5113 err = walk_one_sys_reg(vcpu, i2++, &uind, &total); 5114 if (err) 5115 return err; 5116 } 5117 return total; 5118 } 5119 5120 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu) 5121 { 5122 return num_demux_regs() 5123 + walk_sys_regs(vcpu, (u64 __user *)NULL); 5124 } 5125 5126 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) 5127 { 5128 int err; 5129 5130 err = walk_sys_regs(vcpu, uindices); 5131 if (err < 0) 5132 return err; 5133 uindices += err; 5134 5135 return write_demux_regids(uindices); 5136 } 5137 5138 #define KVM_ARM_FEATURE_ID_RANGE_INDEX(r) \ 5139 KVM_ARM_FEATURE_ID_RANGE_IDX(sys_reg_Op0(r), \ 5140 sys_reg_Op1(r), \ 5141 sys_reg_CRn(r), \ 5142 sys_reg_CRm(r), \ 5143 sys_reg_Op2(r)) 5144 5145 int kvm_vm_ioctl_get_reg_writable_masks(struct kvm *kvm, struct reg_mask_range *range) 5146 { 5147 const void *zero_page = page_to_virt(ZERO_PAGE(0)); 5148 u64 __user *masks = (u64 __user *)range->addr; 5149 5150 /* Only feature id range is supported, reserved[13] must be zero. */ 5151 if (range->range || 5152 memcmp(range->reserved, zero_page, sizeof(range->reserved))) 5153 return -EINVAL; 5154 5155 /* Wipe the whole thing first */ 5156 if (clear_user(masks, KVM_ARM_FEATURE_ID_RANGE_SIZE * sizeof(__u64))) 5157 return -EFAULT; 5158 5159 for (int i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { 5160 const struct sys_reg_desc *reg = &sys_reg_descs[i]; 5161 u32 encoding = reg_to_encoding(reg); 5162 u64 val; 5163 5164 if (!is_feature_id_reg(encoding) || !reg->set_user) 5165 continue; 5166 5167 if (!reg->val || 5168 (is_aa32_id_reg(encoding) && !kvm_supports_32bit_el0())) { 5169 continue; 5170 } 5171 val = reg->val; 5172 5173 if (put_user(val, (masks + KVM_ARM_FEATURE_ID_RANGE_INDEX(encoding)))) 5174 return -EFAULT; 5175 } 5176 5177 return 0; 5178 } 5179 5180 static void vcpu_set_hcr(struct kvm_vcpu *vcpu) 5181 { 5182 struct kvm *kvm = vcpu->kvm; 5183 5184 if (has_vhe() || has_hvhe()) 5185 vcpu->arch.hcr_el2 |= HCR_E2H; 5186 if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN)) { 5187 /* route synchronous external abort exceptions to EL2 */ 5188 vcpu->arch.hcr_el2 |= HCR_TEA; 5189 /* trap error record accesses */ 5190 vcpu->arch.hcr_el2 |= HCR_TERR; 5191 } 5192 5193 if (cpus_have_final_cap(ARM64_HAS_STAGE2_FWB)) 5194 vcpu->arch.hcr_el2 |= HCR_FWB; 5195 5196 if (cpus_have_final_cap(ARM64_HAS_EVT) && 5197 !cpus_have_final_cap(ARM64_MISMATCHED_CACHE_TYPE) && 5198 kvm_read_vm_id_reg(kvm, SYS_CTR_EL0) == read_sanitised_ftr_reg(SYS_CTR_EL0)) 5199 vcpu->arch.hcr_el2 |= HCR_TID4; 5200 else 5201 vcpu->arch.hcr_el2 |= HCR_TID2; 5202 5203 if (vcpu_el1_is_32bit(vcpu)) 5204 vcpu->arch.hcr_el2 &= ~HCR_RW; 5205 5206 if (kvm_has_mte(vcpu->kvm)) 5207 vcpu->arch.hcr_el2 |= HCR_ATA; 5208 5209 /* 5210 * In the absence of FGT, we cannot independently trap TLBI 5211 * Range instructions. This isn't great, but trapping all 5212 * TLBIs would be far worse. Live with it... 5213 */ 5214 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 5215 vcpu->arch.hcr_el2 |= HCR_TTLBOS; 5216 } 5217 5218 void kvm_calculate_traps(struct kvm_vcpu *vcpu) 5219 { 5220 struct kvm *kvm = vcpu->kvm; 5221 5222 mutex_lock(&kvm->arch.config_lock); 5223 vcpu_set_hcr(vcpu); 5224 vcpu_set_ich_hcr(vcpu); 5225 vcpu_set_hcrx(vcpu); 5226 5227 if (test_bit(KVM_ARCH_FLAG_FGU_INITIALIZED, &kvm->arch.flags)) 5228 goto out; 5229 5230 compute_fgu(kvm, HFGRTR_GROUP); 5231 compute_fgu(kvm, HFGITR_GROUP); 5232 compute_fgu(kvm, HDFGRTR_GROUP); 5233 compute_fgu(kvm, HAFGRTR_GROUP); 5234 compute_fgu(kvm, HFGRTR2_GROUP); 5235 compute_fgu(kvm, HFGITR2_GROUP); 5236 compute_fgu(kvm, HDFGRTR2_GROUP); 5237 5238 set_bit(KVM_ARCH_FLAG_FGU_INITIALIZED, &kvm->arch.flags); 5239 out: 5240 mutex_unlock(&kvm->arch.config_lock); 5241 } 5242 5243 /* 5244 * Perform last adjustments to the ID registers that are implied by the 5245 * configuration outside of the ID regs themselves, as well as any 5246 * initialisation that directly depend on these ID registers (such as 5247 * RES0/RES1 behaviours). This is not the place to configure traps though. 5248 * 5249 * Because this can be called once per CPU, changes must be idempotent. 5250 */ 5251 int kvm_finalize_sys_regs(struct kvm_vcpu *vcpu) 5252 { 5253 struct kvm *kvm = vcpu->kvm; 5254 5255 guard(mutex)(&kvm->arch.config_lock); 5256 5257 if (!(static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif) && 5258 irqchip_in_kernel(kvm) && 5259 kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3)) { 5260 kvm->arch.id_regs[IDREG_IDX(SYS_ID_AA64PFR0_EL1)] &= ~ID_AA64PFR0_EL1_GIC_MASK; 5261 kvm->arch.id_regs[IDREG_IDX(SYS_ID_PFR1_EL1)] &= ~ID_PFR1_EL1_GIC_MASK; 5262 } 5263 5264 if (vcpu_has_nv(vcpu)) { 5265 int ret = kvm_init_nv_sysregs(vcpu); 5266 if (ret) 5267 return ret; 5268 } 5269 5270 return 0; 5271 } 5272 5273 int __init kvm_sys_reg_table_init(void) 5274 { 5275 bool valid = true; 5276 unsigned int i; 5277 int ret = 0; 5278 5279 /* Make sure tables are unique and in order. */ 5280 valid &= check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), false); 5281 valid &= check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), true); 5282 valid &= check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), true); 5283 valid &= check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), true); 5284 valid &= check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), true); 5285 valid &= check_sysreg_table(sys_insn_descs, ARRAY_SIZE(sys_insn_descs), false); 5286 5287 if (!valid) 5288 return -EINVAL; 5289 5290 init_imp_id_regs(); 5291 5292 ret = populate_nv_trap_config(); 5293 5294 check_feature_map(); 5295 5296 for (i = 0; !ret && i < ARRAY_SIZE(sys_reg_descs); i++) 5297 ret = populate_sysreg_config(sys_reg_descs + i, i); 5298 5299 for (i = 0; !ret && i < ARRAY_SIZE(sys_insn_descs); i++) 5300 ret = populate_sysreg_config(sys_insn_descs + i, i); 5301 5302 return ret; 5303 } 5304