1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/kvm/coproc.c: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Authors: Rusty Russell <rusty@rustcorp.com.au> 9 * Christoffer Dall <c.dall@virtualopensystems.com> 10 */ 11 12 #include <linux/bitfield.h> 13 #include <linux/bsearch.h> 14 #include <linux/cacheinfo.h> 15 #include <linux/debugfs.h> 16 #include <linux/kvm_host.h> 17 #include <linux/mm.h> 18 #include <linux/printk.h> 19 #include <linux/uaccess.h> 20 21 #include <asm/arm_pmuv3.h> 22 #include <asm/cacheflush.h> 23 #include <asm/cputype.h> 24 #include <asm/debug-monitors.h> 25 #include <asm/esr.h> 26 #include <asm/kvm_arm.h> 27 #include <asm/kvm_emulate.h> 28 #include <asm/kvm_hyp.h> 29 #include <asm/kvm_mmu.h> 30 #include <asm/kvm_nested.h> 31 #include <asm/perf_event.h> 32 #include <asm/sysreg.h> 33 34 #include <trace/events/kvm.h> 35 36 #include "sys_regs.h" 37 #include "vgic/vgic.h" 38 39 #include "trace.h" 40 41 /* 42 * For AArch32, we only take care of what is being trapped. Anything 43 * that has to do with init and userspace access has to go via the 44 * 64bit interface. 45 */ 46 47 static u64 sys_reg_to_index(const struct sys_reg_desc *reg); 48 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 49 u64 val); 50 51 static bool undef_access(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 52 const struct sys_reg_desc *r) 53 { 54 kvm_inject_undefined(vcpu); 55 return false; 56 } 57 58 static bool bad_trap(struct kvm_vcpu *vcpu, 59 struct sys_reg_params *params, 60 const struct sys_reg_desc *r, 61 const char *msg) 62 { 63 WARN_ONCE(1, "Unexpected %s\n", msg); 64 print_sys_reg_instr(params); 65 return undef_access(vcpu, params, r); 66 } 67 68 static bool read_from_write_only(struct kvm_vcpu *vcpu, 69 struct sys_reg_params *params, 70 const struct sys_reg_desc *r) 71 { 72 return bad_trap(vcpu, params, r, 73 "sys_reg read to write-only register"); 74 } 75 76 static bool write_to_read_only(struct kvm_vcpu *vcpu, 77 struct sys_reg_params *params, 78 const struct sys_reg_desc *r) 79 { 80 return bad_trap(vcpu, params, r, 81 "sys_reg write to read-only register"); 82 } 83 84 #define PURE_EL2_SYSREG(el2) \ 85 case el2: { \ 86 *el1r = el2; \ 87 return true; \ 88 } 89 90 #define MAPPED_EL2_SYSREG(el2, el1, fn) \ 91 case el2: { \ 92 *xlate = fn; \ 93 *el1r = el1; \ 94 return true; \ 95 } 96 97 static bool get_el2_to_el1_mapping(unsigned int reg, 98 unsigned int *el1r, u64 (**xlate)(u64)) 99 { 100 switch (reg) { 101 PURE_EL2_SYSREG( VPIDR_EL2 ); 102 PURE_EL2_SYSREG( VMPIDR_EL2 ); 103 PURE_EL2_SYSREG( ACTLR_EL2 ); 104 PURE_EL2_SYSREG( HCR_EL2 ); 105 PURE_EL2_SYSREG( MDCR_EL2 ); 106 PURE_EL2_SYSREG( HSTR_EL2 ); 107 PURE_EL2_SYSREG( HACR_EL2 ); 108 PURE_EL2_SYSREG( VTTBR_EL2 ); 109 PURE_EL2_SYSREG( VTCR_EL2 ); 110 PURE_EL2_SYSREG( RVBAR_EL2 ); 111 PURE_EL2_SYSREG( TPIDR_EL2 ); 112 PURE_EL2_SYSREG( HPFAR_EL2 ); 113 PURE_EL2_SYSREG( HCRX_EL2 ); 114 PURE_EL2_SYSREG( HFGRTR_EL2 ); 115 PURE_EL2_SYSREG( HFGWTR_EL2 ); 116 PURE_EL2_SYSREG( HFGITR_EL2 ); 117 PURE_EL2_SYSREG( HDFGRTR_EL2 ); 118 PURE_EL2_SYSREG( HDFGWTR_EL2 ); 119 PURE_EL2_SYSREG( HAFGRTR_EL2 ); 120 PURE_EL2_SYSREG( CNTVOFF_EL2 ); 121 PURE_EL2_SYSREG( CNTHCTL_EL2 ); 122 MAPPED_EL2_SYSREG(SCTLR_EL2, SCTLR_EL1, 123 translate_sctlr_el2_to_sctlr_el1 ); 124 MAPPED_EL2_SYSREG(CPTR_EL2, CPACR_EL1, 125 translate_cptr_el2_to_cpacr_el1 ); 126 MAPPED_EL2_SYSREG(TTBR0_EL2, TTBR0_EL1, 127 translate_ttbr0_el2_to_ttbr0_el1 ); 128 MAPPED_EL2_SYSREG(TTBR1_EL2, TTBR1_EL1, NULL ); 129 MAPPED_EL2_SYSREG(TCR_EL2, TCR_EL1, 130 translate_tcr_el2_to_tcr_el1 ); 131 MAPPED_EL2_SYSREG(VBAR_EL2, VBAR_EL1, NULL ); 132 MAPPED_EL2_SYSREG(AFSR0_EL2, AFSR0_EL1, NULL ); 133 MAPPED_EL2_SYSREG(AFSR1_EL2, AFSR1_EL1, NULL ); 134 MAPPED_EL2_SYSREG(ESR_EL2, ESR_EL1, NULL ); 135 MAPPED_EL2_SYSREG(FAR_EL2, FAR_EL1, NULL ); 136 MAPPED_EL2_SYSREG(MAIR_EL2, MAIR_EL1, NULL ); 137 MAPPED_EL2_SYSREG(TCR2_EL2, TCR2_EL1, NULL ); 138 MAPPED_EL2_SYSREG(PIR_EL2, PIR_EL1, NULL ); 139 MAPPED_EL2_SYSREG(PIRE0_EL2, PIRE0_EL1, NULL ); 140 MAPPED_EL2_SYSREG(POR_EL2, POR_EL1, NULL ); 141 MAPPED_EL2_SYSREG(AMAIR_EL2, AMAIR_EL1, NULL ); 142 MAPPED_EL2_SYSREG(ELR_EL2, ELR_EL1, NULL ); 143 MAPPED_EL2_SYSREG(SPSR_EL2, SPSR_EL1, NULL ); 144 MAPPED_EL2_SYSREG(ZCR_EL2, ZCR_EL1, NULL ); 145 MAPPED_EL2_SYSREG(CONTEXTIDR_EL2, CONTEXTIDR_EL1, NULL ); 146 default: 147 return false; 148 } 149 } 150 151 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg) 152 { 153 u64 val = 0x8badf00d8badf00d; 154 u64 (*xlate)(u64) = NULL; 155 unsigned int el1r; 156 157 if (!vcpu_get_flag(vcpu, SYSREGS_ON_CPU)) 158 goto memory_read; 159 160 if (unlikely(get_el2_to_el1_mapping(reg, &el1r, &xlate))) { 161 if (!is_hyp_ctxt(vcpu)) 162 goto memory_read; 163 164 /* 165 * CNTHCTL_EL2 requires some special treatment to 166 * account for the bits that can be set via CNTKCTL_EL1. 167 */ 168 switch (reg) { 169 case CNTHCTL_EL2: 170 if (vcpu_el2_e2h_is_set(vcpu)) { 171 val = read_sysreg_el1(SYS_CNTKCTL); 172 val &= CNTKCTL_VALID_BITS; 173 val |= __vcpu_sys_reg(vcpu, reg) & ~CNTKCTL_VALID_BITS; 174 return val; 175 } 176 break; 177 } 178 179 /* 180 * If this register does not have an EL1 counterpart, 181 * then read the stored EL2 version. 182 */ 183 if (reg == el1r) 184 goto memory_read; 185 186 /* 187 * If we have a non-VHE guest and that the sysreg 188 * requires translation to be used at EL1, use the 189 * in-memory copy instead. 190 */ 191 if (!vcpu_el2_e2h_is_set(vcpu) && xlate) 192 goto memory_read; 193 194 /* Get the current version of the EL1 counterpart. */ 195 WARN_ON(!__vcpu_read_sys_reg_from_cpu(el1r, &val)); 196 if (reg >= __SANITISED_REG_START__) 197 val = kvm_vcpu_apply_reg_masks(vcpu, reg, val); 198 199 return val; 200 } 201 202 /* EL1 register can't be on the CPU if the guest is in vEL2. */ 203 if (unlikely(is_hyp_ctxt(vcpu))) 204 goto memory_read; 205 206 if (__vcpu_read_sys_reg_from_cpu(reg, &val)) 207 return val; 208 209 memory_read: 210 return __vcpu_sys_reg(vcpu, reg); 211 } 212 213 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg) 214 { 215 u64 (*xlate)(u64) = NULL; 216 unsigned int el1r; 217 218 if (!vcpu_get_flag(vcpu, SYSREGS_ON_CPU)) 219 goto memory_write; 220 221 if (unlikely(get_el2_to_el1_mapping(reg, &el1r, &xlate))) { 222 if (!is_hyp_ctxt(vcpu)) 223 goto memory_write; 224 225 /* 226 * Always store a copy of the write to memory to avoid having 227 * to reverse-translate virtual EL2 system registers for a 228 * non-VHE guest hypervisor. 229 */ 230 __vcpu_sys_reg(vcpu, reg) = val; 231 232 switch (reg) { 233 case CNTHCTL_EL2: 234 /* 235 * If E2H=0, CNHTCTL_EL2 is a pure shadow register. 236 * Otherwise, some of the bits are backed by 237 * CNTKCTL_EL1, while the rest is kept in memory. 238 * Yes, this is fun stuff. 239 */ 240 if (vcpu_el2_e2h_is_set(vcpu)) 241 write_sysreg_el1(val, SYS_CNTKCTL); 242 return; 243 } 244 245 /* No EL1 counterpart? We're done here.? */ 246 if (reg == el1r) 247 return; 248 249 if (!vcpu_el2_e2h_is_set(vcpu) && xlate) 250 val = xlate(val); 251 252 /* Redirect this to the EL1 version of the register. */ 253 WARN_ON(!__vcpu_write_sys_reg_to_cpu(val, el1r)); 254 return; 255 } 256 257 /* EL1 register can't be on the CPU if the guest is in vEL2. */ 258 if (unlikely(is_hyp_ctxt(vcpu))) 259 goto memory_write; 260 261 if (__vcpu_write_sys_reg_to_cpu(val, reg)) 262 return; 263 264 memory_write: 265 __vcpu_sys_reg(vcpu, reg) = val; 266 } 267 268 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */ 269 #define CSSELR_MAX 14 270 271 /* 272 * Returns the minimum line size for the selected cache, expressed as 273 * Log2(bytes). 274 */ 275 static u8 get_min_cache_line_size(bool icache) 276 { 277 u64 ctr = read_sanitised_ftr_reg(SYS_CTR_EL0); 278 u8 field; 279 280 if (icache) 281 field = SYS_FIELD_GET(CTR_EL0, IminLine, ctr); 282 else 283 field = SYS_FIELD_GET(CTR_EL0, DminLine, ctr); 284 285 /* 286 * Cache line size is represented as Log2(words) in CTR_EL0. 287 * Log2(bytes) can be derived with the following: 288 * 289 * Log2(words) + 2 = Log2(bytes / 4) + 2 290 * = Log2(bytes) - 2 + 2 291 * = Log2(bytes) 292 */ 293 return field + 2; 294 } 295 296 /* Which cache CCSIDR represents depends on CSSELR value. */ 297 static u32 get_ccsidr(struct kvm_vcpu *vcpu, u32 csselr) 298 { 299 u8 line_size; 300 301 if (vcpu->arch.ccsidr) 302 return vcpu->arch.ccsidr[csselr]; 303 304 line_size = get_min_cache_line_size(csselr & CSSELR_EL1_InD); 305 306 /* 307 * Fabricate a CCSIDR value as the overriding value does not exist. 308 * The real CCSIDR value will not be used as it can vary by the 309 * physical CPU which the vcpu currently resides in. 310 * 311 * The line size is determined with get_min_cache_line_size(), which 312 * should be valid for all CPUs even if they have different cache 313 * configuration. 314 * 315 * The associativity bits are cleared, meaning the geometry of all data 316 * and unified caches (which are guaranteed to be PIPT and thus 317 * non-aliasing) are 1 set and 1 way. 318 * Guests should not be doing cache operations by set/way at all, and 319 * for this reason, we trap them and attempt to infer the intent, so 320 * that we can flush the entire guest's address space at the appropriate 321 * time. The exposed geometry minimizes the number of the traps. 322 * [If guests should attempt to infer aliasing properties from the 323 * geometry (which is not permitted by the architecture), they would 324 * only do so for virtually indexed caches.] 325 * 326 * We don't check if the cache level exists as it is allowed to return 327 * an UNKNOWN value if not. 328 */ 329 return SYS_FIELD_PREP(CCSIDR_EL1, LineSize, line_size - 4); 330 } 331 332 static int set_ccsidr(struct kvm_vcpu *vcpu, u32 csselr, u32 val) 333 { 334 u8 line_size = FIELD_GET(CCSIDR_EL1_LineSize, val) + 4; 335 u32 *ccsidr = vcpu->arch.ccsidr; 336 u32 i; 337 338 if ((val & CCSIDR_EL1_RES0) || 339 line_size < get_min_cache_line_size(csselr & CSSELR_EL1_InD)) 340 return -EINVAL; 341 342 if (!ccsidr) { 343 if (val == get_ccsidr(vcpu, csselr)) 344 return 0; 345 346 ccsidr = kmalloc_array(CSSELR_MAX, sizeof(u32), GFP_KERNEL_ACCOUNT); 347 if (!ccsidr) 348 return -ENOMEM; 349 350 for (i = 0; i < CSSELR_MAX; i++) 351 ccsidr[i] = get_ccsidr(vcpu, i); 352 353 vcpu->arch.ccsidr = ccsidr; 354 } 355 356 ccsidr[csselr] = val; 357 358 return 0; 359 } 360 361 static bool access_rw(struct kvm_vcpu *vcpu, 362 struct sys_reg_params *p, 363 const struct sys_reg_desc *r) 364 { 365 if (p->is_write) 366 vcpu_write_sys_reg(vcpu, p->regval, r->reg); 367 else 368 p->regval = vcpu_read_sys_reg(vcpu, r->reg); 369 370 return true; 371 } 372 373 /* 374 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized). 375 */ 376 static bool access_dcsw(struct kvm_vcpu *vcpu, 377 struct sys_reg_params *p, 378 const struct sys_reg_desc *r) 379 { 380 if (!p->is_write) 381 return read_from_write_only(vcpu, p, r); 382 383 /* 384 * Only track S/W ops if we don't have FWB. It still indicates 385 * that the guest is a bit broken (S/W operations should only 386 * be done by firmware, knowing that there is only a single 387 * CPU left in the system, and certainly not from non-secure 388 * software). 389 */ 390 if (!cpus_have_final_cap(ARM64_HAS_STAGE2_FWB)) 391 kvm_set_way_flush(vcpu); 392 393 return true; 394 } 395 396 static bool access_dcgsw(struct kvm_vcpu *vcpu, 397 struct sys_reg_params *p, 398 const struct sys_reg_desc *r) 399 { 400 if (!kvm_has_mte(vcpu->kvm)) 401 return undef_access(vcpu, p, r); 402 403 /* Treat MTE S/W ops as we treat the classic ones: with contempt */ 404 return access_dcsw(vcpu, p, r); 405 } 406 407 static void get_access_mask(const struct sys_reg_desc *r, u64 *mask, u64 *shift) 408 { 409 switch (r->aarch32_map) { 410 case AA32_LO: 411 *mask = GENMASK_ULL(31, 0); 412 *shift = 0; 413 break; 414 case AA32_HI: 415 *mask = GENMASK_ULL(63, 32); 416 *shift = 32; 417 break; 418 default: 419 *mask = GENMASK_ULL(63, 0); 420 *shift = 0; 421 break; 422 } 423 } 424 425 /* 426 * Generic accessor for VM registers. Only called as long as HCR_TVM 427 * is set. If the guest enables the MMU, we stop trapping the VM 428 * sys_regs and leave it in complete control of the caches. 429 */ 430 static bool access_vm_reg(struct kvm_vcpu *vcpu, 431 struct sys_reg_params *p, 432 const struct sys_reg_desc *r) 433 { 434 bool was_enabled = vcpu_has_cache_enabled(vcpu); 435 u64 val, mask, shift; 436 437 BUG_ON(!p->is_write); 438 439 get_access_mask(r, &mask, &shift); 440 441 if (~mask) { 442 val = vcpu_read_sys_reg(vcpu, r->reg); 443 val &= ~mask; 444 } else { 445 val = 0; 446 } 447 448 val |= (p->regval & (mask >> shift)) << shift; 449 vcpu_write_sys_reg(vcpu, val, r->reg); 450 451 kvm_toggle_cache(vcpu, was_enabled); 452 return true; 453 } 454 455 static bool access_actlr(struct kvm_vcpu *vcpu, 456 struct sys_reg_params *p, 457 const struct sys_reg_desc *r) 458 { 459 u64 mask, shift; 460 461 if (p->is_write) 462 return ignore_write(vcpu, p); 463 464 get_access_mask(r, &mask, &shift); 465 p->regval = (vcpu_read_sys_reg(vcpu, r->reg) & mask) >> shift; 466 467 return true; 468 } 469 470 /* 471 * Trap handler for the GICv3 SGI generation system register. 472 * Forward the request to the VGIC emulation. 473 * The cp15_64 code makes sure this automatically works 474 * for both AArch64 and AArch32 accesses. 475 */ 476 static bool access_gic_sgi(struct kvm_vcpu *vcpu, 477 struct sys_reg_params *p, 478 const struct sys_reg_desc *r) 479 { 480 bool g1; 481 482 if (!kvm_has_gicv3(vcpu->kvm)) 483 return undef_access(vcpu, p, r); 484 485 if (!p->is_write) 486 return read_from_write_only(vcpu, p, r); 487 488 /* 489 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates 490 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group, 491 * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively 492 * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure 493 * group. 494 */ 495 if (p->Op0 == 0) { /* AArch32 */ 496 switch (p->Op1) { 497 default: /* Keep GCC quiet */ 498 case 0: /* ICC_SGI1R */ 499 g1 = true; 500 break; 501 case 1: /* ICC_ASGI1R */ 502 case 2: /* ICC_SGI0R */ 503 g1 = false; 504 break; 505 } 506 } else { /* AArch64 */ 507 switch (p->Op2) { 508 default: /* Keep GCC quiet */ 509 case 5: /* ICC_SGI1R_EL1 */ 510 g1 = true; 511 break; 512 case 6: /* ICC_ASGI1R_EL1 */ 513 case 7: /* ICC_SGI0R_EL1 */ 514 g1 = false; 515 break; 516 } 517 } 518 519 vgic_v3_dispatch_sgi(vcpu, p->regval, g1); 520 521 return true; 522 } 523 524 static bool access_gic_sre(struct kvm_vcpu *vcpu, 525 struct sys_reg_params *p, 526 const struct sys_reg_desc *r) 527 { 528 if (!kvm_has_gicv3(vcpu->kvm)) 529 return undef_access(vcpu, p, r); 530 531 if (p->is_write) 532 return ignore_write(vcpu, p); 533 534 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre; 535 return true; 536 } 537 538 static bool trap_raz_wi(struct kvm_vcpu *vcpu, 539 struct sys_reg_params *p, 540 const struct sys_reg_desc *r) 541 { 542 if (p->is_write) 543 return ignore_write(vcpu, p); 544 else 545 return read_zero(vcpu, p); 546 } 547 548 /* 549 * ARMv8.1 mandates at least a trivial LORegion implementation, where all the 550 * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0 551 * system, these registers should UNDEF. LORID_EL1 being a RO register, we 552 * treat it separately. 553 */ 554 static bool trap_loregion(struct kvm_vcpu *vcpu, 555 struct sys_reg_params *p, 556 const struct sys_reg_desc *r) 557 { 558 u32 sr = reg_to_encoding(r); 559 560 if (!kvm_has_feat(vcpu->kvm, ID_AA64MMFR1_EL1, LO, IMP)) 561 return undef_access(vcpu, p, r); 562 563 if (p->is_write && sr == SYS_LORID_EL1) 564 return write_to_read_only(vcpu, p, r); 565 566 return trap_raz_wi(vcpu, p, r); 567 } 568 569 static bool trap_oslar_el1(struct kvm_vcpu *vcpu, 570 struct sys_reg_params *p, 571 const struct sys_reg_desc *r) 572 { 573 u64 oslsr; 574 575 if (!p->is_write) 576 return read_from_write_only(vcpu, p, r); 577 578 /* Forward the OSLK bit to OSLSR */ 579 oslsr = __vcpu_sys_reg(vcpu, OSLSR_EL1) & ~OSLSR_EL1_OSLK; 580 if (p->regval & OSLAR_EL1_OSLK) 581 oslsr |= OSLSR_EL1_OSLK; 582 583 __vcpu_sys_reg(vcpu, OSLSR_EL1) = oslsr; 584 return true; 585 } 586 587 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu, 588 struct sys_reg_params *p, 589 const struct sys_reg_desc *r) 590 { 591 if (p->is_write) 592 return write_to_read_only(vcpu, p, r); 593 594 p->regval = __vcpu_sys_reg(vcpu, r->reg); 595 return true; 596 } 597 598 static int set_oslsr_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 599 u64 val) 600 { 601 /* 602 * The only modifiable bit is the OSLK bit. Refuse the write if 603 * userspace attempts to change any other bit in the register. 604 */ 605 if ((val ^ rd->val) & ~OSLSR_EL1_OSLK) 606 return -EINVAL; 607 608 __vcpu_sys_reg(vcpu, rd->reg) = val; 609 return 0; 610 } 611 612 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu, 613 struct sys_reg_params *p, 614 const struct sys_reg_desc *r) 615 { 616 if (p->is_write) { 617 return ignore_write(vcpu, p); 618 } else { 619 p->regval = read_sysreg(dbgauthstatus_el1); 620 return true; 621 } 622 } 623 624 /* 625 * We want to avoid world-switching all the DBG registers all the 626 * time: 627 * 628 * - If we've touched any debug register, it is likely that we're 629 * going to touch more of them. It then makes sense to disable the 630 * traps and start doing the save/restore dance 631 * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is 632 * then mandatory to save/restore the registers, as the guest 633 * depends on them. 634 * 635 * For this, we use a DIRTY bit, indicating the guest has modified the 636 * debug registers, used as follow: 637 * 638 * On guest entry: 639 * - If the dirty bit is set (because we're coming back from trapping), 640 * disable the traps, save host registers, restore guest registers. 641 * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), 642 * set the dirty bit, disable the traps, save host registers, 643 * restore guest registers. 644 * - Otherwise, enable the traps 645 * 646 * On guest exit: 647 * - If the dirty bit is set, save guest registers, restore host 648 * registers and clear the dirty bit. This ensure that the host can 649 * now use the debug registers. 650 */ 651 static bool trap_debug_regs(struct kvm_vcpu *vcpu, 652 struct sys_reg_params *p, 653 const struct sys_reg_desc *r) 654 { 655 access_rw(vcpu, p, r); 656 if (p->is_write) 657 vcpu_set_flag(vcpu, DEBUG_DIRTY); 658 659 trace_trap_reg(__func__, r->reg, p->is_write, p->regval); 660 661 return true; 662 } 663 664 /* 665 * reg_to_dbg/dbg_to_reg 666 * 667 * A 32 bit write to a debug register leave top bits alone 668 * A 32 bit read from a debug register only returns the bottom bits 669 * 670 * All writes will set the DEBUG_DIRTY flag to ensure the hyp code 671 * switches between host and guest values in future. 672 */ 673 static void reg_to_dbg(struct kvm_vcpu *vcpu, 674 struct sys_reg_params *p, 675 const struct sys_reg_desc *rd, 676 u64 *dbg_reg) 677 { 678 u64 mask, shift, val; 679 680 get_access_mask(rd, &mask, &shift); 681 682 val = *dbg_reg; 683 val &= ~mask; 684 val |= (p->regval & (mask >> shift)) << shift; 685 *dbg_reg = val; 686 687 vcpu_set_flag(vcpu, DEBUG_DIRTY); 688 } 689 690 static void dbg_to_reg(struct kvm_vcpu *vcpu, 691 struct sys_reg_params *p, 692 const struct sys_reg_desc *rd, 693 u64 *dbg_reg) 694 { 695 u64 mask, shift; 696 697 get_access_mask(rd, &mask, &shift); 698 p->regval = (*dbg_reg & mask) >> shift; 699 } 700 701 static bool trap_bvr(struct kvm_vcpu *vcpu, 702 struct sys_reg_params *p, 703 const struct sys_reg_desc *rd) 704 { 705 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm]; 706 707 if (p->is_write) 708 reg_to_dbg(vcpu, p, rd, dbg_reg); 709 else 710 dbg_to_reg(vcpu, p, rd, dbg_reg); 711 712 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); 713 714 return true; 715 } 716 717 static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 718 u64 val) 719 { 720 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = val; 721 return 0; 722 } 723 724 static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 725 u64 *val) 726 { 727 *val = vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm]; 728 return 0; 729 } 730 731 static u64 reset_bvr(struct kvm_vcpu *vcpu, 732 const struct sys_reg_desc *rd) 733 { 734 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = rd->val; 735 return rd->val; 736 } 737 738 static bool trap_bcr(struct kvm_vcpu *vcpu, 739 struct sys_reg_params *p, 740 const struct sys_reg_desc *rd) 741 { 742 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm]; 743 744 if (p->is_write) 745 reg_to_dbg(vcpu, p, rd, dbg_reg); 746 else 747 dbg_to_reg(vcpu, p, rd, dbg_reg); 748 749 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); 750 751 return true; 752 } 753 754 static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 755 u64 val) 756 { 757 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = val; 758 return 0; 759 } 760 761 static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 762 u64 *val) 763 { 764 *val = vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm]; 765 return 0; 766 } 767 768 static u64 reset_bcr(struct kvm_vcpu *vcpu, 769 const struct sys_reg_desc *rd) 770 { 771 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = rd->val; 772 return rd->val; 773 } 774 775 static bool trap_wvr(struct kvm_vcpu *vcpu, 776 struct sys_reg_params *p, 777 const struct sys_reg_desc *rd) 778 { 779 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]; 780 781 if (p->is_write) 782 reg_to_dbg(vcpu, p, rd, dbg_reg); 783 else 784 dbg_to_reg(vcpu, p, rd, dbg_reg); 785 786 trace_trap_reg(__func__, rd->CRm, p->is_write, 787 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]); 788 789 return true; 790 } 791 792 static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 793 u64 val) 794 { 795 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = val; 796 return 0; 797 } 798 799 static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 800 u64 *val) 801 { 802 *val = vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]; 803 return 0; 804 } 805 806 static u64 reset_wvr(struct kvm_vcpu *vcpu, 807 const struct sys_reg_desc *rd) 808 { 809 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = rd->val; 810 return rd->val; 811 } 812 813 static bool trap_wcr(struct kvm_vcpu *vcpu, 814 struct sys_reg_params *p, 815 const struct sys_reg_desc *rd) 816 { 817 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm]; 818 819 if (p->is_write) 820 reg_to_dbg(vcpu, p, rd, dbg_reg); 821 else 822 dbg_to_reg(vcpu, p, rd, dbg_reg); 823 824 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); 825 826 return true; 827 } 828 829 static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 830 u64 val) 831 { 832 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = val; 833 return 0; 834 } 835 836 static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 837 u64 *val) 838 { 839 *val = vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm]; 840 return 0; 841 } 842 843 static u64 reset_wcr(struct kvm_vcpu *vcpu, 844 const struct sys_reg_desc *rd) 845 { 846 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = rd->val; 847 return rd->val; 848 } 849 850 static u64 reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 851 { 852 u64 amair = read_sysreg(amair_el1); 853 vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1); 854 return amair; 855 } 856 857 static u64 reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 858 { 859 u64 actlr = read_sysreg(actlr_el1); 860 vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1); 861 return actlr; 862 } 863 864 static u64 reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 865 { 866 u64 mpidr; 867 868 /* 869 * Map the vcpu_id into the first three affinity level fields of 870 * the MPIDR. We limit the number of VCPUs in level 0 due to a 871 * limitation to 16 CPUs in that level in the ICC_SGIxR registers 872 * of the GICv3 to be able to address each CPU directly when 873 * sending IPIs. 874 */ 875 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0); 876 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1); 877 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2); 878 mpidr |= (1ULL << 31); 879 vcpu_write_sys_reg(vcpu, mpidr, MPIDR_EL1); 880 881 return mpidr; 882 } 883 884 static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu, 885 const struct sys_reg_desc *r) 886 { 887 if (kvm_vcpu_has_pmu(vcpu)) 888 return 0; 889 890 return REG_HIDDEN; 891 } 892 893 static u64 reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 894 { 895 u64 mask = BIT(ARMV8_PMU_CYCLE_IDX); 896 u8 n = vcpu->kvm->arch.pmcr_n; 897 898 if (n) 899 mask |= GENMASK(n - 1, 0); 900 901 reset_unknown(vcpu, r); 902 __vcpu_sys_reg(vcpu, r->reg) &= mask; 903 904 return __vcpu_sys_reg(vcpu, r->reg); 905 } 906 907 static u64 reset_pmevcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 908 { 909 reset_unknown(vcpu, r); 910 __vcpu_sys_reg(vcpu, r->reg) &= GENMASK(31, 0); 911 912 return __vcpu_sys_reg(vcpu, r->reg); 913 } 914 915 static u64 reset_pmevtyper(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 916 { 917 /* This thing will UNDEF, who cares about the reset value? */ 918 if (!kvm_vcpu_has_pmu(vcpu)) 919 return 0; 920 921 reset_unknown(vcpu, r); 922 __vcpu_sys_reg(vcpu, r->reg) &= kvm_pmu_evtyper_mask(vcpu->kvm); 923 924 return __vcpu_sys_reg(vcpu, r->reg); 925 } 926 927 static u64 reset_pmselr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 928 { 929 reset_unknown(vcpu, r); 930 __vcpu_sys_reg(vcpu, r->reg) &= PMSELR_EL0_SEL_MASK; 931 932 return __vcpu_sys_reg(vcpu, r->reg); 933 } 934 935 static u64 reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 936 { 937 u64 pmcr = 0; 938 939 if (!kvm_supports_32bit_el0()) 940 pmcr |= ARMV8_PMU_PMCR_LC; 941 942 /* 943 * The value of PMCR.N field is included when the 944 * vCPU register is read via kvm_vcpu_read_pmcr(). 945 */ 946 __vcpu_sys_reg(vcpu, r->reg) = pmcr; 947 948 return __vcpu_sys_reg(vcpu, r->reg); 949 } 950 951 static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags) 952 { 953 u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0); 954 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu); 955 956 if (!enabled) 957 kvm_inject_undefined(vcpu); 958 959 return !enabled; 960 } 961 962 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu) 963 { 964 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN); 965 } 966 967 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu) 968 { 969 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN); 970 } 971 972 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu) 973 { 974 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN); 975 } 976 977 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu) 978 { 979 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN); 980 } 981 982 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 983 const struct sys_reg_desc *r) 984 { 985 u64 val; 986 987 if (pmu_access_el0_disabled(vcpu)) 988 return false; 989 990 if (p->is_write) { 991 /* 992 * Only update writeable bits of PMCR (continuing into 993 * kvm_pmu_handle_pmcr() as well) 994 */ 995 val = kvm_vcpu_read_pmcr(vcpu); 996 val &= ~ARMV8_PMU_PMCR_MASK; 997 val |= p->regval & ARMV8_PMU_PMCR_MASK; 998 if (!kvm_supports_32bit_el0()) 999 val |= ARMV8_PMU_PMCR_LC; 1000 kvm_pmu_handle_pmcr(vcpu, val); 1001 } else { 1002 /* PMCR.P & PMCR.C are RAZ */ 1003 val = kvm_vcpu_read_pmcr(vcpu) 1004 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C); 1005 p->regval = val; 1006 } 1007 1008 return true; 1009 } 1010 1011 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1012 const struct sys_reg_desc *r) 1013 { 1014 if (pmu_access_event_counter_el0_disabled(vcpu)) 1015 return false; 1016 1017 if (p->is_write) 1018 __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval; 1019 else 1020 /* return PMSELR.SEL field */ 1021 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0) 1022 & PMSELR_EL0_SEL_MASK; 1023 1024 return true; 1025 } 1026 1027 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1028 const struct sys_reg_desc *r) 1029 { 1030 u64 pmceid, mask, shift; 1031 1032 BUG_ON(p->is_write); 1033 1034 if (pmu_access_el0_disabled(vcpu)) 1035 return false; 1036 1037 get_access_mask(r, &mask, &shift); 1038 1039 pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1)); 1040 pmceid &= mask; 1041 pmceid >>= shift; 1042 1043 p->regval = pmceid; 1044 1045 return true; 1046 } 1047 1048 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx) 1049 { 1050 u64 pmcr, val; 1051 1052 pmcr = kvm_vcpu_read_pmcr(vcpu); 1053 val = FIELD_GET(ARMV8_PMU_PMCR_N, pmcr); 1054 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) { 1055 kvm_inject_undefined(vcpu); 1056 return false; 1057 } 1058 1059 return true; 1060 } 1061 1062 static int get_pmu_evcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 1063 u64 *val) 1064 { 1065 u64 idx; 1066 1067 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 0) 1068 /* PMCCNTR_EL0 */ 1069 idx = ARMV8_PMU_CYCLE_IDX; 1070 else 1071 /* PMEVCNTRn_EL0 */ 1072 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 1073 1074 *val = kvm_pmu_get_counter_value(vcpu, idx); 1075 return 0; 1076 } 1077 1078 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu, 1079 struct sys_reg_params *p, 1080 const struct sys_reg_desc *r) 1081 { 1082 u64 idx = ~0UL; 1083 1084 if (r->CRn == 9 && r->CRm == 13) { 1085 if (r->Op2 == 2) { 1086 /* PMXEVCNTR_EL0 */ 1087 if (pmu_access_event_counter_el0_disabled(vcpu)) 1088 return false; 1089 1090 idx = SYS_FIELD_GET(PMSELR_EL0, SEL, 1091 __vcpu_sys_reg(vcpu, PMSELR_EL0)); 1092 } else if (r->Op2 == 0) { 1093 /* PMCCNTR_EL0 */ 1094 if (pmu_access_cycle_counter_el0_disabled(vcpu)) 1095 return false; 1096 1097 idx = ARMV8_PMU_CYCLE_IDX; 1098 } 1099 } else if (r->CRn == 0 && r->CRm == 9) { 1100 /* PMCCNTR */ 1101 if (pmu_access_event_counter_el0_disabled(vcpu)) 1102 return false; 1103 1104 idx = ARMV8_PMU_CYCLE_IDX; 1105 } else if (r->CRn == 14 && (r->CRm & 12) == 8) { 1106 /* PMEVCNTRn_EL0 */ 1107 if (pmu_access_event_counter_el0_disabled(vcpu)) 1108 return false; 1109 1110 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 1111 } 1112 1113 /* Catch any decoding mistake */ 1114 WARN_ON(idx == ~0UL); 1115 1116 if (!pmu_counter_idx_valid(vcpu, idx)) 1117 return false; 1118 1119 if (p->is_write) { 1120 if (pmu_access_el0_disabled(vcpu)) 1121 return false; 1122 1123 kvm_pmu_set_counter_value(vcpu, idx, p->regval); 1124 } else { 1125 p->regval = kvm_pmu_get_counter_value(vcpu, idx); 1126 } 1127 1128 return true; 1129 } 1130 1131 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1132 const struct sys_reg_desc *r) 1133 { 1134 u64 idx, reg; 1135 1136 if (pmu_access_el0_disabled(vcpu)) 1137 return false; 1138 1139 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) { 1140 /* PMXEVTYPER_EL0 */ 1141 idx = SYS_FIELD_GET(PMSELR_EL0, SEL, __vcpu_sys_reg(vcpu, PMSELR_EL0)); 1142 reg = PMEVTYPER0_EL0 + idx; 1143 } else if (r->CRn == 14 && (r->CRm & 12) == 12) { 1144 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 1145 if (idx == ARMV8_PMU_CYCLE_IDX) 1146 reg = PMCCFILTR_EL0; 1147 else 1148 /* PMEVTYPERn_EL0 */ 1149 reg = PMEVTYPER0_EL0 + idx; 1150 } else { 1151 BUG(); 1152 } 1153 1154 if (!pmu_counter_idx_valid(vcpu, idx)) 1155 return false; 1156 1157 if (p->is_write) { 1158 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx); 1159 kvm_vcpu_pmu_restore_guest(vcpu); 1160 } else { 1161 p->regval = __vcpu_sys_reg(vcpu, reg); 1162 } 1163 1164 return true; 1165 } 1166 1167 static int set_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 val) 1168 { 1169 bool set; 1170 1171 val &= kvm_pmu_accessible_counter_mask(vcpu); 1172 1173 switch (r->reg) { 1174 case PMOVSSET_EL0: 1175 /* CRm[1] being set indicates a SET register, and CLR otherwise */ 1176 set = r->CRm & 2; 1177 break; 1178 default: 1179 /* Op2[0] being set indicates a SET register, and CLR otherwise */ 1180 set = r->Op2 & 1; 1181 break; 1182 } 1183 1184 if (set) 1185 __vcpu_sys_reg(vcpu, r->reg) |= val; 1186 else 1187 __vcpu_sys_reg(vcpu, r->reg) &= ~val; 1188 1189 return 0; 1190 } 1191 1192 static int get_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 *val) 1193 { 1194 u64 mask = kvm_pmu_accessible_counter_mask(vcpu); 1195 1196 *val = __vcpu_sys_reg(vcpu, r->reg) & mask; 1197 return 0; 1198 } 1199 1200 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1201 const struct sys_reg_desc *r) 1202 { 1203 u64 val, mask; 1204 1205 if (pmu_access_el0_disabled(vcpu)) 1206 return false; 1207 1208 mask = kvm_pmu_accessible_counter_mask(vcpu); 1209 if (p->is_write) { 1210 val = p->regval & mask; 1211 if (r->Op2 & 0x1) { 1212 /* accessing PMCNTENSET_EL0 */ 1213 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val; 1214 kvm_pmu_enable_counter_mask(vcpu, val); 1215 kvm_vcpu_pmu_restore_guest(vcpu); 1216 } else { 1217 /* accessing PMCNTENCLR_EL0 */ 1218 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val; 1219 kvm_pmu_disable_counter_mask(vcpu, val); 1220 } 1221 } else { 1222 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0); 1223 } 1224 1225 return true; 1226 } 1227 1228 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1229 const struct sys_reg_desc *r) 1230 { 1231 u64 mask = kvm_pmu_accessible_counter_mask(vcpu); 1232 1233 if (check_pmu_access_disabled(vcpu, 0)) 1234 return false; 1235 1236 if (p->is_write) { 1237 u64 val = p->regval & mask; 1238 1239 if (r->Op2 & 0x1) 1240 /* accessing PMINTENSET_EL1 */ 1241 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val; 1242 else 1243 /* accessing PMINTENCLR_EL1 */ 1244 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val; 1245 } else { 1246 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1); 1247 } 1248 1249 return true; 1250 } 1251 1252 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1253 const struct sys_reg_desc *r) 1254 { 1255 u64 mask = kvm_pmu_accessible_counter_mask(vcpu); 1256 1257 if (pmu_access_el0_disabled(vcpu)) 1258 return false; 1259 1260 if (p->is_write) { 1261 if (r->CRm & 0x2) 1262 /* accessing PMOVSSET_EL0 */ 1263 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask); 1264 else 1265 /* accessing PMOVSCLR_EL0 */ 1266 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask); 1267 } else { 1268 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0); 1269 } 1270 1271 return true; 1272 } 1273 1274 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1275 const struct sys_reg_desc *r) 1276 { 1277 u64 mask; 1278 1279 if (!p->is_write) 1280 return read_from_write_only(vcpu, p, r); 1281 1282 if (pmu_write_swinc_el0_disabled(vcpu)) 1283 return false; 1284 1285 mask = kvm_pmu_accessible_counter_mask(vcpu); 1286 kvm_pmu_software_increment(vcpu, p->regval & mask); 1287 return true; 1288 } 1289 1290 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1291 const struct sys_reg_desc *r) 1292 { 1293 if (p->is_write) { 1294 if (!vcpu_mode_priv(vcpu)) 1295 return undef_access(vcpu, p, r); 1296 1297 __vcpu_sys_reg(vcpu, PMUSERENR_EL0) = 1298 p->regval & ARMV8_PMU_USERENR_MASK; 1299 } else { 1300 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0) 1301 & ARMV8_PMU_USERENR_MASK; 1302 } 1303 1304 return true; 1305 } 1306 1307 static int get_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 1308 u64 *val) 1309 { 1310 *val = kvm_vcpu_read_pmcr(vcpu); 1311 return 0; 1312 } 1313 1314 static int set_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 1315 u64 val) 1316 { 1317 u8 new_n = FIELD_GET(ARMV8_PMU_PMCR_N, val); 1318 struct kvm *kvm = vcpu->kvm; 1319 1320 mutex_lock(&kvm->arch.config_lock); 1321 1322 /* 1323 * The vCPU can't have more counters than the PMU hardware 1324 * implements. Ignore this error to maintain compatibility 1325 * with the existing KVM behavior. 1326 */ 1327 if (!kvm_vm_has_ran_once(kvm) && 1328 new_n <= kvm_arm_pmu_get_max_counters(kvm)) 1329 kvm->arch.pmcr_n = new_n; 1330 1331 mutex_unlock(&kvm->arch.config_lock); 1332 1333 /* 1334 * Ignore writes to RES0 bits, read only bits that are cleared on 1335 * vCPU reset, and writable bits that KVM doesn't support yet. 1336 * (i.e. only PMCR.N and bits [7:0] are mutable from userspace) 1337 * The LP bit is RES0 when FEAT_PMUv3p5 is not supported on the vCPU. 1338 * But, we leave the bit as it is here, as the vCPU's PMUver might 1339 * be changed later (NOTE: the bit will be cleared on first vCPU run 1340 * if necessary). 1341 */ 1342 val &= ARMV8_PMU_PMCR_MASK; 1343 1344 /* The LC bit is RES1 when AArch32 is not supported */ 1345 if (!kvm_supports_32bit_el0()) 1346 val |= ARMV8_PMU_PMCR_LC; 1347 1348 __vcpu_sys_reg(vcpu, r->reg) = val; 1349 return 0; 1350 } 1351 1352 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */ 1353 #define DBG_BCR_BVR_WCR_WVR_EL1(n) \ 1354 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \ 1355 trap_bvr, reset_bvr, 0, 0, get_bvr, set_bvr }, \ 1356 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \ 1357 trap_bcr, reset_bcr, 0, 0, get_bcr, set_bcr }, \ 1358 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \ 1359 trap_wvr, reset_wvr, 0, 0, get_wvr, set_wvr }, \ 1360 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \ 1361 trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr } 1362 1363 #define PMU_SYS_REG(name) \ 1364 SYS_DESC(SYS_##name), .reset = reset_pmu_reg, \ 1365 .visibility = pmu_visibility 1366 1367 /* Macro to expand the PMEVCNTRn_EL0 register */ 1368 #define PMU_PMEVCNTR_EL0(n) \ 1369 { PMU_SYS_REG(PMEVCNTRn_EL0(n)), \ 1370 .reset = reset_pmevcntr, .get_user = get_pmu_evcntr, \ 1371 .access = access_pmu_evcntr, .reg = (PMEVCNTR0_EL0 + n), } 1372 1373 /* Macro to expand the PMEVTYPERn_EL0 register */ 1374 #define PMU_PMEVTYPER_EL0(n) \ 1375 { PMU_SYS_REG(PMEVTYPERn_EL0(n)), \ 1376 .reset = reset_pmevtyper, \ 1377 .access = access_pmu_evtyper, .reg = (PMEVTYPER0_EL0 + n), } 1378 1379 /* Macro to expand the AMU counter and type registers*/ 1380 #define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), undef_access } 1381 #define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), undef_access } 1382 #define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), undef_access } 1383 #define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), undef_access } 1384 1385 static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu, 1386 const struct sys_reg_desc *rd) 1387 { 1388 return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN; 1389 } 1390 1391 /* 1392 * If we land here on a PtrAuth access, that is because we didn't 1393 * fixup the access on exit by allowing the PtrAuth sysregs. The only 1394 * way this happens is when the guest does not have PtrAuth support 1395 * enabled. 1396 */ 1397 #define __PTRAUTH_KEY(k) \ 1398 { SYS_DESC(SYS_## k), undef_access, reset_unknown, k, \ 1399 .visibility = ptrauth_visibility} 1400 1401 #define PTRAUTH_KEY(k) \ 1402 __PTRAUTH_KEY(k ## KEYLO_EL1), \ 1403 __PTRAUTH_KEY(k ## KEYHI_EL1) 1404 1405 static bool access_arch_timer(struct kvm_vcpu *vcpu, 1406 struct sys_reg_params *p, 1407 const struct sys_reg_desc *r) 1408 { 1409 enum kvm_arch_timers tmr; 1410 enum kvm_arch_timer_regs treg; 1411 u64 reg = reg_to_encoding(r); 1412 1413 switch (reg) { 1414 case SYS_CNTP_TVAL_EL0: 1415 case SYS_AARCH32_CNTP_TVAL: 1416 tmr = TIMER_PTIMER; 1417 treg = TIMER_REG_TVAL; 1418 break; 1419 case SYS_CNTP_CTL_EL0: 1420 case SYS_AARCH32_CNTP_CTL: 1421 tmr = TIMER_PTIMER; 1422 treg = TIMER_REG_CTL; 1423 break; 1424 case SYS_CNTP_CVAL_EL0: 1425 case SYS_AARCH32_CNTP_CVAL: 1426 tmr = TIMER_PTIMER; 1427 treg = TIMER_REG_CVAL; 1428 break; 1429 case SYS_CNTPCT_EL0: 1430 case SYS_CNTPCTSS_EL0: 1431 case SYS_AARCH32_CNTPCT: 1432 tmr = TIMER_PTIMER; 1433 treg = TIMER_REG_CNT; 1434 break; 1435 default: 1436 print_sys_reg_msg(p, "%s", "Unhandled trapped timer register"); 1437 return undef_access(vcpu, p, r); 1438 } 1439 1440 if (p->is_write) 1441 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval); 1442 else 1443 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg); 1444 1445 return true; 1446 } 1447 1448 static s64 kvm_arm64_ftr_safe_value(u32 id, const struct arm64_ftr_bits *ftrp, 1449 s64 new, s64 cur) 1450 { 1451 struct arm64_ftr_bits kvm_ftr = *ftrp; 1452 1453 /* Some features have different safe value type in KVM than host features */ 1454 switch (id) { 1455 case SYS_ID_AA64DFR0_EL1: 1456 switch (kvm_ftr.shift) { 1457 case ID_AA64DFR0_EL1_PMUVer_SHIFT: 1458 kvm_ftr.type = FTR_LOWER_SAFE; 1459 break; 1460 case ID_AA64DFR0_EL1_DebugVer_SHIFT: 1461 kvm_ftr.type = FTR_LOWER_SAFE; 1462 break; 1463 } 1464 break; 1465 case SYS_ID_DFR0_EL1: 1466 if (kvm_ftr.shift == ID_DFR0_EL1_PerfMon_SHIFT) 1467 kvm_ftr.type = FTR_LOWER_SAFE; 1468 break; 1469 } 1470 1471 return arm64_ftr_safe_value(&kvm_ftr, new, cur); 1472 } 1473 1474 /* 1475 * arm64_check_features() - Check if a feature register value constitutes 1476 * a subset of features indicated by the idreg's KVM sanitised limit. 1477 * 1478 * This function will check if each feature field of @val is the "safe" value 1479 * against idreg's KVM sanitised limit return from reset() callback. 1480 * If a field value in @val is the same as the one in limit, it is always 1481 * considered the safe value regardless For register fields that are not in 1482 * writable, only the value in limit is considered the safe value. 1483 * 1484 * Return: 0 if all the fields are safe. Otherwise, return negative errno. 1485 */ 1486 static int arm64_check_features(struct kvm_vcpu *vcpu, 1487 const struct sys_reg_desc *rd, 1488 u64 val) 1489 { 1490 const struct arm64_ftr_reg *ftr_reg; 1491 const struct arm64_ftr_bits *ftrp = NULL; 1492 u32 id = reg_to_encoding(rd); 1493 u64 writable_mask = rd->val; 1494 u64 limit = rd->reset(vcpu, rd); 1495 u64 mask = 0; 1496 1497 /* 1498 * Hidden and unallocated ID registers may not have a corresponding 1499 * struct arm64_ftr_reg. Of course, if the register is RAZ we know the 1500 * only safe value is 0. 1501 */ 1502 if (sysreg_visible_as_raz(vcpu, rd)) 1503 return val ? -E2BIG : 0; 1504 1505 ftr_reg = get_arm64_ftr_reg(id); 1506 if (!ftr_reg) 1507 return -EINVAL; 1508 1509 ftrp = ftr_reg->ftr_bits; 1510 1511 for (; ftrp && ftrp->width; ftrp++) { 1512 s64 f_val, f_lim, safe_val; 1513 u64 ftr_mask; 1514 1515 ftr_mask = arm64_ftr_mask(ftrp); 1516 if ((ftr_mask & writable_mask) != ftr_mask) 1517 continue; 1518 1519 f_val = arm64_ftr_value(ftrp, val); 1520 f_lim = arm64_ftr_value(ftrp, limit); 1521 mask |= ftr_mask; 1522 1523 if (f_val == f_lim) 1524 safe_val = f_val; 1525 else 1526 safe_val = kvm_arm64_ftr_safe_value(id, ftrp, f_val, f_lim); 1527 1528 if (safe_val != f_val) 1529 return -E2BIG; 1530 } 1531 1532 /* For fields that are not writable, values in limit are the safe values. */ 1533 if ((val & ~mask) != (limit & ~mask)) 1534 return -E2BIG; 1535 1536 return 0; 1537 } 1538 1539 static u8 pmuver_to_perfmon(u8 pmuver) 1540 { 1541 switch (pmuver) { 1542 case ID_AA64DFR0_EL1_PMUVer_IMP: 1543 return ID_DFR0_EL1_PerfMon_PMUv3; 1544 case ID_AA64DFR0_EL1_PMUVer_IMP_DEF: 1545 return ID_DFR0_EL1_PerfMon_IMPDEF; 1546 default: 1547 /* Anything ARMv8.1+ and NI have the same value. For now. */ 1548 return pmuver; 1549 } 1550 } 1551 1552 static u64 sanitise_id_aa64pfr0_el1(const struct kvm_vcpu *vcpu, u64 val); 1553 static u64 sanitise_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, u64 val); 1554 1555 /* Read a sanitised cpufeature ID register by sys_reg_desc */ 1556 static u64 __kvm_read_sanitised_id_reg(const struct kvm_vcpu *vcpu, 1557 const struct sys_reg_desc *r) 1558 { 1559 u32 id = reg_to_encoding(r); 1560 u64 val; 1561 1562 if (sysreg_visible_as_raz(vcpu, r)) 1563 return 0; 1564 1565 val = read_sanitised_ftr_reg(id); 1566 1567 switch (id) { 1568 case SYS_ID_AA64DFR0_EL1: 1569 val = sanitise_id_aa64dfr0_el1(vcpu, val); 1570 break; 1571 case SYS_ID_AA64PFR0_EL1: 1572 val = sanitise_id_aa64pfr0_el1(vcpu, val); 1573 break; 1574 case SYS_ID_AA64PFR1_EL1: 1575 if (!kvm_has_mte(vcpu->kvm)) 1576 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE); 1577 1578 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_SME); 1579 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_RNDR_trap); 1580 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_NMI); 1581 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE_frac); 1582 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_GCS); 1583 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_THE); 1584 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTEX); 1585 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_DF2); 1586 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_PFAR); 1587 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MPAM_frac); 1588 break; 1589 case SYS_ID_AA64PFR2_EL1: 1590 /* We only expose FPMR */ 1591 val &= ID_AA64PFR2_EL1_FPMR; 1592 break; 1593 case SYS_ID_AA64ISAR1_EL1: 1594 if (!vcpu_has_ptrauth(vcpu)) 1595 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) | 1596 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) | 1597 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) | 1598 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI)); 1599 break; 1600 case SYS_ID_AA64ISAR2_EL1: 1601 if (!vcpu_has_ptrauth(vcpu)) 1602 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) | 1603 ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3)); 1604 if (!cpus_have_final_cap(ARM64_HAS_WFXT)) 1605 val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT); 1606 break; 1607 case SYS_ID_AA64MMFR2_EL1: 1608 val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK; 1609 break; 1610 case SYS_ID_AA64MMFR3_EL1: 1611 val &= ID_AA64MMFR3_EL1_TCRX | ID_AA64MMFR3_EL1_S1POE | 1612 ID_AA64MMFR3_EL1_S1PIE; 1613 break; 1614 case SYS_ID_MMFR4_EL1: 1615 val &= ~ARM64_FEATURE_MASK(ID_MMFR4_EL1_CCIDX); 1616 break; 1617 } 1618 1619 return val; 1620 } 1621 1622 static u64 kvm_read_sanitised_id_reg(struct kvm_vcpu *vcpu, 1623 const struct sys_reg_desc *r) 1624 { 1625 return __kvm_read_sanitised_id_reg(vcpu, r); 1626 } 1627 1628 static u64 read_id_reg(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 1629 { 1630 return kvm_read_vm_id_reg(vcpu->kvm, reg_to_encoding(r)); 1631 } 1632 1633 static bool is_feature_id_reg(u32 encoding) 1634 { 1635 return (sys_reg_Op0(encoding) == 3 && 1636 (sys_reg_Op1(encoding) < 2 || sys_reg_Op1(encoding) == 3) && 1637 sys_reg_CRn(encoding) == 0 && 1638 sys_reg_CRm(encoding) <= 7); 1639 } 1640 1641 /* 1642 * Return true if the register's (Op0, Op1, CRn, CRm, Op2) is 1643 * (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8, which is the range of ID 1644 * registers KVM maintains on a per-VM basis. 1645 */ 1646 static inline bool is_vm_ftr_id_reg(u32 id) 1647 { 1648 if (id == SYS_CTR_EL0) 1649 return true; 1650 1651 return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 && 1652 sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 && 1653 sys_reg_CRm(id) < 8); 1654 } 1655 1656 static inline bool is_vcpu_ftr_id_reg(u32 id) 1657 { 1658 return is_feature_id_reg(id) && !is_vm_ftr_id_reg(id); 1659 } 1660 1661 static inline bool is_aa32_id_reg(u32 id) 1662 { 1663 return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 && 1664 sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 && 1665 sys_reg_CRm(id) <= 3); 1666 } 1667 1668 static unsigned int id_visibility(const struct kvm_vcpu *vcpu, 1669 const struct sys_reg_desc *r) 1670 { 1671 u32 id = reg_to_encoding(r); 1672 1673 switch (id) { 1674 case SYS_ID_AA64ZFR0_EL1: 1675 if (!vcpu_has_sve(vcpu)) 1676 return REG_RAZ; 1677 break; 1678 } 1679 1680 return 0; 1681 } 1682 1683 static unsigned int aa32_id_visibility(const struct kvm_vcpu *vcpu, 1684 const struct sys_reg_desc *r) 1685 { 1686 /* 1687 * AArch32 ID registers are UNKNOWN if AArch32 isn't implemented at any 1688 * EL. Promote to RAZ/WI in order to guarantee consistency between 1689 * systems. 1690 */ 1691 if (!kvm_supports_32bit_el0()) 1692 return REG_RAZ | REG_USER_WI; 1693 1694 return id_visibility(vcpu, r); 1695 } 1696 1697 static unsigned int raz_visibility(const struct kvm_vcpu *vcpu, 1698 const struct sys_reg_desc *r) 1699 { 1700 return REG_RAZ; 1701 } 1702 1703 /* cpufeature ID register access trap handlers */ 1704 1705 static bool access_id_reg(struct kvm_vcpu *vcpu, 1706 struct sys_reg_params *p, 1707 const struct sys_reg_desc *r) 1708 { 1709 if (p->is_write) 1710 return write_to_read_only(vcpu, p, r); 1711 1712 p->regval = read_id_reg(vcpu, r); 1713 1714 return true; 1715 } 1716 1717 /* Visibility overrides for SVE-specific control registers */ 1718 static unsigned int sve_visibility(const struct kvm_vcpu *vcpu, 1719 const struct sys_reg_desc *rd) 1720 { 1721 if (vcpu_has_sve(vcpu)) 1722 return 0; 1723 1724 return REG_HIDDEN; 1725 } 1726 1727 static unsigned int sme_visibility(const struct kvm_vcpu *vcpu, 1728 const struct sys_reg_desc *rd) 1729 { 1730 if (kvm_has_feat(vcpu->kvm, ID_AA64PFR1_EL1, SME, IMP)) 1731 return 0; 1732 1733 return REG_HIDDEN; 1734 } 1735 1736 static unsigned int fp8_visibility(const struct kvm_vcpu *vcpu, 1737 const struct sys_reg_desc *rd) 1738 { 1739 if (kvm_has_fpmr(vcpu->kvm)) 1740 return 0; 1741 1742 return REG_HIDDEN; 1743 } 1744 1745 static u64 sanitise_id_aa64pfr0_el1(const struct kvm_vcpu *vcpu, u64 val) 1746 { 1747 if (!vcpu_has_sve(vcpu)) 1748 val &= ~ID_AA64PFR0_EL1_SVE_MASK; 1749 1750 /* 1751 * The default is to expose CSV2 == 1 if the HW isn't affected. 1752 * Although this is a per-CPU feature, we make it global because 1753 * asymmetric systems are just a nuisance. 1754 * 1755 * Userspace can override this as long as it doesn't promise 1756 * the impossible. 1757 */ 1758 if (arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED) { 1759 val &= ~ID_AA64PFR0_EL1_CSV2_MASK; 1760 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV2, IMP); 1761 } 1762 if (arm64_get_meltdown_state() == SPECTRE_UNAFFECTED) { 1763 val &= ~ID_AA64PFR0_EL1_CSV3_MASK; 1764 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV3, IMP); 1765 } 1766 1767 if (kvm_vgic_global_state.type == VGIC_V3) { 1768 val &= ~ID_AA64PFR0_EL1_GIC_MASK; 1769 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, GIC, IMP); 1770 } 1771 1772 val &= ~ID_AA64PFR0_EL1_AMU_MASK; 1773 1774 /* 1775 * MPAM is disabled by default as KVM also needs a set of PARTID to 1776 * program the MPAMVPMx_EL2 PARTID remapping registers with. But some 1777 * older kernels let the guest see the ID bit. 1778 */ 1779 val &= ~ID_AA64PFR0_EL1_MPAM_MASK; 1780 1781 return val; 1782 } 1783 1784 #define ID_REG_LIMIT_FIELD_ENUM(val, reg, field, limit) \ 1785 ({ \ 1786 u64 __f_val = FIELD_GET(reg##_##field##_MASK, val); \ 1787 (val) &= ~reg##_##field##_MASK; \ 1788 (val) |= FIELD_PREP(reg##_##field##_MASK, \ 1789 min(__f_val, \ 1790 (u64)SYS_FIELD_VALUE(reg, field, limit))); \ 1791 (val); \ 1792 }) 1793 1794 static u64 sanitise_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, u64 val) 1795 { 1796 val = ID_REG_LIMIT_FIELD_ENUM(val, ID_AA64DFR0_EL1, DebugVer, V8P8); 1797 1798 /* 1799 * Only initialize the PMU version if the vCPU was configured with one. 1800 */ 1801 val &= ~ID_AA64DFR0_EL1_PMUVer_MASK; 1802 if (kvm_vcpu_has_pmu(vcpu)) 1803 val |= SYS_FIELD_PREP(ID_AA64DFR0_EL1, PMUVer, 1804 kvm_arm_pmu_get_pmuver_limit()); 1805 1806 /* Hide SPE from guests */ 1807 val &= ~ID_AA64DFR0_EL1_PMSVer_MASK; 1808 1809 return val; 1810 } 1811 1812 static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, 1813 const struct sys_reg_desc *rd, 1814 u64 val) 1815 { 1816 u8 debugver = SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, val); 1817 u8 pmuver = SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, val); 1818 1819 /* 1820 * Prior to commit 3d0dba5764b9 ("KVM: arm64: PMU: Move the 1821 * ID_AA64DFR0_EL1.PMUver limit to VM creation"), KVM erroneously 1822 * exposed an IMP_DEF PMU to userspace and the guest on systems w/ 1823 * non-architectural PMUs. Of course, PMUv3 is the only game in town for 1824 * PMU virtualization, so the IMP_DEF value was rather user-hostile. 1825 * 1826 * At minimum, we're on the hook to allow values that were given to 1827 * userspace by KVM. Cover our tracks here and replace the IMP_DEF value 1828 * with a more sensible NI. The value of an ID register changing under 1829 * the nose of the guest is unfortunate, but is certainly no more 1830 * surprising than an ill-guided PMU driver poking at impdef system 1831 * registers that end in an UNDEF... 1832 */ 1833 if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF) 1834 val &= ~ID_AA64DFR0_EL1_PMUVer_MASK; 1835 1836 /* 1837 * ID_AA64DFR0_EL1.DebugVer is one of those awkward fields with a 1838 * nonzero minimum safe value. 1839 */ 1840 if (debugver < ID_AA64DFR0_EL1_DebugVer_IMP) 1841 return -EINVAL; 1842 1843 return set_id_reg(vcpu, rd, val); 1844 } 1845 1846 static u64 read_sanitised_id_dfr0_el1(struct kvm_vcpu *vcpu, 1847 const struct sys_reg_desc *rd) 1848 { 1849 u8 perfmon = pmuver_to_perfmon(kvm_arm_pmu_get_pmuver_limit()); 1850 u64 val = read_sanitised_ftr_reg(SYS_ID_DFR0_EL1); 1851 1852 val &= ~ID_DFR0_EL1_PerfMon_MASK; 1853 if (kvm_vcpu_has_pmu(vcpu)) 1854 val |= SYS_FIELD_PREP(ID_DFR0_EL1, PerfMon, perfmon); 1855 1856 val = ID_REG_LIMIT_FIELD_ENUM(val, ID_DFR0_EL1, CopDbg, Debugv8p8); 1857 1858 return val; 1859 } 1860 1861 static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, 1862 const struct sys_reg_desc *rd, 1863 u64 val) 1864 { 1865 u8 perfmon = SYS_FIELD_GET(ID_DFR0_EL1, PerfMon, val); 1866 u8 copdbg = SYS_FIELD_GET(ID_DFR0_EL1, CopDbg, val); 1867 1868 if (perfmon == ID_DFR0_EL1_PerfMon_IMPDEF) { 1869 val &= ~ID_DFR0_EL1_PerfMon_MASK; 1870 perfmon = 0; 1871 } 1872 1873 /* 1874 * Allow DFR0_EL1.PerfMon to be set from userspace as long as 1875 * it doesn't promise more than what the HW gives us on the 1876 * AArch64 side (as everything is emulated with that), and 1877 * that this is a PMUv3. 1878 */ 1879 if (perfmon != 0 && perfmon < ID_DFR0_EL1_PerfMon_PMUv3) 1880 return -EINVAL; 1881 1882 if (copdbg < ID_DFR0_EL1_CopDbg_Armv8) 1883 return -EINVAL; 1884 1885 return set_id_reg(vcpu, rd, val); 1886 } 1887 1888 static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, 1889 const struct sys_reg_desc *rd, u64 user_val) 1890 { 1891 u64 hw_val = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1892 u64 mpam_mask = ID_AA64PFR0_EL1_MPAM_MASK; 1893 1894 /* 1895 * Commit 011e5f5bf529f ("arm64/cpufeature: Add remaining feature bits 1896 * in ID_AA64PFR0 register") exposed the MPAM field of AA64PFR0_EL1 to 1897 * guests, but didn't add trap handling. KVM doesn't support MPAM and 1898 * always returns an UNDEF for these registers. The guest must see 0 1899 * for this field. 1900 * 1901 * But KVM must also accept values from user-space that were provided 1902 * by KVM. On CPUs that support MPAM, permit user-space to write 1903 * the sanitizied value to ID_AA64PFR0_EL1.MPAM, but ignore this field. 1904 */ 1905 if ((hw_val & mpam_mask) == (user_val & mpam_mask)) 1906 user_val &= ~ID_AA64PFR0_EL1_MPAM_MASK; 1907 1908 return set_id_reg(vcpu, rd, user_val); 1909 } 1910 1911 static int set_id_aa64pfr1_el1(struct kvm_vcpu *vcpu, 1912 const struct sys_reg_desc *rd, u64 user_val) 1913 { 1914 u64 hw_val = read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1); 1915 u64 mpam_mask = ID_AA64PFR1_EL1_MPAM_frac_MASK; 1916 1917 /* See set_id_aa64pfr0_el1 for comment about MPAM */ 1918 if ((hw_val & mpam_mask) == (user_val & mpam_mask)) 1919 user_val &= ~ID_AA64PFR1_EL1_MPAM_frac_MASK; 1920 1921 return set_id_reg(vcpu, rd, user_val); 1922 } 1923 1924 static int set_ctr_el0(struct kvm_vcpu *vcpu, 1925 const struct sys_reg_desc *rd, u64 user_val) 1926 { 1927 u8 user_L1Ip = SYS_FIELD_GET(CTR_EL0, L1Ip, user_val); 1928 1929 /* 1930 * Both AIVIVT (0b01) and VPIPT (0b00) are documented as reserved. 1931 * Hence only allow to set VIPT(0b10) or PIPT(0b11) for L1Ip based 1932 * on what hardware reports. 1933 * 1934 * Using a VIPT software model on PIPT will lead to over invalidation, 1935 * but still correct. Hence, we can allow downgrading PIPT to VIPT, 1936 * but not the other way around. This is handled via arm64_ftr_safe_value() 1937 * as CTR_EL0 ftr_bits has L1Ip field with type FTR_EXACT and safe value 1938 * set as VIPT. 1939 */ 1940 switch (user_L1Ip) { 1941 case CTR_EL0_L1Ip_RESERVED_VPIPT: 1942 case CTR_EL0_L1Ip_RESERVED_AIVIVT: 1943 return -EINVAL; 1944 case CTR_EL0_L1Ip_VIPT: 1945 case CTR_EL0_L1Ip_PIPT: 1946 return set_id_reg(vcpu, rd, user_val); 1947 default: 1948 return -ENOENT; 1949 } 1950 } 1951 1952 /* 1953 * cpufeature ID register user accessors 1954 * 1955 * For now, these registers are immutable for userspace, so no values 1956 * are stored, and for set_id_reg() we don't allow the effective value 1957 * to be changed. 1958 */ 1959 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1960 u64 *val) 1961 { 1962 /* 1963 * Avoid locking if the VM has already started, as the ID registers are 1964 * guaranteed to be invariant at that point. 1965 */ 1966 if (kvm_vm_has_ran_once(vcpu->kvm)) { 1967 *val = read_id_reg(vcpu, rd); 1968 return 0; 1969 } 1970 1971 mutex_lock(&vcpu->kvm->arch.config_lock); 1972 *val = read_id_reg(vcpu, rd); 1973 mutex_unlock(&vcpu->kvm->arch.config_lock); 1974 1975 return 0; 1976 } 1977 1978 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1979 u64 val) 1980 { 1981 u32 id = reg_to_encoding(rd); 1982 int ret; 1983 1984 mutex_lock(&vcpu->kvm->arch.config_lock); 1985 1986 /* 1987 * Once the VM has started the ID registers are immutable. Reject any 1988 * write that does not match the final register value. 1989 */ 1990 if (kvm_vm_has_ran_once(vcpu->kvm)) { 1991 if (val != read_id_reg(vcpu, rd)) 1992 ret = -EBUSY; 1993 else 1994 ret = 0; 1995 1996 mutex_unlock(&vcpu->kvm->arch.config_lock); 1997 return ret; 1998 } 1999 2000 ret = arm64_check_features(vcpu, rd, val); 2001 if (!ret) 2002 kvm_set_vm_id_reg(vcpu->kvm, id, val); 2003 2004 mutex_unlock(&vcpu->kvm->arch.config_lock); 2005 2006 /* 2007 * arm64_check_features() returns -E2BIG to indicate the register's 2008 * feature set is a superset of the maximally-allowed register value. 2009 * While it would be nice to precisely describe this to userspace, the 2010 * existing UAPI for KVM_SET_ONE_REG has it that invalid register 2011 * writes return -EINVAL. 2012 */ 2013 if (ret == -E2BIG) 2014 ret = -EINVAL; 2015 return ret; 2016 } 2017 2018 void kvm_set_vm_id_reg(struct kvm *kvm, u32 reg, u64 val) 2019 { 2020 u64 *p = __vm_id_reg(&kvm->arch, reg); 2021 2022 lockdep_assert_held(&kvm->arch.config_lock); 2023 2024 if (KVM_BUG_ON(kvm_vm_has_ran_once(kvm) || !p, kvm)) 2025 return; 2026 2027 *p = val; 2028 } 2029 2030 static int get_raz_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 2031 u64 *val) 2032 { 2033 *val = 0; 2034 return 0; 2035 } 2036 2037 static int set_wi_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 2038 u64 val) 2039 { 2040 return 0; 2041 } 2042 2043 static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2044 const struct sys_reg_desc *r) 2045 { 2046 if (p->is_write) 2047 return write_to_read_only(vcpu, p, r); 2048 2049 p->regval = kvm_read_vm_id_reg(vcpu->kvm, SYS_CTR_EL0); 2050 return true; 2051 } 2052 2053 static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2054 const struct sys_reg_desc *r) 2055 { 2056 if (p->is_write) 2057 return write_to_read_only(vcpu, p, r); 2058 2059 p->regval = __vcpu_sys_reg(vcpu, r->reg); 2060 return true; 2061 } 2062 2063 /* 2064 * Fabricate a CLIDR_EL1 value instead of using the real value, which can vary 2065 * by the physical CPU which the vcpu currently resides in. 2066 */ 2067 static u64 reset_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 2068 { 2069 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0); 2070 u64 clidr; 2071 u8 loc; 2072 2073 if ((ctr_el0 & CTR_EL0_IDC)) { 2074 /* 2075 * Data cache clean to the PoU is not required so LoUU and LoUIS 2076 * will not be set and a unified cache, which will be marked as 2077 * LoC, will be added. 2078 * 2079 * If not DIC, let the unified cache L2 so that an instruction 2080 * cache can be added as L1 later. 2081 */ 2082 loc = (ctr_el0 & CTR_EL0_DIC) ? 1 : 2; 2083 clidr = CACHE_TYPE_UNIFIED << CLIDR_CTYPE_SHIFT(loc); 2084 } else { 2085 /* 2086 * Data cache clean to the PoU is required so let L1 have a data 2087 * cache and mark it as LoUU and LoUIS. As L1 has a data cache, 2088 * it can be marked as LoC too. 2089 */ 2090 loc = 1; 2091 clidr = 1 << CLIDR_LOUU_SHIFT; 2092 clidr |= 1 << CLIDR_LOUIS_SHIFT; 2093 clidr |= CACHE_TYPE_DATA << CLIDR_CTYPE_SHIFT(1); 2094 } 2095 2096 /* 2097 * Instruction cache invalidation to the PoU is required so let L1 have 2098 * an instruction cache. If L1 already has a data cache, it will be 2099 * CACHE_TYPE_SEPARATE. 2100 */ 2101 if (!(ctr_el0 & CTR_EL0_DIC)) 2102 clidr |= CACHE_TYPE_INST << CLIDR_CTYPE_SHIFT(1); 2103 2104 clidr |= loc << CLIDR_LOC_SHIFT; 2105 2106 /* 2107 * Add tag cache unified to data cache. Allocation tags and data are 2108 * unified in a cache line so that it looks valid even if there is only 2109 * one cache line. 2110 */ 2111 if (kvm_has_mte(vcpu->kvm)) 2112 clidr |= 2ULL << CLIDR_TTYPE_SHIFT(loc); 2113 2114 __vcpu_sys_reg(vcpu, r->reg) = clidr; 2115 2116 return __vcpu_sys_reg(vcpu, r->reg); 2117 } 2118 2119 static int set_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 2120 u64 val) 2121 { 2122 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0); 2123 u64 idc = !CLIDR_LOC(val) || (!CLIDR_LOUIS(val) && !CLIDR_LOUU(val)); 2124 2125 if ((val & CLIDR_EL1_RES0) || (!(ctr_el0 & CTR_EL0_IDC) && idc)) 2126 return -EINVAL; 2127 2128 __vcpu_sys_reg(vcpu, rd->reg) = val; 2129 2130 return 0; 2131 } 2132 2133 static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2134 const struct sys_reg_desc *r) 2135 { 2136 int reg = r->reg; 2137 2138 if (p->is_write) 2139 vcpu_write_sys_reg(vcpu, p->regval, reg); 2140 else 2141 p->regval = vcpu_read_sys_reg(vcpu, reg); 2142 return true; 2143 } 2144 2145 static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2146 const struct sys_reg_desc *r) 2147 { 2148 u32 csselr; 2149 2150 if (p->is_write) 2151 return write_to_read_only(vcpu, p, r); 2152 2153 csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1); 2154 csselr &= CSSELR_EL1_Level | CSSELR_EL1_InD; 2155 if (csselr < CSSELR_MAX) 2156 p->regval = get_ccsidr(vcpu, csselr); 2157 2158 return true; 2159 } 2160 2161 static unsigned int mte_visibility(const struct kvm_vcpu *vcpu, 2162 const struct sys_reg_desc *rd) 2163 { 2164 if (kvm_has_mte(vcpu->kvm)) 2165 return 0; 2166 2167 return REG_HIDDEN; 2168 } 2169 2170 #define MTE_REG(name) { \ 2171 SYS_DESC(SYS_##name), \ 2172 .access = undef_access, \ 2173 .reset = reset_unknown, \ 2174 .reg = name, \ 2175 .visibility = mte_visibility, \ 2176 } 2177 2178 static unsigned int el2_visibility(const struct kvm_vcpu *vcpu, 2179 const struct sys_reg_desc *rd) 2180 { 2181 if (vcpu_has_nv(vcpu)) 2182 return 0; 2183 2184 return REG_HIDDEN; 2185 } 2186 2187 static bool bad_vncr_trap(struct kvm_vcpu *vcpu, 2188 struct sys_reg_params *p, 2189 const struct sys_reg_desc *r) 2190 { 2191 /* 2192 * We really shouldn't be here, and this is likely the result 2193 * of a misconfigured trap, as this register should target the 2194 * VNCR page, and nothing else. 2195 */ 2196 return bad_trap(vcpu, p, r, 2197 "trap of VNCR-backed register"); 2198 } 2199 2200 static bool bad_redir_trap(struct kvm_vcpu *vcpu, 2201 struct sys_reg_params *p, 2202 const struct sys_reg_desc *r) 2203 { 2204 /* 2205 * We really shouldn't be here, and this is likely the result 2206 * of a misconfigured trap, as this register should target the 2207 * corresponding EL1, and nothing else. 2208 */ 2209 return bad_trap(vcpu, p, r, 2210 "trap of EL2 register redirected to EL1"); 2211 } 2212 2213 #define EL2_REG(name, acc, rst, v) { \ 2214 SYS_DESC(SYS_##name), \ 2215 .access = acc, \ 2216 .reset = rst, \ 2217 .reg = name, \ 2218 .visibility = el2_visibility, \ 2219 .val = v, \ 2220 } 2221 2222 #define EL2_REG_FILTERED(name, acc, rst, v, filter) { \ 2223 SYS_DESC(SYS_##name), \ 2224 .access = acc, \ 2225 .reset = rst, \ 2226 .reg = name, \ 2227 .visibility = filter, \ 2228 .val = v, \ 2229 } 2230 2231 #define EL2_REG_VNCR(name, rst, v) EL2_REG(name, bad_vncr_trap, rst, v) 2232 #define EL2_REG_REDIR(name, rst, v) EL2_REG(name, bad_redir_trap, rst, v) 2233 2234 /* 2235 * Since reset() callback and field val are not used for idregs, they will be 2236 * used for specific purposes for idregs. 2237 * The reset() would return KVM sanitised register value. The value would be the 2238 * same as the host kernel sanitised value if there is no KVM sanitisation. 2239 * The val would be used as a mask indicating writable fields for the idreg. 2240 * Only bits with 1 are writable from userspace. This mask might not be 2241 * necessary in the future whenever all ID registers are enabled as writable 2242 * from userspace. 2243 */ 2244 2245 #define ID_DESC(name) \ 2246 SYS_DESC(SYS_##name), \ 2247 .access = access_id_reg, \ 2248 .get_user = get_id_reg \ 2249 2250 /* sys_reg_desc initialiser for known cpufeature ID registers */ 2251 #define ID_SANITISED(name) { \ 2252 ID_DESC(name), \ 2253 .set_user = set_id_reg, \ 2254 .visibility = id_visibility, \ 2255 .reset = kvm_read_sanitised_id_reg, \ 2256 .val = 0, \ 2257 } 2258 2259 /* sys_reg_desc initialiser for known cpufeature ID registers */ 2260 #define AA32_ID_SANITISED(name) { \ 2261 ID_DESC(name), \ 2262 .set_user = set_id_reg, \ 2263 .visibility = aa32_id_visibility, \ 2264 .reset = kvm_read_sanitised_id_reg, \ 2265 .val = 0, \ 2266 } 2267 2268 /* sys_reg_desc initialiser for writable ID registers */ 2269 #define ID_WRITABLE(name, mask) { \ 2270 ID_DESC(name), \ 2271 .set_user = set_id_reg, \ 2272 .visibility = id_visibility, \ 2273 .reset = kvm_read_sanitised_id_reg, \ 2274 .val = mask, \ 2275 } 2276 2277 /* sys_reg_desc initialiser for cpufeature ID registers that need filtering */ 2278 #define ID_FILTERED(sysreg, name, mask) { \ 2279 ID_DESC(sysreg), \ 2280 .set_user = set_##name, \ 2281 .visibility = id_visibility, \ 2282 .reset = kvm_read_sanitised_id_reg, \ 2283 .val = (mask), \ 2284 } 2285 2286 /* 2287 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID 2288 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2 2289 * (1 <= crm < 8, 0 <= Op2 < 8). 2290 */ 2291 #define ID_UNALLOCATED(crm, op2) { \ 2292 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \ 2293 .access = access_id_reg, \ 2294 .get_user = get_id_reg, \ 2295 .set_user = set_id_reg, \ 2296 .visibility = raz_visibility, \ 2297 .reset = kvm_read_sanitised_id_reg, \ 2298 .val = 0, \ 2299 } 2300 2301 /* 2302 * sys_reg_desc initialiser for known ID registers that we hide from guests. 2303 * For now, these are exposed just like unallocated ID regs: they appear 2304 * RAZ for the guest. 2305 */ 2306 #define ID_HIDDEN(name) { \ 2307 ID_DESC(name), \ 2308 .set_user = set_id_reg, \ 2309 .visibility = raz_visibility, \ 2310 .reset = kvm_read_sanitised_id_reg, \ 2311 .val = 0, \ 2312 } 2313 2314 static bool access_sp_el1(struct kvm_vcpu *vcpu, 2315 struct sys_reg_params *p, 2316 const struct sys_reg_desc *r) 2317 { 2318 if (p->is_write) 2319 __vcpu_sys_reg(vcpu, SP_EL1) = p->regval; 2320 else 2321 p->regval = __vcpu_sys_reg(vcpu, SP_EL1); 2322 2323 return true; 2324 } 2325 2326 static bool access_elr(struct kvm_vcpu *vcpu, 2327 struct sys_reg_params *p, 2328 const struct sys_reg_desc *r) 2329 { 2330 if (p->is_write) 2331 vcpu_write_sys_reg(vcpu, p->regval, ELR_EL1); 2332 else 2333 p->regval = vcpu_read_sys_reg(vcpu, ELR_EL1); 2334 2335 return true; 2336 } 2337 2338 static bool access_spsr(struct kvm_vcpu *vcpu, 2339 struct sys_reg_params *p, 2340 const struct sys_reg_desc *r) 2341 { 2342 if (p->is_write) 2343 __vcpu_sys_reg(vcpu, SPSR_EL1) = p->regval; 2344 else 2345 p->regval = __vcpu_sys_reg(vcpu, SPSR_EL1); 2346 2347 return true; 2348 } 2349 2350 static bool access_cntkctl_el12(struct kvm_vcpu *vcpu, 2351 struct sys_reg_params *p, 2352 const struct sys_reg_desc *r) 2353 { 2354 if (p->is_write) 2355 __vcpu_sys_reg(vcpu, CNTKCTL_EL1) = p->regval; 2356 else 2357 p->regval = __vcpu_sys_reg(vcpu, CNTKCTL_EL1); 2358 2359 return true; 2360 } 2361 2362 static u64 reset_hcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 2363 { 2364 u64 val = r->val; 2365 2366 if (!cpus_have_final_cap(ARM64_HAS_HCR_NV1)) 2367 val |= HCR_E2H; 2368 2369 return __vcpu_sys_reg(vcpu, r->reg) = val; 2370 } 2371 2372 static unsigned int __el2_visibility(const struct kvm_vcpu *vcpu, 2373 const struct sys_reg_desc *rd, 2374 unsigned int (*fn)(const struct kvm_vcpu *, 2375 const struct sys_reg_desc *)) 2376 { 2377 return el2_visibility(vcpu, rd) ?: fn(vcpu, rd); 2378 } 2379 2380 static unsigned int sve_el2_visibility(const struct kvm_vcpu *vcpu, 2381 const struct sys_reg_desc *rd) 2382 { 2383 return __el2_visibility(vcpu, rd, sve_visibility); 2384 } 2385 2386 static bool access_zcr_el2(struct kvm_vcpu *vcpu, 2387 struct sys_reg_params *p, 2388 const struct sys_reg_desc *r) 2389 { 2390 unsigned int vq; 2391 2392 if (guest_hyp_sve_traps_enabled(vcpu)) { 2393 kvm_inject_nested_sve_trap(vcpu); 2394 return true; 2395 } 2396 2397 if (!p->is_write) { 2398 p->regval = vcpu_read_sys_reg(vcpu, ZCR_EL2); 2399 return true; 2400 } 2401 2402 vq = SYS_FIELD_GET(ZCR_ELx, LEN, p->regval) + 1; 2403 vq = min(vq, vcpu_sve_max_vq(vcpu)); 2404 vcpu_write_sys_reg(vcpu, vq - 1, ZCR_EL2); 2405 return true; 2406 } 2407 2408 static unsigned int s1poe_visibility(const struct kvm_vcpu *vcpu, 2409 const struct sys_reg_desc *rd) 2410 { 2411 if (kvm_has_s1poe(vcpu->kvm)) 2412 return 0; 2413 2414 return REG_HIDDEN; 2415 } 2416 2417 static unsigned int s1poe_el2_visibility(const struct kvm_vcpu *vcpu, 2418 const struct sys_reg_desc *rd) 2419 { 2420 return __el2_visibility(vcpu, rd, s1poe_visibility); 2421 } 2422 2423 static unsigned int tcr2_visibility(const struct kvm_vcpu *vcpu, 2424 const struct sys_reg_desc *rd) 2425 { 2426 if (kvm_has_tcr2(vcpu->kvm)) 2427 return 0; 2428 2429 return REG_HIDDEN; 2430 } 2431 2432 static unsigned int tcr2_el2_visibility(const struct kvm_vcpu *vcpu, 2433 const struct sys_reg_desc *rd) 2434 { 2435 return __el2_visibility(vcpu, rd, tcr2_visibility); 2436 } 2437 2438 static unsigned int s1pie_visibility(const struct kvm_vcpu *vcpu, 2439 const struct sys_reg_desc *rd) 2440 { 2441 if (kvm_has_s1pie(vcpu->kvm)) 2442 return 0; 2443 2444 return REG_HIDDEN; 2445 } 2446 2447 static unsigned int s1pie_el2_visibility(const struct kvm_vcpu *vcpu, 2448 const struct sys_reg_desc *rd) 2449 { 2450 return __el2_visibility(vcpu, rd, s1pie_visibility); 2451 } 2452 2453 /* 2454 * Architected system registers. 2455 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2 2456 * 2457 * Debug handling: We do trap most, if not all debug related system 2458 * registers. The implementation is good enough to ensure that a guest 2459 * can use these with minimal performance degradation. The drawback is 2460 * that we don't implement any of the external debug architecture. 2461 * This should be revisited if we ever encounter a more demanding 2462 * guest... 2463 */ 2464 static const struct sys_reg_desc sys_reg_descs[] = { 2465 DBG_BCR_BVR_WCR_WVR_EL1(0), 2466 DBG_BCR_BVR_WCR_WVR_EL1(1), 2467 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 }, 2468 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 }, 2469 DBG_BCR_BVR_WCR_WVR_EL1(2), 2470 DBG_BCR_BVR_WCR_WVR_EL1(3), 2471 DBG_BCR_BVR_WCR_WVR_EL1(4), 2472 DBG_BCR_BVR_WCR_WVR_EL1(5), 2473 DBG_BCR_BVR_WCR_WVR_EL1(6), 2474 DBG_BCR_BVR_WCR_WVR_EL1(7), 2475 DBG_BCR_BVR_WCR_WVR_EL1(8), 2476 DBG_BCR_BVR_WCR_WVR_EL1(9), 2477 DBG_BCR_BVR_WCR_WVR_EL1(10), 2478 DBG_BCR_BVR_WCR_WVR_EL1(11), 2479 DBG_BCR_BVR_WCR_WVR_EL1(12), 2480 DBG_BCR_BVR_WCR_WVR_EL1(13), 2481 DBG_BCR_BVR_WCR_WVR_EL1(14), 2482 DBG_BCR_BVR_WCR_WVR_EL1(15), 2483 2484 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi }, 2485 { SYS_DESC(SYS_OSLAR_EL1), trap_oslar_el1 }, 2486 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1, 2487 OSLSR_EL1_OSLM_IMPLEMENTED, .set_user = set_oslsr_el1, }, 2488 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi }, 2489 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi }, 2490 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi }, 2491 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi }, 2492 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 }, 2493 2494 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi }, 2495 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi }, 2496 // DBGDTR[TR]X_EL0 share the same encoding 2497 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi }, 2498 2499 { SYS_DESC(SYS_DBGVCR32_EL2), undef_access, reset_val, DBGVCR32_EL2, 0 }, 2500 2501 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 }, 2502 2503 /* 2504 * ID regs: all ID_SANITISED() entries here must have corresponding 2505 * entries in arm64_ftr_regs[]. 2506 */ 2507 2508 /* AArch64 mappings of the AArch32 ID registers */ 2509 /* CRm=1 */ 2510 AA32_ID_SANITISED(ID_PFR0_EL1), 2511 AA32_ID_SANITISED(ID_PFR1_EL1), 2512 { SYS_DESC(SYS_ID_DFR0_EL1), 2513 .access = access_id_reg, 2514 .get_user = get_id_reg, 2515 .set_user = set_id_dfr0_el1, 2516 .visibility = aa32_id_visibility, 2517 .reset = read_sanitised_id_dfr0_el1, 2518 .val = ID_DFR0_EL1_PerfMon_MASK | 2519 ID_DFR0_EL1_CopDbg_MASK, }, 2520 ID_HIDDEN(ID_AFR0_EL1), 2521 AA32_ID_SANITISED(ID_MMFR0_EL1), 2522 AA32_ID_SANITISED(ID_MMFR1_EL1), 2523 AA32_ID_SANITISED(ID_MMFR2_EL1), 2524 AA32_ID_SANITISED(ID_MMFR3_EL1), 2525 2526 /* CRm=2 */ 2527 AA32_ID_SANITISED(ID_ISAR0_EL1), 2528 AA32_ID_SANITISED(ID_ISAR1_EL1), 2529 AA32_ID_SANITISED(ID_ISAR2_EL1), 2530 AA32_ID_SANITISED(ID_ISAR3_EL1), 2531 AA32_ID_SANITISED(ID_ISAR4_EL1), 2532 AA32_ID_SANITISED(ID_ISAR5_EL1), 2533 AA32_ID_SANITISED(ID_MMFR4_EL1), 2534 AA32_ID_SANITISED(ID_ISAR6_EL1), 2535 2536 /* CRm=3 */ 2537 AA32_ID_SANITISED(MVFR0_EL1), 2538 AA32_ID_SANITISED(MVFR1_EL1), 2539 AA32_ID_SANITISED(MVFR2_EL1), 2540 ID_UNALLOCATED(3,3), 2541 AA32_ID_SANITISED(ID_PFR2_EL1), 2542 ID_HIDDEN(ID_DFR1_EL1), 2543 AA32_ID_SANITISED(ID_MMFR5_EL1), 2544 ID_UNALLOCATED(3,7), 2545 2546 /* AArch64 ID registers */ 2547 /* CRm=4 */ 2548 ID_FILTERED(ID_AA64PFR0_EL1, id_aa64pfr0_el1, 2549 ~(ID_AA64PFR0_EL1_AMU | 2550 ID_AA64PFR0_EL1_MPAM | 2551 ID_AA64PFR0_EL1_SVE | 2552 ID_AA64PFR0_EL1_RAS | 2553 ID_AA64PFR0_EL1_AdvSIMD | 2554 ID_AA64PFR0_EL1_FP)), 2555 ID_FILTERED(ID_AA64PFR1_EL1, id_aa64pfr1_el1, 2556 ~(ID_AA64PFR1_EL1_PFAR | 2557 ID_AA64PFR1_EL1_DF2 | 2558 ID_AA64PFR1_EL1_MTEX | 2559 ID_AA64PFR1_EL1_THE | 2560 ID_AA64PFR1_EL1_GCS | 2561 ID_AA64PFR1_EL1_MTE_frac | 2562 ID_AA64PFR1_EL1_NMI | 2563 ID_AA64PFR1_EL1_RNDR_trap | 2564 ID_AA64PFR1_EL1_SME | 2565 ID_AA64PFR1_EL1_RES0 | 2566 ID_AA64PFR1_EL1_MPAM_frac | 2567 ID_AA64PFR1_EL1_RAS_frac | 2568 ID_AA64PFR1_EL1_MTE)), 2569 ID_WRITABLE(ID_AA64PFR2_EL1, ID_AA64PFR2_EL1_FPMR), 2570 ID_UNALLOCATED(4,3), 2571 ID_WRITABLE(ID_AA64ZFR0_EL1, ~ID_AA64ZFR0_EL1_RES0), 2572 ID_HIDDEN(ID_AA64SMFR0_EL1), 2573 ID_UNALLOCATED(4,6), 2574 ID_WRITABLE(ID_AA64FPFR0_EL1, ~ID_AA64FPFR0_EL1_RES0), 2575 2576 /* CRm=5 */ 2577 /* 2578 * Prior to FEAT_Debugv8.9, the architecture defines context-aware 2579 * breakpoints (CTX_CMPs) as the highest numbered breakpoints (BRPs). 2580 * KVM does not trap + emulate the breakpoint registers, and as such 2581 * cannot support a layout that misaligns with the underlying hardware. 2582 * While it may be possible to describe a subset that aligns with 2583 * hardware, just prevent changes to BRPs and CTX_CMPs altogether for 2584 * simplicity. 2585 * 2586 * See DDI0487K.a, section D2.8.3 Breakpoint types and linking 2587 * of breakpoints for more details. 2588 */ 2589 ID_FILTERED(ID_AA64DFR0_EL1, id_aa64dfr0_el1, 2590 ID_AA64DFR0_EL1_DoubleLock_MASK | 2591 ID_AA64DFR0_EL1_WRPs_MASK | 2592 ID_AA64DFR0_EL1_PMUVer_MASK | 2593 ID_AA64DFR0_EL1_DebugVer_MASK), 2594 ID_SANITISED(ID_AA64DFR1_EL1), 2595 ID_UNALLOCATED(5,2), 2596 ID_UNALLOCATED(5,3), 2597 ID_HIDDEN(ID_AA64AFR0_EL1), 2598 ID_HIDDEN(ID_AA64AFR1_EL1), 2599 ID_UNALLOCATED(5,6), 2600 ID_UNALLOCATED(5,7), 2601 2602 /* CRm=6 */ 2603 ID_WRITABLE(ID_AA64ISAR0_EL1, ~ID_AA64ISAR0_EL1_RES0), 2604 ID_WRITABLE(ID_AA64ISAR1_EL1, ~(ID_AA64ISAR1_EL1_GPI | 2605 ID_AA64ISAR1_EL1_GPA | 2606 ID_AA64ISAR1_EL1_API | 2607 ID_AA64ISAR1_EL1_APA)), 2608 ID_WRITABLE(ID_AA64ISAR2_EL1, ~(ID_AA64ISAR2_EL1_RES0 | 2609 ID_AA64ISAR2_EL1_APA3 | 2610 ID_AA64ISAR2_EL1_GPA3)), 2611 ID_UNALLOCATED(6,3), 2612 ID_UNALLOCATED(6,4), 2613 ID_UNALLOCATED(6,5), 2614 ID_UNALLOCATED(6,6), 2615 ID_UNALLOCATED(6,7), 2616 2617 /* CRm=7 */ 2618 ID_WRITABLE(ID_AA64MMFR0_EL1, ~(ID_AA64MMFR0_EL1_RES0 | 2619 ID_AA64MMFR0_EL1_TGRAN4_2 | 2620 ID_AA64MMFR0_EL1_TGRAN64_2 | 2621 ID_AA64MMFR0_EL1_TGRAN16_2 | 2622 ID_AA64MMFR0_EL1_ASIDBITS)), 2623 ID_WRITABLE(ID_AA64MMFR1_EL1, ~(ID_AA64MMFR1_EL1_RES0 | 2624 ID_AA64MMFR1_EL1_HCX | 2625 ID_AA64MMFR1_EL1_TWED | 2626 ID_AA64MMFR1_EL1_XNX | 2627 ID_AA64MMFR1_EL1_VH | 2628 ID_AA64MMFR1_EL1_VMIDBits)), 2629 ID_WRITABLE(ID_AA64MMFR2_EL1, ~(ID_AA64MMFR2_EL1_RES0 | 2630 ID_AA64MMFR2_EL1_EVT | 2631 ID_AA64MMFR2_EL1_FWB | 2632 ID_AA64MMFR2_EL1_IDS | 2633 ID_AA64MMFR2_EL1_NV | 2634 ID_AA64MMFR2_EL1_CCIDX)), 2635 ID_WRITABLE(ID_AA64MMFR3_EL1, (ID_AA64MMFR3_EL1_TCRX | 2636 ID_AA64MMFR3_EL1_S1PIE | 2637 ID_AA64MMFR3_EL1_S1POE)), 2638 ID_SANITISED(ID_AA64MMFR4_EL1), 2639 ID_UNALLOCATED(7,5), 2640 ID_UNALLOCATED(7,6), 2641 ID_UNALLOCATED(7,7), 2642 2643 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 }, 2644 { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 }, 2645 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 }, 2646 2647 MTE_REG(RGSR_EL1), 2648 MTE_REG(GCR_EL1), 2649 2650 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility }, 2651 { SYS_DESC(SYS_TRFCR_EL1), undef_access }, 2652 { SYS_DESC(SYS_SMPRI_EL1), undef_access }, 2653 { SYS_DESC(SYS_SMCR_EL1), undef_access }, 2654 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 }, 2655 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 }, 2656 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 }, 2657 { SYS_DESC(SYS_TCR2_EL1), access_vm_reg, reset_val, TCR2_EL1, 0, 2658 .visibility = tcr2_visibility }, 2659 2660 PTRAUTH_KEY(APIA), 2661 PTRAUTH_KEY(APIB), 2662 PTRAUTH_KEY(APDA), 2663 PTRAUTH_KEY(APDB), 2664 PTRAUTH_KEY(APGA), 2665 2666 { SYS_DESC(SYS_SPSR_EL1), access_spsr}, 2667 { SYS_DESC(SYS_ELR_EL1), access_elr}, 2668 2669 { SYS_DESC(SYS_ICC_PMR_EL1), undef_access }, 2670 2671 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 }, 2672 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 }, 2673 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 }, 2674 2675 { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi }, 2676 { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi }, 2677 { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi }, 2678 { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi }, 2679 { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi }, 2680 { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi }, 2681 { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi }, 2682 { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi }, 2683 2684 MTE_REG(TFSR_EL1), 2685 MTE_REG(TFSRE0_EL1), 2686 2687 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 }, 2688 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 }, 2689 2690 { SYS_DESC(SYS_PMSCR_EL1), undef_access }, 2691 { SYS_DESC(SYS_PMSNEVFR_EL1), undef_access }, 2692 { SYS_DESC(SYS_PMSICR_EL1), undef_access }, 2693 { SYS_DESC(SYS_PMSIRR_EL1), undef_access }, 2694 { SYS_DESC(SYS_PMSFCR_EL1), undef_access }, 2695 { SYS_DESC(SYS_PMSEVFR_EL1), undef_access }, 2696 { SYS_DESC(SYS_PMSLATFR_EL1), undef_access }, 2697 { SYS_DESC(SYS_PMSIDR_EL1), undef_access }, 2698 { SYS_DESC(SYS_PMBLIMITR_EL1), undef_access }, 2699 { SYS_DESC(SYS_PMBPTR_EL1), undef_access }, 2700 { SYS_DESC(SYS_PMBSR_EL1), undef_access }, 2701 /* PMBIDR_EL1 is not trapped */ 2702 2703 { PMU_SYS_REG(PMINTENSET_EL1), 2704 .access = access_pminten, .reg = PMINTENSET_EL1, 2705 .get_user = get_pmreg, .set_user = set_pmreg }, 2706 { PMU_SYS_REG(PMINTENCLR_EL1), 2707 .access = access_pminten, .reg = PMINTENSET_EL1, 2708 .get_user = get_pmreg, .set_user = set_pmreg }, 2709 { SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi }, 2710 2711 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 }, 2712 { SYS_DESC(SYS_PIRE0_EL1), NULL, reset_unknown, PIRE0_EL1, 2713 .visibility = s1pie_visibility }, 2714 { SYS_DESC(SYS_PIR_EL1), NULL, reset_unknown, PIR_EL1, 2715 .visibility = s1pie_visibility }, 2716 { SYS_DESC(SYS_POR_EL1), NULL, reset_unknown, POR_EL1, 2717 .visibility = s1poe_visibility }, 2718 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 }, 2719 2720 { SYS_DESC(SYS_LORSA_EL1), trap_loregion }, 2721 { SYS_DESC(SYS_LOREA_EL1), trap_loregion }, 2722 { SYS_DESC(SYS_LORN_EL1), trap_loregion }, 2723 { SYS_DESC(SYS_LORC_EL1), trap_loregion }, 2724 { SYS_DESC(SYS_MPAMIDR_EL1), undef_access }, 2725 { SYS_DESC(SYS_LORID_EL1), trap_loregion }, 2726 2727 { SYS_DESC(SYS_MPAM1_EL1), undef_access }, 2728 { SYS_DESC(SYS_MPAM0_EL1), undef_access }, 2729 { SYS_DESC(SYS_VBAR_EL1), access_rw, reset_val, VBAR_EL1, 0 }, 2730 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 }, 2731 2732 { SYS_DESC(SYS_ICC_IAR0_EL1), undef_access }, 2733 { SYS_DESC(SYS_ICC_EOIR0_EL1), undef_access }, 2734 { SYS_DESC(SYS_ICC_HPPIR0_EL1), undef_access }, 2735 { SYS_DESC(SYS_ICC_BPR0_EL1), undef_access }, 2736 { SYS_DESC(SYS_ICC_AP0R0_EL1), undef_access }, 2737 { SYS_DESC(SYS_ICC_AP0R1_EL1), undef_access }, 2738 { SYS_DESC(SYS_ICC_AP0R2_EL1), undef_access }, 2739 { SYS_DESC(SYS_ICC_AP0R3_EL1), undef_access }, 2740 { SYS_DESC(SYS_ICC_AP1R0_EL1), undef_access }, 2741 { SYS_DESC(SYS_ICC_AP1R1_EL1), undef_access }, 2742 { SYS_DESC(SYS_ICC_AP1R2_EL1), undef_access }, 2743 { SYS_DESC(SYS_ICC_AP1R3_EL1), undef_access }, 2744 { SYS_DESC(SYS_ICC_DIR_EL1), undef_access }, 2745 { SYS_DESC(SYS_ICC_RPR_EL1), undef_access }, 2746 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi }, 2747 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi }, 2748 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi }, 2749 { SYS_DESC(SYS_ICC_IAR1_EL1), undef_access }, 2750 { SYS_DESC(SYS_ICC_EOIR1_EL1), undef_access }, 2751 { SYS_DESC(SYS_ICC_HPPIR1_EL1), undef_access }, 2752 { SYS_DESC(SYS_ICC_BPR1_EL1), undef_access }, 2753 { SYS_DESC(SYS_ICC_CTLR_EL1), undef_access }, 2754 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre }, 2755 { SYS_DESC(SYS_ICC_IGRPEN0_EL1), undef_access }, 2756 { SYS_DESC(SYS_ICC_IGRPEN1_EL1), undef_access }, 2757 2758 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 }, 2759 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 }, 2760 2761 { SYS_DESC(SYS_ACCDATA_EL1), undef_access }, 2762 2763 { SYS_DESC(SYS_SCXTNUM_EL1), undef_access }, 2764 2765 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0}, 2766 2767 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr }, 2768 { SYS_DESC(SYS_CLIDR_EL1), access_clidr, reset_clidr, CLIDR_EL1, 2769 .set_user = set_clidr, .val = ~CLIDR_EL1_RES0 }, 2770 { SYS_DESC(SYS_CCSIDR2_EL1), undef_access }, 2771 { SYS_DESC(SYS_SMIDR_EL1), undef_access }, 2772 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, 2773 ID_FILTERED(CTR_EL0, ctr_el0, 2774 CTR_EL0_DIC_MASK | 2775 CTR_EL0_IDC_MASK | 2776 CTR_EL0_DminLine_MASK | 2777 CTR_EL0_L1Ip_MASK | 2778 CTR_EL0_IminLine_MASK), 2779 { SYS_DESC(SYS_SVCR), undef_access, reset_val, SVCR, 0, .visibility = sme_visibility }, 2780 { SYS_DESC(SYS_FPMR), undef_access, reset_val, FPMR, 0, .visibility = fp8_visibility }, 2781 2782 { PMU_SYS_REG(PMCR_EL0), .access = access_pmcr, .reset = reset_pmcr, 2783 .reg = PMCR_EL0, .get_user = get_pmcr, .set_user = set_pmcr }, 2784 { PMU_SYS_REG(PMCNTENSET_EL0), 2785 .access = access_pmcnten, .reg = PMCNTENSET_EL0, 2786 .get_user = get_pmreg, .set_user = set_pmreg }, 2787 { PMU_SYS_REG(PMCNTENCLR_EL0), 2788 .access = access_pmcnten, .reg = PMCNTENSET_EL0, 2789 .get_user = get_pmreg, .set_user = set_pmreg }, 2790 { PMU_SYS_REG(PMOVSCLR_EL0), 2791 .access = access_pmovs, .reg = PMOVSSET_EL0, 2792 .get_user = get_pmreg, .set_user = set_pmreg }, 2793 /* 2794 * PM_SWINC_EL0 is exposed to userspace as RAZ/WI, as it was 2795 * previously (and pointlessly) advertised in the past... 2796 */ 2797 { PMU_SYS_REG(PMSWINC_EL0), 2798 .get_user = get_raz_reg, .set_user = set_wi_reg, 2799 .access = access_pmswinc, .reset = NULL }, 2800 { PMU_SYS_REG(PMSELR_EL0), 2801 .access = access_pmselr, .reset = reset_pmselr, .reg = PMSELR_EL0 }, 2802 { PMU_SYS_REG(PMCEID0_EL0), 2803 .access = access_pmceid, .reset = NULL }, 2804 { PMU_SYS_REG(PMCEID1_EL0), 2805 .access = access_pmceid, .reset = NULL }, 2806 { PMU_SYS_REG(PMCCNTR_EL0), 2807 .access = access_pmu_evcntr, .reset = reset_unknown, 2808 .reg = PMCCNTR_EL0, .get_user = get_pmu_evcntr}, 2809 { PMU_SYS_REG(PMXEVTYPER_EL0), 2810 .access = access_pmu_evtyper, .reset = NULL }, 2811 { PMU_SYS_REG(PMXEVCNTR_EL0), 2812 .access = access_pmu_evcntr, .reset = NULL }, 2813 /* 2814 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero 2815 * in 32bit mode. Here we choose to reset it as zero for consistency. 2816 */ 2817 { PMU_SYS_REG(PMUSERENR_EL0), .access = access_pmuserenr, 2818 .reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 }, 2819 { PMU_SYS_REG(PMOVSSET_EL0), 2820 .access = access_pmovs, .reg = PMOVSSET_EL0, 2821 .get_user = get_pmreg, .set_user = set_pmreg }, 2822 2823 { SYS_DESC(SYS_POR_EL0), NULL, reset_unknown, POR_EL0, 2824 .visibility = s1poe_visibility }, 2825 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 }, 2826 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 }, 2827 { SYS_DESC(SYS_TPIDR2_EL0), undef_access }, 2828 2829 { SYS_DESC(SYS_SCXTNUM_EL0), undef_access }, 2830 2831 { SYS_DESC(SYS_AMCR_EL0), undef_access }, 2832 { SYS_DESC(SYS_AMCFGR_EL0), undef_access }, 2833 { SYS_DESC(SYS_AMCGCR_EL0), undef_access }, 2834 { SYS_DESC(SYS_AMUSERENR_EL0), undef_access }, 2835 { SYS_DESC(SYS_AMCNTENCLR0_EL0), undef_access }, 2836 { SYS_DESC(SYS_AMCNTENSET0_EL0), undef_access }, 2837 { SYS_DESC(SYS_AMCNTENCLR1_EL0), undef_access }, 2838 { SYS_DESC(SYS_AMCNTENSET1_EL0), undef_access }, 2839 AMU_AMEVCNTR0_EL0(0), 2840 AMU_AMEVCNTR0_EL0(1), 2841 AMU_AMEVCNTR0_EL0(2), 2842 AMU_AMEVCNTR0_EL0(3), 2843 AMU_AMEVCNTR0_EL0(4), 2844 AMU_AMEVCNTR0_EL0(5), 2845 AMU_AMEVCNTR0_EL0(6), 2846 AMU_AMEVCNTR0_EL0(7), 2847 AMU_AMEVCNTR0_EL0(8), 2848 AMU_AMEVCNTR0_EL0(9), 2849 AMU_AMEVCNTR0_EL0(10), 2850 AMU_AMEVCNTR0_EL0(11), 2851 AMU_AMEVCNTR0_EL0(12), 2852 AMU_AMEVCNTR0_EL0(13), 2853 AMU_AMEVCNTR0_EL0(14), 2854 AMU_AMEVCNTR0_EL0(15), 2855 AMU_AMEVTYPER0_EL0(0), 2856 AMU_AMEVTYPER0_EL0(1), 2857 AMU_AMEVTYPER0_EL0(2), 2858 AMU_AMEVTYPER0_EL0(3), 2859 AMU_AMEVTYPER0_EL0(4), 2860 AMU_AMEVTYPER0_EL0(5), 2861 AMU_AMEVTYPER0_EL0(6), 2862 AMU_AMEVTYPER0_EL0(7), 2863 AMU_AMEVTYPER0_EL0(8), 2864 AMU_AMEVTYPER0_EL0(9), 2865 AMU_AMEVTYPER0_EL0(10), 2866 AMU_AMEVTYPER0_EL0(11), 2867 AMU_AMEVTYPER0_EL0(12), 2868 AMU_AMEVTYPER0_EL0(13), 2869 AMU_AMEVTYPER0_EL0(14), 2870 AMU_AMEVTYPER0_EL0(15), 2871 AMU_AMEVCNTR1_EL0(0), 2872 AMU_AMEVCNTR1_EL0(1), 2873 AMU_AMEVCNTR1_EL0(2), 2874 AMU_AMEVCNTR1_EL0(3), 2875 AMU_AMEVCNTR1_EL0(4), 2876 AMU_AMEVCNTR1_EL0(5), 2877 AMU_AMEVCNTR1_EL0(6), 2878 AMU_AMEVCNTR1_EL0(7), 2879 AMU_AMEVCNTR1_EL0(8), 2880 AMU_AMEVCNTR1_EL0(9), 2881 AMU_AMEVCNTR1_EL0(10), 2882 AMU_AMEVCNTR1_EL0(11), 2883 AMU_AMEVCNTR1_EL0(12), 2884 AMU_AMEVCNTR1_EL0(13), 2885 AMU_AMEVCNTR1_EL0(14), 2886 AMU_AMEVCNTR1_EL0(15), 2887 AMU_AMEVTYPER1_EL0(0), 2888 AMU_AMEVTYPER1_EL0(1), 2889 AMU_AMEVTYPER1_EL0(2), 2890 AMU_AMEVTYPER1_EL0(3), 2891 AMU_AMEVTYPER1_EL0(4), 2892 AMU_AMEVTYPER1_EL0(5), 2893 AMU_AMEVTYPER1_EL0(6), 2894 AMU_AMEVTYPER1_EL0(7), 2895 AMU_AMEVTYPER1_EL0(8), 2896 AMU_AMEVTYPER1_EL0(9), 2897 AMU_AMEVTYPER1_EL0(10), 2898 AMU_AMEVTYPER1_EL0(11), 2899 AMU_AMEVTYPER1_EL0(12), 2900 AMU_AMEVTYPER1_EL0(13), 2901 AMU_AMEVTYPER1_EL0(14), 2902 AMU_AMEVTYPER1_EL0(15), 2903 2904 { SYS_DESC(SYS_CNTPCT_EL0), access_arch_timer }, 2905 { SYS_DESC(SYS_CNTPCTSS_EL0), access_arch_timer }, 2906 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer }, 2907 { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer }, 2908 { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer }, 2909 2910 /* PMEVCNTRn_EL0 */ 2911 PMU_PMEVCNTR_EL0(0), 2912 PMU_PMEVCNTR_EL0(1), 2913 PMU_PMEVCNTR_EL0(2), 2914 PMU_PMEVCNTR_EL0(3), 2915 PMU_PMEVCNTR_EL0(4), 2916 PMU_PMEVCNTR_EL0(5), 2917 PMU_PMEVCNTR_EL0(6), 2918 PMU_PMEVCNTR_EL0(7), 2919 PMU_PMEVCNTR_EL0(8), 2920 PMU_PMEVCNTR_EL0(9), 2921 PMU_PMEVCNTR_EL0(10), 2922 PMU_PMEVCNTR_EL0(11), 2923 PMU_PMEVCNTR_EL0(12), 2924 PMU_PMEVCNTR_EL0(13), 2925 PMU_PMEVCNTR_EL0(14), 2926 PMU_PMEVCNTR_EL0(15), 2927 PMU_PMEVCNTR_EL0(16), 2928 PMU_PMEVCNTR_EL0(17), 2929 PMU_PMEVCNTR_EL0(18), 2930 PMU_PMEVCNTR_EL0(19), 2931 PMU_PMEVCNTR_EL0(20), 2932 PMU_PMEVCNTR_EL0(21), 2933 PMU_PMEVCNTR_EL0(22), 2934 PMU_PMEVCNTR_EL0(23), 2935 PMU_PMEVCNTR_EL0(24), 2936 PMU_PMEVCNTR_EL0(25), 2937 PMU_PMEVCNTR_EL0(26), 2938 PMU_PMEVCNTR_EL0(27), 2939 PMU_PMEVCNTR_EL0(28), 2940 PMU_PMEVCNTR_EL0(29), 2941 PMU_PMEVCNTR_EL0(30), 2942 /* PMEVTYPERn_EL0 */ 2943 PMU_PMEVTYPER_EL0(0), 2944 PMU_PMEVTYPER_EL0(1), 2945 PMU_PMEVTYPER_EL0(2), 2946 PMU_PMEVTYPER_EL0(3), 2947 PMU_PMEVTYPER_EL0(4), 2948 PMU_PMEVTYPER_EL0(5), 2949 PMU_PMEVTYPER_EL0(6), 2950 PMU_PMEVTYPER_EL0(7), 2951 PMU_PMEVTYPER_EL0(8), 2952 PMU_PMEVTYPER_EL0(9), 2953 PMU_PMEVTYPER_EL0(10), 2954 PMU_PMEVTYPER_EL0(11), 2955 PMU_PMEVTYPER_EL0(12), 2956 PMU_PMEVTYPER_EL0(13), 2957 PMU_PMEVTYPER_EL0(14), 2958 PMU_PMEVTYPER_EL0(15), 2959 PMU_PMEVTYPER_EL0(16), 2960 PMU_PMEVTYPER_EL0(17), 2961 PMU_PMEVTYPER_EL0(18), 2962 PMU_PMEVTYPER_EL0(19), 2963 PMU_PMEVTYPER_EL0(20), 2964 PMU_PMEVTYPER_EL0(21), 2965 PMU_PMEVTYPER_EL0(22), 2966 PMU_PMEVTYPER_EL0(23), 2967 PMU_PMEVTYPER_EL0(24), 2968 PMU_PMEVTYPER_EL0(25), 2969 PMU_PMEVTYPER_EL0(26), 2970 PMU_PMEVTYPER_EL0(27), 2971 PMU_PMEVTYPER_EL0(28), 2972 PMU_PMEVTYPER_EL0(29), 2973 PMU_PMEVTYPER_EL0(30), 2974 /* 2975 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero 2976 * in 32bit mode. Here we choose to reset it as zero for consistency. 2977 */ 2978 { PMU_SYS_REG(PMCCFILTR_EL0), .access = access_pmu_evtyper, 2979 .reset = reset_val, .reg = PMCCFILTR_EL0, .val = 0 }, 2980 2981 EL2_REG_VNCR(VPIDR_EL2, reset_unknown, 0), 2982 EL2_REG_VNCR(VMPIDR_EL2, reset_unknown, 0), 2983 EL2_REG(SCTLR_EL2, access_rw, reset_val, SCTLR_EL2_RES1), 2984 EL2_REG(ACTLR_EL2, access_rw, reset_val, 0), 2985 EL2_REG_VNCR(HCR_EL2, reset_hcr, 0), 2986 EL2_REG(MDCR_EL2, access_rw, reset_val, 0), 2987 EL2_REG(CPTR_EL2, access_rw, reset_val, CPTR_NVHE_EL2_RES1), 2988 EL2_REG_VNCR(HSTR_EL2, reset_val, 0), 2989 EL2_REG_VNCR(HFGRTR_EL2, reset_val, 0), 2990 EL2_REG_VNCR(HFGWTR_EL2, reset_val, 0), 2991 EL2_REG_VNCR(HFGITR_EL2, reset_val, 0), 2992 EL2_REG_VNCR(HACR_EL2, reset_val, 0), 2993 2994 EL2_REG_FILTERED(ZCR_EL2, access_zcr_el2, reset_val, 0, 2995 sve_el2_visibility), 2996 2997 EL2_REG_VNCR(HCRX_EL2, reset_val, 0), 2998 2999 EL2_REG(TTBR0_EL2, access_rw, reset_val, 0), 3000 EL2_REG(TTBR1_EL2, access_rw, reset_val, 0), 3001 EL2_REG(TCR_EL2, access_rw, reset_val, TCR_EL2_RES1), 3002 EL2_REG_FILTERED(TCR2_EL2, access_rw, reset_val, TCR2_EL2_RES1, 3003 tcr2_el2_visibility), 3004 EL2_REG_VNCR(VTTBR_EL2, reset_val, 0), 3005 EL2_REG_VNCR(VTCR_EL2, reset_val, 0), 3006 3007 { SYS_DESC(SYS_DACR32_EL2), undef_access, reset_unknown, DACR32_EL2 }, 3008 EL2_REG_VNCR(HDFGRTR_EL2, reset_val, 0), 3009 EL2_REG_VNCR(HDFGWTR_EL2, reset_val, 0), 3010 EL2_REG_VNCR(HAFGRTR_EL2, reset_val, 0), 3011 EL2_REG_REDIR(SPSR_EL2, reset_val, 0), 3012 EL2_REG_REDIR(ELR_EL2, reset_val, 0), 3013 { SYS_DESC(SYS_SP_EL1), access_sp_el1}, 3014 3015 /* AArch32 SPSR_* are RES0 if trapped from a NV guest */ 3016 { SYS_DESC(SYS_SPSR_irq), .access = trap_raz_wi }, 3017 { SYS_DESC(SYS_SPSR_abt), .access = trap_raz_wi }, 3018 { SYS_DESC(SYS_SPSR_und), .access = trap_raz_wi }, 3019 { SYS_DESC(SYS_SPSR_fiq), .access = trap_raz_wi }, 3020 3021 { SYS_DESC(SYS_IFSR32_EL2), undef_access, reset_unknown, IFSR32_EL2 }, 3022 EL2_REG(AFSR0_EL2, access_rw, reset_val, 0), 3023 EL2_REG(AFSR1_EL2, access_rw, reset_val, 0), 3024 EL2_REG_REDIR(ESR_EL2, reset_val, 0), 3025 { SYS_DESC(SYS_FPEXC32_EL2), undef_access, reset_val, FPEXC32_EL2, 0x700 }, 3026 3027 EL2_REG_REDIR(FAR_EL2, reset_val, 0), 3028 EL2_REG(HPFAR_EL2, access_rw, reset_val, 0), 3029 3030 EL2_REG(MAIR_EL2, access_rw, reset_val, 0), 3031 EL2_REG_FILTERED(PIRE0_EL2, access_rw, reset_val, 0, 3032 s1pie_el2_visibility), 3033 EL2_REG_FILTERED(PIR_EL2, access_rw, reset_val, 0, 3034 s1pie_el2_visibility), 3035 EL2_REG_FILTERED(POR_EL2, access_rw, reset_val, 0, 3036 s1poe_el2_visibility), 3037 EL2_REG(AMAIR_EL2, access_rw, reset_val, 0), 3038 { SYS_DESC(SYS_MPAMHCR_EL2), undef_access }, 3039 { SYS_DESC(SYS_MPAMVPMV_EL2), undef_access }, 3040 { SYS_DESC(SYS_MPAM2_EL2), undef_access }, 3041 { SYS_DESC(SYS_MPAMVPM0_EL2), undef_access }, 3042 { SYS_DESC(SYS_MPAMVPM1_EL2), undef_access }, 3043 { SYS_DESC(SYS_MPAMVPM2_EL2), undef_access }, 3044 { SYS_DESC(SYS_MPAMVPM3_EL2), undef_access }, 3045 { SYS_DESC(SYS_MPAMVPM4_EL2), undef_access }, 3046 { SYS_DESC(SYS_MPAMVPM5_EL2), undef_access }, 3047 { SYS_DESC(SYS_MPAMVPM6_EL2), undef_access }, 3048 { SYS_DESC(SYS_MPAMVPM7_EL2), undef_access }, 3049 3050 EL2_REG(VBAR_EL2, access_rw, reset_val, 0), 3051 EL2_REG(RVBAR_EL2, access_rw, reset_val, 0), 3052 { SYS_DESC(SYS_RMR_EL2), undef_access }, 3053 3054 EL2_REG_VNCR(ICH_HCR_EL2, reset_val, 0), 3055 3056 EL2_REG(CONTEXTIDR_EL2, access_rw, reset_val, 0), 3057 EL2_REG(TPIDR_EL2, access_rw, reset_val, 0), 3058 3059 EL2_REG_VNCR(CNTVOFF_EL2, reset_val, 0), 3060 EL2_REG(CNTHCTL_EL2, access_rw, reset_val, 0), 3061 3062 { SYS_DESC(SYS_CNTKCTL_EL12), access_cntkctl_el12 }, 3063 3064 EL2_REG(SP_EL2, NULL, reset_unknown, 0), 3065 }; 3066 3067 static bool handle_at_s1e01(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3068 const struct sys_reg_desc *r) 3069 { 3070 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3071 3072 __kvm_at_s1e01(vcpu, op, p->regval); 3073 3074 return true; 3075 } 3076 3077 static bool handle_at_s1e2(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3078 const struct sys_reg_desc *r) 3079 { 3080 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3081 3082 /* There is no FGT associated with AT S1E2A :-( */ 3083 if (op == OP_AT_S1E2A && 3084 !kvm_has_feat(vcpu->kvm, ID_AA64ISAR2_EL1, ATS1A, IMP)) { 3085 kvm_inject_undefined(vcpu); 3086 return false; 3087 } 3088 3089 __kvm_at_s1e2(vcpu, op, p->regval); 3090 3091 return true; 3092 } 3093 3094 static bool handle_at_s12(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3095 const struct sys_reg_desc *r) 3096 { 3097 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3098 3099 __kvm_at_s12(vcpu, op, p->regval); 3100 3101 return true; 3102 } 3103 3104 static bool kvm_supported_tlbi_s12_op(struct kvm_vcpu *vpcu, u32 instr) 3105 { 3106 struct kvm *kvm = vpcu->kvm; 3107 u8 CRm = sys_reg_CRm(instr); 3108 3109 if (sys_reg_CRn(instr) == TLBI_CRn_nXS && 3110 !kvm_has_feat(kvm, ID_AA64ISAR1_EL1, XS, IMP)) 3111 return false; 3112 3113 if (CRm == TLBI_CRm_nROS && 3114 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 3115 return false; 3116 3117 return true; 3118 } 3119 3120 static bool handle_alle1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3121 const struct sys_reg_desc *r) 3122 { 3123 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3124 3125 if (!kvm_supported_tlbi_s12_op(vcpu, sys_encoding)) 3126 return undef_access(vcpu, p, r); 3127 3128 write_lock(&vcpu->kvm->mmu_lock); 3129 3130 /* 3131 * Drop all shadow S2s, resulting in S1/S2 TLBIs for each of the 3132 * corresponding VMIDs. 3133 */ 3134 kvm_nested_s2_unmap(vcpu->kvm, true); 3135 3136 write_unlock(&vcpu->kvm->mmu_lock); 3137 3138 return true; 3139 } 3140 3141 static bool kvm_supported_tlbi_ipas2_op(struct kvm_vcpu *vpcu, u32 instr) 3142 { 3143 struct kvm *kvm = vpcu->kvm; 3144 u8 CRm = sys_reg_CRm(instr); 3145 u8 Op2 = sys_reg_Op2(instr); 3146 3147 if (sys_reg_CRn(instr) == TLBI_CRn_nXS && 3148 !kvm_has_feat(kvm, ID_AA64ISAR1_EL1, XS, IMP)) 3149 return false; 3150 3151 if (CRm == TLBI_CRm_IPAIS && (Op2 == 2 || Op2 == 6) && 3152 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE)) 3153 return false; 3154 3155 if (CRm == TLBI_CRm_IPAONS && (Op2 == 0 || Op2 == 4) && 3156 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 3157 return false; 3158 3159 if (CRm == TLBI_CRm_IPAONS && (Op2 == 3 || Op2 == 7) && 3160 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE)) 3161 return false; 3162 3163 return true; 3164 } 3165 3166 /* Only defined here as this is an internal "abstraction" */ 3167 union tlbi_info { 3168 struct { 3169 u64 start; 3170 u64 size; 3171 } range; 3172 3173 struct { 3174 u64 addr; 3175 } ipa; 3176 3177 struct { 3178 u64 addr; 3179 u32 encoding; 3180 } va; 3181 }; 3182 3183 static void s2_mmu_unmap_range(struct kvm_s2_mmu *mmu, 3184 const union tlbi_info *info) 3185 { 3186 /* 3187 * The unmap operation is allowed to drop the MMU lock and block, which 3188 * means that @mmu could be used for a different context than the one 3189 * currently being invalidated. 3190 * 3191 * This behavior is still safe, as: 3192 * 3193 * 1) The vCPU(s) that recycled the MMU are responsible for invalidating 3194 * the entire MMU before reusing it, which still honors the intent 3195 * of a TLBI. 3196 * 3197 * 2) Until the guest TLBI instruction is 'retired' (i.e. increment PC 3198 * and ERET to the guest), other vCPUs are allowed to use stale 3199 * translations. 3200 * 3201 * 3) Accidentally unmapping an unrelated MMU context is nonfatal, and 3202 * at worst may cause more aborts for shadow stage-2 fills. 3203 * 3204 * Dropping the MMU lock also implies that shadow stage-2 fills could 3205 * happen behind the back of the TLBI. This is still safe, though, as 3206 * the L1 needs to put its stage-2 in a consistent state before doing 3207 * the TLBI. 3208 */ 3209 kvm_stage2_unmap_range(mmu, info->range.start, info->range.size, true); 3210 } 3211 3212 static bool handle_vmalls12e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3213 const struct sys_reg_desc *r) 3214 { 3215 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3216 u64 limit, vttbr; 3217 3218 if (!kvm_supported_tlbi_s12_op(vcpu, sys_encoding)) 3219 return undef_access(vcpu, p, r); 3220 3221 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 3222 limit = BIT_ULL(kvm_get_pa_bits(vcpu->kvm)); 3223 3224 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 3225 &(union tlbi_info) { 3226 .range = { 3227 .start = 0, 3228 .size = limit, 3229 }, 3230 }, 3231 s2_mmu_unmap_range); 3232 3233 return true; 3234 } 3235 3236 static bool handle_ripas2e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3237 const struct sys_reg_desc *r) 3238 { 3239 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3240 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 3241 u64 base, range, tg, num, scale; 3242 int shift; 3243 3244 if (!kvm_supported_tlbi_ipas2_op(vcpu, sys_encoding)) 3245 return undef_access(vcpu, p, r); 3246 3247 /* 3248 * Because the shadow S2 structure doesn't necessarily reflect that 3249 * of the guest's S2 (different base granule size, for example), we 3250 * decide to ignore TTL and only use the described range. 3251 */ 3252 tg = FIELD_GET(GENMASK(47, 46), p->regval); 3253 scale = FIELD_GET(GENMASK(45, 44), p->regval); 3254 num = FIELD_GET(GENMASK(43, 39), p->regval); 3255 base = p->regval & GENMASK(36, 0); 3256 3257 switch(tg) { 3258 case 1: 3259 shift = 12; 3260 break; 3261 case 2: 3262 shift = 14; 3263 break; 3264 case 3: 3265 default: /* IMPDEF: handle tg==0 as 64k */ 3266 shift = 16; 3267 break; 3268 } 3269 3270 base <<= shift; 3271 range = __TLBI_RANGE_PAGES(num, scale) << shift; 3272 3273 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 3274 &(union tlbi_info) { 3275 .range = { 3276 .start = base, 3277 .size = range, 3278 }, 3279 }, 3280 s2_mmu_unmap_range); 3281 3282 return true; 3283 } 3284 3285 static void s2_mmu_unmap_ipa(struct kvm_s2_mmu *mmu, 3286 const union tlbi_info *info) 3287 { 3288 unsigned long max_size; 3289 u64 base_addr; 3290 3291 /* 3292 * We drop a number of things from the supplied value: 3293 * 3294 * - NS bit: we're non-secure only. 3295 * 3296 * - IPA[51:48]: We don't support 52bit IPA just yet... 3297 * 3298 * And of course, adjust the IPA to be on an actual address. 3299 */ 3300 base_addr = (info->ipa.addr & GENMASK_ULL(35, 0)) << 12; 3301 max_size = compute_tlb_inval_range(mmu, info->ipa.addr); 3302 base_addr &= ~(max_size - 1); 3303 3304 /* 3305 * See comment in s2_mmu_unmap_range() for why this is allowed to 3306 * reschedule. 3307 */ 3308 kvm_stage2_unmap_range(mmu, base_addr, max_size, true); 3309 } 3310 3311 static bool handle_ipas2e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3312 const struct sys_reg_desc *r) 3313 { 3314 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3315 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 3316 3317 if (!kvm_supported_tlbi_ipas2_op(vcpu, sys_encoding)) 3318 return undef_access(vcpu, p, r); 3319 3320 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 3321 &(union tlbi_info) { 3322 .ipa = { 3323 .addr = p->regval, 3324 }, 3325 }, 3326 s2_mmu_unmap_ipa); 3327 3328 return true; 3329 } 3330 3331 static void s2_mmu_tlbi_s1e1(struct kvm_s2_mmu *mmu, 3332 const union tlbi_info *info) 3333 { 3334 WARN_ON(__kvm_tlbi_s1e2(mmu, info->va.addr, info->va.encoding)); 3335 } 3336 3337 static bool handle_tlbi_el1(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3338 const struct sys_reg_desc *r) 3339 { 3340 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3341 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 3342 3343 /* 3344 * If we're here, this is because we've trapped on a EL1 TLBI 3345 * instruction that affects the EL1 translation regime while 3346 * we're running in a context that doesn't allow us to let the 3347 * HW do its thing (aka vEL2): 3348 * 3349 * - HCR_EL2.E2H == 0 : a non-VHE guest 3350 * - HCR_EL2.{E2H,TGE} == { 1, 0 } : a VHE guest in guest mode 3351 * 3352 * We don't expect these helpers to ever be called when running 3353 * in a vEL1 context. 3354 */ 3355 3356 WARN_ON(!vcpu_is_el2(vcpu)); 3357 3358 if (!kvm_supported_tlbi_s1e1_op(vcpu, sys_encoding)) 3359 return undef_access(vcpu, p, r); 3360 3361 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 3362 &(union tlbi_info) { 3363 .va = { 3364 .addr = p->regval, 3365 .encoding = sys_encoding, 3366 }, 3367 }, 3368 s2_mmu_tlbi_s1e1); 3369 3370 return true; 3371 } 3372 3373 #define SYS_INSN(insn, access_fn) \ 3374 { \ 3375 SYS_DESC(OP_##insn), \ 3376 .access = (access_fn), \ 3377 } 3378 3379 static struct sys_reg_desc sys_insn_descs[] = { 3380 { SYS_DESC(SYS_DC_ISW), access_dcsw }, 3381 { SYS_DESC(SYS_DC_IGSW), access_dcgsw }, 3382 { SYS_DESC(SYS_DC_IGDSW), access_dcgsw }, 3383 3384 SYS_INSN(AT_S1E1R, handle_at_s1e01), 3385 SYS_INSN(AT_S1E1W, handle_at_s1e01), 3386 SYS_INSN(AT_S1E0R, handle_at_s1e01), 3387 SYS_INSN(AT_S1E0W, handle_at_s1e01), 3388 SYS_INSN(AT_S1E1RP, handle_at_s1e01), 3389 SYS_INSN(AT_S1E1WP, handle_at_s1e01), 3390 3391 { SYS_DESC(SYS_DC_CSW), access_dcsw }, 3392 { SYS_DESC(SYS_DC_CGSW), access_dcgsw }, 3393 { SYS_DESC(SYS_DC_CGDSW), access_dcgsw }, 3394 { SYS_DESC(SYS_DC_CISW), access_dcsw }, 3395 { SYS_DESC(SYS_DC_CIGSW), access_dcgsw }, 3396 { SYS_DESC(SYS_DC_CIGDSW), access_dcgsw }, 3397 3398 SYS_INSN(TLBI_VMALLE1OS, handle_tlbi_el1), 3399 SYS_INSN(TLBI_VAE1OS, handle_tlbi_el1), 3400 SYS_INSN(TLBI_ASIDE1OS, handle_tlbi_el1), 3401 SYS_INSN(TLBI_VAAE1OS, handle_tlbi_el1), 3402 SYS_INSN(TLBI_VALE1OS, handle_tlbi_el1), 3403 SYS_INSN(TLBI_VAALE1OS, handle_tlbi_el1), 3404 3405 SYS_INSN(TLBI_RVAE1IS, handle_tlbi_el1), 3406 SYS_INSN(TLBI_RVAAE1IS, handle_tlbi_el1), 3407 SYS_INSN(TLBI_RVALE1IS, handle_tlbi_el1), 3408 SYS_INSN(TLBI_RVAALE1IS, handle_tlbi_el1), 3409 3410 SYS_INSN(TLBI_VMALLE1IS, handle_tlbi_el1), 3411 SYS_INSN(TLBI_VAE1IS, handle_tlbi_el1), 3412 SYS_INSN(TLBI_ASIDE1IS, handle_tlbi_el1), 3413 SYS_INSN(TLBI_VAAE1IS, handle_tlbi_el1), 3414 SYS_INSN(TLBI_VALE1IS, handle_tlbi_el1), 3415 SYS_INSN(TLBI_VAALE1IS, handle_tlbi_el1), 3416 3417 SYS_INSN(TLBI_RVAE1OS, handle_tlbi_el1), 3418 SYS_INSN(TLBI_RVAAE1OS, handle_tlbi_el1), 3419 SYS_INSN(TLBI_RVALE1OS, handle_tlbi_el1), 3420 SYS_INSN(TLBI_RVAALE1OS, handle_tlbi_el1), 3421 3422 SYS_INSN(TLBI_RVAE1, handle_tlbi_el1), 3423 SYS_INSN(TLBI_RVAAE1, handle_tlbi_el1), 3424 SYS_INSN(TLBI_RVALE1, handle_tlbi_el1), 3425 SYS_INSN(TLBI_RVAALE1, handle_tlbi_el1), 3426 3427 SYS_INSN(TLBI_VMALLE1, handle_tlbi_el1), 3428 SYS_INSN(TLBI_VAE1, handle_tlbi_el1), 3429 SYS_INSN(TLBI_ASIDE1, handle_tlbi_el1), 3430 SYS_INSN(TLBI_VAAE1, handle_tlbi_el1), 3431 SYS_INSN(TLBI_VALE1, handle_tlbi_el1), 3432 SYS_INSN(TLBI_VAALE1, handle_tlbi_el1), 3433 3434 SYS_INSN(TLBI_VMALLE1OSNXS, handle_tlbi_el1), 3435 SYS_INSN(TLBI_VAE1OSNXS, handle_tlbi_el1), 3436 SYS_INSN(TLBI_ASIDE1OSNXS, handle_tlbi_el1), 3437 SYS_INSN(TLBI_VAAE1OSNXS, handle_tlbi_el1), 3438 SYS_INSN(TLBI_VALE1OSNXS, handle_tlbi_el1), 3439 SYS_INSN(TLBI_VAALE1OSNXS, handle_tlbi_el1), 3440 3441 SYS_INSN(TLBI_RVAE1ISNXS, handle_tlbi_el1), 3442 SYS_INSN(TLBI_RVAAE1ISNXS, handle_tlbi_el1), 3443 SYS_INSN(TLBI_RVALE1ISNXS, handle_tlbi_el1), 3444 SYS_INSN(TLBI_RVAALE1ISNXS, handle_tlbi_el1), 3445 3446 SYS_INSN(TLBI_VMALLE1ISNXS, handle_tlbi_el1), 3447 SYS_INSN(TLBI_VAE1ISNXS, handle_tlbi_el1), 3448 SYS_INSN(TLBI_ASIDE1ISNXS, handle_tlbi_el1), 3449 SYS_INSN(TLBI_VAAE1ISNXS, handle_tlbi_el1), 3450 SYS_INSN(TLBI_VALE1ISNXS, handle_tlbi_el1), 3451 SYS_INSN(TLBI_VAALE1ISNXS, handle_tlbi_el1), 3452 3453 SYS_INSN(TLBI_RVAE1OSNXS, handle_tlbi_el1), 3454 SYS_INSN(TLBI_RVAAE1OSNXS, handle_tlbi_el1), 3455 SYS_INSN(TLBI_RVALE1OSNXS, handle_tlbi_el1), 3456 SYS_INSN(TLBI_RVAALE1OSNXS, handle_tlbi_el1), 3457 3458 SYS_INSN(TLBI_RVAE1NXS, handle_tlbi_el1), 3459 SYS_INSN(TLBI_RVAAE1NXS, handle_tlbi_el1), 3460 SYS_INSN(TLBI_RVALE1NXS, handle_tlbi_el1), 3461 SYS_INSN(TLBI_RVAALE1NXS, handle_tlbi_el1), 3462 3463 SYS_INSN(TLBI_VMALLE1NXS, handle_tlbi_el1), 3464 SYS_INSN(TLBI_VAE1NXS, handle_tlbi_el1), 3465 SYS_INSN(TLBI_ASIDE1NXS, handle_tlbi_el1), 3466 SYS_INSN(TLBI_VAAE1NXS, handle_tlbi_el1), 3467 SYS_INSN(TLBI_VALE1NXS, handle_tlbi_el1), 3468 SYS_INSN(TLBI_VAALE1NXS, handle_tlbi_el1), 3469 3470 SYS_INSN(AT_S1E2R, handle_at_s1e2), 3471 SYS_INSN(AT_S1E2W, handle_at_s1e2), 3472 SYS_INSN(AT_S12E1R, handle_at_s12), 3473 SYS_INSN(AT_S12E1W, handle_at_s12), 3474 SYS_INSN(AT_S12E0R, handle_at_s12), 3475 SYS_INSN(AT_S12E0W, handle_at_s12), 3476 SYS_INSN(AT_S1E2A, handle_at_s1e2), 3477 3478 SYS_INSN(TLBI_IPAS2E1IS, handle_ipas2e1is), 3479 SYS_INSN(TLBI_RIPAS2E1IS, handle_ripas2e1is), 3480 SYS_INSN(TLBI_IPAS2LE1IS, handle_ipas2e1is), 3481 SYS_INSN(TLBI_RIPAS2LE1IS, handle_ripas2e1is), 3482 3483 SYS_INSN(TLBI_ALLE2OS, undef_access), 3484 SYS_INSN(TLBI_VAE2OS, undef_access), 3485 SYS_INSN(TLBI_ALLE1OS, handle_alle1is), 3486 SYS_INSN(TLBI_VALE2OS, undef_access), 3487 SYS_INSN(TLBI_VMALLS12E1OS, handle_vmalls12e1is), 3488 3489 SYS_INSN(TLBI_RVAE2IS, undef_access), 3490 SYS_INSN(TLBI_RVALE2IS, undef_access), 3491 3492 SYS_INSN(TLBI_ALLE1IS, handle_alle1is), 3493 SYS_INSN(TLBI_VMALLS12E1IS, handle_vmalls12e1is), 3494 SYS_INSN(TLBI_IPAS2E1OS, handle_ipas2e1is), 3495 SYS_INSN(TLBI_IPAS2E1, handle_ipas2e1is), 3496 SYS_INSN(TLBI_RIPAS2E1, handle_ripas2e1is), 3497 SYS_INSN(TLBI_RIPAS2E1OS, handle_ripas2e1is), 3498 SYS_INSN(TLBI_IPAS2LE1OS, handle_ipas2e1is), 3499 SYS_INSN(TLBI_IPAS2LE1, handle_ipas2e1is), 3500 SYS_INSN(TLBI_RIPAS2LE1, handle_ripas2e1is), 3501 SYS_INSN(TLBI_RIPAS2LE1OS, handle_ripas2e1is), 3502 SYS_INSN(TLBI_RVAE2OS, undef_access), 3503 SYS_INSN(TLBI_RVALE2OS, undef_access), 3504 SYS_INSN(TLBI_RVAE2, undef_access), 3505 SYS_INSN(TLBI_RVALE2, undef_access), 3506 SYS_INSN(TLBI_ALLE1, handle_alle1is), 3507 SYS_INSN(TLBI_VMALLS12E1, handle_vmalls12e1is), 3508 3509 SYS_INSN(TLBI_IPAS2E1ISNXS, handle_ipas2e1is), 3510 SYS_INSN(TLBI_RIPAS2E1ISNXS, handle_ripas2e1is), 3511 SYS_INSN(TLBI_IPAS2LE1ISNXS, handle_ipas2e1is), 3512 SYS_INSN(TLBI_RIPAS2LE1ISNXS, handle_ripas2e1is), 3513 3514 SYS_INSN(TLBI_ALLE2OSNXS, undef_access), 3515 SYS_INSN(TLBI_VAE2OSNXS, undef_access), 3516 SYS_INSN(TLBI_ALLE1OSNXS, handle_alle1is), 3517 SYS_INSN(TLBI_VALE2OSNXS, undef_access), 3518 SYS_INSN(TLBI_VMALLS12E1OSNXS, handle_vmalls12e1is), 3519 3520 SYS_INSN(TLBI_RVAE2ISNXS, undef_access), 3521 SYS_INSN(TLBI_RVALE2ISNXS, undef_access), 3522 SYS_INSN(TLBI_ALLE2ISNXS, undef_access), 3523 SYS_INSN(TLBI_VAE2ISNXS, undef_access), 3524 3525 SYS_INSN(TLBI_ALLE1ISNXS, handle_alle1is), 3526 SYS_INSN(TLBI_VALE2ISNXS, undef_access), 3527 SYS_INSN(TLBI_VMALLS12E1ISNXS, handle_vmalls12e1is), 3528 SYS_INSN(TLBI_IPAS2E1OSNXS, handle_ipas2e1is), 3529 SYS_INSN(TLBI_IPAS2E1NXS, handle_ipas2e1is), 3530 SYS_INSN(TLBI_RIPAS2E1NXS, handle_ripas2e1is), 3531 SYS_INSN(TLBI_RIPAS2E1OSNXS, handle_ripas2e1is), 3532 SYS_INSN(TLBI_IPAS2LE1OSNXS, handle_ipas2e1is), 3533 SYS_INSN(TLBI_IPAS2LE1NXS, handle_ipas2e1is), 3534 SYS_INSN(TLBI_RIPAS2LE1NXS, handle_ripas2e1is), 3535 SYS_INSN(TLBI_RIPAS2LE1OSNXS, handle_ripas2e1is), 3536 SYS_INSN(TLBI_RVAE2OSNXS, undef_access), 3537 SYS_INSN(TLBI_RVALE2OSNXS, undef_access), 3538 SYS_INSN(TLBI_RVAE2NXS, undef_access), 3539 SYS_INSN(TLBI_RVALE2NXS, undef_access), 3540 SYS_INSN(TLBI_ALLE2NXS, undef_access), 3541 SYS_INSN(TLBI_VAE2NXS, undef_access), 3542 SYS_INSN(TLBI_ALLE1NXS, handle_alle1is), 3543 SYS_INSN(TLBI_VALE2NXS, undef_access), 3544 SYS_INSN(TLBI_VMALLS12E1NXS, handle_vmalls12e1is), 3545 }; 3546 3547 static bool trap_dbgdidr(struct kvm_vcpu *vcpu, 3548 struct sys_reg_params *p, 3549 const struct sys_reg_desc *r) 3550 { 3551 if (p->is_write) { 3552 return ignore_write(vcpu, p); 3553 } else { 3554 u64 dfr = kvm_read_vm_id_reg(vcpu->kvm, SYS_ID_AA64DFR0_EL1); 3555 u32 el3 = kvm_has_feat(vcpu->kvm, ID_AA64PFR0_EL1, EL3, IMP); 3556 3557 p->regval = ((SYS_FIELD_GET(ID_AA64DFR0_EL1, WRPs, dfr) << 28) | 3558 (SYS_FIELD_GET(ID_AA64DFR0_EL1, BRPs, dfr) << 24) | 3559 (SYS_FIELD_GET(ID_AA64DFR0_EL1, CTX_CMPs, dfr) << 20) | 3560 (SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, dfr) << 16) | 3561 (1 << 15) | (el3 << 14) | (el3 << 12)); 3562 return true; 3563 } 3564 } 3565 3566 /* 3567 * AArch32 debug register mappings 3568 * 3569 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0] 3570 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32] 3571 * 3572 * None of the other registers share their location, so treat them as 3573 * if they were 64bit. 3574 */ 3575 #define DBG_BCR_BVR_WCR_WVR(n) \ 3576 /* DBGBVRn */ \ 3577 { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \ 3578 /* DBGBCRn */ \ 3579 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \ 3580 /* DBGWVRn */ \ 3581 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \ 3582 /* DBGWCRn */ \ 3583 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n } 3584 3585 #define DBGBXVR(n) \ 3586 { AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_bvr, NULL, n } 3587 3588 /* 3589 * Trapped cp14 registers. We generally ignore most of the external 3590 * debug, on the principle that they don't really make sense to a 3591 * guest. Revisit this one day, would this principle change. 3592 */ 3593 static const struct sys_reg_desc cp14_regs[] = { 3594 /* DBGDIDR */ 3595 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgdidr }, 3596 /* DBGDTRRXext */ 3597 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi }, 3598 3599 DBG_BCR_BVR_WCR_WVR(0), 3600 /* DBGDSCRint */ 3601 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi }, 3602 DBG_BCR_BVR_WCR_WVR(1), 3603 /* DBGDCCINT */ 3604 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug_regs, NULL, MDCCINT_EL1 }, 3605 /* DBGDSCRext */ 3606 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug_regs, NULL, MDSCR_EL1 }, 3607 DBG_BCR_BVR_WCR_WVR(2), 3608 /* DBGDTR[RT]Xint */ 3609 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi }, 3610 /* DBGDTR[RT]Xext */ 3611 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi }, 3612 DBG_BCR_BVR_WCR_WVR(3), 3613 DBG_BCR_BVR_WCR_WVR(4), 3614 DBG_BCR_BVR_WCR_WVR(5), 3615 /* DBGWFAR */ 3616 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi }, 3617 /* DBGOSECCR */ 3618 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi }, 3619 DBG_BCR_BVR_WCR_WVR(6), 3620 /* DBGVCR */ 3621 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug_regs, NULL, DBGVCR32_EL2 }, 3622 DBG_BCR_BVR_WCR_WVR(7), 3623 DBG_BCR_BVR_WCR_WVR(8), 3624 DBG_BCR_BVR_WCR_WVR(9), 3625 DBG_BCR_BVR_WCR_WVR(10), 3626 DBG_BCR_BVR_WCR_WVR(11), 3627 DBG_BCR_BVR_WCR_WVR(12), 3628 DBG_BCR_BVR_WCR_WVR(13), 3629 DBG_BCR_BVR_WCR_WVR(14), 3630 DBG_BCR_BVR_WCR_WVR(15), 3631 3632 /* DBGDRAR (32bit) */ 3633 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi }, 3634 3635 DBGBXVR(0), 3636 /* DBGOSLAR */ 3637 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_oslar_el1 }, 3638 DBGBXVR(1), 3639 /* DBGOSLSR */ 3640 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1, NULL, OSLSR_EL1 }, 3641 DBGBXVR(2), 3642 DBGBXVR(3), 3643 /* DBGOSDLR */ 3644 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi }, 3645 DBGBXVR(4), 3646 /* DBGPRCR */ 3647 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi }, 3648 DBGBXVR(5), 3649 DBGBXVR(6), 3650 DBGBXVR(7), 3651 DBGBXVR(8), 3652 DBGBXVR(9), 3653 DBGBXVR(10), 3654 DBGBXVR(11), 3655 DBGBXVR(12), 3656 DBGBXVR(13), 3657 DBGBXVR(14), 3658 DBGBXVR(15), 3659 3660 /* DBGDSAR (32bit) */ 3661 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi }, 3662 3663 /* DBGDEVID2 */ 3664 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi }, 3665 /* DBGDEVID1 */ 3666 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi }, 3667 /* DBGDEVID */ 3668 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi }, 3669 /* DBGCLAIMSET */ 3670 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi }, 3671 /* DBGCLAIMCLR */ 3672 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi }, 3673 /* DBGAUTHSTATUS */ 3674 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 }, 3675 }; 3676 3677 /* Trapped cp14 64bit registers */ 3678 static const struct sys_reg_desc cp14_64_regs[] = { 3679 /* DBGDRAR (64bit) */ 3680 { Op1( 0), CRm( 1), .access = trap_raz_wi }, 3681 3682 /* DBGDSAR (64bit) */ 3683 { Op1( 0), CRm( 2), .access = trap_raz_wi }, 3684 }; 3685 3686 #define CP15_PMU_SYS_REG(_map, _Op1, _CRn, _CRm, _Op2) \ 3687 AA32(_map), \ 3688 Op1(_Op1), CRn(_CRn), CRm(_CRm), Op2(_Op2), \ 3689 .visibility = pmu_visibility 3690 3691 /* Macro to expand the PMEVCNTRn register */ 3692 #define PMU_PMEVCNTR(n) \ 3693 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \ 3694 (0b1000 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \ 3695 .access = access_pmu_evcntr } 3696 3697 /* Macro to expand the PMEVTYPERn register */ 3698 #define PMU_PMEVTYPER(n) \ 3699 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \ 3700 (0b1100 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \ 3701 .access = access_pmu_evtyper } 3702 /* 3703 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding, 3704 * depending on the way they are accessed (as a 32bit or a 64bit 3705 * register). 3706 */ 3707 static const struct sys_reg_desc cp15_regs[] = { 3708 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr }, 3709 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, SCTLR_EL1 }, 3710 /* ACTLR */ 3711 { AA32(LO), Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr, NULL, ACTLR_EL1 }, 3712 /* ACTLR2 */ 3713 { AA32(HI), Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr, NULL, ACTLR_EL1 }, 3714 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, 3715 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, TTBR1_EL1 }, 3716 /* TTBCR */ 3717 { AA32(LO), Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 }, 3718 /* TTBCR2 */ 3719 { AA32(HI), Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, TCR_EL1 }, 3720 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, DACR32_EL2 }, 3721 { CP15_SYS_DESC(SYS_ICC_PMR_EL1), undef_access }, 3722 /* DFSR */ 3723 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, ESR_EL1 }, 3724 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, IFSR32_EL2 }, 3725 /* ADFSR */ 3726 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, AFSR0_EL1 }, 3727 /* AIFSR */ 3728 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, AFSR1_EL1 }, 3729 /* DFAR */ 3730 { AA32(LO), Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, FAR_EL1 }, 3731 /* IFAR */ 3732 { AA32(HI), Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, FAR_EL1 }, 3733 3734 /* 3735 * DC{C,I,CI}SW operations: 3736 */ 3737 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw }, 3738 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw }, 3739 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw }, 3740 3741 /* PMU */ 3742 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 0), .access = access_pmcr }, 3743 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 1), .access = access_pmcnten }, 3744 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 2), .access = access_pmcnten }, 3745 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 3), .access = access_pmovs }, 3746 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 4), .access = access_pmswinc }, 3747 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 5), .access = access_pmselr }, 3748 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 6), .access = access_pmceid }, 3749 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 7), .access = access_pmceid }, 3750 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 0), .access = access_pmu_evcntr }, 3751 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 1), .access = access_pmu_evtyper }, 3752 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 2), .access = access_pmu_evcntr }, 3753 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 0), .access = access_pmuserenr }, 3754 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 1), .access = access_pminten }, 3755 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 2), .access = access_pminten }, 3756 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 3), .access = access_pmovs }, 3757 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 4), .access = access_pmceid }, 3758 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 5), .access = access_pmceid }, 3759 /* PMMIR */ 3760 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 6), .access = trap_raz_wi }, 3761 3762 /* PRRR/MAIR0 */ 3763 { AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 }, 3764 /* NMRR/MAIR1 */ 3765 { AA32(HI), Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, MAIR_EL1 }, 3766 /* AMAIR0 */ 3767 { AA32(LO), Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, AMAIR_EL1 }, 3768 /* AMAIR1 */ 3769 { AA32(HI), Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, AMAIR_EL1 }, 3770 3771 { CP15_SYS_DESC(SYS_ICC_IAR0_EL1), undef_access }, 3772 { CP15_SYS_DESC(SYS_ICC_EOIR0_EL1), undef_access }, 3773 { CP15_SYS_DESC(SYS_ICC_HPPIR0_EL1), undef_access }, 3774 { CP15_SYS_DESC(SYS_ICC_BPR0_EL1), undef_access }, 3775 { CP15_SYS_DESC(SYS_ICC_AP0R0_EL1), undef_access }, 3776 { CP15_SYS_DESC(SYS_ICC_AP0R1_EL1), undef_access }, 3777 { CP15_SYS_DESC(SYS_ICC_AP0R2_EL1), undef_access }, 3778 { CP15_SYS_DESC(SYS_ICC_AP0R3_EL1), undef_access }, 3779 { CP15_SYS_DESC(SYS_ICC_AP1R0_EL1), undef_access }, 3780 { CP15_SYS_DESC(SYS_ICC_AP1R1_EL1), undef_access }, 3781 { CP15_SYS_DESC(SYS_ICC_AP1R2_EL1), undef_access }, 3782 { CP15_SYS_DESC(SYS_ICC_AP1R3_EL1), undef_access }, 3783 { CP15_SYS_DESC(SYS_ICC_DIR_EL1), undef_access }, 3784 { CP15_SYS_DESC(SYS_ICC_RPR_EL1), undef_access }, 3785 { CP15_SYS_DESC(SYS_ICC_IAR1_EL1), undef_access }, 3786 { CP15_SYS_DESC(SYS_ICC_EOIR1_EL1), undef_access }, 3787 { CP15_SYS_DESC(SYS_ICC_HPPIR1_EL1), undef_access }, 3788 { CP15_SYS_DESC(SYS_ICC_BPR1_EL1), undef_access }, 3789 { CP15_SYS_DESC(SYS_ICC_CTLR_EL1), undef_access }, 3790 { CP15_SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre }, 3791 { CP15_SYS_DESC(SYS_ICC_IGRPEN0_EL1), undef_access }, 3792 { CP15_SYS_DESC(SYS_ICC_IGRPEN1_EL1), undef_access }, 3793 3794 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, CONTEXTIDR_EL1 }, 3795 3796 /* Arch Tmers */ 3797 { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer }, 3798 { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer }, 3799 3800 /* PMEVCNTRn */ 3801 PMU_PMEVCNTR(0), 3802 PMU_PMEVCNTR(1), 3803 PMU_PMEVCNTR(2), 3804 PMU_PMEVCNTR(3), 3805 PMU_PMEVCNTR(4), 3806 PMU_PMEVCNTR(5), 3807 PMU_PMEVCNTR(6), 3808 PMU_PMEVCNTR(7), 3809 PMU_PMEVCNTR(8), 3810 PMU_PMEVCNTR(9), 3811 PMU_PMEVCNTR(10), 3812 PMU_PMEVCNTR(11), 3813 PMU_PMEVCNTR(12), 3814 PMU_PMEVCNTR(13), 3815 PMU_PMEVCNTR(14), 3816 PMU_PMEVCNTR(15), 3817 PMU_PMEVCNTR(16), 3818 PMU_PMEVCNTR(17), 3819 PMU_PMEVCNTR(18), 3820 PMU_PMEVCNTR(19), 3821 PMU_PMEVCNTR(20), 3822 PMU_PMEVCNTR(21), 3823 PMU_PMEVCNTR(22), 3824 PMU_PMEVCNTR(23), 3825 PMU_PMEVCNTR(24), 3826 PMU_PMEVCNTR(25), 3827 PMU_PMEVCNTR(26), 3828 PMU_PMEVCNTR(27), 3829 PMU_PMEVCNTR(28), 3830 PMU_PMEVCNTR(29), 3831 PMU_PMEVCNTR(30), 3832 /* PMEVTYPERn */ 3833 PMU_PMEVTYPER(0), 3834 PMU_PMEVTYPER(1), 3835 PMU_PMEVTYPER(2), 3836 PMU_PMEVTYPER(3), 3837 PMU_PMEVTYPER(4), 3838 PMU_PMEVTYPER(5), 3839 PMU_PMEVTYPER(6), 3840 PMU_PMEVTYPER(7), 3841 PMU_PMEVTYPER(8), 3842 PMU_PMEVTYPER(9), 3843 PMU_PMEVTYPER(10), 3844 PMU_PMEVTYPER(11), 3845 PMU_PMEVTYPER(12), 3846 PMU_PMEVTYPER(13), 3847 PMU_PMEVTYPER(14), 3848 PMU_PMEVTYPER(15), 3849 PMU_PMEVTYPER(16), 3850 PMU_PMEVTYPER(17), 3851 PMU_PMEVTYPER(18), 3852 PMU_PMEVTYPER(19), 3853 PMU_PMEVTYPER(20), 3854 PMU_PMEVTYPER(21), 3855 PMU_PMEVTYPER(22), 3856 PMU_PMEVTYPER(23), 3857 PMU_PMEVTYPER(24), 3858 PMU_PMEVTYPER(25), 3859 PMU_PMEVTYPER(26), 3860 PMU_PMEVTYPER(27), 3861 PMU_PMEVTYPER(28), 3862 PMU_PMEVTYPER(29), 3863 PMU_PMEVTYPER(30), 3864 /* PMCCFILTR */ 3865 { CP15_PMU_SYS_REG(DIRECT, 0, 14, 15, 7), .access = access_pmu_evtyper }, 3866 3867 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr }, 3868 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr }, 3869 3870 /* CCSIDR2 */ 3871 { Op1(1), CRn( 0), CRm( 0), Op2(2), undef_access }, 3872 3873 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 }, 3874 }; 3875 3876 static const struct sys_reg_desc cp15_64_regs[] = { 3877 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, 3878 { CP15_PMU_SYS_REG(DIRECT, 0, 0, 9, 0), .access = access_pmu_evcntr }, 3879 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */ 3880 { SYS_DESC(SYS_AARCH32_CNTPCT), access_arch_timer }, 3881 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 }, 3882 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */ 3883 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */ 3884 { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer }, 3885 { SYS_DESC(SYS_AARCH32_CNTPCTSS), access_arch_timer }, 3886 }; 3887 3888 static bool check_sysreg_table(const struct sys_reg_desc *table, unsigned int n, 3889 bool is_32) 3890 { 3891 unsigned int i; 3892 3893 for (i = 0; i < n; i++) { 3894 if (!is_32 && table[i].reg && !table[i].reset) { 3895 kvm_err("sys_reg table %pS entry %d (%s) lacks reset\n", 3896 &table[i], i, table[i].name); 3897 return false; 3898 } 3899 3900 if (i && cmp_sys_reg(&table[i-1], &table[i]) >= 0) { 3901 kvm_err("sys_reg table %pS entry %d (%s -> %s) out of order\n", 3902 &table[i], i, table[i - 1].name, table[i].name); 3903 return false; 3904 } 3905 } 3906 3907 return true; 3908 } 3909 3910 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu) 3911 { 3912 kvm_inject_undefined(vcpu); 3913 return 1; 3914 } 3915 3916 static void perform_access(struct kvm_vcpu *vcpu, 3917 struct sys_reg_params *params, 3918 const struct sys_reg_desc *r) 3919 { 3920 trace_kvm_sys_access(*vcpu_pc(vcpu), params, r); 3921 3922 /* Check for regs disabled by runtime config */ 3923 if (sysreg_hidden(vcpu, r)) { 3924 kvm_inject_undefined(vcpu); 3925 return; 3926 } 3927 3928 /* 3929 * Not having an accessor means that we have configured a trap 3930 * that we don't know how to handle. This certainly qualifies 3931 * as a gross bug that should be fixed right away. 3932 */ 3933 BUG_ON(!r->access); 3934 3935 /* Skip instruction if instructed so */ 3936 if (likely(r->access(vcpu, params, r))) 3937 kvm_incr_pc(vcpu); 3938 } 3939 3940 /* 3941 * emulate_cp -- tries to match a sys_reg access in a handling table, and 3942 * call the corresponding trap handler. 3943 * 3944 * @params: pointer to the descriptor of the access 3945 * @table: array of trap descriptors 3946 * @num: size of the trap descriptor array 3947 * 3948 * Return true if the access has been handled, false if not. 3949 */ 3950 static bool emulate_cp(struct kvm_vcpu *vcpu, 3951 struct sys_reg_params *params, 3952 const struct sys_reg_desc *table, 3953 size_t num) 3954 { 3955 const struct sys_reg_desc *r; 3956 3957 if (!table) 3958 return false; /* Not handled */ 3959 3960 r = find_reg(params, table, num); 3961 3962 if (r) { 3963 perform_access(vcpu, params, r); 3964 return true; 3965 } 3966 3967 /* Not handled */ 3968 return false; 3969 } 3970 3971 static void unhandled_cp_access(struct kvm_vcpu *vcpu, 3972 struct sys_reg_params *params) 3973 { 3974 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu); 3975 int cp = -1; 3976 3977 switch (esr_ec) { 3978 case ESR_ELx_EC_CP15_32: 3979 case ESR_ELx_EC_CP15_64: 3980 cp = 15; 3981 break; 3982 case ESR_ELx_EC_CP14_MR: 3983 case ESR_ELx_EC_CP14_64: 3984 cp = 14; 3985 break; 3986 default: 3987 WARN_ON(1); 3988 } 3989 3990 print_sys_reg_msg(params, 3991 "Unsupported guest CP%d access at: %08lx [%08lx]\n", 3992 cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 3993 kvm_inject_undefined(vcpu); 3994 } 3995 3996 /** 3997 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access 3998 * @vcpu: The VCPU pointer 3999 * @global: &struct sys_reg_desc 4000 * @nr_global: size of the @global array 4001 */ 4002 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu, 4003 const struct sys_reg_desc *global, 4004 size_t nr_global) 4005 { 4006 struct sys_reg_params params; 4007 u64 esr = kvm_vcpu_get_esr(vcpu); 4008 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4009 int Rt2 = (esr >> 10) & 0x1f; 4010 4011 params.CRm = (esr >> 1) & 0xf; 4012 params.is_write = ((esr & 1) == 0); 4013 4014 params.Op0 = 0; 4015 params.Op1 = (esr >> 16) & 0xf; 4016 params.Op2 = 0; 4017 params.CRn = 0; 4018 4019 /* 4020 * Make a 64-bit value out of Rt and Rt2. As we use the same trap 4021 * backends between AArch32 and AArch64, we get away with it. 4022 */ 4023 if (params.is_write) { 4024 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff; 4025 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32; 4026 } 4027 4028 /* 4029 * If the table contains a handler, handle the 4030 * potential register operation in the case of a read and return 4031 * with success. 4032 */ 4033 if (emulate_cp(vcpu, ¶ms, global, nr_global)) { 4034 /* Split up the value between registers for the read side */ 4035 if (!params.is_write) { 4036 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval)); 4037 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval)); 4038 } 4039 4040 return 1; 4041 } 4042 4043 unhandled_cp_access(vcpu, ¶ms); 4044 return 1; 4045 } 4046 4047 static bool emulate_sys_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *params); 4048 4049 /* 4050 * The CP10 ID registers are architecturally mapped to AArch64 feature 4051 * registers. Abuse that fact so we can rely on the AArch64 handler for accesses 4052 * from AArch32. 4053 */ 4054 static bool kvm_esr_cp10_id_to_sys64(u64 esr, struct sys_reg_params *params) 4055 { 4056 u8 reg_id = (esr >> 10) & 0xf; 4057 bool valid; 4058 4059 params->is_write = ((esr & 1) == 0); 4060 params->Op0 = 3; 4061 params->Op1 = 0; 4062 params->CRn = 0; 4063 params->CRm = 3; 4064 4065 /* CP10 ID registers are read-only */ 4066 valid = !params->is_write; 4067 4068 switch (reg_id) { 4069 /* MVFR0 */ 4070 case 0b0111: 4071 params->Op2 = 0; 4072 break; 4073 /* MVFR1 */ 4074 case 0b0110: 4075 params->Op2 = 1; 4076 break; 4077 /* MVFR2 */ 4078 case 0b0101: 4079 params->Op2 = 2; 4080 break; 4081 default: 4082 valid = false; 4083 } 4084 4085 if (valid) 4086 return true; 4087 4088 kvm_pr_unimpl("Unhandled cp10 register %s: %u\n", 4089 params->is_write ? "write" : "read", reg_id); 4090 return false; 4091 } 4092 4093 /** 4094 * kvm_handle_cp10_id() - Handles a VMRS trap on guest access to a 'Media and 4095 * VFP Register' from AArch32. 4096 * @vcpu: The vCPU pointer 4097 * 4098 * MVFR{0-2} are architecturally mapped to the AArch64 MVFR{0-2}_EL1 registers. 4099 * Work out the correct AArch64 system register encoding and reroute to the 4100 * AArch64 system register emulation. 4101 */ 4102 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu) 4103 { 4104 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4105 u64 esr = kvm_vcpu_get_esr(vcpu); 4106 struct sys_reg_params params; 4107 4108 /* UNDEF on any unhandled register access */ 4109 if (!kvm_esr_cp10_id_to_sys64(esr, ¶ms)) { 4110 kvm_inject_undefined(vcpu); 4111 return 1; 4112 } 4113 4114 if (emulate_sys_reg(vcpu, ¶ms)) 4115 vcpu_set_reg(vcpu, Rt, params.regval); 4116 4117 return 1; 4118 } 4119 4120 /** 4121 * kvm_emulate_cp15_id_reg() - Handles an MRC trap on a guest CP15 access where 4122 * CRn=0, which corresponds to the AArch32 feature 4123 * registers. 4124 * @vcpu: the vCPU pointer 4125 * @params: the system register access parameters. 4126 * 4127 * Our cp15 system register tables do not enumerate the AArch32 feature 4128 * registers. Conveniently, our AArch64 table does, and the AArch32 system 4129 * register encoding can be trivially remapped into the AArch64 for the feature 4130 * registers: Append op0=3, leaving op1, CRn, CRm, and op2 the same. 4131 * 4132 * According to DDI0487G.b G7.3.1, paragraph "Behavior of VMSAv8-32 32-bit 4133 * System registers with (coproc=0b1111, CRn==c0)", read accesses from this 4134 * range are either UNKNOWN or RES0. Rerouting remains architectural as we 4135 * treat undefined registers in this range as RAZ. 4136 */ 4137 static int kvm_emulate_cp15_id_reg(struct kvm_vcpu *vcpu, 4138 struct sys_reg_params *params) 4139 { 4140 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4141 4142 /* Treat impossible writes to RO registers as UNDEFINED */ 4143 if (params->is_write) { 4144 unhandled_cp_access(vcpu, params); 4145 return 1; 4146 } 4147 4148 params->Op0 = 3; 4149 4150 /* 4151 * All registers where CRm > 3 are known to be UNKNOWN/RAZ from AArch32. 4152 * Avoid conflicting with future expansion of AArch64 feature registers 4153 * and simply treat them as RAZ here. 4154 */ 4155 if (params->CRm > 3) 4156 params->regval = 0; 4157 else if (!emulate_sys_reg(vcpu, params)) 4158 return 1; 4159 4160 vcpu_set_reg(vcpu, Rt, params->regval); 4161 return 1; 4162 } 4163 4164 /** 4165 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access 4166 * @vcpu: The VCPU pointer 4167 * @params: &struct sys_reg_params 4168 * @global: &struct sys_reg_desc 4169 * @nr_global: size of the @global array 4170 */ 4171 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu, 4172 struct sys_reg_params *params, 4173 const struct sys_reg_desc *global, 4174 size_t nr_global) 4175 { 4176 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4177 4178 params->regval = vcpu_get_reg(vcpu, Rt); 4179 4180 if (emulate_cp(vcpu, params, global, nr_global)) { 4181 if (!params->is_write) 4182 vcpu_set_reg(vcpu, Rt, params->regval); 4183 return 1; 4184 } 4185 4186 unhandled_cp_access(vcpu, params); 4187 return 1; 4188 } 4189 4190 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu) 4191 { 4192 return kvm_handle_cp_64(vcpu, cp15_64_regs, ARRAY_SIZE(cp15_64_regs)); 4193 } 4194 4195 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu) 4196 { 4197 struct sys_reg_params params; 4198 4199 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu)); 4200 4201 /* 4202 * Certain AArch32 ID registers are handled by rerouting to the AArch64 4203 * system register table. Registers in the ID range where CRm=0 are 4204 * excluded from this scheme as they do not trivially map into AArch64 4205 * system register encodings. 4206 */ 4207 if (params.Op1 == 0 && params.CRn == 0 && params.CRm) 4208 return kvm_emulate_cp15_id_reg(vcpu, ¶ms); 4209 4210 return kvm_handle_cp_32(vcpu, ¶ms, cp15_regs, ARRAY_SIZE(cp15_regs)); 4211 } 4212 4213 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu) 4214 { 4215 return kvm_handle_cp_64(vcpu, cp14_64_regs, ARRAY_SIZE(cp14_64_regs)); 4216 } 4217 4218 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu) 4219 { 4220 struct sys_reg_params params; 4221 4222 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu)); 4223 4224 return kvm_handle_cp_32(vcpu, ¶ms, cp14_regs, ARRAY_SIZE(cp14_regs)); 4225 } 4226 4227 /** 4228 * emulate_sys_reg - Emulate a guest access to an AArch64 system register 4229 * @vcpu: The VCPU pointer 4230 * @params: Decoded system register parameters 4231 * 4232 * Return: true if the system register access was successful, false otherwise. 4233 */ 4234 static bool emulate_sys_reg(struct kvm_vcpu *vcpu, 4235 struct sys_reg_params *params) 4236 { 4237 const struct sys_reg_desc *r; 4238 4239 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 4240 if (likely(r)) { 4241 perform_access(vcpu, params, r); 4242 return true; 4243 } 4244 4245 print_sys_reg_msg(params, 4246 "Unsupported guest sys_reg access at: %lx [%08lx]\n", 4247 *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 4248 kvm_inject_undefined(vcpu); 4249 4250 return false; 4251 } 4252 4253 static const struct sys_reg_desc *idregs_debug_find(struct kvm *kvm, u8 pos) 4254 { 4255 unsigned long i, idreg_idx = 0; 4256 4257 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { 4258 const struct sys_reg_desc *r = &sys_reg_descs[i]; 4259 4260 if (!is_vm_ftr_id_reg(reg_to_encoding(r))) 4261 continue; 4262 4263 if (idreg_idx == pos) 4264 return r; 4265 4266 idreg_idx++; 4267 } 4268 4269 return NULL; 4270 } 4271 4272 static void *idregs_debug_start(struct seq_file *s, loff_t *pos) 4273 { 4274 struct kvm *kvm = s->private; 4275 u8 *iter; 4276 4277 mutex_lock(&kvm->arch.config_lock); 4278 4279 iter = &kvm->arch.idreg_debugfs_iter; 4280 if (test_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags) && 4281 *iter == (u8)~0) { 4282 *iter = *pos; 4283 if (!idregs_debug_find(kvm, *iter)) 4284 iter = NULL; 4285 } else { 4286 iter = ERR_PTR(-EBUSY); 4287 } 4288 4289 mutex_unlock(&kvm->arch.config_lock); 4290 4291 return iter; 4292 } 4293 4294 static void *idregs_debug_next(struct seq_file *s, void *v, loff_t *pos) 4295 { 4296 struct kvm *kvm = s->private; 4297 4298 (*pos)++; 4299 4300 if (idregs_debug_find(kvm, kvm->arch.idreg_debugfs_iter + 1)) { 4301 kvm->arch.idreg_debugfs_iter++; 4302 4303 return &kvm->arch.idreg_debugfs_iter; 4304 } 4305 4306 return NULL; 4307 } 4308 4309 static void idregs_debug_stop(struct seq_file *s, void *v) 4310 { 4311 struct kvm *kvm = s->private; 4312 4313 if (IS_ERR(v)) 4314 return; 4315 4316 mutex_lock(&kvm->arch.config_lock); 4317 4318 kvm->arch.idreg_debugfs_iter = ~0; 4319 4320 mutex_unlock(&kvm->arch.config_lock); 4321 } 4322 4323 static int idregs_debug_show(struct seq_file *s, void *v) 4324 { 4325 const struct sys_reg_desc *desc; 4326 struct kvm *kvm = s->private; 4327 4328 desc = idregs_debug_find(kvm, kvm->arch.idreg_debugfs_iter); 4329 4330 if (!desc->name) 4331 return 0; 4332 4333 seq_printf(s, "%20s:\t%016llx\n", 4334 desc->name, kvm_read_vm_id_reg(kvm, reg_to_encoding(desc))); 4335 4336 return 0; 4337 } 4338 4339 static const struct seq_operations idregs_debug_sops = { 4340 .start = idregs_debug_start, 4341 .next = idregs_debug_next, 4342 .stop = idregs_debug_stop, 4343 .show = idregs_debug_show, 4344 }; 4345 4346 DEFINE_SEQ_ATTRIBUTE(idregs_debug); 4347 4348 void kvm_sys_regs_create_debugfs(struct kvm *kvm) 4349 { 4350 kvm->arch.idreg_debugfs_iter = ~0; 4351 4352 debugfs_create_file("idregs", 0444, kvm->debugfs_dentry, kvm, 4353 &idregs_debug_fops); 4354 } 4355 4356 static void reset_vm_ftr_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *reg) 4357 { 4358 u32 id = reg_to_encoding(reg); 4359 struct kvm *kvm = vcpu->kvm; 4360 4361 if (test_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags)) 4362 return; 4363 4364 kvm_set_vm_id_reg(kvm, id, reg->reset(vcpu, reg)); 4365 } 4366 4367 static void reset_vcpu_ftr_id_reg(struct kvm_vcpu *vcpu, 4368 const struct sys_reg_desc *reg) 4369 { 4370 if (kvm_vcpu_initialized(vcpu)) 4371 return; 4372 4373 reg->reset(vcpu, reg); 4374 } 4375 4376 /** 4377 * kvm_reset_sys_regs - sets system registers to reset value 4378 * @vcpu: The VCPU pointer 4379 * 4380 * This function finds the right table above and sets the registers on the 4381 * virtual CPU struct to their architecturally defined reset values. 4382 */ 4383 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu) 4384 { 4385 struct kvm *kvm = vcpu->kvm; 4386 unsigned long i; 4387 4388 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { 4389 const struct sys_reg_desc *r = &sys_reg_descs[i]; 4390 4391 if (!r->reset) 4392 continue; 4393 4394 if (is_vm_ftr_id_reg(reg_to_encoding(r))) 4395 reset_vm_ftr_id_reg(vcpu, r); 4396 else if (is_vcpu_ftr_id_reg(reg_to_encoding(r))) 4397 reset_vcpu_ftr_id_reg(vcpu, r); 4398 else 4399 r->reset(vcpu, r); 4400 } 4401 4402 set_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags); 4403 } 4404 4405 /** 4406 * kvm_handle_sys_reg -- handles a system instruction or mrs/msr instruction 4407 * trap on a guest execution 4408 * @vcpu: The VCPU pointer 4409 */ 4410 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu) 4411 { 4412 const struct sys_reg_desc *desc = NULL; 4413 struct sys_reg_params params; 4414 unsigned long esr = kvm_vcpu_get_esr(vcpu); 4415 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4416 int sr_idx; 4417 4418 trace_kvm_handle_sys_reg(esr); 4419 4420 if (triage_sysreg_trap(vcpu, &sr_idx)) 4421 return 1; 4422 4423 params = esr_sys64_to_params(esr); 4424 params.regval = vcpu_get_reg(vcpu, Rt); 4425 4426 /* System registers have Op0=={2,3}, as per DDI487 J.a C5.1.2 */ 4427 if (params.Op0 == 2 || params.Op0 == 3) 4428 desc = &sys_reg_descs[sr_idx]; 4429 else 4430 desc = &sys_insn_descs[sr_idx]; 4431 4432 perform_access(vcpu, ¶ms, desc); 4433 4434 /* Read from system register? */ 4435 if (!params.is_write && 4436 (params.Op0 == 2 || params.Op0 == 3)) 4437 vcpu_set_reg(vcpu, Rt, params.regval); 4438 4439 return 1; 4440 } 4441 4442 /****************************************************************************** 4443 * Userspace API 4444 *****************************************************************************/ 4445 4446 static bool index_to_params(u64 id, struct sys_reg_params *params) 4447 { 4448 switch (id & KVM_REG_SIZE_MASK) { 4449 case KVM_REG_SIZE_U64: 4450 /* Any unused index bits means it's not valid. */ 4451 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK 4452 | KVM_REG_ARM_COPROC_MASK 4453 | KVM_REG_ARM64_SYSREG_OP0_MASK 4454 | KVM_REG_ARM64_SYSREG_OP1_MASK 4455 | KVM_REG_ARM64_SYSREG_CRN_MASK 4456 | KVM_REG_ARM64_SYSREG_CRM_MASK 4457 | KVM_REG_ARM64_SYSREG_OP2_MASK)) 4458 return false; 4459 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK) 4460 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT); 4461 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK) 4462 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT); 4463 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK) 4464 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT); 4465 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK) 4466 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT); 4467 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK) 4468 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT); 4469 return true; 4470 default: 4471 return false; 4472 } 4473 } 4474 4475 const struct sys_reg_desc *get_reg_by_id(u64 id, 4476 const struct sys_reg_desc table[], 4477 unsigned int num) 4478 { 4479 struct sys_reg_params params; 4480 4481 if (!index_to_params(id, ¶ms)) 4482 return NULL; 4483 4484 return find_reg(¶ms, table, num); 4485 } 4486 4487 /* Decode an index value, and find the sys_reg_desc entry. */ 4488 static const struct sys_reg_desc * 4489 id_to_sys_reg_desc(struct kvm_vcpu *vcpu, u64 id, 4490 const struct sys_reg_desc table[], unsigned int num) 4491 4492 { 4493 const struct sys_reg_desc *r; 4494 4495 /* We only do sys_reg for now. */ 4496 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG) 4497 return NULL; 4498 4499 r = get_reg_by_id(id, table, num); 4500 4501 /* Not saved in the sys_reg array and not otherwise accessible? */ 4502 if (r && (!(r->reg || r->get_user) || sysreg_hidden(vcpu, r))) 4503 r = NULL; 4504 4505 return r; 4506 } 4507 4508 /* 4509 * These are the invariant sys_reg registers: we let the guest see the 4510 * host versions of these, so they're part of the guest state. 4511 * 4512 * A future CPU may provide a mechanism to present different values to 4513 * the guest, or a future kvm may trap them. 4514 */ 4515 4516 #define FUNCTION_INVARIANT(reg) \ 4517 static u64 reset_##reg(struct kvm_vcpu *v, \ 4518 const struct sys_reg_desc *r) \ 4519 { \ 4520 ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \ 4521 return ((struct sys_reg_desc *)r)->val; \ 4522 } 4523 4524 FUNCTION_INVARIANT(midr_el1) 4525 FUNCTION_INVARIANT(revidr_el1) 4526 FUNCTION_INVARIANT(aidr_el1) 4527 4528 /* ->val is filled in by kvm_sys_reg_table_init() */ 4529 static struct sys_reg_desc invariant_sys_regs[] __ro_after_init = { 4530 { SYS_DESC(SYS_MIDR_EL1), NULL, reset_midr_el1 }, 4531 { SYS_DESC(SYS_REVIDR_EL1), NULL, reset_revidr_el1 }, 4532 { SYS_DESC(SYS_AIDR_EL1), NULL, reset_aidr_el1 }, 4533 }; 4534 4535 static int get_invariant_sys_reg(u64 id, u64 __user *uaddr) 4536 { 4537 const struct sys_reg_desc *r; 4538 4539 r = get_reg_by_id(id, invariant_sys_regs, 4540 ARRAY_SIZE(invariant_sys_regs)); 4541 if (!r) 4542 return -ENOENT; 4543 4544 return put_user(r->val, uaddr); 4545 } 4546 4547 static int set_invariant_sys_reg(u64 id, u64 __user *uaddr) 4548 { 4549 const struct sys_reg_desc *r; 4550 u64 val; 4551 4552 r = get_reg_by_id(id, invariant_sys_regs, 4553 ARRAY_SIZE(invariant_sys_regs)); 4554 if (!r) 4555 return -ENOENT; 4556 4557 if (get_user(val, uaddr)) 4558 return -EFAULT; 4559 4560 /* This is what we mean by invariant: you can't change it. */ 4561 if (r->val != val) 4562 return -EINVAL; 4563 4564 return 0; 4565 } 4566 4567 static int demux_c15_get(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) 4568 { 4569 u32 val; 4570 u32 __user *uval = uaddr; 4571 4572 /* Fail if we have unknown bits set. */ 4573 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 4574 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 4575 return -ENOENT; 4576 4577 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 4578 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 4579 if (KVM_REG_SIZE(id) != 4) 4580 return -ENOENT; 4581 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 4582 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 4583 if (val >= CSSELR_MAX) 4584 return -ENOENT; 4585 4586 return put_user(get_ccsidr(vcpu, val), uval); 4587 default: 4588 return -ENOENT; 4589 } 4590 } 4591 4592 static int demux_c15_set(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) 4593 { 4594 u32 val, newval; 4595 u32 __user *uval = uaddr; 4596 4597 /* Fail if we have unknown bits set. */ 4598 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 4599 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 4600 return -ENOENT; 4601 4602 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 4603 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 4604 if (KVM_REG_SIZE(id) != 4) 4605 return -ENOENT; 4606 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 4607 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 4608 if (val >= CSSELR_MAX) 4609 return -ENOENT; 4610 4611 if (get_user(newval, uval)) 4612 return -EFAULT; 4613 4614 return set_ccsidr(vcpu, val, newval); 4615 default: 4616 return -ENOENT; 4617 } 4618 } 4619 4620 int kvm_sys_reg_get_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg, 4621 const struct sys_reg_desc table[], unsigned int num) 4622 { 4623 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr; 4624 const struct sys_reg_desc *r; 4625 u64 val; 4626 int ret; 4627 4628 r = id_to_sys_reg_desc(vcpu, reg->id, table, num); 4629 if (!r || sysreg_hidden(vcpu, r)) 4630 return -ENOENT; 4631 4632 if (r->get_user) { 4633 ret = (r->get_user)(vcpu, r, &val); 4634 } else { 4635 val = __vcpu_sys_reg(vcpu, r->reg); 4636 ret = 0; 4637 } 4638 4639 if (!ret) 4640 ret = put_user(val, uaddr); 4641 4642 return ret; 4643 } 4644 4645 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 4646 { 4647 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 4648 int err; 4649 4650 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 4651 return demux_c15_get(vcpu, reg->id, uaddr); 4652 4653 err = get_invariant_sys_reg(reg->id, uaddr); 4654 if (err != -ENOENT) 4655 return err; 4656 4657 return kvm_sys_reg_get_user(vcpu, reg, 4658 sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 4659 } 4660 4661 int kvm_sys_reg_set_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg, 4662 const struct sys_reg_desc table[], unsigned int num) 4663 { 4664 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr; 4665 const struct sys_reg_desc *r; 4666 u64 val; 4667 int ret; 4668 4669 if (get_user(val, uaddr)) 4670 return -EFAULT; 4671 4672 r = id_to_sys_reg_desc(vcpu, reg->id, table, num); 4673 if (!r || sysreg_hidden(vcpu, r)) 4674 return -ENOENT; 4675 4676 if (sysreg_user_write_ignore(vcpu, r)) 4677 return 0; 4678 4679 if (r->set_user) { 4680 ret = (r->set_user)(vcpu, r, val); 4681 } else { 4682 __vcpu_sys_reg(vcpu, r->reg) = val; 4683 ret = 0; 4684 } 4685 4686 return ret; 4687 } 4688 4689 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 4690 { 4691 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 4692 int err; 4693 4694 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 4695 return demux_c15_set(vcpu, reg->id, uaddr); 4696 4697 err = set_invariant_sys_reg(reg->id, uaddr); 4698 if (err != -ENOENT) 4699 return err; 4700 4701 return kvm_sys_reg_set_user(vcpu, reg, 4702 sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 4703 } 4704 4705 static unsigned int num_demux_regs(void) 4706 { 4707 return CSSELR_MAX; 4708 } 4709 4710 static int write_demux_regids(u64 __user *uindices) 4711 { 4712 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX; 4713 unsigned int i; 4714 4715 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR; 4716 for (i = 0; i < CSSELR_MAX; i++) { 4717 if (put_user(val | i, uindices)) 4718 return -EFAULT; 4719 uindices++; 4720 } 4721 return 0; 4722 } 4723 4724 static u64 sys_reg_to_index(const struct sys_reg_desc *reg) 4725 { 4726 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | 4727 KVM_REG_ARM64_SYSREG | 4728 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) | 4729 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) | 4730 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) | 4731 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) | 4732 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT)); 4733 } 4734 4735 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind) 4736 { 4737 if (!*uind) 4738 return true; 4739 4740 if (put_user(sys_reg_to_index(reg), *uind)) 4741 return false; 4742 4743 (*uind)++; 4744 return true; 4745 } 4746 4747 static int walk_one_sys_reg(const struct kvm_vcpu *vcpu, 4748 const struct sys_reg_desc *rd, 4749 u64 __user **uind, 4750 unsigned int *total) 4751 { 4752 /* 4753 * Ignore registers we trap but don't save, 4754 * and for which no custom user accessor is provided. 4755 */ 4756 if (!(rd->reg || rd->get_user)) 4757 return 0; 4758 4759 if (sysreg_hidden(vcpu, rd)) 4760 return 0; 4761 4762 if (!copy_reg_to_user(rd, uind)) 4763 return -EFAULT; 4764 4765 (*total)++; 4766 return 0; 4767 } 4768 4769 /* Assumed ordered tables, see kvm_sys_reg_table_init. */ 4770 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind) 4771 { 4772 const struct sys_reg_desc *i2, *end2; 4773 unsigned int total = 0; 4774 int err; 4775 4776 i2 = sys_reg_descs; 4777 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs); 4778 4779 while (i2 != end2) { 4780 err = walk_one_sys_reg(vcpu, i2++, &uind, &total); 4781 if (err) 4782 return err; 4783 } 4784 return total; 4785 } 4786 4787 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu) 4788 { 4789 return ARRAY_SIZE(invariant_sys_regs) 4790 + num_demux_regs() 4791 + walk_sys_regs(vcpu, (u64 __user *)NULL); 4792 } 4793 4794 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) 4795 { 4796 unsigned int i; 4797 int err; 4798 4799 /* Then give them all the invariant registers' indices. */ 4800 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) { 4801 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices)) 4802 return -EFAULT; 4803 uindices++; 4804 } 4805 4806 err = walk_sys_regs(vcpu, uindices); 4807 if (err < 0) 4808 return err; 4809 uindices += err; 4810 4811 return write_demux_regids(uindices); 4812 } 4813 4814 #define KVM_ARM_FEATURE_ID_RANGE_INDEX(r) \ 4815 KVM_ARM_FEATURE_ID_RANGE_IDX(sys_reg_Op0(r), \ 4816 sys_reg_Op1(r), \ 4817 sys_reg_CRn(r), \ 4818 sys_reg_CRm(r), \ 4819 sys_reg_Op2(r)) 4820 4821 int kvm_vm_ioctl_get_reg_writable_masks(struct kvm *kvm, struct reg_mask_range *range) 4822 { 4823 const void *zero_page = page_to_virt(ZERO_PAGE(0)); 4824 u64 __user *masks = (u64 __user *)range->addr; 4825 4826 /* Only feature id range is supported, reserved[13] must be zero. */ 4827 if (range->range || 4828 memcmp(range->reserved, zero_page, sizeof(range->reserved))) 4829 return -EINVAL; 4830 4831 /* Wipe the whole thing first */ 4832 if (clear_user(masks, KVM_ARM_FEATURE_ID_RANGE_SIZE * sizeof(__u64))) 4833 return -EFAULT; 4834 4835 for (int i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { 4836 const struct sys_reg_desc *reg = &sys_reg_descs[i]; 4837 u32 encoding = reg_to_encoding(reg); 4838 u64 val; 4839 4840 if (!is_feature_id_reg(encoding) || !reg->set_user) 4841 continue; 4842 4843 if (!reg->val || 4844 (is_aa32_id_reg(encoding) && !kvm_supports_32bit_el0())) { 4845 continue; 4846 } 4847 val = reg->val; 4848 4849 if (put_user(val, (masks + KVM_ARM_FEATURE_ID_RANGE_INDEX(encoding)))) 4850 return -EFAULT; 4851 } 4852 4853 return 0; 4854 } 4855 4856 static void vcpu_set_hcr(struct kvm_vcpu *vcpu) 4857 { 4858 struct kvm *kvm = vcpu->kvm; 4859 4860 if (has_vhe() || has_hvhe()) 4861 vcpu->arch.hcr_el2 |= HCR_E2H; 4862 if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN)) { 4863 /* route synchronous external abort exceptions to EL2 */ 4864 vcpu->arch.hcr_el2 |= HCR_TEA; 4865 /* trap error record accesses */ 4866 vcpu->arch.hcr_el2 |= HCR_TERR; 4867 } 4868 4869 if (cpus_have_final_cap(ARM64_HAS_STAGE2_FWB)) 4870 vcpu->arch.hcr_el2 |= HCR_FWB; 4871 4872 if (cpus_have_final_cap(ARM64_HAS_EVT) && 4873 !cpus_have_final_cap(ARM64_MISMATCHED_CACHE_TYPE) && 4874 kvm_read_vm_id_reg(kvm, SYS_CTR_EL0) == read_sanitised_ftr_reg(SYS_CTR_EL0)) 4875 vcpu->arch.hcr_el2 |= HCR_TID4; 4876 else 4877 vcpu->arch.hcr_el2 |= HCR_TID2; 4878 4879 if (vcpu_el1_is_32bit(vcpu)) 4880 vcpu->arch.hcr_el2 &= ~HCR_RW; 4881 4882 if (kvm_has_mte(vcpu->kvm)) 4883 vcpu->arch.hcr_el2 |= HCR_ATA; 4884 4885 /* 4886 * In the absence of FGT, we cannot independently trap TLBI 4887 * Range instructions. This isn't great, but trapping all 4888 * TLBIs would be far worse. Live with it... 4889 */ 4890 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 4891 vcpu->arch.hcr_el2 |= HCR_TTLBOS; 4892 } 4893 4894 void kvm_calculate_traps(struct kvm_vcpu *vcpu) 4895 { 4896 struct kvm *kvm = vcpu->kvm; 4897 4898 mutex_lock(&kvm->arch.config_lock); 4899 vcpu_set_hcr(vcpu); 4900 vcpu_set_ich_hcr(vcpu); 4901 4902 if (cpus_have_final_cap(ARM64_HAS_HCX)) { 4903 /* 4904 * In general, all HCRX_EL2 bits are gated by a feature. 4905 * The only reason we can set SMPME without checking any 4906 * feature is that its effects are not directly observable 4907 * from the guest. 4908 */ 4909 vcpu->arch.hcrx_el2 = HCRX_EL2_SMPME; 4910 4911 if (kvm_has_feat(kvm, ID_AA64ISAR2_EL1, MOPS, IMP)) 4912 vcpu->arch.hcrx_el2 |= (HCRX_EL2_MSCEn | HCRX_EL2_MCE2); 4913 4914 if (kvm_has_tcr2(kvm)) 4915 vcpu->arch.hcrx_el2 |= HCRX_EL2_TCR2En; 4916 4917 if (kvm_has_fpmr(kvm)) 4918 vcpu->arch.hcrx_el2 |= HCRX_EL2_EnFPM; 4919 } 4920 4921 if (test_bit(KVM_ARCH_FLAG_FGU_INITIALIZED, &kvm->arch.flags)) 4922 goto out; 4923 4924 kvm->arch.fgu[HFGxTR_GROUP] = (HFGxTR_EL2_nAMAIR2_EL1 | 4925 HFGxTR_EL2_nMAIR2_EL1 | 4926 HFGxTR_EL2_nS2POR_EL1 | 4927 HFGxTR_EL2_nACCDATA_EL1 | 4928 HFGxTR_EL2_nSMPRI_EL1_MASK | 4929 HFGxTR_EL2_nTPIDR2_EL0_MASK); 4930 4931 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 4932 kvm->arch.fgu[HFGITR_GROUP] |= (HFGITR_EL2_TLBIRVAALE1OS| 4933 HFGITR_EL2_TLBIRVALE1OS | 4934 HFGITR_EL2_TLBIRVAAE1OS | 4935 HFGITR_EL2_TLBIRVAE1OS | 4936 HFGITR_EL2_TLBIVAALE1OS | 4937 HFGITR_EL2_TLBIVALE1OS | 4938 HFGITR_EL2_TLBIVAAE1OS | 4939 HFGITR_EL2_TLBIASIDE1OS | 4940 HFGITR_EL2_TLBIVAE1OS | 4941 HFGITR_EL2_TLBIVMALLE1OS); 4942 4943 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE)) 4944 kvm->arch.fgu[HFGITR_GROUP] |= (HFGITR_EL2_TLBIRVAALE1 | 4945 HFGITR_EL2_TLBIRVALE1 | 4946 HFGITR_EL2_TLBIRVAAE1 | 4947 HFGITR_EL2_TLBIRVAE1 | 4948 HFGITR_EL2_TLBIRVAALE1IS| 4949 HFGITR_EL2_TLBIRVALE1IS | 4950 HFGITR_EL2_TLBIRVAAE1IS | 4951 HFGITR_EL2_TLBIRVAE1IS | 4952 HFGITR_EL2_TLBIRVAALE1OS| 4953 HFGITR_EL2_TLBIRVALE1OS | 4954 HFGITR_EL2_TLBIRVAAE1OS | 4955 HFGITR_EL2_TLBIRVAE1OS); 4956 4957 if (!kvm_has_feat(kvm, ID_AA64ISAR2_EL1, ATS1A, IMP)) 4958 kvm->arch.fgu[HFGITR_GROUP] |= HFGITR_EL2_ATS1E1A; 4959 4960 if (!kvm_has_feat(kvm, ID_AA64MMFR1_EL1, PAN, PAN2)) 4961 kvm->arch.fgu[HFGITR_GROUP] |= (HFGITR_EL2_ATS1E1RP | 4962 HFGITR_EL2_ATS1E1WP); 4963 4964 if (!kvm_has_s1pie(kvm)) 4965 kvm->arch.fgu[HFGxTR_GROUP] |= (HFGxTR_EL2_nPIRE0_EL1 | 4966 HFGxTR_EL2_nPIR_EL1); 4967 4968 if (!kvm_has_s1poe(kvm)) 4969 kvm->arch.fgu[HFGxTR_GROUP] |= (HFGxTR_EL2_nPOR_EL1 | 4970 HFGxTR_EL2_nPOR_EL0); 4971 4972 if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, AMU, IMP)) 4973 kvm->arch.fgu[HAFGRTR_GROUP] |= ~(HAFGRTR_EL2_RES0 | 4974 HAFGRTR_EL2_RES1); 4975 4976 set_bit(KVM_ARCH_FLAG_FGU_INITIALIZED, &kvm->arch.flags); 4977 out: 4978 mutex_unlock(&kvm->arch.config_lock); 4979 } 4980 4981 /* 4982 * Perform last adjustments to the ID registers that are implied by the 4983 * configuration outside of the ID regs themselves, as well as any 4984 * initialisation that directly depend on these ID registers (such as 4985 * RES0/RES1 behaviours). This is not the place to configure traps though. 4986 * 4987 * Because this can be called once per CPU, changes must be idempotent. 4988 */ 4989 int kvm_finalize_sys_regs(struct kvm_vcpu *vcpu) 4990 { 4991 struct kvm *kvm = vcpu->kvm; 4992 4993 guard(mutex)(&kvm->arch.config_lock); 4994 4995 if (!(static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif) && 4996 irqchip_in_kernel(kvm) && 4997 kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3)) { 4998 kvm->arch.id_regs[IDREG_IDX(SYS_ID_AA64PFR0_EL1)] &= ~ID_AA64PFR0_EL1_GIC_MASK; 4999 kvm->arch.id_regs[IDREG_IDX(SYS_ID_PFR1_EL1)] &= ~ID_PFR1_EL1_GIC_MASK; 5000 } 5001 5002 if (vcpu_has_nv(vcpu)) { 5003 int ret = kvm_init_nv_sysregs(kvm); 5004 if (ret) 5005 return ret; 5006 } 5007 5008 return 0; 5009 } 5010 5011 int __init kvm_sys_reg_table_init(void) 5012 { 5013 bool valid = true; 5014 unsigned int i; 5015 int ret = 0; 5016 5017 /* Make sure tables are unique and in order. */ 5018 valid &= check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), false); 5019 valid &= check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), true); 5020 valid &= check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), true); 5021 valid &= check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), true); 5022 valid &= check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), true); 5023 valid &= check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs), false); 5024 valid &= check_sysreg_table(sys_insn_descs, ARRAY_SIZE(sys_insn_descs), false); 5025 5026 if (!valid) 5027 return -EINVAL; 5028 5029 /* We abuse the reset function to overwrite the table itself. */ 5030 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) 5031 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]); 5032 5033 ret = populate_nv_trap_config(); 5034 5035 for (i = 0; !ret && i < ARRAY_SIZE(sys_reg_descs); i++) 5036 ret = populate_sysreg_config(sys_reg_descs + i, i); 5037 5038 for (i = 0; !ret && i < ARRAY_SIZE(sys_insn_descs); i++) 5039 ret = populate_sysreg_config(sys_insn_descs + i, i); 5040 5041 return ret; 5042 } 5043