1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/kvm/coproc.c: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Authors: Rusty Russell <rusty@rustcorp.com.au> 9 * Christoffer Dall <c.dall@virtualopensystems.com> 10 */ 11 12 #include <linux/bitfield.h> 13 #include <linux/bsearch.h> 14 #include <linux/kvm_host.h> 15 #include <linux/mm.h> 16 #include <linux/printk.h> 17 #include <linux/uaccess.h> 18 19 #include <asm/cacheflush.h> 20 #include <asm/cputype.h> 21 #include <asm/debug-monitors.h> 22 #include <asm/esr.h> 23 #include <asm/kvm_arm.h> 24 #include <asm/kvm_emulate.h> 25 #include <asm/kvm_hyp.h> 26 #include <asm/kvm_mmu.h> 27 #include <asm/kvm_nested.h> 28 #include <asm/perf_event.h> 29 #include <asm/sysreg.h> 30 31 #include <trace/events/kvm.h> 32 33 #include "sys_regs.h" 34 35 #include "trace.h" 36 37 /* 38 * For AArch32, we only take care of what is being trapped. Anything 39 * that has to do with init and userspace access has to go via the 40 * 64bit interface. 41 */ 42 43 static u64 sys_reg_to_index(const struct sys_reg_desc *reg); 44 45 static bool read_from_write_only(struct kvm_vcpu *vcpu, 46 struct sys_reg_params *params, 47 const struct sys_reg_desc *r) 48 { 49 WARN_ONCE(1, "Unexpected sys_reg read to write-only register\n"); 50 print_sys_reg_instr(params); 51 kvm_inject_undefined(vcpu); 52 return false; 53 } 54 55 static bool write_to_read_only(struct kvm_vcpu *vcpu, 56 struct sys_reg_params *params, 57 const struct sys_reg_desc *r) 58 { 59 WARN_ONCE(1, "Unexpected sys_reg write to read-only register\n"); 60 print_sys_reg_instr(params); 61 kvm_inject_undefined(vcpu); 62 return false; 63 } 64 65 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg) 66 { 67 u64 val = 0x8badf00d8badf00d; 68 69 if (vcpu_get_flag(vcpu, SYSREGS_ON_CPU) && 70 __vcpu_read_sys_reg_from_cpu(reg, &val)) 71 return val; 72 73 return __vcpu_sys_reg(vcpu, reg); 74 } 75 76 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg) 77 { 78 if (vcpu_get_flag(vcpu, SYSREGS_ON_CPU) && 79 __vcpu_write_sys_reg_to_cpu(val, reg)) 80 return; 81 82 __vcpu_sys_reg(vcpu, reg) = val; 83 } 84 85 /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */ 86 static u32 cache_levels; 87 88 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */ 89 #define CSSELR_MAX 14 90 91 /* Which cache CCSIDR represents depends on CSSELR value. */ 92 static u32 get_ccsidr(u32 csselr) 93 { 94 u32 ccsidr; 95 96 /* Make sure noone else changes CSSELR during this! */ 97 local_irq_disable(); 98 write_sysreg(csselr, csselr_el1); 99 isb(); 100 ccsidr = read_sysreg(ccsidr_el1); 101 local_irq_enable(); 102 103 return ccsidr; 104 } 105 106 static bool access_rw(struct kvm_vcpu *vcpu, 107 struct sys_reg_params *p, 108 const struct sys_reg_desc *r) 109 { 110 if (p->is_write) 111 vcpu_write_sys_reg(vcpu, p->regval, r->reg); 112 else 113 p->regval = vcpu_read_sys_reg(vcpu, r->reg); 114 115 return true; 116 } 117 118 /* 119 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized). 120 */ 121 static bool access_dcsw(struct kvm_vcpu *vcpu, 122 struct sys_reg_params *p, 123 const struct sys_reg_desc *r) 124 { 125 if (!p->is_write) 126 return read_from_write_only(vcpu, p, r); 127 128 /* 129 * Only track S/W ops if we don't have FWB. It still indicates 130 * that the guest is a bit broken (S/W operations should only 131 * be done by firmware, knowing that there is only a single 132 * CPU left in the system, and certainly not from non-secure 133 * software). 134 */ 135 if (!cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) 136 kvm_set_way_flush(vcpu); 137 138 return true; 139 } 140 141 static void get_access_mask(const struct sys_reg_desc *r, u64 *mask, u64 *shift) 142 { 143 switch (r->aarch32_map) { 144 case AA32_LO: 145 *mask = GENMASK_ULL(31, 0); 146 *shift = 0; 147 break; 148 case AA32_HI: 149 *mask = GENMASK_ULL(63, 32); 150 *shift = 32; 151 break; 152 default: 153 *mask = GENMASK_ULL(63, 0); 154 *shift = 0; 155 break; 156 } 157 } 158 159 /* 160 * Generic accessor for VM registers. Only called as long as HCR_TVM 161 * is set. If the guest enables the MMU, we stop trapping the VM 162 * sys_regs and leave it in complete control of the caches. 163 */ 164 static bool access_vm_reg(struct kvm_vcpu *vcpu, 165 struct sys_reg_params *p, 166 const struct sys_reg_desc *r) 167 { 168 bool was_enabled = vcpu_has_cache_enabled(vcpu); 169 u64 val, mask, shift; 170 171 BUG_ON(!p->is_write); 172 173 get_access_mask(r, &mask, &shift); 174 175 if (~mask) { 176 val = vcpu_read_sys_reg(vcpu, r->reg); 177 val &= ~mask; 178 } else { 179 val = 0; 180 } 181 182 val |= (p->regval & (mask >> shift)) << shift; 183 vcpu_write_sys_reg(vcpu, val, r->reg); 184 185 kvm_toggle_cache(vcpu, was_enabled); 186 return true; 187 } 188 189 static bool access_actlr(struct kvm_vcpu *vcpu, 190 struct sys_reg_params *p, 191 const struct sys_reg_desc *r) 192 { 193 u64 mask, shift; 194 195 if (p->is_write) 196 return ignore_write(vcpu, p); 197 198 get_access_mask(r, &mask, &shift); 199 p->regval = (vcpu_read_sys_reg(vcpu, r->reg) & mask) >> shift; 200 201 return true; 202 } 203 204 /* 205 * Trap handler for the GICv3 SGI generation system register. 206 * Forward the request to the VGIC emulation. 207 * The cp15_64 code makes sure this automatically works 208 * for both AArch64 and AArch32 accesses. 209 */ 210 static bool access_gic_sgi(struct kvm_vcpu *vcpu, 211 struct sys_reg_params *p, 212 const struct sys_reg_desc *r) 213 { 214 bool g1; 215 216 if (!p->is_write) 217 return read_from_write_only(vcpu, p, r); 218 219 /* 220 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates 221 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group, 222 * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively 223 * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure 224 * group. 225 */ 226 if (p->Op0 == 0) { /* AArch32 */ 227 switch (p->Op1) { 228 default: /* Keep GCC quiet */ 229 case 0: /* ICC_SGI1R */ 230 g1 = true; 231 break; 232 case 1: /* ICC_ASGI1R */ 233 case 2: /* ICC_SGI0R */ 234 g1 = false; 235 break; 236 } 237 } else { /* AArch64 */ 238 switch (p->Op2) { 239 default: /* Keep GCC quiet */ 240 case 5: /* ICC_SGI1R_EL1 */ 241 g1 = true; 242 break; 243 case 6: /* ICC_ASGI1R_EL1 */ 244 case 7: /* ICC_SGI0R_EL1 */ 245 g1 = false; 246 break; 247 } 248 } 249 250 vgic_v3_dispatch_sgi(vcpu, p->regval, g1); 251 252 return true; 253 } 254 255 static bool access_gic_sre(struct kvm_vcpu *vcpu, 256 struct sys_reg_params *p, 257 const struct sys_reg_desc *r) 258 { 259 if (p->is_write) 260 return ignore_write(vcpu, p); 261 262 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre; 263 return true; 264 } 265 266 static bool trap_raz_wi(struct kvm_vcpu *vcpu, 267 struct sys_reg_params *p, 268 const struct sys_reg_desc *r) 269 { 270 if (p->is_write) 271 return ignore_write(vcpu, p); 272 else 273 return read_zero(vcpu, p); 274 } 275 276 static bool trap_undef(struct kvm_vcpu *vcpu, 277 struct sys_reg_params *p, 278 const struct sys_reg_desc *r) 279 { 280 kvm_inject_undefined(vcpu); 281 return false; 282 } 283 284 /* 285 * ARMv8.1 mandates at least a trivial LORegion implementation, where all the 286 * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0 287 * system, these registers should UNDEF. LORID_EL1 being a RO register, we 288 * treat it separately. 289 */ 290 static bool trap_loregion(struct kvm_vcpu *vcpu, 291 struct sys_reg_params *p, 292 const struct sys_reg_desc *r) 293 { 294 u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 295 u32 sr = reg_to_encoding(r); 296 297 if (!(val & (0xfUL << ID_AA64MMFR1_EL1_LO_SHIFT))) { 298 kvm_inject_undefined(vcpu); 299 return false; 300 } 301 302 if (p->is_write && sr == SYS_LORID_EL1) 303 return write_to_read_only(vcpu, p, r); 304 305 return trap_raz_wi(vcpu, p, r); 306 } 307 308 static bool trap_oslar_el1(struct kvm_vcpu *vcpu, 309 struct sys_reg_params *p, 310 const struct sys_reg_desc *r) 311 { 312 u64 oslsr; 313 314 if (!p->is_write) 315 return read_from_write_only(vcpu, p, r); 316 317 /* Forward the OSLK bit to OSLSR */ 318 oslsr = __vcpu_sys_reg(vcpu, OSLSR_EL1) & ~SYS_OSLSR_OSLK; 319 if (p->regval & SYS_OSLAR_OSLK) 320 oslsr |= SYS_OSLSR_OSLK; 321 322 __vcpu_sys_reg(vcpu, OSLSR_EL1) = oslsr; 323 return true; 324 } 325 326 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu, 327 struct sys_reg_params *p, 328 const struct sys_reg_desc *r) 329 { 330 if (p->is_write) 331 return write_to_read_only(vcpu, p, r); 332 333 p->regval = __vcpu_sys_reg(vcpu, r->reg); 334 return true; 335 } 336 337 static int set_oslsr_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 338 u64 val) 339 { 340 /* 341 * The only modifiable bit is the OSLK bit. Refuse the write if 342 * userspace attempts to change any other bit in the register. 343 */ 344 if ((val ^ rd->val) & ~SYS_OSLSR_OSLK) 345 return -EINVAL; 346 347 __vcpu_sys_reg(vcpu, rd->reg) = val; 348 return 0; 349 } 350 351 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu, 352 struct sys_reg_params *p, 353 const struct sys_reg_desc *r) 354 { 355 if (p->is_write) { 356 return ignore_write(vcpu, p); 357 } else { 358 p->regval = read_sysreg(dbgauthstatus_el1); 359 return true; 360 } 361 } 362 363 /* 364 * We want to avoid world-switching all the DBG registers all the 365 * time: 366 * 367 * - If we've touched any debug register, it is likely that we're 368 * going to touch more of them. It then makes sense to disable the 369 * traps and start doing the save/restore dance 370 * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is 371 * then mandatory to save/restore the registers, as the guest 372 * depends on them. 373 * 374 * For this, we use a DIRTY bit, indicating the guest has modified the 375 * debug registers, used as follow: 376 * 377 * On guest entry: 378 * - If the dirty bit is set (because we're coming back from trapping), 379 * disable the traps, save host registers, restore guest registers. 380 * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), 381 * set the dirty bit, disable the traps, save host registers, 382 * restore guest registers. 383 * - Otherwise, enable the traps 384 * 385 * On guest exit: 386 * - If the dirty bit is set, save guest registers, restore host 387 * registers and clear the dirty bit. This ensure that the host can 388 * now use the debug registers. 389 */ 390 static bool trap_debug_regs(struct kvm_vcpu *vcpu, 391 struct sys_reg_params *p, 392 const struct sys_reg_desc *r) 393 { 394 access_rw(vcpu, p, r); 395 if (p->is_write) 396 vcpu_set_flag(vcpu, DEBUG_DIRTY); 397 398 trace_trap_reg(__func__, r->reg, p->is_write, p->regval); 399 400 return true; 401 } 402 403 /* 404 * reg_to_dbg/dbg_to_reg 405 * 406 * A 32 bit write to a debug register leave top bits alone 407 * A 32 bit read from a debug register only returns the bottom bits 408 * 409 * All writes will set the DEBUG_DIRTY flag to ensure the hyp code 410 * switches between host and guest values in future. 411 */ 412 static void reg_to_dbg(struct kvm_vcpu *vcpu, 413 struct sys_reg_params *p, 414 const struct sys_reg_desc *rd, 415 u64 *dbg_reg) 416 { 417 u64 mask, shift, val; 418 419 get_access_mask(rd, &mask, &shift); 420 421 val = *dbg_reg; 422 val &= ~mask; 423 val |= (p->regval & (mask >> shift)) << shift; 424 *dbg_reg = val; 425 426 vcpu_set_flag(vcpu, DEBUG_DIRTY); 427 } 428 429 static void dbg_to_reg(struct kvm_vcpu *vcpu, 430 struct sys_reg_params *p, 431 const struct sys_reg_desc *rd, 432 u64 *dbg_reg) 433 { 434 u64 mask, shift; 435 436 get_access_mask(rd, &mask, &shift); 437 p->regval = (*dbg_reg & mask) >> shift; 438 } 439 440 static bool trap_bvr(struct kvm_vcpu *vcpu, 441 struct sys_reg_params *p, 442 const struct sys_reg_desc *rd) 443 { 444 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm]; 445 446 if (p->is_write) 447 reg_to_dbg(vcpu, p, rd, dbg_reg); 448 else 449 dbg_to_reg(vcpu, p, rd, dbg_reg); 450 451 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); 452 453 return true; 454 } 455 456 static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 457 u64 val) 458 { 459 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = val; 460 return 0; 461 } 462 463 static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 464 u64 *val) 465 { 466 *val = vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm]; 467 return 0; 468 } 469 470 static void reset_bvr(struct kvm_vcpu *vcpu, 471 const struct sys_reg_desc *rd) 472 { 473 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = rd->val; 474 } 475 476 static bool trap_bcr(struct kvm_vcpu *vcpu, 477 struct sys_reg_params *p, 478 const struct sys_reg_desc *rd) 479 { 480 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm]; 481 482 if (p->is_write) 483 reg_to_dbg(vcpu, p, rd, dbg_reg); 484 else 485 dbg_to_reg(vcpu, p, rd, dbg_reg); 486 487 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); 488 489 return true; 490 } 491 492 static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 493 u64 val) 494 { 495 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = val; 496 return 0; 497 } 498 499 static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 500 u64 *val) 501 { 502 *val = vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm]; 503 return 0; 504 } 505 506 static void reset_bcr(struct kvm_vcpu *vcpu, 507 const struct sys_reg_desc *rd) 508 { 509 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = rd->val; 510 } 511 512 static bool trap_wvr(struct kvm_vcpu *vcpu, 513 struct sys_reg_params *p, 514 const struct sys_reg_desc *rd) 515 { 516 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]; 517 518 if (p->is_write) 519 reg_to_dbg(vcpu, p, rd, dbg_reg); 520 else 521 dbg_to_reg(vcpu, p, rd, dbg_reg); 522 523 trace_trap_reg(__func__, rd->CRm, p->is_write, 524 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]); 525 526 return true; 527 } 528 529 static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 530 u64 val) 531 { 532 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = val; 533 return 0; 534 } 535 536 static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 537 u64 *val) 538 { 539 *val = vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]; 540 return 0; 541 } 542 543 static void reset_wvr(struct kvm_vcpu *vcpu, 544 const struct sys_reg_desc *rd) 545 { 546 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = rd->val; 547 } 548 549 static bool trap_wcr(struct kvm_vcpu *vcpu, 550 struct sys_reg_params *p, 551 const struct sys_reg_desc *rd) 552 { 553 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm]; 554 555 if (p->is_write) 556 reg_to_dbg(vcpu, p, rd, dbg_reg); 557 else 558 dbg_to_reg(vcpu, p, rd, dbg_reg); 559 560 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); 561 562 return true; 563 } 564 565 static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 566 u64 val) 567 { 568 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = val; 569 return 0; 570 } 571 572 static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 573 u64 *val) 574 { 575 *val = vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm]; 576 return 0; 577 } 578 579 static void reset_wcr(struct kvm_vcpu *vcpu, 580 const struct sys_reg_desc *rd) 581 { 582 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = rd->val; 583 } 584 585 static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 586 { 587 u64 amair = read_sysreg(amair_el1); 588 vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1); 589 } 590 591 static void reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 592 { 593 u64 actlr = read_sysreg(actlr_el1); 594 vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1); 595 } 596 597 static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 598 { 599 u64 mpidr; 600 601 /* 602 * Map the vcpu_id into the first three affinity level fields of 603 * the MPIDR. We limit the number of VCPUs in level 0 due to a 604 * limitation to 16 CPUs in that level in the ICC_SGIxR registers 605 * of the GICv3 to be able to address each CPU directly when 606 * sending IPIs. 607 */ 608 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0); 609 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1); 610 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2); 611 vcpu_write_sys_reg(vcpu, (1ULL << 31) | mpidr, MPIDR_EL1); 612 } 613 614 static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu, 615 const struct sys_reg_desc *r) 616 { 617 if (kvm_vcpu_has_pmu(vcpu)) 618 return 0; 619 620 return REG_HIDDEN; 621 } 622 623 static void reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 624 { 625 u64 n, mask = BIT(ARMV8_PMU_CYCLE_IDX); 626 627 /* No PMU available, any PMU reg may UNDEF... */ 628 if (!kvm_arm_support_pmu_v3()) 629 return; 630 631 n = read_sysreg(pmcr_el0) >> ARMV8_PMU_PMCR_N_SHIFT; 632 n &= ARMV8_PMU_PMCR_N_MASK; 633 if (n) 634 mask |= GENMASK(n - 1, 0); 635 636 reset_unknown(vcpu, r); 637 __vcpu_sys_reg(vcpu, r->reg) &= mask; 638 } 639 640 static void reset_pmevcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 641 { 642 reset_unknown(vcpu, r); 643 __vcpu_sys_reg(vcpu, r->reg) &= GENMASK(31, 0); 644 } 645 646 static void reset_pmevtyper(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 647 { 648 reset_unknown(vcpu, r); 649 __vcpu_sys_reg(vcpu, r->reg) &= ARMV8_PMU_EVTYPE_MASK; 650 } 651 652 static void reset_pmselr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 653 { 654 reset_unknown(vcpu, r); 655 __vcpu_sys_reg(vcpu, r->reg) &= ARMV8_PMU_COUNTER_MASK; 656 } 657 658 static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 659 { 660 u64 pmcr; 661 662 /* No PMU available, PMCR_EL0 may UNDEF... */ 663 if (!kvm_arm_support_pmu_v3()) 664 return; 665 666 /* Only preserve PMCR_EL0.N, and reset the rest to 0 */ 667 pmcr = read_sysreg(pmcr_el0) & (ARMV8_PMU_PMCR_N_MASK << ARMV8_PMU_PMCR_N_SHIFT); 668 if (!kvm_supports_32bit_el0()) 669 pmcr |= ARMV8_PMU_PMCR_LC; 670 671 __vcpu_sys_reg(vcpu, r->reg) = pmcr; 672 } 673 674 static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags) 675 { 676 u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0); 677 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu); 678 679 if (!enabled) 680 kvm_inject_undefined(vcpu); 681 682 return !enabled; 683 } 684 685 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu) 686 { 687 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN); 688 } 689 690 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu) 691 { 692 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN); 693 } 694 695 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu) 696 { 697 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN); 698 } 699 700 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu) 701 { 702 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN); 703 } 704 705 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 706 const struct sys_reg_desc *r) 707 { 708 u64 val; 709 710 if (pmu_access_el0_disabled(vcpu)) 711 return false; 712 713 if (p->is_write) { 714 /* 715 * Only update writeable bits of PMCR (continuing into 716 * kvm_pmu_handle_pmcr() as well) 717 */ 718 val = __vcpu_sys_reg(vcpu, PMCR_EL0); 719 val &= ~ARMV8_PMU_PMCR_MASK; 720 val |= p->regval & ARMV8_PMU_PMCR_MASK; 721 if (!kvm_supports_32bit_el0()) 722 val |= ARMV8_PMU_PMCR_LC; 723 kvm_pmu_handle_pmcr(vcpu, val); 724 kvm_vcpu_pmu_restore_guest(vcpu); 725 } else { 726 /* PMCR.P & PMCR.C are RAZ */ 727 val = __vcpu_sys_reg(vcpu, PMCR_EL0) 728 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C); 729 p->regval = val; 730 } 731 732 return true; 733 } 734 735 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 736 const struct sys_reg_desc *r) 737 { 738 if (pmu_access_event_counter_el0_disabled(vcpu)) 739 return false; 740 741 if (p->is_write) 742 __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval; 743 else 744 /* return PMSELR.SEL field */ 745 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0) 746 & ARMV8_PMU_COUNTER_MASK; 747 748 return true; 749 } 750 751 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 752 const struct sys_reg_desc *r) 753 { 754 u64 pmceid, mask, shift; 755 756 BUG_ON(p->is_write); 757 758 if (pmu_access_el0_disabled(vcpu)) 759 return false; 760 761 get_access_mask(r, &mask, &shift); 762 763 pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1)); 764 pmceid &= mask; 765 pmceid >>= shift; 766 767 p->regval = pmceid; 768 769 return true; 770 } 771 772 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx) 773 { 774 u64 pmcr, val; 775 776 pmcr = __vcpu_sys_reg(vcpu, PMCR_EL0); 777 val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK; 778 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) { 779 kvm_inject_undefined(vcpu); 780 return false; 781 } 782 783 return true; 784 } 785 786 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu, 787 struct sys_reg_params *p, 788 const struct sys_reg_desc *r) 789 { 790 u64 idx = ~0UL; 791 792 if (r->CRn == 9 && r->CRm == 13) { 793 if (r->Op2 == 2) { 794 /* PMXEVCNTR_EL0 */ 795 if (pmu_access_event_counter_el0_disabled(vcpu)) 796 return false; 797 798 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) 799 & ARMV8_PMU_COUNTER_MASK; 800 } else if (r->Op2 == 0) { 801 /* PMCCNTR_EL0 */ 802 if (pmu_access_cycle_counter_el0_disabled(vcpu)) 803 return false; 804 805 idx = ARMV8_PMU_CYCLE_IDX; 806 } 807 } else if (r->CRn == 0 && r->CRm == 9) { 808 /* PMCCNTR */ 809 if (pmu_access_event_counter_el0_disabled(vcpu)) 810 return false; 811 812 idx = ARMV8_PMU_CYCLE_IDX; 813 } else if (r->CRn == 14 && (r->CRm & 12) == 8) { 814 /* PMEVCNTRn_EL0 */ 815 if (pmu_access_event_counter_el0_disabled(vcpu)) 816 return false; 817 818 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 819 } 820 821 /* Catch any decoding mistake */ 822 WARN_ON(idx == ~0UL); 823 824 if (!pmu_counter_idx_valid(vcpu, idx)) 825 return false; 826 827 if (p->is_write) { 828 if (pmu_access_el0_disabled(vcpu)) 829 return false; 830 831 kvm_pmu_set_counter_value(vcpu, idx, p->regval); 832 } else { 833 p->regval = kvm_pmu_get_counter_value(vcpu, idx); 834 } 835 836 return true; 837 } 838 839 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 840 const struct sys_reg_desc *r) 841 { 842 u64 idx, reg; 843 844 if (pmu_access_el0_disabled(vcpu)) 845 return false; 846 847 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) { 848 /* PMXEVTYPER_EL0 */ 849 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK; 850 reg = PMEVTYPER0_EL0 + idx; 851 } else if (r->CRn == 14 && (r->CRm & 12) == 12) { 852 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 853 if (idx == ARMV8_PMU_CYCLE_IDX) 854 reg = PMCCFILTR_EL0; 855 else 856 /* PMEVTYPERn_EL0 */ 857 reg = PMEVTYPER0_EL0 + idx; 858 } else { 859 BUG(); 860 } 861 862 if (!pmu_counter_idx_valid(vcpu, idx)) 863 return false; 864 865 if (p->is_write) { 866 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx); 867 __vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK; 868 kvm_vcpu_pmu_restore_guest(vcpu); 869 } else { 870 p->regval = __vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK; 871 } 872 873 return true; 874 } 875 876 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 877 const struct sys_reg_desc *r) 878 { 879 u64 val, mask; 880 881 if (pmu_access_el0_disabled(vcpu)) 882 return false; 883 884 mask = kvm_pmu_valid_counter_mask(vcpu); 885 if (p->is_write) { 886 val = p->regval & mask; 887 if (r->Op2 & 0x1) { 888 /* accessing PMCNTENSET_EL0 */ 889 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val; 890 kvm_pmu_enable_counter_mask(vcpu, val); 891 kvm_vcpu_pmu_restore_guest(vcpu); 892 } else { 893 /* accessing PMCNTENCLR_EL0 */ 894 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val; 895 kvm_pmu_disable_counter_mask(vcpu, val); 896 } 897 } else { 898 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0); 899 } 900 901 return true; 902 } 903 904 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 905 const struct sys_reg_desc *r) 906 { 907 u64 mask = kvm_pmu_valid_counter_mask(vcpu); 908 909 if (check_pmu_access_disabled(vcpu, 0)) 910 return false; 911 912 if (p->is_write) { 913 u64 val = p->regval & mask; 914 915 if (r->Op2 & 0x1) 916 /* accessing PMINTENSET_EL1 */ 917 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val; 918 else 919 /* accessing PMINTENCLR_EL1 */ 920 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val; 921 } else { 922 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1); 923 } 924 925 return true; 926 } 927 928 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 929 const struct sys_reg_desc *r) 930 { 931 u64 mask = kvm_pmu_valid_counter_mask(vcpu); 932 933 if (pmu_access_el0_disabled(vcpu)) 934 return false; 935 936 if (p->is_write) { 937 if (r->CRm & 0x2) 938 /* accessing PMOVSSET_EL0 */ 939 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask); 940 else 941 /* accessing PMOVSCLR_EL0 */ 942 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask); 943 } else { 944 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0); 945 } 946 947 return true; 948 } 949 950 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 951 const struct sys_reg_desc *r) 952 { 953 u64 mask; 954 955 if (!p->is_write) 956 return read_from_write_only(vcpu, p, r); 957 958 if (pmu_write_swinc_el0_disabled(vcpu)) 959 return false; 960 961 mask = kvm_pmu_valid_counter_mask(vcpu); 962 kvm_pmu_software_increment(vcpu, p->regval & mask); 963 return true; 964 } 965 966 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 967 const struct sys_reg_desc *r) 968 { 969 if (p->is_write) { 970 if (!vcpu_mode_priv(vcpu)) { 971 kvm_inject_undefined(vcpu); 972 return false; 973 } 974 975 __vcpu_sys_reg(vcpu, PMUSERENR_EL0) = 976 p->regval & ARMV8_PMU_USERENR_MASK; 977 } else { 978 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0) 979 & ARMV8_PMU_USERENR_MASK; 980 } 981 982 return true; 983 } 984 985 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */ 986 #define DBG_BCR_BVR_WCR_WVR_EL1(n) \ 987 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \ 988 trap_bvr, reset_bvr, 0, 0, get_bvr, set_bvr }, \ 989 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \ 990 trap_bcr, reset_bcr, 0, 0, get_bcr, set_bcr }, \ 991 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \ 992 trap_wvr, reset_wvr, 0, 0, get_wvr, set_wvr }, \ 993 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \ 994 trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr } 995 996 #define PMU_SYS_REG(r) \ 997 SYS_DESC(r), .reset = reset_pmu_reg, .visibility = pmu_visibility 998 999 /* Macro to expand the PMEVCNTRn_EL0 register */ 1000 #define PMU_PMEVCNTR_EL0(n) \ 1001 { PMU_SYS_REG(SYS_PMEVCNTRn_EL0(n)), \ 1002 .reset = reset_pmevcntr, \ 1003 .access = access_pmu_evcntr, .reg = (PMEVCNTR0_EL0 + n), } 1004 1005 /* Macro to expand the PMEVTYPERn_EL0 register */ 1006 #define PMU_PMEVTYPER_EL0(n) \ 1007 { PMU_SYS_REG(SYS_PMEVTYPERn_EL0(n)), \ 1008 .reset = reset_pmevtyper, \ 1009 .access = access_pmu_evtyper, .reg = (PMEVTYPER0_EL0 + n), } 1010 1011 static bool undef_access(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1012 const struct sys_reg_desc *r) 1013 { 1014 kvm_inject_undefined(vcpu); 1015 1016 return false; 1017 } 1018 1019 /* Macro to expand the AMU counter and type registers*/ 1020 #define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), undef_access } 1021 #define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), undef_access } 1022 #define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), undef_access } 1023 #define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), undef_access } 1024 1025 static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu, 1026 const struct sys_reg_desc *rd) 1027 { 1028 return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN; 1029 } 1030 1031 /* 1032 * If we land here on a PtrAuth access, that is because we didn't 1033 * fixup the access on exit by allowing the PtrAuth sysregs. The only 1034 * way this happens is when the guest does not have PtrAuth support 1035 * enabled. 1036 */ 1037 #define __PTRAUTH_KEY(k) \ 1038 { SYS_DESC(SYS_## k), undef_access, reset_unknown, k, \ 1039 .visibility = ptrauth_visibility} 1040 1041 #define PTRAUTH_KEY(k) \ 1042 __PTRAUTH_KEY(k ## KEYLO_EL1), \ 1043 __PTRAUTH_KEY(k ## KEYHI_EL1) 1044 1045 static bool access_arch_timer(struct kvm_vcpu *vcpu, 1046 struct sys_reg_params *p, 1047 const struct sys_reg_desc *r) 1048 { 1049 enum kvm_arch_timers tmr; 1050 enum kvm_arch_timer_regs treg; 1051 u64 reg = reg_to_encoding(r); 1052 1053 switch (reg) { 1054 case SYS_CNTP_TVAL_EL0: 1055 case SYS_AARCH32_CNTP_TVAL: 1056 tmr = TIMER_PTIMER; 1057 treg = TIMER_REG_TVAL; 1058 break; 1059 case SYS_CNTP_CTL_EL0: 1060 case SYS_AARCH32_CNTP_CTL: 1061 tmr = TIMER_PTIMER; 1062 treg = TIMER_REG_CTL; 1063 break; 1064 case SYS_CNTP_CVAL_EL0: 1065 case SYS_AARCH32_CNTP_CVAL: 1066 tmr = TIMER_PTIMER; 1067 treg = TIMER_REG_CVAL; 1068 break; 1069 default: 1070 BUG(); 1071 } 1072 1073 if (p->is_write) 1074 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval); 1075 else 1076 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg); 1077 1078 return true; 1079 } 1080 1081 static u8 vcpu_pmuver(const struct kvm_vcpu *vcpu) 1082 { 1083 if (kvm_vcpu_has_pmu(vcpu)) 1084 return vcpu->kvm->arch.dfr0_pmuver.imp; 1085 1086 return vcpu->kvm->arch.dfr0_pmuver.unimp; 1087 } 1088 1089 static u8 perfmon_to_pmuver(u8 perfmon) 1090 { 1091 switch (perfmon) { 1092 case ID_DFR0_EL1_PerfMon_PMUv3: 1093 return ID_AA64DFR0_EL1_PMUVer_IMP; 1094 case ID_DFR0_EL1_PerfMon_IMPDEF: 1095 return ID_AA64DFR0_EL1_PMUVer_IMP_DEF; 1096 default: 1097 /* Anything ARMv8.1+ and NI have the same value. For now. */ 1098 return perfmon; 1099 } 1100 } 1101 1102 static u8 pmuver_to_perfmon(u8 pmuver) 1103 { 1104 switch (pmuver) { 1105 case ID_AA64DFR0_EL1_PMUVer_IMP: 1106 return ID_DFR0_EL1_PerfMon_PMUv3; 1107 case ID_AA64DFR0_EL1_PMUVer_IMP_DEF: 1108 return ID_DFR0_EL1_PerfMon_IMPDEF; 1109 default: 1110 /* Anything ARMv8.1+ and NI have the same value. For now. */ 1111 return pmuver; 1112 } 1113 } 1114 1115 /* Read a sanitised cpufeature ID register by sys_reg_desc */ 1116 static u64 read_id_reg(const struct kvm_vcpu *vcpu, struct sys_reg_desc const *r) 1117 { 1118 u32 id = reg_to_encoding(r); 1119 u64 val; 1120 1121 if (sysreg_visible_as_raz(vcpu, r)) 1122 return 0; 1123 1124 val = read_sanitised_ftr_reg(id); 1125 1126 switch (id) { 1127 case SYS_ID_AA64PFR0_EL1: 1128 if (!vcpu_has_sve(vcpu)) 1129 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_SVE); 1130 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AMU); 1131 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2); 1132 val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2), (u64)vcpu->kvm->arch.pfr0_csv2); 1133 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3); 1134 val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3), (u64)vcpu->kvm->arch.pfr0_csv3); 1135 if (kvm_vgic_global_state.type == VGIC_V3) { 1136 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC); 1137 val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC), 1); 1138 } 1139 break; 1140 case SYS_ID_AA64PFR1_EL1: 1141 if (!kvm_has_mte(vcpu->kvm)) 1142 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE); 1143 1144 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_SME); 1145 break; 1146 case SYS_ID_AA64ISAR1_EL1: 1147 if (!vcpu_has_ptrauth(vcpu)) 1148 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) | 1149 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) | 1150 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) | 1151 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI)); 1152 break; 1153 case SYS_ID_AA64ISAR2_EL1: 1154 if (!vcpu_has_ptrauth(vcpu)) 1155 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) | 1156 ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3)); 1157 if (!cpus_have_final_cap(ARM64_HAS_WFXT)) 1158 val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT); 1159 break; 1160 case SYS_ID_AA64DFR0_EL1: 1161 /* Limit debug to ARMv8.0 */ 1162 val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer); 1163 val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer), 6); 1164 /* Set PMUver to the required version */ 1165 val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer); 1166 val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), 1167 vcpu_pmuver(vcpu)); 1168 /* Hide SPE from guests */ 1169 val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMSVer); 1170 break; 1171 case SYS_ID_DFR0_EL1: 1172 val &= ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon); 1173 val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon), 1174 pmuver_to_perfmon(vcpu_pmuver(vcpu))); 1175 break; 1176 } 1177 1178 return val; 1179 } 1180 1181 static unsigned int id_visibility(const struct kvm_vcpu *vcpu, 1182 const struct sys_reg_desc *r) 1183 { 1184 u32 id = reg_to_encoding(r); 1185 1186 switch (id) { 1187 case SYS_ID_AA64ZFR0_EL1: 1188 if (!vcpu_has_sve(vcpu)) 1189 return REG_RAZ; 1190 break; 1191 } 1192 1193 return 0; 1194 } 1195 1196 static unsigned int aa32_id_visibility(const struct kvm_vcpu *vcpu, 1197 const struct sys_reg_desc *r) 1198 { 1199 /* 1200 * AArch32 ID registers are UNKNOWN if AArch32 isn't implemented at any 1201 * EL. Promote to RAZ/WI in order to guarantee consistency between 1202 * systems. 1203 */ 1204 if (!kvm_supports_32bit_el0()) 1205 return REG_RAZ | REG_USER_WI; 1206 1207 return id_visibility(vcpu, r); 1208 } 1209 1210 static unsigned int raz_visibility(const struct kvm_vcpu *vcpu, 1211 const struct sys_reg_desc *r) 1212 { 1213 return REG_RAZ; 1214 } 1215 1216 /* cpufeature ID register access trap handlers */ 1217 1218 static bool access_id_reg(struct kvm_vcpu *vcpu, 1219 struct sys_reg_params *p, 1220 const struct sys_reg_desc *r) 1221 { 1222 if (p->is_write) 1223 return write_to_read_only(vcpu, p, r); 1224 1225 p->regval = read_id_reg(vcpu, r); 1226 return true; 1227 } 1228 1229 /* Visibility overrides for SVE-specific control registers */ 1230 static unsigned int sve_visibility(const struct kvm_vcpu *vcpu, 1231 const struct sys_reg_desc *rd) 1232 { 1233 if (vcpu_has_sve(vcpu)) 1234 return 0; 1235 1236 return REG_HIDDEN; 1237 } 1238 1239 static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, 1240 const struct sys_reg_desc *rd, 1241 u64 val) 1242 { 1243 u8 csv2, csv3; 1244 1245 /* 1246 * Allow AA64PFR0_EL1.CSV2 to be set from userspace as long as 1247 * it doesn't promise more than what is actually provided (the 1248 * guest could otherwise be covered in ectoplasmic residue). 1249 */ 1250 csv2 = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR0_EL1_CSV2_SHIFT); 1251 if (csv2 > 1 || 1252 (csv2 && arm64_get_spectre_v2_state() != SPECTRE_UNAFFECTED)) 1253 return -EINVAL; 1254 1255 /* Same thing for CSV3 */ 1256 csv3 = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR0_EL1_CSV3_SHIFT); 1257 if (csv3 > 1 || 1258 (csv3 && arm64_get_meltdown_state() != SPECTRE_UNAFFECTED)) 1259 return -EINVAL; 1260 1261 /* We can only differ with CSV[23], and anything else is an error */ 1262 val ^= read_id_reg(vcpu, rd); 1263 val &= ~(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2) | 1264 ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3)); 1265 if (val) 1266 return -EINVAL; 1267 1268 vcpu->kvm->arch.pfr0_csv2 = csv2; 1269 vcpu->kvm->arch.pfr0_csv3 = csv3; 1270 1271 return 0; 1272 } 1273 1274 static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, 1275 const struct sys_reg_desc *rd, 1276 u64 val) 1277 { 1278 u8 pmuver, host_pmuver; 1279 bool valid_pmu; 1280 1281 host_pmuver = kvm_arm_pmu_get_pmuver_limit(); 1282 1283 /* 1284 * Allow AA64DFR0_EL1.PMUver to be set from userspace as long 1285 * as it doesn't promise more than what the HW gives us. We 1286 * allow an IMPDEF PMU though, only if no PMU is supported 1287 * (KVM backward compatibility handling). 1288 */ 1289 pmuver = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), val); 1290 if ((pmuver != ID_AA64DFR0_EL1_PMUVer_IMP_DEF && pmuver > host_pmuver)) 1291 return -EINVAL; 1292 1293 valid_pmu = (pmuver != 0 && pmuver != ID_AA64DFR0_EL1_PMUVer_IMP_DEF); 1294 1295 /* Make sure view register and PMU support do match */ 1296 if (kvm_vcpu_has_pmu(vcpu) != valid_pmu) 1297 return -EINVAL; 1298 1299 /* We can only differ with PMUver, and anything else is an error */ 1300 val ^= read_id_reg(vcpu, rd); 1301 val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer); 1302 if (val) 1303 return -EINVAL; 1304 1305 if (valid_pmu) 1306 vcpu->kvm->arch.dfr0_pmuver.imp = pmuver; 1307 else 1308 vcpu->kvm->arch.dfr0_pmuver.unimp = pmuver; 1309 1310 return 0; 1311 } 1312 1313 static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, 1314 const struct sys_reg_desc *rd, 1315 u64 val) 1316 { 1317 u8 perfmon, host_perfmon; 1318 bool valid_pmu; 1319 1320 host_perfmon = pmuver_to_perfmon(kvm_arm_pmu_get_pmuver_limit()); 1321 1322 /* 1323 * Allow DFR0_EL1.PerfMon to be set from userspace as long as 1324 * it doesn't promise more than what the HW gives us on the 1325 * AArch64 side (as everything is emulated with that), and 1326 * that this is a PMUv3. 1327 */ 1328 perfmon = FIELD_GET(ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon), val); 1329 if ((perfmon != ID_DFR0_EL1_PerfMon_IMPDEF && perfmon > host_perfmon) || 1330 (perfmon != 0 && perfmon < ID_DFR0_EL1_PerfMon_PMUv3)) 1331 return -EINVAL; 1332 1333 valid_pmu = (perfmon != 0 && perfmon != ID_DFR0_EL1_PerfMon_IMPDEF); 1334 1335 /* Make sure view register and PMU support do match */ 1336 if (kvm_vcpu_has_pmu(vcpu) != valid_pmu) 1337 return -EINVAL; 1338 1339 /* We can only differ with PerfMon, and anything else is an error */ 1340 val ^= read_id_reg(vcpu, rd); 1341 val &= ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon); 1342 if (val) 1343 return -EINVAL; 1344 1345 if (valid_pmu) 1346 vcpu->kvm->arch.dfr0_pmuver.imp = perfmon_to_pmuver(perfmon); 1347 else 1348 vcpu->kvm->arch.dfr0_pmuver.unimp = perfmon_to_pmuver(perfmon); 1349 1350 return 0; 1351 } 1352 1353 /* 1354 * cpufeature ID register user accessors 1355 * 1356 * For now, these registers are immutable for userspace, so no values 1357 * are stored, and for set_id_reg() we don't allow the effective value 1358 * to be changed. 1359 */ 1360 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1361 u64 *val) 1362 { 1363 *val = read_id_reg(vcpu, rd); 1364 return 0; 1365 } 1366 1367 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1368 u64 val) 1369 { 1370 /* This is what we mean by invariant: you can't change it. */ 1371 if (val != read_id_reg(vcpu, rd)) 1372 return -EINVAL; 1373 1374 return 0; 1375 } 1376 1377 static int get_raz_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1378 u64 *val) 1379 { 1380 *val = 0; 1381 return 0; 1382 } 1383 1384 static int set_wi_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1385 u64 val) 1386 { 1387 return 0; 1388 } 1389 1390 static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1391 const struct sys_reg_desc *r) 1392 { 1393 if (p->is_write) 1394 return write_to_read_only(vcpu, p, r); 1395 1396 p->regval = read_sanitised_ftr_reg(SYS_CTR_EL0); 1397 return true; 1398 } 1399 1400 static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1401 const struct sys_reg_desc *r) 1402 { 1403 if (p->is_write) 1404 return write_to_read_only(vcpu, p, r); 1405 1406 p->regval = read_sysreg(clidr_el1); 1407 return true; 1408 } 1409 1410 static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1411 const struct sys_reg_desc *r) 1412 { 1413 int reg = r->reg; 1414 1415 if (p->is_write) 1416 vcpu_write_sys_reg(vcpu, p->regval, reg); 1417 else 1418 p->regval = vcpu_read_sys_reg(vcpu, reg); 1419 return true; 1420 } 1421 1422 static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1423 const struct sys_reg_desc *r) 1424 { 1425 u32 csselr; 1426 1427 if (p->is_write) 1428 return write_to_read_only(vcpu, p, r); 1429 1430 csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1); 1431 p->regval = get_ccsidr(csselr); 1432 1433 /* 1434 * Guests should not be doing cache operations by set/way at all, and 1435 * for this reason, we trap them and attempt to infer the intent, so 1436 * that we can flush the entire guest's address space at the appropriate 1437 * time. 1438 * To prevent this trapping from causing performance problems, let's 1439 * expose the geometry of all data and unified caches (which are 1440 * guaranteed to be PIPT and thus non-aliasing) as 1 set and 1 way. 1441 * [If guests should attempt to infer aliasing properties from the 1442 * geometry (which is not permitted by the architecture), they would 1443 * only do so for virtually indexed caches.] 1444 */ 1445 if (!(csselr & 1)) // data or unified cache 1446 p->regval &= ~GENMASK(27, 3); 1447 return true; 1448 } 1449 1450 static unsigned int mte_visibility(const struct kvm_vcpu *vcpu, 1451 const struct sys_reg_desc *rd) 1452 { 1453 if (kvm_has_mte(vcpu->kvm)) 1454 return 0; 1455 1456 return REG_HIDDEN; 1457 } 1458 1459 #define MTE_REG(name) { \ 1460 SYS_DESC(SYS_##name), \ 1461 .access = undef_access, \ 1462 .reset = reset_unknown, \ 1463 .reg = name, \ 1464 .visibility = mte_visibility, \ 1465 } 1466 1467 static unsigned int el2_visibility(const struct kvm_vcpu *vcpu, 1468 const struct sys_reg_desc *rd) 1469 { 1470 if (vcpu_has_nv(vcpu)) 1471 return 0; 1472 1473 return REG_HIDDEN; 1474 } 1475 1476 #define EL2_REG(name, acc, rst, v) { \ 1477 SYS_DESC(SYS_##name), \ 1478 .access = acc, \ 1479 .reset = rst, \ 1480 .reg = name, \ 1481 .visibility = el2_visibility, \ 1482 .val = v, \ 1483 } 1484 1485 /* 1486 * EL{0,1}2 registers are the EL2 view on an EL0 or EL1 register when 1487 * HCR_EL2.E2H==1, and only in the sysreg table for convenience of 1488 * handling traps. Given that, they are always hidden from userspace. 1489 */ 1490 static unsigned int elx2_visibility(const struct kvm_vcpu *vcpu, 1491 const struct sys_reg_desc *rd) 1492 { 1493 return REG_HIDDEN_USER; 1494 } 1495 1496 #define EL12_REG(name, acc, rst, v) { \ 1497 SYS_DESC(SYS_##name##_EL12), \ 1498 .access = acc, \ 1499 .reset = rst, \ 1500 .reg = name##_EL1, \ 1501 .val = v, \ 1502 .visibility = elx2_visibility, \ 1503 } 1504 1505 /* sys_reg_desc initialiser for known cpufeature ID registers */ 1506 #define ID_SANITISED(name) { \ 1507 SYS_DESC(SYS_##name), \ 1508 .access = access_id_reg, \ 1509 .get_user = get_id_reg, \ 1510 .set_user = set_id_reg, \ 1511 .visibility = id_visibility, \ 1512 } 1513 1514 /* sys_reg_desc initialiser for known cpufeature ID registers */ 1515 #define AA32_ID_SANITISED(name) { \ 1516 SYS_DESC(SYS_##name), \ 1517 .access = access_id_reg, \ 1518 .get_user = get_id_reg, \ 1519 .set_user = set_id_reg, \ 1520 .visibility = aa32_id_visibility, \ 1521 } 1522 1523 /* 1524 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID 1525 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2 1526 * (1 <= crm < 8, 0 <= Op2 < 8). 1527 */ 1528 #define ID_UNALLOCATED(crm, op2) { \ 1529 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \ 1530 .access = access_id_reg, \ 1531 .get_user = get_id_reg, \ 1532 .set_user = set_id_reg, \ 1533 .visibility = raz_visibility \ 1534 } 1535 1536 /* 1537 * sys_reg_desc initialiser for known ID registers that we hide from guests. 1538 * For now, these are exposed just like unallocated ID regs: they appear 1539 * RAZ for the guest. 1540 */ 1541 #define ID_HIDDEN(name) { \ 1542 SYS_DESC(SYS_##name), \ 1543 .access = access_id_reg, \ 1544 .get_user = get_id_reg, \ 1545 .set_user = set_id_reg, \ 1546 .visibility = raz_visibility, \ 1547 } 1548 1549 static bool access_sp_el1(struct kvm_vcpu *vcpu, 1550 struct sys_reg_params *p, 1551 const struct sys_reg_desc *r) 1552 { 1553 if (p->is_write) 1554 __vcpu_sys_reg(vcpu, SP_EL1) = p->regval; 1555 else 1556 p->regval = __vcpu_sys_reg(vcpu, SP_EL1); 1557 1558 return true; 1559 } 1560 1561 static bool access_elr(struct kvm_vcpu *vcpu, 1562 struct sys_reg_params *p, 1563 const struct sys_reg_desc *r) 1564 { 1565 if (p->is_write) 1566 vcpu_write_sys_reg(vcpu, p->regval, ELR_EL1); 1567 else 1568 p->regval = vcpu_read_sys_reg(vcpu, ELR_EL1); 1569 1570 return true; 1571 } 1572 1573 static bool access_spsr(struct kvm_vcpu *vcpu, 1574 struct sys_reg_params *p, 1575 const struct sys_reg_desc *r) 1576 { 1577 if (p->is_write) 1578 __vcpu_sys_reg(vcpu, SPSR_EL1) = p->regval; 1579 else 1580 p->regval = __vcpu_sys_reg(vcpu, SPSR_EL1); 1581 1582 return true; 1583 } 1584 1585 /* 1586 * Architected system registers. 1587 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2 1588 * 1589 * Debug handling: We do trap most, if not all debug related system 1590 * registers. The implementation is good enough to ensure that a guest 1591 * can use these with minimal performance degradation. The drawback is 1592 * that we don't implement any of the external debug architecture. 1593 * This should be revisited if we ever encounter a more demanding 1594 * guest... 1595 */ 1596 static const struct sys_reg_desc sys_reg_descs[] = { 1597 { SYS_DESC(SYS_DC_ISW), access_dcsw }, 1598 { SYS_DESC(SYS_DC_CSW), access_dcsw }, 1599 { SYS_DESC(SYS_DC_CISW), access_dcsw }, 1600 1601 DBG_BCR_BVR_WCR_WVR_EL1(0), 1602 DBG_BCR_BVR_WCR_WVR_EL1(1), 1603 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 }, 1604 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 }, 1605 DBG_BCR_BVR_WCR_WVR_EL1(2), 1606 DBG_BCR_BVR_WCR_WVR_EL1(3), 1607 DBG_BCR_BVR_WCR_WVR_EL1(4), 1608 DBG_BCR_BVR_WCR_WVR_EL1(5), 1609 DBG_BCR_BVR_WCR_WVR_EL1(6), 1610 DBG_BCR_BVR_WCR_WVR_EL1(7), 1611 DBG_BCR_BVR_WCR_WVR_EL1(8), 1612 DBG_BCR_BVR_WCR_WVR_EL1(9), 1613 DBG_BCR_BVR_WCR_WVR_EL1(10), 1614 DBG_BCR_BVR_WCR_WVR_EL1(11), 1615 DBG_BCR_BVR_WCR_WVR_EL1(12), 1616 DBG_BCR_BVR_WCR_WVR_EL1(13), 1617 DBG_BCR_BVR_WCR_WVR_EL1(14), 1618 DBG_BCR_BVR_WCR_WVR_EL1(15), 1619 1620 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi }, 1621 { SYS_DESC(SYS_OSLAR_EL1), trap_oslar_el1 }, 1622 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1, 1623 SYS_OSLSR_OSLM_IMPLEMENTED, .set_user = set_oslsr_el1, }, 1624 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi }, 1625 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi }, 1626 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi }, 1627 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi }, 1628 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 }, 1629 1630 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi }, 1631 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi }, 1632 // DBGDTR[TR]X_EL0 share the same encoding 1633 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi }, 1634 1635 { SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 }, 1636 1637 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 }, 1638 1639 /* 1640 * ID regs: all ID_SANITISED() entries here must have corresponding 1641 * entries in arm64_ftr_regs[]. 1642 */ 1643 1644 /* AArch64 mappings of the AArch32 ID registers */ 1645 /* CRm=1 */ 1646 AA32_ID_SANITISED(ID_PFR0_EL1), 1647 AA32_ID_SANITISED(ID_PFR1_EL1), 1648 { SYS_DESC(SYS_ID_DFR0_EL1), .access = access_id_reg, 1649 .get_user = get_id_reg, .set_user = set_id_dfr0_el1, 1650 .visibility = aa32_id_visibility, }, 1651 ID_HIDDEN(ID_AFR0_EL1), 1652 AA32_ID_SANITISED(ID_MMFR0_EL1), 1653 AA32_ID_SANITISED(ID_MMFR1_EL1), 1654 AA32_ID_SANITISED(ID_MMFR2_EL1), 1655 AA32_ID_SANITISED(ID_MMFR3_EL1), 1656 1657 /* CRm=2 */ 1658 AA32_ID_SANITISED(ID_ISAR0_EL1), 1659 AA32_ID_SANITISED(ID_ISAR1_EL1), 1660 AA32_ID_SANITISED(ID_ISAR2_EL1), 1661 AA32_ID_SANITISED(ID_ISAR3_EL1), 1662 AA32_ID_SANITISED(ID_ISAR4_EL1), 1663 AA32_ID_SANITISED(ID_ISAR5_EL1), 1664 AA32_ID_SANITISED(ID_MMFR4_EL1), 1665 AA32_ID_SANITISED(ID_ISAR6_EL1), 1666 1667 /* CRm=3 */ 1668 AA32_ID_SANITISED(MVFR0_EL1), 1669 AA32_ID_SANITISED(MVFR1_EL1), 1670 AA32_ID_SANITISED(MVFR2_EL1), 1671 ID_UNALLOCATED(3,3), 1672 AA32_ID_SANITISED(ID_PFR2_EL1), 1673 ID_HIDDEN(ID_DFR1_EL1), 1674 AA32_ID_SANITISED(ID_MMFR5_EL1), 1675 ID_UNALLOCATED(3,7), 1676 1677 /* AArch64 ID registers */ 1678 /* CRm=4 */ 1679 { SYS_DESC(SYS_ID_AA64PFR0_EL1), .access = access_id_reg, 1680 .get_user = get_id_reg, .set_user = set_id_aa64pfr0_el1, }, 1681 ID_SANITISED(ID_AA64PFR1_EL1), 1682 ID_UNALLOCATED(4,2), 1683 ID_UNALLOCATED(4,3), 1684 ID_SANITISED(ID_AA64ZFR0_EL1), 1685 ID_HIDDEN(ID_AA64SMFR0_EL1), 1686 ID_UNALLOCATED(4,6), 1687 ID_UNALLOCATED(4,7), 1688 1689 /* CRm=5 */ 1690 { SYS_DESC(SYS_ID_AA64DFR0_EL1), .access = access_id_reg, 1691 .get_user = get_id_reg, .set_user = set_id_aa64dfr0_el1, }, 1692 ID_SANITISED(ID_AA64DFR1_EL1), 1693 ID_UNALLOCATED(5,2), 1694 ID_UNALLOCATED(5,3), 1695 ID_HIDDEN(ID_AA64AFR0_EL1), 1696 ID_HIDDEN(ID_AA64AFR1_EL1), 1697 ID_UNALLOCATED(5,6), 1698 ID_UNALLOCATED(5,7), 1699 1700 /* CRm=6 */ 1701 ID_SANITISED(ID_AA64ISAR0_EL1), 1702 ID_SANITISED(ID_AA64ISAR1_EL1), 1703 ID_SANITISED(ID_AA64ISAR2_EL1), 1704 ID_UNALLOCATED(6,3), 1705 ID_UNALLOCATED(6,4), 1706 ID_UNALLOCATED(6,5), 1707 ID_UNALLOCATED(6,6), 1708 ID_UNALLOCATED(6,7), 1709 1710 /* CRm=7 */ 1711 ID_SANITISED(ID_AA64MMFR0_EL1), 1712 ID_SANITISED(ID_AA64MMFR1_EL1), 1713 ID_SANITISED(ID_AA64MMFR2_EL1), 1714 ID_UNALLOCATED(7,3), 1715 ID_UNALLOCATED(7,4), 1716 ID_UNALLOCATED(7,5), 1717 ID_UNALLOCATED(7,6), 1718 ID_UNALLOCATED(7,7), 1719 1720 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 }, 1721 { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 }, 1722 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 }, 1723 1724 MTE_REG(RGSR_EL1), 1725 MTE_REG(GCR_EL1), 1726 1727 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility }, 1728 { SYS_DESC(SYS_TRFCR_EL1), undef_access }, 1729 { SYS_DESC(SYS_SMPRI_EL1), undef_access }, 1730 { SYS_DESC(SYS_SMCR_EL1), undef_access }, 1731 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 }, 1732 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 }, 1733 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 }, 1734 1735 PTRAUTH_KEY(APIA), 1736 PTRAUTH_KEY(APIB), 1737 PTRAUTH_KEY(APDA), 1738 PTRAUTH_KEY(APDB), 1739 PTRAUTH_KEY(APGA), 1740 1741 { SYS_DESC(SYS_SPSR_EL1), access_spsr}, 1742 { SYS_DESC(SYS_ELR_EL1), access_elr}, 1743 1744 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 }, 1745 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 }, 1746 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 }, 1747 1748 { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi }, 1749 { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi }, 1750 { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi }, 1751 { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi }, 1752 { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi }, 1753 { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi }, 1754 { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi }, 1755 { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi }, 1756 1757 MTE_REG(TFSR_EL1), 1758 MTE_REG(TFSRE0_EL1), 1759 1760 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 }, 1761 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 }, 1762 1763 { SYS_DESC(SYS_PMSCR_EL1), undef_access }, 1764 { SYS_DESC(SYS_PMSNEVFR_EL1), undef_access }, 1765 { SYS_DESC(SYS_PMSICR_EL1), undef_access }, 1766 { SYS_DESC(SYS_PMSIRR_EL1), undef_access }, 1767 { SYS_DESC(SYS_PMSFCR_EL1), undef_access }, 1768 { SYS_DESC(SYS_PMSEVFR_EL1), undef_access }, 1769 { SYS_DESC(SYS_PMSLATFR_EL1), undef_access }, 1770 { SYS_DESC(SYS_PMSIDR_EL1), undef_access }, 1771 { SYS_DESC(SYS_PMBLIMITR_EL1), undef_access }, 1772 { SYS_DESC(SYS_PMBPTR_EL1), undef_access }, 1773 { SYS_DESC(SYS_PMBSR_EL1), undef_access }, 1774 /* PMBIDR_EL1 is not trapped */ 1775 1776 { PMU_SYS_REG(SYS_PMINTENSET_EL1), 1777 .access = access_pminten, .reg = PMINTENSET_EL1 }, 1778 { PMU_SYS_REG(SYS_PMINTENCLR_EL1), 1779 .access = access_pminten, .reg = PMINTENSET_EL1 }, 1780 { SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi }, 1781 1782 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 }, 1783 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 }, 1784 1785 { SYS_DESC(SYS_LORSA_EL1), trap_loregion }, 1786 { SYS_DESC(SYS_LOREA_EL1), trap_loregion }, 1787 { SYS_DESC(SYS_LORN_EL1), trap_loregion }, 1788 { SYS_DESC(SYS_LORC_EL1), trap_loregion }, 1789 { SYS_DESC(SYS_LORID_EL1), trap_loregion }, 1790 1791 { SYS_DESC(SYS_VBAR_EL1), access_rw, reset_val, VBAR_EL1, 0 }, 1792 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 }, 1793 1794 { SYS_DESC(SYS_ICC_IAR0_EL1), write_to_read_only }, 1795 { SYS_DESC(SYS_ICC_EOIR0_EL1), read_from_write_only }, 1796 { SYS_DESC(SYS_ICC_HPPIR0_EL1), write_to_read_only }, 1797 { SYS_DESC(SYS_ICC_DIR_EL1), read_from_write_only }, 1798 { SYS_DESC(SYS_ICC_RPR_EL1), write_to_read_only }, 1799 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi }, 1800 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi }, 1801 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi }, 1802 { SYS_DESC(SYS_ICC_IAR1_EL1), write_to_read_only }, 1803 { SYS_DESC(SYS_ICC_EOIR1_EL1), read_from_write_only }, 1804 { SYS_DESC(SYS_ICC_HPPIR1_EL1), write_to_read_only }, 1805 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre }, 1806 1807 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 }, 1808 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 }, 1809 1810 { SYS_DESC(SYS_SCXTNUM_EL1), undef_access }, 1811 1812 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0}, 1813 1814 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr }, 1815 { SYS_DESC(SYS_CLIDR_EL1), access_clidr }, 1816 { SYS_DESC(SYS_SMIDR_EL1), undef_access }, 1817 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, 1818 { SYS_DESC(SYS_CTR_EL0), access_ctr }, 1819 { SYS_DESC(SYS_SVCR), undef_access }, 1820 1821 { PMU_SYS_REG(SYS_PMCR_EL0), .access = access_pmcr, 1822 .reset = reset_pmcr, .reg = PMCR_EL0 }, 1823 { PMU_SYS_REG(SYS_PMCNTENSET_EL0), 1824 .access = access_pmcnten, .reg = PMCNTENSET_EL0 }, 1825 { PMU_SYS_REG(SYS_PMCNTENCLR_EL0), 1826 .access = access_pmcnten, .reg = PMCNTENSET_EL0 }, 1827 { PMU_SYS_REG(SYS_PMOVSCLR_EL0), 1828 .access = access_pmovs, .reg = PMOVSSET_EL0 }, 1829 /* 1830 * PM_SWINC_EL0 is exposed to userspace as RAZ/WI, as it was 1831 * previously (and pointlessly) advertised in the past... 1832 */ 1833 { PMU_SYS_REG(SYS_PMSWINC_EL0), 1834 .get_user = get_raz_reg, .set_user = set_wi_reg, 1835 .access = access_pmswinc, .reset = NULL }, 1836 { PMU_SYS_REG(SYS_PMSELR_EL0), 1837 .access = access_pmselr, .reset = reset_pmselr, .reg = PMSELR_EL0 }, 1838 { PMU_SYS_REG(SYS_PMCEID0_EL0), 1839 .access = access_pmceid, .reset = NULL }, 1840 { PMU_SYS_REG(SYS_PMCEID1_EL0), 1841 .access = access_pmceid, .reset = NULL }, 1842 { PMU_SYS_REG(SYS_PMCCNTR_EL0), 1843 .access = access_pmu_evcntr, .reset = reset_unknown, .reg = PMCCNTR_EL0 }, 1844 { PMU_SYS_REG(SYS_PMXEVTYPER_EL0), 1845 .access = access_pmu_evtyper, .reset = NULL }, 1846 { PMU_SYS_REG(SYS_PMXEVCNTR_EL0), 1847 .access = access_pmu_evcntr, .reset = NULL }, 1848 /* 1849 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero 1850 * in 32bit mode. Here we choose to reset it as zero for consistency. 1851 */ 1852 { PMU_SYS_REG(SYS_PMUSERENR_EL0), .access = access_pmuserenr, 1853 .reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 }, 1854 { PMU_SYS_REG(SYS_PMOVSSET_EL0), 1855 .access = access_pmovs, .reg = PMOVSSET_EL0 }, 1856 1857 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 }, 1858 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 }, 1859 { SYS_DESC(SYS_TPIDR2_EL0), undef_access }, 1860 1861 { SYS_DESC(SYS_SCXTNUM_EL0), undef_access }, 1862 1863 { SYS_DESC(SYS_AMCR_EL0), undef_access }, 1864 { SYS_DESC(SYS_AMCFGR_EL0), undef_access }, 1865 { SYS_DESC(SYS_AMCGCR_EL0), undef_access }, 1866 { SYS_DESC(SYS_AMUSERENR_EL0), undef_access }, 1867 { SYS_DESC(SYS_AMCNTENCLR0_EL0), undef_access }, 1868 { SYS_DESC(SYS_AMCNTENSET0_EL0), undef_access }, 1869 { SYS_DESC(SYS_AMCNTENCLR1_EL0), undef_access }, 1870 { SYS_DESC(SYS_AMCNTENSET1_EL0), undef_access }, 1871 AMU_AMEVCNTR0_EL0(0), 1872 AMU_AMEVCNTR0_EL0(1), 1873 AMU_AMEVCNTR0_EL0(2), 1874 AMU_AMEVCNTR0_EL0(3), 1875 AMU_AMEVCNTR0_EL0(4), 1876 AMU_AMEVCNTR0_EL0(5), 1877 AMU_AMEVCNTR0_EL0(6), 1878 AMU_AMEVCNTR0_EL0(7), 1879 AMU_AMEVCNTR0_EL0(8), 1880 AMU_AMEVCNTR0_EL0(9), 1881 AMU_AMEVCNTR0_EL0(10), 1882 AMU_AMEVCNTR0_EL0(11), 1883 AMU_AMEVCNTR0_EL0(12), 1884 AMU_AMEVCNTR0_EL0(13), 1885 AMU_AMEVCNTR0_EL0(14), 1886 AMU_AMEVCNTR0_EL0(15), 1887 AMU_AMEVTYPER0_EL0(0), 1888 AMU_AMEVTYPER0_EL0(1), 1889 AMU_AMEVTYPER0_EL0(2), 1890 AMU_AMEVTYPER0_EL0(3), 1891 AMU_AMEVTYPER0_EL0(4), 1892 AMU_AMEVTYPER0_EL0(5), 1893 AMU_AMEVTYPER0_EL0(6), 1894 AMU_AMEVTYPER0_EL0(7), 1895 AMU_AMEVTYPER0_EL0(8), 1896 AMU_AMEVTYPER0_EL0(9), 1897 AMU_AMEVTYPER0_EL0(10), 1898 AMU_AMEVTYPER0_EL0(11), 1899 AMU_AMEVTYPER0_EL0(12), 1900 AMU_AMEVTYPER0_EL0(13), 1901 AMU_AMEVTYPER0_EL0(14), 1902 AMU_AMEVTYPER0_EL0(15), 1903 AMU_AMEVCNTR1_EL0(0), 1904 AMU_AMEVCNTR1_EL0(1), 1905 AMU_AMEVCNTR1_EL0(2), 1906 AMU_AMEVCNTR1_EL0(3), 1907 AMU_AMEVCNTR1_EL0(4), 1908 AMU_AMEVCNTR1_EL0(5), 1909 AMU_AMEVCNTR1_EL0(6), 1910 AMU_AMEVCNTR1_EL0(7), 1911 AMU_AMEVCNTR1_EL0(8), 1912 AMU_AMEVCNTR1_EL0(9), 1913 AMU_AMEVCNTR1_EL0(10), 1914 AMU_AMEVCNTR1_EL0(11), 1915 AMU_AMEVCNTR1_EL0(12), 1916 AMU_AMEVCNTR1_EL0(13), 1917 AMU_AMEVCNTR1_EL0(14), 1918 AMU_AMEVCNTR1_EL0(15), 1919 AMU_AMEVTYPER1_EL0(0), 1920 AMU_AMEVTYPER1_EL0(1), 1921 AMU_AMEVTYPER1_EL0(2), 1922 AMU_AMEVTYPER1_EL0(3), 1923 AMU_AMEVTYPER1_EL0(4), 1924 AMU_AMEVTYPER1_EL0(5), 1925 AMU_AMEVTYPER1_EL0(6), 1926 AMU_AMEVTYPER1_EL0(7), 1927 AMU_AMEVTYPER1_EL0(8), 1928 AMU_AMEVTYPER1_EL0(9), 1929 AMU_AMEVTYPER1_EL0(10), 1930 AMU_AMEVTYPER1_EL0(11), 1931 AMU_AMEVTYPER1_EL0(12), 1932 AMU_AMEVTYPER1_EL0(13), 1933 AMU_AMEVTYPER1_EL0(14), 1934 AMU_AMEVTYPER1_EL0(15), 1935 1936 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer }, 1937 { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer }, 1938 { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer }, 1939 1940 /* PMEVCNTRn_EL0 */ 1941 PMU_PMEVCNTR_EL0(0), 1942 PMU_PMEVCNTR_EL0(1), 1943 PMU_PMEVCNTR_EL0(2), 1944 PMU_PMEVCNTR_EL0(3), 1945 PMU_PMEVCNTR_EL0(4), 1946 PMU_PMEVCNTR_EL0(5), 1947 PMU_PMEVCNTR_EL0(6), 1948 PMU_PMEVCNTR_EL0(7), 1949 PMU_PMEVCNTR_EL0(8), 1950 PMU_PMEVCNTR_EL0(9), 1951 PMU_PMEVCNTR_EL0(10), 1952 PMU_PMEVCNTR_EL0(11), 1953 PMU_PMEVCNTR_EL0(12), 1954 PMU_PMEVCNTR_EL0(13), 1955 PMU_PMEVCNTR_EL0(14), 1956 PMU_PMEVCNTR_EL0(15), 1957 PMU_PMEVCNTR_EL0(16), 1958 PMU_PMEVCNTR_EL0(17), 1959 PMU_PMEVCNTR_EL0(18), 1960 PMU_PMEVCNTR_EL0(19), 1961 PMU_PMEVCNTR_EL0(20), 1962 PMU_PMEVCNTR_EL0(21), 1963 PMU_PMEVCNTR_EL0(22), 1964 PMU_PMEVCNTR_EL0(23), 1965 PMU_PMEVCNTR_EL0(24), 1966 PMU_PMEVCNTR_EL0(25), 1967 PMU_PMEVCNTR_EL0(26), 1968 PMU_PMEVCNTR_EL0(27), 1969 PMU_PMEVCNTR_EL0(28), 1970 PMU_PMEVCNTR_EL0(29), 1971 PMU_PMEVCNTR_EL0(30), 1972 /* PMEVTYPERn_EL0 */ 1973 PMU_PMEVTYPER_EL0(0), 1974 PMU_PMEVTYPER_EL0(1), 1975 PMU_PMEVTYPER_EL0(2), 1976 PMU_PMEVTYPER_EL0(3), 1977 PMU_PMEVTYPER_EL0(4), 1978 PMU_PMEVTYPER_EL0(5), 1979 PMU_PMEVTYPER_EL0(6), 1980 PMU_PMEVTYPER_EL0(7), 1981 PMU_PMEVTYPER_EL0(8), 1982 PMU_PMEVTYPER_EL0(9), 1983 PMU_PMEVTYPER_EL0(10), 1984 PMU_PMEVTYPER_EL0(11), 1985 PMU_PMEVTYPER_EL0(12), 1986 PMU_PMEVTYPER_EL0(13), 1987 PMU_PMEVTYPER_EL0(14), 1988 PMU_PMEVTYPER_EL0(15), 1989 PMU_PMEVTYPER_EL0(16), 1990 PMU_PMEVTYPER_EL0(17), 1991 PMU_PMEVTYPER_EL0(18), 1992 PMU_PMEVTYPER_EL0(19), 1993 PMU_PMEVTYPER_EL0(20), 1994 PMU_PMEVTYPER_EL0(21), 1995 PMU_PMEVTYPER_EL0(22), 1996 PMU_PMEVTYPER_EL0(23), 1997 PMU_PMEVTYPER_EL0(24), 1998 PMU_PMEVTYPER_EL0(25), 1999 PMU_PMEVTYPER_EL0(26), 2000 PMU_PMEVTYPER_EL0(27), 2001 PMU_PMEVTYPER_EL0(28), 2002 PMU_PMEVTYPER_EL0(29), 2003 PMU_PMEVTYPER_EL0(30), 2004 /* 2005 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero 2006 * in 32bit mode. Here we choose to reset it as zero for consistency. 2007 */ 2008 { PMU_SYS_REG(SYS_PMCCFILTR_EL0), .access = access_pmu_evtyper, 2009 .reset = reset_val, .reg = PMCCFILTR_EL0, .val = 0 }, 2010 2011 EL2_REG(VPIDR_EL2, access_rw, reset_unknown, 0), 2012 EL2_REG(VMPIDR_EL2, access_rw, reset_unknown, 0), 2013 EL2_REG(SCTLR_EL2, access_rw, reset_val, SCTLR_EL2_RES1), 2014 EL2_REG(ACTLR_EL2, access_rw, reset_val, 0), 2015 EL2_REG(HCR_EL2, access_rw, reset_val, 0), 2016 EL2_REG(MDCR_EL2, access_rw, reset_val, 0), 2017 EL2_REG(CPTR_EL2, access_rw, reset_val, CPTR_EL2_DEFAULT ), 2018 EL2_REG(HSTR_EL2, access_rw, reset_val, 0), 2019 EL2_REG(HACR_EL2, access_rw, reset_val, 0), 2020 2021 EL2_REG(TTBR0_EL2, access_rw, reset_val, 0), 2022 EL2_REG(TTBR1_EL2, access_rw, reset_val, 0), 2023 EL2_REG(TCR_EL2, access_rw, reset_val, TCR_EL2_RES1), 2024 EL2_REG(VTTBR_EL2, access_rw, reset_val, 0), 2025 EL2_REG(VTCR_EL2, access_rw, reset_val, 0), 2026 2027 { SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 }, 2028 EL2_REG(SPSR_EL2, access_rw, reset_val, 0), 2029 EL2_REG(ELR_EL2, access_rw, reset_val, 0), 2030 { SYS_DESC(SYS_SP_EL1), access_sp_el1}, 2031 2032 { SYS_DESC(SYS_IFSR32_EL2), NULL, reset_unknown, IFSR32_EL2 }, 2033 EL2_REG(AFSR0_EL2, access_rw, reset_val, 0), 2034 EL2_REG(AFSR1_EL2, access_rw, reset_val, 0), 2035 EL2_REG(ESR_EL2, access_rw, reset_val, 0), 2036 { SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x700 }, 2037 2038 EL2_REG(FAR_EL2, access_rw, reset_val, 0), 2039 EL2_REG(HPFAR_EL2, access_rw, reset_val, 0), 2040 2041 EL2_REG(MAIR_EL2, access_rw, reset_val, 0), 2042 EL2_REG(AMAIR_EL2, access_rw, reset_val, 0), 2043 2044 EL2_REG(VBAR_EL2, access_rw, reset_val, 0), 2045 EL2_REG(RVBAR_EL2, access_rw, reset_val, 0), 2046 { SYS_DESC(SYS_RMR_EL2), trap_undef }, 2047 2048 EL2_REG(CONTEXTIDR_EL2, access_rw, reset_val, 0), 2049 EL2_REG(TPIDR_EL2, access_rw, reset_val, 0), 2050 2051 EL2_REG(CNTVOFF_EL2, access_rw, reset_val, 0), 2052 EL2_REG(CNTHCTL_EL2, access_rw, reset_val, 0), 2053 2054 EL12_REG(SCTLR, access_vm_reg, reset_val, 0x00C50078), 2055 EL12_REG(CPACR, access_rw, reset_val, 0), 2056 EL12_REG(TTBR0, access_vm_reg, reset_unknown, 0), 2057 EL12_REG(TTBR1, access_vm_reg, reset_unknown, 0), 2058 EL12_REG(TCR, access_vm_reg, reset_val, 0), 2059 { SYS_DESC(SYS_SPSR_EL12), access_spsr}, 2060 { SYS_DESC(SYS_ELR_EL12), access_elr}, 2061 EL12_REG(AFSR0, access_vm_reg, reset_unknown, 0), 2062 EL12_REG(AFSR1, access_vm_reg, reset_unknown, 0), 2063 EL12_REG(ESR, access_vm_reg, reset_unknown, 0), 2064 EL12_REG(FAR, access_vm_reg, reset_unknown, 0), 2065 EL12_REG(MAIR, access_vm_reg, reset_unknown, 0), 2066 EL12_REG(AMAIR, access_vm_reg, reset_amair_el1, 0), 2067 EL12_REG(VBAR, access_rw, reset_val, 0), 2068 EL12_REG(CONTEXTIDR, access_vm_reg, reset_val, 0), 2069 EL12_REG(CNTKCTL, access_rw, reset_val, 0), 2070 2071 EL2_REG(SP_EL2, NULL, reset_unknown, 0), 2072 }; 2073 2074 static bool trap_dbgdidr(struct kvm_vcpu *vcpu, 2075 struct sys_reg_params *p, 2076 const struct sys_reg_desc *r) 2077 { 2078 if (p->is_write) { 2079 return ignore_write(vcpu, p); 2080 } else { 2081 u64 dfr = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); 2082 u64 pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 2083 u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL1_EL3_SHIFT); 2084 2085 p->regval = ((((dfr >> ID_AA64DFR0_EL1_WRPs_SHIFT) & 0xf) << 28) | 2086 (((dfr >> ID_AA64DFR0_EL1_BRPs_SHIFT) & 0xf) << 24) | 2087 (((dfr >> ID_AA64DFR0_EL1_CTX_CMPs_SHIFT) & 0xf) << 20) 2088 | (6 << 16) | (1 << 15) | (el3 << 14) | (el3 << 12)); 2089 return true; 2090 } 2091 } 2092 2093 /* 2094 * AArch32 debug register mappings 2095 * 2096 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0] 2097 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32] 2098 * 2099 * None of the other registers share their location, so treat them as 2100 * if they were 64bit. 2101 */ 2102 #define DBG_BCR_BVR_WCR_WVR(n) \ 2103 /* DBGBVRn */ \ 2104 { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \ 2105 /* DBGBCRn */ \ 2106 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \ 2107 /* DBGWVRn */ \ 2108 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \ 2109 /* DBGWCRn */ \ 2110 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n } 2111 2112 #define DBGBXVR(n) \ 2113 { AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_bvr, NULL, n } 2114 2115 /* 2116 * Trapped cp14 registers. We generally ignore most of the external 2117 * debug, on the principle that they don't really make sense to a 2118 * guest. Revisit this one day, would this principle change. 2119 */ 2120 static const struct sys_reg_desc cp14_regs[] = { 2121 /* DBGDIDR */ 2122 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgdidr }, 2123 /* DBGDTRRXext */ 2124 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi }, 2125 2126 DBG_BCR_BVR_WCR_WVR(0), 2127 /* DBGDSCRint */ 2128 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi }, 2129 DBG_BCR_BVR_WCR_WVR(1), 2130 /* DBGDCCINT */ 2131 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug_regs, NULL, MDCCINT_EL1 }, 2132 /* DBGDSCRext */ 2133 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug_regs, NULL, MDSCR_EL1 }, 2134 DBG_BCR_BVR_WCR_WVR(2), 2135 /* DBGDTR[RT]Xint */ 2136 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi }, 2137 /* DBGDTR[RT]Xext */ 2138 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi }, 2139 DBG_BCR_BVR_WCR_WVR(3), 2140 DBG_BCR_BVR_WCR_WVR(4), 2141 DBG_BCR_BVR_WCR_WVR(5), 2142 /* DBGWFAR */ 2143 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi }, 2144 /* DBGOSECCR */ 2145 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi }, 2146 DBG_BCR_BVR_WCR_WVR(6), 2147 /* DBGVCR */ 2148 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug_regs, NULL, DBGVCR32_EL2 }, 2149 DBG_BCR_BVR_WCR_WVR(7), 2150 DBG_BCR_BVR_WCR_WVR(8), 2151 DBG_BCR_BVR_WCR_WVR(9), 2152 DBG_BCR_BVR_WCR_WVR(10), 2153 DBG_BCR_BVR_WCR_WVR(11), 2154 DBG_BCR_BVR_WCR_WVR(12), 2155 DBG_BCR_BVR_WCR_WVR(13), 2156 DBG_BCR_BVR_WCR_WVR(14), 2157 DBG_BCR_BVR_WCR_WVR(15), 2158 2159 /* DBGDRAR (32bit) */ 2160 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi }, 2161 2162 DBGBXVR(0), 2163 /* DBGOSLAR */ 2164 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_oslar_el1 }, 2165 DBGBXVR(1), 2166 /* DBGOSLSR */ 2167 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1, NULL, OSLSR_EL1 }, 2168 DBGBXVR(2), 2169 DBGBXVR(3), 2170 /* DBGOSDLR */ 2171 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi }, 2172 DBGBXVR(4), 2173 /* DBGPRCR */ 2174 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi }, 2175 DBGBXVR(5), 2176 DBGBXVR(6), 2177 DBGBXVR(7), 2178 DBGBXVR(8), 2179 DBGBXVR(9), 2180 DBGBXVR(10), 2181 DBGBXVR(11), 2182 DBGBXVR(12), 2183 DBGBXVR(13), 2184 DBGBXVR(14), 2185 DBGBXVR(15), 2186 2187 /* DBGDSAR (32bit) */ 2188 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi }, 2189 2190 /* DBGDEVID2 */ 2191 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi }, 2192 /* DBGDEVID1 */ 2193 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi }, 2194 /* DBGDEVID */ 2195 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi }, 2196 /* DBGCLAIMSET */ 2197 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi }, 2198 /* DBGCLAIMCLR */ 2199 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi }, 2200 /* DBGAUTHSTATUS */ 2201 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 }, 2202 }; 2203 2204 /* Trapped cp14 64bit registers */ 2205 static const struct sys_reg_desc cp14_64_regs[] = { 2206 /* DBGDRAR (64bit) */ 2207 { Op1( 0), CRm( 1), .access = trap_raz_wi }, 2208 2209 /* DBGDSAR (64bit) */ 2210 { Op1( 0), CRm( 2), .access = trap_raz_wi }, 2211 }; 2212 2213 #define CP15_PMU_SYS_REG(_map, _Op1, _CRn, _CRm, _Op2) \ 2214 AA32(_map), \ 2215 Op1(_Op1), CRn(_CRn), CRm(_CRm), Op2(_Op2), \ 2216 .visibility = pmu_visibility 2217 2218 /* Macro to expand the PMEVCNTRn register */ 2219 #define PMU_PMEVCNTR(n) \ 2220 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \ 2221 (0b1000 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \ 2222 .access = access_pmu_evcntr } 2223 2224 /* Macro to expand the PMEVTYPERn register */ 2225 #define PMU_PMEVTYPER(n) \ 2226 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \ 2227 (0b1100 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \ 2228 .access = access_pmu_evtyper } 2229 /* 2230 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding, 2231 * depending on the way they are accessed (as a 32bit or a 64bit 2232 * register). 2233 */ 2234 static const struct sys_reg_desc cp15_regs[] = { 2235 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr }, 2236 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, SCTLR_EL1 }, 2237 /* ACTLR */ 2238 { AA32(LO), Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr, NULL, ACTLR_EL1 }, 2239 /* ACTLR2 */ 2240 { AA32(HI), Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr, NULL, ACTLR_EL1 }, 2241 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, 2242 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, TTBR1_EL1 }, 2243 /* TTBCR */ 2244 { AA32(LO), Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 }, 2245 /* TTBCR2 */ 2246 { AA32(HI), Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, TCR_EL1 }, 2247 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, DACR32_EL2 }, 2248 /* DFSR */ 2249 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, ESR_EL1 }, 2250 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, IFSR32_EL2 }, 2251 /* ADFSR */ 2252 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, AFSR0_EL1 }, 2253 /* AIFSR */ 2254 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, AFSR1_EL1 }, 2255 /* DFAR */ 2256 { AA32(LO), Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, FAR_EL1 }, 2257 /* IFAR */ 2258 { AA32(HI), Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, FAR_EL1 }, 2259 2260 /* 2261 * DC{C,I,CI}SW operations: 2262 */ 2263 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw }, 2264 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw }, 2265 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw }, 2266 2267 /* PMU */ 2268 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 0), .access = access_pmcr }, 2269 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 1), .access = access_pmcnten }, 2270 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 2), .access = access_pmcnten }, 2271 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 3), .access = access_pmovs }, 2272 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 4), .access = access_pmswinc }, 2273 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 5), .access = access_pmselr }, 2274 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 6), .access = access_pmceid }, 2275 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 7), .access = access_pmceid }, 2276 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 0), .access = access_pmu_evcntr }, 2277 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 1), .access = access_pmu_evtyper }, 2278 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 2), .access = access_pmu_evcntr }, 2279 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 0), .access = access_pmuserenr }, 2280 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 1), .access = access_pminten }, 2281 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 2), .access = access_pminten }, 2282 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 3), .access = access_pmovs }, 2283 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 4), .access = access_pmceid }, 2284 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 5), .access = access_pmceid }, 2285 /* PMMIR */ 2286 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 6), .access = trap_raz_wi }, 2287 2288 /* PRRR/MAIR0 */ 2289 { AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 }, 2290 /* NMRR/MAIR1 */ 2291 { AA32(HI), Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, MAIR_EL1 }, 2292 /* AMAIR0 */ 2293 { AA32(LO), Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, AMAIR_EL1 }, 2294 /* AMAIR1 */ 2295 { AA32(HI), Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, AMAIR_EL1 }, 2296 2297 /* ICC_SRE */ 2298 { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre }, 2299 2300 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, CONTEXTIDR_EL1 }, 2301 2302 /* Arch Tmers */ 2303 { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer }, 2304 { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer }, 2305 2306 /* PMEVCNTRn */ 2307 PMU_PMEVCNTR(0), 2308 PMU_PMEVCNTR(1), 2309 PMU_PMEVCNTR(2), 2310 PMU_PMEVCNTR(3), 2311 PMU_PMEVCNTR(4), 2312 PMU_PMEVCNTR(5), 2313 PMU_PMEVCNTR(6), 2314 PMU_PMEVCNTR(7), 2315 PMU_PMEVCNTR(8), 2316 PMU_PMEVCNTR(9), 2317 PMU_PMEVCNTR(10), 2318 PMU_PMEVCNTR(11), 2319 PMU_PMEVCNTR(12), 2320 PMU_PMEVCNTR(13), 2321 PMU_PMEVCNTR(14), 2322 PMU_PMEVCNTR(15), 2323 PMU_PMEVCNTR(16), 2324 PMU_PMEVCNTR(17), 2325 PMU_PMEVCNTR(18), 2326 PMU_PMEVCNTR(19), 2327 PMU_PMEVCNTR(20), 2328 PMU_PMEVCNTR(21), 2329 PMU_PMEVCNTR(22), 2330 PMU_PMEVCNTR(23), 2331 PMU_PMEVCNTR(24), 2332 PMU_PMEVCNTR(25), 2333 PMU_PMEVCNTR(26), 2334 PMU_PMEVCNTR(27), 2335 PMU_PMEVCNTR(28), 2336 PMU_PMEVCNTR(29), 2337 PMU_PMEVCNTR(30), 2338 /* PMEVTYPERn */ 2339 PMU_PMEVTYPER(0), 2340 PMU_PMEVTYPER(1), 2341 PMU_PMEVTYPER(2), 2342 PMU_PMEVTYPER(3), 2343 PMU_PMEVTYPER(4), 2344 PMU_PMEVTYPER(5), 2345 PMU_PMEVTYPER(6), 2346 PMU_PMEVTYPER(7), 2347 PMU_PMEVTYPER(8), 2348 PMU_PMEVTYPER(9), 2349 PMU_PMEVTYPER(10), 2350 PMU_PMEVTYPER(11), 2351 PMU_PMEVTYPER(12), 2352 PMU_PMEVTYPER(13), 2353 PMU_PMEVTYPER(14), 2354 PMU_PMEVTYPER(15), 2355 PMU_PMEVTYPER(16), 2356 PMU_PMEVTYPER(17), 2357 PMU_PMEVTYPER(18), 2358 PMU_PMEVTYPER(19), 2359 PMU_PMEVTYPER(20), 2360 PMU_PMEVTYPER(21), 2361 PMU_PMEVTYPER(22), 2362 PMU_PMEVTYPER(23), 2363 PMU_PMEVTYPER(24), 2364 PMU_PMEVTYPER(25), 2365 PMU_PMEVTYPER(26), 2366 PMU_PMEVTYPER(27), 2367 PMU_PMEVTYPER(28), 2368 PMU_PMEVTYPER(29), 2369 PMU_PMEVTYPER(30), 2370 /* PMCCFILTR */ 2371 { CP15_PMU_SYS_REG(DIRECT, 0, 14, 15, 7), .access = access_pmu_evtyper }, 2372 2373 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr }, 2374 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr }, 2375 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 }, 2376 }; 2377 2378 static const struct sys_reg_desc cp15_64_regs[] = { 2379 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, 2380 { CP15_PMU_SYS_REG(DIRECT, 0, 0, 9, 0), .access = access_pmu_evcntr }, 2381 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */ 2382 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 }, 2383 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */ 2384 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */ 2385 { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer }, 2386 }; 2387 2388 static bool check_sysreg_table(const struct sys_reg_desc *table, unsigned int n, 2389 bool is_32) 2390 { 2391 unsigned int i; 2392 2393 for (i = 0; i < n; i++) { 2394 if (!is_32 && table[i].reg && !table[i].reset) { 2395 kvm_err("sys_reg table %pS entry %d lacks reset\n", &table[i], i); 2396 return false; 2397 } 2398 2399 if (i && cmp_sys_reg(&table[i-1], &table[i]) >= 0) { 2400 kvm_err("sys_reg table %pS entry %d out of order\n", &table[i - 1], i - 1); 2401 return false; 2402 } 2403 } 2404 2405 return true; 2406 } 2407 2408 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu) 2409 { 2410 kvm_inject_undefined(vcpu); 2411 return 1; 2412 } 2413 2414 static void perform_access(struct kvm_vcpu *vcpu, 2415 struct sys_reg_params *params, 2416 const struct sys_reg_desc *r) 2417 { 2418 trace_kvm_sys_access(*vcpu_pc(vcpu), params, r); 2419 2420 /* Check for regs disabled by runtime config */ 2421 if (sysreg_hidden(vcpu, r)) { 2422 kvm_inject_undefined(vcpu); 2423 return; 2424 } 2425 2426 /* 2427 * Not having an accessor means that we have configured a trap 2428 * that we don't know how to handle. This certainly qualifies 2429 * as a gross bug that should be fixed right away. 2430 */ 2431 BUG_ON(!r->access); 2432 2433 /* Skip instruction if instructed so */ 2434 if (likely(r->access(vcpu, params, r))) 2435 kvm_incr_pc(vcpu); 2436 } 2437 2438 /* 2439 * emulate_cp -- tries to match a sys_reg access in a handling table, and 2440 * call the corresponding trap handler. 2441 * 2442 * @params: pointer to the descriptor of the access 2443 * @table: array of trap descriptors 2444 * @num: size of the trap descriptor array 2445 * 2446 * Return true if the access has been handled, false if not. 2447 */ 2448 static bool emulate_cp(struct kvm_vcpu *vcpu, 2449 struct sys_reg_params *params, 2450 const struct sys_reg_desc *table, 2451 size_t num) 2452 { 2453 const struct sys_reg_desc *r; 2454 2455 if (!table) 2456 return false; /* Not handled */ 2457 2458 r = find_reg(params, table, num); 2459 2460 if (r) { 2461 perform_access(vcpu, params, r); 2462 return true; 2463 } 2464 2465 /* Not handled */ 2466 return false; 2467 } 2468 2469 static void unhandled_cp_access(struct kvm_vcpu *vcpu, 2470 struct sys_reg_params *params) 2471 { 2472 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu); 2473 int cp = -1; 2474 2475 switch (esr_ec) { 2476 case ESR_ELx_EC_CP15_32: 2477 case ESR_ELx_EC_CP15_64: 2478 cp = 15; 2479 break; 2480 case ESR_ELx_EC_CP14_MR: 2481 case ESR_ELx_EC_CP14_64: 2482 cp = 14; 2483 break; 2484 default: 2485 WARN_ON(1); 2486 } 2487 2488 print_sys_reg_msg(params, 2489 "Unsupported guest CP%d access at: %08lx [%08lx]\n", 2490 cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 2491 kvm_inject_undefined(vcpu); 2492 } 2493 2494 /** 2495 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access 2496 * @vcpu: The VCPU pointer 2497 * @run: The kvm_run struct 2498 */ 2499 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu, 2500 const struct sys_reg_desc *global, 2501 size_t nr_global) 2502 { 2503 struct sys_reg_params params; 2504 u64 esr = kvm_vcpu_get_esr(vcpu); 2505 int Rt = kvm_vcpu_sys_get_rt(vcpu); 2506 int Rt2 = (esr >> 10) & 0x1f; 2507 2508 params.CRm = (esr >> 1) & 0xf; 2509 params.is_write = ((esr & 1) == 0); 2510 2511 params.Op0 = 0; 2512 params.Op1 = (esr >> 16) & 0xf; 2513 params.Op2 = 0; 2514 params.CRn = 0; 2515 2516 /* 2517 * Make a 64-bit value out of Rt and Rt2. As we use the same trap 2518 * backends between AArch32 and AArch64, we get away with it. 2519 */ 2520 if (params.is_write) { 2521 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff; 2522 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32; 2523 } 2524 2525 /* 2526 * If the table contains a handler, handle the 2527 * potential register operation in the case of a read and return 2528 * with success. 2529 */ 2530 if (emulate_cp(vcpu, ¶ms, global, nr_global)) { 2531 /* Split up the value between registers for the read side */ 2532 if (!params.is_write) { 2533 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval)); 2534 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval)); 2535 } 2536 2537 return 1; 2538 } 2539 2540 unhandled_cp_access(vcpu, ¶ms); 2541 return 1; 2542 } 2543 2544 static bool emulate_sys_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *params); 2545 2546 /* 2547 * The CP10 ID registers are architecturally mapped to AArch64 feature 2548 * registers. Abuse that fact so we can rely on the AArch64 handler for accesses 2549 * from AArch32. 2550 */ 2551 static bool kvm_esr_cp10_id_to_sys64(u64 esr, struct sys_reg_params *params) 2552 { 2553 u8 reg_id = (esr >> 10) & 0xf; 2554 bool valid; 2555 2556 params->is_write = ((esr & 1) == 0); 2557 params->Op0 = 3; 2558 params->Op1 = 0; 2559 params->CRn = 0; 2560 params->CRm = 3; 2561 2562 /* CP10 ID registers are read-only */ 2563 valid = !params->is_write; 2564 2565 switch (reg_id) { 2566 /* MVFR0 */ 2567 case 0b0111: 2568 params->Op2 = 0; 2569 break; 2570 /* MVFR1 */ 2571 case 0b0110: 2572 params->Op2 = 1; 2573 break; 2574 /* MVFR2 */ 2575 case 0b0101: 2576 params->Op2 = 2; 2577 break; 2578 default: 2579 valid = false; 2580 } 2581 2582 if (valid) 2583 return true; 2584 2585 kvm_pr_unimpl("Unhandled cp10 register %s: %u\n", 2586 params->is_write ? "write" : "read", reg_id); 2587 return false; 2588 } 2589 2590 /** 2591 * kvm_handle_cp10_id() - Handles a VMRS trap on guest access to a 'Media and 2592 * VFP Register' from AArch32. 2593 * @vcpu: The vCPU pointer 2594 * 2595 * MVFR{0-2} are architecturally mapped to the AArch64 MVFR{0-2}_EL1 registers. 2596 * Work out the correct AArch64 system register encoding and reroute to the 2597 * AArch64 system register emulation. 2598 */ 2599 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu) 2600 { 2601 int Rt = kvm_vcpu_sys_get_rt(vcpu); 2602 u64 esr = kvm_vcpu_get_esr(vcpu); 2603 struct sys_reg_params params; 2604 2605 /* UNDEF on any unhandled register access */ 2606 if (!kvm_esr_cp10_id_to_sys64(esr, ¶ms)) { 2607 kvm_inject_undefined(vcpu); 2608 return 1; 2609 } 2610 2611 if (emulate_sys_reg(vcpu, ¶ms)) 2612 vcpu_set_reg(vcpu, Rt, params.regval); 2613 2614 return 1; 2615 } 2616 2617 /** 2618 * kvm_emulate_cp15_id_reg() - Handles an MRC trap on a guest CP15 access where 2619 * CRn=0, which corresponds to the AArch32 feature 2620 * registers. 2621 * @vcpu: the vCPU pointer 2622 * @params: the system register access parameters. 2623 * 2624 * Our cp15 system register tables do not enumerate the AArch32 feature 2625 * registers. Conveniently, our AArch64 table does, and the AArch32 system 2626 * register encoding can be trivially remapped into the AArch64 for the feature 2627 * registers: Append op0=3, leaving op1, CRn, CRm, and op2 the same. 2628 * 2629 * According to DDI0487G.b G7.3.1, paragraph "Behavior of VMSAv8-32 32-bit 2630 * System registers with (coproc=0b1111, CRn==c0)", read accesses from this 2631 * range are either UNKNOWN or RES0. Rerouting remains architectural as we 2632 * treat undefined registers in this range as RAZ. 2633 */ 2634 static int kvm_emulate_cp15_id_reg(struct kvm_vcpu *vcpu, 2635 struct sys_reg_params *params) 2636 { 2637 int Rt = kvm_vcpu_sys_get_rt(vcpu); 2638 2639 /* Treat impossible writes to RO registers as UNDEFINED */ 2640 if (params->is_write) { 2641 unhandled_cp_access(vcpu, params); 2642 return 1; 2643 } 2644 2645 params->Op0 = 3; 2646 2647 /* 2648 * All registers where CRm > 3 are known to be UNKNOWN/RAZ from AArch32. 2649 * Avoid conflicting with future expansion of AArch64 feature registers 2650 * and simply treat them as RAZ here. 2651 */ 2652 if (params->CRm > 3) 2653 params->regval = 0; 2654 else if (!emulate_sys_reg(vcpu, params)) 2655 return 1; 2656 2657 vcpu_set_reg(vcpu, Rt, params->regval); 2658 return 1; 2659 } 2660 2661 /** 2662 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access 2663 * @vcpu: The VCPU pointer 2664 * @run: The kvm_run struct 2665 */ 2666 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu, 2667 struct sys_reg_params *params, 2668 const struct sys_reg_desc *global, 2669 size_t nr_global) 2670 { 2671 int Rt = kvm_vcpu_sys_get_rt(vcpu); 2672 2673 params->regval = vcpu_get_reg(vcpu, Rt); 2674 2675 if (emulate_cp(vcpu, params, global, nr_global)) { 2676 if (!params->is_write) 2677 vcpu_set_reg(vcpu, Rt, params->regval); 2678 return 1; 2679 } 2680 2681 unhandled_cp_access(vcpu, params); 2682 return 1; 2683 } 2684 2685 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu) 2686 { 2687 return kvm_handle_cp_64(vcpu, cp15_64_regs, ARRAY_SIZE(cp15_64_regs)); 2688 } 2689 2690 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu) 2691 { 2692 struct sys_reg_params params; 2693 2694 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu)); 2695 2696 /* 2697 * Certain AArch32 ID registers are handled by rerouting to the AArch64 2698 * system register table. Registers in the ID range where CRm=0 are 2699 * excluded from this scheme as they do not trivially map into AArch64 2700 * system register encodings. 2701 */ 2702 if (params.Op1 == 0 && params.CRn == 0 && params.CRm) 2703 return kvm_emulate_cp15_id_reg(vcpu, ¶ms); 2704 2705 return kvm_handle_cp_32(vcpu, ¶ms, cp15_regs, ARRAY_SIZE(cp15_regs)); 2706 } 2707 2708 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu) 2709 { 2710 return kvm_handle_cp_64(vcpu, cp14_64_regs, ARRAY_SIZE(cp14_64_regs)); 2711 } 2712 2713 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu) 2714 { 2715 struct sys_reg_params params; 2716 2717 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu)); 2718 2719 return kvm_handle_cp_32(vcpu, ¶ms, cp14_regs, ARRAY_SIZE(cp14_regs)); 2720 } 2721 2722 static bool is_imp_def_sys_reg(struct sys_reg_params *params) 2723 { 2724 // See ARM DDI 0487E.a, section D12.3.2 2725 return params->Op0 == 3 && (params->CRn & 0b1011) == 0b1011; 2726 } 2727 2728 /** 2729 * emulate_sys_reg - Emulate a guest access to an AArch64 system register 2730 * @vcpu: The VCPU pointer 2731 * @params: Decoded system register parameters 2732 * 2733 * Return: true if the system register access was successful, false otherwise. 2734 */ 2735 static bool emulate_sys_reg(struct kvm_vcpu *vcpu, 2736 struct sys_reg_params *params) 2737 { 2738 const struct sys_reg_desc *r; 2739 2740 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 2741 2742 if (likely(r)) { 2743 perform_access(vcpu, params, r); 2744 return true; 2745 } 2746 2747 if (is_imp_def_sys_reg(params)) { 2748 kvm_inject_undefined(vcpu); 2749 } else { 2750 print_sys_reg_msg(params, 2751 "Unsupported guest sys_reg access at: %lx [%08lx]\n", 2752 *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 2753 kvm_inject_undefined(vcpu); 2754 } 2755 return false; 2756 } 2757 2758 /** 2759 * kvm_reset_sys_regs - sets system registers to reset value 2760 * @vcpu: The VCPU pointer 2761 * 2762 * This function finds the right table above and sets the registers on the 2763 * virtual CPU struct to their architecturally defined reset values. 2764 */ 2765 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu) 2766 { 2767 unsigned long i; 2768 2769 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) 2770 if (sys_reg_descs[i].reset) 2771 sys_reg_descs[i].reset(vcpu, &sys_reg_descs[i]); 2772 } 2773 2774 /** 2775 * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access 2776 * @vcpu: The VCPU pointer 2777 */ 2778 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu) 2779 { 2780 struct sys_reg_params params; 2781 unsigned long esr = kvm_vcpu_get_esr(vcpu); 2782 int Rt = kvm_vcpu_sys_get_rt(vcpu); 2783 2784 trace_kvm_handle_sys_reg(esr); 2785 2786 params = esr_sys64_to_params(esr); 2787 params.regval = vcpu_get_reg(vcpu, Rt); 2788 2789 if (!emulate_sys_reg(vcpu, ¶ms)) 2790 return 1; 2791 2792 if (!params.is_write) 2793 vcpu_set_reg(vcpu, Rt, params.regval); 2794 return 1; 2795 } 2796 2797 /****************************************************************************** 2798 * Userspace API 2799 *****************************************************************************/ 2800 2801 static bool index_to_params(u64 id, struct sys_reg_params *params) 2802 { 2803 switch (id & KVM_REG_SIZE_MASK) { 2804 case KVM_REG_SIZE_U64: 2805 /* Any unused index bits means it's not valid. */ 2806 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK 2807 | KVM_REG_ARM_COPROC_MASK 2808 | KVM_REG_ARM64_SYSREG_OP0_MASK 2809 | KVM_REG_ARM64_SYSREG_OP1_MASK 2810 | KVM_REG_ARM64_SYSREG_CRN_MASK 2811 | KVM_REG_ARM64_SYSREG_CRM_MASK 2812 | KVM_REG_ARM64_SYSREG_OP2_MASK)) 2813 return false; 2814 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK) 2815 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT); 2816 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK) 2817 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT); 2818 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK) 2819 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT); 2820 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK) 2821 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT); 2822 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK) 2823 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT); 2824 return true; 2825 default: 2826 return false; 2827 } 2828 } 2829 2830 const struct sys_reg_desc *get_reg_by_id(u64 id, 2831 const struct sys_reg_desc table[], 2832 unsigned int num) 2833 { 2834 struct sys_reg_params params; 2835 2836 if (!index_to_params(id, ¶ms)) 2837 return NULL; 2838 2839 return find_reg(¶ms, table, num); 2840 } 2841 2842 /* Decode an index value, and find the sys_reg_desc entry. */ 2843 static const struct sys_reg_desc * 2844 id_to_sys_reg_desc(struct kvm_vcpu *vcpu, u64 id, 2845 const struct sys_reg_desc table[], unsigned int num) 2846 2847 { 2848 const struct sys_reg_desc *r; 2849 2850 /* We only do sys_reg for now. */ 2851 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG) 2852 return NULL; 2853 2854 r = get_reg_by_id(id, table, num); 2855 2856 /* Not saved in the sys_reg array and not otherwise accessible? */ 2857 if (r && (!(r->reg || r->get_user) || sysreg_hidden(vcpu, r))) 2858 r = NULL; 2859 2860 return r; 2861 } 2862 2863 /* 2864 * These are the invariant sys_reg registers: we let the guest see the 2865 * host versions of these, so they're part of the guest state. 2866 * 2867 * A future CPU may provide a mechanism to present different values to 2868 * the guest, or a future kvm may trap them. 2869 */ 2870 2871 #define FUNCTION_INVARIANT(reg) \ 2872 static void get_##reg(struct kvm_vcpu *v, \ 2873 const struct sys_reg_desc *r) \ 2874 { \ 2875 ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \ 2876 } 2877 2878 FUNCTION_INVARIANT(midr_el1) 2879 FUNCTION_INVARIANT(revidr_el1) 2880 FUNCTION_INVARIANT(clidr_el1) 2881 FUNCTION_INVARIANT(aidr_el1) 2882 2883 static void get_ctr_el0(struct kvm_vcpu *v, const struct sys_reg_desc *r) 2884 { 2885 ((struct sys_reg_desc *)r)->val = read_sanitised_ftr_reg(SYS_CTR_EL0); 2886 } 2887 2888 /* ->val is filled in by kvm_sys_reg_table_init() */ 2889 static struct sys_reg_desc invariant_sys_regs[] = { 2890 { SYS_DESC(SYS_MIDR_EL1), NULL, get_midr_el1 }, 2891 { SYS_DESC(SYS_REVIDR_EL1), NULL, get_revidr_el1 }, 2892 { SYS_DESC(SYS_CLIDR_EL1), NULL, get_clidr_el1 }, 2893 { SYS_DESC(SYS_AIDR_EL1), NULL, get_aidr_el1 }, 2894 { SYS_DESC(SYS_CTR_EL0), NULL, get_ctr_el0 }, 2895 }; 2896 2897 static int get_invariant_sys_reg(u64 id, u64 __user *uaddr) 2898 { 2899 const struct sys_reg_desc *r; 2900 2901 r = get_reg_by_id(id, invariant_sys_regs, 2902 ARRAY_SIZE(invariant_sys_regs)); 2903 if (!r) 2904 return -ENOENT; 2905 2906 return put_user(r->val, uaddr); 2907 } 2908 2909 static int set_invariant_sys_reg(u64 id, u64 __user *uaddr) 2910 { 2911 const struct sys_reg_desc *r; 2912 u64 val; 2913 2914 r = get_reg_by_id(id, invariant_sys_regs, 2915 ARRAY_SIZE(invariant_sys_regs)); 2916 if (!r) 2917 return -ENOENT; 2918 2919 if (get_user(val, uaddr)) 2920 return -EFAULT; 2921 2922 /* This is what we mean by invariant: you can't change it. */ 2923 if (r->val != val) 2924 return -EINVAL; 2925 2926 return 0; 2927 } 2928 2929 static bool is_valid_cache(u32 val) 2930 { 2931 u32 level, ctype; 2932 2933 if (val >= CSSELR_MAX) 2934 return false; 2935 2936 /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */ 2937 level = (val >> 1); 2938 ctype = (cache_levels >> (level * 3)) & 7; 2939 2940 switch (ctype) { 2941 case 0: /* No cache */ 2942 return false; 2943 case 1: /* Instruction cache only */ 2944 return (val & 1); 2945 case 2: /* Data cache only */ 2946 case 4: /* Unified cache */ 2947 return !(val & 1); 2948 case 3: /* Separate instruction and data caches */ 2949 return true; 2950 default: /* Reserved: we can't know instruction or data. */ 2951 return false; 2952 } 2953 } 2954 2955 static int demux_c15_get(u64 id, void __user *uaddr) 2956 { 2957 u32 val; 2958 u32 __user *uval = uaddr; 2959 2960 /* Fail if we have unknown bits set. */ 2961 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 2962 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 2963 return -ENOENT; 2964 2965 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 2966 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 2967 if (KVM_REG_SIZE(id) != 4) 2968 return -ENOENT; 2969 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 2970 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 2971 if (!is_valid_cache(val)) 2972 return -ENOENT; 2973 2974 return put_user(get_ccsidr(val), uval); 2975 default: 2976 return -ENOENT; 2977 } 2978 } 2979 2980 static int demux_c15_set(u64 id, void __user *uaddr) 2981 { 2982 u32 val, newval; 2983 u32 __user *uval = uaddr; 2984 2985 /* Fail if we have unknown bits set. */ 2986 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 2987 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 2988 return -ENOENT; 2989 2990 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 2991 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 2992 if (KVM_REG_SIZE(id) != 4) 2993 return -ENOENT; 2994 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 2995 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 2996 if (!is_valid_cache(val)) 2997 return -ENOENT; 2998 2999 if (get_user(newval, uval)) 3000 return -EFAULT; 3001 3002 /* This is also invariant: you can't change it. */ 3003 if (newval != get_ccsidr(val)) 3004 return -EINVAL; 3005 return 0; 3006 default: 3007 return -ENOENT; 3008 } 3009 } 3010 3011 int kvm_sys_reg_get_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg, 3012 const struct sys_reg_desc table[], unsigned int num) 3013 { 3014 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr; 3015 const struct sys_reg_desc *r; 3016 u64 val; 3017 int ret; 3018 3019 r = id_to_sys_reg_desc(vcpu, reg->id, table, num); 3020 if (!r || sysreg_hidden_user(vcpu, r)) 3021 return -ENOENT; 3022 3023 if (r->get_user) { 3024 ret = (r->get_user)(vcpu, r, &val); 3025 } else { 3026 val = __vcpu_sys_reg(vcpu, r->reg); 3027 ret = 0; 3028 } 3029 3030 if (!ret) 3031 ret = put_user(val, uaddr); 3032 3033 return ret; 3034 } 3035 3036 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 3037 { 3038 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 3039 int err; 3040 3041 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 3042 return demux_c15_get(reg->id, uaddr); 3043 3044 err = get_invariant_sys_reg(reg->id, uaddr); 3045 if (err != -ENOENT) 3046 return err; 3047 3048 return kvm_sys_reg_get_user(vcpu, reg, 3049 sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 3050 } 3051 3052 int kvm_sys_reg_set_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg, 3053 const struct sys_reg_desc table[], unsigned int num) 3054 { 3055 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr; 3056 const struct sys_reg_desc *r; 3057 u64 val; 3058 int ret; 3059 3060 if (get_user(val, uaddr)) 3061 return -EFAULT; 3062 3063 r = id_to_sys_reg_desc(vcpu, reg->id, table, num); 3064 if (!r || sysreg_hidden_user(vcpu, r)) 3065 return -ENOENT; 3066 3067 if (sysreg_user_write_ignore(vcpu, r)) 3068 return 0; 3069 3070 if (r->set_user) { 3071 ret = (r->set_user)(vcpu, r, val); 3072 } else { 3073 __vcpu_sys_reg(vcpu, r->reg) = val; 3074 ret = 0; 3075 } 3076 3077 return ret; 3078 } 3079 3080 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 3081 { 3082 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 3083 int err; 3084 3085 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 3086 return demux_c15_set(reg->id, uaddr); 3087 3088 err = set_invariant_sys_reg(reg->id, uaddr); 3089 if (err != -ENOENT) 3090 return err; 3091 3092 return kvm_sys_reg_set_user(vcpu, reg, 3093 sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 3094 } 3095 3096 static unsigned int num_demux_regs(void) 3097 { 3098 unsigned int i, count = 0; 3099 3100 for (i = 0; i < CSSELR_MAX; i++) 3101 if (is_valid_cache(i)) 3102 count++; 3103 3104 return count; 3105 } 3106 3107 static int write_demux_regids(u64 __user *uindices) 3108 { 3109 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX; 3110 unsigned int i; 3111 3112 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR; 3113 for (i = 0; i < CSSELR_MAX; i++) { 3114 if (!is_valid_cache(i)) 3115 continue; 3116 if (put_user(val | i, uindices)) 3117 return -EFAULT; 3118 uindices++; 3119 } 3120 return 0; 3121 } 3122 3123 static u64 sys_reg_to_index(const struct sys_reg_desc *reg) 3124 { 3125 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | 3126 KVM_REG_ARM64_SYSREG | 3127 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) | 3128 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) | 3129 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) | 3130 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) | 3131 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT)); 3132 } 3133 3134 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind) 3135 { 3136 if (!*uind) 3137 return true; 3138 3139 if (put_user(sys_reg_to_index(reg), *uind)) 3140 return false; 3141 3142 (*uind)++; 3143 return true; 3144 } 3145 3146 static int walk_one_sys_reg(const struct kvm_vcpu *vcpu, 3147 const struct sys_reg_desc *rd, 3148 u64 __user **uind, 3149 unsigned int *total) 3150 { 3151 /* 3152 * Ignore registers we trap but don't save, 3153 * and for which no custom user accessor is provided. 3154 */ 3155 if (!(rd->reg || rd->get_user)) 3156 return 0; 3157 3158 if (sysreg_hidden_user(vcpu, rd)) 3159 return 0; 3160 3161 if (!copy_reg_to_user(rd, uind)) 3162 return -EFAULT; 3163 3164 (*total)++; 3165 return 0; 3166 } 3167 3168 /* Assumed ordered tables, see kvm_sys_reg_table_init. */ 3169 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind) 3170 { 3171 const struct sys_reg_desc *i2, *end2; 3172 unsigned int total = 0; 3173 int err; 3174 3175 i2 = sys_reg_descs; 3176 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs); 3177 3178 while (i2 != end2) { 3179 err = walk_one_sys_reg(vcpu, i2++, &uind, &total); 3180 if (err) 3181 return err; 3182 } 3183 return total; 3184 } 3185 3186 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu) 3187 { 3188 return ARRAY_SIZE(invariant_sys_regs) 3189 + num_demux_regs() 3190 + walk_sys_regs(vcpu, (u64 __user *)NULL); 3191 } 3192 3193 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) 3194 { 3195 unsigned int i; 3196 int err; 3197 3198 /* Then give them all the invariant registers' indices. */ 3199 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) { 3200 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices)) 3201 return -EFAULT; 3202 uindices++; 3203 } 3204 3205 err = walk_sys_regs(vcpu, uindices); 3206 if (err < 0) 3207 return err; 3208 uindices += err; 3209 3210 return write_demux_regids(uindices); 3211 } 3212 3213 int kvm_sys_reg_table_init(void) 3214 { 3215 bool valid = true; 3216 unsigned int i; 3217 struct sys_reg_desc clidr; 3218 3219 /* Make sure tables are unique and in order. */ 3220 valid &= check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), false); 3221 valid &= check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), true); 3222 valid &= check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), true); 3223 valid &= check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), true); 3224 valid &= check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), true); 3225 valid &= check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs), false); 3226 3227 if (!valid) 3228 return -EINVAL; 3229 3230 /* We abuse the reset function to overwrite the table itself. */ 3231 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) 3232 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]); 3233 3234 /* 3235 * CLIDR format is awkward, so clean it up. See ARM B4.1.20: 3236 * 3237 * If software reads the Cache Type fields from Ctype1 3238 * upwards, once it has seen a value of 0b000, no caches 3239 * exist at further-out levels of the hierarchy. So, for 3240 * example, if Ctype3 is the first Cache Type field with a 3241 * value of 0b000, the values of Ctype4 to Ctype7 must be 3242 * ignored. 3243 */ 3244 get_clidr_el1(NULL, &clidr); /* Ugly... */ 3245 cache_levels = clidr.val; 3246 for (i = 0; i < 7; i++) 3247 if (((cache_levels >> (i*3)) & 7) == 0) 3248 break; 3249 /* Clear all higher bits. */ 3250 cache_levels &= (1 << (i*3))-1; 3251 3252 return 0; 3253 } 3254