1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/kvm/coproc.c: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Authors: Rusty Russell <rusty@rustcorp.com.au> 9 * Christoffer Dall <c.dall@virtualopensystems.com> 10 */ 11 12 #include <linux/bitfield.h> 13 #include <linux/bsearch.h> 14 #include <linux/cacheinfo.h> 15 #include <linux/debugfs.h> 16 #include <linux/kvm_host.h> 17 #include <linux/mm.h> 18 #include <linux/printk.h> 19 #include <linux/uaccess.h> 20 #include <linux/irqchip/arm-gic-v3.h> 21 22 #include <asm/arm_pmuv3.h> 23 #include <asm/cacheflush.h> 24 #include <asm/cputype.h> 25 #include <asm/debug-monitors.h> 26 #include <asm/esr.h> 27 #include <asm/kvm_arm.h> 28 #include <asm/kvm_emulate.h> 29 #include <asm/kvm_hyp.h> 30 #include <asm/kvm_mmu.h> 31 #include <asm/kvm_nested.h> 32 #include <asm/perf_event.h> 33 #include <asm/sysreg.h> 34 35 #include <trace/events/kvm.h> 36 37 #include "sys_regs.h" 38 #include "vgic/vgic.h" 39 40 #include "trace.h" 41 42 /* 43 * For AArch32, we only take care of what is being trapped. Anything 44 * that has to do with init and userspace access has to go via the 45 * 64bit interface. 46 */ 47 48 static u64 sys_reg_to_index(const struct sys_reg_desc *reg); 49 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 50 u64 val); 51 52 static bool undef_access(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 53 const struct sys_reg_desc *r) 54 { 55 kvm_inject_undefined(vcpu); 56 return false; 57 } 58 59 static bool bad_trap(struct kvm_vcpu *vcpu, 60 struct sys_reg_params *params, 61 const struct sys_reg_desc *r, 62 const char *msg) 63 { 64 WARN_ONCE(1, "Unexpected %s\n", msg); 65 print_sys_reg_instr(params); 66 return undef_access(vcpu, params, r); 67 } 68 69 static bool read_from_write_only(struct kvm_vcpu *vcpu, 70 struct sys_reg_params *params, 71 const struct sys_reg_desc *r) 72 { 73 return bad_trap(vcpu, params, r, 74 "sys_reg read to write-only register"); 75 } 76 77 static bool write_to_read_only(struct kvm_vcpu *vcpu, 78 struct sys_reg_params *params, 79 const struct sys_reg_desc *r) 80 { 81 return bad_trap(vcpu, params, r, 82 "sys_reg write to read-only register"); 83 } 84 85 enum sr_loc_attr { 86 SR_LOC_MEMORY = 0, /* Register definitely in memory */ 87 SR_LOC_LOADED = BIT(0), /* Register on CPU, unless it cannot */ 88 SR_LOC_MAPPED = BIT(1), /* Register in a different CPU register */ 89 SR_LOC_XLATED = BIT(2), /* Register translated to fit another reg */ 90 SR_LOC_SPECIAL = BIT(3), /* Demanding register, implies loaded */ 91 }; 92 93 struct sr_loc { 94 enum sr_loc_attr loc; 95 enum vcpu_sysreg map_reg; 96 u64 (*xlate)(u64); 97 }; 98 99 static enum sr_loc_attr locate_direct_register(const struct kvm_vcpu *vcpu, 100 enum vcpu_sysreg reg) 101 { 102 switch (reg) { 103 case SCTLR_EL1: 104 case CPACR_EL1: 105 case TTBR0_EL1: 106 case TTBR1_EL1: 107 case TCR_EL1: 108 case TCR2_EL1: 109 case PIR_EL1: 110 case PIRE0_EL1: 111 case POR_EL1: 112 case ESR_EL1: 113 case AFSR0_EL1: 114 case AFSR1_EL1: 115 case FAR_EL1: 116 case MAIR_EL1: 117 case VBAR_EL1: 118 case CONTEXTIDR_EL1: 119 case AMAIR_EL1: 120 case CNTKCTL_EL1: 121 case ELR_EL1: 122 case SPSR_EL1: 123 case ZCR_EL1: 124 case SCTLR2_EL1: 125 /* 126 * EL1 registers which have an ELx2 mapping are loaded if 127 * we're not in hypervisor context. 128 */ 129 return is_hyp_ctxt(vcpu) ? SR_LOC_MEMORY : SR_LOC_LOADED; 130 131 case TPIDR_EL0: 132 case TPIDRRO_EL0: 133 case TPIDR_EL1: 134 case PAR_EL1: 135 case DACR32_EL2: 136 case IFSR32_EL2: 137 case DBGVCR32_EL2: 138 /* These registers are always loaded, no matter what */ 139 return SR_LOC_LOADED; 140 141 default: 142 /* Non-mapped EL2 registers are by definition in memory. */ 143 return SR_LOC_MEMORY; 144 } 145 } 146 147 static void locate_mapped_el2_register(const struct kvm_vcpu *vcpu, 148 enum vcpu_sysreg reg, 149 enum vcpu_sysreg map_reg, 150 u64 (*xlate)(u64), 151 struct sr_loc *loc) 152 { 153 if (!is_hyp_ctxt(vcpu)) { 154 loc->loc = SR_LOC_MEMORY; 155 return; 156 } 157 158 loc->loc = SR_LOC_LOADED | SR_LOC_MAPPED; 159 loc->map_reg = map_reg; 160 161 WARN_ON(locate_direct_register(vcpu, map_reg) != SR_LOC_MEMORY); 162 163 if (xlate != NULL && !vcpu_el2_e2h_is_set(vcpu)) { 164 loc->loc |= SR_LOC_XLATED; 165 loc->xlate = xlate; 166 } 167 } 168 169 #define MAPPED_EL2_SYSREG(r, m, t) \ 170 case r: { \ 171 locate_mapped_el2_register(vcpu, r, m, t, loc); \ 172 break; \ 173 } 174 175 static void locate_register(const struct kvm_vcpu *vcpu, enum vcpu_sysreg reg, 176 struct sr_loc *loc) 177 { 178 if (!vcpu_get_flag(vcpu, SYSREGS_ON_CPU)) { 179 loc->loc = SR_LOC_MEMORY; 180 return; 181 } 182 183 switch (reg) { 184 MAPPED_EL2_SYSREG(SCTLR_EL2, SCTLR_EL1, 185 translate_sctlr_el2_to_sctlr_el1 ); 186 MAPPED_EL2_SYSREG(TTBR0_EL2, TTBR0_EL1, 187 translate_ttbr0_el2_to_ttbr0_el1 ); 188 MAPPED_EL2_SYSREG(TTBR1_EL2, TTBR1_EL1, NULL ); 189 MAPPED_EL2_SYSREG(TCR_EL2, TCR_EL1, 190 translate_tcr_el2_to_tcr_el1 ); 191 MAPPED_EL2_SYSREG(VBAR_EL2, VBAR_EL1, NULL ); 192 MAPPED_EL2_SYSREG(AFSR0_EL2, AFSR0_EL1, NULL ); 193 MAPPED_EL2_SYSREG(AFSR1_EL2, AFSR1_EL1, NULL ); 194 MAPPED_EL2_SYSREG(ESR_EL2, ESR_EL1, NULL ); 195 MAPPED_EL2_SYSREG(FAR_EL2, FAR_EL1, NULL ); 196 MAPPED_EL2_SYSREG(MAIR_EL2, MAIR_EL1, NULL ); 197 MAPPED_EL2_SYSREG(TCR2_EL2, TCR2_EL1, NULL ); 198 MAPPED_EL2_SYSREG(PIR_EL2, PIR_EL1, NULL ); 199 MAPPED_EL2_SYSREG(PIRE0_EL2, PIRE0_EL1, NULL ); 200 MAPPED_EL2_SYSREG(POR_EL2, POR_EL1, NULL ); 201 MAPPED_EL2_SYSREG(AMAIR_EL2, AMAIR_EL1, NULL ); 202 MAPPED_EL2_SYSREG(ELR_EL2, ELR_EL1, NULL ); 203 MAPPED_EL2_SYSREG(SPSR_EL2, SPSR_EL1, NULL ); 204 MAPPED_EL2_SYSREG(CONTEXTIDR_EL2, CONTEXTIDR_EL1, NULL ); 205 MAPPED_EL2_SYSREG(SCTLR2_EL2, SCTLR2_EL1, NULL ); 206 case CNTHCTL_EL2: 207 /* CNTHCTL_EL2 is super special, until we support NV2.1 */ 208 loc->loc = ((is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) ? 209 SR_LOC_SPECIAL : SR_LOC_MEMORY); 210 break; 211 case CPTR_EL2: 212 /* 213 * CPTR_EL2 is just as special, and needs a certain amount 214 * of handholding. It always lives in memory, due to being 215 * heavily trapped thanks to CPACR_EL1.TCPAC being RES0. 216 * FEAT_NV2p1 fixes this. 217 */ 218 locate_mapped_el2_register(vcpu, CPTR_EL2, CPACR_EL1, 219 translate_cptr_el2_to_cpacr_el1, 220 loc); 221 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) 222 loc->loc = SR_LOC_SPECIAL; 223 break; 224 case NVHCR_EL2: 225 /* 226 * Yes, NVHCR_EL2 maps to itself when loaded in nested 227 * context. If you feel like the architecture is double 228 * backing on itself upside down, you're not alone. 229 */ 230 WARN_ON_ONCE(!kvm_has_nv3(vcpu->kvm)); 231 if (is_hyp_ctxt(vcpu)) { 232 loc->loc = SR_LOC_MEMORY; 233 } else { 234 loc->loc = SR_LOC_LOADED | SR_LOC_MAPPED; 235 loc->map_reg = NVHCR_EL2; 236 } 237 break; 238 default: 239 loc->loc = locate_direct_register(vcpu, reg); 240 } 241 } 242 243 static u64 read_sr_from_cpu(enum vcpu_sysreg reg) 244 { 245 u64 val = 0x8badf00d8badf00d; 246 247 switch (reg) { 248 case SCTLR_EL1: val = read_sysreg_s(SYS_SCTLR_EL12); break; 249 case CPACR_EL1: val = read_sysreg_s(SYS_CPACR_EL12); break; 250 case TTBR0_EL1: val = read_sysreg_s(SYS_TTBR0_EL12); break; 251 case TTBR1_EL1: val = read_sysreg_s(SYS_TTBR1_EL12); break; 252 case TCR_EL1: val = read_sysreg_s(SYS_TCR_EL12); break; 253 case TCR2_EL1: val = read_sysreg_s(SYS_TCR2_EL12); break; 254 case PIR_EL1: val = read_sysreg_s(SYS_PIR_EL12); break; 255 case PIRE0_EL1: val = read_sysreg_s(SYS_PIRE0_EL12); break; 256 case POR_EL1: val = read_sysreg_s(SYS_POR_EL12); break; 257 case ESR_EL1: val = read_sysreg_s(SYS_ESR_EL12); break; 258 case AFSR0_EL1: val = read_sysreg_s(SYS_AFSR0_EL12); break; 259 case AFSR1_EL1: val = read_sysreg_s(SYS_AFSR1_EL12); break; 260 case FAR_EL1: val = read_sysreg_s(SYS_FAR_EL12); break; 261 case MAIR_EL1: val = read_sysreg_s(SYS_MAIR_EL12); break; 262 case VBAR_EL1: val = read_sysreg_s(SYS_VBAR_EL12); break; 263 case CONTEXTIDR_EL1: val = read_sysreg_s(SYS_CONTEXTIDR_EL12);break; 264 case AMAIR_EL1: val = read_sysreg_s(SYS_AMAIR_EL12); break; 265 case CNTKCTL_EL1: val = read_sysreg_s(SYS_CNTKCTL_EL12); break; 266 case ELR_EL1: val = read_sysreg_s(SYS_ELR_EL12); break; 267 case SPSR_EL1: val = read_sysreg_s(SYS_SPSR_EL12); break; 268 case ZCR_EL1: val = read_sysreg_s(SYS_ZCR_EL12); break; 269 case SCTLR2_EL1: val = read_sysreg_s(SYS_SCTLR2_EL12); break; 270 case TPIDR_EL0: val = read_sysreg_s(SYS_TPIDR_EL0); break; 271 case TPIDRRO_EL0: val = read_sysreg_s(SYS_TPIDRRO_EL0); break; 272 case TPIDR_EL1: val = read_sysreg_s(SYS_TPIDR_EL1); break; 273 case PAR_EL1: val = read_sysreg_par(); break; 274 case DACR32_EL2: val = read_sysreg_s(SYS_DACR32_EL2); break; 275 case IFSR32_EL2: val = read_sysreg_s(SYS_IFSR32_EL2); break; 276 case DBGVCR32_EL2: val = read_sysreg_s(SYS_DBGVCR32_EL2); break; 277 case NVHCR_EL2: val = read_sysreg_s(SYS_NVHCR_EL2); break; 278 default: WARN_ON_ONCE(1); 279 } 280 281 return val; 282 } 283 284 static void write_sr_to_cpu(enum vcpu_sysreg reg, u64 val) 285 { 286 switch (reg) { 287 case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); break; 288 case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); break; 289 case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); break; 290 case TTBR1_EL1: write_sysreg_s(val, SYS_TTBR1_EL12); break; 291 case TCR_EL1: write_sysreg_s(val, SYS_TCR_EL12); break; 292 case TCR2_EL1: write_sysreg_s(val, SYS_TCR2_EL12); break; 293 case PIR_EL1: write_sysreg_s(val, SYS_PIR_EL12); break; 294 case PIRE0_EL1: write_sysreg_s(val, SYS_PIRE0_EL12); break; 295 case POR_EL1: write_sysreg_s(val, SYS_POR_EL12); break; 296 case ESR_EL1: write_sysreg_s(val, SYS_ESR_EL12); break; 297 case AFSR0_EL1: write_sysreg_s(val, SYS_AFSR0_EL12); break; 298 case AFSR1_EL1: write_sysreg_s(val, SYS_AFSR1_EL12); break; 299 case FAR_EL1: write_sysreg_s(val, SYS_FAR_EL12); break; 300 case MAIR_EL1: write_sysreg_s(val, SYS_MAIR_EL12); break; 301 case VBAR_EL1: write_sysreg_s(val, SYS_VBAR_EL12); break; 302 case CONTEXTIDR_EL1: write_sysreg_s(val, SYS_CONTEXTIDR_EL12);break; 303 case AMAIR_EL1: write_sysreg_s(val, SYS_AMAIR_EL12); break; 304 case CNTKCTL_EL1: write_sysreg_s(val, SYS_CNTKCTL_EL12); break; 305 case ELR_EL1: write_sysreg_s(val, SYS_ELR_EL12); break; 306 case SPSR_EL1: write_sysreg_s(val, SYS_SPSR_EL12); break; 307 case ZCR_EL1: write_sysreg_s(val, SYS_ZCR_EL12); break; 308 case SCTLR2_EL1: write_sysreg_s(val, SYS_SCTLR2_EL12); break; 309 case TPIDR_EL0: write_sysreg_s(val, SYS_TPIDR_EL0); break; 310 case TPIDRRO_EL0: write_sysreg_s(val, SYS_TPIDRRO_EL0); break; 311 case TPIDR_EL1: write_sysreg_s(val, SYS_TPIDR_EL1); break; 312 case PAR_EL1: write_sysreg_s(val, SYS_PAR_EL1); break; 313 case DACR32_EL2: write_sysreg_s(val, SYS_DACR32_EL2); break; 314 case IFSR32_EL2: write_sysreg_s(val, SYS_IFSR32_EL2); break; 315 case DBGVCR32_EL2: write_sysreg_s(val, SYS_DBGVCR32_EL2); break; 316 case NVHCR_EL2: write_sysreg_s(val, SYS_NVHCR_EL2); break; 317 default: WARN_ON_ONCE(1); 318 } 319 } 320 321 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, enum vcpu_sysreg reg) 322 { 323 struct sr_loc loc = {}; 324 325 locate_register(vcpu, reg, &loc); 326 327 WARN_ON_ONCE(!has_vhe() && loc.loc != SR_LOC_MEMORY); 328 329 if (loc.loc & SR_LOC_SPECIAL) { 330 u64 val; 331 332 WARN_ON_ONCE(loc.loc & ~SR_LOC_SPECIAL); 333 334 /* 335 * CNTHCTL_EL2 requires some special treatment to account 336 * for the bits that can be set via CNTKCTL_EL1 when E2H==1. 337 */ 338 switch (reg) { 339 case CNTHCTL_EL2: 340 val = read_sysreg_el1(SYS_CNTKCTL); 341 if (!cpus_have_final_cap(ARM64_HAS_NV2P1)) { 342 val &= CNTKCTL_VALID_BITS; 343 val |= __vcpu_sys_reg(vcpu, reg) & ~CNTKCTL_VALID_BITS; 344 } 345 return val; 346 case CPTR_EL2: 347 if (cpus_have_final_cap(ARM64_HAS_NV2P1)) 348 return read_sysreg_el1(SYS_CPACR); 349 else 350 return __vcpu_sys_reg(vcpu, reg); 351 default: 352 WARN_ON_ONCE(1); 353 } 354 } 355 356 if (loc.loc & SR_LOC_LOADED) { 357 enum vcpu_sysreg map_reg = reg; 358 359 if (loc.loc & SR_LOC_MAPPED) 360 map_reg = loc.map_reg; 361 362 if (!(loc.loc & SR_LOC_XLATED)) { 363 u64 val = read_sr_from_cpu(map_reg); 364 365 if (reg >= __SANITISED_REG_START__) 366 val = kvm_vcpu_apply_reg_masks(vcpu, reg, val); 367 368 return val; 369 } 370 } 371 372 return __vcpu_sys_reg(vcpu, reg); 373 } 374 375 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, enum vcpu_sysreg reg) 376 { 377 struct sr_loc loc = {}; 378 379 locate_register(vcpu, reg, &loc); 380 381 WARN_ON_ONCE(!has_vhe() && loc.loc != SR_LOC_MEMORY); 382 383 if (loc.loc & SR_LOC_SPECIAL) { 384 385 WARN_ON_ONCE(loc.loc & ~SR_LOC_SPECIAL); 386 387 switch (reg) { 388 case CNTHCTL_EL2: 389 /* 390 * If E2H=1, some of the bits are backed by 391 * CNTKCTL_EL1, while the rest is kept in memory. 392 * Yes, this is fun stuff. 393 */ 394 write_sysreg_el1(val, SYS_CNTKCTL); 395 break; 396 case CPTR_EL2: 397 write_sysreg_el1(val, SYS_CPACR); 398 break; 399 default: 400 WARN_ON_ONCE(1); 401 } 402 } 403 404 if (loc.loc & SR_LOC_LOADED) { 405 enum vcpu_sysreg map_reg = reg; 406 u64 xlated_val; 407 408 if (reg >= __SANITISED_REG_START__) 409 val = kvm_vcpu_apply_reg_masks(vcpu, reg, val); 410 411 if (loc.loc & SR_LOC_MAPPED) 412 map_reg = loc.map_reg; 413 414 if (loc.loc & SR_LOC_XLATED) 415 xlated_val = loc.xlate(val); 416 else 417 xlated_val = val; 418 419 write_sr_to_cpu(map_reg, xlated_val); 420 421 /* 422 * Fall through to write the backing store anyway, which 423 * allows translated registers to be directly read without a 424 * reverse translation. 425 */ 426 } 427 428 __vcpu_assign_sys_reg(vcpu, reg, val); 429 } 430 431 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */ 432 #define CSSELR_MAX 14 433 434 /* 435 * Returns the minimum line size for the selected cache, expressed as 436 * Log2(bytes). 437 */ 438 static u8 get_min_cache_line_size(bool icache) 439 { 440 u64 ctr = read_sanitised_ftr_reg(SYS_CTR_EL0); 441 u8 field; 442 443 if (icache) 444 field = SYS_FIELD_GET(CTR_EL0, IminLine, ctr); 445 else 446 field = SYS_FIELD_GET(CTR_EL0, DminLine, ctr); 447 448 /* 449 * Cache line size is represented as Log2(words) in CTR_EL0. 450 * Log2(bytes) can be derived with the following: 451 * 452 * Log2(words) + 2 = Log2(bytes / 4) + 2 453 * = Log2(bytes) - 2 + 2 454 * = Log2(bytes) 455 */ 456 return field + 2; 457 } 458 459 /* Which cache CCSIDR represents depends on CSSELR value. */ 460 static u32 get_ccsidr(struct kvm_vcpu *vcpu, u32 csselr) 461 { 462 u8 line_size; 463 464 if (vcpu->arch.ccsidr) 465 return vcpu->arch.ccsidr[csselr]; 466 467 line_size = get_min_cache_line_size(csselr & CSSELR_EL1_InD); 468 469 /* 470 * Fabricate a CCSIDR value as the overriding value does not exist. 471 * The real CCSIDR value will not be used as it can vary by the 472 * physical CPU which the vcpu currently resides in. 473 * 474 * The line size is determined with get_min_cache_line_size(), which 475 * should be valid for all CPUs even if they have different cache 476 * configuration. 477 * 478 * The associativity bits are cleared, meaning the geometry of all data 479 * and unified caches (which are guaranteed to be PIPT and thus 480 * non-aliasing) are 1 set and 1 way. 481 * Guests should not be doing cache operations by set/way at all, and 482 * for this reason, we trap them and attempt to infer the intent, so 483 * that we can flush the entire guest's address space at the appropriate 484 * time. The exposed geometry minimizes the number of the traps. 485 * [If guests should attempt to infer aliasing properties from the 486 * geometry (which is not permitted by the architecture), they would 487 * only do so for virtually indexed caches.] 488 * 489 * We don't check if the cache level exists as it is allowed to return 490 * an UNKNOWN value if not. 491 */ 492 return SYS_FIELD_PREP(CCSIDR_EL1, LineSize, line_size - 4); 493 } 494 495 static int set_ccsidr(struct kvm_vcpu *vcpu, u32 csselr, u32 val) 496 { 497 u8 line_size = FIELD_GET(CCSIDR_EL1_LineSize, val) + 4; 498 u32 *ccsidr = vcpu->arch.ccsidr; 499 u32 i; 500 501 if ((val & CCSIDR_EL1_RES0) || 502 line_size < get_min_cache_line_size(csselr & CSSELR_EL1_InD)) 503 return -EINVAL; 504 505 if (!ccsidr) { 506 if (val == get_ccsidr(vcpu, csselr)) 507 return 0; 508 509 ccsidr = kmalloc_array(CSSELR_MAX, sizeof(u32), GFP_KERNEL_ACCOUNT); 510 if (!ccsidr) 511 return -ENOMEM; 512 513 for (i = 0; i < CSSELR_MAX; i++) 514 ccsidr[i] = get_ccsidr(vcpu, i); 515 516 vcpu->arch.ccsidr = ccsidr; 517 } 518 519 ccsidr[csselr] = val; 520 521 return 0; 522 } 523 524 static bool access_rw(struct kvm_vcpu *vcpu, 525 struct sys_reg_params *p, 526 const struct sys_reg_desc *r) 527 { 528 if (p->is_write) 529 vcpu_write_sys_reg(vcpu, p->regval, r->reg); 530 else 531 p->regval = vcpu_read_sys_reg(vcpu, r->reg); 532 533 return true; 534 } 535 536 /* 537 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized). 538 */ 539 static bool access_dcsw(struct kvm_vcpu *vcpu, 540 struct sys_reg_params *p, 541 const struct sys_reg_desc *r) 542 { 543 if (!p->is_write) 544 return read_from_write_only(vcpu, p, r); 545 546 /* 547 * Only track S/W ops if we don't have FWB. It still indicates 548 * that the guest is a bit broken (S/W operations should only 549 * be done by firmware, knowing that there is only a single 550 * CPU left in the system, and certainly not from non-secure 551 * software). 552 */ 553 if (!cpus_have_final_cap(ARM64_HAS_STAGE2_FWB)) 554 kvm_set_way_flush(vcpu); 555 556 return true; 557 } 558 559 static bool access_dcgsw(struct kvm_vcpu *vcpu, 560 struct sys_reg_params *p, 561 const struct sys_reg_desc *r) 562 { 563 if (!kvm_has_mte(vcpu->kvm)) 564 return undef_access(vcpu, p, r); 565 566 /* Treat MTE S/W ops as we treat the classic ones: with contempt */ 567 return access_dcsw(vcpu, p, r); 568 } 569 570 static void get_access_mask(const struct sys_reg_desc *r, u64 *mask, u64 *shift) 571 { 572 switch (r->aarch32_map) { 573 case AA32_LO: 574 *mask = GENMASK_ULL(31, 0); 575 *shift = 0; 576 break; 577 case AA32_HI: 578 *mask = GENMASK_ULL(63, 32); 579 *shift = 32; 580 break; 581 default: 582 *mask = GENMASK_ULL(63, 0); 583 *shift = 0; 584 break; 585 } 586 } 587 588 /* 589 * Generic accessor for VM registers. Only called as long as HCR_TVM 590 * is set. If the guest enables the MMU, we stop trapping the VM 591 * sys_regs and leave it in complete control of the caches. 592 */ 593 static bool access_vm_reg(struct kvm_vcpu *vcpu, 594 struct sys_reg_params *p, 595 const struct sys_reg_desc *r) 596 { 597 bool was_enabled = vcpu_has_cache_enabled(vcpu); 598 u64 val, mask, shift; 599 600 BUG_ON(!p->is_write); 601 602 get_access_mask(r, &mask, &shift); 603 604 if (~mask) { 605 val = vcpu_read_sys_reg(vcpu, r->reg); 606 val &= ~mask; 607 } else { 608 val = 0; 609 } 610 611 val |= (p->regval & (mask >> shift)) << shift; 612 vcpu_write_sys_reg(vcpu, val, r->reg); 613 614 kvm_toggle_cache(vcpu, was_enabled); 615 return true; 616 } 617 618 static bool access_actlr(struct kvm_vcpu *vcpu, 619 struct sys_reg_params *p, 620 const struct sys_reg_desc *r) 621 { 622 u64 mask, shift; 623 624 if (p->is_write) 625 return ignore_write(vcpu, p); 626 627 get_access_mask(r, &mask, &shift); 628 p->regval = (vcpu_read_sys_reg(vcpu, r->reg) & mask) >> shift; 629 630 return true; 631 } 632 633 /* 634 * Trap handler for the GICv3 SGI generation system register. 635 * Forward the request to the VGIC emulation. 636 * The cp15_64 code makes sure this automatically works 637 * for both AArch64 and AArch32 accesses. 638 */ 639 static bool access_gic_sgi(struct kvm_vcpu *vcpu, 640 struct sys_reg_params *p, 641 const struct sys_reg_desc *r) 642 { 643 bool g1; 644 645 if (!kvm_has_gicv3(vcpu->kvm)) 646 return undef_access(vcpu, p, r); 647 648 if (!p->is_write) 649 return read_from_write_only(vcpu, p, r); 650 651 /* 652 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates 653 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group, 654 * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively 655 * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure 656 * group. 657 */ 658 if (p->Op0 == 0) { /* AArch32 */ 659 switch (p->Op1) { 660 default: /* Keep GCC quiet */ 661 case 0: /* ICC_SGI1R */ 662 g1 = true; 663 break; 664 case 1: /* ICC_ASGI1R */ 665 case 2: /* ICC_SGI0R */ 666 g1 = false; 667 break; 668 } 669 } else { /* AArch64 */ 670 switch (p->Op2) { 671 default: /* Keep GCC quiet */ 672 case 5: /* ICC_SGI1R_EL1 */ 673 g1 = true; 674 break; 675 case 6: /* ICC_ASGI1R_EL1 */ 676 case 7: /* ICC_SGI0R_EL1 */ 677 g1 = false; 678 break; 679 } 680 } 681 682 vgic_v3_dispatch_sgi(vcpu, p->regval, g1); 683 684 return true; 685 } 686 687 static bool access_gic_sre(struct kvm_vcpu *vcpu, 688 struct sys_reg_params *p, 689 const struct sys_reg_desc *r) 690 { 691 if (!kvm_has_gicv3(vcpu->kvm)) 692 return undef_access(vcpu, p, r); 693 694 if (p->is_write) 695 return ignore_write(vcpu, p); 696 697 if (p->Op1 == 4) { /* ICC_SRE_EL2 */ 698 p->regval = KVM_ICC_SRE_EL2; 699 } else { /* ICC_SRE_EL1 */ 700 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre; 701 } 702 703 return true; 704 } 705 706 static bool access_gic_dir(struct kvm_vcpu *vcpu, 707 struct sys_reg_params *p, 708 const struct sys_reg_desc *r) 709 { 710 if (!kvm_has_gicv3(vcpu->kvm)) 711 return undef_access(vcpu, p, r); 712 713 if (!p->is_write) 714 return undef_access(vcpu, p, r); 715 716 vgic_v3_deactivate(vcpu, p->regval); 717 718 return true; 719 } 720 721 static bool access_gicv5_idr0(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 722 const struct sys_reg_desc *r) 723 { 724 if (p->is_write) 725 return undef_access(vcpu, p, r); 726 727 /* 728 * Expose KVM's priority- and ID-bits to the guest, but not GCIE_LEGACY. 729 * 730 * Note: for GICv5 the mimic the way that the num_pri_bits and 731 * num_id_bits fields are used with GICv3: 732 * - num_pri_bits stores the actual number of priority bits, whereas the 733 * register field stores num_pri_bits - 1. 734 * - num_id_bits stores the raw field value, which is 0b0000 for 16 bits 735 * and 0b0001 for 24 bits. 736 */ 737 p->regval = FIELD_PREP(ICC_IDR0_EL1_PRI_BITS, vcpu->arch.vgic_cpu.num_pri_bits - 1) | 738 FIELD_PREP(ICC_IDR0_EL1_ID_BITS, vcpu->arch.vgic_cpu.num_id_bits); 739 740 return true; 741 } 742 743 static bool access_gicv5_iaffid(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 744 const struct sys_reg_desc *r) 745 { 746 if (p->is_write) 747 return undef_access(vcpu, p, r); 748 749 /* 750 * For GICv5 VMs, the IAFFID value is the same as the VPE ID. The VPE ID 751 * is the same as the VCPU's ID. 752 */ 753 p->regval = FIELD_PREP(ICC_IAFFIDR_EL1_IAFFID, vcpu->vcpu_id); 754 755 return true; 756 } 757 758 static bool access_gicv5_ppi_enabler(struct kvm_vcpu *vcpu, 759 struct sys_reg_params *p, 760 const struct sys_reg_desc *r) 761 { 762 unsigned long *mask = vcpu->kvm->arch.vgic.gicv5_vm.vgic_ppi_mask; 763 struct vgic_v5_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v5; 764 unsigned long reg = p->regval; 765 int i; 766 767 /* We never expect to get here with a read! */ 768 if (WARN_ON_ONCE(!p->is_write)) 769 return undef_access(vcpu, p, r); 770 771 /* 772 * As we're only handling architected PPIs, the guest writes to the 773 * enable for the non-architected PPIs just return as there's 774 * nothing to do at all. We don't even allocate the storage for them. 775 */ 776 if (p->Op2 % 2) 777 return true; 778 779 /* 780 * Merge the raw guest write into out bitmap, anded with our PPI mask. 781 */ 782 bitmap_and(cpu_if->vgic_ppi_enabler, ®, mask, VGIC_V5_NR_PRIVATE_IRQS); 783 784 /* 785 * Sync the change in enable states to the vgic_irqs. We consider all 786 * PPIs as we don't expose many to the guest. 787 */ 788 for_each_visible_v5_ppi(i, vcpu->kvm) { 789 u32 intid = vgic_v5_make_ppi(i); 790 struct vgic_irq *irq; 791 792 irq = vgic_get_vcpu_irq(vcpu, intid); 793 794 scoped_guard(raw_spinlock_irqsave, &irq->irq_lock) 795 irq->enabled = test_bit(i, cpu_if->vgic_ppi_enabler); 796 797 vgic_put_irq(vcpu->kvm, irq); 798 } 799 800 return true; 801 } 802 803 static bool trap_raz_wi(struct kvm_vcpu *vcpu, 804 struct sys_reg_params *p, 805 const struct sys_reg_desc *r) 806 { 807 if (p->is_write) 808 return ignore_write(vcpu, p); 809 else 810 return read_zero(vcpu, p); 811 } 812 813 /* 814 * ARMv8.1 mandates at least a trivial LORegion implementation, where all the 815 * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0 816 * system, these registers should UNDEF. LORID_EL1 being a RO register, we 817 * treat it separately. 818 */ 819 static bool trap_loregion(struct kvm_vcpu *vcpu, 820 struct sys_reg_params *p, 821 const struct sys_reg_desc *r) 822 { 823 u32 sr = reg_to_encoding(r); 824 825 if (!kvm_has_feat(vcpu->kvm, ID_AA64MMFR1_EL1, LO, IMP)) 826 return undef_access(vcpu, p, r); 827 828 if (p->is_write && sr == SYS_LORID_EL1) 829 return write_to_read_only(vcpu, p, r); 830 831 return trap_raz_wi(vcpu, p, r); 832 } 833 834 static bool trap_oslar_el1(struct kvm_vcpu *vcpu, 835 struct sys_reg_params *p, 836 const struct sys_reg_desc *r) 837 { 838 if (!p->is_write) 839 return read_from_write_only(vcpu, p, r); 840 841 kvm_debug_handle_oslar(vcpu, p->regval); 842 return true; 843 } 844 845 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu, 846 struct sys_reg_params *p, 847 const struct sys_reg_desc *r) 848 { 849 if (p->is_write) 850 return write_to_read_only(vcpu, p, r); 851 852 p->regval = __vcpu_sys_reg(vcpu, r->reg); 853 return true; 854 } 855 856 static int set_oslsr_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 857 u64 val) 858 { 859 /* 860 * The only modifiable bit is the OSLK bit. Refuse the write if 861 * userspace attempts to change any other bit in the register. 862 */ 863 if ((val ^ rd->val) & ~OSLSR_EL1_OSLK) 864 return -EINVAL; 865 866 __vcpu_assign_sys_reg(vcpu, rd->reg, val); 867 return 0; 868 } 869 870 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu, 871 struct sys_reg_params *p, 872 const struct sys_reg_desc *r) 873 { 874 if (p->is_write) { 875 return ignore_write(vcpu, p); 876 } else { 877 p->regval = read_sysreg(dbgauthstatus_el1); 878 return true; 879 } 880 } 881 882 static bool trap_debug_regs(struct kvm_vcpu *vcpu, 883 struct sys_reg_params *p, 884 const struct sys_reg_desc *r) 885 { 886 access_rw(vcpu, p, r); 887 888 kvm_debug_set_guest_ownership(vcpu); 889 return true; 890 } 891 892 /* 893 * reg_to_dbg/dbg_to_reg 894 * 895 * A 32 bit write to a debug register leave top bits alone 896 * A 32 bit read from a debug register only returns the bottom bits 897 */ 898 static void reg_to_dbg(struct kvm_vcpu *vcpu, 899 struct sys_reg_params *p, 900 const struct sys_reg_desc *rd, 901 u64 *dbg_reg) 902 { 903 u64 mask, shift, val; 904 905 get_access_mask(rd, &mask, &shift); 906 907 val = *dbg_reg; 908 val &= ~mask; 909 val |= (p->regval & (mask >> shift)) << shift; 910 *dbg_reg = val; 911 } 912 913 static void dbg_to_reg(struct kvm_vcpu *vcpu, 914 struct sys_reg_params *p, 915 const struct sys_reg_desc *rd, 916 u64 *dbg_reg) 917 { 918 u64 mask, shift; 919 920 get_access_mask(rd, &mask, &shift); 921 p->regval = (*dbg_reg & mask) >> shift; 922 } 923 924 static u64 *demux_wb_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd) 925 { 926 struct kvm_guest_debug_arch *dbg = &vcpu->arch.vcpu_debug_state; 927 928 switch (rd->Op2) { 929 case 0b001: 930 case 0b100: 931 return &dbg->dbg_bvr[rd->CRm]; 932 case 0b101: 933 return &dbg->dbg_bcr[rd->CRm]; 934 case 0b110: 935 return &dbg->dbg_wvr[rd->CRm]; 936 case 0b111: 937 return &dbg->dbg_wcr[rd->CRm]; 938 default: 939 KVM_BUG_ON(1, vcpu->kvm); 940 return NULL; 941 } 942 } 943 944 static bool trap_dbg_wb_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 945 const struct sys_reg_desc *rd) 946 { 947 u64 *reg = demux_wb_reg(vcpu, rd); 948 949 if (!reg) 950 return false; 951 952 if (p->is_write) 953 reg_to_dbg(vcpu, p, rd, reg); 954 else 955 dbg_to_reg(vcpu, p, rd, reg); 956 957 kvm_debug_set_guest_ownership(vcpu); 958 return true; 959 } 960 961 static int set_dbg_wb_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 962 u64 val) 963 { 964 u64 *reg = demux_wb_reg(vcpu, rd); 965 966 if (!reg) 967 return -EINVAL; 968 969 *reg = val; 970 return 0; 971 } 972 973 static int get_dbg_wb_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 974 u64 *val) 975 { 976 u64 *reg = demux_wb_reg(vcpu, rd); 977 978 if (!reg) 979 return -EINVAL; 980 981 *val = *reg; 982 return 0; 983 } 984 985 static u64 reset_dbg_wb_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd) 986 { 987 u64 *reg = demux_wb_reg(vcpu, rd); 988 989 /* 990 * Bail early if we couldn't find storage for the register, the 991 * KVM_BUG_ON() in demux_wb_reg() will prevent this VM from ever 992 * being run. 993 */ 994 if (!reg) 995 return 0; 996 997 *reg = rd->val; 998 return rd->val; 999 } 1000 1001 static u64 reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 1002 { 1003 u64 amair = read_sysreg(amair_el1); 1004 vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1); 1005 return amair; 1006 } 1007 1008 static u64 reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 1009 { 1010 u64 actlr = read_sysreg(actlr_el1); 1011 vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1); 1012 return actlr; 1013 } 1014 1015 static u64 reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 1016 { 1017 u64 mpidr = kvm_calculate_mpidr(vcpu); 1018 1019 vcpu_write_sys_reg(vcpu, mpidr, MPIDR_EL1); 1020 return mpidr; 1021 } 1022 1023 static unsigned int hidden_visibility(const struct kvm_vcpu *vcpu, 1024 const struct sys_reg_desc *r) 1025 { 1026 return REG_HIDDEN; 1027 } 1028 1029 static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu, 1030 const struct sys_reg_desc *r) 1031 { 1032 if (kvm_vcpu_has_pmu(vcpu)) 1033 return 0; 1034 1035 return REG_HIDDEN; 1036 } 1037 1038 static u64 reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 1039 { 1040 u64 mask = BIT(ARMV8_PMU_CYCLE_IDX); 1041 u8 n = vcpu->kvm->arch.nr_pmu_counters; 1042 1043 if (n) 1044 mask |= GENMASK(n - 1, 0); 1045 1046 reset_unknown(vcpu, r); 1047 __vcpu_rmw_sys_reg(vcpu, r->reg, &=, mask); 1048 1049 return __vcpu_sys_reg(vcpu, r->reg); 1050 } 1051 1052 static u64 reset_pmevcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 1053 { 1054 reset_unknown(vcpu, r); 1055 __vcpu_rmw_sys_reg(vcpu, r->reg, &=, GENMASK(31, 0)); 1056 1057 return __vcpu_sys_reg(vcpu, r->reg); 1058 } 1059 1060 static u64 reset_pmevtyper(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 1061 { 1062 /* This thing will UNDEF, who cares about the reset value? */ 1063 if (!kvm_vcpu_has_pmu(vcpu)) 1064 return 0; 1065 1066 reset_unknown(vcpu, r); 1067 __vcpu_rmw_sys_reg(vcpu, r->reg, &=, kvm_pmu_evtyper_mask(vcpu->kvm)); 1068 1069 return __vcpu_sys_reg(vcpu, r->reg); 1070 } 1071 1072 static u64 reset_pmselr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 1073 { 1074 reset_unknown(vcpu, r); 1075 __vcpu_rmw_sys_reg(vcpu, r->reg, &=, PMSELR_EL0_SEL_MASK); 1076 1077 return __vcpu_sys_reg(vcpu, r->reg); 1078 } 1079 1080 static u64 reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 1081 { 1082 u64 pmcr = 0; 1083 1084 if (!kvm_supports_32bit_el0()) 1085 pmcr |= ARMV8_PMU_PMCR_LC; 1086 1087 /* 1088 * The value of PMCR.N field is included when the 1089 * vCPU register is read via kvm_vcpu_read_pmcr(). 1090 */ 1091 __vcpu_assign_sys_reg(vcpu, r->reg, pmcr); 1092 1093 return __vcpu_sys_reg(vcpu, r->reg); 1094 } 1095 1096 static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags) 1097 { 1098 u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0); 1099 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu); 1100 1101 if (!enabled) 1102 kvm_inject_undefined(vcpu); 1103 1104 return !enabled; 1105 } 1106 1107 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu) 1108 { 1109 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN); 1110 } 1111 1112 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu) 1113 { 1114 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN); 1115 } 1116 1117 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu) 1118 { 1119 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN); 1120 } 1121 1122 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu) 1123 { 1124 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN); 1125 } 1126 1127 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1128 const struct sys_reg_desc *r) 1129 { 1130 u64 val; 1131 1132 if (pmu_access_el0_disabled(vcpu)) 1133 return false; 1134 1135 if (p->is_write) { 1136 /* 1137 * Only update writeable bits of PMCR (continuing into 1138 * kvm_pmu_handle_pmcr() as well) 1139 */ 1140 val = kvm_vcpu_read_pmcr(vcpu); 1141 val &= ~ARMV8_PMU_PMCR_MASK; 1142 val |= p->regval & ARMV8_PMU_PMCR_MASK; 1143 if (!kvm_supports_32bit_el0()) 1144 val |= ARMV8_PMU_PMCR_LC; 1145 kvm_pmu_handle_pmcr(vcpu, val); 1146 } else { 1147 /* PMCR.P & PMCR.C are RAZ */ 1148 val = kvm_vcpu_read_pmcr(vcpu) 1149 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C); 1150 p->regval = val; 1151 } 1152 1153 return true; 1154 } 1155 1156 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1157 const struct sys_reg_desc *r) 1158 { 1159 if (pmu_access_event_counter_el0_disabled(vcpu)) 1160 return false; 1161 1162 if (p->is_write) 1163 __vcpu_assign_sys_reg(vcpu, PMSELR_EL0, p->regval); 1164 else 1165 /* return PMSELR.SEL field */ 1166 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0) 1167 & PMSELR_EL0_SEL_MASK; 1168 1169 return true; 1170 } 1171 1172 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1173 const struct sys_reg_desc *r) 1174 { 1175 u64 pmceid, mask, shift; 1176 1177 BUG_ON(p->is_write); 1178 1179 if (pmu_access_el0_disabled(vcpu)) 1180 return false; 1181 1182 get_access_mask(r, &mask, &shift); 1183 1184 pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1)); 1185 pmceid &= mask; 1186 pmceid >>= shift; 1187 1188 p->regval = pmceid; 1189 1190 return true; 1191 } 1192 1193 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx) 1194 { 1195 u64 pmcr, val; 1196 1197 pmcr = kvm_vcpu_read_pmcr(vcpu); 1198 val = FIELD_GET(ARMV8_PMU_PMCR_N, pmcr); 1199 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) { 1200 kvm_inject_undefined(vcpu); 1201 return false; 1202 } 1203 1204 return true; 1205 } 1206 1207 static int get_pmu_evcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 1208 u64 *val) 1209 { 1210 u64 idx; 1211 1212 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 0) 1213 /* PMCCNTR_EL0 */ 1214 idx = ARMV8_PMU_CYCLE_IDX; 1215 else 1216 /* PMEVCNTRn_EL0 */ 1217 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 1218 1219 *val = kvm_pmu_get_counter_value(vcpu, idx); 1220 return 0; 1221 } 1222 1223 static int set_pmu_evcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 1224 u64 val) 1225 { 1226 u64 idx; 1227 1228 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 0) 1229 /* PMCCNTR_EL0 */ 1230 idx = ARMV8_PMU_CYCLE_IDX; 1231 else 1232 /* PMEVCNTRn_EL0 */ 1233 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 1234 1235 kvm_pmu_set_counter_value_user(vcpu, idx, val); 1236 return 0; 1237 } 1238 1239 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu, 1240 struct sys_reg_params *p, 1241 const struct sys_reg_desc *r) 1242 { 1243 u64 idx = ~0UL; 1244 1245 if (r->CRn == 9 && r->CRm == 13) { 1246 if (r->Op2 == 2) { 1247 /* PMXEVCNTR_EL0 */ 1248 if (pmu_access_event_counter_el0_disabled(vcpu)) 1249 return false; 1250 1251 idx = SYS_FIELD_GET(PMSELR_EL0, SEL, 1252 __vcpu_sys_reg(vcpu, PMSELR_EL0)); 1253 } else if (r->Op2 == 0) { 1254 /* PMCCNTR_EL0 */ 1255 if (pmu_access_cycle_counter_el0_disabled(vcpu)) 1256 return false; 1257 1258 idx = ARMV8_PMU_CYCLE_IDX; 1259 } 1260 } else if (r->CRn == 0 && r->CRm == 9) { 1261 /* PMCCNTR */ 1262 if (pmu_access_event_counter_el0_disabled(vcpu)) 1263 return false; 1264 1265 idx = ARMV8_PMU_CYCLE_IDX; 1266 } else if (r->CRn == 14 && (r->CRm & 12) == 8) { 1267 /* PMEVCNTRn_EL0 */ 1268 if (pmu_access_event_counter_el0_disabled(vcpu)) 1269 return false; 1270 1271 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 1272 } 1273 1274 /* Catch any decoding mistake */ 1275 WARN_ON(idx == ~0UL); 1276 1277 if (!pmu_counter_idx_valid(vcpu, idx)) 1278 return false; 1279 1280 if (p->is_write) { 1281 if (pmu_access_el0_disabled(vcpu)) 1282 return false; 1283 1284 kvm_pmu_set_counter_value(vcpu, idx, p->regval); 1285 } else { 1286 p->regval = kvm_pmu_get_counter_value(vcpu, idx); 1287 } 1288 1289 return true; 1290 } 1291 1292 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1293 const struct sys_reg_desc *r) 1294 { 1295 u64 idx, reg; 1296 1297 if (pmu_access_el0_disabled(vcpu)) 1298 return false; 1299 1300 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) { 1301 /* PMXEVTYPER_EL0 */ 1302 idx = SYS_FIELD_GET(PMSELR_EL0, SEL, __vcpu_sys_reg(vcpu, PMSELR_EL0)); 1303 reg = PMEVTYPER0_EL0 + idx; 1304 } else if (r->CRn == 14 && (r->CRm & 12) == 12) { 1305 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 1306 if (idx == ARMV8_PMU_CYCLE_IDX) 1307 reg = PMCCFILTR_EL0; 1308 else 1309 /* PMEVTYPERn_EL0 */ 1310 reg = PMEVTYPER0_EL0 + idx; 1311 } else { 1312 BUG(); 1313 } 1314 1315 if (!pmu_counter_idx_valid(vcpu, idx)) 1316 return false; 1317 1318 if (p->is_write) { 1319 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx); 1320 kvm_vcpu_pmu_restore_guest(vcpu); 1321 } else { 1322 p->regval = __vcpu_sys_reg(vcpu, reg); 1323 } 1324 1325 return true; 1326 } 1327 1328 static int set_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 val) 1329 { 1330 u64 mask = kvm_pmu_accessible_counter_mask(vcpu); 1331 1332 __vcpu_assign_sys_reg(vcpu, r->reg, val & mask); 1333 kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu); 1334 1335 return 0; 1336 } 1337 1338 static int get_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 *val) 1339 { 1340 u64 mask = kvm_pmu_accessible_counter_mask(vcpu); 1341 1342 *val = __vcpu_sys_reg(vcpu, r->reg) & mask; 1343 return 0; 1344 } 1345 1346 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1347 const struct sys_reg_desc *r) 1348 { 1349 u64 val, mask; 1350 1351 if (pmu_access_el0_disabled(vcpu)) 1352 return false; 1353 1354 mask = kvm_pmu_accessible_counter_mask(vcpu); 1355 if (p->is_write) { 1356 val = p->regval & mask; 1357 if (r->Op2 & 0x1) 1358 /* accessing PMCNTENSET_EL0 */ 1359 __vcpu_rmw_sys_reg(vcpu, PMCNTENSET_EL0, |=, val); 1360 else 1361 /* accessing PMCNTENCLR_EL0 */ 1362 __vcpu_rmw_sys_reg(vcpu, PMCNTENSET_EL0, &=, ~val); 1363 1364 kvm_pmu_reprogram_counter_mask(vcpu, val); 1365 } else { 1366 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0); 1367 } 1368 1369 return true; 1370 } 1371 1372 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1373 const struct sys_reg_desc *r) 1374 { 1375 u64 mask = kvm_pmu_accessible_counter_mask(vcpu); 1376 1377 if (check_pmu_access_disabled(vcpu, 0)) 1378 return false; 1379 1380 if (p->is_write) { 1381 u64 val = p->regval & mask; 1382 1383 if (r->Op2 & 0x1) 1384 /* accessing PMINTENSET_EL1 */ 1385 __vcpu_rmw_sys_reg(vcpu, PMINTENSET_EL1, |=, val); 1386 else 1387 /* accessing PMINTENCLR_EL1 */ 1388 __vcpu_rmw_sys_reg(vcpu, PMINTENSET_EL1, &=, ~val); 1389 } else { 1390 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1); 1391 } 1392 1393 return true; 1394 } 1395 1396 static bool access_pmmir(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1397 const struct sys_reg_desc *r) 1398 { 1399 if (p->is_write) 1400 return write_to_read_only(vcpu, p, r); 1401 1402 /* 1403 * If KVM_ARM_VCPU_PMU_V3_STRICT is set and PMU was explicitly 1404 * selected, the underlying hardware SLOTS value was read into this 1405 * field. Otherwise, it stays 0. All other PMMIR_EL1 fields are RAZ. 1406 */ 1407 p->regval = FIELD_PREP(ARMV8_PMU_SLOTS, vcpu->kvm->arch.pmmir_slots); 1408 return true; 1409 } 1410 1411 static int get_pmmir(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 1412 u64 *val) 1413 { 1414 *val = FIELD_PREP(ARMV8_PMU_SLOTS, vcpu->kvm->arch.pmmir_slots); 1415 return 0; 1416 } 1417 1418 static int set_pmmir(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 1419 u64 val) 1420 { 1421 struct kvm *kvm = vcpu->kvm; 1422 u8 slots = FIELD_GET(ARMV8_PMU_SLOTS, val); 1423 1424 /* 1425 * Only the SLOTS field is exposed (get_pmmir returns just that field), 1426 * so reject a write that sets any other bit rather than silently 1427 * masking it. 1428 */ 1429 if (val & ~(u64)ARMV8_PMU_SLOTS) 1430 return -EINVAL; 1431 1432 guard(mutex)(&kvm->arch.config_lock); 1433 1434 /* 1435 * Once the VM has started PMMIR_EL1 is immutable. Reject any write 1436 * that does not match the current value. 1437 */ 1438 if (kvm_vm_has_ran_once(kvm)) 1439 return slots == kvm->arch.pmmir_slots ? 0 : -EBUSY; 1440 1441 /* 1442 * Only SLOTS = 0 is honored for backwards compatibility with the 1443 * old RAZ behavior. Reject any non-zero write that does not match 1444 * the current value. 1445 */ 1446 if (!slots) 1447 kvm->arch.pmmir_slots = 0; 1448 else if (slots != kvm->arch.pmmir_slots) 1449 return -EINVAL; 1450 1451 return 0; 1452 } 1453 1454 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1455 const struct sys_reg_desc *r) 1456 { 1457 u64 mask = kvm_pmu_accessible_counter_mask(vcpu); 1458 1459 if (pmu_access_el0_disabled(vcpu)) 1460 return false; 1461 1462 if (p->is_write) { 1463 if (r->CRm & 0x2) 1464 /* accessing PMOVSSET_EL0 */ 1465 __vcpu_rmw_sys_reg(vcpu, PMOVSSET_EL0, |=, (p->regval & mask)); 1466 else 1467 /* accessing PMOVSCLR_EL0 */ 1468 __vcpu_rmw_sys_reg(vcpu, PMOVSSET_EL0, &=, ~(p->regval & mask)); 1469 } else { 1470 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0); 1471 } 1472 1473 return true; 1474 } 1475 1476 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1477 const struct sys_reg_desc *r) 1478 { 1479 u64 mask; 1480 1481 if (!p->is_write) 1482 return read_from_write_only(vcpu, p, r); 1483 1484 if (pmu_write_swinc_el0_disabled(vcpu)) 1485 return false; 1486 1487 mask = kvm_pmu_accessible_counter_mask(vcpu); 1488 kvm_pmu_software_increment(vcpu, p->regval & mask); 1489 return true; 1490 } 1491 1492 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1493 const struct sys_reg_desc *r) 1494 { 1495 if (p->is_write) { 1496 if (!vcpu_mode_priv(vcpu)) 1497 return undef_access(vcpu, p, r); 1498 1499 __vcpu_assign_sys_reg(vcpu, PMUSERENR_EL0, 1500 (p->regval & ARMV8_PMU_USERENR_MASK)); 1501 } else { 1502 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0) 1503 & ARMV8_PMU_USERENR_MASK; 1504 } 1505 1506 return true; 1507 } 1508 1509 static int get_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 1510 u64 *val) 1511 { 1512 *val = kvm_vcpu_read_pmcr(vcpu); 1513 return 0; 1514 } 1515 1516 static int set_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 1517 u64 val) 1518 { 1519 u8 new_n = FIELD_GET(ARMV8_PMU_PMCR_N, val); 1520 struct kvm *kvm = vcpu->kvm; 1521 1522 mutex_lock(&kvm->arch.config_lock); 1523 1524 /* 1525 * The vCPU can't have more counters than the PMU hardware 1526 * implements. Ignore this error to maintain compatibility 1527 * with the existing KVM behavior. 1528 */ 1529 if (!kvm_vm_has_ran_once(kvm) && 1530 !vcpu_has_nv(vcpu) && 1531 !kvm_vcpu_has_pmuv3_strict(vcpu) && 1532 new_n <= kvm_arm_pmu_get_max_counters(kvm)) 1533 kvm->arch.nr_pmu_counters = new_n; 1534 1535 mutex_unlock(&kvm->arch.config_lock); 1536 1537 /* 1538 * Ignore writes to RES0 bits, read only bits that are cleared on 1539 * vCPU reset, and writable bits that KVM doesn't support yet. 1540 * (i.e. only PMCR.N and bits [7:0] are mutable from userspace) 1541 * The LP bit is RES0 when FEAT_PMUv3p5 is not supported on the vCPU. 1542 * But, we leave the bit as it is here, as the vCPU's PMUver might 1543 * be changed later (NOTE: the bit will be cleared on first vCPU run 1544 * if necessary). 1545 */ 1546 val &= ARMV8_PMU_PMCR_MASK; 1547 1548 /* The LC bit is RES1 when AArch32 is not supported */ 1549 if (!kvm_supports_32bit_el0()) 1550 val |= ARMV8_PMU_PMCR_LC; 1551 1552 __vcpu_assign_sys_reg(vcpu, r->reg, val); 1553 kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu); 1554 1555 return 0; 1556 } 1557 1558 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */ 1559 #define DBG_BCR_BVR_WCR_WVR_EL1(n) \ 1560 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \ 1561 trap_dbg_wb_reg, reset_dbg_wb_reg, 0, 0, \ 1562 get_dbg_wb_reg, set_dbg_wb_reg }, \ 1563 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \ 1564 trap_dbg_wb_reg, reset_dbg_wb_reg, 0, 0, \ 1565 get_dbg_wb_reg, set_dbg_wb_reg }, \ 1566 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \ 1567 trap_dbg_wb_reg, reset_dbg_wb_reg, 0, 0, \ 1568 get_dbg_wb_reg, set_dbg_wb_reg }, \ 1569 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \ 1570 trap_dbg_wb_reg, reset_dbg_wb_reg, 0, 0, \ 1571 get_dbg_wb_reg, set_dbg_wb_reg } 1572 1573 #define PMU_SYS_REG(name) \ 1574 SYS_DESC(SYS_##name), .reset = reset_pmu_reg, \ 1575 .visibility = pmu_visibility 1576 1577 /* Macro to expand the PMEVCNTRn_EL0 register */ 1578 #define PMU_PMEVCNTR_EL0(n) \ 1579 { PMU_SYS_REG(PMEVCNTRn_EL0(n)), \ 1580 .reset = reset_pmevcntr, .get_user = get_pmu_evcntr, \ 1581 .set_user = set_pmu_evcntr, \ 1582 .access = access_pmu_evcntr, .reg = (PMEVCNTR0_EL0 + n), } 1583 1584 /* Macro to expand the PMEVTYPERn_EL0 register */ 1585 #define PMU_PMEVTYPER_EL0(n) \ 1586 { PMU_SYS_REG(PMEVTYPERn_EL0(n)), \ 1587 .reset = reset_pmevtyper, \ 1588 .access = access_pmu_evtyper, .reg = (PMEVTYPER0_EL0 + n), } 1589 1590 /* Macro to expand the AMU counter and type registers*/ 1591 #define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), undef_access } 1592 #define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), undef_access } 1593 #define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), undef_access } 1594 #define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), undef_access } 1595 1596 static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu, 1597 const struct sys_reg_desc *rd) 1598 { 1599 return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN; 1600 } 1601 1602 /* 1603 * If we land here on a PtrAuth access, that is because we didn't 1604 * fixup the access on exit by allowing the PtrAuth sysregs. The only 1605 * way this happens is when the guest does not have PtrAuth support 1606 * enabled. 1607 */ 1608 #define __PTRAUTH_KEY(k) \ 1609 { SYS_DESC(SYS_## k), undef_access, reset_unknown, k, \ 1610 .visibility = ptrauth_visibility} 1611 1612 #define PTRAUTH_KEY(k) \ 1613 __PTRAUTH_KEY(k ## KEYLO_EL1), \ 1614 __PTRAUTH_KEY(k ## KEYHI_EL1) 1615 1616 static bool access_arch_timer(struct kvm_vcpu *vcpu, 1617 struct sys_reg_params *p, 1618 const struct sys_reg_desc *r) 1619 { 1620 enum kvm_arch_timers tmr; 1621 enum kvm_arch_timer_regs treg; 1622 u64 reg = reg_to_encoding(r); 1623 1624 switch (reg) { 1625 case SYS_CNTP_TVAL_EL0: 1626 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) 1627 tmr = TIMER_HPTIMER; 1628 else 1629 tmr = TIMER_PTIMER; 1630 treg = TIMER_REG_TVAL; 1631 break; 1632 1633 case SYS_CNTV_TVAL_EL0: 1634 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) 1635 tmr = TIMER_HVTIMER; 1636 else 1637 tmr = TIMER_VTIMER; 1638 treg = TIMER_REG_TVAL; 1639 break; 1640 1641 case SYS_AARCH32_CNTP_TVAL: 1642 case SYS_CNTP_TVAL_EL02: 1643 tmr = TIMER_PTIMER; 1644 treg = TIMER_REG_TVAL; 1645 break; 1646 1647 case SYS_CNTV_TVAL_EL02: 1648 tmr = TIMER_VTIMER; 1649 treg = TIMER_REG_TVAL; 1650 break; 1651 1652 case SYS_CNTHP_TVAL_EL2: 1653 tmr = TIMER_HPTIMER; 1654 treg = TIMER_REG_TVAL; 1655 break; 1656 1657 case SYS_CNTHV_TVAL_EL2: 1658 tmr = TIMER_HVTIMER; 1659 treg = TIMER_REG_TVAL; 1660 break; 1661 1662 case SYS_CNTP_CTL_EL0: 1663 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) 1664 tmr = TIMER_HPTIMER; 1665 else 1666 tmr = TIMER_PTIMER; 1667 treg = TIMER_REG_CTL; 1668 break; 1669 1670 case SYS_CNTV_CTL_EL0: 1671 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) 1672 tmr = TIMER_HVTIMER; 1673 else 1674 tmr = TIMER_VTIMER; 1675 treg = TIMER_REG_CTL; 1676 break; 1677 1678 case SYS_AARCH32_CNTP_CTL: 1679 case SYS_CNTP_CTL_EL02: 1680 tmr = TIMER_PTIMER; 1681 treg = TIMER_REG_CTL; 1682 break; 1683 1684 case SYS_CNTV_CTL_EL02: 1685 tmr = TIMER_VTIMER; 1686 treg = TIMER_REG_CTL; 1687 break; 1688 1689 case SYS_CNTHP_CTL_EL2: 1690 tmr = TIMER_HPTIMER; 1691 treg = TIMER_REG_CTL; 1692 break; 1693 1694 case SYS_CNTHV_CTL_EL2: 1695 tmr = TIMER_HVTIMER; 1696 treg = TIMER_REG_CTL; 1697 break; 1698 1699 case SYS_CNTP_CVAL_EL0: 1700 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) 1701 tmr = TIMER_HPTIMER; 1702 else 1703 tmr = TIMER_PTIMER; 1704 treg = TIMER_REG_CVAL; 1705 break; 1706 1707 case SYS_CNTV_CVAL_EL0: 1708 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) 1709 tmr = TIMER_HVTIMER; 1710 else 1711 tmr = TIMER_VTIMER; 1712 treg = TIMER_REG_CVAL; 1713 break; 1714 1715 case SYS_AARCH32_CNTP_CVAL: 1716 case SYS_CNTP_CVAL_EL02: 1717 tmr = TIMER_PTIMER; 1718 treg = TIMER_REG_CVAL; 1719 break; 1720 1721 case SYS_CNTV_CVAL_EL02: 1722 tmr = TIMER_VTIMER; 1723 treg = TIMER_REG_CVAL; 1724 break; 1725 1726 case SYS_CNTHP_CVAL_EL2: 1727 tmr = TIMER_HPTIMER; 1728 treg = TIMER_REG_CVAL; 1729 break; 1730 1731 case SYS_CNTHV_CVAL_EL2: 1732 tmr = TIMER_HVTIMER; 1733 treg = TIMER_REG_CVAL; 1734 break; 1735 1736 case SYS_CNTPCT_EL0: 1737 case SYS_CNTPCTSS_EL0: 1738 if (is_hyp_ctxt(vcpu)) 1739 tmr = TIMER_HPTIMER; 1740 else 1741 tmr = TIMER_PTIMER; 1742 treg = TIMER_REG_CNT; 1743 break; 1744 1745 case SYS_AARCH32_CNTPCT: 1746 case SYS_AARCH32_CNTPCTSS: 1747 tmr = TIMER_PTIMER; 1748 treg = TIMER_REG_CNT; 1749 break; 1750 1751 case SYS_CNTVCT_EL0: 1752 case SYS_CNTVCTSS_EL0: 1753 if (is_hyp_ctxt(vcpu)) 1754 tmr = TIMER_HVTIMER; 1755 else 1756 tmr = TIMER_VTIMER; 1757 treg = TIMER_REG_CNT; 1758 break; 1759 1760 case SYS_AARCH32_CNTVCT: 1761 case SYS_AARCH32_CNTVCTSS: 1762 tmr = TIMER_VTIMER; 1763 treg = TIMER_REG_CNT; 1764 break; 1765 1766 default: 1767 print_sys_reg_msg(p, "%s", "Unhandled trapped timer register"); 1768 return undef_access(vcpu, p, r); 1769 } 1770 1771 if (p->is_write) 1772 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval); 1773 else 1774 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg); 1775 1776 return true; 1777 } 1778 1779 static int arch_timer_set_user(struct kvm_vcpu *vcpu, 1780 const struct sys_reg_desc *rd, 1781 u64 val) 1782 { 1783 switch (reg_to_encoding(rd)) { 1784 case SYS_CNTV_CTL_EL0: 1785 case SYS_CNTP_CTL_EL0: 1786 case SYS_CNTHV_CTL_EL2: 1787 case SYS_CNTHP_CTL_EL2: 1788 val &= ~ARCH_TIMER_CTRL_IT_STAT; 1789 break; 1790 case SYS_CNTVCT_EL0: 1791 if (!test_bit(KVM_ARCH_FLAG_VM_COUNTER_OFFSET, &vcpu->kvm->arch.flags)) 1792 timer_set_offset(vcpu_vtimer(vcpu), kvm_phys_timer_read() - val); 1793 return 0; 1794 case SYS_CNTPCT_EL0: 1795 if (!test_bit(KVM_ARCH_FLAG_VM_COUNTER_OFFSET, &vcpu->kvm->arch.flags)) 1796 timer_set_offset(vcpu_ptimer(vcpu), kvm_phys_timer_read() - val); 1797 return 0; 1798 } 1799 1800 __vcpu_assign_sys_reg(vcpu, rd->reg, val); 1801 return 0; 1802 } 1803 1804 static int arch_timer_get_user(struct kvm_vcpu *vcpu, 1805 const struct sys_reg_desc *rd, 1806 u64 *val) 1807 { 1808 switch (reg_to_encoding(rd)) { 1809 case SYS_CNTVCT_EL0: 1810 *val = kvm_phys_timer_read() - timer_get_offset(vcpu_vtimer(vcpu)); 1811 break; 1812 case SYS_CNTPCT_EL0: 1813 *val = kvm_phys_timer_read() - timer_get_offset(vcpu_ptimer(vcpu)); 1814 break; 1815 default: 1816 *val = __vcpu_sys_reg(vcpu, rd->reg); 1817 } 1818 1819 return 0; 1820 } 1821 1822 static s64 kvm_arm64_ftr_safe_value(u32 id, const struct arm64_ftr_bits *ftrp, 1823 s64 new, s64 cur) 1824 { 1825 struct arm64_ftr_bits kvm_ftr = *ftrp; 1826 1827 /* Some features have different safe value type in KVM than host features */ 1828 switch (id) { 1829 case SYS_ID_AA64DFR0_EL1: 1830 switch (kvm_ftr.shift) { 1831 case ID_AA64DFR0_EL1_PMUVer_SHIFT: 1832 kvm_ftr.type = FTR_LOWER_SAFE; 1833 break; 1834 case ID_AA64DFR0_EL1_DebugVer_SHIFT: 1835 kvm_ftr.type = FTR_LOWER_SAFE; 1836 break; 1837 } 1838 break; 1839 case SYS_ID_DFR0_EL1: 1840 if (kvm_ftr.shift == ID_DFR0_EL1_PerfMon_SHIFT) 1841 kvm_ftr.type = FTR_LOWER_SAFE; 1842 break; 1843 } 1844 1845 return arm64_ftr_safe_value(&kvm_ftr, new, cur); 1846 } 1847 1848 /* 1849 * arm64_check_features() - Check if a feature register value constitutes 1850 * a subset of features indicated by the idreg's KVM sanitised limit. 1851 * 1852 * This function will check if each feature field of @val is the "safe" value 1853 * against idreg's KVM sanitised limit return from reset() callback. 1854 * If a field value in @val is the same as the one in limit, it is always 1855 * considered the safe value regardless For register fields that are not in 1856 * writable, only the value in limit is considered the safe value. 1857 * 1858 * Return: 0 if all the fields are safe. Otherwise, return negative errno. 1859 */ 1860 static int arm64_check_features(struct kvm_vcpu *vcpu, 1861 const struct sys_reg_desc *rd, 1862 u64 val) 1863 { 1864 const struct arm64_ftr_reg *ftr_reg; 1865 const struct arm64_ftr_bits *ftrp = NULL; 1866 u32 id = reg_to_encoding(rd); 1867 u64 writable_mask = rd->val; 1868 u64 limit = rd->reset(vcpu, rd); 1869 u64 mask = 0; 1870 1871 /* 1872 * Hidden and unallocated ID registers may not have a corresponding 1873 * struct arm64_ftr_reg. Of course, if the register is RAZ we know the 1874 * only safe value is 0. 1875 */ 1876 if (sysreg_visible_as_raz(vcpu, rd)) 1877 return val ? -E2BIG : 0; 1878 1879 ftr_reg = get_arm64_ftr_reg(id); 1880 if (!ftr_reg) 1881 return -EINVAL; 1882 1883 ftrp = ftr_reg->ftr_bits; 1884 1885 for (; ftrp && ftrp->width; ftrp++) { 1886 s64 f_val, f_lim, safe_val; 1887 u64 ftr_mask; 1888 1889 ftr_mask = arm64_ftr_mask(ftrp); 1890 if ((ftr_mask & writable_mask) != ftr_mask) 1891 continue; 1892 1893 f_val = arm64_ftr_value(ftrp, val); 1894 f_lim = arm64_ftr_value(ftrp, limit); 1895 mask |= ftr_mask; 1896 1897 if (f_val == f_lim) 1898 safe_val = f_val; 1899 else 1900 safe_val = kvm_arm64_ftr_safe_value(id, ftrp, f_val, f_lim); 1901 1902 if (safe_val != f_val) 1903 return -E2BIG; 1904 } 1905 1906 /* For fields that are not writable, values in limit are the safe values. */ 1907 if ((val & ~mask) != (limit & ~mask)) 1908 return -E2BIG; 1909 1910 return 0; 1911 } 1912 1913 static u8 pmuver_to_perfmon(u8 pmuver) 1914 { 1915 switch (pmuver) { 1916 case ID_AA64DFR0_EL1_PMUVer_IMP: 1917 return ID_DFR0_EL1_PerfMon_PMUv3; 1918 case ID_AA64DFR0_EL1_PMUVer_IMP_DEF: 1919 return ID_DFR0_EL1_PerfMon_IMPDEF; 1920 default: 1921 /* Anything ARMv8.1+ and NI have the same value. For now. */ 1922 return pmuver; 1923 } 1924 } 1925 1926 static u64 sanitise_id_aa64pfr0_el1(const struct kvm_vcpu *vcpu, u64 val); 1927 static u64 sanitise_id_aa64pfr1_el1(const struct kvm_vcpu *vcpu, u64 val); 1928 static u64 sanitise_id_aa64pfr2_el1(const struct kvm_vcpu *vcpu, u64 val); 1929 static u64 sanitise_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, u64 val); 1930 1931 /* Read a sanitised cpufeature ID register by sys_reg_desc */ 1932 static u64 __kvm_read_sanitised_id_reg(const struct kvm_vcpu *vcpu, 1933 const struct sys_reg_desc *r) 1934 { 1935 u32 id = reg_to_encoding(r); 1936 u64 val; 1937 1938 if (sysreg_visible_as_raz(vcpu, r)) 1939 return 0; 1940 1941 val = read_sanitised_ftr_reg(id); 1942 1943 switch (id) { 1944 case SYS_ID_AA64DFR0_EL1: 1945 val = sanitise_id_aa64dfr0_el1(vcpu, val); 1946 break; 1947 case SYS_ID_AA64PFR0_EL1: 1948 val = sanitise_id_aa64pfr0_el1(vcpu, val); 1949 break; 1950 case SYS_ID_AA64PFR1_EL1: 1951 val = sanitise_id_aa64pfr1_el1(vcpu, val); 1952 break; 1953 case SYS_ID_AA64PFR2_EL1: 1954 val = sanitise_id_aa64pfr2_el1(vcpu, val); 1955 break; 1956 case SYS_ID_AA64ISAR1_EL1: 1957 if (!vcpu_has_ptrauth(vcpu)) 1958 val &= ~(ID_AA64ISAR1_EL1_APA | 1959 ID_AA64ISAR1_EL1_API | 1960 ID_AA64ISAR1_EL1_GPA | 1961 ID_AA64ISAR1_EL1_GPI); 1962 break; 1963 case SYS_ID_AA64ISAR2_EL1: 1964 if (!vcpu_has_ptrauth(vcpu)) 1965 val &= ~(ID_AA64ISAR2_EL1_APA3 | 1966 ID_AA64ISAR2_EL1_GPA3); 1967 if (!cpus_have_final_cap(ARM64_HAS_WFXT) || 1968 has_broken_cntvoff()) 1969 val &= ~ID_AA64ISAR2_EL1_WFxT; 1970 break; 1971 case SYS_ID_AA64ISAR3_EL1: 1972 val &= ID_AA64ISAR3_EL1_FPRCVT | ID_AA64ISAR3_EL1_LSFE | 1973 ID_AA64ISAR3_EL1_FAMINMAX | ID_AA64ISAR3_EL1_LSUI; 1974 break; 1975 case SYS_ID_AA64MMFR2_EL1: 1976 val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK; 1977 val &= ~ID_AA64MMFR2_EL1_NV; 1978 break; 1979 case SYS_ID_AA64MMFR3_EL1: 1980 val &= ID_AA64MMFR3_EL1_TCRX | 1981 ID_AA64MMFR3_EL1_SCTLRX | 1982 ID_AA64MMFR3_EL1_S1POE | 1983 ID_AA64MMFR3_EL1_S1PIE; 1984 1985 if (!system_supports_poe()) 1986 val &= ~ID_AA64MMFR3_EL1_S1POE; 1987 break; 1988 case SYS_ID_MMFR4_EL1: 1989 val &= ~ID_MMFR4_EL1_CCIDX; 1990 break; 1991 } 1992 1993 if (vcpu_has_nv(vcpu)) 1994 val = limit_nv_id_reg(vcpu->kvm, id, val); 1995 1996 return val; 1997 } 1998 1999 static u64 kvm_read_sanitised_id_reg(struct kvm_vcpu *vcpu, 2000 const struct sys_reg_desc *r) 2001 { 2002 return __kvm_read_sanitised_id_reg(vcpu, r); 2003 } 2004 2005 static u64 read_id_reg(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 2006 { 2007 return kvm_read_vm_id_reg(vcpu->kvm, reg_to_encoding(r)); 2008 } 2009 2010 static bool is_feature_id_reg(u32 encoding) 2011 { 2012 return (sys_reg_Op0(encoding) == 3 && 2013 (sys_reg_Op1(encoding) < 2 || sys_reg_Op1(encoding) == 3) && 2014 sys_reg_CRn(encoding) == 0 && 2015 sys_reg_CRm(encoding) <= 7); 2016 } 2017 2018 /* 2019 * Return true if the register's (Op0, Op1, CRn, CRm, Op2) is 2020 * (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8, which is the range of ID 2021 * registers KVM maintains on a per-VM basis. 2022 * 2023 * Additionally, the implementation ID registers and CTR_EL0 are handled as 2024 * per-VM registers. 2025 */ 2026 static inline bool is_vm_ftr_id_reg(u32 id) 2027 { 2028 switch (id) { 2029 case SYS_CTR_EL0: 2030 case SYS_MIDR_EL1: 2031 case SYS_REVIDR_EL1: 2032 case SYS_AIDR_EL1: 2033 return true; 2034 default: 2035 return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 && 2036 sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 && 2037 sys_reg_CRm(id) < 8); 2038 2039 } 2040 } 2041 2042 static inline bool is_vcpu_ftr_id_reg(u32 id) 2043 { 2044 return is_feature_id_reg(id) && !is_vm_ftr_id_reg(id); 2045 } 2046 2047 static inline bool is_aa32_id_reg(u32 id) 2048 { 2049 return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 && 2050 sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 && 2051 sys_reg_CRm(id) <= 3); 2052 } 2053 2054 static unsigned int id_visibility(const struct kvm_vcpu *vcpu, 2055 const struct sys_reg_desc *r) 2056 { 2057 u32 id = reg_to_encoding(r); 2058 2059 switch (id) { 2060 case SYS_ID_AA64ZFR0_EL1: 2061 if (!vcpu_has_sve(vcpu)) 2062 return REG_RAZ; 2063 break; 2064 } 2065 2066 return 0; 2067 } 2068 2069 static unsigned int aa32_id_visibility(const struct kvm_vcpu *vcpu, 2070 const struct sys_reg_desc *r) 2071 { 2072 /* 2073 * AArch32 ID registers are UNKNOWN if AArch32 isn't implemented at any 2074 * EL. Promote to RAZ/WI in order to guarantee consistency between 2075 * systems. 2076 */ 2077 if (!kvm_supports_32bit_el0()) 2078 return REG_RAZ | REG_USER_WI; 2079 2080 return id_visibility(vcpu, r); 2081 } 2082 2083 static unsigned int raz_visibility(const struct kvm_vcpu *vcpu, 2084 const struct sys_reg_desc *r) 2085 { 2086 return REG_RAZ; 2087 } 2088 2089 /* cpufeature ID register access trap handlers */ 2090 2091 static bool access_id_reg(struct kvm_vcpu *vcpu, 2092 struct sys_reg_params *p, 2093 const struct sys_reg_desc *r) 2094 { 2095 if (p->is_write) 2096 return write_to_read_only(vcpu, p, r); 2097 2098 p->regval = read_id_reg(vcpu, r); 2099 2100 return true; 2101 } 2102 2103 /* Visibility overrides for SVE-specific control registers */ 2104 static unsigned int sve_visibility(const struct kvm_vcpu *vcpu, 2105 const struct sys_reg_desc *rd) 2106 { 2107 if (vcpu_has_sve(vcpu)) 2108 return 0; 2109 2110 return REG_HIDDEN; 2111 } 2112 2113 static unsigned int sme_visibility(const struct kvm_vcpu *vcpu, 2114 const struct sys_reg_desc *rd) 2115 { 2116 if (kvm_has_feat(vcpu->kvm, ID_AA64PFR1_EL1, SME, IMP)) 2117 return 0; 2118 2119 return REG_HIDDEN; 2120 } 2121 2122 static unsigned int fp8_visibility(const struct kvm_vcpu *vcpu, 2123 const struct sys_reg_desc *rd) 2124 { 2125 if (kvm_has_fpmr(vcpu->kvm)) 2126 return 0; 2127 2128 return REG_HIDDEN; 2129 } 2130 2131 static u64 sanitise_id_aa64pfr0_el1(const struct kvm_vcpu *vcpu, u64 val) 2132 { 2133 if (!vcpu_has_sve(vcpu)) 2134 val &= ~ID_AA64PFR0_EL1_SVE_MASK; 2135 2136 /* 2137 * The default is to expose CSV2 == 1 if the HW isn't affected. 2138 * Although this is a per-CPU feature, we make it global because 2139 * asymmetric systems are just a nuisance. 2140 * 2141 * Userspace can override this as long as it doesn't promise 2142 * the impossible. 2143 */ 2144 if (arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED) { 2145 val &= ~ID_AA64PFR0_EL1_CSV2_MASK; 2146 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV2, IMP); 2147 } 2148 if (arm64_get_meltdown_state() == SPECTRE_UNAFFECTED) { 2149 val &= ~ID_AA64PFR0_EL1_CSV3_MASK; 2150 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV3, IMP); 2151 } 2152 2153 if (vgic_host_has_gicv3()) { 2154 val &= ~ID_AA64PFR0_EL1_GIC_MASK; 2155 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, GIC, IMP); 2156 } 2157 2158 val &= ~ID_AA64PFR0_EL1_AMU_MASK; 2159 2160 /* 2161 * MPAM is disabled by default as KVM also needs a set of PARTID to 2162 * program the MPAMVPMx_EL2 PARTID remapping registers with. But some 2163 * older kernels let the guest see the ID bit. 2164 */ 2165 val &= ~ID_AA64PFR0_EL1_MPAM_MASK; 2166 2167 return val; 2168 } 2169 2170 static u64 sanitise_id_aa64pfr1_el1(const struct kvm_vcpu *vcpu, u64 val) 2171 { 2172 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 2173 2174 if (!kvm_has_mte(vcpu->kvm)) { 2175 val &= ~ID_AA64PFR1_EL1_MTE; 2176 val &= ~ID_AA64PFR1_EL1_MTE_frac; 2177 } 2178 2179 if (!(cpus_have_final_cap(ARM64_HAS_RASV1P1_EXTN) && 2180 SYS_FIELD_GET(ID_AA64PFR0_EL1, RAS, pfr0) == ID_AA64PFR0_EL1_RAS_IMP)) 2181 val &= ~ID_AA64PFR1_EL1_RAS_frac; 2182 2183 val &= ~ID_AA64PFR1_EL1_SME; 2184 val &= ~ID_AA64PFR1_EL1_RNDR_trap; 2185 val &= ~ID_AA64PFR1_EL1_NMI; 2186 val &= ~ID_AA64PFR1_EL1_GCS; 2187 val &= ~ID_AA64PFR1_EL1_THE; 2188 val &= ~ID_AA64PFR1_EL1_MTEX; 2189 val &= ~ID_AA64PFR1_EL1_PFAR; 2190 val &= ~ID_AA64PFR1_EL1_MPAM_frac; 2191 2192 return val; 2193 } 2194 2195 static u64 sanitise_id_aa64pfr2_el1(const struct kvm_vcpu *vcpu, u64 val) 2196 { 2197 val &= ID_AA64PFR2_EL1_FPMR | 2198 ID_AA64PFR2_EL1_MTEFAR | 2199 ID_AA64PFR2_EL1_MTESTOREONLY; 2200 2201 if (!kvm_has_mte(vcpu->kvm)) { 2202 val &= ~ID_AA64PFR2_EL1_MTEFAR; 2203 val &= ~ID_AA64PFR2_EL1_MTESTOREONLY; 2204 } 2205 2206 if (vgic_host_has_gicv5()) 2207 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR2_EL1, GCIE, IMP); 2208 2209 return val; 2210 } 2211 2212 static u64 sanitise_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, u64 val) 2213 { 2214 val = ID_REG_LIMIT_FIELD_ENUM(val, ID_AA64DFR0_EL1, DebugVer, V8P8); 2215 2216 /* 2217 * Only initialize the PMU version if the vCPU was configured with one. 2218 */ 2219 val &= ~ID_AA64DFR0_EL1_PMUVer_MASK; 2220 if (kvm_vcpu_has_pmu(vcpu)) 2221 val |= SYS_FIELD_PREP(ID_AA64DFR0_EL1, PMUVer, 2222 kvm_arm_pmu_get_pmuver_limit()); 2223 2224 /* Hide SPE from guests */ 2225 val &= ~ID_AA64DFR0_EL1_PMSVer_MASK; 2226 2227 /* Hide BRBE from guests */ 2228 val &= ~ID_AA64DFR0_EL1_BRBE_MASK; 2229 2230 return val; 2231 } 2232 2233 /* 2234 * Older versions of KVM erroneously claim support for FEAT_DoubleLock with 2235 * NV-enabled VMs on unsupporting hardware. Silently ignore the incorrect 2236 * value if it is consistent with the bug. 2237 */ 2238 static bool ignore_feat_doublelock(struct kvm_vcpu *vcpu, u64 val) 2239 { 2240 u8 host, user; 2241 2242 if (!vcpu_has_nv(vcpu)) 2243 return false; 2244 2245 host = SYS_FIELD_GET(ID_AA64DFR0_EL1, DoubleLock, 2246 read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1)); 2247 user = SYS_FIELD_GET(ID_AA64DFR0_EL1, DoubleLock, val); 2248 2249 return host == ID_AA64DFR0_EL1_DoubleLock_NI && 2250 user == ID_AA64DFR0_EL1_DoubleLock_IMP; 2251 } 2252 2253 static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, 2254 const struct sys_reg_desc *rd, 2255 u64 val) 2256 { 2257 u8 debugver = SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, val); 2258 u8 pmuver = SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, val); 2259 2260 /* 2261 * Prior to commit 3d0dba5764b9 ("KVM: arm64: PMU: Move the 2262 * ID_AA64DFR0_EL1.PMUver limit to VM creation"), KVM erroneously 2263 * exposed an IMP_DEF PMU to userspace and the guest on systems w/ 2264 * non-architectural PMUs. Of course, PMUv3 is the only game in town for 2265 * PMU virtualization, so the IMP_DEF value was rather user-hostile. 2266 * 2267 * At minimum, we're on the hook to allow values that were given to 2268 * userspace by KVM. Cover our tracks here and replace the IMP_DEF value 2269 * with a more sensible NI. The value of an ID register changing under 2270 * the nose of the guest is unfortunate, but is certainly no more 2271 * surprising than an ill-guided PMU driver poking at impdef system 2272 * registers that end in an UNDEF... 2273 */ 2274 if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF) 2275 val &= ~ID_AA64DFR0_EL1_PMUVer_MASK; 2276 2277 /* 2278 * ID_AA64DFR0_EL1.DebugVer is one of those awkward fields with a 2279 * nonzero minimum safe value. 2280 */ 2281 if (debugver < ID_AA64DFR0_EL1_DebugVer_IMP) 2282 return -EINVAL; 2283 2284 if (ignore_feat_doublelock(vcpu, val)) { 2285 val &= ~ID_AA64DFR0_EL1_DoubleLock; 2286 val |= SYS_FIELD_PREP_ENUM(ID_AA64DFR0_EL1, DoubleLock, NI); 2287 } 2288 2289 return set_id_reg(vcpu, rd, val); 2290 } 2291 2292 static u64 read_sanitised_id_dfr0_el1(struct kvm_vcpu *vcpu, 2293 const struct sys_reg_desc *rd) 2294 { 2295 u8 perfmon; 2296 u64 val = read_sanitised_ftr_reg(SYS_ID_DFR0_EL1); 2297 2298 val &= ~ID_DFR0_EL1_PerfMon_MASK; 2299 if (kvm_vcpu_has_pmu(vcpu)) { 2300 perfmon = pmuver_to_perfmon(kvm_arm_pmu_get_pmuver_limit()); 2301 val |= SYS_FIELD_PREP(ID_DFR0_EL1, PerfMon, perfmon); 2302 } 2303 2304 val = ID_REG_LIMIT_FIELD_ENUM(val, ID_DFR0_EL1, CopDbg, Debugv8p8); 2305 2306 return val; 2307 } 2308 2309 static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, 2310 const struct sys_reg_desc *rd, 2311 u64 val) 2312 { 2313 u8 perfmon = SYS_FIELD_GET(ID_DFR0_EL1, PerfMon, val); 2314 u8 copdbg = SYS_FIELD_GET(ID_DFR0_EL1, CopDbg, val); 2315 2316 if (perfmon == ID_DFR0_EL1_PerfMon_IMPDEF) { 2317 val &= ~ID_DFR0_EL1_PerfMon_MASK; 2318 perfmon = 0; 2319 } 2320 2321 /* 2322 * Allow DFR0_EL1.PerfMon to be set from userspace as long as 2323 * it doesn't promise more than what the HW gives us on the 2324 * AArch64 side (as everything is emulated with that), and 2325 * that this is a PMUv3. 2326 */ 2327 if (perfmon != 0 && perfmon < ID_DFR0_EL1_PerfMon_PMUv3) 2328 return -EINVAL; 2329 2330 if (copdbg < ID_DFR0_EL1_CopDbg_Armv8) 2331 return -EINVAL; 2332 2333 return set_id_reg(vcpu, rd, val); 2334 } 2335 2336 static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, 2337 const struct sys_reg_desc *rd, u64 user_val) 2338 { 2339 u64 hw_val = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 2340 u64 mpam_mask = ID_AA64PFR0_EL1_MPAM_MASK; 2341 2342 /* 2343 * Commit 011e5f5bf529f ("arm64/cpufeature: Add remaining feature bits 2344 * in ID_AA64PFR0 register") exposed the MPAM field of AA64PFR0_EL1 to 2345 * guests, but didn't add trap handling. KVM doesn't support MPAM and 2346 * always returns an UNDEF for these registers. The guest must see 0 2347 * for this field. 2348 * 2349 * But KVM must also accept values from user-space that were provided 2350 * by KVM. On CPUs that support MPAM, permit user-space to write 2351 * the sanitizied value to ID_AA64PFR0_EL1.MPAM, but ignore this field. 2352 */ 2353 if ((hw_val & mpam_mask) == (user_val & mpam_mask)) 2354 user_val &= ~ID_AA64PFR0_EL1_MPAM_MASK; 2355 2356 /* Fail the guest's request to disable the AA64 ISA at EL{0,1,2} */ 2357 if (!FIELD_GET(ID_AA64PFR0_EL1_EL0, user_val) || 2358 !FIELD_GET(ID_AA64PFR0_EL1_EL1, user_val) || 2359 (vcpu_has_nv(vcpu) && !FIELD_GET(ID_AA64PFR0_EL1_EL2, user_val))) 2360 return -EINVAL; 2361 2362 return set_id_reg(vcpu, rd, user_val); 2363 } 2364 2365 static int set_id_aa64pfr1_el1(struct kvm_vcpu *vcpu, 2366 const struct sys_reg_desc *rd, u64 user_val) 2367 { 2368 u64 hw_val = read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1); 2369 u64 mpam_mask = ID_AA64PFR1_EL1_MPAM_frac_MASK; 2370 u8 mte = SYS_FIELD_GET(ID_AA64PFR1_EL1, MTE, hw_val); 2371 u8 user_mte_frac = SYS_FIELD_GET(ID_AA64PFR1_EL1, MTE_frac, user_val); 2372 u8 hw_mte_frac = SYS_FIELD_GET(ID_AA64PFR1_EL1, MTE_frac, hw_val); 2373 2374 /* See set_id_aa64pfr0_el1 for comment about MPAM */ 2375 if ((hw_val & mpam_mask) == (user_val & mpam_mask)) 2376 user_val &= ~ID_AA64PFR1_EL1_MPAM_frac_MASK; 2377 2378 /* 2379 * Previously MTE_frac was hidden from guest. However, if the 2380 * hardware supports MTE2 but not MTE_ASYM_FAULT then a value 2381 * of 0 for this field indicates that the hardware supports 2382 * MTE_ASYNC. Whereas, 0xf indicates MTE_ASYNC is not supported. 2383 * 2384 * As KVM must accept values from KVM provided by user-space, 2385 * when ID_AA64PFR1_EL1.MTE is 2 allow user-space to set 2386 * ID_AA64PFR1_EL1.MTE_frac to 0. However, ignore it to avoid 2387 * incorrectly claiming hardware support for MTE_ASYNC in the 2388 * guest. 2389 */ 2390 2391 if (mte == ID_AA64PFR1_EL1_MTE_MTE2 && 2392 hw_mte_frac == ID_AA64PFR1_EL1_MTE_frac_NI && 2393 user_mte_frac == ID_AA64PFR1_EL1_MTE_frac_ASYNC) { 2394 user_val &= ~ID_AA64PFR1_EL1_MTE_frac_MASK; 2395 user_val |= hw_val & ID_AA64PFR1_EL1_MTE_frac_MASK; 2396 } 2397 2398 return set_id_reg(vcpu, rd, user_val); 2399 } 2400 2401 static int set_id_aa64pfr2_el1(struct kvm_vcpu *vcpu, 2402 const struct sys_reg_desc *rd, u64 user_val) 2403 { 2404 return set_id_reg(vcpu, rd, user_val); 2405 } 2406 2407 /* 2408 * Allow userspace to de-feature a stage-2 translation granule but prevent it 2409 * from claiming the impossible. 2410 */ 2411 #define tgran2_val_allowed(tg, safe, user) \ 2412 ({ \ 2413 u8 __s = SYS_FIELD_GET(ID_AA64MMFR0_EL1, tg, safe); \ 2414 u8 __u = SYS_FIELD_GET(ID_AA64MMFR0_EL1, tg, user); \ 2415 \ 2416 __s == __u || __u == ID_AA64MMFR0_EL1_##tg##_NI; \ 2417 }) 2418 2419 static int set_id_aa64mmfr0_el1(struct kvm_vcpu *vcpu, 2420 const struct sys_reg_desc *rd, u64 user_val) 2421 { 2422 u64 sanitized_val = kvm_read_sanitised_id_reg(vcpu, rd); 2423 2424 if (!vcpu_has_nv(vcpu)) 2425 return set_id_reg(vcpu, rd, user_val); 2426 2427 if (!tgran2_val_allowed(TGRAN4_2, sanitized_val, user_val) || 2428 !tgran2_val_allowed(TGRAN16_2, sanitized_val, user_val) || 2429 !tgran2_val_allowed(TGRAN64_2, sanitized_val, user_val)) 2430 return -EINVAL; 2431 2432 return set_id_reg(vcpu, rd, user_val); 2433 } 2434 2435 static int set_id_aa64mmfr2_el1(struct kvm_vcpu *vcpu, 2436 const struct sys_reg_desc *rd, u64 user_val) 2437 { 2438 u64 hw_val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR2_EL1); 2439 u64 nv_mask = ID_AA64MMFR2_EL1_NV_MASK; 2440 2441 /* 2442 * We made the mistake to expose the now deprecated NV field, 2443 * so allow userspace to write it, but silently ignore it. 2444 */ 2445 if ((hw_val & nv_mask) == (user_val & nv_mask)) 2446 user_val &= ~nv_mask; 2447 2448 return set_id_reg(vcpu, rd, user_val); 2449 } 2450 2451 static int set_ctr_el0(struct kvm_vcpu *vcpu, 2452 const struct sys_reg_desc *rd, u64 user_val) 2453 { 2454 u8 user_L1Ip = SYS_FIELD_GET(CTR_EL0, L1Ip, user_val); 2455 2456 /* 2457 * Both AIVIVT (0b01) and VPIPT (0b00) are documented as reserved. 2458 * Hence only allow to set VIPT(0b10) or PIPT(0b11) for L1Ip based 2459 * on what hardware reports. 2460 * 2461 * Using a VIPT software model on PIPT will lead to over invalidation, 2462 * but still correct. Hence, we can allow downgrading PIPT to VIPT, 2463 * but not the other way around. This is handled via arm64_ftr_safe_value() 2464 * as CTR_EL0 ftr_bits has L1Ip field with type FTR_EXACT and safe value 2465 * set as VIPT. 2466 */ 2467 switch (user_L1Ip) { 2468 case CTR_EL0_L1Ip_RESERVED_VPIPT: 2469 case CTR_EL0_L1Ip_RESERVED_AIVIVT: 2470 return -EINVAL; 2471 case CTR_EL0_L1Ip_VIPT: 2472 case CTR_EL0_L1Ip_PIPT: 2473 return set_id_reg(vcpu, rd, user_val); 2474 default: 2475 return -ENOENT; 2476 } 2477 } 2478 2479 /* 2480 * cpufeature ID register user accessors 2481 * 2482 * For now, these registers are immutable for userspace, so no values 2483 * are stored, and for set_id_reg() we don't allow the effective value 2484 * to be changed. 2485 */ 2486 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 2487 u64 *val) 2488 { 2489 /* 2490 * Avoid locking if the VM has already started, as the ID registers are 2491 * guaranteed to be invariant at that point. 2492 */ 2493 if (kvm_vm_has_ran_once(vcpu->kvm)) { 2494 *val = read_id_reg(vcpu, rd); 2495 return 0; 2496 } 2497 2498 mutex_lock(&vcpu->kvm->arch.config_lock); 2499 *val = read_id_reg(vcpu, rd); 2500 mutex_unlock(&vcpu->kvm->arch.config_lock); 2501 2502 return 0; 2503 } 2504 2505 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 2506 u64 val) 2507 { 2508 u32 id = reg_to_encoding(rd); 2509 int ret; 2510 2511 mutex_lock(&vcpu->kvm->arch.config_lock); 2512 2513 /* 2514 * Once the VM has started the ID registers are immutable. Reject any 2515 * write that does not match the final register value. 2516 */ 2517 if (kvm_vm_has_ran_once(vcpu->kvm)) { 2518 if (val != read_id_reg(vcpu, rd)) 2519 ret = -EBUSY; 2520 else 2521 ret = 0; 2522 2523 mutex_unlock(&vcpu->kvm->arch.config_lock); 2524 return ret; 2525 } 2526 2527 ret = arm64_check_features(vcpu, rd, val); 2528 if (!ret) 2529 kvm_set_vm_id_reg(vcpu->kvm, id, val); 2530 2531 mutex_unlock(&vcpu->kvm->arch.config_lock); 2532 2533 /* 2534 * arm64_check_features() returns -E2BIG to indicate the register's 2535 * feature set is a superset of the maximally-allowed register value. 2536 * While it would be nice to precisely describe this to userspace, the 2537 * existing UAPI for KVM_SET_ONE_REG has it that invalid register 2538 * writes return -EINVAL. 2539 */ 2540 if (ret == -E2BIG) 2541 ret = -EINVAL; 2542 return ret; 2543 } 2544 2545 void kvm_set_vm_id_reg(struct kvm *kvm, u32 reg, u64 val) 2546 { 2547 u64 *p = __vm_id_reg(&kvm->arch, reg); 2548 2549 lockdep_assert_held(&kvm->arch.config_lock); 2550 2551 if (KVM_BUG_ON(kvm_vm_has_ran_once(kvm) || !p, kvm)) 2552 return; 2553 2554 *p = val; 2555 } 2556 2557 static int get_raz_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 2558 u64 *val) 2559 { 2560 *val = 0; 2561 return 0; 2562 } 2563 2564 static int set_wi_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 2565 u64 val) 2566 { 2567 return 0; 2568 } 2569 2570 static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2571 const struct sys_reg_desc *r) 2572 { 2573 if (p->is_write) 2574 return write_to_read_only(vcpu, p, r); 2575 2576 p->regval = kvm_read_vm_id_reg(vcpu->kvm, SYS_CTR_EL0); 2577 return true; 2578 } 2579 2580 static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2581 const struct sys_reg_desc *r) 2582 { 2583 if (p->is_write) 2584 return write_to_read_only(vcpu, p, r); 2585 2586 p->regval = __vcpu_sys_reg(vcpu, r->reg); 2587 return true; 2588 } 2589 2590 /* 2591 * Fabricate a CLIDR_EL1 value instead of using the real value, which can vary 2592 * by the physical CPU which the vcpu currently resides in. 2593 */ 2594 static u64 reset_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 2595 { 2596 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0); 2597 u64 clidr; 2598 u8 loc; 2599 2600 if ((ctr_el0 & CTR_EL0_IDC)) { 2601 /* 2602 * Data cache clean to the PoU is not required so LoUU and LoUIS 2603 * will not be set and a unified cache, which will be marked as 2604 * LoC, will be added. 2605 * 2606 * If not DIC, let the unified cache L2 so that an instruction 2607 * cache can be added as L1 later. 2608 */ 2609 loc = (ctr_el0 & CTR_EL0_DIC) ? 1 : 2; 2610 clidr = CACHE_TYPE_UNIFIED << CLIDR_CTYPE_SHIFT(loc); 2611 } else { 2612 /* 2613 * Data cache clean to the PoU is required so let L1 have a data 2614 * cache and mark it as LoUU and LoUIS. As L1 has a data cache, 2615 * it can be marked as LoC too. 2616 */ 2617 loc = 1; 2618 clidr = 1 << CLIDR_LOUU_SHIFT; 2619 clidr |= 1 << CLIDR_LOUIS_SHIFT; 2620 clidr |= CACHE_TYPE_DATA << CLIDR_CTYPE_SHIFT(1); 2621 } 2622 2623 /* 2624 * Instruction cache invalidation to the PoU is required so let L1 have 2625 * an instruction cache. If L1 already has a data cache, it will be 2626 * CACHE_TYPE_SEPARATE. 2627 */ 2628 if (!(ctr_el0 & CTR_EL0_DIC)) 2629 clidr |= CACHE_TYPE_INST << CLIDR_CTYPE_SHIFT(1); 2630 2631 clidr |= loc << CLIDR_LOC_SHIFT; 2632 2633 /* 2634 * Add tag cache unified to data cache. Allocation tags and data are 2635 * unified in a cache line so that it looks valid even if there is only 2636 * one cache line. 2637 */ 2638 if (kvm_has_mte(vcpu->kvm)) 2639 clidr |= 2ULL << CLIDR_TTYPE_SHIFT(loc); 2640 2641 __vcpu_assign_sys_reg(vcpu, r->reg, clidr); 2642 2643 return __vcpu_sys_reg(vcpu, r->reg); 2644 } 2645 2646 static int set_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 2647 u64 val) 2648 { 2649 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0); 2650 u64 idc = !CLIDR_LOC(val) || (!CLIDR_LOUIS(val) && !CLIDR_LOUU(val)); 2651 2652 if ((val & CLIDR_EL1_RES0) || (!(ctr_el0 & CTR_EL0_IDC) && idc)) 2653 return -EINVAL; 2654 2655 __vcpu_assign_sys_reg(vcpu, rd->reg, val); 2656 2657 return 0; 2658 } 2659 2660 static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2661 const struct sys_reg_desc *r) 2662 { 2663 int reg = r->reg; 2664 2665 if (p->is_write) 2666 vcpu_write_sys_reg(vcpu, p->regval, reg); 2667 else 2668 p->regval = vcpu_read_sys_reg(vcpu, reg); 2669 return true; 2670 } 2671 2672 static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2673 const struct sys_reg_desc *r) 2674 { 2675 u32 csselr; 2676 2677 if (p->is_write) 2678 return write_to_read_only(vcpu, p, r); 2679 2680 csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1); 2681 csselr &= CSSELR_EL1_Level | CSSELR_EL1_InD; 2682 if (csselr < CSSELR_MAX) 2683 p->regval = get_ccsidr(vcpu, csselr); 2684 2685 return true; 2686 } 2687 2688 static unsigned int mte_visibility(const struct kvm_vcpu *vcpu, 2689 const struct sys_reg_desc *rd) 2690 { 2691 if (kvm_has_mte(vcpu->kvm)) 2692 return 0; 2693 2694 return REG_HIDDEN; 2695 } 2696 2697 #define MTE_REG(name) { \ 2698 SYS_DESC(SYS_##name), \ 2699 .access = undef_access, \ 2700 .reset = reset_unknown, \ 2701 .reg = name, \ 2702 .visibility = mte_visibility, \ 2703 } 2704 2705 static unsigned int el2_visibility(const struct kvm_vcpu *vcpu, 2706 const struct sys_reg_desc *rd) 2707 { 2708 if (vcpu_has_nv(vcpu)) 2709 return 0; 2710 2711 return REG_HIDDEN; 2712 } 2713 2714 static bool bad_vncr_trap(struct kvm_vcpu *vcpu, 2715 struct sys_reg_params *p, 2716 const struct sys_reg_desc *r) 2717 { 2718 /* 2719 * We really shouldn't be here, and this is likely the result 2720 * of a misconfigured trap, as this register should target the 2721 * VNCR page, and nothing else. 2722 */ 2723 return bad_trap(vcpu, p, r, 2724 "trap of VNCR-backed register"); 2725 } 2726 2727 static bool bad_redir_trap(struct kvm_vcpu *vcpu, 2728 struct sys_reg_params *p, 2729 const struct sys_reg_desc *r) 2730 { 2731 /* 2732 * We really shouldn't be here, and this is likely the result 2733 * of a misconfigured trap, as this register should target the 2734 * corresponding EL1, and nothing else. 2735 */ 2736 return bad_trap(vcpu, p, r, 2737 "trap of EL2 register redirected to EL1"); 2738 } 2739 2740 #define SYS_REG_USER_FILTER(name, acc, rst, v, gu, su, filter) { \ 2741 SYS_DESC(SYS_##name), \ 2742 .access = acc, \ 2743 .reset = rst, \ 2744 .reg = name, \ 2745 .get_user = gu, \ 2746 .set_user = su, \ 2747 .visibility = filter, \ 2748 .val = v, \ 2749 } 2750 2751 #define EL2_REG_FILTERED(name, acc, rst, v, filter) \ 2752 SYS_REG_USER_FILTER(name, acc, rst, v, NULL, NULL, filter) 2753 2754 #define EL2_REG(name, acc, rst, v) \ 2755 EL2_REG_FILTERED(name, acc, rst, v, el2_visibility) 2756 2757 #define EL2_REG_VNCR(name, rst, v) EL2_REG(name, bad_vncr_trap, rst, v) 2758 #define EL2_REG_VNCR_FILT(name, vis) \ 2759 EL2_REG_FILTERED(name, bad_vncr_trap, reset_val, 0, vis) 2760 #define EL2_REG_VNCR_GICv3(name) \ 2761 EL2_REG_VNCR_FILT(name, hidden_visibility) 2762 #define EL2_REG_REDIR(name, rst, v) EL2_REG(name, bad_redir_trap, rst, v) 2763 2764 #define TIMER_REG(name, vis) \ 2765 SYS_REG_USER_FILTER(name, access_arch_timer, reset_val, 0, \ 2766 arch_timer_get_user, arch_timer_set_user, vis) 2767 2768 /* 2769 * Since reset() callback and field val are not used for idregs, they will be 2770 * used for specific purposes for idregs. 2771 * The reset() would return KVM sanitised register value. The value would be the 2772 * same as the host kernel sanitised value if there is no KVM sanitisation. 2773 * The val would be used as a mask indicating writable fields for the idreg. 2774 * Only bits with 1 are writable from userspace. This mask might not be 2775 * necessary in the future whenever all ID registers are enabled as writable 2776 * from userspace. 2777 */ 2778 2779 #define ID_DESC_DEFAULT_CALLBACKS \ 2780 .access = access_id_reg, \ 2781 .get_user = get_id_reg, \ 2782 .set_user = set_id_reg, \ 2783 .visibility = id_visibility, \ 2784 .reset = kvm_read_sanitised_id_reg 2785 2786 #define ID_DESC(name) \ 2787 SYS_DESC(SYS_##name), \ 2788 ID_DESC_DEFAULT_CALLBACKS 2789 2790 /* sys_reg_desc initialiser for known cpufeature ID registers */ 2791 #define ID_SANITISED(name) { \ 2792 ID_DESC(name), \ 2793 .val = 0, \ 2794 } 2795 2796 /* sys_reg_desc initialiser for writable ID registers */ 2797 #define ID_WRITABLE(name, mask) { \ 2798 ID_DESC(name), \ 2799 .val = mask, \ 2800 } 2801 2802 /* 2803 * 32bit ID regs are fully writable when the guest is 32bit 2804 * capable. Nothing in the KVM code should rely on 32bit features 2805 * anyway, only 64bit, so let the VMM do its worse. 2806 */ 2807 #define AA32_ID_WRITABLE(name) { \ 2808 ID_DESC(name), \ 2809 .visibility = aa32_id_visibility, \ 2810 .val = GENMASK(31, 0), \ 2811 } 2812 2813 /* sys_reg_desc initialiser for cpufeature ID registers that need filtering */ 2814 #define ID_FILTERED(sysreg, name, mask) { \ 2815 ID_DESC(sysreg), \ 2816 .set_user = set_##name, \ 2817 .val = (mask), \ 2818 } 2819 2820 /* 2821 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID 2822 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2 2823 * (1 <= crm < 8, 0 <= Op2 < 8). 2824 */ 2825 #define ID_UNALLOCATED(crm, op2) { \ 2826 .name = "S3_0_0_" #crm "_" #op2, \ 2827 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \ 2828 ID_DESC_DEFAULT_CALLBACKS, \ 2829 .visibility = raz_visibility, \ 2830 .val = 0, \ 2831 } 2832 2833 /* 2834 * sys_reg_desc initialiser for known ID registers that we hide from guests. 2835 * For now, these are exposed just like unallocated ID regs: they appear 2836 * RAZ for the guest. 2837 */ 2838 #define ID_HIDDEN(name) { \ 2839 ID_DESC(name), \ 2840 .visibility = raz_visibility, \ 2841 .val = 0, \ 2842 } 2843 2844 static bool access_sp_el1(struct kvm_vcpu *vcpu, 2845 struct sys_reg_params *p, 2846 const struct sys_reg_desc *r) 2847 { 2848 if (p->is_write) 2849 __vcpu_assign_sys_reg(vcpu, SP_EL1, p->regval); 2850 else 2851 p->regval = __vcpu_sys_reg(vcpu, SP_EL1); 2852 2853 return true; 2854 } 2855 2856 static bool access_elr(struct kvm_vcpu *vcpu, 2857 struct sys_reg_params *p, 2858 const struct sys_reg_desc *r) 2859 { 2860 if (p->is_write) 2861 vcpu_write_sys_reg(vcpu, p->regval, ELR_EL1); 2862 else 2863 p->regval = vcpu_read_sys_reg(vcpu, ELR_EL1); 2864 2865 return true; 2866 } 2867 2868 static bool access_spsr(struct kvm_vcpu *vcpu, 2869 struct sys_reg_params *p, 2870 const struct sys_reg_desc *r) 2871 { 2872 if (p->is_write) 2873 __vcpu_assign_sys_reg(vcpu, SPSR_EL1, p->regval); 2874 else 2875 p->regval = __vcpu_sys_reg(vcpu, SPSR_EL1); 2876 2877 return true; 2878 } 2879 2880 static bool access_cntkctl_el12(struct kvm_vcpu *vcpu, 2881 struct sys_reg_params *p, 2882 const struct sys_reg_desc *r) 2883 { 2884 if (p->is_write) 2885 __vcpu_assign_sys_reg(vcpu, CNTKCTL_EL1, p->regval); 2886 else 2887 p->regval = __vcpu_sys_reg(vcpu, CNTKCTL_EL1); 2888 2889 return true; 2890 } 2891 2892 static u64 reset_hcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 2893 { 2894 u64 val = r->val; 2895 2896 if (!cpus_have_final_cap(ARM64_HAS_HCR_NV1)) 2897 val |= HCR_E2H; 2898 2899 __vcpu_assign_sys_reg(vcpu, r->reg, val); 2900 2901 return __vcpu_sys_reg(vcpu, r->reg); 2902 } 2903 2904 static unsigned int __el2_visibility(const struct kvm_vcpu *vcpu, 2905 const struct sys_reg_desc *rd, 2906 unsigned int (*fn)(const struct kvm_vcpu *, 2907 const struct sys_reg_desc *)) 2908 { 2909 return el2_visibility(vcpu, rd) ?: fn(vcpu, rd); 2910 } 2911 2912 static unsigned int sve_el2_visibility(const struct kvm_vcpu *vcpu, 2913 const struct sys_reg_desc *rd) 2914 { 2915 return __el2_visibility(vcpu, rd, sve_visibility); 2916 } 2917 2918 static unsigned int vncr_el2_visibility(const struct kvm_vcpu *vcpu, 2919 const struct sys_reg_desc *rd) 2920 { 2921 if (el2_visibility(vcpu, rd) == 0 && 2922 kvm_has_feat(vcpu->kvm, ID_AA64MMFR4_EL1, NV_frac, NV2_ONLY)) 2923 return 0; 2924 2925 return REG_HIDDEN; 2926 } 2927 2928 static unsigned int nvhcr_el2_visibility(const struct kvm_vcpu *vcpu, 2929 const struct sys_reg_desc *rd) 2930 { 2931 if (el2_visibility(vcpu, rd) == 0 && 2932 kvm_has_feat(vcpu->kvm, ID_AA64MMFR4_EL1, NV_frac, NV3)) 2933 return 0; 2934 2935 return REG_HIDDEN; 2936 } 2937 2938 static unsigned int sctlr2_visibility(const struct kvm_vcpu *vcpu, 2939 const struct sys_reg_desc *rd) 2940 { 2941 if (kvm_has_sctlr2(vcpu->kvm)) 2942 return 0; 2943 2944 return REG_HIDDEN; 2945 } 2946 2947 static unsigned int sctlr2_el2_visibility(const struct kvm_vcpu *vcpu, 2948 const struct sys_reg_desc *rd) 2949 { 2950 return __el2_visibility(vcpu, rd, sctlr2_visibility); 2951 } 2952 2953 static bool access_zcr_el2(struct kvm_vcpu *vcpu, 2954 struct sys_reg_params *p, 2955 const struct sys_reg_desc *r) 2956 { 2957 if (guest_hyp_sve_traps_enabled(vcpu)) { 2958 kvm_inject_nested_sve_trap(vcpu); 2959 return false; 2960 } 2961 2962 if (!p->is_write) 2963 p->regval = __vcpu_sys_reg(vcpu, ZCR_EL2); 2964 else 2965 __vcpu_assign_sys_reg(vcpu, ZCR_EL2, p->regval); 2966 2967 return true; 2968 } 2969 2970 static bool access_gic_vtr(struct kvm_vcpu *vcpu, 2971 struct sys_reg_params *p, 2972 const struct sys_reg_desc *r) 2973 { 2974 if (p->is_write) 2975 return write_to_read_only(vcpu, p, r); 2976 2977 p->regval = kvm_get_guest_vtr_el2(); 2978 2979 return true; 2980 } 2981 2982 static bool access_gic_misr(struct kvm_vcpu *vcpu, 2983 struct sys_reg_params *p, 2984 const struct sys_reg_desc *r) 2985 { 2986 if (p->is_write) 2987 return write_to_read_only(vcpu, p, r); 2988 2989 p->regval = vgic_v3_get_misr(vcpu); 2990 2991 return true; 2992 } 2993 2994 static bool access_gic_eisr(struct kvm_vcpu *vcpu, 2995 struct sys_reg_params *p, 2996 const struct sys_reg_desc *r) 2997 { 2998 if (p->is_write) 2999 return write_to_read_only(vcpu, p, r); 3000 3001 p->regval = vgic_v3_get_eisr(vcpu); 3002 3003 return true; 3004 } 3005 3006 static bool access_gic_elrsr(struct kvm_vcpu *vcpu, 3007 struct sys_reg_params *p, 3008 const struct sys_reg_desc *r) 3009 { 3010 if (p->is_write) 3011 return write_to_read_only(vcpu, p, r); 3012 3013 p->regval = vgic_v3_get_elrsr(vcpu); 3014 3015 return true; 3016 } 3017 3018 static unsigned int s1poe_visibility(const struct kvm_vcpu *vcpu, 3019 const struct sys_reg_desc *rd) 3020 { 3021 if (kvm_has_s1poe(vcpu->kvm)) 3022 return 0; 3023 3024 return REG_HIDDEN; 3025 } 3026 3027 static unsigned int s1poe_el2_visibility(const struct kvm_vcpu *vcpu, 3028 const struct sys_reg_desc *rd) 3029 { 3030 return __el2_visibility(vcpu, rd, s1poe_visibility); 3031 } 3032 3033 static unsigned int tcr2_visibility(const struct kvm_vcpu *vcpu, 3034 const struct sys_reg_desc *rd) 3035 { 3036 if (kvm_has_tcr2(vcpu->kvm)) 3037 return 0; 3038 3039 return REG_HIDDEN; 3040 } 3041 3042 static unsigned int tcr2_el2_visibility(const struct kvm_vcpu *vcpu, 3043 const struct sys_reg_desc *rd) 3044 { 3045 return __el2_visibility(vcpu, rd, tcr2_visibility); 3046 } 3047 3048 static unsigned int fgt2_visibility(const struct kvm_vcpu *vcpu, 3049 const struct sys_reg_desc *rd) 3050 { 3051 if (el2_visibility(vcpu, rd) == 0 && 3052 kvm_has_feat(vcpu->kvm, ID_AA64MMFR0_EL1, FGT, FGT2)) 3053 return 0; 3054 3055 return REG_HIDDEN; 3056 } 3057 3058 static unsigned int fgt_visibility(const struct kvm_vcpu *vcpu, 3059 const struct sys_reg_desc *rd) 3060 { 3061 if (el2_visibility(vcpu, rd) == 0 && 3062 kvm_has_feat(vcpu->kvm, ID_AA64MMFR0_EL1, FGT, IMP)) 3063 return 0; 3064 3065 return REG_HIDDEN; 3066 } 3067 3068 static unsigned int s1pie_visibility(const struct kvm_vcpu *vcpu, 3069 const struct sys_reg_desc *rd) 3070 { 3071 if (kvm_has_s1pie(vcpu->kvm)) 3072 return 0; 3073 3074 return REG_HIDDEN; 3075 } 3076 3077 static unsigned int s1pie_el2_visibility(const struct kvm_vcpu *vcpu, 3078 const struct sys_reg_desc *rd) 3079 { 3080 return __el2_visibility(vcpu, rd, s1pie_visibility); 3081 } 3082 3083 static unsigned int cnthv_visibility(const struct kvm_vcpu *vcpu, 3084 const struct sys_reg_desc *rd) 3085 { 3086 if (vcpu_has_nv(vcpu) && 3087 !vcpu_has_feature(vcpu, KVM_ARM_VCPU_HAS_EL2_E2H0)) 3088 return 0; 3089 3090 return REG_HIDDEN; 3091 } 3092 3093 static bool access_mdcr(struct kvm_vcpu *vcpu, 3094 struct sys_reg_params *p, 3095 const struct sys_reg_desc *r) 3096 { 3097 u64 hpmn, val, old = __vcpu_sys_reg(vcpu, MDCR_EL2); 3098 3099 if (!p->is_write) { 3100 p->regval = old; 3101 return true; 3102 } 3103 3104 val = p->regval; 3105 hpmn = FIELD_GET(MDCR_EL2_HPMN, val); 3106 3107 /* 3108 * If HPMN is out of bounds, limit it to what we actually 3109 * support. This matches the UNKNOWN definition of the field 3110 * in that case, and keeps the emulation simple. Sort of. 3111 */ 3112 if (hpmn > vcpu->kvm->arch.nr_pmu_counters) { 3113 hpmn = vcpu->kvm->arch.nr_pmu_counters; 3114 u64p_replace_bits(&val, hpmn, MDCR_EL2_HPMN); 3115 } 3116 3117 __vcpu_assign_sys_reg(vcpu, MDCR_EL2, val); 3118 3119 /* 3120 * Request a reload of the PMU to enable/disable the counters 3121 * affected by HPME. 3122 */ 3123 if ((old ^ val) & MDCR_EL2_HPME) 3124 kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu); 3125 3126 return true; 3127 } 3128 3129 static bool access_ras(struct kvm_vcpu *vcpu, 3130 struct sys_reg_params *p, 3131 const struct sys_reg_desc *r) 3132 { 3133 struct kvm *kvm = vcpu->kvm; 3134 3135 switch(reg_to_encoding(r)) { 3136 case SYS_ERXPFGCDN_EL1: 3137 case SYS_ERXPFGCTL_EL1: 3138 case SYS_ERXPFGF_EL1: 3139 case SYS_ERXMISC2_EL1: 3140 case SYS_ERXMISC3_EL1: 3141 if (!(kvm_has_feat(kvm, ID_AA64PFR0_EL1, RAS, V1P1) || 3142 (kvm_has_feat_enum(kvm, ID_AA64PFR0_EL1, RAS, IMP) && 3143 kvm_has_feat(kvm, ID_AA64PFR1_EL1, RAS_frac, RASv1p1)))) { 3144 kvm_inject_undefined(vcpu); 3145 return false; 3146 } 3147 break; 3148 default: 3149 if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, RAS, IMP)) { 3150 kvm_inject_undefined(vcpu); 3151 return false; 3152 } 3153 } 3154 3155 return trap_raz_wi(vcpu, p, r); 3156 } 3157 3158 /* 3159 * For historical (ahem ABI) reasons, KVM treated MIDR_EL1, REVIDR_EL1, and 3160 * AIDR_EL1 as "invariant" registers, meaning userspace cannot change them. 3161 * The values made visible to userspace were the register values of the boot 3162 * CPU. 3163 * 3164 * At the same time, reads from these registers at EL1 previously were not 3165 * trapped, allowing the guest to read the actual hardware value. On big-little 3166 * machines, this means the VM can see different values depending on where a 3167 * given vCPU got scheduled. 3168 * 3169 * These registers are now trapped as collateral damage from SME, and what 3170 * follows attempts to give a user / guest view consistent with the existing 3171 * ABI. 3172 */ 3173 static bool access_imp_id_reg(struct kvm_vcpu *vcpu, 3174 struct sys_reg_params *p, 3175 const struct sys_reg_desc *r) 3176 { 3177 if (p->is_write) 3178 return write_to_read_only(vcpu, p, r); 3179 3180 /* 3181 * Return the VM-scoped implementation ID register values if userspace 3182 * has made them writable. 3183 */ 3184 if (test_bit(KVM_ARCH_FLAG_WRITABLE_IMP_ID_REGS, &vcpu->kvm->arch.flags)) 3185 return access_id_reg(vcpu, p, r); 3186 3187 /* 3188 * Otherwise, fall back to the old behavior of returning the value of 3189 * the current CPU. 3190 */ 3191 switch (reg_to_encoding(r)) { 3192 case SYS_REVIDR_EL1: 3193 p->regval = read_sysreg(revidr_el1); 3194 break; 3195 case SYS_AIDR_EL1: 3196 p->regval = read_sysreg(aidr_el1); 3197 break; 3198 default: 3199 WARN_ON_ONCE(1); 3200 } 3201 3202 return true; 3203 } 3204 3205 static u64 __ro_after_init boot_cpu_midr_val; 3206 static u64 __ro_after_init boot_cpu_revidr_val; 3207 static u64 __ro_after_init boot_cpu_aidr_val; 3208 3209 static void init_imp_id_regs(void) 3210 { 3211 boot_cpu_midr_val = read_sysreg(midr_el1); 3212 boot_cpu_revidr_val = read_sysreg(revidr_el1); 3213 boot_cpu_aidr_val = read_sysreg(aidr_el1); 3214 } 3215 3216 static u64 reset_imp_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 3217 { 3218 switch (reg_to_encoding(r)) { 3219 case SYS_MIDR_EL1: 3220 return boot_cpu_midr_val; 3221 case SYS_REVIDR_EL1: 3222 return boot_cpu_revidr_val; 3223 case SYS_AIDR_EL1: 3224 return boot_cpu_aidr_val; 3225 default: 3226 KVM_BUG_ON(1, vcpu->kvm); 3227 return 0; 3228 } 3229 } 3230 3231 static int set_imp_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 3232 u64 val) 3233 { 3234 struct kvm *kvm = vcpu->kvm; 3235 u64 expected; 3236 3237 guard(mutex)(&kvm->arch.config_lock); 3238 3239 expected = read_id_reg(vcpu, r); 3240 if (expected == val) 3241 return 0; 3242 3243 if (!test_bit(KVM_ARCH_FLAG_WRITABLE_IMP_ID_REGS, &kvm->arch.flags)) 3244 return -EINVAL; 3245 3246 /* 3247 * Once the VM has started the ID registers are immutable. Reject the 3248 * write if userspace tries to change it. 3249 */ 3250 if (kvm_vm_has_ran_once(kvm)) 3251 return -EBUSY; 3252 3253 /* 3254 * Any value is allowed for the implementation ID registers so long as 3255 * it is within the writable mask. 3256 */ 3257 if ((val & r->val) != val) 3258 return -EINVAL; 3259 3260 kvm_set_vm_id_reg(kvm, reg_to_encoding(r), val); 3261 return 0; 3262 } 3263 3264 #define IMPLEMENTATION_ID(reg, mask) { \ 3265 SYS_DESC(SYS_##reg), \ 3266 .access = access_imp_id_reg, \ 3267 .get_user = get_id_reg, \ 3268 .set_user = set_imp_id_reg, \ 3269 .reset = reset_imp_id_reg, \ 3270 .val = mask, \ 3271 } 3272 3273 static u64 reset_mdcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 3274 { 3275 __vcpu_assign_sys_reg(vcpu, r->reg, vcpu->kvm->arch.nr_pmu_counters); 3276 return vcpu->kvm->arch.nr_pmu_counters; 3277 } 3278 3279 /* 3280 * Architected system registers. 3281 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2 3282 * 3283 * Debug handling: We do trap most, if not all debug related system 3284 * registers. The implementation is good enough to ensure that a guest 3285 * can use these with minimal performance degradation. The drawback is 3286 * that we don't implement any of the external debug architecture. 3287 * This should be revisited if we ever encounter a more demanding 3288 * guest... 3289 */ 3290 static const struct sys_reg_desc sys_reg_descs[] = { 3291 DBG_BCR_BVR_WCR_WVR_EL1(0), 3292 DBG_BCR_BVR_WCR_WVR_EL1(1), 3293 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 }, 3294 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 }, 3295 DBG_BCR_BVR_WCR_WVR_EL1(2), 3296 DBG_BCR_BVR_WCR_WVR_EL1(3), 3297 DBG_BCR_BVR_WCR_WVR_EL1(4), 3298 DBG_BCR_BVR_WCR_WVR_EL1(5), 3299 DBG_BCR_BVR_WCR_WVR_EL1(6), 3300 DBG_BCR_BVR_WCR_WVR_EL1(7), 3301 DBG_BCR_BVR_WCR_WVR_EL1(8), 3302 DBG_BCR_BVR_WCR_WVR_EL1(9), 3303 DBG_BCR_BVR_WCR_WVR_EL1(10), 3304 DBG_BCR_BVR_WCR_WVR_EL1(11), 3305 DBG_BCR_BVR_WCR_WVR_EL1(12), 3306 DBG_BCR_BVR_WCR_WVR_EL1(13), 3307 DBG_BCR_BVR_WCR_WVR_EL1(14), 3308 DBG_BCR_BVR_WCR_WVR_EL1(15), 3309 3310 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi }, 3311 { SYS_DESC(SYS_OSLAR_EL1), trap_oslar_el1 }, 3312 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1, 3313 OSLSR_EL1_OSLM_IMPLEMENTED, .set_user = set_oslsr_el1, }, 3314 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi }, 3315 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi }, 3316 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi }, 3317 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi }, 3318 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 }, 3319 3320 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi }, 3321 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi }, 3322 // DBGDTR[TR]X_EL0 share the same encoding 3323 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi }, 3324 3325 { SYS_DESC(SYS_DBGVCR32_EL2), undef_access, reset_val, DBGVCR32_EL2, 0 }, 3326 3327 IMPLEMENTATION_ID(MIDR_EL1, GENMASK_ULL(31, 0)), 3328 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 }, 3329 IMPLEMENTATION_ID(REVIDR_EL1, GENMASK_ULL(63, 0)), 3330 3331 /* 3332 * ID regs: all ID_SANITISED() entries here must have corresponding 3333 * entries in arm64_ftr_regs[]. 3334 */ 3335 3336 /* AArch64 mappings of the AArch32 ID registers */ 3337 /* CRm=1 */ 3338 AA32_ID_WRITABLE(ID_PFR0_EL1), 3339 AA32_ID_WRITABLE(ID_PFR1_EL1), 3340 { SYS_DESC(SYS_ID_DFR0_EL1), 3341 .access = access_id_reg, 3342 .get_user = get_id_reg, 3343 .set_user = set_id_dfr0_el1, 3344 .visibility = aa32_id_visibility, 3345 .reset = read_sanitised_id_dfr0_el1, 3346 .val = GENMASK(31, 0) }, 3347 ID_HIDDEN(ID_AFR0_EL1), 3348 AA32_ID_WRITABLE(ID_MMFR0_EL1), 3349 AA32_ID_WRITABLE(ID_MMFR1_EL1), 3350 AA32_ID_WRITABLE(ID_MMFR2_EL1), 3351 AA32_ID_WRITABLE(ID_MMFR3_EL1), 3352 3353 /* CRm=2 */ 3354 AA32_ID_WRITABLE(ID_ISAR0_EL1), 3355 AA32_ID_WRITABLE(ID_ISAR1_EL1), 3356 AA32_ID_WRITABLE(ID_ISAR2_EL1), 3357 AA32_ID_WRITABLE(ID_ISAR3_EL1), 3358 AA32_ID_WRITABLE(ID_ISAR4_EL1), 3359 AA32_ID_WRITABLE(ID_ISAR5_EL1), 3360 AA32_ID_WRITABLE(ID_MMFR4_EL1), 3361 AA32_ID_WRITABLE(ID_ISAR6_EL1), 3362 3363 /* CRm=3 */ 3364 AA32_ID_WRITABLE(MVFR0_EL1), 3365 AA32_ID_WRITABLE(MVFR1_EL1), 3366 AA32_ID_WRITABLE(MVFR2_EL1), 3367 ID_UNALLOCATED(3,3), 3368 AA32_ID_WRITABLE(ID_PFR2_EL1), 3369 ID_HIDDEN(ID_DFR1_EL1), 3370 AA32_ID_WRITABLE(ID_MMFR5_EL1), 3371 ID_UNALLOCATED(3,7), 3372 3373 /* AArch64 ID registers */ 3374 /* CRm=4 */ 3375 ID_FILTERED(ID_AA64PFR0_EL1, id_aa64pfr0_el1, 3376 ~(ID_AA64PFR0_EL1_AMU | 3377 ID_AA64PFR0_EL1_MPAM | 3378 ID_AA64PFR0_EL1_SVE | 3379 ID_AA64PFR0_EL1_AdvSIMD | 3380 ID_AA64PFR0_EL1_FP)), 3381 ID_FILTERED(ID_AA64PFR1_EL1, id_aa64pfr1_el1, 3382 ~(ID_AA64PFR1_EL1_PFAR | 3383 ID_AA64PFR1_EL1_MTEX | 3384 ID_AA64PFR1_EL1_THE | 3385 ID_AA64PFR1_EL1_GCS | 3386 ID_AA64PFR1_EL1_MTE_frac | 3387 ID_AA64PFR1_EL1_NMI | 3388 ID_AA64PFR1_EL1_RNDR_trap | 3389 ID_AA64PFR1_EL1_SME | 3390 ID_AA64PFR1_EL1_RES0 | 3391 ID_AA64PFR1_EL1_MPAM_frac | 3392 ID_AA64PFR1_EL1_MTE)), 3393 ID_FILTERED(ID_AA64PFR2_EL1, id_aa64pfr2_el1, 3394 (ID_AA64PFR2_EL1_FPMR | 3395 ID_AA64PFR2_EL1_MTEFAR | 3396 ID_AA64PFR2_EL1_MTESTOREONLY | 3397 ID_AA64PFR2_EL1_GCIE)), 3398 ID_UNALLOCATED(4,3), 3399 ID_WRITABLE(ID_AA64ZFR0_EL1, ~ID_AA64ZFR0_EL1_RES0), 3400 ID_HIDDEN(ID_AA64SMFR0_EL1), 3401 ID_UNALLOCATED(4,6), 3402 ID_WRITABLE(ID_AA64FPFR0_EL1, ~ID_AA64FPFR0_EL1_RES0), 3403 3404 /* CRm=5 */ 3405 /* 3406 * Prior to FEAT_Debugv8.9, the architecture defines context-aware 3407 * breakpoints (CTX_CMPs) as the highest numbered breakpoints (BRPs). 3408 * KVM does not trap + emulate the breakpoint registers, and as such 3409 * cannot support a layout that misaligns with the underlying hardware. 3410 * While it may be possible to describe a subset that aligns with 3411 * hardware, just prevent changes to BRPs and CTX_CMPs altogether for 3412 * simplicity. 3413 * 3414 * See DDI0487K.a, section D2.8.3 Breakpoint types and linking 3415 * of breakpoints for more details. 3416 */ 3417 ID_FILTERED(ID_AA64DFR0_EL1, id_aa64dfr0_el1, 3418 ID_AA64DFR0_EL1_DoubleLock_MASK | 3419 ID_AA64DFR0_EL1_WRPs_MASK | 3420 ID_AA64DFR0_EL1_PMUVer_MASK | 3421 ID_AA64DFR0_EL1_DebugVer_MASK), 3422 ID_SANITISED(ID_AA64DFR1_EL1), 3423 ID_UNALLOCATED(5,2), 3424 ID_UNALLOCATED(5,3), 3425 ID_HIDDEN(ID_AA64AFR0_EL1), 3426 ID_HIDDEN(ID_AA64AFR1_EL1), 3427 ID_UNALLOCATED(5,6), 3428 ID_UNALLOCATED(5,7), 3429 3430 /* CRm=6 */ 3431 ID_WRITABLE(ID_AA64ISAR0_EL1, ~ID_AA64ISAR0_EL1_RES0), 3432 ID_WRITABLE(ID_AA64ISAR1_EL1, ~(ID_AA64ISAR1_EL1_GPI | 3433 ID_AA64ISAR1_EL1_GPA | 3434 ID_AA64ISAR1_EL1_API | 3435 ID_AA64ISAR1_EL1_APA)), 3436 ID_WRITABLE(ID_AA64ISAR2_EL1, ~(ID_AA64ISAR2_EL1_RES0 | 3437 ID_AA64ISAR2_EL1_APA3 | 3438 ID_AA64ISAR2_EL1_GPA3)), 3439 ID_WRITABLE(ID_AA64ISAR3_EL1, (ID_AA64ISAR3_EL1_FPRCVT | 3440 ID_AA64ISAR3_EL1_LSFE | 3441 ID_AA64ISAR3_EL1_LSUI | 3442 ID_AA64ISAR3_EL1_FAMINMAX)), 3443 ID_UNALLOCATED(6,4), 3444 ID_UNALLOCATED(6,5), 3445 ID_UNALLOCATED(6,6), 3446 ID_UNALLOCATED(6,7), 3447 3448 /* CRm=7 */ 3449 ID_FILTERED(ID_AA64MMFR0_EL1, id_aa64mmfr0_el1, 3450 ~(ID_AA64MMFR0_EL1_RES0 | 3451 ID_AA64MMFR0_EL1_ASIDBITS)), 3452 ID_WRITABLE(ID_AA64MMFR1_EL1, ~(ID_AA64MMFR1_EL1_RES0 | 3453 ID_AA64MMFR1_EL1_XNX | 3454 ID_AA64MMFR1_EL1_VH | 3455 ID_AA64MMFR1_EL1_VMIDBits)), 3456 ID_FILTERED(ID_AA64MMFR2_EL1, 3457 id_aa64mmfr2_el1, ~(ID_AA64MMFR2_EL1_RES0 | 3458 ID_AA64MMFR2_EL1_EVT | 3459 ID_AA64MMFR2_EL1_FWB | 3460 ID_AA64MMFR2_EL1_IDS | 3461 ID_AA64MMFR2_EL1_NV | 3462 ID_AA64MMFR2_EL1_CCIDX)), 3463 ID_WRITABLE(ID_AA64MMFR3_EL1, (ID_AA64MMFR3_EL1_TCRX | 3464 ID_AA64MMFR3_EL1_SCTLRX | 3465 ID_AA64MMFR3_EL1_S1PIE | 3466 ID_AA64MMFR3_EL1_S1POE)), 3467 ID_WRITABLE(ID_AA64MMFR4_EL1, ID_AA64MMFR4_EL1_NV_frac), 3468 ID_UNALLOCATED(7,5), 3469 ID_UNALLOCATED(7,6), 3470 ID_UNALLOCATED(7,7), 3471 3472 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 }, 3473 { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 }, 3474 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 }, 3475 { SYS_DESC(SYS_SCTLR2_EL1), access_vm_reg, reset_val, SCTLR2_EL1, 0, 3476 .visibility = sctlr2_visibility }, 3477 3478 MTE_REG(RGSR_EL1), 3479 MTE_REG(GCR_EL1), 3480 3481 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility }, 3482 { SYS_DESC(SYS_TRFCR_EL1), undef_access }, 3483 { SYS_DESC(SYS_SMPRI_EL1), undef_access }, 3484 { SYS_DESC(SYS_SMCR_EL1), undef_access }, 3485 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 }, 3486 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 }, 3487 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 }, 3488 { SYS_DESC(SYS_TCR2_EL1), access_vm_reg, reset_val, TCR2_EL1, 0, 3489 .visibility = tcr2_visibility }, 3490 3491 PTRAUTH_KEY(APIA), 3492 PTRAUTH_KEY(APIB), 3493 PTRAUTH_KEY(APDA), 3494 PTRAUTH_KEY(APDB), 3495 PTRAUTH_KEY(APGA), 3496 3497 { SYS_DESC(SYS_SPSR_EL1), access_spsr}, 3498 { SYS_DESC(SYS_ELR_EL1), access_elr}, 3499 3500 { SYS_DESC(SYS_ICC_PMR_EL1), undef_access }, 3501 3502 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 }, 3503 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 }, 3504 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 }, 3505 3506 { SYS_DESC(SYS_ERRIDR_EL1), access_ras }, 3507 { SYS_DESC(SYS_ERRSELR_EL1), access_ras }, 3508 { SYS_DESC(SYS_ERXFR_EL1), access_ras }, 3509 { SYS_DESC(SYS_ERXCTLR_EL1), access_ras }, 3510 { SYS_DESC(SYS_ERXSTATUS_EL1), access_ras }, 3511 { SYS_DESC(SYS_ERXADDR_EL1), access_ras }, 3512 { SYS_DESC(SYS_ERXPFGF_EL1), access_ras }, 3513 { SYS_DESC(SYS_ERXPFGCTL_EL1), access_ras }, 3514 { SYS_DESC(SYS_ERXPFGCDN_EL1), access_ras }, 3515 { SYS_DESC(SYS_ERXMISC0_EL1), access_ras }, 3516 { SYS_DESC(SYS_ERXMISC1_EL1), access_ras }, 3517 { SYS_DESC(SYS_ERXMISC2_EL1), access_ras }, 3518 { SYS_DESC(SYS_ERXMISC3_EL1), access_ras }, 3519 3520 MTE_REG(TFSR_EL1), 3521 MTE_REG(TFSRE0_EL1), 3522 3523 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 }, 3524 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 }, 3525 3526 { SYS_DESC(SYS_PMSCR_EL1), undef_access }, 3527 { SYS_DESC(SYS_PMSNEVFR_EL1), undef_access }, 3528 { SYS_DESC(SYS_PMSICR_EL1), undef_access }, 3529 { SYS_DESC(SYS_PMSIRR_EL1), undef_access }, 3530 { SYS_DESC(SYS_PMSFCR_EL1), undef_access }, 3531 { SYS_DESC(SYS_PMSEVFR_EL1), undef_access }, 3532 { SYS_DESC(SYS_PMSLATFR_EL1), undef_access }, 3533 { SYS_DESC(SYS_PMSIDR_EL1), undef_access }, 3534 { SYS_DESC(SYS_PMBLIMITR_EL1), undef_access }, 3535 { SYS_DESC(SYS_PMBPTR_EL1), undef_access }, 3536 { SYS_DESC(SYS_PMBSR_EL1), undef_access }, 3537 { SYS_DESC(SYS_PMSDSFR_EL1), undef_access }, 3538 /* PMBIDR_EL1 is not trapped */ 3539 3540 { PMU_SYS_REG(PMINTENSET_EL1), 3541 .access = access_pminten, .reg = PMINTENSET_EL1, 3542 .get_user = get_pmreg, .set_user = set_pmreg }, 3543 { PMU_SYS_REG(PMINTENCLR_EL1), 3544 .access = access_pminten, .reg = PMINTENSET_EL1, 3545 .get_user = get_pmreg, .set_user = set_pmreg }, 3546 { PMU_SYS_REG(PMMIR_EL1), .access = access_pmmir, .reset = NULL, 3547 .get_user = get_pmmir, .set_user = set_pmmir }, 3548 3549 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 }, 3550 { SYS_DESC(SYS_PIRE0_EL1), NULL, reset_unknown, PIRE0_EL1, 3551 .visibility = s1pie_visibility }, 3552 { SYS_DESC(SYS_PIR_EL1), NULL, reset_unknown, PIR_EL1, 3553 .visibility = s1pie_visibility }, 3554 { SYS_DESC(SYS_POR_EL1), NULL, reset_unknown, POR_EL1, 3555 .visibility = s1poe_visibility }, 3556 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 }, 3557 3558 { SYS_DESC(SYS_LORSA_EL1), trap_loregion }, 3559 { SYS_DESC(SYS_LOREA_EL1), trap_loregion }, 3560 { SYS_DESC(SYS_LORN_EL1), trap_loregion }, 3561 { SYS_DESC(SYS_LORC_EL1), trap_loregion }, 3562 { SYS_DESC(SYS_MPAMIDR_EL1), undef_access }, 3563 { SYS_DESC(SYS_LORID_EL1), trap_loregion }, 3564 3565 { SYS_DESC(SYS_MPAM1_EL1), undef_access }, 3566 { SYS_DESC(SYS_MPAM0_EL1), undef_access }, 3567 { SYS_DESC(SYS_MPAMSM_EL1), undef_access }, 3568 3569 { SYS_DESC(SYS_VBAR_EL1), access_rw, reset_val, VBAR_EL1, 0 }, 3570 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 }, 3571 3572 { SYS_DESC(SYS_ICC_IAR0_EL1), undef_access }, 3573 { SYS_DESC(SYS_ICC_EOIR0_EL1), undef_access }, 3574 { SYS_DESC(SYS_ICC_HPPIR0_EL1), undef_access }, 3575 { SYS_DESC(SYS_ICC_BPR0_EL1), undef_access }, 3576 { SYS_DESC(SYS_ICC_AP0R0_EL1), undef_access }, 3577 { SYS_DESC(SYS_ICC_AP0R1_EL1), undef_access }, 3578 { SYS_DESC(SYS_ICC_AP0R2_EL1), undef_access }, 3579 { SYS_DESC(SYS_ICC_AP0R3_EL1), undef_access }, 3580 { SYS_DESC(SYS_ICC_AP1R0_EL1), undef_access }, 3581 { SYS_DESC(SYS_ICC_AP1R1_EL1), undef_access }, 3582 { SYS_DESC(SYS_ICC_AP1R2_EL1), undef_access }, 3583 { SYS_DESC(SYS_ICC_AP1R3_EL1), undef_access }, 3584 { SYS_DESC(SYS_ICC_IDR0_EL1), access_gicv5_idr0 }, 3585 { SYS_DESC(SYS_ICC_IAFFIDR_EL1), access_gicv5_iaffid }, 3586 { SYS_DESC(SYS_ICC_PPI_ENABLER0_EL1), access_gicv5_ppi_enabler }, 3587 { SYS_DESC(SYS_ICC_PPI_ENABLER1_EL1), access_gicv5_ppi_enabler }, 3588 { SYS_DESC(SYS_ICC_DIR_EL1), access_gic_dir }, 3589 { SYS_DESC(SYS_ICC_RPR_EL1), undef_access }, 3590 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi }, 3591 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi }, 3592 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi }, 3593 { SYS_DESC(SYS_ICC_IAR1_EL1), undef_access }, 3594 { SYS_DESC(SYS_ICC_EOIR1_EL1), undef_access }, 3595 { SYS_DESC(SYS_ICC_HPPIR1_EL1), undef_access }, 3596 { SYS_DESC(SYS_ICC_BPR1_EL1), undef_access }, 3597 { SYS_DESC(SYS_ICC_CTLR_EL1), undef_access }, 3598 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre }, 3599 { SYS_DESC(SYS_ICC_IGRPEN0_EL1), undef_access }, 3600 { SYS_DESC(SYS_ICC_IGRPEN1_EL1), undef_access }, 3601 3602 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 }, 3603 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 }, 3604 3605 { SYS_DESC(SYS_ACCDATA_EL1), undef_access }, 3606 3607 { SYS_DESC(SYS_SCXTNUM_EL1), undef_access }, 3608 3609 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0}, 3610 3611 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr }, 3612 { SYS_DESC(SYS_CLIDR_EL1), access_clidr, reset_clidr, CLIDR_EL1, 3613 .set_user = set_clidr, .val = ~CLIDR_EL1_RES0 }, 3614 IMPLEMENTATION_ID(AIDR_EL1, GENMASK_ULL(63, 0)), 3615 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, 3616 ID_FILTERED(CTR_EL0, ctr_el0, 3617 CTR_EL0_DIC_MASK | 3618 CTR_EL0_IDC_MASK | 3619 CTR_EL0_DminLine_MASK | 3620 CTR_EL0_L1Ip_MASK | 3621 CTR_EL0_IminLine_MASK), 3622 { SYS_DESC(SYS_SVCR), undef_access, reset_val, SVCR, 0, .visibility = sme_visibility }, 3623 { SYS_DESC(SYS_FPMR), undef_access, reset_val, FPMR, 0, .visibility = fp8_visibility }, 3624 3625 { PMU_SYS_REG(PMCR_EL0), .access = access_pmcr, .reset = reset_pmcr, 3626 .reg = PMCR_EL0, .get_user = get_pmcr, .set_user = set_pmcr }, 3627 { PMU_SYS_REG(PMCNTENSET_EL0), 3628 .access = access_pmcnten, .reg = PMCNTENSET_EL0, 3629 .get_user = get_pmreg, .set_user = set_pmreg }, 3630 { PMU_SYS_REG(PMCNTENCLR_EL0), 3631 .access = access_pmcnten, .reg = PMCNTENSET_EL0, 3632 .get_user = get_pmreg, .set_user = set_pmreg }, 3633 { PMU_SYS_REG(PMOVSCLR_EL0), 3634 .access = access_pmovs, .reg = PMOVSSET_EL0, 3635 .get_user = get_pmreg, .set_user = set_pmreg }, 3636 /* 3637 * PM_SWINC_EL0 is exposed to userspace as RAZ/WI, as it was 3638 * previously (and pointlessly) advertised in the past... 3639 */ 3640 { PMU_SYS_REG(PMSWINC_EL0), 3641 .get_user = get_raz_reg, .set_user = set_wi_reg, 3642 .access = access_pmswinc, .reset = NULL }, 3643 { PMU_SYS_REG(PMSELR_EL0), 3644 .access = access_pmselr, .reset = reset_pmselr, .reg = PMSELR_EL0 }, 3645 { PMU_SYS_REG(PMCEID0_EL0), 3646 .access = access_pmceid, .reset = NULL }, 3647 { PMU_SYS_REG(PMCEID1_EL0), 3648 .access = access_pmceid, .reset = NULL }, 3649 { PMU_SYS_REG(PMCCNTR_EL0), 3650 .access = access_pmu_evcntr, .reset = reset_unknown, 3651 .reg = PMCCNTR_EL0, .get_user = get_pmu_evcntr, 3652 .set_user = set_pmu_evcntr }, 3653 { PMU_SYS_REG(PMXEVTYPER_EL0), 3654 .access = access_pmu_evtyper, .reset = NULL }, 3655 { PMU_SYS_REG(PMXEVCNTR_EL0), 3656 .access = access_pmu_evcntr, .reset = NULL }, 3657 /* 3658 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero 3659 * in 32bit mode. Here we choose to reset it as zero for consistency. 3660 */ 3661 { PMU_SYS_REG(PMUSERENR_EL0), .access = access_pmuserenr, 3662 .reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 }, 3663 { PMU_SYS_REG(PMOVSSET_EL0), 3664 .access = access_pmovs, .reg = PMOVSSET_EL0, 3665 .get_user = get_pmreg, .set_user = set_pmreg }, 3666 3667 { SYS_DESC(SYS_POR_EL0), NULL, reset_unknown, POR_EL0, 3668 .visibility = s1poe_visibility }, 3669 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 }, 3670 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 }, 3671 { SYS_DESC(SYS_TPIDR2_EL0), undef_access }, 3672 3673 { SYS_DESC(SYS_SCXTNUM_EL0), undef_access }, 3674 3675 { SYS_DESC(SYS_AMCR_EL0), undef_access }, 3676 { SYS_DESC(SYS_AMCFGR_EL0), undef_access }, 3677 { SYS_DESC(SYS_AMCGCR_EL0), undef_access }, 3678 { SYS_DESC(SYS_AMUSERENR_EL0), undef_access }, 3679 { SYS_DESC(SYS_AMCNTENCLR0_EL0), undef_access }, 3680 { SYS_DESC(SYS_AMCNTENSET0_EL0), undef_access }, 3681 { SYS_DESC(SYS_AMCNTENCLR1_EL0), undef_access }, 3682 { SYS_DESC(SYS_AMCNTENSET1_EL0), undef_access }, 3683 AMU_AMEVCNTR0_EL0(0), 3684 AMU_AMEVCNTR0_EL0(1), 3685 AMU_AMEVCNTR0_EL0(2), 3686 AMU_AMEVCNTR0_EL0(3), 3687 AMU_AMEVCNTR0_EL0(4), 3688 AMU_AMEVCNTR0_EL0(5), 3689 AMU_AMEVCNTR0_EL0(6), 3690 AMU_AMEVCNTR0_EL0(7), 3691 AMU_AMEVCNTR0_EL0(8), 3692 AMU_AMEVCNTR0_EL0(9), 3693 AMU_AMEVCNTR0_EL0(10), 3694 AMU_AMEVCNTR0_EL0(11), 3695 AMU_AMEVCNTR0_EL0(12), 3696 AMU_AMEVCNTR0_EL0(13), 3697 AMU_AMEVCNTR0_EL0(14), 3698 AMU_AMEVCNTR0_EL0(15), 3699 AMU_AMEVTYPER0_EL0(0), 3700 AMU_AMEVTYPER0_EL0(1), 3701 AMU_AMEVTYPER0_EL0(2), 3702 AMU_AMEVTYPER0_EL0(3), 3703 AMU_AMEVTYPER0_EL0(4), 3704 AMU_AMEVTYPER0_EL0(5), 3705 AMU_AMEVTYPER0_EL0(6), 3706 AMU_AMEVTYPER0_EL0(7), 3707 AMU_AMEVTYPER0_EL0(8), 3708 AMU_AMEVTYPER0_EL0(9), 3709 AMU_AMEVTYPER0_EL0(10), 3710 AMU_AMEVTYPER0_EL0(11), 3711 AMU_AMEVTYPER0_EL0(12), 3712 AMU_AMEVTYPER0_EL0(13), 3713 AMU_AMEVTYPER0_EL0(14), 3714 AMU_AMEVTYPER0_EL0(15), 3715 AMU_AMEVCNTR1_EL0(0), 3716 AMU_AMEVCNTR1_EL0(1), 3717 AMU_AMEVCNTR1_EL0(2), 3718 AMU_AMEVCNTR1_EL0(3), 3719 AMU_AMEVCNTR1_EL0(4), 3720 AMU_AMEVCNTR1_EL0(5), 3721 AMU_AMEVCNTR1_EL0(6), 3722 AMU_AMEVCNTR1_EL0(7), 3723 AMU_AMEVCNTR1_EL0(8), 3724 AMU_AMEVCNTR1_EL0(9), 3725 AMU_AMEVCNTR1_EL0(10), 3726 AMU_AMEVCNTR1_EL0(11), 3727 AMU_AMEVCNTR1_EL0(12), 3728 AMU_AMEVCNTR1_EL0(13), 3729 AMU_AMEVCNTR1_EL0(14), 3730 AMU_AMEVCNTR1_EL0(15), 3731 AMU_AMEVTYPER1_EL0(0), 3732 AMU_AMEVTYPER1_EL0(1), 3733 AMU_AMEVTYPER1_EL0(2), 3734 AMU_AMEVTYPER1_EL0(3), 3735 AMU_AMEVTYPER1_EL0(4), 3736 AMU_AMEVTYPER1_EL0(5), 3737 AMU_AMEVTYPER1_EL0(6), 3738 AMU_AMEVTYPER1_EL0(7), 3739 AMU_AMEVTYPER1_EL0(8), 3740 AMU_AMEVTYPER1_EL0(9), 3741 AMU_AMEVTYPER1_EL0(10), 3742 AMU_AMEVTYPER1_EL0(11), 3743 AMU_AMEVTYPER1_EL0(12), 3744 AMU_AMEVTYPER1_EL0(13), 3745 AMU_AMEVTYPER1_EL0(14), 3746 AMU_AMEVTYPER1_EL0(15), 3747 3748 { SYS_DESC(SYS_CNTPCT_EL0), .access = access_arch_timer, 3749 .get_user = arch_timer_get_user, .set_user = arch_timer_set_user }, 3750 { SYS_DESC(SYS_CNTVCT_EL0), .access = access_arch_timer, 3751 .get_user = arch_timer_get_user, .set_user = arch_timer_set_user }, 3752 { SYS_DESC(SYS_CNTPCTSS_EL0), access_arch_timer }, 3753 { SYS_DESC(SYS_CNTVCTSS_EL0), access_arch_timer }, 3754 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer }, 3755 TIMER_REG(CNTP_CTL_EL0, NULL), 3756 TIMER_REG(CNTP_CVAL_EL0, NULL), 3757 3758 { SYS_DESC(SYS_CNTV_TVAL_EL0), access_arch_timer }, 3759 TIMER_REG(CNTV_CTL_EL0, NULL), 3760 TIMER_REG(CNTV_CVAL_EL0, NULL), 3761 3762 /* PMEVCNTRn_EL0 */ 3763 PMU_PMEVCNTR_EL0(0), 3764 PMU_PMEVCNTR_EL0(1), 3765 PMU_PMEVCNTR_EL0(2), 3766 PMU_PMEVCNTR_EL0(3), 3767 PMU_PMEVCNTR_EL0(4), 3768 PMU_PMEVCNTR_EL0(5), 3769 PMU_PMEVCNTR_EL0(6), 3770 PMU_PMEVCNTR_EL0(7), 3771 PMU_PMEVCNTR_EL0(8), 3772 PMU_PMEVCNTR_EL0(9), 3773 PMU_PMEVCNTR_EL0(10), 3774 PMU_PMEVCNTR_EL0(11), 3775 PMU_PMEVCNTR_EL0(12), 3776 PMU_PMEVCNTR_EL0(13), 3777 PMU_PMEVCNTR_EL0(14), 3778 PMU_PMEVCNTR_EL0(15), 3779 PMU_PMEVCNTR_EL0(16), 3780 PMU_PMEVCNTR_EL0(17), 3781 PMU_PMEVCNTR_EL0(18), 3782 PMU_PMEVCNTR_EL0(19), 3783 PMU_PMEVCNTR_EL0(20), 3784 PMU_PMEVCNTR_EL0(21), 3785 PMU_PMEVCNTR_EL0(22), 3786 PMU_PMEVCNTR_EL0(23), 3787 PMU_PMEVCNTR_EL0(24), 3788 PMU_PMEVCNTR_EL0(25), 3789 PMU_PMEVCNTR_EL0(26), 3790 PMU_PMEVCNTR_EL0(27), 3791 PMU_PMEVCNTR_EL0(28), 3792 PMU_PMEVCNTR_EL0(29), 3793 PMU_PMEVCNTR_EL0(30), 3794 /* PMEVTYPERn_EL0 */ 3795 PMU_PMEVTYPER_EL0(0), 3796 PMU_PMEVTYPER_EL0(1), 3797 PMU_PMEVTYPER_EL0(2), 3798 PMU_PMEVTYPER_EL0(3), 3799 PMU_PMEVTYPER_EL0(4), 3800 PMU_PMEVTYPER_EL0(5), 3801 PMU_PMEVTYPER_EL0(6), 3802 PMU_PMEVTYPER_EL0(7), 3803 PMU_PMEVTYPER_EL0(8), 3804 PMU_PMEVTYPER_EL0(9), 3805 PMU_PMEVTYPER_EL0(10), 3806 PMU_PMEVTYPER_EL0(11), 3807 PMU_PMEVTYPER_EL0(12), 3808 PMU_PMEVTYPER_EL0(13), 3809 PMU_PMEVTYPER_EL0(14), 3810 PMU_PMEVTYPER_EL0(15), 3811 PMU_PMEVTYPER_EL0(16), 3812 PMU_PMEVTYPER_EL0(17), 3813 PMU_PMEVTYPER_EL0(18), 3814 PMU_PMEVTYPER_EL0(19), 3815 PMU_PMEVTYPER_EL0(20), 3816 PMU_PMEVTYPER_EL0(21), 3817 PMU_PMEVTYPER_EL0(22), 3818 PMU_PMEVTYPER_EL0(23), 3819 PMU_PMEVTYPER_EL0(24), 3820 PMU_PMEVTYPER_EL0(25), 3821 PMU_PMEVTYPER_EL0(26), 3822 PMU_PMEVTYPER_EL0(27), 3823 PMU_PMEVTYPER_EL0(28), 3824 PMU_PMEVTYPER_EL0(29), 3825 PMU_PMEVTYPER_EL0(30), 3826 /* 3827 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero 3828 * in 32bit mode. Here we choose to reset it as zero for consistency. 3829 */ 3830 { PMU_SYS_REG(PMCCFILTR_EL0), .access = access_pmu_evtyper, 3831 .reset = reset_val, .reg = PMCCFILTR_EL0, .val = 0 }, 3832 3833 EL2_REG_VNCR(VPIDR_EL2, reset_unknown, 0), 3834 EL2_REG_VNCR(VMPIDR_EL2, reset_unknown, 0), 3835 EL2_REG(SCTLR_EL2, access_rw, reset_val, SCTLR_EL2_RES1), 3836 EL2_REG(ACTLR_EL2, access_rw, reset_val, 0), 3837 EL2_REG_FILTERED(SCTLR2_EL2, access_vm_reg, reset_val, 0, 3838 sctlr2_el2_visibility), 3839 EL2_REG_VNCR(HCR_EL2, reset_hcr, 0), 3840 EL2_REG(MDCR_EL2, access_mdcr, reset_mdcr, 0), 3841 EL2_REG(CPTR_EL2, access_rw, reset_val, CPTR_NVHE_EL2_RES1), 3842 EL2_REG_VNCR(HSTR_EL2, reset_val, 0), 3843 EL2_REG_VNCR_FILT(HFGRTR_EL2, fgt_visibility), 3844 EL2_REG_VNCR_FILT(HFGWTR_EL2, fgt_visibility), 3845 EL2_REG_VNCR(HFGITR_EL2, reset_val, 0), 3846 EL2_REG_VNCR(HACR_EL2, reset_val, 0), 3847 3848 EL2_REG_FILTERED(ZCR_EL2, access_zcr_el2, reset_val, 0, 3849 sve_el2_visibility), 3850 3851 EL2_REG_VNCR(HCRX_EL2, reset_val, 0), 3852 EL2_REG_FILTERED(NVHCR_EL2, undef_access, reset_val, 0, 3853 nvhcr_el2_visibility), 3854 3855 EL2_REG(TTBR0_EL2, access_rw, reset_val, 0), 3856 EL2_REG(TTBR1_EL2, access_rw, reset_val, 0), 3857 EL2_REG(TCR_EL2, access_rw, reset_val, TCR_EL2_RES1), 3858 EL2_REG_FILTERED(TCR2_EL2, access_rw, reset_val, TCR2_EL2_RES1, 3859 tcr2_el2_visibility), 3860 EL2_REG_VNCR(VTTBR_EL2, reset_val, 0), 3861 EL2_REG_VNCR(VTCR_EL2, reset_val, 0), 3862 EL2_REG_FILTERED(VNCR_EL2, bad_vncr_trap, reset_val, 0, 3863 vncr_el2_visibility), 3864 3865 { SYS_DESC(SYS_DACR32_EL2), undef_access, reset_unknown, DACR32_EL2 }, 3866 EL2_REG_VNCR_FILT(HDFGRTR2_EL2, fgt2_visibility), 3867 EL2_REG_VNCR_FILT(HDFGWTR2_EL2, fgt2_visibility), 3868 EL2_REG_VNCR_FILT(HFGRTR2_EL2, fgt2_visibility), 3869 EL2_REG_VNCR_FILT(HFGWTR2_EL2, fgt2_visibility), 3870 EL2_REG_VNCR_FILT(HDFGRTR_EL2, fgt_visibility), 3871 EL2_REG_VNCR_FILT(HDFGWTR_EL2, fgt_visibility), 3872 EL2_REG_VNCR_FILT(HAFGRTR_EL2, fgt_visibility), 3873 EL2_REG_VNCR_FILT(HFGITR2_EL2, fgt2_visibility), 3874 EL2_REG_REDIR(SPSR_EL2, reset_val, 0), 3875 EL2_REG_REDIR(ELR_EL2, reset_val, 0), 3876 { SYS_DESC(SYS_SP_EL1), access_sp_el1}, 3877 3878 /* AArch32 SPSR_* are RES0 if trapped from a NV guest */ 3879 { SYS_DESC(SYS_SPSR_irq), .access = trap_raz_wi }, 3880 { SYS_DESC(SYS_SPSR_abt), .access = trap_raz_wi }, 3881 { SYS_DESC(SYS_SPSR_und), .access = trap_raz_wi }, 3882 { SYS_DESC(SYS_SPSR_fiq), .access = trap_raz_wi }, 3883 3884 { SYS_DESC(SYS_IFSR32_EL2), undef_access, reset_unknown, IFSR32_EL2 }, 3885 EL2_REG(AFSR0_EL2, access_rw, reset_val, 0), 3886 EL2_REG(AFSR1_EL2, access_rw, reset_val, 0), 3887 EL2_REG_REDIR(ESR_EL2, reset_val, 0), 3888 EL2_REG_VNCR(VSESR_EL2, reset_unknown, 0), 3889 { SYS_DESC(SYS_FPEXC32_EL2), undef_access, reset_val, FPEXC32_EL2, 0x700 }, 3890 3891 EL2_REG_REDIR(FAR_EL2, reset_val, 0), 3892 EL2_REG(HPFAR_EL2, access_rw, reset_val, 0), 3893 3894 EL2_REG(MAIR_EL2, access_rw, reset_val, 0), 3895 EL2_REG_FILTERED(PIRE0_EL2, access_rw, reset_val, 0, 3896 s1pie_el2_visibility), 3897 EL2_REG_FILTERED(PIR_EL2, access_rw, reset_val, 0, 3898 s1pie_el2_visibility), 3899 EL2_REG_FILTERED(POR_EL2, access_rw, reset_val, 0, 3900 s1poe_el2_visibility), 3901 EL2_REG(AMAIR_EL2, access_rw, reset_val, 0), 3902 { SYS_DESC(SYS_MPAMHCR_EL2), undef_access }, 3903 { SYS_DESC(SYS_MPAMVPMV_EL2), undef_access }, 3904 { SYS_DESC(SYS_MPAM2_EL2), undef_access }, 3905 { SYS_DESC(SYS_MPAMVPM0_EL2), undef_access }, 3906 { SYS_DESC(SYS_MPAMVPM1_EL2), undef_access }, 3907 { SYS_DESC(SYS_MPAMVPM2_EL2), undef_access }, 3908 { SYS_DESC(SYS_MPAMVPM3_EL2), undef_access }, 3909 { SYS_DESC(SYS_MPAMVPM4_EL2), undef_access }, 3910 { SYS_DESC(SYS_MPAMVPM5_EL2), undef_access }, 3911 { SYS_DESC(SYS_MPAMVPM6_EL2), undef_access }, 3912 { SYS_DESC(SYS_MPAMVPM7_EL2), undef_access }, 3913 3914 EL2_REG(VBAR_EL2, access_rw, reset_val, 0), 3915 { SYS_DESC(SYS_RVBAR_EL2), undef_access }, 3916 { SYS_DESC(SYS_RMR_EL2), undef_access }, 3917 EL2_REG_VNCR(VDISR_EL2, reset_unknown, 0), 3918 3919 EL2_REG_VNCR_GICv3(ICH_AP0R0_EL2), 3920 EL2_REG_VNCR_GICv3(ICH_AP0R1_EL2), 3921 EL2_REG_VNCR_GICv3(ICH_AP0R2_EL2), 3922 EL2_REG_VNCR_GICv3(ICH_AP0R3_EL2), 3923 EL2_REG_VNCR_GICv3(ICH_AP1R0_EL2), 3924 EL2_REG_VNCR_GICv3(ICH_AP1R1_EL2), 3925 EL2_REG_VNCR_GICv3(ICH_AP1R2_EL2), 3926 EL2_REG_VNCR_GICv3(ICH_AP1R3_EL2), 3927 3928 { SYS_DESC(SYS_ICC_SRE_EL2), access_gic_sre }, 3929 3930 EL2_REG_VNCR_GICv3(ICH_HCR_EL2), 3931 { SYS_DESC(SYS_ICH_VTR_EL2), access_gic_vtr }, 3932 { SYS_DESC(SYS_ICH_MISR_EL2), access_gic_misr }, 3933 { SYS_DESC(SYS_ICH_EISR_EL2), access_gic_eisr }, 3934 { SYS_DESC(SYS_ICH_ELRSR_EL2), access_gic_elrsr }, 3935 EL2_REG_VNCR_GICv3(ICH_VMCR_EL2), 3936 3937 EL2_REG_VNCR_GICv3(ICH_LR0_EL2), 3938 EL2_REG_VNCR_GICv3(ICH_LR1_EL2), 3939 EL2_REG_VNCR_GICv3(ICH_LR2_EL2), 3940 EL2_REG_VNCR_GICv3(ICH_LR3_EL2), 3941 EL2_REG_VNCR_GICv3(ICH_LR4_EL2), 3942 EL2_REG_VNCR_GICv3(ICH_LR5_EL2), 3943 EL2_REG_VNCR_GICv3(ICH_LR6_EL2), 3944 EL2_REG_VNCR_GICv3(ICH_LR7_EL2), 3945 EL2_REG_VNCR_GICv3(ICH_LR8_EL2), 3946 EL2_REG_VNCR_GICv3(ICH_LR9_EL2), 3947 EL2_REG_VNCR_GICv3(ICH_LR10_EL2), 3948 EL2_REG_VNCR_GICv3(ICH_LR11_EL2), 3949 EL2_REG_VNCR_GICv3(ICH_LR12_EL2), 3950 EL2_REG_VNCR_GICv3(ICH_LR13_EL2), 3951 EL2_REG_VNCR_GICv3(ICH_LR14_EL2), 3952 EL2_REG_VNCR_GICv3(ICH_LR15_EL2), 3953 3954 EL2_REG(CONTEXTIDR_EL2, access_rw, reset_val, 0), 3955 EL2_REG(TPIDR_EL2, access_rw, reset_val, 0), 3956 3957 EL2_REG_VNCR(CNTVOFF_EL2, reset_val, 0), 3958 EL2_REG(CNTHCTL_EL2, access_rw, reset_val, 0), 3959 { SYS_DESC(SYS_CNTHP_TVAL_EL2), access_arch_timer }, 3960 TIMER_REG(CNTHP_CTL_EL2, el2_visibility), 3961 TIMER_REG(CNTHP_CVAL_EL2, el2_visibility), 3962 3963 { SYS_DESC(SYS_CNTHV_TVAL_EL2), access_arch_timer, .visibility = cnthv_visibility }, 3964 TIMER_REG(CNTHV_CTL_EL2, cnthv_visibility), 3965 TIMER_REG(CNTHV_CVAL_EL2, cnthv_visibility), 3966 3967 { SYS_DESC(SYS_CNTKCTL_EL12), access_cntkctl_el12 }, 3968 3969 { SYS_DESC(SYS_CNTP_TVAL_EL02), access_arch_timer }, 3970 { SYS_DESC(SYS_CNTP_CTL_EL02), access_arch_timer }, 3971 { SYS_DESC(SYS_CNTP_CVAL_EL02), access_arch_timer }, 3972 3973 { SYS_DESC(SYS_CNTV_TVAL_EL02), access_arch_timer }, 3974 { SYS_DESC(SYS_CNTV_CTL_EL02), access_arch_timer }, 3975 { SYS_DESC(SYS_CNTV_CVAL_EL02), access_arch_timer }, 3976 3977 EL2_REG(SP_EL2, NULL, reset_unknown, 0), 3978 }; 3979 3980 static bool handle_at_s1e01(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3981 const struct sys_reg_desc *r) 3982 { 3983 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3984 3985 if (__kvm_at_s1e01(vcpu, op, p->regval)) 3986 return false; 3987 3988 return true; 3989 } 3990 3991 static bool handle_at_s1e2(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3992 const struct sys_reg_desc *r) 3993 { 3994 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3995 3996 /* There is no FGT associated with AT S1E2A :-( */ 3997 if (op == OP_AT_S1E2A && 3998 !kvm_has_feat(vcpu->kvm, ID_AA64ISAR2_EL1, ATS1A, IMP)) { 3999 kvm_inject_undefined(vcpu); 4000 return false; 4001 } 4002 4003 if (__kvm_at_s1e2(vcpu, op, p->regval)) 4004 return false; 4005 4006 return true; 4007 } 4008 4009 static bool handle_at_s12(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 4010 const struct sys_reg_desc *r) 4011 { 4012 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 4013 4014 if (__kvm_at_s12(vcpu, op, p->regval)) 4015 return false; 4016 4017 return true; 4018 } 4019 4020 static bool kvm_supported_tlbi_s12_op(struct kvm_vcpu *vpcu, u32 instr) 4021 { 4022 struct kvm *kvm = vpcu->kvm; 4023 u8 CRm = sys_reg_CRm(instr); 4024 4025 if (sys_reg_CRn(instr) == TLBI_CRn_nXS && 4026 !kvm_has_feat(kvm, ID_AA64ISAR1_EL1, XS, IMP)) 4027 return false; 4028 4029 if (CRm == TLBI_CRm_nROS && 4030 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 4031 return false; 4032 4033 return true; 4034 } 4035 4036 static bool handle_alle1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 4037 const struct sys_reg_desc *r) 4038 { 4039 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 4040 4041 if (!kvm_supported_tlbi_s12_op(vcpu, sys_encoding)) 4042 return undef_access(vcpu, p, r); 4043 4044 write_lock(&vcpu->kvm->mmu_lock); 4045 4046 /* 4047 * Drop all shadow S2s, resulting in S1/S2 TLBIs for each of the 4048 * corresponding VMIDs. 4049 */ 4050 kvm_nested_s2_unmap(vcpu->kvm, true); 4051 4052 write_unlock(&vcpu->kvm->mmu_lock); 4053 4054 return true; 4055 } 4056 4057 static bool kvm_supported_tlbi_ipas2_op(struct kvm_vcpu *vpcu, u32 instr) 4058 { 4059 struct kvm *kvm = vpcu->kvm; 4060 u8 CRm = sys_reg_CRm(instr); 4061 u8 Op2 = sys_reg_Op2(instr); 4062 4063 if (sys_reg_CRn(instr) == TLBI_CRn_nXS && 4064 !kvm_has_feat(kvm, ID_AA64ISAR1_EL1, XS, IMP)) 4065 return false; 4066 4067 if (CRm == TLBI_CRm_IPAIS && (Op2 == 2 || Op2 == 6) && 4068 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE)) 4069 return false; 4070 4071 if (CRm == TLBI_CRm_IPAONS && (Op2 == 0 || Op2 == 4) && 4072 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 4073 return false; 4074 4075 if (CRm == TLBI_CRm_IPAONS && (Op2 == 3 || Op2 == 7) && 4076 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE)) 4077 return false; 4078 4079 return true; 4080 } 4081 4082 /* Only defined here as this is an internal "abstraction" */ 4083 union tlbi_info { 4084 struct { 4085 u64 start; 4086 u64 size; 4087 } range; 4088 4089 struct { 4090 u64 addr; 4091 } ipa; 4092 4093 struct { 4094 u64 addr; 4095 u32 encoding; 4096 } va; 4097 }; 4098 4099 static void s2_mmu_unmap_range(struct kvm_s2_mmu *mmu, 4100 const union tlbi_info *info) 4101 { 4102 /* 4103 * The unmap operation is allowed to drop the MMU lock and block, which 4104 * means that @mmu could be used for a different context than the one 4105 * currently being invalidated. 4106 * 4107 * This behavior is still safe, as: 4108 * 4109 * 1) The vCPU(s) that recycled the MMU are responsible for invalidating 4110 * the entire MMU before reusing it, which still honors the intent 4111 * of a TLBI. 4112 * 4113 * 2) Until the guest TLBI instruction is 'retired' (i.e. increment PC 4114 * and ERET to the guest), other vCPUs are allowed to use stale 4115 * translations. 4116 * 4117 * 3) Accidentally unmapping an unrelated MMU context is nonfatal, and 4118 * at worst may cause more aborts for shadow stage-2 fills. 4119 * 4120 * Dropping the MMU lock also implies that shadow stage-2 fills could 4121 * happen behind the back of the TLBI. This is still safe, though, as 4122 * the L1 needs to put its stage-2 in a consistent state before doing 4123 * the TLBI. 4124 */ 4125 kvm_stage2_unmap_range(mmu, info->range.start, info->range.size, true); 4126 } 4127 4128 static bool handle_vmalls12e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 4129 const struct sys_reg_desc *r) 4130 { 4131 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 4132 u64 limit, vttbr; 4133 4134 if (!kvm_supported_tlbi_s12_op(vcpu, sys_encoding)) 4135 return undef_access(vcpu, p, r); 4136 4137 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 4138 limit = BIT_ULL(kvm_get_pa_bits(vcpu->kvm)); 4139 4140 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 4141 &(union tlbi_info) { 4142 .range = { 4143 .start = 0, 4144 .size = limit, 4145 }, 4146 }, 4147 s2_mmu_unmap_range); 4148 4149 return true; 4150 } 4151 4152 static bool handle_ripas2e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 4153 const struct sys_reg_desc *r) 4154 { 4155 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 4156 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 4157 u64 base, range; 4158 int pa_bits; 4159 4160 if (!kvm_supported_tlbi_ipas2_op(vcpu, sys_encoding)) 4161 return undef_access(vcpu, p, r); 4162 4163 /* 4164 * Because the shadow S2 structure doesn't necessarily reflect that 4165 * of the guest's S2 (different base granule size, for example), we 4166 * decide to ignore TTL and only use the described range. 4167 */ 4168 base = decode_range_tlbi(p->regval, &range, NULL); 4169 4170 /* 4171 * Ignore TLBIs that start out of PA_bits range, and cap the 4172 * invalidation to the [base:bit(PA_bits)] interval. 4173 */ 4174 pa_bits = kvm_get_pa_bits(vcpu->kvm); 4175 if (fls64(base) > pa_bits) 4176 return true; 4177 4178 range = min(range, BIT_ULL(pa_bits) - base); 4179 4180 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 4181 &(union tlbi_info) { 4182 .range = { 4183 .start = base, 4184 .size = range, 4185 }, 4186 }, 4187 s2_mmu_unmap_range); 4188 4189 return true; 4190 } 4191 4192 static void s2_mmu_unmap_ipa(struct kvm_s2_mmu *mmu, 4193 const union tlbi_info *info) 4194 { 4195 unsigned long max_size; 4196 u64 base_addr; 4197 4198 /* 4199 * We drop a number of things from the supplied value: 4200 * 4201 * - NS bit: we're non-secure only. 4202 * 4203 * - IPA[51:48]: We don't support 52bit IPA just yet... 4204 * 4205 * And of course, adjust the IPA to be on an actual address. 4206 */ 4207 base_addr = (info->ipa.addr & GENMASK_ULL(35, 0)) << 12; 4208 max_size = compute_tlb_inval_range(mmu, info->ipa.addr); 4209 base_addr &= ~(max_size - 1); 4210 4211 /* 4212 * See comment in s2_mmu_unmap_range() for why this is allowed to 4213 * reschedule. 4214 */ 4215 kvm_stage2_unmap_range(mmu, base_addr, max_size, true); 4216 } 4217 4218 static bool handle_ipas2e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 4219 const struct sys_reg_desc *r) 4220 { 4221 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 4222 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 4223 4224 if (!kvm_supported_tlbi_ipas2_op(vcpu, sys_encoding)) 4225 return undef_access(vcpu, p, r); 4226 4227 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 4228 &(union tlbi_info) { 4229 .ipa = { 4230 .addr = p->regval, 4231 }, 4232 }, 4233 s2_mmu_unmap_ipa); 4234 4235 return true; 4236 } 4237 4238 static void s2_mmu_tlbi_s1e1(struct kvm_s2_mmu *mmu, 4239 const union tlbi_info *info) 4240 { 4241 WARN_ON(__kvm_tlbi_s1e2(mmu, info->va.addr, info->va.encoding)); 4242 } 4243 4244 static bool handle_tlbi_el2(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 4245 const struct sys_reg_desc *r) 4246 { 4247 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 4248 4249 if (!kvm_supported_tlbi_s1e2_op(vcpu, sys_encoding)) 4250 return undef_access(vcpu, p, r); 4251 4252 kvm_handle_s1e2_tlbi(vcpu, sys_encoding, p->regval); 4253 return true; 4254 } 4255 4256 static bool handle_tlbi_el1(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 4257 const struct sys_reg_desc *r) 4258 { 4259 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 4260 4261 /* 4262 * If we're here, this is because we've trapped on a EL1 TLBI 4263 * instruction that affects the EL1 translation regime while 4264 * we're running in a context that doesn't allow us to let the 4265 * HW do its thing (aka vEL2): 4266 * 4267 * - HCR_EL2.E2H == 0 : a non-VHE guest 4268 * - HCR_EL2.{E2H,TGE} == { 1, 0 } : a VHE guest in guest mode 4269 * 4270 * Another possibility is that we are invalidating the EL2 context 4271 * using EL1 instructions, but that we landed here because we need 4272 * additional invalidation for structures that are not held in the 4273 * CPU TLBs (such as the VNCR pseudo-TLB and its EL2 mapping). In 4274 * that case, we are guaranteed that HCR_EL2.{E2H,TGE} == { 1, 1 } 4275 * as we don't allow an NV-capable L1 in a nVHE configuration. 4276 * 4277 * We don't expect these helpers to ever be called when running 4278 * in a vEL1 context. 4279 */ 4280 4281 WARN_ON(!vcpu_is_el2(vcpu)); 4282 4283 if (!kvm_supported_tlbi_s1e1_op(vcpu, sys_encoding)) 4284 return undef_access(vcpu, p, r); 4285 4286 if (vcpu_el2_e2h_is_set(vcpu) && vcpu_el2_tge_is_set(vcpu)) { 4287 kvm_handle_s1e2_tlbi(vcpu, sys_encoding, p->regval); 4288 return true; 4289 } 4290 4291 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, 4292 get_vmid(__vcpu_sys_reg(vcpu, VTTBR_EL2)), 4293 &(union tlbi_info) { 4294 .va = { 4295 .addr = p->regval, 4296 .encoding = sys_encoding, 4297 }, 4298 }, 4299 s2_mmu_tlbi_s1e1); 4300 4301 return true; 4302 } 4303 4304 #define SYS_INSN(insn, access_fn) \ 4305 { \ 4306 SYS_DESC(OP_##insn), \ 4307 .access = (access_fn), \ 4308 } 4309 4310 static struct sys_reg_desc sys_insn_descs[] = { 4311 { SYS_DESC(SYS_DC_ISW), access_dcsw }, 4312 { SYS_DESC(SYS_DC_IGSW), access_dcgsw }, 4313 { SYS_DESC(SYS_DC_IGDSW), access_dcgsw }, 4314 4315 SYS_INSN(AT_S1E1R, handle_at_s1e01), 4316 SYS_INSN(AT_S1E1W, handle_at_s1e01), 4317 SYS_INSN(AT_S1E0R, handle_at_s1e01), 4318 SYS_INSN(AT_S1E0W, handle_at_s1e01), 4319 SYS_INSN(AT_S1E1RP, handle_at_s1e01), 4320 SYS_INSN(AT_S1E1WP, handle_at_s1e01), 4321 SYS_INSN(AT_S1E1A, handle_at_s1e01), 4322 4323 { SYS_DESC(SYS_DC_CSW), access_dcsw }, 4324 { SYS_DESC(SYS_DC_CGSW), access_dcgsw }, 4325 { SYS_DESC(SYS_DC_CGDSW), access_dcgsw }, 4326 { SYS_DESC(SYS_DC_CISW), access_dcsw }, 4327 { SYS_DESC(SYS_DC_CIGSW), access_dcgsw }, 4328 { SYS_DESC(SYS_DC_CIGDSW), access_dcgsw }, 4329 4330 SYS_INSN(TLBI_VMALLE1OS, handle_tlbi_el1), 4331 SYS_INSN(TLBI_VAE1OS, handle_tlbi_el1), 4332 SYS_INSN(TLBI_ASIDE1OS, handle_tlbi_el1), 4333 SYS_INSN(TLBI_VAAE1OS, handle_tlbi_el1), 4334 SYS_INSN(TLBI_VALE1OS, handle_tlbi_el1), 4335 SYS_INSN(TLBI_VAALE1OS, handle_tlbi_el1), 4336 4337 SYS_INSN(TLBI_RVAE1IS, handle_tlbi_el1), 4338 SYS_INSN(TLBI_RVAAE1IS, handle_tlbi_el1), 4339 SYS_INSN(TLBI_RVALE1IS, handle_tlbi_el1), 4340 SYS_INSN(TLBI_RVAALE1IS, handle_tlbi_el1), 4341 4342 SYS_INSN(TLBI_VMALLE1IS, handle_tlbi_el1), 4343 SYS_INSN(TLBI_VAE1IS, handle_tlbi_el1), 4344 SYS_INSN(TLBI_ASIDE1IS, handle_tlbi_el1), 4345 SYS_INSN(TLBI_VAAE1IS, handle_tlbi_el1), 4346 SYS_INSN(TLBI_VALE1IS, handle_tlbi_el1), 4347 SYS_INSN(TLBI_VAALE1IS, handle_tlbi_el1), 4348 4349 SYS_INSN(TLBI_RVAE1OS, handle_tlbi_el1), 4350 SYS_INSN(TLBI_RVAAE1OS, handle_tlbi_el1), 4351 SYS_INSN(TLBI_RVALE1OS, handle_tlbi_el1), 4352 SYS_INSN(TLBI_RVAALE1OS, handle_tlbi_el1), 4353 4354 SYS_INSN(TLBI_RVAE1, handle_tlbi_el1), 4355 SYS_INSN(TLBI_RVAAE1, handle_tlbi_el1), 4356 SYS_INSN(TLBI_RVALE1, handle_tlbi_el1), 4357 SYS_INSN(TLBI_RVAALE1, handle_tlbi_el1), 4358 4359 SYS_INSN(TLBI_VMALLE1, handle_tlbi_el1), 4360 SYS_INSN(TLBI_VAE1, handle_tlbi_el1), 4361 SYS_INSN(TLBI_ASIDE1, handle_tlbi_el1), 4362 SYS_INSN(TLBI_VAAE1, handle_tlbi_el1), 4363 SYS_INSN(TLBI_VALE1, handle_tlbi_el1), 4364 SYS_INSN(TLBI_VAALE1, handle_tlbi_el1), 4365 4366 SYS_INSN(TLBI_VMALLE1OSNXS, handle_tlbi_el1), 4367 SYS_INSN(TLBI_VAE1OSNXS, handle_tlbi_el1), 4368 SYS_INSN(TLBI_ASIDE1OSNXS, handle_tlbi_el1), 4369 SYS_INSN(TLBI_VAAE1OSNXS, handle_tlbi_el1), 4370 SYS_INSN(TLBI_VALE1OSNXS, handle_tlbi_el1), 4371 SYS_INSN(TLBI_VAALE1OSNXS, handle_tlbi_el1), 4372 4373 SYS_INSN(TLBI_RVAE1ISNXS, handle_tlbi_el1), 4374 SYS_INSN(TLBI_RVAAE1ISNXS, handle_tlbi_el1), 4375 SYS_INSN(TLBI_RVALE1ISNXS, handle_tlbi_el1), 4376 SYS_INSN(TLBI_RVAALE1ISNXS, handle_tlbi_el1), 4377 4378 SYS_INSN(TLBI_VMALLE1ISNXS, handle_tlbi_el1), 4379 SYS_INSN(TLBI_VAE1ISNXS, handle_tlbi_el1), 4380 SYS_INSN(TLBI_ASIDE1ISNXS, handle_tlbi_el1), 4381 SYS_INSN(TLBI_VAAE1ISNXS, handle_tlbi_el1), 4382 SYS_INSN(TLBI_VALE1ISNXS, handle_tlbi_el1), 4383 SYS_INSN(TLBI_VAALE1ISNXS, handle_tlbi_el1), 4384 4385 SYS_INSN(TLBI_RVAE1OSNXS, handle_tlbi_el1), 4386 SYS_INSN(TLBI_RVAAE1OSNXS, handle_tlbi_el1), 4387 SYS_INSN(TLBI_RVALE1OSNXS, handle_tlbi_el1), 4388 SYS_INSN(TLBI_RVAALE1OSNXS, handle_tlbi_el1), 4389 4390 SYS_INSN(TLBI_RVAE1NXS, handle_tlbi_el1), 4391 SYS_INSN(TLBI_RVAAE1NXS, handle_tlbi_el1), 4392 SYS_INSN(TLBI_RVALE1NXS, handle_tlbi_el1), 4393 SYS_INSN(TLBI_RVAALE1NXS, handle_tlbi_el1), 4394 4395 SYS_INSN(TLBI_VMALLE1NXS, handle_tlbi_el1), 4396 SYS_INSN(TLBI_VAE1NXS, handle_tlbi_el1), 4397 SYS_INSN(TLBI_ASIDE1NXS, handle_tlbi_el1), 4398 SYS_INSN(TLBI_VAAE1NXS, handle_tlbi_el1), 4399 SYS_INSN(TLBI_VALE1NXS, handle_tlbi_el1), 4400 SYS_INSN(TLBI_VAALE1NXS, handle_tlbi_el1), 4401 4402 SYS_INSN(AT_S1E2R, handle_at_s1e2), 4403 SYS_INSN(AT_S1E2W, handle_at_s1e2), 4404 SYS_INSN(AT_S12E1R, handle_at_s12), 4405 SYS_INSN(AT_S12E1W, handle_at_s12), 4406 SYS_INSN(AT_S12E0R, handle_at_s12), 4407 SYS_INSN(AT_S12E0W, handle_at_s12), 4408 SYS_INSN(AT_S1E2A, handle_at_s1e2), 4409 4410 SYS_INSN(TLBI_IPAS2E1IS, handle_ipas2e1is), 4411 SYS_INSN(TLBI_RIPAS2E1IS, handle_ripas2e1is), 4412 SYS_INSN(TLBI_IPAS2LE1IS, handle_ipas2e1is), 4413 SYS_INSN(TLBI_RIPAS2LE1IS, handle_ripas2e1is), 4414 4415 SYS_INSN(TLBI_ALLE2OS, handle_tlbi_el2), 4416 SYS_INSN(TLBI_VAE2OS, handle_tlbi_el2), 4417 SYS_INSN(TLBI_ALLE1OS, handle_alle1is), 4418 SYS_INSN(TLBI_VALE2OS, handle_tlbi_el2), 4419 SYS_INSN(TLBI_VMALLS12E1OS, handle_vmalls12e1is), 4420 4421 SYS_INSN(TLBI_RVAE2IS, handle_tlbi_el2), 4422 SYS_INSN(TLBI_RVALE2IS, handle_tlbi_el2), 4423 SYS_INSN(TLBI_ALLE2IS, handle_tlbi_el2), 4424 SYS_INSN(TLBI_VAE2IS, handle_tlbi_el2), 4425 4426 SYS_INSN(TLBI_ALLE1IS, handle_alle1is), 4427 4428 SYS_INSN(TLBI_VALE2IS, handle_tlbi_el2), 4429 4430 SYS_INSN(TLBI_VMALLS12E1IS, handle_vmalls12e1is), 4431 SYS_INSN(TLBI_IPAS2E1OS, handle_ipas2e1is), 4432 SYS_INSN(TLBI_IPAS2E1, handle_ipas2e1is), 4433 SYS_INSN(TLBI_RIPAS2E1, handle_ripas2e1is), 4434 SYS_INSN(TLBI_RIPAS2E1OS, handle_ripas2e1is), 4435 SYS_INSN(TLBI_IPAS2LE1OS, handle_ipas2e1is), 4436 SYS_INSN(TLBI_IPAS2LE1, handle_ipas2e1is), 4437 SYS_INSN(TLBI_RIPAS2LE1, handle_ripas2e1is), 4438 SYS_INSN(TLBI_RIPAS2LE1OS, handle_ripas2e1is), 4439 SYS_INSN(TLBI_RVAE2OS, handle_tlbi_el2), 4440 SYS_INSN(TLBI_RVALE2OS, handle_tlbi_el2), 4441 SYS_INSN(TLBI_RVAE2, handle_tlbi_el2), 4442 SYS_INSN(TLBI_RVALE2, handle_tlbi_el2), 4443 SYS_INSN(TLBI_ALLE2, handle_tlbi_el2), 4444 SYS_INSN(TLBI_VAE2, handle_tlbi_el2), 4445 4446 SYS_INSN(TLBI_ALLE1, handle_alle1is), 4447 4448 SYS_INSN(TLBI_VALE2, handle_tlbi_el2), 4449 4450 SYS_INSN(TLBI_VMALLS12E1, handle_vmalls12e1is), 4451 4452 SYS_INSN(TLBI_IPAS2E1ISNXS, handle_ipas2e1is), 4453 SYS_INSN(TLBI_RIPAS2E1ISNXS, handle_ripas2e1is), 4454 SYS_INSN(TLBI_IPAS2LE1ISNXS, handle_ipas2e1is), 4455 SYS_INSN(TLBI_RIPAS2LE1ISNXS, handle_ripas2e1is), 4456 4457 SYS_INSN(TLBI_ALLE2OSNXS, handle_tlbi_el2), 4458 SYS_INSN(TLBI_VAE2OSNXS, handle_tlbi_el2), 4459 SYS_INSN(TLBI_ALLE1OSNXS, handle_alle1is), 4460 SYS_INSN(TLBI_VALE2OSNXS, handle_tlbi_el2), 4461 SYS_INSN(TLBI_VMALLS12E1OSNXS, handle_vmalls12e1is), 4462 4463 SYS_INSN(TLBI_RVAE2ISNXS, handle_tlbi_el2), 4464 SYS_INSN(TLBI_RVALE2ISNXS, handle_tlbi_el2), 4465 SYS_INSN(TLBI_ALLE2ISNXS, handle_tlbi_el2), 4466 SYS_INSN(TLBI_VAE2ISNXS, handle_tlbi_el2), 4467 4468 SYS_INSN(TLBI_ALLE1ISNXS, handle_alle1is), 4469 SYS_INSN(TLBI_VALE2ISNXS, handle_tlbi_el2), 4470 SYS_INSN(TLBI_VMALLS12E1ISNXS, handle_vmalls12e1is), 4471 SYS_INSN(TLBI_IPAS2E1OSNXS, handle_ipas2e1is), 4472 SYS_INSN(TLBI_IPAS2E1NXS, handle_ipas2e1is), 4473 SYS_INSN(TLBI_RIPAS2E1NXS, handle_ripas2e1is), 4474 SYS_INSN(TLBI_RIPAS2E1OSNXS, handle_ripas2e1is), 4475 SYS_INSN(TLBI_IPAS2LE1OSNXS, handle_ipas2e1is), 4476 SYS_INSN(TLBI_IPAS2LE1NXS, handle_ipas2e1is), 4477 SYS_INSN(TLBI_RIPAS2LE1NXS, handle_ripas2e1is), 4478 SYS_INSN(TLBI_RIPAS2LE1OSNXS, handle_ripas2e1is), 4479 SYS_INSN(TLBI_RVAE2OSNXS, handle_tlbi_el2), 4480 SYS_INSN(TLBI_RVALE2OSNXS, handle_tlbi_el2), 4481 SYS_INSN(TLBI_RVAE2NXS, handle_tlbi_el2), 4482 SYS_INSN(TLBI_RVALE2NXS, handle_tlbi_el2), 4483 SYS_INSN(TLBI_ALLE2NXS, handle_tlbi_el2), 4484 SYS_INSN(TLBI_VAE2NXS, handle_tlbi_el2), 4485 SYS_INSN(TLBI_ALLE1NXS, handle_alle1is), 4486 SYS_INSN(TLBI_VALE2NXS, handle_tlbi_el2), 4487 SYS_INSN(TLBI_VMALLS12E1NXS, handle_vmalls12e1is), 4488 }; 4489 4490 static bool trap_dbgdidr(struct kvm_vcpu *vcpu, 4491 struct sys_reg_params *p, 4492 const struct sys_reg_desc *r) 4493 { 4494 if (p->is_write) { 4495 return ignore_write(vcpu, p); 4496 } else { 4497 u64 dfr = kvm_read_vm_id_reg(vcpu->kvm, SYS_ID_AA64DFR0_EL1); 4498 u32 el3 = kvm_has_feat(vcpu->kvm, ID_AA64PFR0_EL1, EL3, IMP); 4499 4500 p->regval = ((SYS_FIELD_GET(ID_AA64DFR0_EL1, WRPs, dfr) << 28) | 4501 (SYS_FIELD_GET(ID_AA64DFR0_EL1, BRPs, dfr) << 24) | 4502 (SYS_FIELD_GET(ID_AA64DFR0_EL1, CTX_CMPs, dfr) << 20) | 4503 (SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, dfr) << 16) | 4504 (1 << 15) | (el3 << 14) | (el3 << 12)); 4505 return true; 4506 } 4507 } 4508 4509 /* 4510 * AArch32 debug register mappings 4511 * 4512 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0] 4513 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32] 4514 * 4515 * None of the other registers share their location, so treat them as 4516 * if they were 64bit. 4517 */ 4518 #define DBG_BCR_BVR_WCR_WVR(n) \ 4519 /* DBGBVRn */ \ 4520 { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), \ 4521 trap_dbg_wb_reg, NULL, n }, \ 4522 /* DBGBCRn */ \ 4523 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_dbg_wb_reg, NULL, n }, \ 4524 /* DBGWVRn */ \ 4525 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_dbg_wb_reg, NULL, n }, \ 4526 /* DBGWCRn */ \ 4527 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_dbg_wb_reg, NULL, n } 4528 4529 #define DBGBXVR(n) \ 4530 { AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), \ 4531 trap_dbg_wb_reg, NULL, n } 4532 4533 /* 4534 * Trapped cp14 registers. We generally ignore most of the external 4535 * debug, on the principle that they don't really make sense to a 4536 * guest. Revisit this one day, would this principle change. 4537 */ 4538 static const struct sys_reg_desc cp14_regs[] = { 4539 /* DBGDIDR */ 4540 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgdidr }, 4541 /* DBGDTRRXext */ 4542 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi }, 4543 4544 DBG_BCR_BVR_WCR_WVR(0), 4545 /* DBGDSCRint */ 4546 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi }, 4547 DBG_BCR_BVR_WCR_WVR(1), 4548 /* DBGDCCINT */ 4549 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug_regs, NULL, MDCCINT_EL1 }, 4550 /* DBGDSCRext */ 4551 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug_regs, NULL, MDSCR_EL1 }, 4552 DBG_BCR_BVR_WCR_WVR(2), 4553 /* DBGDTR[RT]Xint */ 4554 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi }, 4555 /* DBGDTR[RT]Xext */ 4556 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi }, 4557 DBG_BCR_BVR_WCR_WVR(3), 4558 DBG_BCR_BVR_WCR_WVR(4), 4559 DBG_BCR_BVR_WCR_WVR(5), 4560 /* DBGWFAR */ 4561 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi }, 4562 /* DBGOSECCR */ 4563 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi }, 4564 DBG_BCR_BVR_WCR_WVR(6), 4565 /* DBGVCR */ 4566 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug_regs, NULL, DBGVCR32_EL2 }, 4567 DBG_BCR_BVR_WCR_WVR(7), 4568 DBG_BCR_BVR_WCR_WVR(8), 4569 DBG_BCR_BVR_WCR_WVR(9), 4570 DBG_BCR_BVR_WCR_WVR(10), 4571 DBG_BCR_BVR_WCR_WVR(11), 4572 DBG_BCR_BVR_WCR_WVR(12), 4573 DBG_BCR_BVR_WCR_WVR(13), 4574 DBG_BCR_BVR_WCR_WVR(14), 4575 DBG_BCR_BVR_WCR_WVR(15), 4576 4577 /* DBGDRAR (32bit) */ 4578 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi }, 4579 4580 DBGBXVR(0), 4581 /* DBGOSLAR */ 4582 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_oslar_el1 }, 4583 DBGBXVR(1), 4584 /* DBGOSLSR */ 4585 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1, NULL, OSLSR_EL1 }, 4586 DBGBXVR(2), 4587 DBGBXVR(3), 4588 /* DBGOSDLR */ 4589 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi }, 4590 DBGBXVR(4), 4591 /* DBGPRCR */ 4592 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi }, 4593 DBGBXVR(5), 4594 DBGBXVR(6), 4595 DBGBXVR(7), 4596 DBGBXVR(8), 4597 DBGBXVR(9), 4598 DBGBXVR(10), 4599 DBGBXVR(11), 4600 DBGBXVR(12), 4601 DBGBXVR(13), 4602 DBGBXVR(14), 4603 DBGBXVR(15), 4604 4605 /* DBGDSAR (32bit) */ 4606 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi }, 4607 4608 /* DBGDEVID2 */ 4609 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi }, 4610 /* DBGDEVID1 */ 4611 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi }, 4612 /* DBGDEVID */ 4613 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi }, 4614 /* DBGCLAIMSET */ 4615 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi }, 4616 /* DBGCLAIMCLR */ 4617 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi }, 4618 /* DBGAUTHSTATUS */ 4619 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 }, 4620 }; 4621 4622 /* Trapped cp14 64bit registers */ 4623 static const struct sys_reg_desc cp14_64_regs[] = { 4624 /* DBGDRAR (64bit) */ 4625 { Op1( 0), CRm( 1), .access = trap_raz_wi }, 4626 4627 /* DBGDSAR (64bit) */ 4628 { Op1( 0), CRm( 2), .access = trap_raz_wi }, 4629 }; 4630 4631 #define CP15_PMU_SYS_REG(_map, _Op1, _CRn, _CRm, _Op2) \ 4632 AA32(_map), \ 4633 Op1(_Op1), CRn(_CRn), CRm(_CRm), Op2(_Op2), \ 4634 .visibility = pmu_visibility 4635 4636 /* Macro to expand the PMEVCNTRn register */ 4637 #define PMU_PMEVCNTR(n) \ 4638 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \ 4639 (0b1000 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \ 4640 .access = access_pmu_evcntr } 4641 4642 /* Macro to expand the PMEVTYPERn register */ 4643 #define PMU_PMEVTYPER(n) \ 4644 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \ 4645 (0b1100 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \ 4646 .access = access_pmu_evtyper } 4647 /* 4648 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding, 4649 * depending on the way they are accessed (as a 32bit or a 64bit 4650 * register). 4651 */ 4652 static const struct sys_reg_desc cp15_regs[] = { 4653 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr }, 4654 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, SCTLR_EL1 }, 4655 /* ACTLR */ 4656 { AA32(LO), Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr, NULL, ACTLR_EL1 }, 4657 /* ACTLR2 */ 4658 { AA32(HI), Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr, NULL, ACTLR_EL1 }, 4659 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, 4660 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, TTBR1_EL1 }, 4661 /* TTBCR */ 4662 { AA32(LO), Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 }, 4663 /* TTBCR2 */ 4664 { AA32(HI), Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, TCR_EL1 }, 4665 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, DACR32_EL2 }, 4666 { CP15_SYS_DESC(SYS_ICC_PMR_EL1), undef_access }, 4667 /* DFSR */ 4668 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, ESR_EL1 }, 4669 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, IFSR32_EL2 }, 4670 /* ADFSR */ 4671 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, AFSR0_EL1 }, 4672 /* AIFSR */ 4673 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, AFSR1_EL1 }, 4674 /* DFAR */ 4675 { AA32(LO), Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, FAR_EL1 }, 4676 /* IFAR */ 4677 { AA32(HI), Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, FAR_EL1 }, 4678 4679 /* 4680 * DC{C,I,CI}SW operations: 4681 */ 4682 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw }, 4683 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw }, 4684 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw }, 4685 4686 /* PMU */ 4687 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 0), .access = access_pmcr }, 4688 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 1), .access = access_pmcnten }, 4689 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 2), .access = access_pmcnten }, 4690 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 3), .access = access_pmovs }, 4691 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 4), .access = access_pmswinc }, 4692 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 5), .access = access_pmselr }, 4693 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 6), .access = access_pmceid }, 4694 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 7), .access = access_pmceid }, 4695 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 0), .access = access_pmu_evcntr }, 4696 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 1), .access = access_pmu_evtyper }, 4697 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 2), .access = access_pmu_evcntr }, 4698 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 0), .access = access_pmuserenr }, 4699 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 1), .access = access_pminten }, 4700 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 2), .access = access_pminten }, 4701 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 3), .access = access_pmovs }, 4702 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 4), .access = access_pmceid }, 4703 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 5), .access = access_pmceid }, 4704 /* PMMIR */ 4705 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 6), .access = access_pmmir }, 4706 4707 /* PRRR/MAIR0 */ 4708 { AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 }, 4709 /* NMRR/MAIR1 */ 4710 { AA32(HI), Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, MAIR_EL1 }, 4711 /* AMAIR0 */ 4712 { AA32(LO), Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, AMAIR_EL1 }, 4713 /* AMAIR1 */ 4714 { AA32(HI), Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, AMAIR_EL1 }, 4715 4716 { CP15_SYS_DESC(SYS_ICC_IAR0_EL1), undef_access }, 4717 { CP15_SYS_DESC(SYS_ICC_EOIR0_EL1), undef_access }, 4718 { CP15_SYS_DESC(SYS_ICC_HPPIR0_EL1), undef_access }, 4719 { CP15_SYS_DESC(SYS_ICC_BPR0_EL1), undef_access }, 4720 { CP15_SYS_DESC(SYS_ICC_AP0R0_EL1), undef_access }, 4721 { CP15_SYS_DESC(SYS_ICC_AP0R1_EL1), undef_access }, 4722 { CP15_SYS_DESC(SYS_ICC_AP0R2_EL1), undef_access }, 4723 { CP15_SYS_DESC(SYS_ICC_AP0R3_EL1), undef_access }, 4724 { CP15_SYS_DESC(SYS_ICC_AP1R0_EL1), undef_access }, 4725 { CP15_SYS_DESC(SYS_ICC_AP1R1_EL1), undef_access }, 4726 { CP15_SYS_DESC(SYS_ICC_AP1R2_EL1), undef_access }, 4727 { CP15_SYS_DESC(SYS_ICC_AP1R3_EL1), undef_access }, 4728 { CP15_SYS_DESC(SYS_ICC_DIR_EL1), access_gic_dir }, 4729 { CP15_SYS_DESC(SYS_ICC_RPR_EL1), undef_access }, 4730 { CP15_SYS_DESC(SYS_ICC_IAR1_EL1), undef_access }, 4731 { CP15_SYS_DESC(SYS_ICC_EOIR1_EL1), undef_access }, 4732 { CP15_SYS_DESC(SYS_ICC_HPPIR1_EL1), undef_access }, 4733 { CP15_SYS_DESC(SYS_ICC_BPR1_EL1), undef_access }, 4734 { CP15_SYS_DESC(SYS_ICC_CTLR_EL1), undef_access }, 4735 { CP15_SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre }, 4736 { CP15_SYS_DESC(SYS_ICC_IGRPEN0_EL1), undef_access }, 4737 { CP15_SYS_DESC(SYS_ICC_IGRPEN1_EL1), undef_access }, 4738 4739 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, CONTEXTIDR_EL1 }, 4740 4741 /* Arch Tmers */ 4742 { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer }, 4743 { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer }, 4744 4745 /* PMEVCNTRn */ 4746 PMU_PMEVCNTR(0), 4747 PMU_PMEVCNTR(1), 4748 PMU_PMEVCNTR(2), 4749 PMU_PMEVCNTR(3), 4750 PMU_PMEVCNTR(4), 4751 PMU_PMEVCNTR(5), 4752 PMU_PMEVCNTR(6), 4753 PMU_PMEVCNTR(7), 4754 PMU_PMEVCNTR(8), 4755 PMU_PMEVCNTR(9), 4756 PMU_PMEVCNTR(10), 4757 PMU_PMEVCNTR(11), 4758 PMU_PMEVCNTR(12), 4759 PMU_PMEVCNTR(13), 4760 PMU_PMEVCNTR(14), 4761 PMU_PMEVCNTR(15), 4762 PMU_PMEVCNTR(16), 4763 PMU_PMEVCNTR(17), 4764 PMU_PMEVCNTR(18), 4765 PMU_PMEVCNTR(19), 4766 PMU_PMEVCNTR(20), 4767 PMU_PMEVCNTR(21), 4768 PMU_PMEVCNTR(22), 4769 PMU_PMEVCNTR(23), 4770 PMU_PMEVCNTR(24), 4771 PMU_PMEVCNTR(25), 4772 PMU_PMEVCNTR(26), 4773 PMU_PMEVCNTR(27), 4774 PMU_PMEVCNTR(28), 4775 PMU_PMEVCNTR(29), 4776 PMU_PMEVCNTR(30), 4777 /* PMEVTYPERn */ 4778 PMU_PMEVTYPER(0), 4779 PMU_PMEVTYPER(1), 4780 PMU_PMEVTYPER(2), 4781 PMU_PMEVTYPER(3), 4782 PMU_PMEVTYPER(4), 4783 PMU_PMEVTYPER(5), 4784 PMU_PMEVTYPER(6), 4785 PMU_PMEVTYPER(7), 4786 PMU_PMEVTYPER(8), 4787 PMU_PMEVTYPER(9), 4788 PMU_PMEVTYPER(10), 4789 PMU_PMEVTYPER(11), 4790 PMU_PMEVTYPER(12), 4791 PMU_PMEVTYPER(13), 4792 PMU_PMEVTYPER(14), 4793 PMU_PMEVTYPER(15), 4794 PMU_PMEVTYPER(16), 4795 PMU_PMEVTYPER(17), 4796 PMU_PMEVTYPER(18), 4797 PMU_PMEVTYPER(19), 4798 PMU_PMEVTYPER(20), 4799 PMU_PMEVTYPER(21), 4800 PMU_PMEVTYPER(22), 4801 PMU_PMEVTYPER(23), 4802 PMU_PMEVTYPER(24), 4803 PMU_PMEVTYPER(25), 4804 PMU_PMEVTYPER(26), 4805 PMU_PMEVTYPER(27), 4806 PMU_PMEVTYPER(28), 4807 PMU_PMEVTYPER(29), 4808 PMU_PMEVTYPER(30), 4809 /* PMCCFILTR */ 4810 { CP15_PMU_SYS_REG(DIRECT, 0, 14, 15, 7), .access = access_pmu_evtyper }, 4811 4812 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr }, 4813 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr }, 4814 4815 /* CCSIDR2 */ 4816 { Op1(1), CRn( 0), CRm( 0), Op2(2), undef_access }, 4817 4818 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 }, 4819 }; 4820 4821 static const struct sys_reg_desc cp15_64_regs[] = { 4822 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, 4823 { CP15_PMU_SYS_REG(DIRECT, 0, 0, 9, 0), .access = access_pmu_evcntr }, 4824 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */ 4825 { SYS_DESC(SYS_AARCH32_CNTPCT), access_arch_timer }, 4826 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 }, 4827 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */ 4828 { SYS_DESC(SYS_AARCH32_CNTVCT), access_arch_timer }, 4829 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */ 4830 { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer }, 4831 { SYS_DESC(SYS_AARCH32_CNTPCTSS), access_arch_timer }, 4832 { SYS_DESC(SYS_AARCH32_CNTVCTSS), access_arch_timer }, 4833 }; 4834 4835 static bool check_sysreg_table(const struct sys_reg_desc *table, unsigned int n, 4836 bool reset_check) 4837 { 4838 unsigned int i; 4839 4840 for (i = 0; i < n; i++) { 4841 if (reset_check && table[i].reg && !table[i].reset) { 4842 kvm_err("sys_reg table %pS entry %d (%s) lacks reset\n", 4843 &table[i], i, table[i].name); 4844 return false; 4845 } 4846 4847 if (i && cmp_sys_reg(&table[i-1], &table[i]) >= 0) { 4848 kvm_err("sys_reg table %pS entry %d (%s -> %s) out of order\n", 4849 &table[i], i, table[i - 1].name, table[i].name); 4850 return false; 4851 } 4852 } 4853 4854 return true; 4855 } 4856 4857 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu) 4858 { 4859 kvm_inject_undefined(vcpu); 4860 return 1; 4861 } 4862 4863 static void perform_access(struct kvm_vcpu *vcpu, 4864 struct sys_reg_params *params, 4865 const struct sys_reg_desc *r) 4866 { 4867 trace_kvm_sys_access(*vcpu_pc(vcpu), params, r); 4868 4869 /* Check for regs disabled by runtime config */ 4870 if (sysreg_hidden(vcpu, r)) { 4871 kvm_inject_undefined(vcpu); 4872 return; 4873 } 4874 4875 /* 4876 * Not having an accessor means that we have configured a trap 4877 * that we don't know how to handle. This certainly qualifies 4878 * as a gross bug that should be fixed right away. 4879 */ 4880 if (!r->access) { 4881 bad_trap(vcpu, params, r, "register access"); 4882 return; 4883 } 4884 4885 /* Skip instruction if instructed so */ 4886 if (likely(r->access(vcpu, params, r))) 4887 kvm_incr_pc(vcpu); 4888 } 4889 4890 /* 4891 * emulate_cp -- tries to match a sys_reg access in a handling table, and 4892 * call the corresponding trap handler. 4893 * 4894 * @params: pointer to the descriptor of the access 4895 * @table: array of trap descriptors 4896 * @num: size of the trap descriptor array 4897 * 4898 * Return true if the access has been handled, false if not. 4899 */ 4900 static bool emulate_cp(struct kvm_vcpu *vcpu, 4901 struct sys_reg_params *params, 4902 const struct sys_reg_desc *table, 4903 size_t num) 4904 { 4905 const struct sys_reg_desc *r; 4906 4907 if (!table) 4908 return false; /* Not handled */ 4909 4910 r = find_reg(params, table, num); 4911 4912 if (r) { 4913 perform_access(vcpu, params, r); 4914 return true; 4915 } 4916 4917 /* Not handled */ 4918 return false; 4919 } 4920 4921 static void unhandled_cp_access(struct kvm_vcpu *vcpu, 4922 struct sys_reg_params *params) 4923 { 4924 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu); 4925 int cp = -1; 4926 4927 switch (esr_ec) { 4928 case ESR_ELx_EC_CP15_32: 4929 case ESR_ELx_EC_CP15_64: 4930 cp = 15; 4931 break; 4932 case ESR_ELx_EC_CP14_MR: 4933 case ESR_ELx_EC_CP14_64: 4934 cp = 14; 4935 break; 4936 default: 4937 WARN_ON(1); 4938 } 4939 4940 print_sys_reg_msg(params, 4941 "Unsupported guest CP%d access at: %08lx [%08lx]\n", 4942 cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 4943 kvm_inject_undefined(vcpu); 4944 } 4945 4946 /** 4947 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access 4948 * @vcpu: The VCPU pointer 4949 * @global: &struct sys_reg_desc 4950 * @nr_global: size of the @global array 4951 */ 4952 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu, 4953 const struct sys_reg_desc *global, 4954 size_t nr_global) 4955 { 4956 struct sys_reg_params params; 4957 u64 esr = kvm_vcpu_get_esr(vcpu); 4958 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4959 int Rt2 = (esr >> 10) & 0x1f; 4960 4961 params.CRm = (esr >> 1) & 0xf; 4962 params.is_write = ((esr & 1) == 0); 4963 4964 params.Op0 = 0; 4965 params.Op1 = (esr >> 16) & 0xf; 4966 params.Op2 = 0; 4967 params.CRn = 0; 4968 4969 /* 4970 * Make a 64-bit value out of Rt and Rt2. As we use the same trap 4971 * backends between AArch32 and AArch64, we get away with it. 4972 */ 4973 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff; 4974 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32; 4975 4976 /* 4977 * If the table contains a handler, handle the 4978 * potential register operation in the case of a read and return 4979 * with success. 4980 */ 4981 if (emulate_cp(vcpu, ¶ms, global, nr_global)) { 4982 /* Split up the value between registers for the read side */ 4983 if (!params.is_write) { 4984 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval)); 4985 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval)); 4986 } 4987 4988 return 1; 4989 } 4990 4991 unhandled_cp_access(vcpu, ¶ms); 4992 return 1; 4993 } 4994 4995 static bool emulate_sys_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *params); 4996 4997 /* 4998 * The CP10 ID registers are architecturally mapped to AArch64 feature 4999 * registers. Abuse that fact so we can rely on the AArch64 handler for accesses 5000 * from AArch32. 5001 */ 5002 static bool kvm_esr_cp10_id_to_sys64(u64 esr, struct sys_reg_params *params) 5003 { 5004 u8 reg_id = (esr >> 10) & 0xf; 5005 bool valid; 5006 5007 params->is_write = ((esr & 1) == 0); 5008 params->Op0 = 3; 5009 params->Op1 = 0; 5010 params->CRn = 0; 5011 params->CRm = 3; 5012 5013 /* CP10 ID registers are read-only */ 5014 valid = !params->is_write; 5015 5016 switch (reg_id) { 5017 /* MVFR0 */ 5018 case 0b0111: 5019 params->Op2 = 0; 5020 break; 5021 /* MVFR1 */ 5022 case 0b0110: 5023 params->Op2 = 1; 5024 break; 5025 /* MVFR2 */ 5026 case 0b0101: 5027 params->Op2 = 2; 5028 break; 5029 default: 5030 valid = false; 5031 } 5032 5033 if (valid) 5034 return true; 5035 5036 kvm_pr_unimpl("Unhandled cp10 register %s: %u\n", 5037 str_write_read(params->is_write), reg_id); 5038 return false; 5039 } 5040 5041 /** 5042 * kvm_handle_cp10_id() - Handles a VMRS trap on guest access to a 'Media and 5043 * VFP Register' from AArch32. 5044 * @vcpu: The vCPU pointer 5045 * 5046 * MVFR{0-2} are architecturally mapped to the AArch64 MVFR{0-2}_EL1 registers. 5047 * Work out the correct AArch64 system register encoding and reroute to the 5048 * AArch64 system register emulation. 5049 */ 5050 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu) 5051 { 5052 int Rt = kvm_vcpu_sys_get_rt(vcpu); 5053 u64 esr = kvm_vcpu_get_esr(vcpu); 5054 struct sys_reg_params params; 5055 5056 /* UNDEF on any unhandled register access */ 5057 if (!kvm_esr_cp10_id_to_sys64(esr, ¶ms)) { 5058 kvm_inject_undefined(vcpu); 5059 return 1; 5060 } 5061 5062 if (emulate_sys_reg(vcpu, ¶ms)) 5063 vcpu_set_reg(vcpu, Rt, params.regval); 5064 5065 return 1; 5066 } 5067 5068 /** 5069 * kvm_emulate_cp15_id_reg() - Handles an MRC trap on a guest CP15 access where 5070 * CRn=0, which corresponds to the AArch32 feature 5071 * registers. 5072 * @vcpu: the vCPU pointer 5073 * @params: the system register access parameters. 5074 * 5075 * Our cp15 system register tables do not enumerate the AArch32 feature 5076 * registers. Conveniently, our AArch64 table does, and the AArch32 system 5077 * register encoding can be trivially remapped into the AArch64 for the feature 5078 * registers: Append op0=3, leaving op1, CRn, CRm, and op2 the same. 5079 * 5080 * According to DDI0487G.b G7.3.1, paragraph "Behavior of VMSAv8-32 32-bit 5081 * System registers with (coproc=0b1111, CRn==c0)", read accesses from this 5082 * range are either UNKNOWN or RES0. Rerouting remains architectural as we 5083 * treat undefined registers in this range as RAZ. 5084 */ 5085 static int kvm_emulate_cp15_id_reg(struct kvm_vcpu *vcpu, 5086 struct sys_reg_params *params) 5087 { 5088 int Rt = kvm_vcpu_sys_get_rt(vcpu); 5089 5090 /* Treat impossible writes to RO registers as UNDEFINED */ 5091 if (params->is_write) { 5092 unhandled_cp_access(vcpu, params); 5093 return 1; 5094 } 5095 5096 params->Op0 = 3; 5097 5098 /* 5099 * All registers where CRm > 3 are known to be UNKNOWN/RAZ from AArch32. 5100 * Avoid conflicting with future expansion of AArch64 feature registers 5101 * and simply treat them as RAZ here. 5102 */ 5103 if (params->CRm > 3) 5104 params->regval = 0; 5105 else if (!emulate_sys_reg(vcpu, params)) 5106 return 1; 5107 5108 vcpu_set_reg(vcpu, Rt, params->regval); 5109 return 1; 5110 } 5111 5112 /** 5113 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access 5114 * @vcpu: The VCPU pointer 5115 * @params: &struct sys_reg_params 5116 * @global: &struct sys_reg_desc 5117 * @nr_global: size of the @global array 5118 */ 5119 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu, 5120 struct sys_reg_params *params, 5121 const struct sys_reg_desc *global, 5122 size_t nr_global) 5123 { 5124 int Rt = kvm_vcpu_sys_get_rt(vcpu); 5125 5126 params->regval = vcpu_get_reg(vcpu, Rt); 5127 5128 if (emulate_cp(vcpu, params, global, nr_global)) { 5129 if (!params->is_write) 5130 vcpu_set_reg(vcpu, Rt, params->regval); 5131 return 1; 5132 } 5133 5134 unhandled_cp_access(vcpu, params); 5135 return 1; 5136 } 5137 5138 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu) 5139 { 5140 return kvm_handle_cp_64(vcpu, cp15_64_regs, ARRAY_SIZE(cp15_64_regs)); 5141 } 5142 5143 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu) 5144 { 5145 struct sys_reg_params params; 5146 5147 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu)); 5148 5149 /* 5150 * Certain AArch32 ID registers are handled by rerouting to the AArch64 5151 * system register table. Registers in the ID range where CRm=0 are 5152 * excluded from this scheme as they do not trivially map into AArch64 5153 * system register encodings, except for AIDR/REVIDR. 5154 */ 5155 if (params.Op1 == 0 && params.CRn == 0 && 5156 (params.CRm || params.Op2 == 6 /* REVIDR */)) 5157 return kvm_emulate_cp15_id_reg(vcpu, ¶ms); 5158 if (params.Op1 == 1 && params.CRn == 0 && 5159 params.CRm == 0 && params.Op2 == 7 /* AIDR */) 5160 return kvm_emulate_cp15_id_reg(vcpu, ¶ms); 5161 5162 return kvm_handle_cp_32(vcpu, ¶ms, cp15_regs, ARRAY_SIZE(cp15_regs)); 5163 } 5164 5165 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu) 5166 { 5167 return kvm_handle_cp_64(vcpu, cp14_64_regs, ARRAY_SIZE(cp14_64_regs)); 5168 } 5169 5170 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu) 5171 { 5172 struct sys_reg_params params; 5173 5174 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu)); 5175 5176 return kvm_handle_cp_32(vcpu, ¶ms, cp14_regs, ARRAY_SIZE(cp14_regs)); 5177 } 5178 5179 /** 5180 * emulate_sys_reg - Emulate a guest access to an AArch64 system register 5181 * @vcpu: The VCPU pointer 5182 * @params: Decoded system register parameters 5183 * 5184 * Return: true if the system register access was successful, false otherwise. 5185 */ 5186 static bool emulate_sys_reg(struct kvm_vcpu *vcpu, 5187 struct sys_reg_params *params) 5188 { 5189 const struct sys_reg_desc *r; 5190 5191 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 5192 if (likely(r)) { 5193 perform_access(vcpu, params, r); 5194 return true; 5195 } 5196 5197 print_sys_reg_msg(params, 5198 "Unsupported guest sys_reg access at: %lx [%08lx]\n", 5199 *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 5200 kvm_inject_undefined(vcpu); 5201 5202 return false; 5203 } 5204 5205 static const struct sys_reg_desc *idregs_debug_find(struct kvm *kvm, loff_t pos) 5206 { 5207 unsigned long i, idreg_idx = 0; 5208 5209 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { 5210 const struct sys_reg_desc *r = &sys_reg_descs[i]; 5211 5212 if (!is_vm_ftr_id_reg(reg_to_encoding(r))) 5213 continue; 5214 5215 if (idreg_idx++ == pos) 5216 return r; 5217 } 5218 5219 return NULL; 5220 } 5221 5222 static void *idregs_debug_start(struct seq_file *s, loff_t *pos) 5223 { 5224 struct kvm *kvm = s->private; 5225 5226 if (!test_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags)) 5227 return NULL; 5228 5229 return (void *)idregs_debug_find(kvm, *pos); 5230 } 5231 5232 static void *idregs_debug_next(struct seq_file *s, void *v, loff_t *pos) 5233 { 5234 struct kvm *kvm = s->private; 5235 5236 (*pos)++; 5237 5238 return (void *)idregs_debug_find(kvm, *pos); 5239 } 5240 5241 static void idregs_debug_stop(struct seq_file *s, void *v) 5242 { 5243 } 5244 5245 static int idregs_debug_show(struct seq_file *s, void *v) 5246 { 5247 const struct sys_reg_desc *desc = v; 5248 struct kvm *kvm = s->private; 5249 5250 if (!desc) 5251 return 0; 5252 5253 seq_printf(s, "%20s:\t%016llx\n", 5254 desc->name, kvm_read_vm_id_reg(kvm, reg_to_encoding(desc))); 5255 5256 return 0; 5257 } 5258 5259 static const struct seq_operations idregs_debug_sops = { 5260 .start = idregs_debug_start, 5261 .next = idregs_debug_next, 5262 .stop = idregs_debug_stop, 5263 .show = idregs_debug_show, 5264 }; 5265 5266 DEFINE_SEQ_ATTRIBUTE(idregs_debug); 5267 5268 static const struct sys_reg_desc *sr_resx_find(struct kvm *kvm, loff_t pos) 5269 { 5270 unsigned long i, sr_idx = 0; 5271 5272 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { 5273 const struct sys_reg_desc *r = &sys_reg_descs[i]; 5274 5275 if (r->reg < __SANITISED_REG_START__) 5276 continue; 5277 5278 if (sr_idx++ == pos) 5279 return r; 5280 } 5281 5282 return NULL; 5283 } 5284 5285 static void *sr_resx_start(struct seq_file *s, loff_t *pos) 5286 { 5287 struct kvm *kvm = s->private; 5288 5289 if (!kvm->arch.sysreg_masks) 5290 return NULL; 5291 5292 return (void *)sr_resx_find(kvm, *pos); 5293 } 5294 5295 static void *sr_resx_next(struct seq_file *s, void *v, loff_t *pos) 5296 { 5297 struct kvm *kvm = s->private; 5298 5299 (*pos)++; 5300 5301 return (void *)sr_resx_find(kvm, *pos); 5302 } 5303 5304 static void sr_resx_stop(struct seq_file *s, void *v) 5305 { 5306 } 5307 5308 static int sr_resx_show(struct seq_file *s, void *v) 5309 { 5310 const struct sys_reg_desc *desc = v; 5311 struct kvm *kvm = s->private; 5312 struct resx resx; 5313 5314 if (!desc) 5315 return 0; 5316 5317 resx = kvm_get_sysreg_resx(kvm, desc->reg); 5318 5319 seq_printf(s, "%20s:\tRES0:%016llx\tRES1:%016llx\n", 5320 desc->name, resx.res0, resx.res1); 5321 5322 return 0; 5323 } 5324 5325 static const struct seq_operations sr_resx_sops = { 5326 .start = sr_resx_start, 5327 .next = sr_resx_next, 5328 .stop = sr_resx_stop, 5329 .show = sr_resx_show, 5330 }; 5331 5332 DEFINE_SEQ_ATTRIBUTE(sr_resx); 5333 5334 void kvm_sys_regs_create_debugfs(struct kvm *kvm) 5335 { 5336 debugfs_create_file("idregs", 0444, kvm->debugfs_dentry, kvm, 5337 &idregs_debug_fops); 5338 debugfs_create_file("resx", 0444, kvm->debugfs_dentry, kvm, 5339 &sr_resx_fops); 5340 } 5341 5342 static void reset_vm_ftr_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *reg) 5343 { 5344 u32 id = reg_to_encoding(reg); 5345 struct kvm *kvm = vcpu->kvm; 5346 5347 if (test_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags)) 5348 return; 5349 5350 kvm_set_vm_id_reg(kvm, id, reg->reset(vcpu, reg)); 5351 } 5352 5353 static void reset_vcpu_ftr_id_reg(struct kvm_vcpu *vcpu, 5354 const struct sys_reg_desc *reg) 5355 { 5356 if (kvm_vcpu_initialized(vcpu)) 5357 return; 5358 5359 reg->reset(vcpu, reg); 5360 } 5361 5362 /** 5363 * kvm_reset_sys_regs - sets system registers to reset value 5364 * @vcpu: The VCPU pointer 5365 * 5366 * This function finds the right table above and sets the registers on the 5367 * virtual CPU struct to their architecturally defined reset values. 5368 */ 5369 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu) 5370 { 5371 struct kvm *kvm = vcpu->kvm; 5372 unsigned long i; 5373 5374 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { 5375 const struct sys_reg_desc *r = &sys_reg_descs[i]; 5376 5377 if (!r->reset) 5378 continue; 5379 5380 if (is_vm_ftr_id_reg(reg_to_encoding(r))) 5381 reset_vm_ftr_id_reg(vcpu, r); 5382 else if (is_vcpu_ftr_id_reg(reg_to_encoding(r))) 5383 reset_vcpu_ftr_id_reg(vcpu, r); 5384 else 5385 r->reset(vcpu, r); 5386 5387 if (r->reg >= __SANITISED_REG_START__ && r->reg < NR_SYS_REGS) 5388 __vcpu_rmw_sys_reg(vcpu, r->reg, |=, 0); 5389 } 5390 5391 set_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags); 5392 5393 if (kvm_vcpu_has_pmu(vcpu)) 5394 kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu); 5395 } 5396 5397 /** 5398 * kvm_handle_sys_reg -- handles a system instruction or mrs/msr instruction 5399 * trap on a guest execution 5400 * @vcpu: The VCPU pointer 5401 */ 5402 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu) 5403 { 5404 const struct sys_reg_desc *desc = NULL; 5405 struct sys_reg_params params; 5406 unsigned long esr = kvm_vcpu_get_esr(vcpu); 5407 int Rt = kvm_vcpu_sys_get_rt(vcpu); 5408 int sr_idx; 5409 5410 trace_kvm_handle_sys_reg(esr); 5411 5412 if (triage_sysreg_trap(vcpu, &sr_idx)) 5413 return 1; 5414 5415 params = esr_sys64_to_params(esr); 5416 params.regval = vcpu_get_reg(vcpu, Rt); 5417 5418 /* System registers have Op0=={2,3}, as per DDI487 J.a C5.1.2 */ 5419 if (params.Op0 == 2 || params.Op0 == 3) 5420 desc = &sys_reg_descs[sr_idx]; 5421 else 5422 desc = &sys_insn_descs[sr_idx]; 5423 5424 perform_access(vcpu, ¶ms, desc); 5425 5426 /* Read from system register? */ 5427 if (!params.is_write && 5428 (params.Op0 == 2 || params.Op0 == 3)) 5429 vcpu_set_reg(vcpu, Rt, params.regval); 5430 5431 return 1; 5432 } 5433 5434 /****************************************************************************** 5435 * Userspace API 5436 *****************************************************************************/ 5437 5438 static bool index_to_params(u64 id, struct sys_reg_params *params) 5439 { 5440 switch (id & KVM_REG_SIZE_MASK) { 5441 case KVM_REG_SIZE_U64: 5442 /* Any unused index bits means it's not valid. */ 5443 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK 5444 | KVM_REG_ARM_COPROC_MASK 5445 | KVM_REG_ARM64_SYSREG_OP0_MASK 5446 | KVM_REG_ARM64_SYSREG_OP1_MASK 5447 | KVM_REG_ARM64_SYSREG_CRN_MASK 5448 | KVM_REG_ARM64_SYSREG_CRM_MASK 5449 | KVM_REG_ARM64_SYSREG_OP2_MASK)) 5450 return false; 5451 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK) 5452 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT); 5453 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK) 5454 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT); 5455 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK) 5456 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT); 5457 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK) 5458 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT); 5459 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK) 5460 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT); 5461 return true; 5462 default: 5463 return false; 5464 } 5465 } 5466 5467 const struct sys_reg_desc *get_reg_by_id(u64 id, 5468 const struct sys_reg_desc table[], 5469 unsigned int num) 5470 { 5471 struct sys_reg_params params; 5472 5473 if (!index_to_params(id, ¶ms)) 5474 return NULL; 5475 5476 return find_reg(¶ms, table, num); 5477 } 5478 5479 /* Decode an index value, and find the sys_reg_desc entry. */ 5480 static const struct sys_reg_desc * 5481 id_to_sys_reg_desc(struct kvm_vcpu *vcpu, u64 id, 5482 const struct sys_reg_desc table[], unsigned int num) 5483 5484 { 5485 const struct sys_reg_desc *r; 5486 5487 /* We only do sys_reg for now. */ 5488 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG) 5489 return NULL; 5490 5491 r = get_reg_by_id(id, table, num); 5492 5493 /* Not saved in the sys_reg array and not otherwise accessible? */ 5494 if (r && (!(r->reg || r->get_user) || sysreg_hidden(vcpu, r))) 5495 r = NULL; 5496 5497 return r; 5498 } 5499 5500 static int demux_c15_get(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) 5501 { 5502 u32 val; 5503 u32 __user *uval = uaddr; 5504 5505 /* Fail if we have unknown bits set. */ 5506 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 5507 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 5508 return -ENOENT; 5509 5510 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 5511 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 5512 if (KVM_REG_SIZE(id) != 4) 5513 return -ENOENT; 5514 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 5515 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 5516 if (val >= CSSELR_MAX) 5517 return -ENOENT; 5518 5519 return put_user(get_ccsidr(vcpu, val), uval); 5520 default: 5521 return -ENOENT; 5522 } 5523 } 5524 5525 static int demux_c15_set(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) 5526 { 5527 u32 val, newval; 5528 u32 __user *uval = uaddr; 5529 5530 /* Fail if we have unknown bits set. */ 5531 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 5532 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 5533 return -ENOENT; 5534 5535 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 5536 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 5537 if (KVM_REG_SIZE(id) != 4) 5538 return -ENOENT; 5539 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 5540 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 5541 if (val >= CSSELR_MAX) 5542 return -ENOENT; 5543 5544 if (get_user(newval, uval)) 5545 return -EFAULT; 5546 5547 return set_ccsidr(vcpu, val, newval); 5548 default: 5549 return -ENOENT; 5550 } 5551 } 5552 5553 static u64 kvm_one_reg_to_id(const struct kvm_one_reg *reg) 5554 { 5555 switch(reg->id) { 5556 case KVM_REG_ARM_TIMER_CVAL: 5557 return TO_ARM64_SYS_REG(CNTV_CVAL_EL0); 5558 case KVM_REG_ARM_TIMER_CNT: 5559 return TO_ARM64_SYS_REG(CNTVCT_EL0); 5560 default: 5561 return reg->id; 5562 } 5563 } 5564 5565 int kvm_sys_reg_get_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg, 5566 const struct sys_reg_desc table[], unsigned int num) 5567 { 5568 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr; 5569 const struct sys_reg_desc *r; 5570 u64 id = kvm_one_reg_to_id(reg); 5571 u64 val; 5572 int ret; 5573 5574 r = id_to_sys_reg_desc(vcpu, id, table, num); 5575 if (!r || sysreg_hidden(vcpu, r)) 5576 return -ENOENT; 5577 5578 if (r->get_user) { 5579 ret = (r->get_user)(vcpu, r, &val); 5580 } else { 5581 val = __vcpu_sys_reg(vcpu, r->reg); 5582 ret = 0; 5583 } 5584 5585 if (!ret) 5586 ret = put_user(val, uaddr); 5587 5588 return ret; 5589 } 5590 5591 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 5592 { 5593 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 5594 5595 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 5596 return demux_c15_get(vcpu, reg->id, uaddr); 5597 5598 return kvm_sys_reg_get_user(vcpu, reg, 5599 sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 5600 } 5601 5602 int kvm_sys_reg_set_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg, 5603 const struct sys_reg_desc table[], unsigned int num) 5604 { 5605 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr; 5606 const struct sys_reg_desc *r; 5607 u64 id = kvm_one_reg_to_id(reg); 5608 u64 val; 5609 int ret; 5610 5611 if (get_user(val, uaddr)) 5612 return -EFAULT; 5613 5614 r = id_to_sys_reg_desc(vcpu, id, table, num); 5615 if (!r || sysreg_hidden(vcpu, r)) 5616 return -ENOENT; 5617 5618 if (sysreg_user_write_ignore(vcpu, r)) 5619 return 0; 5620 5621 if (r->set_user) { 5622 ret = (r->set_user)(vcpu, r, val); 5623 } else { 5624 __vcpu_assign_sys_reg(vcpu, r->reg, val); 5625 ret = 0; 5626 } 5627 5628 return ret; 5629 } 5630 5631 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 5632 { 5633 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 5634 5635 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 5636 return demux_c15_set(vcpu, reg->id, uaddr); 5637 5638 return kvm_sys_reg_set_user(vcpu, reg, 5639 sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 5640 } 5641 5642 static unsigned int num_demux_regs(void) 5643 { 5644 return CSSELR_MAX; 5645 } 5646 5647 static int write_demux_regids(u64 __user *uindices) 5648 { 5649 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX; 5650 unsigned int i; 5651 5652 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR; 5653 for (i = 0; i < CSSELR_MAX; i++) { 5654 if (put_user(val | i, uindices)) 5655 return -EFAULT; 5656 uindices++; 5657 } 5658 return 0; 5659 } 5660 5661 static u64 sys_reg_to_index(const struct sys_reg_desc *reg) 5662 { 5663 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | 5664 KVM_REG_ARM64_SYSREG | 5665 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) | 5666 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) | 5667 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) | 5668 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) | 5669 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT)); 5670 } 5671 5672 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind) 5673 { 5674 u64 idx; 5675 5676 if (!*uind) 5677 return true; 5678 5679 switch (reg_to_encoding(reg)) { 5680 case SYS_CNTV_CVAL_EL0: 5681 idx = KVM_REG_ARM_TIMER_CVAL; 5682 break; 5683 case SYS_CNTVCT_EL0: 5684 idx = KVM_REG_ARM_TIMER_CNT; 5685 break; 5686 default: 5687 idx = sys_reg_to_index(reg); 5688 } 5689 5690 if (put_user(idx, *uind)) 5691 return false; 5692 5693 (*uind)++; 5694 return true; 5695 } 5696 5697 static int walk_one_sys_reg(const struct kvm_vcpu *vcpu, 5698 const struct sys_reg_desc *rd, 5699 u64 __user **uind, 5700 unsigned int *total) 5701 { 5702 /* 5703 * Ignore registers we trap but don't save, 5704 * and for which no custom user accessor is provided. 5705 */ 5706 if (!(rd->reg || rd->get_user)) 5707 return 0; 5708 5709 if (sysreg_hidden(vcpu, rd)) 5710 return 0; 5711 5712 if (!copy_reg_to_user(rd, uind)) 5713 return -EFAULT; 5714 5715 (*total)++; 5716 return 0; 5717 } 5718 5719 /* Assumed ordered tables, see kvm_sys_reg_table_init. */ 5720 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind) 5721 { 5722 const struct sys_reg_desc *i2, *end2; 5723 unsigned int total = 0; 5724 int err; 5725 5726 i2 = sys_reg_descs; 5727 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs); 5728 5729 while (i2 != end2) { 5730 err = walk_one_sys_reg(vcpu, i2++, &uind, &total); 5731 if (err) 5732 return err; 5733 } 5734 return total; 5735 } 5736 5737 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu) 5738 { 5739 return num_demux_regs() 5740 + walk_sys_regs(vcpu, (u64 __user *)NULL); 5741 } 5742 5743 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) 5744 { 5745 int err; 5746 5747 err = walk_sys_regs(vcpu, uindices); 5748 if (err < 0) 5749 return err; 5750 uindices += err; 5751 5752 return write_demux_regids(uindices); 5753 } 5754 5755 #define KVM_ARM_FEATURE_ID_RANGE_INDEX(r) \ 5756 KVM_ARM_FEATURE_ID_RANGE_IDX(sys_reg_Op0(r), \ 5757 sys_reg_Op1(r), \ 5758 sys_reg_CRn(r), \ 5759 sys_reg_CRm(r), \ 5760 sys_reg_Op2(r)) 5761 5762 int kvm_vm_ioctl_get_reg_writable_masks(struct kvm *kvm, struct reg_mask_range *range) 5763 { 5764 const void *zero_page = page_to_virt(ZERO_PAGE(0)); 5765 u64 __user *masks = (u64 __user *)range->addr; 5766 5767 /* Only feature id range is supported, reserved[13] must be zero. */ 5768 if (range->range || 5769 memcmp(range->reserved, zero_page, sizeof(range->reserved))) 5770 return -EINVAL; 5771 5772 /* Wipe the whole thing first */ 5773 if (clear_user(masks, KVM_ARM_FEATURE_ID_RANGE_SIZE * sizeof(__u64))) 5774 return -EFAULT; 5775 5776 for (int i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { 5777 const struct sys_reg_desc *reg = &sys_reg_descs[i]; 5778 u32 encoding = reg_to_encoding(reg); 5779 u64 val; 5780 5781 if (!is_feature_id_reg(encoding) || !reg->set_user) 5782 continue; 5783 5784 if (!reg->val || 5785 (is_aa32_id_reg(encoding) && !kvm_supports_32bit_el0())) { 5786 continue; 5787 } 5788 val = reg->val; 5789 5790 if (put_user(val, (masks + KVM_ARM_FEATURE_ID_RANGE_INDEX(encoding)))) 5791 return -EFAULT; 5792 } 5793 5794 return 0; 5795 } 5796 5797 static void vcpu_set_hcr(struct kvm_vcpu *vcpu) 5798 { 5799 struct kvm *kvm = vcpu->kvm; 5800 5801 if (has_vhe() || has_hvhe()) 5802 vcpu->arch.hcr_el2 |= HCR_E2H; 5803 if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN)) { 5804 /* route synchronous external abort exceptions to EL2 */ 5805 vcpu->arch.hcr_el2 |= HCR_TEA; 5806 /* trap error record accesses */ 5807 vcpu->arch.hcr_el2 |= HCR_TERR; 5808 } 5809 5810 if (cpus_have_final_cap(ARM64_HAS_STAGE2_FWB)) 5811 vcpu->arch.hcr_el2 |= HCR_FWB; 5812 5813 if (cpus_have_final_cap(ARM64_HAS_EVT) && 5814 !cpus_have_final_cap(ARM64_MISMATCHED_CACHE_TYPE) && 5815 kvm_read_vm_id_reg(kvm, SYS_CTR_EL0) == read_sanitised_ftr_reg(SYS_CTR_EL0)) 5816 vcpu->arch.hcr_el2 |= HCR_TID4; 5817 else 5818 vcpu->arch.hcr_el2 |= HCR_TID2; 5819 5820 if (vcpu_el1_is_32bit(vcpu)) 5821 vcpu->arch.hcr_el2 &= ~HCR_RW; 5822 5823 if (kvm_has_mte(vcpu->kvm)) 5824 vcpu->arch.hcr_el2 |= HCR_ATA; 5825 else 5826 vcpu->arch.hcr_el2 |= HCR_TID5; 5827 5828 /* 5829 * In the absence of FGT, we cannot independently trap TLBI 5830 * Range instructions. This isn't great, but trapping all 5831 * TLBIs would be far worse. Live with it... 5832 */ 5833 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 5834 vcpu->arch.hcr_el2 |= HCR_TTLBOS; 5835 } 5836 5837 void kvm_calculate_traps(struct kvm_vcpu *vcpu) 5838 { 5839 struct kvm *kvm = vcpu->kvm; 5840 5841 mutex_lock(&kvm->arch.config_lock); 5842 vcpu_set_hcr(vcpu); 5843 vcpu_set_ich_hcr(vcpu); 5844 vcpu_set_hcrx(vcpu); 5845 5846 if (test_bit(KVM_ARCH_FLAG_FGU_INITIALIZED, &kvm->arch.flags)) 5847 goto out; 5848 5849 compute_fgu(kvm, HFGRTR_GROUP); 5850 compute_fgu(kvm, HFGITR_GROUP); 5851 compute_fgu(kvm, HDFGRTR_GROUP); 5852 compute_fgu(kvm, HAFGRTR_GROUP); 5853 compute_fgu(kvm, HFGRTR2_GROUP); 5854 compute_fgu(kvm, HFGITR2_GROUP); 5855 compute_fgu(kvm, HDFGRTR2_GROUP); 5856 compute_fgu(kvm, ICH_HFGRTR_GROUP); 5857 compute_fgu(kvm, ICH_HFGITR_GROUP); 5858 5859 set_bit(KVM_ARCH_FLAG_FGU_INITIALIZED, &kvm->arch.flags); 5860 out: 5861 mutex_unlock(&kvm->arch.config_lock); 5862 } 5863 5864 /* 5865 * Perform last adjustments to the ID registers that are implied by the 5866 * configuration outside of the ID regs themselves, as well as any 5867 * initialisation that directly depend on these ID registers (such as 5868 * RES0/RES1 behaviours). This is not the place to configure traps though. 5869 * 5870 * Because this can be called once per CPU, changes must be idempotent. 5871 */ 5872 int kvm_finalize_sys_regs(struct kvm_vcpu *vcpu) 5873 { 5874 struct kvm *kvm = vcpu->kvm; 5875 5876 guard(mutex)(&kvm->arch.config_lock); 5877 5878 if (vcpu_has_nv(vcpu)) { 5879 int ret = kvm_init_nv_sysregs(vcpu); 5880 if (ret) 5881 return ret; 5882 } 5883 5884 if (kvm_vm_has_ran_once(kvm)) 5885 return 0; 5886 5887 /* 5888 * This hacks into the ID registers, so only perform it when the 5889 * first vcpu runs, or the kvm_set_vm_id_reg() helper will scream. 5890 */ 5891 if (!irqchip_in_kernel(kvm)) { 5892 u64 val; 5893 5894 val = kvm_read_vm_id_reg(kvm, SYS_ID_AA64PFR0_EL1) & ~ID_AA64PFR0_EL1_GIC; 5895 kvm_set_vm_id_reg(kvm, SYS_ID_AA64PFR0_EL1, val); 5896 val = kvm_read_vm_id_reg(kvm, SYS_ID_AA64PFR2_EL1) & ~ID_AA64PFR2_EL1_GCIE; 5897 kvm_set_vm_id_reg(kvm, SYS_ID_AA64PFR2_EL1, val); 5898 val = kvm_read_vm_id_reg(kvm, SYS_ID_PFR1_EL1) & ~ID_PFR1_EL1_GIC; 5899 kvm_set_vm_id_reg(kvm, SYS_ID_PFR1_EL1, val); 5900 } else { 5901 /* 5902 * Certain userspace software - QEMU - samples the system 5903 * register state without creating an irqchip, then blindly 5904 * restores the state prior to running the final guest. This 5905 * means that it restores the virtualization & emulation 5906 * capabilities of the host system, rather than something that 5907 * reflects the final guest state. Moreover, it checks that the 5908 * state was "correctly" restored (i.e., verbatim), bailing if 5909 * it isn't, so masking off invalid state isn't an option. 5910 * 5911 * On GICv5 hardware that supports FEAT_GCIE_LEGACY we can run 5912 * both GICv3- and GICv5-based guests. Therefore, we initially 5913 * present both ID_AA64PFR0.GIC and ID_AA64PFR2.GCIE as IMP to 5914 * reflect that userspace can create EITHER a vGICv3 or a 5915 * vGICv5. This is an architecturally invalid combination, of 5916 * course. Once an in-kernel GIC is created, the sysreg state is 5917 * updated to reflect the actual, valid configuration. 5918 * 5919 * Setting both the GIC and GCIE features to IMP unsurprisingly 5920 * results in guests falling over, and hence we need to fix up 5921 * this mess in KVM. Before running for the first time we yet 5922 * again ensure that the GIC and GCIE fields accurately reflect 5923 * the actual hardware the guest should see. 5924 * 5925 * This hack allows legacy QEMU-based GICv3 guests to run 5926 * unmodified on compatible GICv5 hosts, and avoids the inverse 5927 * problem for GICv5-based guests in the future. 5928 */ 5929 kvm_vgic_finalize_idregs(kvm); 5930 } 5931 5932 return 0; 5933 } 5934 5935 int __init kvm_sys_reg_table_init(void) 5936 { 5937 const struct sys_reg_desc *gicv3_regs; 5938 bool valid = true; 5939 unsigned int i, sz; 5940 int ret = 0; 5941 5942 /* Make sure tables are unique and in order. */ 5943 valid &= check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), true); 5944 valid &= check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), false); 5945 valid &= check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), false); 5946 valid &= check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), false); 5947 valid &= check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), false); 5948 valid &= check_sysreg_table(sys_insn_descs, ARRAY_SIZE(sys_insn_descs), false); 5949 5950 gicv3_regs = vgic_v3_get_sysreg_table(&sz); 5951 valid &= check_sysreg_table(gicv3_regs, sz, false); 5952 5953 if (!valid) 5954 return -EINVAL; 5955 5956 init_imp_id_regs(); 5957 5958 ret = populate_nv_trap_config(); 5959 5960 check_feature_map(); 5961 5962 for (i = 0; !ret && i < ARRAY_SIZE(sys_reg_descs); i++) 5963 ret = populate_sysreg_config(sys_reg_descs + i, i); 5964 5965 for (i = 0; !ret && i < ARRAY_SIZE(sys_insn_descs); i++) 5966 ret = populate_sysreg_config(sys_insn_descs + i, i); 5967 5968 return ret; 5969 } 5970