1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/kvm/coproc.c: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Authors: Rusty Russell <rusty@rustcorp.com.au> 9 * Christoffer Dall <c.dall@virtualopensystems.com> 10 */ 11 12 #include <linux/bitfield.h> 13 #include <linux/bsearch.h> 14 #include <linux/cacheinfo.h> 15 #include <linux/debugfs.h> 16 #include <linux/kvm_host.h> 17 #include <linux/mm.h> 18 #include <linux/printk.h> 19 #include <linux/uaccess.h> 20 21 #include <asm/cacheflush.h> 22 #include <asm/cputype.h> 23 #include <asm/debug-monitors.h> 24 #include <asm/esr.h> 25 #include <asm/kvm_arm.h> 26 #include <asm/kvm_emulate.h> 27 #include <asm/kvm_hyp.h> 28 #include <asm/kvm_mmu.h> 29 #include <asm/kvm_nested.h> 30 #include <asm/perf_event.h> 31 #include <asm/sysreg.h> 32 33 #include <trace/events/kvm.h> 34 35 #include "sys_regs.h" 36 37 #include "trace.h" 38 39 /* 40 * For AArch32, we only take care of what is being trapped. Anything 41 * that has to do with init and userspace access has to go via the 42 * 64bit interface. 43 */ 44 45 static u64 sys_reg_to_index(const struct sys_reg_desc *reg); 46 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 47 u64 val); 48 49 static bool bad_trap(struct kvm_vcpu *vcpu, 50 struct sys_reg_params *params, 51 const struct sys_reg_desc *r, 52 const char *msg) 53 { 54 WARN_ONCE(1, "Unexpected %s\n", msg); 55 print_sys_reg_instr(params); 56 kvm_inject_undefined(vcpu); 57 return false; 58 } 59 60 static bool read_from_write_only(struct kvm_vcpu *vcpu, 61 struct sys_reg_params *params, 62 const struct sys_reg_desc *r) 63 { 64 return bad_trap(vcpu, params, r, 65 "sys_reg read to write-only register"); 66 } 67 68 static bool write_to_read_only(struct kvm_vcpu *vcpu, 69 struct sys_reg_params *params, 70 const struct sys_reg_desc *r) 71 { 72 return bad_trap(vcpu, params, r, 73 "sys_reg write to read-only register"); 74 } 75 76 #define PURE_EL2_SYSREG(el2) \ 77 case el2: { \ 78 *el1r = el2; \ 79 return true; \ 80 } 81 82 #define MAPPED_EL2_SYSREG(el2, el1, fn) \ 83 case el2: { \ 84 *xlate = fn; \ 85 *el1r = el1; \ 86 return true; \ 87 } 88 89 static bool get_el2_to_el1_mapping(unsigned int reg, 90 unsigned int *el1r, u64 (**xlate)(u64)) 91 { 92 switch (reg) { 93 PURE_EL2_SYSREG( VPIDR_EL2 ); 94 PURE_EL2_SYSREG( VMPIDR_EL2 ); 95 PURE_EL2_SYSREG( ACTLR_EL2 ); 96 PURE_EL2_SYSREG( HCR_EL2 ); 97 PURE_EL2_SYSREG( MDCR_EL2 ); 98 PURE_EL2_SYSREG( HSTR_EL2 ); 99 PURE_EL2_SYSREG( HACR_EL2 ); 100 PURE_EL2_SYSREG( VTTBR_EL2 ); 101 PURE_EL2_SYSREG( VTCR_EL2 ); 102 PURE_EL2_SYSREG( RVBAR_EL2 ); 103 PURE_EL2_SYSREG( TPIDR_EL2 ); 104 PURE_EL2_SYSREG( HPFAR_EL2 ); 105 PURE_EL2_SYSREG( CNTHCTL_EL2 ); 106 MAPPED_EL2_SYSREG(SCTLR_EL2, SCTLR_EL1, 107 translate_sctlr_el2_to_sctlr_el1 ); 108 MAPPED_EL2_SYSREG(CPTR_EL2, CPACR_EL1, 109 translate_cptr_el2_to_cpacr_el1 ); 110 MAPPED_EL2_SYSREG(TTBR0_EL2, TTBR0_EL1, 111 translate_ttbr0_el2_to_ttbr0_el1 ); 112 MAPPED_EL2_SYSREG(TTBR1_EL2, TTBR1_EL1, NULL ); 113 MAPPED_EL2_SYSREG(TCR_EL2, TCR_EL1, 114 translate_tcr_el2_to_tcr_el1 ); 115 MAPPED_EL2_SYSREG(VBAR_EL2, VBAR_EL1, NULL ); 116 MAPPED_EL2_SYSREG(AFSR0_EL2, AFSR0_EL1, NULL ); 117 MAPPED_EL2_SYSREG(AFSR1_EL2, AFSR1_EL1, NULL ); 118 MAPPED_EL2_SYSREG(ESR_EL2, ESR_EL1, NULL ); 119 MAPPED_EL2_SYSREG(FAR_EL2, FAR_EL1, NULL ); 120 MAPPED_EL2_SYSREG(MAIR_EL2, MAIR_EL1, NULL ); 121 MAPPED_EL2_SYSREG(AMAIR_EL2, AMAIR_EL1, NULL ); 122 MAPPED_EL2_SYSREG(ELR_EL2, ELR_EL1, NULL ); 123 MAPPED_EL2_SYSREG(SPSR_EL2, SPSR_EL1, NULL ); 124 default: 125 return false; 126 } 127 } 128 129 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg) 130 { 131 u64 val = 0x8badf00d8badf00d; 132 u64 (*xlate)(u64) = NULL; 133 unsigned int el1r; 134 135 if (!vcpu_get_flag(vcpu, SYSREGS_ON_CPU)) 136 goto memory_read; 137 138 if (unlikely(get_el2_to_el1_mapping(reg, &el1r, &xlate))) { 139 if (!is_hyp_ctxt(vcpu)) 140 goto memory_read; 141 142 /* 143 * If this register does not have an EL1 counterpart, 144 * then read the stored EL2 version. 145 */ 146 if (reg == el1r) 147 goto memory_read; 148 149 /* 150 * If we have a non-VHE guest and that the sysreg 151 * requires translation to be used at EL1, use the 152 * in-memory copy instead. 153 */ 154 if (!vcpu_el2_e2h_is_set(vcpu) && xlate) 155 goto memory_read; 156 157 /* Get the current version of the EL1 counterpart. */ 158 WARN_ON(!__vcpu_read_sys_reg_from_cpu(el1r, &val)); 159 return val; 160 } 161 162 /* EL1 register can't be on the CPU if the guest is in vEL2. */ 163 if (unlikely(is_hyp_ctxt(vcpu))) 164 goto memory_read; 165 166 if (__vcpu_read_sys_reg_from_cpu(reg, &val)) 167 return val; 168 169 memory_read: 170 return __vcpu_sys_reg(vcpu, reg); 171 } 172 173 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg) 174 { 175 u64 (*xlate)(u64) = NULL; 176 unsigned int el1r; 177 178 if (!vcpu_get_flag(vcpu, SYSREGS_ON_CPU)) 179 goto memory_write; 180 181 if (unlikely(get_el2_to_el1_mapping(reg, &el1r, &xlate))) { 182 if (!is_hyp_ctxt(vcpu)) 183 goto memory_write; 184 185 /* 186 * Always store a copy of the write to memory to avoid having 187 * to reverse-translate virtual EL2 system registers for a 188 * non-VHE guest hypervisor. 189 */ 190 __vcpu_sys_reg(vcpu, reg) = val; 191 192 /* No EL1 counterpart? We're done here.? */ 193 if (reg == el1r) 194 return; 195 196 if (!vcpu_el2_e2h_is_set(vcpu) && xlate) 197 val = xlate(val); 198 199 /* Redirect this to the EL1 version of the register. */ 200 WARN_ON(!__vcpu_write_sys_reg_to_cpu(val, el1r)); 201 return; 202 } 203 204 /* EL1 register can't be on the CPU if the guest is in vEL2. */ 205 if (unlikely(is_hyp_ctxt(vcpu))) 206 goto memory_write; 207 208 if (__vcpu_write_sys_reg_to_cpu(val, reg)) 209 return; 210 211 memory_write: 212 __vcpu_sys_reg(vcpu, reg) = val; 213 } 214 215 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */ 216 #define CSSELR_MAX 14 217 218 /* 219 * Returns the minimum line size for the selected cache, expressed as 220 * Log2(bytes). 221 */ 222 static u8 get_min_cache_line_size(bool icache) 223 { 224 u64 ctr = read_sanitised_ftr_reg(SYS_CTR_EL0); 225 u8 field; 226 227 if (icache) 228 field = SYS_FIELD_GET(CTR_EL0, IminLine, ctr); 229 else 230 field = SYS_FIELD_GET(CTR_EL0, DminLine, ctr); 231 232 /* 233 * Cache line size is represented as Log2(words) in CTR_EL0. 234 * Log2(bytes) can be derived with the following: 235 * 236 * Log2(words) + 2 = Log2(bytes / 4) + 2 237 * = Log2(bytes) - 2 + 2 238 * = Log2(bytes) 239 */ 240 return field + 2; 241 } 242 243 /* Which cache CCSIDR represents depends on CSSELR value. */ 244 static u32 get_ccsidr(struct kvm_vcpu *vcpu, u32 csselr) 245 { 246 u8 line_size; 247 248 if (vcpu->arch.ccsidr) 249 return vcpu->arch.ccsidr[csselr]; 250 251 line_size = get_min_cache_line_size(csselr & CSSELR_EL1_InD); 252 253 /* 254 * Fabricate a CCSIDR value as the overriding value does not exist. 255 * The real CCSIDR value will not be used as it can vary by the 256 * physical CPU which the vcpu currently resides in. 257 * 258 * The line size is determined with get_min_cache_line_size(), which 259 * should be valid for all CPUs even if they have different cache 260 * configuration. 261 * 262 * The associativity bits are cleared, meaning the geometry of all data 263 * and unified caches (which are guaranteed to be PIPT and thus 264 * non-aliasing) are 1 set and 1 way. 265 * Guests should not be doing cache operations by set/way at all, and 266 * for this reason, we trap them and attempt to infer the intent, so 267 * that we can flush the entire guest's address space at the appropriate 268 * time. The exposed geometry minimizes the number of the traps. 269 * [If guests should attempt to infer aliasing properties from the 270 * geometry (which is not permitted by the architecture), they would 271 * only do so for virtually indexed caches.] 272 * 273 * We don't check if the cache level exists as it is allowed to return 274 * an UNKNOWN value if not. 275 */ 276 return SYS_FIELD_PREP(CCSIDR_EL1, LineSize, line_size - 4); 277 } 278 279 static int set_ccsidr(struct kvm_vcpu *vcpu, u32 csselr, u32 val) 280 { 281 u8 line_size = FIELD_GET(CCSIDR_EL1_LineSize, val) + 4; 282 u32 *ccsidr = vcpu->arch.ccsidr; 283 u32 i; 284 285 if ((val & CCSIDR_EL1_RES0) || 286 line_size < get_min_cache_line_size(csselr & CSSELR_EL1_InD)) 287 return -EINVAL; 288 289 if (!ccsidr) { 290 if (val == get_ccsidr(vcpu, csselr)) 291 return 0; 292 293 ccsidr = kmalloc_array(CSSELR_MAX, sizeof(u32), GFP_KERNEL_ACCOUNT); 294 if (!ccsidr) 295 return -ENOMEM; 296 297 for (i = 0; i < CSSELR_MAX; i++) 298 ccsidr[i] = get_ccsidr(vcpu, i); 299 300 vcpu->arch.ccsidr = ccsidr; 301 } 302 303 ccsidr[csselr] = val; 304 305 return 0; 306 } 307 308 static bool access_rw(struct kvm_vcpu *vcpu, 309 struct sys_reg_params *p, 310 const struct sys_reg_desc *r) 311 { 312 if (p->is_write) 313 vcpu_write_sys_reg(vcpu, p->regval, r->reg); 314 else 315 p->regval = vcpu_read_sys_reg(vcpu, r->reg); 316 317 return true; 318 } 319 320 /* 321 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized). 322 */ 323 static bool access_dcsw(struct kvm_vcpu *vcpu, 324 struct sys_reg_params *p, 325 const struct sys_reg_desc *r) 326 { 327 if (!p->is_write) 328 return read_from_write_only(vcpu, p, r); 329 330 /* 331 * Only track S/W ops if we don't have FWB. It still indicates 332 * that the guest is a bit broken (S/W operations should only 333 * be done by firmware, knowing that there is only a single 334 * CPU left in the system, and certainly not from non-secure 335 * software). 336 */ 337 if (!cpus_have_final_cap(ARM64_HAS_STAGE2_FWB)) 338 kvm_set_way_flush(vcpu); 339 340 return true; 341 } 342 343 static bool access_dcgsw(struct kvm_vcpu *vcpu, 344 struct sys_reg_params *p, 345 const struct sys_reg_desc *r) 346 { 347 if (!kvm_has_mte(vcpu->kvm)) { 348 kvm_inject_undefined(vcpu); 349 return false; 350 } 351 352 /* Treat MTE S/W ops as we treat the classic ones: with contempt */ 353 return access_dcsw(vcpu, p, r); 354 } 355 356 static void get_access_mask(const struct sys_reg_desc *r, u64 *mask, u64 *shift) 357 { 358 switch (r->aarch32_map) { 359 case AA32_LO: 360 *mask = GENMASK_ULL(31, 0); 361 *shift = 0; 362 break; 363 case AA32_HI: 364 *mask = GENMASK_ULL(63, 32); 365 *shift = 32; 366 break; 367 default: 368 *mask = GENMASK_ULL(63, 0); 369 *shift = 0; 370 break; 371 } 372 } 373 374 /* 375 * Generic accessor for VM registers. Only called as long as HCR_TVM 376 * is set. If the guest enables the MMU, we stop trapping the VM 377 * sys_regs and leave it in complete control of the caches. 378 */ 379 static bool access_vm_reg(struct kvm_vcpu *vcpu, 380 struct sys_reg_params *p, 381 const struct sys_reg_desc *r) 382 { 383 bool was_enabled = vcpu_has_cache_enabled(vcpu); 384 u64 val, mask, shift; 385 386 BUG_ON(!p->is_write); 387 388 get_access_mask(r, &mask, &shift); 389 390 if (~mask) { 391 val = vcpu_read_sys_reg(vcpu, r->reg); 392 val &= ~mask; 393 } else { 394 val = 0; 395 } 396 397 val |= (p->regval & (mask >> shift)) << shift; 398 vcpu_write_sys_reg(vcpu, val, r->reg); 399 400 kvm_toggle_cache(vcpu, was_enabled); 401 return true; 402 } 403 404 static bool access_actlr(struct kvm_vcpu *vcpu, 405 struct sys_reg_params *p, 406 const struct sys_reg_desc *r) 407 { 408 u64 mask, shift; 409 410 if (p->is_write) 411 return ignore_write(vcpu, p); 412 413 get_access_mask(r, &mask, &shift); 414 p->regval = (vcpu_read_sys_reg(vcpu, r->reg) & mask) >> shift; 415 416 return true; 417 } 418 419 /* 420 * Trap handler for the GICv3 SGI generation system register. 421 * Forward the request to the VGIC emulation. 422 * The cp15_64 code makes sure this automatically works 423 * for both AArch64 and AArch32 accesses. 424 */ 425 static bool access_gic_sgi(struct kvm_vcpu *vcpu, 426 struct sys_reg_params *p, 427 const struct sys_reg_desc *r) 428 { 429 bool g1; 430 431 if (!p->is_write) 432 return read_from_write_only(vcpu, p, r); 433 434 /* 435 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates 436 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group, 437 * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively 438 * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure 439 * group. 440 */ 441 if (p->Op0 == 0) { /* AArch32 */ 442 switch (p->Op1) { 443 default: /* Keep GCC quiet */ 444 case 0: /* ICC_SGI1R */ 445 g1 = true; 446 break; 447 case 1: /* ICC_ASGI1R */ 448 case 2: /* ICC_SGI0R */ 449 g1 = false; 450 break; 451 } 452 } else { /* AArch64 */ 453 switch (p->Op2) { 454 default: /* Keep GCC quiet */ 455 case 5: /* ICC_SGI1R_EL1 */ 456 g1 = true; 457 break; 458 case 6: /* ICC_ASGI1R_EL1 */ 459 case 7: /* ICC_SGI0R_EL1 */ 460 g1 = false; 461 break; 462 } 463 } 464 465 vgic_v3_dispatch_sgi(vcpu, p->regval, g1); 466 467 return true; 468 } 469 470 static bool access_gic_sre(struct kvm_vcpu *vcpu, 471 struct sys_reg_params *p, 472 const struct sys_reg_desc *r) 473 { 474 if (p->is_write) 475 return ignore_write(vcpu, p); 476 477 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre; 478 return true; 479 } 480 481 static bool trap_raz_wi(struct kvm_vcpu *vcpu, 482 struct sys_reg_params *p, 483 const struct sys_reg_desc *r) 484 { 485 if (p->is_write) 486 return ignore_write(vcpu, p); 487 else 488 return read_zero(vcpu, p); 489 } 490 491 static bool trap_undef(struct kvm_vcpu *vcpu, 492 struct sys_reg_params *p, 493 const struct sys_reg_desc *r) 494 { 495 kvm_inject_undefined(vcpu); 496 return false; 497 } 498 499 /* 500 * ARMv8.1 mandates at least a trivial LORegion implementation, where all the 501 * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0 502 * system, these registers should UNDEF. LORID_EL1 being a RO register, we 503 * treat it separately. 504 */ 505 static bool trap_loregion(struct kvm_vcpu *vcpu, 506 struct sys_reg_params *p, 507 const struct sys_reg_desc *r) 508 { 509 u32 sr = reg_to_encoding(r); 510 511 if (!kvm_has_feat(vcpu->kvm, ID_AA64MMFR1_EL1, LO, IMP)) { 512 kvm_inject_undefined(vcpu); 513 return false; 514 } 515 516 if (p->is_write && sr == SYS_LORID_EL1) 517 return write_to_read_only(vcpu, p, r); 518 519 return trap_raz_wi(vcpu, p, r); 520 } 521 522 static bool trap_oslar_el1(struct kvm_vcpu *vcpu, 523 struct sys_reg_params *p, 524 const struct sys_reg_desc *r) 525 { 526 u64 oslsr; 527 528 if (!p->is_write) 529 return read_from_write_only(vcpu, p, r); 530 531 /* Forward the OSLK bit to OSLSR */ 532 oslsr = __vcpu_sys_reg(vcpu, OSLSR_EL1) & ~OSLSR_EL1_OSLK; 533 if (p->regval & OSLAR_EL1_OSLK) 534 oslsr |= OSLSR_EL1_OSLK; 535 536 __vcpu_sys_reg(vcpu, OSLSR_EL1) = oslsr; 537 return true; 538 } 539 540 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu, 541 struct sys_reg_params *p, 542 const struct sys_reg_desc *r) 543 { 544 if (p->is_write) 545 return write_to_read_only(vcpu, p, r); 546 547 p->regval = __vcpu_sys_reg(vcpu, r->reg); 548 return true; 549 } 550 551 static int set_oslsr_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 552 u64 val) 553 { 554 /* 555 * The only modifiable bit is the OSLK bit. Refuse the write if 556 * userspace attempts to change any other bit in the register. 557 */ 558 if ((val ^ rd->val) & ~OSLSR_EL1_OSLK) 559 return -EINVAL; 560 561 __vcpu_sys_reg(vcpu, rd->reg) = val; 562 return 0; 563 } 564 565 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu, 566 struct sys_reg_params *p, 567 const struct sys_reg_desc *r) 568 { 569 if (p->is_write) { 570 return ignore_write(vcpu, p); 571 } else { 572 p->regval = read_sysreg(dbgauthstatus_el1); 573 return true; 574 } 575 } 576 577 /* 578 * We want to avoid world-switching all the DBG registers all the 579 * time: 580 * 581 * - If we've touched any debug register, it is likely that we're 582 * going to touch more of them. It then makes sense to disable the 583 * traps and start doing the save/restore dance 584 * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is 585 * then mandatory to save/restore the registers, as the guest 586 * depends on them. 587 * 588 * For this, we use a DIRTY bit, indicating the guest has modified the 589 * debug registers, used as follow: 590 * 591 * On guest entry: 592 * - If the dirty bit is set (because we're coming back from trapping), 593 * disable the traps, save host registers, restore guest registers. 594 * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), 595 * set the dirty bit, disable the traps, save host registers, 596 * restore guest registers. 597 * - Otherwise, enable the traps 598 * 599 * On guest exit: 600 * - If the dirty bit is set, save guest registers, restore host 601 * registers and clear the dirty bit. This ensure that the host can 602 * now use the debug registers. 603 */ 604 static bool trap_debug_regs(struct kvm_vcpu *vcpu, 605 struct sys_reg_params *p, 606 const struct sys_reg_desc *r) 607 { 608 access_rw(vcpu, p, r); 609 if (p->is_write) 610 vcpu_set_flag(vcpu, DEBUG_DIRTY); 611 612 trace_trap_reg(__func__, r->reg, p->is_write, p->regval); 613 614 return true; 615 } 616 617 /* 618 * reg_to_dbg/dbg_to_reg 619 * 620 * A 32 bit write to a debug register leave top bits alone 621 * A 32 bit read from a debug register only returns the bottom bits 622 * 623 * All writes will set the DEBUG_DIRTY flag to ensure the hyp code 624 * switches between host and guest values in future. 625 */ 626 static void reg_to_dbg(struct kvm_vcpu *vcpu, 627 struct sys_reg_params *p, 628 const struct sys_reg_desc *rd, 629 u64 *dbg_reg) 630 { 631 u64 mask, shift, val; 632 633 get_access_mask(rd, &mask, &shift); 634 635 val = *dbg_reg; 636 val &= ~mask; 637 val |= (p->regval & (mask >> shift)) << shift; 638 *dbg_reg = val; 639 640 vcpu_set_flag(vcpu, DEBUG_DIRTY); 641 } 642 643 static void dbg_to_reg(struct kvm_vcpu *vcpu, 644 struct sys_reg_params *p, 645 const struct sys_reg_desc *rd, 646 u64 *dbg_reg) 647 { 648 u64 mask, shift; 649 650 get_access_mask(rd, &mask, &shift); 651 p->regval = (*dbg_reg & mask) >> shift; 652 } 653 654 static bool trap_bvr(struct kvm_vcpu *vcpu, 655 struct sys_reg_params *p, 656 const struct sys_reg_desc *rd) 657 { 658 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm]; 659 660 if (p->is_write) 661 reg_to_dbg(vcpu, p, rd, dbg_reg); 662 else 663 dbg_to_reg(vcpu, p, rd, dbg_reg); 664 665 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); 666 667 return true; 668 } 669 670 static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 671 u64 val) 672 { 673 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = val; 674 return 0; 675 } 676 677 static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 678 u64 *val) 679 { 680 *val = vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm]; 681 return 0; 682 } 683 684 static u64 reset_bvr(struct kvm_vcpu *vcpu, 685 const struct sys_reg_desc *rd) 686 { 687 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = rd->val; 688 return rd->val; 689 } 690 691 static bool trap_bcr(struct kvm_vcpu *vcpu, 692 struct sys_reg_params *p, 693 const struct sys_reg_desc *rd) 694 { 695 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm]; 696 697 if (p->is_write) 698 reg_to_dbg(vcpu, p, rd, dbg_reg); 699 else 700 dbg_to_reg(vcpu, p, rd, dbg_reg); 701 702 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); 703 704 return true; 705 } 706 707 static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 708 u64 val) 709 { 710 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = val; 711 return 0; 712 } 713 714 static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 715 u64 *val) 716 { 717 *val = vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm]; 718 return 0; 719 } 720 721 static u64 reset_bcr(struct kvm_vcpu *vcpu, 722 const struct sys_reg_desc *rd) 723 { 724 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = rd->val; 725 return rd->val; 726 } 727 728 static bool trap_wvr(struct kvm_vcpu *vcpu, 729 struct sys_reg_params *p, 730 const struct sys_reg_desc *rd) 731 { 732 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]; 733 734 if (p->is_write) 735 reg_to_dbg(vcpu, p, rd, dbg_reg); 736 else 737 dbg_to_reg(vcpu, p, rd, dbg_reg); 738 739 trace_trap_reg(__func__, rd->CRm, p->is_write, 740 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]); 741 742 return true; 743 } 744 745 static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 746 u64 val) 747 { 748 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = val; 749 return 0; 750 } 751 752 static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 753 u64 *val) 754 { 755 *val = vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]; 756 return 0; 757 } 758 759 static u64 reset_wvr(struct kvm_vcpu *vcpu, 760 const struct sys_reg_desc *rd) 761 { 762 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = rd->val; 763 return rd->val; 764 } 765 766 static bool trap_wcr(struct kvm_vcpu *vcpu, 767 struct sys_reg_params *p, 768 const struct sys_reg_desc *rd) 769 { 770 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm]; 771 772 if (p->is_write) 773 reg_to_dbg(vcpu, p, rd, dbg_reg); 774 else 775 dbg_to_reg(vcpu, p, rd, dbg_reg); 776 777 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); 778 779 return true; 780 } 781 782 static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 783 u64 val) 784 { 785 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = val; 786 return 0; 787 } 788 789 static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 790 u64 *val) 791 { 792 *val = vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm]; 793 return 0; 794 } 795 796 static u64 reset_wcr(struct kvm_vcpu *vcpu, 797 const struct sys_reg_desc *rd) 798 { 799 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = rd->val; 800 return rd->val; 801 } 802 803 static u64 reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 804 { 805 u64 amair = read_sysreg(amair_el1); 806 vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1); 807 return amair; 808 } 809 810 static u64 reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 811 { 812 u64 actlr = read_sysreg(actlr_el1); 813 vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1); 814 return actlr; 815 } 816 817 static u64 reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 818 { 819 u64 mpidr; 820 821 /* 822 * Map the vcpu_id into the first three affinity level fields of 823 * the MPIDR. We limit the number of VCPUs in level 0 due to a 824 * limitation to 16 CPUs in that level in the ICC_SGIxR registers 825 * of the GICv3 to be able to address each CPU directly when 826 * sending IPIs. 827 */ 828 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0); 829 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1); 830 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2); 831 mpidr |= (1ULL << 31); 832 vcpu_write_sys_reg(vcpu, mpidr, MPIDR_EL1); 833 834 return mpidr; 835 } 836 837 static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu, 838 const struct sys_reg_desc *r) 839 { 840 if (kvm_vcpu_has_pmu(vcpu)) 841 return 0; 842 843 return REG_HIDDEN; 844 } 845 846 static u64 reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 847 { 848 u64 mask = BIT(ARMV8_PMU_CYCLE_IDX); 849 u8 n = vcpu->kvm->arch.pmcr_n; 850 851 if (n) 852 mask |= GENMASK(n - 1, 0); 853 854 reset_unknown(vcpu, r); 855 __vcpu_sys_reg(vcpu, r->reg) &= mask; 856 857 return __vcpu_sys_reg(vcpu, r->reg); 858 } 859 860 static u64 reset_pmevcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 861 { 862 reset_unknown(vcpu, r); 863 __vcpu_sys_reg(vcpu, r->reg) &= GENMASK(31, 0); 864 865 return __vcpu_sys_reg(vcpu, r->reg); 866 } 867 868 static u64 reset_pmevtyper(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 869 { 870 /* This thing will UNDEF, who cares about the reset value? */ 871 if (!kvm_vcpu_has_pmu(vcpu)) 872 return 0; 873 874 reset_unknown(vcpu, r); 875 __vcpu_sys_reg(vcpu, r->reg) &= kvm_pmu_evtyper_mask(vcpu->kvm); 876 877 return __vcpu_sys_reg(vcpu, r->reg); 878 } 879 880 static u64 reset_pmselr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 881 { 882 reset_unknown(vcpu, r); 883 __vcpu_sys_reg(vcpu, r->reg) &= ARMV8_PMU_COUNTER_MASK; 884 885 return __vcpu_sys_reg(vcpu, r->reg); 886 } 887 888 static u64 reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 889 { 890 u64 pmcr = 0; 891 892 if (!kvm_supports_32bit_el0()) 893 pmcr |= ARMV8_PMU_PMCR_LC; 894 895 /* 896 * The value of PMCR.N field is included when the 897 * vCPU register is read via kvm_vcpu_read_pmcr(). 898 */ 899 __vcpu_sys_reg(vcpu, r->reg) = pmcr; 900 901 return __vcpu_sys_reg(vcpu, r->reg); 902 } 903 904 static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags) 905 { 906 u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0); 907 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu); 908 909 if (!enabled) 910 kvm_inject_undefined(vcpu); 911 912 return !enabled; 913 } 914 915 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu) 916 { 917 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN); 918 } 919 920 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu) 921 { 922 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN); 923 } 924 925 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu) 926 { 927 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN); 928 } 929 930 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu) 931 { 932 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN); 933 } 934 935 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 936 const struct sys_reg_desc *r) 937 { 938 u64 val; 939 940 if (pmu_access_el0_disabled(vcpu)) 941 return false; 942 943 if (p->is_write) { 944 /* 945 * Only update writeable bits of PMCR (continuing into 946 * kvm_pmu_handle_pmcr() as well) 947 */ 948 val = kvm_vcpu_read_pmcr(vcpu); 949 val &= ~ARMV8_PMU_PMCR_MASK; 950 val |= p->regval & ARMV8_PMU_PMCR_MASK; 951 if (!kvm_supports_32bit_el0()) 952 val |= ARMV8_PMU_PMCR_LC; 953 kvm_pmu_handle_pmcr(vcpu, val); 954 } else { 955 /* PMCR.P & PMCR.C are RAZ */ 956 val = kvm_vcpu_read_pmcr(vcpu) 957 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C); 958 p->regval = val; 959 } 960 961 return true; 962 } 963 964 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 965 const struct sys_reg_desc *r) 966 { 967 if (pmu_access_event_counter_el0_disabled(vcpu)) 968 return false; 969 970 if (p->is_write) 971 __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval; 972 else 973 /* return PMSELR.SEL field */ 974 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0) 975 & ARMV8_PMU_COUNTER_MASK; 976 977 return true; 978 } 979 980 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 981 const struct sys_reg_desc *r) 982 { 983 u64 pmceid, mask, shift; 984 985 BUG_ON(p->is_write); 986 987 if (pmu_access_el0_disabled(vcpu)) 988 return false; 989 990 get_access_mask(r, &mask, &shift); 991 992 pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1)); 993 pmceid &= mask; 994 pmceid >>= shift; 995 996 p->regval = pmceid; 997 998 return true; 999 } 1000 1001 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx) 1002 { 1003 u64 pmcr, val; 1004 1005 pmcr = kvm_vcpu_read_pmcr(vcpu); 1006 val = FIELD_GET(ARMV8_PMU_PMCR_N, pmcr); 1007 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) { 1008 kvm_inject_undefined(vcpu); 1009 return false; 1010 } 1011 1012 return true; 1013 } 1014 1015 static int get_pmu_evcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 1016 u64 *val) 1017 { 1018 u64 idx; 1019 1020 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 0) 1021 /* PMCCNTR_EL0 */ 1022 idx = ARMV8_PMU_CYCLE_IDX; 1023 else 1024 /* PMEVCNTRn_EL0 */ 1025 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 1026 1027 *val = kvm_pmu_get_counter_value(vcpu, idx); 1028 return 0; 1029 } 1030 1031 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu, 1032 struct sys_reg_params *p, 1033 const struct sys_reg_desc *r) 1034 { 1035 u64 idx = ~0UL; 1036 1037 if (r->CRn == 9 && r->CRm == 13) { 1038 if (r->Op2 == 2) { 1039 /* PMXEVCNTR_EL0 */ 1040 if (pmu_access_event_counter_el0_disabled(vcpu)) 1041 return false; 1042 1043 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) 1044 & ARMV8_PMU_COUNTER_MASK; 1045 } else if (r->Op2 == 0) { 1046 /* PMCCNTR_EL0 */ 1047 if (pmu_access_cycle_counter_el0_disabled(vcpu)) 1048 return false; 1049 1050 idx = ARMV8_PMU_CYCLE_IDX; 1051 } 1052 } else if (r->CRn == 0 && r->CRm == 9) { 1053 /* PMCCNTR */ 1054 if (pmu_access_event_counter_el0_disabled(vcpu)) 1055 return false; 1056 1057 idx = ARMV8_PMU_CYCLE_IDX; 1058 } else if (r->CRn == 14 && (r->CRm & 12) == 8) { 1059 /* PMEVCNTRn_EL0 */ 1060 if (pmu_access_event_counter_el0_disabled(vcpu)) 1061 return false; 1062 1063 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 1064 } 1065 1066 /* Catch any decoding mistake */ 1067 WARN_ON(idx == ~0UL); 1068 1069 if (!pmu_counter_idx_valid(vcpu, idx)) 1070 return false; 1071 1072 if (p->is_write) { 1073 if (pmu_access_el0_disabled(vcpu)) 1074 return false; 1075 1076 kvm_pmu_set_counter_value(vcpu, idx, p->regval); 1077 } else { 1078 p->regval = kvm_pmu_get_counter_value(vcpu, idx); 1079 } 1080 1081 return true; 1082 } 1083 1084 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1085 const struct sys_reg_desc *r) 1086 { 1087 u64 idx, reg; 1088 1089 if (pmu_access_el0_disabled(vcpu)) 1090 return false; 1091 1092 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) { 1093 /* PMXEVTYPER_EL0 */ 1094 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK; 1095 reg = PMEVTYPER0_EL0 + idx; 1096 } else if (r->CRn == 14 && (r->CRm & 12) == 12) { 1097 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 1098 if (idx == ARMV8_PMU_CYCLE_IDX) 1099 reg = PMCCFILTR_EL0; 1100 else 1101 /* PMEVTYPERn_EL0 */ 1102 reg = PMEVTYPER0_EL0 + idx; 1103 } else { 1104 BUG(); 1105 } 1106 1107 if (!pmu_counter_idx_valid(vcpu, idx)) 1108 return false; 1109 1110 if (p->is_write) { 1111 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx); 1112 kvm_vcpu_pmu_restore_guest(vcpu); 1113 } else { 1114 p->regval = __vcpu_sys_reg(vcpu, reg); 1115 } 1116 1117 return true; 1118 } 1119 1120 static int set_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 val) 1121 { 1122 bool set; 1123 1124 val &= kvm_pmu_valid_counter_mask(vcpu); 1125 1126 switch (r->reg) { 1127 case PMOVSSET_EL0: 1128 /* CRm[1] being set indicates a SET register, and CLR otherwise */ 1129 set = r->CRm & 2; 1130 break; 1131 default: 1132 /* Op2[0] being set indicates a SET register, and CLR otherwise */ 1133 set = r->Op2 & 1; 1134 break; 1135 } 1136 1137 if (set) 1138 __vcpu_sys_reg(vcpu, r->reg) |= val; 1139 else 1140 __vcpu_sys_reg(vcpu, r->reg) &= ~val; 1141 1142 return 0; 1143 } 1144 1145 static int get_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 *val) 1146 { 1147 u64 mask = kvm_pmu_valid_counter_mask(vcpu); 1148 1149 *val = __vcpu_sys_reg(vcpu, r->reg) & mask; 1150 return 0; 1151 } 1152 1153 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1154 const struct sys_reg_desc *r) 1155 { 1156 u64 val, mask; 1157 1158 if (pmu_access_el0_disabled(vcpu)) 1159 return false; 1160 1161 mask = kvm_pmu_valid_counter_mask(vcpu); 1162 if (p->is_write) { 1163 val = p->regval & mask; 1164 if (r->Op2 & 0x1) { 1165 /* accessing PMCNTENSET_EL0 */ 1166 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val; 1167 kvm_pmu_enable_counter_mask(vcpu, val); 1168 kvm_vcpu_pmu_restore_guest(vcpu); 1169 } else { 1170 /* accessing PMCNTENCLR_EL0 */ 1171 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val; 1172 kvm_pmu_disable_counter_mask(vcpu, val); 1173 } 1174 } else { 1175 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0); 1176 } 1177 1178 return true; 1179 } 1180 1181 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1182 const struct sys_reg_desc *r) 1183 { 1184 u64 mask = kvm_pmu_valid_counter_mask(vcpu); 1185 1186 if (check_pmu_access_disabled(vcpu, 0)) 1187 return false; 1188 1189 if (p->is_write) { 1190 u64 val = p->regval & mask; 1191 1192 if (r->Op2 & 0x1) 1193 /* accessing PMINTENSET_EL1 */ 1194 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val; 1195 else 1196 /* accessing PMINTENCLR_EL1 */ 1197 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val; 1198 } else { 1199 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1); 1200 } 1201 1202 return true; 1203 } 1204 1205 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1206 const struct sys_reg_desc *r) 1207 { 1208 u64 mask = kvm_pmu_valid_counter_mask(vcpu); 1209 1210 if (pmu_access_el0_disabled(vcpu)) 1211 return false; 1212 1213 if (p->is_write) { 1214 if (r->CRm & 0x2) 1215 /* accessing PMOVSSET_EL0 */ 1216 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask); 1217 else 1218 /* accessing PMOVSCLR_EL0 */ 1219 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask); 1220 } else { 1221 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0); 1222 } 1223 1224 return true; 1225 } 1226 1227 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1228 const struct sys_reg_desc *r) 1229 { 1230 u64 mask; 1231 1232 if (!p->is_write) 1233 return read_from_write_only(vcpu, p, r); 1234 1235 if (pmu_write_swinc_el0_disabled(vcpu)) 1236 return false; 1237 1238 mask = kvm_pmu_valid_counter_mask(vcpu); 1239 kvm_pmu_software_increment(vcpu, p->regval & mask); 1240 return true; 1241 } 1242 1243 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1244 const struct sys_reg_desc *r) 1245 { 1246 if (p->is_write) { 1247 if (!vcpu_mode_priv(vcpu)) { 1248 kvm_inject_undefined(vcpu); 1249 return false; 1250 } 1251 1252 __vcpu_sys_reg(vcpu, PMUSERENR_EL0) = 1253 p->regval & ARMV8_PMU_USERENR_MASK; 1254 } else { 1255 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0) 1256 & ARMV8_PMU_USERENR_MASK; 1257 } 1258 1259 return true; 1260 } 1261 1262 static int get_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 1263 u64 *val) 1264 { 1265 *val = kvm_vcpu_read_pmcr(vcpu); 1266 return 0; 1267 } 1268 1269 static int set_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 1270 u64 val) 1271 { 1272 u8 new_n = FIELD_GET(ARMV8_PMU_PMCR_N, val); 1273 struct kvm *kvm = vcpu->kvm; 1274 1275 mutex_lock(&kvm->arch.config_lock); 1276 1277 /* 1278 * The vCPU can't have more counters than the PMU hardware 1279 * implements. Ignore this error to maintain compatibility 1280 * with the existing KVM behavior. 1281 */ 1282 if (!kvm_vm_has_ran_once(kvm) && 1283 new_n <= kvm_arm_pmu_get_max_counters(kvm)) 1284 kvm->arch.pmcr_n = new_n; 1285 1286 mutex_unlock(&kvm->arch.config_lock); 1287 1288 /* 1289 * Ignore writes to RES0 bits, read only bits that are cleared on 1290 * vCPU reset, and writable bits that KVM doesn't support yet. 1291 * (i.e. only PMCR.N and bits [7:0] are mutable from userspace) 1292 * The LP bit is RES0 when FEAT_PMUv3p5 is not supported on the vCPU. 1293 * But, we leave the bit as it is here, as the vCPU's PMUver might 1294 * be changed later (NOTE: the bit will be cleared on first vCPU run 1295 * if necessary). 1296 */ 1297 val &= ARMV8_PMU_PMCR_MASK; 1298 1299 /* The LC bit is RES1 when AArch32 is not supported */ 1300 if (!kvm_supports_32bit_el0()) 1301 val |= ARMV8_PMU_PMCR_LC; 1302 1303 __vcpu_sys_reg(vcpu, r->reg) = val; 1304 return 0; 1305 } 1306 1307 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */ 1308 #define DBG_BCR_BVR_WCR_WVR_EL1(n) \ 1309 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \ 1310 trap_bvr, reset_bvr, 0, 0, get_bvr, set_bvr }, \ 1311 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \ 1312 trap_bcr, reset_bcr, 0, 0, get_bcr, set_bcr }, \ 1313 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \ 1314 trap_wvr, reset_wvr, 0, 0, get_wvr, set_wvr }, \ 1315 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \ 1316 trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr } 1317 1318 #define PMU_SYS_REG(name) \ 1319 SYS_DESC(SYS_##name), .reset = reset_pmu_reg, \ 1320 .visibility = pmu_visibility 1321 1322 /* Macro to expand the PMEVCNTRn_EL0 register */ 1323 #define PMU_PMEVCNTR_EL0(n) \ 1324 { PMU_SYS_REG(PMEVCNTRn_EL0(n)), \ 1325 .reset = reset_pmevcntr, .get_user = get_pmu_evcntr, \ 1326 .access = access_pmu_evcntr, .reg = (PMEVCNTR0_EL0 + n), } 1327 1328 /* Macro to expand the PMEVTYPERn_EL0 register */ 1329 #define PMU_PMEVTYPER_EL0(n) \ 1330 { PMU_SYS_REG(PMEVTYPERn_EL0(n)), \ 1331 .reset = reset_pmevtyper, \ 1332 .access = access_pmu_evtyper, .reg = (PMEVTYPER0_EL0 + n), } 1333 1334 static bool undef_access(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1335 const struct sys_reg_desc *r) 1336 { 1337 kvm_inject_undefined(vcpu); 1338 1339 return false; 1340 } 1341 1342 /* Macro to expand the AMU counter and type registers*/ 1343 #define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), undef_access } 1344 #define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), undef_access } 1345 #define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), undef_access } 1346 #define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), undef_access } 1347 1348 static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu, 1349 const struct sys_reg_desc *rd) 1350 { 1351 return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN; 1352 } 1353 1354 /* 1355 * If we land here on a PtrAuth access, that is because we didn't 1356 * fixup the access on exit by allowing the PtrAuth sysregs. The only 1357 * way this happens is when the guest does not have PtrAuth support 1358 * enabled. 1359 */ 1360 #define __PTRAUTH_KEY(k) \ 1361 { SYS_DESC(SYS_## k), undef_access, reset_unknown, k, \ 1362 .visibility = ptrauth_visibility} 1363 1364 #define PTRAUTH_KEY(k) \ 1365 __PTRAUTH_KEY(k ## KEYLO_EL1), \ 1366 __PTRAUTH_KEY(k ## KEYHI_EL1) 1367 1368 static bool access_arch_timer(struct kvm_vcpu *vcpu, 1369 struct sys_reg_params *p, 1370 const struct sys_reg_desc *r) 1371 { 1372 enum kvm_arch_timers tmr; 1373 enum kvm_arch_timer_regs treg; 1374 u64 reg = reg_to_encoding(r); 1375 1376 switch (reg) { 1377 case SYS_CNTP_TVAL_EL0: 1378 case SYS_AARCH32_CNTP_TVAL: 1379 tmr = TIMER_PTIMER; 1380 treg = TIMER_REG_TVAL; 1381 break; 1382 case SYS_CNTP_CTL_EL0: 1383 case SYS_AARCH32_CNTP_CTL: 1384 tmr = TIMER_PTIMER; 1385 treg = TIMER_REG_CTL; 1386 break; 1387 case SYS_CNTP_CVAL_EL0: 1388 case SYS_AARCH32_CNTP_CVAL: 1389 tmr = TIMER_PTIMER; 1390 treg = TIMER_REG_CVAL; 1391 break; 1392 case SYS_CNTPCT_EL0: 1393 case SYS_CNTPCTSS_EL0: 1394 case SYS_AARCH32_CNTPCT: 1395 tmr = TIMER_PTIMER; 1396 treg = TIMER_REG_CNT; 1397 break; 1398 default: 1399 print_sys_reg_msg(p, "%s", "Unhandled trapped timer register"); 1400 kvm_inject_undefined(vcpu); 1401 return false; 1402 } 1403 1404 if (p->is_write) 1405 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval); 1406 else 1407 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg); 1408 1409 return true; 1410 } 1411 1412 static s64 kvm_arm64_ftr_safe_value(u32 id, const struct arm64_ftr_bits *ftrp, 1413 s64 new, s64 cur) 1414 { 1415 struct arm64_ftr_bits kvm_ftr = *ftrp; 1416 1417 /* Some features have different safe value type in KVM than host features */ 1418 switch (id) { 1419 case SYS_ID_AA64DFR0_EL1: 1420 switch (kvm_ftr.shift) { 1421 case ID_AA64DFR0_EL1_PMUVer_SHIFT: 1422 kvm_ftr.type = FTR_LOWER_SAFE; 1423 break; 1424 case ID_AA64DFR0_EL1_DebugVer_SHIFT: 1425 kvm_ftr.type = FTR_LOWER_SAFE; 1426 break; 1427 } 1428 break; 1429 case SYS_ID_DFR0_EL1: 1430 if (kvm_ftr.shift == ID_DFR0_EL1_PerfMon_SHIFT) 1431 kvm_ftr.type = FTR_LOWER_SAFE; 1432 break; 1433 } 1434 1435 return arm64_ftr_safe_value(&kvm_ftr, new, cur); 1436 } 1437 1438 /* 1439 * arm64_check_features() - Check if a feature register value constitutes 1440 * a subset of features indicated by the idreg's KVM sanitised limit. 1441 * 1442 * This function will check if each feature field of @val is the "safe" value 1443 * against idreg's KVM sanitised limit return from reset() callback. 1444 * If a field value in @val is the same as the one in limit, it is always 1445 * considered the safe value regardless For register fields that are not in 1446 * writable, only the value in limit is considered the safe value. 1447 * 1448 * Return: 0 if all the fields are safe. Otherwise, return negative errno. 1449 */ 1450 static int arm64_check_features(struct kvm_vcpu *vcpu, 1451 const struct sys_reg_desc *rd, 1452 u64 val) 1453 { 1454 const struct arm64_ftr_reg *ftr_reg; 1455 const struct arm64_ftr_bits *ftrp = NULL; 1456 u32 id = reg_to_encoding(rd); 1457 u64 writable_mask = rd->val; 1458 u64 limit = rd->reset(vcpu, rd); 1459 u64 mask = 0; 1460 1461 /* 1462 * Hidden and unallocated ID registers may not have a corresponding 1463 * struct arm64_ftr_reg. Of course, if the register is RAZ we know the 1464 * only safe value is 0. 1465 */ 1466 if (sysreg_visible_as_raz(vcpu, rd)) 1467 return val ? -E2BIG : 0; 1468 1469 ftr_reg = get_arm64_ftr_reg(id); 1470 if (!ftr_reg) 1471 return -EINVAL; 1472 1473 ftrp = ftr_reg->ftr_bits; 1474 1475 for (; ftrp && ftrp->width; ftrp++) { 1476 s64 f_val, f_lim, safe_val; 1477 u64 ftr_mask; 1478 1479 ftr_mask = arm64_ftr_mask(ftrp); 1480 if ((ftr_mask & writable_mask) != ftr_mask) 1481 continue; 1482 1483 f_val = arm64_ftr_value(ftrp, val); 1484 f_lim = arm64_ftr_value(ftrp, limit); 1485 mask |= ftr_mask; 1486 1487 if (f_val == f_lim) 1488 safe_val = f_val; 1489 else 1490 safe_val = kvm_arm64_ftr_safe_value(id, ftrp, f_val, f_lim); 1491 1492 if (safe_val != f_val) 1493 return -E2BIG; 1494 } 1495 1496 /* For fields that are not writable, values in limit are the safe values. */ 1497 if ((val & ~mask) != (limit & ~mask)) 1498 return -E2BIG; 1499 1500 return 0; 1501 } 1502 1503 static u8 pmuver_to_perfmon(u8 pmuver) 1504 { 1505 switch (pmuver) { 1506 case ID_AA64DFR0_EL1_PMUVer_IMP: 1507 return ID_DFR0_EL1_PerfMon_PMUv3; 1508 case ID_AA64DFR0_EL1_PMUVer_IMP_DEF: 1509 return ID_DFR0_EL1_PerfMon_IMPDEF; 1510 default: 1511 /* Anything ARMv8.1+ and NI have the same value. For now. */ 1512 return pmuver; 1513 } 1514 } 1515 1516 /* Read a sanitised cpufeature ID register by sys_reg_desc */ 1517 static u64 __kvm_read_sanitised_id_reg(const struct kvm_vcpu *vcpu, 1518 const struct sys_reg_desc *r) 1519 { 1520 u32 id = reg_to_encoding(r); 1521 u64 val; 1522 1523 if (sysreg_visible_as_raz(vcpu, r)) 1524 return 0; 1525 1526 val = read_sanitised_ftr_reg(id); 1527 1528 switch (id) { 1529 case SYS_ID_AA64PFR1_EL1: 1530 if (!kvm_has_mte(vcpu->kvm)) 1531 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE); 1532 1533 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_SME); 1534 break; 1535 case SYS_ID_AA64ISAR1_EL1: 1536 if (!vcpu_has_ptrauth(vcpu)) 1537 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) | 1538 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) | 1539 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) | 1540 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI)); 1541 break; 1542 case SYS_ID_AA64ISAR2_EL1: 1543 if (!vcpu_has_ptrauth(vcpu)) 1544 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) | 1545 ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3)); 1546 if (!cpus_have_final_cap(ARM64_HAS_WFXT)) 1547 val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT); 1548 break; 1549 case SYS_ID_AA64MMFR2_EL1: 1550 val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK; 1551 break; 1552 case SYS_ID_MMFR4_EL1: 1553 val &= ~ARM64_FEATURE_MASK(ID_MMFR4_EL1_CCIDX); 1554 break; 1555 } 1556 1557 return val; 1558 } 1559 1560 static u64 kvm_read_sanitised_id_reg(struct kvm_vcpu *vcpu, 1561 const struct sys_reg_desc *r) 1562 { 1563 return __kvm_read_sanitised_id_reg(vcpu, r); 1564 } 1565 1566 static u64 read_id_reg(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 1567 { 1568 return IDREG(vcpu->kvm, reg_to_encoding(r)); 1569 } 1570 1571 static bool is_feature_id_reg(u32 encoding) 1572 { 1573 return (sys_reg_Op0(encoding) == 3 && 1574 (sys_reg_Op1(encoding) < 2 || sys_reg_Op1(encoding) == 3) && 1575 sys_reg_CRn(encoding) == 0 && 1576 sys_reg_CRm(encoding) <= 7); 1577 } 1578 1579 /* 1580 * Return true if the register's (Op0, Op1, CRn, CRm, Op2) is 1581 * (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8, which is the range of ID 1582 * registers KVM maintains on a per-VM basis. 1583 */ 1584 static inline bool is_vm_ftr_id_reg(u32 id) 1585 { 1586 return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 && 1587 sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 && 1588 sys_reg_CRm(id) < 8); 1589 } 1590 1591 static inline bool is_vcpu_ftr_id_reg(u32 id) 1592 { 1593 return is_feature_id_reg(id) && !is_vm_ftr_id_reg(id); 1594 } 1595 1596 static inline bool is_aa32_id_reg(u32 id) 1597 { 1598 return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 && 1599 sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 && 1600 sys_reg_CRm(id) <= 3); 1601 } 1602 1603 static unsigned int id_visibility(const struct kvm_vcpu *vcpu, 1604 const struct sys_reg_desc *r) 1605 { 1606 u32 id = reg_to_encoding(r); 1607 1608 switch (id) { 1609 case SYS_ID_AA64ZFR0_EL1: 1610 if (!vcpu_has_sve(vcpu)) 1611 return REG_RAZ; 1612 break; 1613 } 1614 1615 return 0; 1616 } 1617 1618 static unsigned int aa32_id_visibility(const struct kvm_vcpu *vcpu, 1619 const struct sys_reg_desc *r) 1620 { 1621 /* 1622 * AArch32 ID registers are UNKNOWN if AArch32 isn't implemented at any 1623 * EL. Promote to RAZ/WI in order to guarantee consistency between 1624 * systems. 1625 */ 1626 if (!kvm_supports_32bit_el0()) 1627 return REG_RAZ | REG_USER_WI; 1628 1629 return id_visibility(vcpu, r); 1630 } 1631 1632 static unsigned int raz_visibility(const struct kvm_vcpu *vcpu, 1633 const struct sys_reg_desc *r) 1634 { 1635 return REG_RAZ; 1636 } 1637 1638 /* cpufeature ID register access trap handlers */ 1639 1640 static bool access_id_reg(struct kvm_vcpu *vcpu, 1641 struct sys_reg_params *p, 1642 const struct sys_reg_desc *r) 1643 { 1644 if (p->is_write) 1645 return write_to_read_only(vcpu, p, r); 1646 1647 p->regval = read_id_reg(vcpu, r); 1648 1649 return true; 1650 } 1651 1652 /* Visibility overrides for SVE-specific control registers */ 1653 static unsigned int sve_visibility(const struct kvm_vcpu *vcpu, 1654 const struct sys_reg_desc *rd) 1655 { 1656 if (vcpu_has_sve(vcpu)) 1657 return 0; 1658 1659 return REG_HIDDEN; 1660 } 1661 1662 static u64 read_sanitised_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, 1663 const struct sys_reg_desc *rd) 1664 { 1665 u64 val = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1666 1667 if (!vcpu_has_sve(vcpu)) 1668 val &= ~ID_AA64PFR0_EL1_SVE_MASK; 1669 1670 /* 1671 * The default is to expose CSV2 == 1 if the HW isn't affected. 1672 * Although this is a per-CPU feature, we make it global because 1673 * asymmetric systems are just a nuisance. 1674 * 1675 * Userspace can override this as long as it doesn't promise 1676 * the impossible. 1677 */ 1678 if (arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED) { 1679 val &= ~ID_AA64PFR0_EL1_CSV2_MASK; 1680 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV2, IMP); 1681 } 1682 if (arm64_get_meltdown_state() == SPECTRE_UNAFFECTED) { 1683 val &= ~ID_AA64PFR0_EL1_CSV3_MASK; 1684 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV3, IMP); 1685 } 1686 1687 if (kvm_vgic_global_state.type == VGIC_V3) { 1688 val &= ~ID_AA64PFR0_EL1_GIC_MASK; 1689 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, GIC, IMP); 1690 } 1691 1692 val &= ~ID_AA64PFR0_EL1_AMU_MASK; 1693 1694 return val; 1695 } 1696 1697 #define ID_REG_LIMIT_FIELD_ENUM(val, reg, field, limit) \ 1698 ({ \ 1699 u64 __f_val = FIELD_GET(reg##_##field##_MASK, val); \ 1700 (val) &= ~reg##_##field##_MASK; \ 1701 (val) |= FIELD_PREP(reg##_##field##_MASK, \ 1702 min(__f_val, \ 1703 (u64)SYS_FIELD_VALUE(reg, field, limit))); \ 1704 (val); \ 1705 }) 1706 1707 static u64 read_sanitised_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, 1708 const struct sys_reg_desc *rd) 1709 { 1710 u64 val = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); 1711 1712 val = ID_REG_LIMIT_FIELD_ENUM(val, ID_AA64DFR0_EL1, DebugVer, V8P8); 1713 1714 /* 1715 * Only initialize the PMU version if the vCPU was configured with one. 1716 */ 1717 val &= ~ID_AA64DFR0_EL1_PMUVer_MASK; 1718 if (kvm_vcpu_has_pmu(vcpu)) 1719 val |= SYS_FIELD_PREP(ID_AA64DFR0_EL1, PMUVer, 1720 kvm_arm_pmu_get_pmuver_limit()); 1721 1722 /* Hide SPE from guests */ 1723 val &= ~ID_AA64DFR0_EL1_PMSVer_MASK; 1724 1725 return val; 1726 } 1727 1728 static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, 1729 const struct sys_reg_desc *rd, 1730 u64 val) 1731 { 1732 u8 debugver = SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, val); 1733 u8 pmuver = SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, val); 1734 1735 /* 1736 * Prior to commit 3d0dba5764b9 ("KVM: arm64: PMU: Move the 1737 * ID_AA64DFR0_EL1.PMUver limit to VM creation"), KVM erroneously 1738 * exposed an IMP_DEF PMU to userspace and the guest on systems w/ 1739 * non-architectural PMUs. Of course, PMUv3 is the only game in town for 1740 * PMU virtualization, so the IMP_DEF value was rather user-hostile. 1741 * 1742 * At minimum, we're on the hook to allow values that were given to 1743 * userspace by KVM. Cover our tracks here and replace the IMP_DEF value 1744 * with a more sensible NI. The value of an ID register changing under 1745 * the nose of the guest is unfortunate, but is certainly no more 1746 * surprising than an ill-guided PMU driver poking at impdef system 1747 * registers that end in an UNDEF... 1748 */ 1749 if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF) 1750 val &= ~ID_AA64DFR0_EL1_PMUVer_MASK; 1751 1752 /* 1753 * ID_AA64DFR0_EL1.DebugVer is one of those awkward fields with a 1754 * nonzero minimum safe value. 1755 */ 1756 if (debugver < ID_AA64DFR0_EL1_DebugVer_IMP) 1757 return -EINVAL; 1758 1759 return set_id_reg(vcpu, rd, val); 1760 } 1761 1762 static u64 read_sanitised_id_dfr0_el1(struct kvm_vcpu *vcpu, 1763 const struct sys_reg_desc *rd) 1764 { 1765 u8 perfmon = pmuver_to_perfmon(kvm_arm_pmu_get_pmuver_limit()); 1766 u64 val = read_sanitised_ftr_reg(SYS_ID_DFR0_EL1); 1767 1768 val &= ~ID_DFR0_EL1_PerfMon_MASK; 1769 if (kvm_vcpu_has_pmu(vcpu)) 1770 val |= SYS_FIELD_PREP(ID_DFR0_EL1, PerfMon, perfmon); 1771 1772 val = ID_REG_LIMIT_FIELD_ENUM(val, ID_DFR0_EL1, CopDbg, Debugv8p8); 1773 1774 return val; 1775 } 1776 1777 static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, 1778 const struct sys_reg_desc *rd, 1779 u64 val) 1780 { 1781 u8 perfmon = SYS_FIELD_GET(ID_DFR0_EL1, PerfMon, val); 1782 u8 copdbg = SYS_FIELD_GET(ID_DFR0_EL1, CopDbg, val); 1783 1784 if (perfmon == ID_DFR0_EL1_PerfMon_IMPDEF) { 1785 val &= ~ID_DFR0_EL1_PerfMon_MASK; 1786 perfmon = 0; 1787 } 1788 1789 /* 1790 * Allow DFR0_EL1.PerfMon to be set from userspace as long as 1791 * it doesn't promise more than what the HW gives us on the 1792 * AArch64 side (as everything is emulated with that), and 1793 * that this is a PMUv3. 1794 */ 1795 if (perfmon != 0 && perfmon < ID_DFR0_EL1_PerfMon_PMUv3) 1796 return -EINVAL; 1797 1798 if (copdbg < ID_DFR0_EL1_CopDbg_Armv8) 1799 return -EINVAL; 1800 1801 return set_id_reg(vcpu, rd, val); 1802 } 1803 1804 /* 1805 * cpufeature ID register user accessors 1806 * 1807 * For now, these registers are immutable for userspace, so no values 1808 * are stored, and for set_id_reg() we don't allow the effective value 1809 * to be changed. 1810 */ 1811 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1812 u64 *val) 1813 { 1814 /* 1815 * Avoid locking if the VM has already started, as the ID registers are 1816 * guaranteed to be invariant at that point. 1817 */ 1818 if (kvm_vm_has_ran_once(vcpu->kvm)) { 1819 *val = read_id_reg(vcpu, rd); 1820 return 0; 1821 } 1822 1823 mutex_lock(&vcpu->kvm->arch.config_lock); 1824 *val = read_id_reg(vcpu, rd); 1825 mutex_unlock(&vcpu->kvm->arch.config_lock); 1826 1827 return 0; 1828 } 1829 1830 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1831 u64 val) 1832 { 1833 u32 id = reg_to_encoding(rd); 1834 int ret; 1835 1836 mutex_lock(&vcpu->kvm->arch.config_lock); 1837 1838 /* 1839 * Once the VM has started the ID registers are immutable. Reject any 1840 * write that does not match the final register value. 1841 */ 1842 if (kvm_vm_has_ran_once(vcpu->kvm)) { 1843 if (val != read_id_reg(vcpu, rd)) 1844 ret = -EBUSY; 1845 else 1846 ret = 0; 1847 1848 mutex_unlock(&vcpu->kvm->arch.config_lock); 1849 return ret; 1850 } 1851 1852 ret = arm64_check_features(vcpu, rd, val); 1853 if (!ret) 1854 IDREG(vcpu->kvm, id) = val; 1855 1856 mutex_unlock(&vcpu->kvm->arch.config_lock); 1857 1858 /* 1859 * arm64_check_features() returns -E2BIG to indicate the register's 1860 * feature set is a superset of the maximally-allowed register value. 1861 * While it would be nice to precisely describe this to userspace, the 1862 * existing UAPI for KVM_SET_ONE_REG has it that invalid register 1863 * writes return -EINVAL. 1864 */ 1865 if (ret == -E2BIG) 1866 ret = -EINVAL; 1867 return ret; 1868 } 1869 1870 static int get_raz_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1871 u64 *val) 1872 { 1873 *val = 0; 1874 return 0; 1875 } 1876 1877 static int set_wi_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1878 u64 val) 1879 { 1880 return 0; 1881 } 1882 1883 static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1884 const struct sys_reg_desc *r) 1885 { 1886 if (p->is_write) 1887 return write_to_read_only(vcpu, p, r); 1888 1889 p->regval = read_sanitised_ftr_reg(SYS_CTR_EL0); 1890 return true; 1891 } 1892 1893 static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1894 const struct sys_reg_desc *r) 1895 { 1896 if (p->is_write) 1897 return write_to_read_only(vcpu, p, r); 1898 1899 p->regval = __vcpu_sys_reg(vcpu, r->reg); 1900 return true; 1901 } 1902 1903 /* 1904 * Fabricate a CLIDR_EL1 value instead of using the real value, which can vary 1905 * by the physical CPU which the vcpu currently resides in. 1906 */ 1907 static u64 reset_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 1908 { 1909 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0); 1910 u64 clidr; 1911 u8 loc; 1912 1913 if ((ctr_el0 & CTR_EL0_IDC)) { 1914 /* 1915 * Data cache clean to the PoU is not required so LoUU and LoUIS 1916 * will not be set and a unified cache, which will be marked as 1917 * LoC, will be added. 1918 * 1919 * If not DIC, let the unified cache L2 so that an instruction 1920 * cache can be added as L1 later. 1921 */ 1922 loc = (ctr_el0 & CTR_EL0_DIC) ? 1 : 2; 1923 clidr = CACHE_TYPE_UNIFIED << CLIDR_CTYPE_SHIFT(loc); 1924 } else { 1925 /* 1926 * Data cache clean to the PoU is required so let L1 have a data 1927 * cache and mark it as LoUU and LoUIS. As L1 has a data cache, 1928 * it can be marked as LoC too. 1929 */ 1930 loc = 1; 1931 clidr = 1 << CLIDR_LOUU_SHIFT; 1932 clidr |= 1 << CLIDR_LOUIS_SHIFT; 1933 clidr |= CACHE_TYPE_DATA << CLIDR_CTYPE_SHIFT(1); 1934 } 1935 1936 /* 1937 * Instruction cache invalidation to the PoU is required so let L1 have 1938 * an instruction cache. If L1 already has a data cache, it will be 1939 * CACHE_TYPE_SEPARATE. 1940 */ 1941 if (!(ctr_el0 & CTR_EL0_DIC)) 1942 clidr |= CACHE_TYPE_INST << CLIDR_CTYPE_SHIFT(1); 1943 1944 clidr |= loc << CLIDR_LOC_SHIFT; 1945 1946 /* 1947 * Add tag cache unified to data cache. Allocation tags and data are 1948 * unified in a cache line so that it looks valid even if there is only 1949 * one cache line. 1950 */ 1951 if (kvm_has_mte(vcpu->kvm)) 1952 clidr |= 2 << CLIDR_TTYPE_SHIFT(loc); 1953 1954 __vcpu_sys_reg(vcpu, r->reg) = clidr; 1955 1956 return __vcpu_sys_reg(vcpu, r->reg); 1957 } 1958 1959 static int set_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1960 u64 val) 1961 { 1962 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0); 1963 u64 idc = !CLIDR_LOC(val) || (!CLIDR_LOUIS(val) && !CLIDR_LOUU(val)); 1964 1965 if ((val & CLIDR_EL1_RES0) || (!(ctr_el0 & CTR_EL0_IDC) && idc)) 1966 return -EINVAL; 1967 1968 __vcpu_sys_reg(vcpu, rd->reg) = val; 1969 1970 return 0; 1971 } 1972 1973 static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1974 const struct sys_reg_desc *r) 1975 { 1976 int reg = r->reg; 1977 1978 if (p->is_write) 1979 vcpu_write_sys_reg(vcpu, p->regval, reg); 1980 else 1981 p->regval = vcpu_read_sys_reg(vcpu, reg); 1982 return true; 1983 } 1984 1985 static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1986 const struct sys_reg_desc *r) 1987 { 1988 u32 csselr; 1989 1990 if (p->is_write) 1991 return write_to_read_only(vcpu, p, r); 1992 1993 csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1); 1994 csselr &= CSSELR_EL1_Level | CSSELR_EL1_InD; 1995 if (csselr < CSSELR_MAX) 1996 p->regval = get_ccsidr(vcpu, csselr); 1997 1998 return true; 1999 } 2000 2001 static unsigned int mte_visibility(const struct kvm_vcpu *vcpu, 2002 const struct sys_reg_desc *rd) 2003 { 2004 if (kvm_has_mte(vcpu->kvm)) 2005 return 0; 2006 2007 return REG_HIDDEN; 2008 } 2009 2010 #define MTE_REG(name) { \ 2011 SYS_DESC(SYS_##name), \ 2012 .access = undef_access, \ 2013 .reset = reset_unknown, \ 2014 .reg = name, \ 2015 .visibility = mte_visibility, \ 2016 } 2017 2018 static unsigned int el2_visibility(const struct kvm_vcpu *vcpu, 2019 const struct sys_reg_desc *rd) 2020 { 2021 if (vcpu_has_nv(vcpu)) 2022 return 0; 2023 2024 return REG_HIDDEN; 2025 } 2026 2027 static bool bad_vncr_trap(struct kvm_vcpu *vcpu, 2028 struct sys_reg_params *p, 2029 const struct sys_reg_desc *r) 2030 { 2031 /* 2032 * We really shouldn't be here, and this is likely the result 2033 * of a misconfigured trap, as this register should target the 2034 * VNCR page, and nothing else. 2035 */ 2036 return bad_trap(vcpu, p, r, 2037 "trap of VNCR-backed register"); 2038 } 2039 2040 static bool bad_redir_trap(struct kvm_vcpu *vcpu, 2041 struct sys_reg_params *p, 2042 const struct sys_reg_desc *r) 2043 { 2044 /* 2045 * We really shouldn't be here, and this is likely the result 2046 * of a misconfigured trap, as this register should target the 2047 * corresponding EL1, and nothing else. 2048 */ 2049 return bad_trap(vcpu, p, r, 2050 "trap of EL2 register redirected to EL1"); 2051 } 2052 2053 #define EL2_REG(name, acc, rst, v) { \ 2054 SYS_DESC(SYS_##name), \ 2055 .access = acc, \ 2056 .reset = rst, \ 2057 .reg = name, \ 2058 .visibility = el2_visibility, \ 2059 .val = v, \ 2060 } 2061 2062 #define EL2_REG_VNCR(name, rst, v) EL2_REG(name, bad_vncr_trap, rst, v) 2063 #define EL2_REG_REDIR(name, rst, v) EL2_REG(name, bad_redir_trap, rst, v) 2064 2065 /* 2066 * EL{0,1}2 registers are the EL2 view on an EL0 or EL1 register when 2067 * HCR_EL2.E2H==1, and only in the sysreg table for convenience of 2068 * handling traps. Given that, they are always hidden from userspace. 2069 */ 2070 static unsigned int hidden_user_visibility(const struct kvm_vcpu *vcpu, 2071 const struct sys_reg_desc *rd) 2072 { 2073 return REG_HIDDEN_USER; 2074 } 2075 2076 #define EL12_REG(name, acc, rst, v) { \ 2077 SYS_DESC(SYS_##name##_EL12), \ 2078 .access = acc, \ 2079 .reset = rst, \ 2080 .reg = name##_EL1, \ 2081 .val = v, \ 2082 .visibility = hidden_user_visibility, \ 2083 } 2084 2085 /* 2086 * Since reset() callback and field val are not used for idregs, they will be 2087 * used for specific purposes for idregs. 2088 * The reset() would return KVM sanitised register value. The value would be the 2089 * same as the host kernel sanitised value if there is no KVM sanitisation. 2090 * The val would be used as a mask indicating writable fields for the idreg. 2091 * Only bits with 1 are writable from userspace. This mask might not be 2092 * necessary in the future whenever all ID registers are enabled as writable 2093 * from userspace. 2094 */ 2095 2096 #define ID_DESC(name) \ 2097 SYS_DESC(SYS_##name), \ 2098 .access = access_id_reg, \ 2099 .get_user = get_id_reg \ 2100 2101 /* sys_reg_desc initialiser for known cpufeature ID registers */ 2102 #define ID_SANITISED(name) { \ 2103 ID_DESC(name), \ 2104 .set_user = set_id_reg, \ 2105 .visibility = id_visibility, \ 2106 .reset = kvm_read_sanitised_id_reg, \ 2107 .val = 0, \ 2108 } 2109 2110 /* sys_reg_desc initialiser for known cpufeature ID registers */ 2111 #define AA32_ID_SANITISED(name) { \ 2112 ID_DESC(name), \ 2113 .set_user = set_id_reg, \ 2114 .visibility = aa32_id_visibility, \ 2115 .reset = kvm_read_sanitised_id_reg, \ 2116 .val = 0, \ 2117 } 2118 2119 /* sys_reg_desc initialiser for writable ID registers */ 2120 #define ID_WRITABLE(name, mask) { \ 2121 ID_DESC(name), \ 2122 .set_user = set_id_reg, \ 2123 .visibility = id_visibility, \ 2124 .reset = kvm_read_sanitised_id_reg, \ 2125 .val = mask, \ 2126 } 2127 2128 /* 2129 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID 2130 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2 2131 * (1 <= crm < 8, 0 <= Op2 < 8). 2132 */ 2133 #define ID_UNALLOCATED(crm, op2) { \ 2134 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \ 2135 .access = access_id_reg, \ 2136 .get_user = get_id_reg, \ 2137 .set_user = set_id_reg, \ 2138 .visibility = raz_visibility, \ 2139 .reset = kvm_read_sanitised_id_reg, \ 2140 .val = 0, \ 2141 } 2142 2143 /* 2144 * sys_reg_desc initialiser for known ID registers that we hide from guests. 2145 * For now, these are exposed just like unallocated ID regs: they appear 2146 * RAZ for the guest. 2147 */ 2148 #define ID_HIDDEN(name) { \ 2149 ID_DESC(name), \ 2150 .set_user = set_id_reg, \ 2151 .visibility = raz_visibility, \ 2152 .reset = kvm_read_sanitised_id_reg, \ 2153 .val = 0, \ 2154 } 2155 2156 static bool access_sp_el1(struct kvm_vcpu *vcpu, 2157 struct sys_reg_params *p, 2158 const struct sys_reg_desc *r) 2159 { 2160 if (p->is_write) 2161 __vcpu_sys_reg(vcpu, SP_EL1) = p->regval; 2162 else 2163 p->regval = __vcpu_sys_reg(vcpu, SP_EL1); 2164 2165 return true; 2166 } 2167 2168 static bool access_elr(struct kvm_vcpu *vcpu, 2169 struct sys_reg_params *p, 2170 const struct sys_reg_desc *r) 2171 { 2172 if (p->is_write) 2173 vcpu_write_sys_reg(vcpu, p->regval, ELR_EL1); 2174 else 2175 p->regval = vcpu_read_sys_reg(vcpu, ELR_EL1); 2176 2177 return true; 2178 } 2179 2180 static bool access_spsr(struct kvm_vcpu *vcpu, 2181 struct sys_reg_params *p, 2182 const struct sys_reg_desc *r) 2183 { 2184 if (p->is_write) 2185 __vcpu_sys_reg(vcpu, SPSR_EL1) = p->regval; 2186 else 2187 p->regval = __vcpu_sys_reg(vcpu, SPSR_EL1); 2188 2189 return true; 2190 } 2191 2192 static u64 reset_hcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 2193 { 2194 u64 val = r->val; 2195 2196 if (!cpus_have_final_cap(ARM64_HAS_HCR_NV1)) 2197 val |= HCR_E2H; 2198 2199 return __vcpu_sys_reg(vcpu, r->reg) = val; 2200 } 2201 2202 /* 2203 * Architected system registers. 2204 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2 2205 * 2206 * Debug handling: We do trap most, if not all debug related system 2207 * registers. The implementation is good enough to ensure that a guest 2208 * can use these with minimal performance degradation. The drawback is 2209 * that we don't implement any of the external debug architecture. 2210 * This should be revisited if we ever encounter a more demanding 2211 * guest... 2212 */ 2213 static const struct sys_reg_desc sys_reg_descs[] = { 2214 DBG_BCR_BVR_WCR_WVR_EL1(0), 2215 DBG_BCR_BVR_WCR_WVR_EL1(1), 2216 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 }, 2217 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 }, 2218 DBG_BCR_BVR_WCR_WVR_EL1(2), 2219 DBG_BCR_BVR_WCR_WVR_EL1(3), 2220 DBG_BCR_BVR_WCR_WVR_EL1(4), 2221 DBG_BCR_BVR_WCR_WVR_EL1(5), 2222 DBG_BCR_BVR_WCR_WVR_EL1(6), 2223 DBG_BCR_BVR_WCR_WVR_EL1(7), 2224 DBG_BCR_BVR_WCR_WVR_EL1(8), 2225 DBG_BCR_BVR_WCR_WVR_EL1(9), 2226 DBG_BCR_BVR_WCR_WVR_EL1(10), 2227 DBG_BCR_BVR_WCR_WVR_EL1(11), 2228 DBG_BCR_BVR_WCR_WVR_EL1(12), 2229 DBG_BCR_BVR_WCR_WVR_EL1(13), 2230 DBG_BCR_BVR_WCR_WVR_EL1(14), 2231 DBG_BCR_BVR_WCR_WVR_EL1(15), 2232 2233 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi }, 2234 { SYS_DESC(SYS_OSLAR_EL1), trap_oslar_el1 }, 2235 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1, 2236 OSLSR_EL1_OSLM_IMPLEMENTED, .set_user = set_oslsr_el1, }, 2237 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi }, 2238 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi }, 2239 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi }, 2240 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi }, 2241 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 }, 2242 2243 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi }, 2244 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi }, 2245 // DBGDTR[TR]X_EL0 share the same encoding 2246 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi }, 2247 2248 { SYS_DESC(SYS_DBGVCR32_EL2), trap_undef, reset_val, DBGVCR32_EL2, 0 }, 2249 2250 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 }, 2251 2252 /* 2253 * ID regs: all ID_SANITISED() entries here must have corresponding 2254 * entries in arm64_ftr_regs[]. 2255 */ 2256 2257 /* AArch64 mappings of the AArch32 ID registers */ 2258 /* CRm=1 */ 2259 AA32_ID_SANITISED(ID_PFR0_EL1), 2260 AA32_ID_SANITISED(ID_PFR1_EL1), 2261 { SYS_DESC(SYS_ID_DFR0_EL1), 2262 .access = access_id_reg, 2263 .get_user = get_id_reg, 2264 .set_user = set_id_dfr0_el1, 2265 .visibility = aa32_id_visibility, 2266 .reset = read_sanitised_id_dfr0_el1, 2267 .val = ID_DFR0_EL1_PerfMon_MASK | 2268 ID_DFR0_EL1_CopDbg_MASK, }, 2269 ID_HIDDEN(ID_AFR0_EL1), 2270 AA32_ID_SANITISED(ID_MMFR0_EL1), 2271 AA32_ID_SANITISED(ID_MMFR1_EL1), 2272 AA32_ID_SANITISED(ID_MMFR2_EL1), 2273 AA32_ID_SANITISED(ID_MMFR3_EL1), 2274 2275 /* CRm=2 */ 2276 AA32_ID_SANITISED(ID_ISAR0_EL1), 2277 AA32_ID_SANITISED(ID_ISAR1_EL1), 2278 AA32_ID_SANITISED(ID_ISAR2_EL1), 2279 AA32_ID_SANITISED(ID_ISAR3_EL1), 2280 AA32_ID_SANITISED(ID_ISAR4_EL1), 2281 AA32_ID_SANITISED(ID_ISAR5_EL1), 2282 AA32_ID_SANITISED(ID_MMFR4_EL1), 2283 AA32_ID_SANITISED(ID_ISAR6_EL1), 2284 2285 /* CRm=3 */ 2286 AA32_ID_SANITISED(MVFR0_EL1), 2287 AA32_ID_SANITISED(MVFR1_EL1), 2288 AA32_ID_SANITISED(MVFR2_EL1), 2289 ID_UNALLOCATED(3,3), 2290 AA32_ID_SANITISED(ID_PFR2_EL1), 2291 ID_HIDDEN(ID_DFR1_EL1), 2292 AA32_ID_SANITISED(ID_MMFR5_EL1), 2293 ID_UNALLOCATED(3,7), 2294 2295 /* AArch64 ID registers */ 2296 /* CRm=4 */ 2297 { SYS_DESC(SYS_ID_AA64PFR0_EL1), 2298 .access = access_id_reg, 2299 .get_user = get_id_reg, 2300 .set_user = set_id_reg, 2301 .reset = read_sanitised_id_aa64pfr0_el1, 2302 .val = ~(ID_AA64PFR0_EL1_AMU | 2303 ID_AA64PFR0_EL1_MPAM | 2304 ID_AA64PFR0_EL1_SVE | 2305 ID_AA64PFR0_EL1_RAS | 2306 ID_AA64PFR0_EL1_GIC | 2307 ID_AA64PFR0_EL1_AdvSIMD | 2308 ID_AA64PFR0_EL1_FP), }, 2309 ID_SANITISED(ID_AA64PFR1_EL1), 2310 ID_UNALLOCATED(4,2), 2311 ID_UNALLOCATED(4,3), 2312 ID_WRITABLE(ID_AA64ZFR0_EL1, ~ID_AA64ZFR0_EL1_RES0), 2313 ID_HIDDEN(ID_AA64SMFR0_EL1), 2314 ID_UNALLOCATED(4,6), 2315 ID_UNALLOCATED(4,7), 2316 2317 /* CRm=5 */ 2318 { SYS_DESC(SYS_ID_AA64DFR0_EL1), 2319 .access = access_id_reg, 2320 .get_user = get_id_reg, 2321 .set_user = set_id_aa64dfr0_el1, 2322 .reset = read_sanitised_id_aa64dfr0_el1, 2323 .val = ID_AA64DFR0_EL1_PMUVer_MASK | 2324 ID_AA64DFR0_EL1_DebugVer_MASK, }, 2325 ID_SANITISED(ID_AA64DFR1_EL1), 2326 ID_UNALLOCATED(5,2), 2327 ID_UNALLOCATED(5,3), 2328 ID_HIDDEN(ID_AA64AFR0_EL1), 2329 ID_HIDDEN(ID_AA64AFR1_EL1), 2330 ID_UNALLOCATED(5,6), 2331 ID_UNALLOCATED(5,7), 2332 2333 /* CRm=6 */ 2334 ID_WRITABLE(ID_AA64ISAR0_EL1, ~ID_AA64ISAR0_EL1_RES0), 2335 ID_WRITABLE(ID_AA64ISAR1_EL1, ~(ID_AA64ISAR1_EL1_GPI | 2336 ID_AA64ISAR1_EL1_GPA | 2337 ID_AA64ISAR1_EL1_API | 2338 ID_AA64ISAR1_EL1_APA)), 2339 ID_WRITABLE(ID_AA64ISAR2_EL1, ~(ID_AA64ISAR2_EL1_RES0 | 2340 ID_AA64ISAR2_EL1_APA3 | 2341 ID_AA64ISAR2_EL1_GPA3)), 2342 ID_UNALLOCATED(6,3), 2343 ID_UNALLOCATED(6,4), 2344 ID_UNALLOCATED(6,5), 2345 ID_UNALLOCATED(6,6), 2346 ID_UNALLOCATED(6,7), 2347 2348 /* CRm=7 */ 2349 ID_WRITABLE(ID_AA64MMFR0_EL1, ~(ID_AA64MMFR0_EL1_RES0 | 2350 ID_AA64MMFR0_EL1_TGRAN4_2 | 2351 ID_AA64MMFR0_EL1_TGRAN64_2 | 2352 ID_AA64MMFR0_EL1_TGRAN16_2)), 2353 ID_WRITABLE(ID_AA64MMFR1_EL1, ~(ID_AA64MMFR1_EL1_RES0 | 2354 ID_AA64MMFR1_EL1_HCX | 2355 ID_AA64MMFR1_EL1_TWED | 2356 ID_AA64MMFR1_EL1_XNX | 2357 ID_AA64MMFR1_EL1_VH | 2358 ID_AA64MMFR1_EL1_VMIDBits)), 2359 ID_WRITABLE(ID_AA64MMFR2_EL1, ~(ID_AA64MMFR2_EL1_RES0 | 2360 ID_AA64MMFR2_EL1_EVT | 2361 ID_AA64MMFR2_EL1_FWB | 2362 ID_AA64MMFR2_EL1_IDS | 2363 ID_AA64MMFR2_EL1_NV | 2364 ID_AA64MMFR2_EL1_CCIDX)), 2365 ID_SANITISED(ID_AA64MMFR3_EL1), 2366 ID_SANITISED(ID_AA64MMFR4_EL1), 2367 ID_UNALLOCATED(7,5), 2368 ID_UNALLOCATED(7,6), 2369 ID_UNALLOCATED(7,7), 2370 2371 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 }, 2372 { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 }, 2373 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 }, 2374 2375 MTE_REG(RGSR_EL1), 2376 MTE_REG(GCR_EL1), 2377 2378 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility }, 2379 { SYS_DESC(SYS_TRFCR_EL1), undef_access }, 2380 { SYS_DESC(SYS_SMPRI_EL1), undef_access }, 2381 { SYS_DESC(SYS_SMCR_EL1), undef_access }, 2382 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 }, 2383 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 }, 2384 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 }, 2385 { SYS_DESC(SYS_TCR2_EL1), access_vm_reg, reset_val, TCR2_EL1, 0 }, 2386 2387 PTRAUTH_KEY(APIA), 2388 PTRAUTH_KEY(APIB), 2389 PTRAUTH_KEY(APDA), 2390 PTRAUTH_KEY(APDB), 2391 PTRAUTH_KEY(APGA), 2392 2393 { SYS_DESC(SYS_SPSR_EL1), access_spsr}, 2394 { SYS_DESC(SYS_ELR_EL1), access_elr}, 2395 2396 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 }, 2397 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 }, 2398 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 }, 2399 2400 { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi }, 2401 { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi }, 2402 { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi }, 2403 { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi }, 2404 { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi }, 2405 { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi }, 2406 { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi }, 2407 { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi }, 2408 2409 MTE_REG(TFSR_EL1), 2410 MTE_REG(TFSRE0_EL1), 2411 2412 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 }, 2413 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 }, 2414 2415 { SYS_DESC(SYS_PMSCR_EL1), undef_access }, 2416 { SYS_DESC(SYS_PMSNEVFR_EL1), undef_access }, 2417 { SYS_DESC(SYS_PMSICR_EL1), undef_access }, 2418 { SYS_DESC(SYS_PMSIRR_EL1), undef_access }, 2419 { SYS_DESC(SYS_PMSFCR_EL1), undef_access }, 2420 { SYS_DESC(SYS_PMSEVFR_EL1), undef_access }, 2421 { SYS_DESC(SYS_PMSLATFR_EL1), undef_access }, 2422 { SYS_DESC(SYS_PMSIDR_EL1), undef_access }, 2423 { SYS_DESC(SYS_PMBLIMITR_EL1), undef_access }, 2424 { SYS_DESC(SYS_PMBPTR_EL1), undef_access }, 2425 { SYS_DESC(SYS_PMBSR_EL1), undef_access }, 2426 /* PMBIDR_EL1 is not trapped */ 2427 2428 { PMU_SYS_REG(PMINTENSET_EL1), 2429 .access = access_pminten, .reg = PMINTENSET_EL1, 2430 .get_user = get_pmreg, .set_user = set_pmreg }, 2431 { PMU_SYS_REG(PMINTENCLR_EL1), 2432 .access = access_pminten, .reg = PMINTENSET_EL1, 2433 .get_user = get_pmreg, .set_user = set_pmreg }, 2434 { SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi }, 2435 2436 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 }, 2437 { SYS_DESC(SYS_PIRE0_EL1), NULL, reset_unknown, PIRE0_EL1 }, 2438 { SYS_DESC(SYS_PIR_EL1), NULL, reset_unknown, PIR_EL1 }, 2439 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 }, 2440 2441 { SYS_DESC(SYS_LORSA_EL1), trap_loregion }, 2442 { SYS_DESC(SYS_LOREA_EL1), trap_loregion }, 2443 { SYS_DESC(SYS_LORN_EL1), trap_loregion }, 2444 { SYS_DESC(SYS_LORC_EL1), trap_loregion }, 2445 { SYS_DESC(SYS_LORID_EL1), trap_loregion }, 2446 2447 { SYS_DESC(SYS_VBAR_EL1), access_rw, reset_val, VBAR_EL1, 0 }, 2448 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 }, 2449 2450 { SYS_DESC(SYS_ICC_IAR0_EL1), write_to_read_only }, 2451 { SYS_DESC(SYS_ICC_EOIR0_EL1), read_from_write_only }, 2452 { SYS_DESC(SYS_ICC_HPPIR0_EL1), write_to_read_only }, 2453 { SYS_DESC(SYS_ICC_DIR_EL1), read_from_write_only }, 2454 { SYS_DESC(SYS_ICC_RPR_EL1), write_to_read_only }, 2455 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi }, 2456 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi }, 2457 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi }, 2458 { SYS_DESC(SYS_ICC_IAR1_EL1), write_to_read_only }, 2459 { SYS_DESC(SYS_ICC_EOIR1_EL1), read_from_write_only }, 2460 { SYS_DESC(SYS_ICC_HPPIR1_EL1), write_to_read_only }, 2461 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre }, 2462 2463 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 }, 2464 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 }, 2465 2466 { SYS_DESC(SYS_ACCDATA_EL1), undef_access }, 2467 2468 { SYS_DESC(SYS_SCXTNUM_EL1), undef_access }, 2469 2470 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0}, 2471 2472 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr }, 2473 { SYS_DESC(SYS_CLIDR_EL1), access_clidr, reset_clidr, CLIDR_EL1, 2474 .set_user = set_clidr }, 2475 { SYS_DESC(SYS_CCSIDR2_EL1), undef_access }, 2476 { SYS_DESC(SYS_SMIDR_EL1), undef_access }, 2477 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, 2478 { SYS_DESC(SYS_CTR_EL0), access_ctr }, 2479 { SYS_DESC(SYS_SVCR), undef_access }, 2480 2481 { PMU_SYS_REG(PMCR_EL0), .access = access_pmcr, .reset = reset_pmcr, 2482 .reg = PMCR_EL0, .get_user = get_pmcr, .set_user = set_pmcr }, 2483 { PMU_SYS_REG(PMCNTENSET_EL0), 2484 .access = access_pmcnten, .reg = PMCNTENSET_EL0, 2485 .get_user = get_pmreg, .set_user = set_pmreg }, 2486 { PMU_SYS_REG(PMCNTENCLR_EL0), 2487 .access = access_pmcnten, .reg = PMCNTENSET_EL0, 2488 .get_user = get_pmreg, .set_user = set_pmreg }, 2489 { PMU_SYS_REG(PMOVSCLR_EL0), 2490 .access = access_pmovs, .reg = PMOVSSET_EL0, 2491 .get_user = get_pmreg, .set_user = set_pmreg }, 2492 /* 2493 * PM_SWINC_EL0 is exposed to userspace as RAZ/WI, as it was 2494 * previously (and pointlessly) advertised in the past... 2495 */ 2496 { PMU_SYS_REG(PMSWINC_EL0), 2497 .get_user = get_raz_reg, .set_user = set_wi_reg, 2498 .access = access_pmswinc, .reset = NULL }, 2499 { PMU_SYS_REG(PMSELR_EL0), 2500 .access = access_pmselr, .reset = reset_pmselr, .reg = PMSELR_EL0 }, 2501 { PMU_SYS_REG(PMCEID0_EL0), 2502 .access = access_pmceid, .reset = NULL }, 2503 { PMU_SYS_REG(PMCEID1_EL0), 2504 .access = access_pmceid, .reset = NULL }, 2505 { PMU_SYS_REG(PMCCNTR_EL0), 2506 .access = access_pmu_evcntr, .reset = reset_unknown, 2507 .reg = PMCCNTR_EL0, .get_user = get_pmu_evcntr}, 2508 { PMU_SYS_REG(PMXEVTYPER_EL0), 2509 .access = access_pmu_evtyper, .reset = NULL }, 2510 { PMU_SYS_REG(PMXEVCNTR_EL0), 2511 .access = access_pmu_evcntr, .reset = NULL }, 2512 /* 2513 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero 2514 * in 32bit mode. Here we choose to reset it as zero for consistency. 2515 */ 2516 { PMU_SYS_REG(PMUSERENR_EL0), .access = access_pmuserenr, 2517 .reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 }, 2518 { PMU_SYS_REG(PMOVSSET_EL0), 2519 .access = access_pmovs, .reg = PMOVSSET_EL0, 2520 .get_user = get_pmreg, .set_user = set_pmreg }, 2521 2522 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 }, 2523 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 }, 2524 { SYS_DESC(SYS_TPIDR2_EL0), undef_access }, 2525 2526 { SYS_DESC(SYS_SCXTNUM_EL0), undef_access }, 2527 2528 { SYS_DESC(SYS_AMCR_EL0), undef_access }, 2529 { SYS_DESC(SYS_AMCFGR_EL0), undef_access }, 2530 { SYS_DESC(SYS_AMCGCR_EL0), undef_access }, 2531 { SYS_DESC(SYS_AMUSERENR_EL0), undef_access }, 2532 { SYS_DESC(SYS_AMCNTENCLR0_EL0), undef_access }, 2533 { SYS_DESC(SYS_AMCNTENSET0_EL0), undef_access }, 2534 { SYS_DESC(SYS_AMCNTENCLR1_EL0), undef_access }, 2535 { SYS_DESC(SYS_AMCNTENSET1_EL0), undef_access }, 2536 AMU_AMEVCNTR0_EL0(0), 2537 AMU_AMEVCNTR0_EL0(1), 2538 AMU_AMEVCNTR0_EL0(2), 2539 AMU_AMEVCNTR0_EL0(3), 2540 AMU_AMEVCNTR0_EL0(4), 2541 AMU_AMEVCNTR0_EL0(5), 2542 AMU_AMEVCNTR0_EL0(6), 2543 AMU_AMEVCNTR0_EL0(7), 2544 AMU_AMEVCNTR0_EL0(8), 2545 AMU_AMEVCNTR0_EL0(9), 2546 AMU_AMEVCNTR0_EL0(10), 2547 AMU_AMEVCNTR0_EL0(11), 2548 AMU_AMEVCNTR0_EL0(12), 2549 AMU_AMEVCNTR0_EL0(13), 2550 AMU_AMEVCNTR0_EL0(14), 2551 AMU_AMEVCNTR0_EL0(15), 2552 AMU_AMEVTYPER0_EL0(0), 2553 AMU_AMEVTYPER0_EL0(1), 2554 AMU_AMEVTYPER0_EL0(2), 2555 AMU_AMEVTYPER0_EL0(3), 2556 AMU_AMEVTYPER0_EL0(4), 2557 AMU_AMEVTYPER0_EL0(5), 2558 AMU_AMEVTYPER0_EL0(6), 2559 AMU_AMEVTYPER0_EL0(7), 2560 AMU_AMEVTYPER0_EL0(8), 2561 AMU_AMEVTYPER0_EL0(9), 2562 AMU_AMEVTYPER0_EL0(10), 2563 AMU_AMEVTYPER0_EL0(11), 2564 AMU_AMEVTYPER0_EL0(12), 2565 AMU_AMEVTYPER0_EL0(13), 2566 AMU_AMEVTYPER0_EL0(14), 2567 AMU_AMEVTYPER0_EL0(15), 2568 AMU_AMEVCNTR1_EL0(0), 2569 AMU_AMEVCNTR1_EL0(1), 2570 AMU_AMEVCNTR1_EL0(2), 2571 AMU_AMEVCNTR1_EL0(3), 2572 AMU_AMEVCNTR1_EL0(4), 2573 AMU_AMEVCNTR1_EL0(5), 2574 AMU_AMEVCNTR1_EL0(6), 2575 AMU_AMEVCNTR1_EL0(7), 2576 AMU_AMEVCNTR1_EL0(8), 2577 AMU_AMEVCNTR1_EL0(9), 2578 AMU_AMEVCNTR1_EL0(10), 2579 AMU_AMEVCNTR1_EL0(11), 2580 AMU_AMEVCNTR1_EL0(12), 2581 AMU_AMEVCNTR1_EL0(13), 2582 AMU_AMEVCNTR1_EL0(14), 2583 AMU_AMEVCNTR1_EL0(15), 2584 AMU_AMEVTYPER1_EL0(0), 2585 AMU_AMEVTYPER1_EL0(1), 2586 AMU_AMEVTYPER1_EL0(2), 2587 AMU_AMEVTYPER1_EL0(3), 2588 AMU_AMEVTYPER1_EL0(4), 2589 AMU_AMEVTYPER1_EL0(5), 2590 AMU_AMEVTYPER1_EL0(6), 2591 AMU_AMEVTYPER1_EL0(7), 2592 AMU_AMEVTYPER1_EL0(8), 2593 AMU_AMEVTYPER1_EL0(9), 2594 AMU_AMEVTYPER1_EL0(10), 2595 AMU_AMEVTYPER1_EL0(11), 2596 AMU_AMEVTYPER1_EL0(12), 2597 AMU_AMEVTYPER1_EL0(13), 2598 AMU_AMEVTYPER1_EL0(14), 2599 AMU_AMEVTYPER1_EL0(15), 2600 2601 { SYS_DESC(SYS_CNTPCT_EL0), access_arch_timer }, 2602 { SYS_DESC(SYS_CNTPCTSS_EL0), access_arch_timer }, 2603 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer }, 2604 { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer }, 2605 { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer }, 2606 2607 /* PMEVCNTRn_EL0 */ 2608 PMU_PMEVCNTR_EL0(0), 2609 PMU_PMEVCNTR_EL0(1), 2610 PMU_PMEVCNTR_EL0(2), 2611 PMU_PMEVCNTR_EL0(3), 2612 PMU_PMEVCNTR_EL0(4), 2613 PMU_PMEVCNTR_EL0(5), 2614 PMU_PMEVCNTR_EL0(6), 2615 PMU_PMEVCNTR_EL0(7), 2616 PMU_PMEVCNTR_EL0(8), 2617 PMU_PMEVCNTR_EL0(9), 2618 PMU_PMEVCNTR_EL0(10), 2619 PMU_PMEVCNTR_EL0(11), 2620 PMU_PMEVCNTR_EL0(12), 2621 PMU_PMEVCNTR_EL0(13), 2622 PMU_PMEVCNTR_EL0(14), 2623 PMU_PMEVCNTR_EL0(15), 2624 PMU_PMEVCNTR_EL0(16), 2625 PMU_PMEVCNTR_EL0(17), 2626 PMU_PMEVCNTR_EL0(18), 2627 PMU_PMEVCNTR_EL0(19), 2628 PMU_PMEVCNTR_EL0(20), 2629 PMU_PMEVCNTR_EL0(21), 2630 PMU_PMEVCNTR_EL0(22), 2631 PMU_PMEVCNTR_EL0(23), 2632 PMU_PMEVCNTR_EL0(24), 2633 PMU_PMEVCNTR_EL0(25), 2634 PMU_PMEVCNTR_EL0(26), 2635 PMU_PMEVCNTR_EL0(27), 2636 PMU_PMEVCNTR_EL0(28), 2637 PMU_PMEVCNTR_EL0(29), 2638 PMU_PMEVCNTR_EL0(30), 2639 /* PMEVTYPERn_EL0 */ 2640 PMU_PMEVTYPER_EL0(0), 2641 PMU_PMEVTYPER_EL0(1), 2642 PMU_PMEVTYPER_EL0(2), 2643 PMU_PMEVTYPER_EL0(3), 2644 PMU_PMEVTYPER_EL0(4), 2645 PMU_PMEVTYPER_EL0(5), 2646 PMU_PMEVTYPER_EL0(6), 2647 PMU_PMEVTYPER_EL0(7), 2648 PMU_PMEVTYPER_EL0(8), 2649 PMU_PMEVTYPER_EL0(9), 2650 PMU_PMEVTYPER_EL0(10), 2651 PMU_PMEVTYPER_EL0(11), 2652 PMU_PMEVTYPER_EL0(12), 2653 PMU_PMEVTYPER_EL0(13), 2654 PMU_PMEVTYPER_EL0(14), 2655 PMU_PMEVTYPER_EL0(15), 2656 PMU_PMEVTYPER_EL0(16), 2657 PMU_PMEVTYPER_EL0(17), 2658 PMU_PMEVTYPER_EL0(18), 2659 PMU_PMEVTYPER_EL0(19), 2660 PMU_PMEVTYPER_EL0(20), 2661 PMU_PMEVTYPER_EL0(21), 2662 PMU_PMEVTYPER_EL0(22), 2663 PMU_PMEVTYPER_EL0(23), 2664 PMU_PMEVTYPER_EL0(24), 2665 PMU_PMEVTYPER_EL0(25), 2666 PMU_PMEVTYPER_EL0(26), 2667 PMU_PMEVTYPER_EL0(27), 2668 PMU_PMEVTYPER_EL0(28), 2669 PMU_PMEVTYPER_EL0(29), 2670 PMU_PMEVTYPER_EL0(30), 2671 /* 2672 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero 2673 * in 32bit mode. Here we choose to reset it as zero for consistency. 2674 */ 2675 { PMU_SYS_REG(PMCCFILTR_EL0), .access = access_pmu_evtyper, 2676 .reset = reset_val, .reg = PMCCFILTR_EL0, .val = 0 }, 2677 2678 EL2_REG_VNCR(VPIDR_EL2, reset_unknown, 0), 2679 EL2_REG_VNCR(VMPIDR_EL2, reset_unknown, 0), 2680 EL2_REG(SCTLR_EL2, access_rw, reset_val, SCTLR_EL2_RES1), 2681 EL2_REG(ACTLR_EL2, access_rw, reset_val, 0), 2682 EL2_REG_VNCR(HCR_EL2, reset_hcr, 0), 2683 EL2_REG(MDCR_EL2, access_rw, reset_val, 0), 2684 EL2_REG(CPTR_EL2, access_rw, reset_val, CPTR_NVHE_EL2_RES1), 2685 EL2_REG_VNCR(HSTR_EL2, reset_val, 0), 2686 EL2_REG_VNCR(HFGRTR_EL2, reset_val, 0), 2687 EL2_REG_VNCR(HFGWTR_EL2, reset_val, 0), 2688 EL2_REG_VNCR(HFGITR_EL2, reset_val, 0), 2689 EL2_REG_VNCR(HACR_EL2, reset_val, 0), 2690 2691 EL2_REG_VNCR(HCRX_EL2, reset_val, 0), 2692 2693 EL2_REG(TTBR0_EL2, access_rw, reset_val, 0), 2694 EL2_REG(TTBR1_EL2, access_rw, reset_val, 0), 2695 EL2_REG(TCR_EL2, access_rw, reset_val, TCR_EL2_RES1), 2696 EL2_REG_VNCR(VTTBR_EL2, reset_val, 0), 2697 EL2_REG_VNCR(VTCR_EL2, reset_val, 0), 2698 2699 { SYS_DESC(SYS_DACR32_EL2), trap_undef, reset_unknown, DACR32_EL2 }, 2700 EL2_REG_VNCR(HDFGRTR_EL2, reset_val, 0), 2701 EL2_REG_VNCR(HDFGWTR_EL2, reset_val, 0), 2702 EL2_REG_VNCR(HAFGRTR_EL2, reset_val, 0), 2703 EL2_REG_REDIR(SPSR_EL2, reset_val, 0), 2704 EL2_REG_REDIR(ELR_EL2, reset_val, 0), 2705 { SYS_DESC(SYS_SP_EL1), access_sp_el1}, 2706 2707 /* AArch32 SPSR_* are RES0 if trapped from a NV guest */ 2708 { SYS_DESC(SYS_SPSR_irq), .access = trap_raz_wi, 2709 .visibility = hidden_user_visibility }, 2710 { SYS_DESC(SYS_SPSR_abt), .access = trap_raz_wi, 2711 .visibility = hidden_user_visibility }, 2712 { SYS_DESC(SYS_SPSR_und), .access = trap_raz_wi, 2713 .visibility = hidden_user_visibility }, 2714 { SYS_DESC(SYS_SPSR_fiq), .access = trap_raz_wi, 2715 .visibility = hidden_user_visibility }, 2716 2717 { SYS_DESC(SYS_IFSR32_EL2), trap_undef, reset_unknown, IFSR32_EL2 }, 2718 EL2_REG(AFSR0_EL2, access_rw, reset_val, 0), 2719 EL2_REG(AFSR1_EL2, access_rw, reset_val, 0), 2720 EL2_REG_REDIR(ESR_EL2, reset_val, 0), 2721 { SYS_DESC(SYS_FPEXC32_EL2), trap_undef, reset_val, FPEXC32_EL2, 0x700 }, 2722 2723 EL2_REG_REDIR(FAR_EL2, reset_val, 0), 2724 EL2_REG(HPFAR_EL2, access_rw, reset_val, 0), 2725 2726 EL2_REG(MAIR_EL2, access_rw, reset_val, 0), 2727 EL2_REG(AMAIR_EL2, access_rw, reset_val, 0), 2728 2729 EL2_REG(VBAR_EL2, access_rw, reset_val, 0), 2730 EL2_REG(RVBAR_EL2, access_rw, reset_val, 0), 2731 { SYS_DESC(SYS_RMR_EL2), trap_undef }, 2732 2733 EL2_REG(CONTEXTIDR_EL2, access_rw, reset_val, 0), 2734 EL2_REG(TPIDR_EL2, access_rw, reset_val, 0), 2735 2736 EL2_REG_VNCR(CNTVOFF_EL2, reset_val, 0), 2737 EL2_REG(CNTHCTL_EL2, access_rw, reset_val, 0), 2738 2739 EL12_REG(CNTKCTL, access_rw, reset_val, 0), 2740 2741 EL2_REG(SP_EL2, NULL, reset_unknown, 0), 2742 }; 2743 2744 static bool kvm_supported_tlbi_s12_op(struct kvm_vcpu *vpcu, u32 instr) 2745 { 2746 struct kvm *kvm = vpcu->kvm; 2747 u8 CRm = sys_reg_CRm(instr); 2748 2749 if (sys_reg_CRn(instr) == TLBI_CRn_nXS && 2750 !kvm_has_feat(kvm, ID_AA64ISAR1_EL1, XS, IMP)) 2751 return false; 2752 2753 if (CRm == TLBI_CRm_nROS && 2754 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 2755 return false; 2756 2757 return true; 2758 } 2759 2760 static bool handle_alle1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2761 const struct sys_reg_desc *r) 2762 { 2763 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 2764 2765 if (!kvm_supported_tlbi_s12_op(vcpu, sys_encoding)) { 2766 kvm_inject_undefined(vcpu); 2767 return false; 2768 } 2769 2770 write_lock(&vcpu->kvm->mmu_lock); 2771 2772 /* 2773 * Drop all shadow S2s, resulting in S1/S2 TLBIs for each of the 2774 * corresponding VMIDs. 2775 */ 2776 kvm_nested_s2_unmap(vcpu->kvm); 2777 2778 write_unlock(&vcpu->kvm->mmu_lock); 2779 2780 return true; 2781 } 2782 2783 static bool kvm_supported_tlbi_ipas2_op(struct kvm_vcpu *vpcu, u32 instr) 2784 { 2785 struct kvm *kvm = vpcu->kvm; 2786 u8 CRm = sys_reg_CRm(instr); 2787 u8 Op2 = sys_reg_Op2(instr); 2788 2789 if (sys_reg_CRn(instr) == TLBI_CRn_nXS && 2790 !kvm_has_feat(kvm, ID_AA64ISAR1_EL1, XS, IMP)) 2791 return false; 2792 2793 if (CRm == TLBI_CRm_IPAIS && (Op2 == 2 || Op2 == 6) && 2794 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE)) 2795 return false; 2796 2797 if (CRm == TLBI_CRm_IPAONS && (Op2 == 0 || Op2 == 4) && 2798 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 2799 return false; 2800 2801 if (CRm == TLBI_CRm_IPAONS && (Op2 == 3 || Op2 == 7) && 2802 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE)) 2803 return false; 2804 2805 return true; 2806 } 2807 2808 /* Only defined here as this is an internal "abstraction" */ 2809 union tlbi_info { 2810 struct { 2811 u64 start; 2812 u64 size; 2813 } range; 2814 2815 struct { 2816 u64 addr; 2817 } ipa; 2818 2819 struct { 2820 u64 addr; 2821 u32 encoding; 2822 } va; 2823 }; 2824 2825 static void s2_mmu_unmap_range(struct kvm_s2_mmu *mmu, 2826 const union tlbi_info *info) 2827 { 2828 kvm_stage2_unmap_range(mmu, info->range.start, info->range.size); 2829 } 2830 2831 static bool handle_vmalls12e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2832 const struct sys_reg_desc *r) 2833 { 2834 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 2835 u64 limit, vttbr; 2836 2837 if (!kvm_supported_tlbi_s12_op(vcpu, sys_encoding)) { 2838 kvm_inject_undefined(vcpu); 2839 return false; 2840 } 2841 2842 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 2843 limit = BIT_ULL(kvm_get_pa_bits(vcpu->kvm)); 2844 2845 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 2846 &(union tlbi_info) { 2847 .range = { 2848 .start = 0, 2849 .size = limit, 2850 }, 2851 }, 2852 s2_mmu_unmap_range); 2853 2854 return true; 2855 } 2856 2857 static bool handle_ripas2e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2858 const struct sys_reg_desc *r) 2859 { 2860 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 2861 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 2862 u64 base, range, tg, num, scale; 2863 int shift; 2864 2865 if (!kvm_supported_tlbi_ipas2_op(vcpu, sys_encoding)) { 2866 kvm_inject_undefined(vcpu); 2867 return false; 2868 } 2869 2870 /* 2871 * Because the shadow S2 structure doesn't necessarily reflect that 2872 * of the guest's S2 (different base granule size, for example), we 2873 * decide to ignore TTL and only use the described range. 2874 */ 2875 tg = FIELD_GET(GENMASK(47, 46), p->regval); 2876 scale = FIELD_GET(GENMASK(45, 44), p->regval); 2877 num = FIELD_GET(GENMASK(43, 39), p->regval); 2878 base = p->regval & GENMASK(36, 0); 2879 2880 switch(tg) { 2881 case 1: 2882 shift = 12; 2883 break; 2884 case 2: 2885 shift = 14; 2886 break; 2887 case 3: 2888 default: /* IMPDEF: handle tg==0 as 64k */ 2889 shift = 16; 2890 break; 2891 } 2892 2893 base <<= shift; 2894 range = __TLBI_RANGE_PAGES(num, scale) << shift; 2895 2896 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 2897 &(union tlbi_info) { 2898 .range = { 2899 .start = base, 2900 .size = range, 2901 }, 2902 }, 2903 s2_mmu_unmap_range); 2904 2905 return true; 2906 } 2907 2908 static void s2_mmu_unmap_ipa(struct kvm_s2_mmu *mmu, 2909 const union tlbi_info *info) 2910 { 2911 unsigned long max_size; 2912 u64 base_addr; 2913 2914 /* 2915 * We drop a number of things from the supplied value: 2916 * 2917 * - NS bit: we're non-secure only. 2918 * 2919 * - IPA[51:48]: We don't support 52bit IPA just yet... 2920 * 2921 * And of course, adjust the IPA to be on an actual address. 2922 */ 2923 base_addr = (info->ipa.addr & GENMASK_ULL(35, 0)) << 12; 2924 max_size = compute_tlb_inval_range(mmu, info->ipa.addr); 2925 base_addr &= ~(max_size - 1); 2926 2927 kvm_stage2_unmap_range(mmu, base_addr, max_size); 2928 } 2929 2930 static bool handle_ipas2e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2931 const struct sys_reg_desc *r) 2932 { 2933 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 2934 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 2935 2936 if (!kvm_supported_tlbi_ipas2_op(vcpu, sys_encoding)) { 2937 kvm_inject_undefined(vcpu); 2938 return false; 2939 } 2940 2941 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 2942 &(union tlbi_info) { 2943 .ipa = { 2944 .addr = p->regval, 2945 }, 2946 }, 2947 s2_mmu_unmap_ipa); 2948 2949 return true; 2950 } 2951 2952 static void s2_mmu_tlbi_s1e1(struct kvm_s2_mmu *mmu, 2953 const union tlbi_info *info) 2954 { 2955 WARN_ON(__kvm_tlbi_s1e2(mmu, info->va.addr, info->va.encoding)); 2956 } 2957 2958 static bool handle_tlbi_el1(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2959 const struct sys_reg_desc *r) 2960 { 2961 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 2962 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 2963 2964 /* 2965 * If we're here, this is because we've trapped on a EL1 TLBI 2966 * instruction that affects the EL1 translation regime while 2967 * we're running in a context that doesn't allow us to let the 2968 * HW do its thing (aka vEL2): 2969 * 2970 * - HCR_EL2.E2H == 0 : a non-VHE guest 2971 * - HCR_EL2.{E2H,TGE} == { 1, 0 } : a VHE guest in guest mode 2972 * 2973 * We don't expect these helpers to ever be called when running 2974 * in a vEL1 context. 2975 */ 2976 2977 WARN_ON(!vcpu_is_el2(vcpu)); 2978 2979 if (!kvm_supported_tlbi_s1e1_op(vcpu, sys_encoding)) { 2980 kvm_inject_undefined(vcpu); 2981 return false; 2982 } 2983 2984 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 2985 &(union tlbi_info) { 2986 .va = { 2987 .addr = p->regval, 2988 .encoding = sys_encoding, 2989 }, 2990 }, 2991 s2_mmu_tlbi_s1e1); 2992 2993 return true; 2994 } 2995 2996 #define SYS_INSN(insn, access_fn) \ 2997 { \ 2998 SYS_DESC(OP_##insn), \ 2999 .access = (access_fn), \ 3000 } 3001 3002 static struct sys_reg_desc sys_insn_descs[] = { 3003 { SYS_DESC(SYS_DC_ISW), access_dcsw }, 3004 { SYS_DESC(SYS_DC_IGSW), access_dcgsw }, 3005 { SYS_DESC(SYS_DC_IGDSW), access_dcgsw }, 3006 { SYS_DESC(SYS_DC_CSW), access_dcsw }, 3007 { SYS_DESC(SYS_DC_CGSW), access_dcgsw }, 3008 { SYS_DESC(SYS_DC_CGDSW), access_dcgsw }, 3009 { SYS_DESC(SYS_DC_CISW), access_dcsw }, 3010 { SYS_DESC(SYS_DC_CIGSW), access_dcgsw }, 3011 { SYS_DESC(SYS_DC_CIGDSW), access_dcgsw }, 3012 3013 SYS_INSN(TLBI_VMALLE1OS, handle_tlbi_el1), 3014 SYS_INSN(TLBI_VAE1OS, handle_tlbi_el1), 3015 SYS_INSN(TLBI_ASIDE1OS, handle_tlbi_el1), 3016 SYS_INSN(TLBI_VAAE1OS, handle_tlbi_el1), 3017 SYS_INSN(TLBI_VALE1OS, handle_tlbi_el1), 3018 SYS_INSN(TLBI_VAALE1OS, handle_tlbi_el1), 3019 3020 SYS_INSN(TLBI_RVAE1IS, handle_tlbi_el1), 3021 SYS_INSN(TLBI_RVAAE1IS, handle_tlbi_el1), 3022 SYS_INSN(TLBI_RVALE1IS, handle_tlbi_el1), 3023 SYS_INSN(TLBI_RVAALE1IS, handle_tlbi_el1), 3024 3025 SYS_INSN(TLBI_VMALLE1IS, handle_tlbi_el1), 3026 SYS_INSN(TLBI_VAE1IS, handle_tlbi_el1), 3027 SYS_INSN(TLBI_ASIDE1IS, handle_tlbi_el1), 3028 SYS_INSN(TLBI_VAAE1IS, handle_tlbi_el1), 3029 SYS_INSN(TLBI_VALE1IS, handle_tlbi_el1), 3030 SYS_INSN(TLBI_VAALE1IS, handle_tlbi_el1), 3031 3032 SYS_INSN(TLBI_RVAE1OS, handle_tlbi_el1), 3033 SYS_INSN(TLBI_RVAAE1OS, handle_tlbi_el1), 3034 SYS_INSN(TLBI_RVALE1OS, handle_tlbi_el1), 3035 SYS_INSN(TLBI_RVAALE1OS, handle_tlbi_el1), 3036 3037 SYS_INSN(TLBI_RVAE1, handle_tlbi_el1), 3038 SYS_INSN(TLBI_RVAAE1, handle_tlbi_el1), 3039 SYS_INSN(TLBI_RVALE1, handle_tlbi_el1), 3040 SYS_INSN(TLBI_RVAALE1, handle_tlbi_el1), 3041 3042 SYS_INSN(TLBI_VMALLE1, handle_tlbi_el1), 3043 SYS_INSN(TLBI_VAE1, handle_tlbi_el1), 3044 SYS_INSN(TLBI_ASIDE1, handle_tlbi_el1), 3045 SYS_INSN(TLBI_VAAE1, handle_tlbi_el1), 3046 SYS_INSN(TLBI_VALE1, handle_tlbi_el1), 3047 SYS_INSN(TLBI_VAALE1, handle_tlbi_el1), 3048 3049 SYS_INSN(TLBI_VMALLE1OSNXS, handle_tlbi_el1), 3050 SYS_INSN(TLBI_VAE1OSNXS, handle_tlbi_el1), 3051 SYS_INSN(TLBI_ASIDE1OSNXS, handle_tlbi_el1), 3052 SYS_INSN(TLBI_VAAE1OSNXS, handle_tlbi_el1), 3053 SYS_INSN(TLBI_VALE1OSNXS, handle_tlbi_el1), 3054 SYS_INSN(TLBI_VAALE1OSNXS, handle_tlbi_el1), 3055 3056 SYS_INSN(TLBI_RVAE1ISNXS, handle_tlbi_el1), 3057 SYS_INSN(TLBI_RVAAE1ISNXS, handle_tlbi_el1), 3058 SYS_INSN(TLBI_RVALE1ISNXS, handle_tlbi_el1), 3059 SYS_INSN(TLBI_RVAALE1ISNXS, handle_tlbi_el1), 3060 3061 SYS_INSN(TLBI_VMALLE1ISNXS, handle_tlbi_el1), 3062 SYS_INSN(TLBI_VAE1ISNXS, handle_tlbi_el1), 3063 SYS_INSN(TLBI_ASIDE1ISNXS, handle_tlbi_el1), 3064 SYS_INSN(TLBI_VAAE1ISNXS, handle_tlbi_el1), 3065 SYS_INSN(TLBI_VALE1ISNXS, handle_tlbi_el1), 3066 SYS_INSN(TLBI_VAALE1ISNXS, handle_tlbi_el1), 3067 3068 SYS_INSN(TLBI_RVAE1OSNXS, handle_tlbi_el1), 3069 SYS_INSN(TLBI_RVAAE1OSNXS, handle_tlbi_el1), 3070 SYS_INSN(TLBI_RVALE1OSNXS, handle_tlbi_el1), 3071 SYS_INSN(TLBI_RVAALE1OSNXS, handle_tlbi_el1), 3072 3073 SYS_INSN(TLBI_RVAE1NXS, handle_tlbi_el1), 3074 SYS_INSN(TLBI_RVAAE1NXS, handle_tlbi_el1), 3075 SYS_INSN(TLBI_RVALE1NXS, handle_tlbi_el1), 3076 SYS_INSN(TLBI_RVAALE1NXS, handle_tlbi_el1), 3077 3078 SYS_INSN(TLBI_VMALLE1NXS, handle_tlbi_el1), 3079 SYS_INSN(TLBI_VAE1NXS, handle_tlbi_el1), 3080 SYS_INSN(TLBI_ASIDE1NXS, handle_tlbi_el1), 3081 SYS_INSN(TLBI_VAAE1NXS, handle_tlbi_el1), 3082 SYS_INSN(TLBI_VALE1NXS, handle_tlbi_el1), 3083 SYS_INSN(TLBI_VAALE1NXS, handle_tlbi_el1), 3084 3085 SYS_INSN(TLBI_IPAS2E1IS, handle_ipas2e1is), 3086 SYS_INSN(TLBI_RIPAS2E1IS, handle_ripas2e1is), 3087 SYS_INSN(TLBI_IPAS2LE1IS, handle_ipas2e1is), 3088 SYS_INSN(TLBI_RIPAS2LE1IS, handle_ripas2e1is), 3089 3090 SYS_INSN(TLBI_ALLE2OS, trap_undef), 3091 SYS_INSN(TLBI_VAE2OS, trap_undef), 3092 SYS_INSN(TLBI_ALLE1OS, handle_alle1is), 3093 SYS_INSN(TLBI_VALE2OS, trap_undef), 3094 SYS_INSN(TLBI_VMALLS12E1OS, handle_vmalls12e1is), 3095 3096 SYS_INSN(TLBI_RVAE2IS, trap_undef), 3097 SYS_INSN(TLBI_RVALE2IS, trap_undef), 3098 3099 SYS_INSN(TLBI_ALLE1IS, handle_alle1is), 3100 SYS_INSN(TLBI_VMALLS12E1IS, handle_vmalls12e1is), 3101 SYS_INSN(TLBI_IPAS2E1OS, handle_ipas2e1is), 3102 SYS_INSN(TLBI_IPAS2E1, handle_ipas2e1is), 3103 SYS_INSN(TLBI_RIPAS2E1, handle_ripas2e1is), 3104 SYS_INSN(TLBI_RIPAS2E1OS, handle_ripas2e1is), 3105 SYS_INSN(TLBI_IPAS2LE1OS, handle_ipas2e1is), 3106 SYS_INSN(TLBI_IPAS2LE1, handle_ipas2e1is), 3107 SYS_INSN(TLBI_RIPAS2LE1, handle_ripas2e1is), 3108 SYS_INSN(TLBI_RIPAS2LE1OS, handle_ripas2e1is), 3109 SYS_INSN(TLBI_RVAE2OS, trap_undef), 3110 SYS_INSN(TLBI_RVALE2OS, trap_undef), 3111 SYS_INSN(TLBI_RVAE2, trap_undef), 3112 SYS_INSN(TLBI_RVALE2, trap_undef), 3113 SYS_INSN(TLBI_ALLE1, handle_alle1is), 3114 SYS_INSN(TLBI_VMALLS12E1, handle_vmalls12e1is), 3115 3116 SYS_INSN(TLBI_IPAS2E1ISNXS, handle_ipas2e1is), 3117 SYS_INSN(TLBI_RIPAS2E1ISNXS, handle_ripas2e1is), 3118 SYS_INSN(TLBI_IPAS2LE1ISNXS, handle_ipas2e1is), 3119 SYS_INSN(TLBI_RIPAS2LE1ISNXS, handle_ripas2e1is), 3120 3121 SYS_INSN(TLBI_ALLE2OSNXS, trap_undef), 3122 SYS_INSN(TLBI_VAE2OSNXS, trap_undef), 3123 SYS_INSN(TLBI_ALLE1OSNXS, handle_alle1is), 3124 SYS_INSN(TLBI_VALE2OSNXS, trap_undef), 3125 SYS_INSN(TLBI_VMALLS12E1OSNXS, handle_vmalls12e1is), 3126 3127 SYS_INSN(TLBI_RVAE2ISNXS, trap_undef), 3128 SYS_INSN(TLBI_RVALE2ISNXS, trap_undef), 3129 SYS_INSN(TLBI_ALLE2ISNXS, trap_undef), 3130 SYS_INSN(TLBI_VAE2ISNXS, trap_undef), 3131 3132 SYS_INSN(TLBI_ALLE1ISNXS, handle_alle1is), 3133 SYS_INSN(TLBI_VALE2ISNXS, trap_undef), 3134 SYS_INSN(TLBI_VMALLS12E1ISNXS, handle_vmalls12e1is), 3135 SYS_INSN(TLBI_IPAS2E1OSNXS, handle_ipas2e1is), 3136 SYS_INSN(TLBI_IPAS2E1NXS, handle_ipas2e1is), 3137 SYS_INSN(TLBI_RIPAS2E1NXS, handle_ripas2e1is), 3138 SYS_INSN(TLBI_RIPAS2E1OSNXS, handle_ripas2e1is), 3139 SYS_INSN(TLBI_IPAS2LE1OSNXS, handle_ipas2e1is), 3140 SYS_INSN(TLBI_IPAS2LE1NXS, handle_ipas2e1is), 3141 SYS_INSN(TLBI_RIPAS2LE1NXS, handle_ripas2e1is), 3142 SYS_INSN(TLBI_RIPAS2LE1OSNXS, handle_ripas2e1is), 3143 SYS_INSN(TLBI_RVAE2OSNXS, trap_undef), 3144 SYS_INSN(TLBI_RVALE2OSNXS, trap_undef), 3145 SYS_INSN(TLBI_RVAE2NXS, trap_undef), 3146 SYS_INSN(TLBI_RVALE2NXS, trap_undef), 3147 SYS_INSN(TLBI_ALLE2NXS, trap_undef), 3148 SYS_INSN(TLBI_VAE2NXS, trap_undef), 3149 SYS_INSN(TLBI_ALLE1NXS, handle_alle1is), 3150 SYS_INSN(TLBI_VALE2NXS, trap_undef), 3151 SYS_INSN(TLBI_VMALLS12E1NXS, handle_vmalls12e1is), 3152 }; 3153 3154 static const struct sys_reg_desc *first_idreg; 3155 3156 static bool trap_dbgdidr(struct kvm_vcpu *vcpu, 3157 struct sys_reg_params *p, 3158 const struct sys_reg_desc *r) 3159 { 3160 if (p->is_write) { 3161 return ignore_write(vcpu, p); 3162 } else { 3163 u64 dfr = IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1); 3164 u32 el3 = kvm_has_feat(vcpu->kvm, ID_AA64PFR0_EL1, EL3, IMP); 3165 3166 p->regval = ((SYS_FIELD_GET(ID_AA64DFR0_EL1, WRPs, dfr) << 28) | 3167 (SYS_FIELD_GET(ID_AA64DFR0_EL1, BRPs, dfr) << 24) | 3168 (SYS_FIELD_GET(ID_AA64DFR0_EL1, CTX_CMPs, dfr) << 20) | 3169 (SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, dfr) << 16) | 3170 (1 << 15) | (el3 << 14) | (el3 << 12)); 3171 return true; 3172 } 3173 } 3174 3175 /* 3176 * AArch32 debug register mappings 3177 * 3178 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0] 3179 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32] 3180 * 3181 * None of the other registers share their location, so treat them as 3182 * if they were 64bit. 3183 */ 3184 #define DBG_BCR_BVR_WCR_WVR(n) \ 3185 /* DBGBVRn */ \ 3186 { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \ 3187 /* DBGBCRn */ \ 3188 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \ 3189 /* DBGWVRn */ \ 3190 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \ 3191 /* DBGWCRn */ \ 3192 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n } 3193 3194 #define DBGBXVR(n) \ 3195 { AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_bvr, NULL, n } 3196 3197 /* 3198 * Trapped cp14 registers. We generally ignore most of the external 3199 * debug, on the principle that they don't really make sense to a 3200 * guest. Revisit this one day, would this principle change. 3201 */ 3202 static const struct sys_reg_desc cp14_regs[] = { 3203 /* DBGDIDR */ 3204 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgdidr }, 3205 /* DBGDTRRXext */ 3206 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi }, 3207 3208 DBG_BCR_BVR_WCR_WVR(0), 3209 /* DBGDSCRint */ 3210 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi }, 3211 DBG_BCR_BVR_WCR_WVR(1), 3212 /* DBGDCCINT */ 3213 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug_regs, NULL, MDCCINT_EL1 }, 3214 /* DBGDSCRext */ 3215 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug_regs, NULL, MDSCR_EL1 }, 3216 DBG_BCR_BVR_WCR_WVR(2), 3217 /* DBGDTR[RT]Xint */ 3218 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi }, 3219 /* DBGDTR[RT]Xext */ 3220 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi }, 3221 DBG_BCR_BVR_WCR_WVR(3), 3222 DBG_BCR_BVR_WCR_WVR(4), 3223 DBG_BCR_BVR_WCR_WVR(5), 3224 /* DBGWFAR */ 3225 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi }, 3226 /* DBGOSECCR */ 3227 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi }, 3228 DBG_BCR_BVR_WCR_WVR(6), 3229 /* DBGVCR */ 3230 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug_regs, NULL, DBGVCR32_EL2 }, 3231 DBG_BCR_BVR_WCR_WVR(7), 3232 DBG_BCR_BVR_WCR_WVR(8), 3233 DBG_BCR_BVR_WCR_WVR(9), 3234 DBG_BCR_BVR_WCR_WVR(10), 3235 DBG_BCR_BVR_WCR_WVR(11), 3236 DBG_BCR_BVR_WCR_WVR(12), 3237 DBG_BCR_BVR_WCR_WVR(13), 3238 DBG_BCR_BVR_WCR_WVR(14), 3239 DBG_BCR_BVR_WCR_WVR(15), 3240 3241 /* DBGDRAR (32bit) */ 3242 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi }, 3243 3244 DBGBXVR(0), 3245 /* DBGOSLAR */ 3246 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_oslar_el1 }, 3247 DBGBXVR(1), 3248 /* DBGOSLSR */ 3249 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1, NULL, OSLSR_EL1 }, 3250 DBGBXVR(2), 3251 DBGBXVR(3), 3252 /* DBGOSDLR */ 3253 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi }, 3254 DBGBXVR(4), 3255 /* DBGPRCR */ 3256 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi }, 3257 DBGBXVR(5), 3258 DBGBXVR(6), 3259 DBGBXVR(7), 3260 DBGBXVR(8), 3261 DBGBXVR(9), 3262 DBGBXVR(10), 3263 DBGBXVR(11), 3264 DBGBXVR(12), 3265 DBGBXVR(13), 3266 DBGBXVR(14), 3267 DBGBXVR(15), 3268 3269 /* DBGDSAR (32bit) */ 3270 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi }, 3271 3272 /* DBGDEVID2 */ 3273 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi }, 3274 /* DBGDEVID1 */ 3275 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi }, 3276 /* DBGDEVID */ 3277 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi }, 3278 /* DBGCLAIMSET */ 3279 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi }, 3280 /* DBGCLAIMCLR */ 3281 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi }, 3282 /* DBGAUTHSTATUS */ 3283 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 }, 3284 }; 3285 3286 /* Trapped cp14 64bit registers */ 3287 static const struct sys_reg_desc cp14_64_regs[] = { 3288 /* DBGDRAR (64bit) */ 3289 { Op1( 0), CRm( 1), .access = trap_raz_wi }, 3290 3291 /* DBGDSAR (64bit) */ 3292 { Op1( 0), CRm( 2), .access = trap_raz_wi }, 3293 }; 3294 3295 #define CP15_PMU_SYS_REG(_map, _Op1, _CRn, _CRm, _Op2) \ 3296 AA32(_map), \ 3297 Op1(_Op1), CRn(_CRn), CRm(_CRm), Op2(_Op2), \ 3298 .visibility = pmu_visibility 3299 3300 /* Macro to expand the PMEVCNTRn register */ 3301 #define PMU_PMEVCNTR(n) \ 3302 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \ 3303 (0b1000 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \ 3304 .access = access_pmu_evcntr } 3305 3306 /* Macro to expand the PMEVTYPERn register */ 3307 #define PMU_PMEVTYPER(n) \ 3308 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \ 3309 (0b1100 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \ 3310 .access = access_pmu_evtyper } 3311 /* 3312 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding, 3313 * depending on the way they are accessed (as a 32bit or a 64bit 3314 * register). 3315 */ 3316 static const struct sys_reg_desc cp15_regs[] = { 3317 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr }, 3318 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, SCTLR_EL1 }, 3319 /* ACTLR */ 3320 { AA32(LO), Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr, NULL, ACTLR_EL1 }, 3321 /* ACTLR2 */ 3322 { AA32(HI), Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr, NULL, ACTLR_EL1 }, 3323 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, 3324 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, TTBR1_EL1 }, 3325 /* TTBCR */ 3326 { AA32(LO), Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 }, 3327 /* TTBCR2 */ 3328 { AA32(HI), Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, TCR_EL1 }, 3329 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, DACR32_EL2 }, 3330 /* DFSR */ 3331 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, ESR_EL1 }, 3332 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, IFSR32_EL2 }, 3333 /* ADFSR */ 3334 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, AFSR0_EL1 }, 3335 /* AIFSR */ 3336 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, AFSR1_EL1 }, 3337 /* DFAR */ 3338 { AA32(LO), Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, FAR_EL1 }, 3339 /* IFAR */ 3340 { AA32(HI), Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, FAR_EL1 }, 3341 3342 /* 3343 * DC{C,I,CI}SW operations: 3344 */ 3345 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw }, 3346 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw }, 3347 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw }, 3348 3349 /* PMU */ 3350 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 0), .access = access_pmcr }, 3351 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 1), .access = access_pmcnten }, 3352 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 2), .access = access_pmcnten }, 3353 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 3), .access = access_pmovs }, 3354 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 4), .access = access_pmswinc }, 3355 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 5), .access = access_pmselr }, 3356 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 6), .access = access_pmceid }, 3357 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 7), .access = access_pmceid }, 3358 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 0), .access = access_pmu_evcntr }, 3359 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 1), .access = access_pmu_evtyper }, 3360 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 2), .access = access_pmu_evcntr }, 3361 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 0), .access = access_pmuserenr }, 3362 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 1), .access = access_pminten }, 3363 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 2), .access = access_pminten }, 3364 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 3), .access = access_pmovs }, 3365 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 4), .access = access_pmceid }, 3366 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 5), .access = access_pmceid }, 3367 /* PMMIR */ 3368 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 6), .access = trap_raz_wi }, 3369 3370 /* PRRR/MAIR0 */ 3371 { AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 }, 3372 /* NMRR/MAIR1 */ 3373 { AA32(HI), Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, MAIR_EL1 }, 3374 /* AMAIR0 */ 3375 { AA32(LO), Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, AMAIR_EL1 }, 3376 /* AMAIR1 */ 3377 { AA32(HI), Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, AMAIR_EL1 }, 3378 3379 /* ICC_SRE */ 3380 { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre }, 3381 3382 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, CONTEXTIDR_EL1 }, 3383 3384 /* Arch Tmers */ 3385 { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer }, 3386 { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer }, 3387 3388 /* PMEVCNTRn */ 3389 PMU_PMEVCNTR(0), 3390 PMU_PMEVCNTR(1), 3391 PMU_PMEVCNTR(2), 3392 PMU_PMEVCNTR(3), 3393 PMU_PMEVCNTR(4), 3394 PMU_PMEVCNTR(5), 3395 PMU_PMEVCNTR(6), 3396 PMU_PMEVCNTR(7), 3397 PMU_PMEVCNTR(8), 3398 PMU_PMEVCNTR(9), 3399 PMU_PMEVCNTR(10), 3400 PMU_PMEVCNTR(11), 3401 PMU_PMEVCNTR(12), 3402 PMU_PMEVCNTR(13), 3403 PMU_PMEVCNTR(14), 3404 PMU_PMEVCNTR(15), 3405 PMU_PMEVCNTR(16), 3406 PMU_PMEVCNTR(17), 3407 PMU_PMEVCNTR(18), 3408 PMU_PMEVCNTR(19), 3409 PMU_PMEVCNTR(20), 3410 PMU_PMEVCNTR(21), 3411 PMU_PMEVCNTR(22), 3412 PMU_PMEVCNTR(23), 3413 PMU_PMEVCNTR(24), 3414 PMU_PMEVCNTR(25), 3415 PMU_PMEVCNTR(26), 3416 PMU_PMEVCNTR(27), 3417 PMU_PMEVCNTR(28), 3418 PMU_PMEVCNTR(29), 3419 PMU_PMEVCNTR(30), 3420 /* PMEVTYPERn */ 3421 PMU_PMEVTYPER(0), 3422 PMU_PMEVTYPER(1), 3423 PMU_PMEVTYPER(2), 3424 PMU_PMEVTYPER(3), 3425 PMU_PMEVTYPER(4), 3426 PMU_PMEVTYPER(5), 3427 PMU_PMEVTYPER(6), 3428 PMU_PMEVTYPER(7), 3429 PMU_PMEVTYPER(8), 3430 PMU_PMEVTYPER(9), 3431 PMU_PMEVTYPER(10), 3432 PMU_PMEVTYPER(11), 3433 PMU_PMEVTYPER(12), 3434 PMU_PMEVTYPER(13), 3435 PMU_PMEVTYPER(14), 3436 PMU_PMEVTYPER(15), 3437 PMU_PMEVTYPER(16), 3438 PMU_PMEVTYPER(17), 3439 PMU_PMEVTYPER(18), 3440 PMU_PMEVTYPER(19), 3441 PMU_PMEVTYPER(20), 3442 PMU_PMEVTYPER(21), 3443 PMU_PMEVTYPER(22), 3444 PMU_PMEVTYPER(23), 3445 PMU_PMEVTYPER(24), 3446 PMU_PMEVTYPER(25), 3447 PMU_PMEVTYPER(26), 3448 PMU_PMEVTYPER(27), 3449 PMU_PMEVTYPER(28), 3450 PMU_PMEVTYPER(29), 3451 PMU_PMEVTYPER(30), 3452 /* PMCCFILTR */ 3453 { CP15_PMU_SYS_REG(DIRECT, 0, 14, 15, 7), .access = access_pmu_evtyper }, 3454 3455 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr }, 3456 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr }, 3457 3458 /* CCSIDR2 */ 3459 { Op1(1), CRn( 0), CRm( 0), Op2(2), undef_access }, 3460 3461 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 }, 3462 }; 3463 3464 static const struct sys_reg_desc cp15_64_regs[] = { 3465 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, 3466 { CP15_PMU_SYS_REG(DIRECT, 0, 0, 9, 0), .access = access_pmu_evcntr }, 3467 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */ 3468 { SYS_DESC(SYS_AARCH32_CNTPCT), access_arch_timer }, 3469 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 }, 3470 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */ 3471 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */ 3472 { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer }, 3473 { SYS_DESC(SYS_AARCH32_CNTPCTSS), access_arch_timer }, 3474 }; 3475 3476 static bool check_sysreg_table(const struct sys_reg_desc *table, unsigned int n, 3477 bool is_32) 3478 { 3479 unsigned int i; 3480 3481 for (i = 0; i < n; i++) { 3482 if (!is_32 && table[i].reg && !table[i].reset) { 3483 kvm_err("sys_reg table %pS entry %d (%s) lacks reset\n", 3484 &table[i], i, table[i].name); 3485 return false; 3486 } 3487 3488 if (i && cmp_sys_reg(&table[i-1], &table[i]) >= 0) { 3489 kvm_err("sys_reg table %pS entry %d (%s -> %s) out of order\n", 3490 &table[i], i, table[i - 1].name, table[i].name); 3491 return false; 3492 } 3493 } 3494 3495 return true; 3496 } 3497 3498 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu) 3499 { 3500 kvm_inject_undefined(vcpu); 3501 return 1; 3502 } 3503 3504 static void perform_access(struct kvm_vcpu *vcpu, 3505 struct sys_reg_params *params, 3506 const struct sys_reg_desc *r) 3507 { 3508 trace_kvm_sys_access(*vcpu_pc(vcpu), params, r); 3509 3510 /* Check for regs disabled by runtime config */ 3511 if (sysreg_hidden(vcpu, r)) { 3512 kvm_inject_undefined(vcpu); 3513 return; 3514 } 3515 3516 /* 3517 * Not having an accessor means that we have configured a trap 3518 * that we don't know how to handle. This certainly qualifies 3519 * as a gross bug that should be fixed right away. 3520 */ 3521 BUG_ON(!r->access); 3522 3523 /* Skip instruction if instructed so */ 3524 if (likely(r->access(vcpu, params, r))) 3525 kvm_incr_pc(vcpu); 3526 } 3527 3528 /* 3529 * emulate_cp -- tries to match a sys_reg access in a handling table, and 3530 * call the corresponding trap handler. 3531 * 3532 * @params: pointer to the descriptor of the access 3533 * @table: array of trap descriptors 3534 * @num: size of the trap descriptor array 3535 * 3536 * Return true if the access has been handled, false if not. 3537 */ 3538 static bool emulate_cp(struct kvm_vcpu *vcpu, 3539 struct sys_reg_params *params, 3540 const struct sys_reg_desc *table, 3541 size_t num) 3542 { 3543 const struct sys_reg_desc *r; 3544 3545 if (!table) 3546 return false; /* Not handled */ 3547 3548 r = find_reg(params, table, num); 3549 3550 if (r) { 3551 perform_access(vcpu, params, r); 3552 return true; 3553 } 3554 3555 /* Not handled */ 3556 return false; 3557 } 3558 3559 static void unhandled_cp_access(struct kvm_vcpu *vcpu, 3560 struct sys_reg_params *params) 3561 { 3562 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu); 3563 int cp = -1; 3564 3565 switch (esr_ec) { 3566 case ESR_ELx_EC_CP15_32: 3567 case ESR_ELx_EC_CP15_64: 3568 cp = 15; 3569 break; 3570 case ESR_ELx_EC_CP14_MR: 3571 case ESR_ELx_EC_CP14_64: 3572 cp = 14; 3573 break; 3574 default: 3575 WARN_ON(1); 3576 } 3577 3578 print_sys_reg_msg(params, 3579 "Unsupported guest CP%d access at: %08lx [%08lx]\n", 3580 cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 3581 kvm_inject_undefined(vcpu); 3582 } 3583 3584 /** 3585 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access 3586 * @vcpu: The VCPU pointer 3587 * @global: &struct sys_reg_desc 3588 * @nr_global: size of the @global array 3589 */ 3590 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu, 3591 const struct sys_reg_desc *global, 3592 size_t nr_global) 3593 { 3594 struct sys_reg_params params; 3595 u64 esr = kvm_vcpu_get_esr(vcpu); 3596 int Rt = kvm_vcpu_sys_get_rt(vcpu); 3597 int Rt2 = (esr >> 10) & 0x1f; 3598 3599 params.CRm = (esr >> 1) & 0xf; 3600 params.is_write = ((esr & 1) == 0); 3601 3602 params.Op0 = 0; 3603 params.Op1 = (esr >> 16) & 0xf; 3604 params.Op2 = 0; 3605 params.CRn = 0; 3606 3607 /* 3608 * Make a 64-bit value out of Rt and Rt2. As we use the same trap 3609 * backends between AArch32 and AArch64, we get away with it. 3610 */ 3611 if (params.is_write) { 3612 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff; 3613 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32; 3614 } 3615 3616 /* 3617 * If the table contains a handler, handle the 3618 * potential register operation in the case of a read and return 3619 * with success. 3620 */ 3621 if (emulate_cp(vcpu, ¶ms, global, nr_global)) { 3622 /* Split up the value between registers for the read side */ 3623 if (!params.is_write) { 3624 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval)); 3625 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval)); 3626 } 3627 3628 return 1; 3629 } 3630 3631 unhandled_cp_access(vcpu, ¶ms); 3632 return 1; 3633 } 3634 3635 static bool emulate_sys_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *params); 3636 3637 /* 3638 * The CP10 ID registers are architecturally mapped to AArch64 feature 3639 * registers. Abuse that fact so we can rely on the AArch64 handler for accesses 3640 * from AArch32. 3641 */ 3642 static bool kvm_esr_cp10_id_to_sys64(u64 esr, struct sys_reg_params *params) 3643 { 3644 u8 reg_id = (esr >> 10) & 0xf; 3645 bool valid; 3646 3647 params->is_write = ((esr & 1) == 0); 3648 params->Op0 = 3; 3649 params->Op1 = 0; 3650 params->CRn = 0; 3651 params->CRm = 3; 3652 3653 /* CP10 ID registers are read-only */ 3654 valid = !params->is_write; 3655 3656 switch (reg_id) { 3657 /* MVFR0 */ 3658 case 0b0111: 3659 params->Op2 = 0; 3660 break; 3661 /* MVFR1 */ 3662 case 0b0110: 3663 params->Op2 = 1; 3664 break; 3665 /* MVFR2 */ 3666 case 0b0101: 3667 params->Op2 = 2; 3668 break; 3669 default: 3670 valid = false; 3671 } 3672 3673 if (valid) 3674 return true; 3675 3676 kvm_pr_unimpl("Unhandled cp10 register %s: %u\n", 3677 params->is_write ? "write" : "read", reg_id); 3678 return false; 3679 } 3680 3681 /** 3682 * kvm_handle_cp10_id() - Handles a VMRS trap on guest access to a 'Media and 3683 * VFP Register' from AArch32. 3684 * @vcpu: The vCPU pointer 3685 * 3686 * MVFR{0-2} are architecturally mapped to the AArch64 MVFR{0-2}_EL1 registers. 3687 * Work out the correct AArch64 system register encoding and reroute to the 3688 * AArch64 system register emulation. 3689 */ 3690 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu) 3691 { 3692 int Rt = kvm_vcpu_sys_get_rt(vcpu); 3693 u64 esr = kvm_vcpu_get_esr(vcpu); 3694 struct sys_reg_params params; 3695 3696 /* UNDEF on any unhandled register access */ 3697 if (!kvm_esr_cp10_id_to_sys64(esr, ¶ms)) { 3698 kvm_inject_undefined(vcpu); 3699 return 1; 3700 } 3701 3702 if (emulate_sys_reg(vcpu, ¶ms)) 3703 vcpu_set_reg(vcpu, Rt, params.regval); 3704 3705 return 1; 3706 } 3707 3708 /** 3709 * kvm_emulate_cp15_id_reg() - Handles an MRC trap on a guest CP15 access where 3710 * CRn=0, which corresponds to the AArch32 feature 3711 * registers. 3712 * @vcpu: the vCPU pointer 3713 * @params: the system register access parameters. 3714 * 3715 * Our cp15 system register tables do not enumerate the AArch32 feature 3716 * registers. Conveniently, our AArch64 table does, and the AArch32 system 3717 * register encoding can be trivially remapped into the AArch64 for the feature 3718 * registers: Append op0=3, leaving op1, CRn, CRm, and op2 the same. 3719 * 3720 * According to DDI0487G.b G7.3.1, paragraph "Behavior of VMSAv8-32 32-bit 3721 * System registers with (coproc=0b1111, CRn==c0)", read accesses from this 3722 * range are either UNKNOWN or RES0. Rerouting remains architectural as we 3723 * treat undefined registers in this range as RAZ. 3724 */ 3725 static int kvm_emulate_cp15_id_reg(struct kvm_vcpu *vcpu, 3726 struct sys_reg_params *params) 3727 { 3728 int Rt = kvm_vcpu_sys_get_rt(vcpu); 3729 3730 /* Treat impossible writes to RO registers as UNDEFINED */ 3731 if (params->is_write) { 3732 unhandled_cp_access(vcpu, params); 3733 return 1; 3734 } 3735 3736 params->Op0 = 3; 3737 3738 /* 3739 * All registers where CRm > 3 are known to be UNKNOWN/RAZ from AArch32. 3740 * Avoid conflicting with future expansion of AArch64 feature registers 3741 * and simply treat them as RAZ here. 3742 */ 3743 if (params->CRm > 3) 3744 params->regval = 0; 3745 else if (!emulate_sys_reg(vcpu, params)) 3746 return 1; 3747 3748 vcpu_set_reg(vcpu, Rt, params->regval); 3749 return 1; 3750 } 3751 3752 /** 3753 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access 3754 * @vcpu: The VCPU pointer 3755 * @params: &struct sys_reg_params 3756 * @global: &struct sys_reg_desc 3757 * @nr_global: size of the @global array 3758 */ 3759 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu, 3760 struct sys_reg_params *params, 3761 const struct sys_reg_desc *global, 3762 size_t nr_global) 3763 { 3764 int Rt = kvm_vcpu_sys_get_rt(vcpu); 3765 3766 params->regval = vcpu_get_reg(vcpu, Rt); 3767 3768 if (emulate_cp(vcpu, params, global, nr_global)) { 3769 if (!params->is_write) 3770 vcpu_set_reg(vcpu, Rt, params->regval); 3771 return 1; 3772 } 3773 3774 unhandled_cp_access(vcpu, params); 3775 return 1; 3776 } 3777 3778 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu) 3779 { 3780 return kvm_handle_cp_64(vcpu, cp15_64_regs, ARRAY_SIZE(cp15_64_regs)); 3781 } 3782 3783 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu) 3784 { 3785 struct sys_reg_params params; 3786 3787 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu)); 3788 3789 /* 3790 * Certain AArch32 ID registers are handled by rerouting to the AArch64 3791 * system register table. Registers in the ID range where CRm=0 are 3792 * excluded from this scheme as they do not trivially map into AArch64 3793 * system register encodings. 3794 */ 3795 if (params.Op1 == 0 && params.CRn == 0 && params.CRm) 3796 return kvm_emulate_cp15_id_reg(vcpu, ¶ms); 3797 3798 return kvm_handle_cp_32(vcpu, ¶ms, cp15_regs, ARRAY_SIZE(cp15_regs)); 3799 } 3800 3801 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu) 3802 { 3803 return kvm_handle_cp_64(vcpu, cp14_64_regs, ARRAY_SIZE(cp14_64_regs)); 3804 } 3805 3806 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu) 3807 { 3808 struct sys_reg_params params; 3809 3810 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu)); 3811 3812 return kvm_handle_cp_32(vcpu, ¶ms, cp14_regs, ARRAY_SIZE(cp14_regs)); 3813 } 3814 3815 /** 3816 * emulate_sys_reg - Emulate a guest access to an AArch64 system register 3817 * @vcpu: The VCPU pointer 3818 * @params: Decoded system register parameters 3819 * 3820 * Return: true if the system register access was successful, false otherwise. 3821 */ 3822 static bool emulate_sys_reg(struct kvm_vcpu *vcpu, 3823 struct sys_reg_params *params) 3824 { 3825 const struct sys_reg_desc *r; 3826 3827 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 3828 if (likely(r)) { 3829 perform_access(vcpu, params, r); 3830 return true; 3831 } 3832 3833 print_sys_reg_msg(params, 3834 "Unsupported guest sys_reg access at: %lx [%08lx]\n", 3835 *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 3836 kvm_inject_undefined(vcpu); 3837 3838 return false; 3839 } 3840 3841 static void *idregs_debug_start(struct seq_file *s, loff_t *pos) 3842 { 3843 struct kvm *kvm = s->private; 3844 u8 *iter; 3845 3846 mutex_lock(&kvm->arch.config_lock); 3847 3848 iter = &kvm->arch.idreg_debugfs_iter; 3849 if (test_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags) && 3850 *iter == (u8)~0) { 3851 *iter = *pos; 3852 if (*iter >= KVM_ARM_ID_REG_NUM) 3853 iter = NULL; 3854 } else { 3855 iter = ERR_PTR(-EBUSY); 3856 } 3857 3858 mutex_unlock(&kvm->arch.config_lock); 3859 3860 return iter; 3861 } 3862 3863 static void *idregs_debug_next(struct seq_file *s, void *v, loff_t *pos) 3864 { 3865 struct kvm *kvm = s->private; 3866 3867 (*pos)++; 3868 3869 if ((kvm->arch.idreg_debugfs_iter + 1) < KVM_ARM_ID_REG_NUM) { 3870 kvm->arch.idreg_debugfs_iter++; 3871 3872 return &kvm->arch.idreg_debugfs_iter; 3873 } 3874 3875 return NULL; 3876 } 3877 3878 static void idregs_debug_stop(struct seq_file *s, void *v) 3879 { 3880 struct kvm *kvm = s->private; 3881 3882 if (IS_ERR(v)) 3883 return; 3884 3885 mutex_lock(&kvm->arch.config_lock); 3886 3887 kvm->arch.idreg_debugfs_iter = ~0; 3888 3889 mutex_unlock(&kvm->arch.config_lock); 3890 } 3891 3892 static int idregs_debug_show(struct seq_file *s, void *v) 3893 { 3894 struct kvm *kvm = s->private; 3895 const struct sys_reg_desc *desc; 3896 3897 desc = first_idreg + kvm->arch.idreg_debugfs_iter; 3898 3899 if (!desc->name) 3900 return 0; 3901 3902 seq_printf(s, "%20s:\t%016llx\n", 3903 desc->name, IDREG(kvm, IDX_IDREG(kvm->arch.idreg_debugfs_iter))); 3904 3905 return 0; 3906 } 3907 3908 static const struct seq_operations idregs_debug_sops = { 3909 .start = idregs_debug_start, 3910 .next = idregs_debug_next, 3911 .stop = idregs_debug_stop, 3912 .show = idregs_debug_show, 3913 }; 3914 3915 DEFINE_SEQ_ATTRIBUTE(idregs_debug); 3916 3917 void kvm_sys_regs_create_debugfs(struct kvm *kvm) 3918 { 3919 kvm->arch.idreg_debugfs_iter = ~0; 3920 3921 debugfs_create_file("idregs", 0444, kvm->debugfs_dentry, kvm, 3922 &idregs_debug_fops); 3923 } 3924 3925 static void reset_vm_ftr_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *reg) 3926 { 3927 u32 id = reg_to_encoding(reg); 3928 struct kvm *kvm = vcpu->kvm; 3929 3930 if (test_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags)) 3931 return; 3932 3933 lockdep_assert_held(&kvm->arch.config_lock); 3934 IDREG(kvm, id) = reg->reset(vcpu, reg); 3935 } 3936 3937 static void reset_vcpu_ftr_id_reg(struct kvm_vcpu *vcpu, 3938 const struct sys_reg_desc *reg) 3939 { 3940 if (kvm_vcpu_initialized(vcpu)) 3941 return; 3942 3943 reg->reset(vcpu, reg); 3944 } 3945 3946 /** 3947 * kvm_reset_sys_regs - sets system registers to reset value 3948 * @vcpu: The VCPU pointer 3949 * 3950 * This function finds the right table above and sets the registers on the 3951 * virtual CPU struct to their architecturally defined reset values. 3952 */ 3953 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu) 3954 { 3955 struct kvm *kvm = vcpu->kvm; 3956 unsigned long i; 3957 3958 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { 3959 const struct sys_reg_desc *r = &sys_reg_descs[i]; 3960 3961 if (!r->reset) 3962 continue; 3963 3964 if (is_vm_ftr_id_reg(reg_to_encoding(r))) 3965 reset_vm_ftr_id_reg(vcpu, r); 3966 else if (is_vcpu_ftr_id_reg(reg_to_encoding(r))) 3967 reset_vcpu_ftr_id_reg(vcpu, r); 3968 else 3969 r->reset(vcpu, r); 3970 } 3971 3972 set_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags); 3973 } 3974 3975 /** 3976 * kvm_handle_sys_reg -- handles a system instruction or mrs/msr instruction 3977 * trap on a guest execution 3978 * @vcpu: The VCPU pointer 3979 */ 3980 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu) 3981 { 3982 const struct sys_reg_desc *desc = NULL; 3983 struct sys_reg_params params; 3984 unsigned long esr = kvm_vcpu_get_esr(vcpu); 3985 int Rt = kvm_vcpu_sys_get_rt(vcpu); 3986 int sr_idx; 3987 3988 trace_kvm_handle_sys_reg(esr); 3989 3990 if (triage_sysreg_trap(vcpu, &sr_idx)) 3991 return 1; 3992 3993 params = esr_sys64_to_params(esr); 3994 params.regval = vcpu_get_reg(vcpu, Rt); 3995 3996 /* System registers have Op0=={2,3}, as per DDI487 J.a C5.1.2 */ 3997 if (params.Op0 == 2 || params.Op0 == 3) 3998 desc = &sys_reg_descs[sr_idx]; 3999 else 4000 desc = &sys_insn_descs[sr_idx]; 4001 4002 perform_access(vcpu, ¶ms, desc); 4003 4004 /* Read from system register? */ 4005 if (!params.is_write && 4006 (params.Op0 == 2 || params.Op0 == 3)) 4007 vcpu_set_reg(vcpu, Rt, params.regval); 4008 4009 return 1; 4010 } 4011 4012 /****************************************************************************** 4013 * Userspace API 4014 *****************************************************************************/ 4015 4016 static bool index_to_params(u64 id, struct sys_reg_params *params) 4017 { 4018 switch (id & KVM_REG_SIZE_MASK) { 4019 case KVM_REG_SIZE_U64: 4020 /* Any unused index bits means it's not valid. */ 4021 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK 4022 | KVM_REG_ARM_COPROC_MASK 4023 | KVM_REG_ARM64_SYSREG_OP0_MASK 4024 | KVM_REG_ARM64_SYSREG_OP1_MASK 4025 | KVM_REG_ARM64_SYSREG_CRN_MASK 4026 | KVM_REG_ARM64_SYSREG_CRM_MASK 4027 | KVM_REG_ARM64_SYSREG_OP2_MASK)) 4028 return false; 4029 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK) 4030 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT); 4031 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK) 4032 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT); 4033 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK) 4034 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT); 4035 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK) 4036 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT); 4037 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK) 4038 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT); 4039 return true; 4040 default: 4041 return false; 4042 } 4043 } 4044 4045 const struct sys_reg_desc *get_reg_by_id(u64 id, 4046 const struct sys_reg_desc table[], 4047 unsigned int num) 4048 { 4049 struct sys_reg_params params; 4050 4051 if (!index_to_params(id, ¶ms)) 4052 return NULL; 4053 4054 return find_reg(¶ms, table, num); 4055 } 4056 4057 /* Decode an index value, and find the sys_reg_desc entry. */ 4058 static const struct sys_reg_desc * 4059 id_to_sys_reg_desc(struct kvm_vcpu *vcpu, u64 id, 4060 const struct sys_reg_desc table[], unsigned int num) 4061 4062 { 4063 const struct sys_reg_desc *r; 4064 4065 /* We only do sys_reg for now. */ 4066 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG) 4067 return NULL; 4068 4069 r = get_reg_by_id(id, table, num); 4070 4071 /* Not saved in the sys_reg array and not otherwise accessible? */ 4072 if (r && (!(r->reg || r->get_user) || sysreg_hidden(vcpu, r))) 4073 r = NULL; 4074 4075 return r; 4076 } 4077 4078 /* 4079 * These are the invariant sys_reg registers: we let the guest see the 4080 * host versions of these, so they're part of the guest state. 4081 * 4082 * A future CPU may provide a mechanism to present different values to 4083 * the guest, or a future kvm may trap them. 4084 */ 4085 4086 #define FUNCTION_INVARIANT(reg) \ 4087 static u64 get_##reg(struct kvm_vcpu *v, \ 4088 const struct sys_reg_desc *r) \ 4089 { \ 4090 ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \ 4091 return ((struct sys_reg_desc *)r)->val; \ 4092 } 4093 4094 FUNCTION_INVARIANT(midr_el1) 4095 FUNCTION_INVARIANT(revidr_el1) 4096 FUNCTION_INVARIANT(aidr_el1) 4097 4098 static u64 get_ctr_el0(struct kvm_vcpu *v, const struct sys_reg_desc *r) 4099 { 4100 ((struct sys_reg_desc *)r)->val = read_sanitised_ftr_reg(SYS_CTR_EL0); 4101 return ((struct sys_reg_desc *)r)->val; 4102 } 4103 4104 /* ->val is filled in by kvm_sys_reg_table_init() */ 4105 static struct sys_reg_desc invariant_sys_regs[] __ro_after_init = { 4106 { SYS_DESC(SYS_MIDR_EL1), NULL, get_midr_el1 }, 4107 { SYS_DESC(SYS_REVIDR_EL1), NULL, get_revidr_el1 }, 4108 { SYS_DESC(SYS_AIDR_EL1), NULL, get_aidr_el1 }, 4109 { SYS_DESC(SYS_CTR_EL0), NULL, get_ctr_el0 }, 4110 }; 4111 4112 static int get_invariant_sys_reg(u64 id, u64 __user *uaddr) 4113 { 4114 const struct sys_reg_desc *r; 4115 4116 r = get_reg_by_id(id, invariant_sys_regs, 4117 ARRAY_SIZE(invariant_sys_regs)); 4118 if (!r) 4119 return -ENOENT; 4120 4121 return put_user(r->val, uaddr); 4122 } 4123 4124 static int set_invariant_sys_reg(u64 id, u64 __user *uaddr) 4125 { 4126 const struct sys_reg_desc *r; 4127 u64 val; 4128 4129 r = get_reg_by_id(id, invariant_sys_regs, 4130 ARRAY_SIZE(invariant_sys_regs)); 4131 if (!r) 4132 return -ENOENT; 4133 4134 if (get_user(val, uaddr)) 4135 return -EFAULT; 4136 4137 /* This is what we mean by invariant: you can't change it. */ 4138 if (r->val != val) 4139 return -EINVAL; 4140 4141 return 0; 4142 } 4143 4144 static int demux_c15_get(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) 4145 { 4146 u32 val; 4147 u32 __user *uval = uaddr; 4148 4149 /* Fail if we have unknown bits set. */ 4150 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 4151 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 4152 return -ENOENT; 4153 4154 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 4155 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 4156 if (KVM_REG_SIZE(id) != 4) 4157 return -ENOENT; 4158 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 4159 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 4160 if (val >= CSSELR_MAX) 4161 return -ENOENT; 4162 4163 return put_user(get_ccsidr(vcpu, val), uval); 4164 default: 4165 return -ENOENT; 4166 } 4167 } 4168 4169 static int demux_c15_set(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) 4170 { 4171 u32 val, newval; 4172 u32 __user *uval = uaddr; 4173 4174 /* Fail if we have unknown bits set. */ 4175 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 4176 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 4177 return -ENOENT; 4178 4179 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 4180 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 4181 if (KVM_REG_SIZE(id) != 4) 4182 return -ENOENT; 4183 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 4184 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 4185 if (val >= CSSELR_MAX) 4186 return -ENOENT; 4187 4188 if (get_user(newval, uval)) 4189 return -EFAULT; 4190 4191 return set_ccsidr(vcpu, val, newval); 4192 default: 4193 return -ENOENT; 4194 } 4195 } 4196 4197 int kvm_sys_reg_get_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg, 4198 const struct sys_reg_desc table[], unsigned int num) 4199 { 4200 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr; 4201 const struct sys_reg_desc *r; 4202 u64 val; 4203 int ret; 4204 4205 r = id_to_sys_reg_desc(vcpu, reg->id, table, num); 4206 if (!r || sysreg_hidden_user(vcpu, r)) 4207 return -ENOENT; 4208 4209 if (r->get_user) { 4210 ret = (r->get_user)(vcpu, r, &val); 4211 } else { 4212 val = __vcpu_sys_reg(vcpu, r->reg); 4213 ret = 0; 4214 } 4215 4216 if (!ret) 4217 ret = put_user(val, uaddr); 4218 4219 return ret; 4220 } 4221 4222 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 4223 { 4224 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 4225 int err; 4226 4227 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 4228 return demux_c15_get(vcpu, reg->id, uaddr); 4229 4230 err = get_invariant_sys_reg(reg->id, uaddr); 4231 if (err != -ENOENT) 4232 return err; 4233 4234 return kvm_sys_reg_get_user(vcpu, reg, 4235 sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 4236 } 4237 4238 int kvm_sys_reg_set_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg, 4239 const struct sys_reg_desc table[], unsigned int num) 4240 { 4241 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr; 4242 const struct sys_reg_desc *r; 4243 u64 val; 4244 int ret; 4245 4246 if (get_user(val, uaddr)) 4247 return -EFAULT; 4248 4249 r = id_to_sys_reg_desc(vcpu, reg->id, table, num); 4250 if (!r || sysreg_hidden_user(vcpu, r)) 4251 return -ENOENT; 4252 4253 if (sysreg_user_write_ignore(vcpu, r)) 4254 return 0; 4255 4256 if (r->set_user) { 4257 ret = (r->set_user)(vcpu, r, val); 4258 } else { 4259 __vcpu_sys_reg(vcpu, r->reg) = val; 4260 ret = 0; 4261 } 4262 4263 return ret; 4264 } 4265 4266 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 4267 { 4268 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 4269 int err; 4270 4271 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 4272 return demux_c15_set(vcpu, reg->id, uaddr); 4273 4274 err = set_invariant_sys_reg(reg->id, uaddr); 4275 if (err != -ENOENT) 4276 return err; 4277 4278 return kvm_sys_reg_set_user(vcpu, reg, 4279 sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 4280 } 4281 4282 static unsigned int num_demux_regs(void) 4283 { 4284 return CSSELR_MAX; 4285 } 4286 4287 static int write_demux_regids(u64 __user *uindices) 4288 { 4289 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX; 4290 unsigned int i; 4291 4292 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR; 4293 for (i = 0; i < CSSELR_MAX; i++) { 4294 if (put_user(val | i, uindices)) 4295 return -EFAULT; 4296 uindices++; 4297 } 4298 return 0; 4299 } 4300 4301 static u64 sys_reg_to_index(const struct sys_reg_desc *reg) 4302 { 4303 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | 4304 KVM_REG_ARM64_SYSREG | 4305 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) | 4306 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) | 4307 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) | 4308 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) | 4309 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT)); 4310 } 4311 4312 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind) 4313 { 4314 if (!*uind) 4315 return true; 4316 4317 if (put_user(sys_reg_to_index(reg), *uind)) 4318 return false; 4319 4320 (*uind)++; 4321 return true; 4322 } 4323 4324 static int walk_one_sys_reg(const struct kvm_vcpu *vcpu, 4325 const struct sys_reg_desc *rd, 4326 u64 __user **uind, 4327 unsigned int *total) 4328 { 4329 /* 4330 * Ignore registers we trap but don't save, 4331 * and for which no custom user accessor is provided. 4332 */ 4333 if (!(rd->reg || rd->get_user)) 4334 return 0; 4335 4336 if (sysreg_hidden_user(vcpu, rd)) 4337 return 0; 4338 4339 if (!copy_reg_to_user(rd, uind)) 4340 return -EFAULT; 4341 4342 (*total)++; 4343 return 0; 4344 } 4345 4346 /* Assumed ordered tables, see kvm_sys_reg_table_init. */ 4347 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind) 4348 { 4349 const struct sys_reg_desc *i2, *end2; 4350 unsigned int total = 0; 4351 int err; 4352 4353 i2 = sys_reg_descs; 4354 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs); 4355 4356 while (i2 != end2) { 4357 err = walk_one_sys_reg(vcpu, i2++, &uind, &total); 4358 if (err) 4359 return err; 4360 } 4361 return total; 4362 } 4363 4364 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu) 4365 { 4366 return ARRAY_SIZE(invariant_sys_regs) 4367 + num_demux_regs() 4368 + walk_sys_regs(vcpu, (u64 __user *)NULL); 4369 } 4370 4371 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) 4372 { 4373 unsigned int i; 4374 int err; 4375 4376 /* Then give them all the invariant registers' indices. */ 4377 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) { 4378 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices)) 4379 return -EFAULT; 4380 uindices++; 4381 } 4382 4383 err = walk_sys_regs(vcpu, uindices); 4384 if (err < 0) 4385 return err; 4386 uindices += err; 4387 4388 return write_demux_regids(uindices); 4389 } 4390 4391 #define KVM_ARM_FEATURE_ID_RANGE_INDEX(r) \ 4392 KVM_ARM_FEATURE_ID_RANGE_IDX(sys_reg_Op0(r), \ 4393 sys_reg_Op1(r), \ 4394 sys_reg_CRn(r), \ 4395 sys_reg_CRm(r), \ 4396 sys_reg_Op2(r)) 4397 4398 int kvm_vm_ioctl_get_reg_writable_masks(struct kvm *kvm, struct reg_mask_range *range) 4399 { 4400 const void *zero_page = page_to_virt(ZERO_PAGE(0)); 4401 u64 __user *masks = (u64 __user *)range->addr; 4402 4403 /* Only feature id range is supported, reserved[13] must be zero. */ 4404 if (range->range || 4405 memcmp(range->reserved, zero_page, sizeof(range->reserved))) 4406 return -EINVAL; 4407 4408 /* Wipe the whole thing first */ 4409 if (clear_user(masks, KVM_ARM_FEATURE_ID_RANGE_SIZE * sizeof(__u64))) 4410 return -EFAULT; 4411 4412 for (int i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { 4413 const struct sys_reg_desc *reg = &sys_reg_descs[i]; 4414 u32 encoding = reg_to_encoding(reg); 4415 u64 val; 4416 4417 if (!is_feature_id_reg(encoding) || !reg->set_user) 4418 continue; 4419 4420 /* 4421 * For ID registers, we return the writable mask. Other feature 4422 * registers return a full 64bit mask. That's not necessary 4423 * compliant with a given revision of the architecture, but the 4424 * RES0/RES1 definitions allow us to do that. 4425 */ 4426 if (is_vm_ftr_id_reg(encoding)) { 4427 if (!reg->val || 4428 (is_aa32_id_reg(encoding) && !kvm_supports_32bit_el0())) 4429 continue; 4430 val = reg->val; 4431 } else { 4432 val = ~0UL; 4433 } 4434 4435 if (put_user(val, (masks + KVM_ARM_FEATURE_ID_RANGE_INDEX(encoding)))) 4436 return -EFAULT; 4437 } 4438 4439 return 0; 4440 } 4441 4442 void kvm_init_sysreg(struct kvm_vcpu *vcpu) 4443 { 4444 struct kvm *kvm = vcpu->kvm; 4445 4446 mutex_lock(&kvm->arch.config_lock); 4447 4448 /* 4449 * In the absence of FGT, we cannot independently trap TLBI 4450 * Range instructions. This isn't great, but trapping all 4451 * TLBIs would be far worse. Live with it... 4452 */ 4453 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 4454 vcpu->arch.hcr_el2 |= HCR_TTLBOS; 4455 4456 if (cpus_have_final_cap(ARM64_HAS_HCX)) { 4457 vcpu->arch.hcrx_el2 = HCRX_GUEST_FLAGS; 4458 4459 if (kvm_has_feat(kvm, ID_AA64ISAR2_EL1, MOPS, IMP)) 4460 vcpu->arch.hcrx_el2 |= (HCRX_EL2_MSCEn | HCRX_EL2_MCE2); 4461 } 4462 4463 if (test_bit(KVM_ARCH_FLAG_FGU_INITIALIZED, &kvm->arch.flags)) 4464 goto out; 4465 4466 kvm->arch.fgu[HFGxTR_GROUP] = (HFGxTR_EL2_nAMAIR2_EL1 | 4467 HFGxTR_EL2_nMAIR2_EL1 | 4468 HFGxTR_EL2_nS2POR_EL1 | 4469 HFGxTR_EL2_nPOR_EL1 | 4470 HFGxTR_EL2_nPOR_EL0 | 4471 HFGxTR_EL2_nACCDATA_EL1 | 4472 HFGxTR_EL2_nSMPRI_EL1_MASK | 4473 HFGxTR_EL2_nTPIDR2_EL0_MASK); 4474 4475 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 4476 kvm->arch.fgu[HFGITR_GROUP] |= (HFGITR_EL2_TLBIRVAALE1OS| 4477 HFGITR_EL2_TLBIRVALE1OS | 4478 HFGITR_EL2_TLBIRVAAE1OS | 4479 HFGITR_EL2_TLBIRVAE1OS | 4480 HFGITR_EL2_TLBIVAALE1OS | 4481 HFGITR_EL2_TLBIVALE1OS | 4482 HFGITR_EL2_TLBIVAAE1OS | 4483 HFGITR_EL2_TLBIASIDE1OS | 4484 HFGITR_EL2_TLBIVAE1OS | 4485 HFGITR_EL2_TLBIVMALLE1OS); 4486 4487 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE)) 4488 kvm->arch.fgu[HFGITR_GROUP] |= (HFGITR_EL2_TLBIRVAALE1 | 4489 HFGITR_EL2_TLBIRVALE1 | 4490 HFGITR_EL2_TLBIRVAAE1 | 4491 HFGITR_EL2_TLBIRVAE1 | 4492 HFGITR_EL2_TLBIRVAALE1IS| 4493 HFGITR_EL2_TLBIRVALE1IS | 4494 HFGITR_EL2_TLBIRVAAE1IS | 4495 HFGITR_EL2_TLBIRVAE1IS | 4496 HFGITR_EL2_TLBIRVAALE1OS| 4497 HFGITR_EL2_TLBIRVALE1OS | 4498 HFGITR_EL2_TLBIRVAAE1OS | 4499 HFGITR_EL2_TLBIRVAE1OS); 4500 4501 if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, S1PIE, IMP)) 4502 kvm->arch.fgu[HFGxTR_GROUP] |= (HFGxTR_EL2_nPIRE0_EL1 | 4503 HFGxTR_EL2_nPIR_EL1); 4504 4505 if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, AMU, IMP)) 4506 kvm->arch.fgu[HAFGRTR_GROUP] |= ~(HAFGRTR_EL2_RES0 | 4507 HAFGRTR_EL2_RES1); 4508 4509 set_bit(KVM_ARCH_FLAG_FGU_INITIALIZED, &kvm->arch.flags); 4510 out: 4511 mutex_unlock(&kvm->arch.config_lock); 4512 } 4513 4514 int __init kvm_sys_reg_table_init(void) 4515 { 4516 struct sys_reg_params params; 4517 bool valid = true; 4518 unsigned int i; 4519 int ret = 0; 4520 4521 /* Make sure tables are unique and in order. */ 4522 valid &= check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), false); 4523 valid &= check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), true); 4524 valid &= check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), true); 4525 valid &= check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), true); 4526 valid &= check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), true); 4527 valid &= check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs), false); 4528 valid &= check_sysreg_table(sys_insn_descs, ARRAY_SIZE(sys_insn_descs), false); 4529 4530 if (!valid) 4531 return -EINVAL; 4532 4533 /* We abuse the reset function to overwrite the table itself. */ 4534 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) 4535 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]); 4536 4537 /* Find the first idreg (SYS_ID_PFR0_EL1) in sys_reg_descs. */ 4538 params = encoding_to_params(SYS_ID_PFR0_EL1); 4539 first_idreg = find_reg(¶ms, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 4540 if (!first_idreg) 4541 return -EINVAL; 4542 4543 ret = populate_nv_trap_config(); 4544 4545 for (i = 0; !ret && i < ARRAY_SIZE(sys_reg_descs); i++) 4546 ret = populate_sysreg_config(sys_reg_descs + i, i); 4547 4548 for (i = 0; !ret && i < ARRAY_SIZE(sys_insn_descs); i++) 4549 ret = populate_sysreg_config(sys_insn_descs + i, i); 4550 4551 return ret; 4552 } 4553