1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/kvm/coproc.c: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Authors: Rusty Russell <rusty@rustcorp.com.au> 9 * Christoffer Dall <c.dall@virtualopensystems.com> 10 */ 11 12 #include <linux/bitfield.h> 13 #include <linux/bsearch.h> 14 #include <linux/cacheinfo.h> 15 #include <linux/debugfs.h> 16 #include <linux/kvm_host.h> 17 #include <linux/mm.h> 18 #include <linux/printk.h> 19 #include <linux/uaccess.h> 20 #include <linux/irqchip/arm-gic-v3.h> 21 22 #include <asm/arm_pmuv3.h> 23 #include <asm/cacheflush.h> 24 #include <asm/cputype.h> 25 #include <asm/debug-monitors.h> 26 #include <asm/esr.h> 27 #include <asm/kvm_arm.h> 28 #include <asm/kvm_emulate.h> 29 #include <asm/kvm_hyp.h> 30 #include <asm/kvm_mmu.h> 31 #include <asm/kvm_nested.h> 32 #include <asm/perf_event.h> 33 #include <asm/sysreg.h> 34 35 #include <trace/events/kvm.h> 36 37 #include "sys_regs.h" 38 #include "vgic/vgic.h" 39 40 #include "trace.h" 41 42 /* 43 * For AArch32, we only take care of what is being trapped. Anything 44 * that has to do with init and userspace access has to go via the 45 * 64bit interface. 46 */ 47 48 static u64 sys_reg_to_index(const struct sys_reg_desc *reg); 49 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 50 u64 val); 51 52 static bool undef_access(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 53 const struct sys_reg_desc *r) 54 { 55 kvm_inject_undefined(vcpu); 56 return false; 57 } 58 59 static bool bad_trap(struct kvm_vcpu *vcpu, 60 struct sys_reg_params *params, 61 const struct sys_reg_desc *r, 62 const char *msg) 63 { 64 WARN_ONCE(1, "Unexpected %s\n", msg); 65 print_sys_reg_instr(params); 66 return undef_access(vcpu, params, r); 67 } 68 69 static bool read_from_write_only(struct kvm_vcpu *vcpu, 70 struct sys_reg_params *params, 71 const struct sys_reg_desc *r) 72 { 73 return bad_trap(vcpu, params, r, 74 "sys_reg read to write-only register"); 75 } 76 77 static bool write_to_read_only(struct kvm_vcpu *vcpu, 78 struct sys_reg_params *params, 79 const struct sys_reg_desc *r) 80 { 81 return bad_trap(vcpu, params, r, 82 "sys_reg write to read-only register"); 83 } 84 85 enum sr_loc_attr { 86 SR_LOC_MEMORY = 0, /* Register definitely in memory */ 87 SR_LOC_LOADED = BIT(0), /* Register on CPU, unless it cannot */ 88 SR_LOC_MAPPED = BIT(1), /* Register in a different CPU register */ 89 SR_LOC_XLATED = BIT(2), /* Register translated to fit another reg */ 90 SR_LOC_SPECIAL = BIT(3), /* Demanding register, implies loaded */ 91 }; 92 93 struct sr_loc { 94 enum sr_loc_attr loc; 95 enum vcpu_sysreg map_reg; 96 u64 (*xlate)(u64); 97 }; 98 99 static enum sr_loc_attr locate_direct_register(const struct kvm_vcpu *vcpu, 100 enum vcpu_sysreg reg) 101 { 102 switch (reg) { 103 case SCTLR_EL1: 104 case CPACR_EL1: 105 case TTBR0_EL1: 106 case TTBR1_EL1: 107 case TCR_EL1: 108 case TCR2_EL1: 109 case PIR_EL1: 110 case PIRE0_EL1: 111 case POR_EL1: 112 case ESR_EL1: 113 case AFSR0_EL1: 114 case AFSR1_EL1: 115 case FAR_EL1: 116 case MAIR_EL1: 117 case VBAR_EL1: 118 case CONTEXTIDR_EL1: 119 case AMAIR_EL1: 120 case CNTKCTL_EL1: 121 case ELR_EL1: 122 case SPSR_EL1: 123 case ZCR_EL1: 124 case SCTLR2_EL1: 125 /* 126 * EL1 registers which have an ELx2 mapping are loaded if 127 * we're not in hypervisor context. 128 */ 129 return is_hyp_ctxt(vcpu) ? SR_LOC_MEMORY : SR_LOC_LOADED; 130 131 case TPIDR_EL0: 132 case TPIDRRO_EL0: 133 case TPIDR_EL1: 134 case PAR_EL1: 135 case DACR32_EL2: 136 case IFSR32_EL2: 137 case DBGVCR32_EL2: 138 /* These registers are always loaded, no matter what */ 139 return SR_LOC_LOADED; 140 141 default: 142 /* Non-mapped EL2 registers are by definition in memory. */ 143 return SR_LOC_MEMORY; 144 } 145 } 146 147 static void locate_mapped_el2_register(const struct kvm_vcpu *vcpu, 148 enum vcpu_sysreg reg, 149 enum vcpu_sysreg map_reg, 150 u64 (*xlate)(u64), 151 struct sr_loc *loc) 152 { 153 if (!is_hyp_ctxt(vcpu)) { 154 loc->loc = SR_LOC_MEMORY; 155 return; 156 } 157 158 loc->loc = SR_LOC_LOADED | SR_LOC_MAPPED; 159 loc->map_reg = map_reg; 160 161 WARN_ON(locate_direct_register(vcpu, map_reg) != SR_LOC_MEMORY); 162 163 if (xlate != NULL && !vcpu_el2_e2h_is_set(vcpu)) { 164 loc->loc |= SR_LOC_XLATED; 165 loc->xlate = xlate; 166 } 167 } 168 169 #define MAPPED_EL2_SYSREG(r, m, t) \ 170 case r: { \ 171 locate_mapped_el2_register(vcpu, r, m, t, loc); \ 172 break; \ 173 } 174 175 static void locate_register(const struct kvm_vcpu *vcpu, enum vcpu_sysreg reg, 176 struct sr_loc *loc) 177 { 178 if (!vcpu_get_flag(vcpu, SYSREGS_ON_CPU)) { 179 loc->loc = SR_LOC_MEMORY; 180 return; 181 } 182 183 switch (reg) { 184 MAPPED_EL2_SYSREG(SCTLR_EL2, SCTLR_EL1, 185 translate_sctlr_el2_to_sctlr_el1 ); 186 MAPPED_EL2_SYSREG(CPTR_EL2, CPACR_EL1, 187 translate_cptr_el2_to_cpacr_el1 ); 188 MAPPED_EL2_SYSREG(TTBR0_EL2, TTBR0_EL1, 189 translate_ttbr0_el2_to_ttbr0_el1 ); 190 MAPPED_EL2_SYSREG(TTBR1_EL2, TTBR1_EL1, NULL ); 191 MAPPED_EL2_SYSREG(TCR_EL2, TCR_EL1, 192 translate_tcr_el2_to_tcr_el1 ); 193 MAPPED_EL2_SYSREG(VBAR_EL2, VBAR_EL1, NULL ); 194 MAPPED_EL2_SYSREG(AFSR0_EL2, AFSR0_EL1, NULL ); 195 MAPPED_EL2_SYSREG(AFSR1_EL2, AFSR1_EL1, NULL ); 196 MAPPED_EL2_SYSREG(ESR_EL2, ESR_EL1, NULL ); 197 MAPPED_EL2_SYSREG(FAR_EL2, FAR_EL1, NULL ); 198 MAPPED_EL2_SYSREG(MAIR_EL2, MAIR_EL1, NULL ); 199 MAPPED_EL2_SYSREG(TCR2_EL2, TCR2_EL1, NULL ); 200 MAPPED_EL2_SYSREG(PIR_EL2, PIR_EL1, NULL ); 201 MAPPED_EL2_SYSREG(PIRE0_EL2, PIRE0_EL1, NULL ); 202 MAPPED_EL2_SYSREG(POR_EL2, POR_EL1, NULL ); 203 MAPPED_EL2_SYSREG(AMAIR_EL2, AMAIR_EL1, NULL ); 204 MAPPED_EL2_SYSREG(ELR_EL2, ELR_EL1, NULL ); 205 MAPPED_EL2_SYSREG(SPSR_EL2, SPSR_EL1, NULL ); 206 MAPPED_EL2_SYSREG(CONTEXTIDR_EL2, CONTEXTIDR_EL1, NULL ); 207 MAPPED_EL2_SYSREG(SCTLR2_EL2, SCTLR2_EL1, NULL ); 208 case CNTHCTL_EL2: 209 /* CNTHCTL_EL2 is super special, until we support NV2.1 */ 210 loc->loc = ((is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) ? 211 SR_LOC_SPECIAL : SR_LOC_MEMORY); 212 break; 213 default: 214 loc->loc = locate_direct_register(vcpu, reg); 215 } 216 } 217 218 static u64 read_sr_from_cpu(enum vcpu_sysreg reg) 219 { 220 u64 val = 0x8badf00d8badf00d; 221 222 switch (reg) { 223 case SCTLR_EL1: val = read_sysreg_s(SYS_SCTLR_EL12); break; 224 case CPACR_EL1: val = read_sysreg_s(SYS_CPACR_EL12); break; 225 case TTBR0_EL1: val = read_sysreg_s(SYS_TTBR0_EL12); break; 226 case TTBR1_EL1: val = read_sysreg_s(SYS_TTBR1_EL12); break; 227 case TCR_EL1: val = read_sysreg_s(SYS_TCR_EL12); break; 228 case TCR2_EL1: val = read_sysreg_s(SYS_TCR2_EL12); break; 229 case PIR_EL1: val = read_sysreg_s(SYS_PIR_EL12); break; 230 case PIRE0_EL1: val = read_sysreg_s(SYS_PIRE0_EL12); break; 231 case POR_EL1: val = read_sysreg_s(SYS_POR_EL12); break; 232 case ESR_EL1: val = read_sysreg_s(SYS_ESR_EL12); break; 233 case AFSR0_EL1: val = read_sysreg_s(SYS_AFSR0_EL12); break; 234 case AFSR1_EL1: val = read_sysreg_s(SYS_AFSR1_EL12); break; 235 case FAR_EL1: val = read_sysreg_s(SYS_FAR_EL12); break; 236 case MAIR_EL1: val = read_sysreg_s(SYS_MAIR_EL12); break; 237 case VBAR_EL1: val = read_sysreg_s(SYS_VBAR_EL12); break; 238 case CONTEXTIDR_EL1: val = read_sysreg_s(SYS_CONTEXTIDR_EL12);break; 239 case AMAIR_EL1: val = read_sysreg_s(SYS_AMAIR_EL12); break; 240 case CNTKCTL_EL1: val = read_sysreg_s(SYS_CNTKCTL_EL12); break; 241 case ELR_EL1: val = read_sysreg_s(SYS_ELR_EL12); break; 242 case SPSR_EL1: val = read_sysreg_s(SYS_SPSR_EL12); break; 243 case ZCR_EL1: val = read_sysreg_s(SYS_ZCR_EL12); break; 244 case SCTLR2_EL1: val = read_sysreg_s(SYS_SCTLR2_EL12); break; 245 case TPIDR_EL0: val = read_sysreg_s(SYS_TPIDR_EL0); break; 246 case TPIDRRO_EL0: val = read_sysreg_s(SYS_TPIDRRO_EL0); break; 247 case TPIDR_EL1: val = read_sysreg_s(SYS_TPIDR_EL1); break; 248 case PAR_EL1: val = read_sysreg_par(); break; 249 case DACR32_EL2: val = read_sysreg_s(SYS_DACR32_EL2); break; 250 case IFSR32_EL2: val = read_sysreg_s(SYS_IFSR32_EL2); break; 251 case DBGVCR32_EL2: val = read_sysreg_s(SYS_DBGVCR32_EL2); break; 252 default: WARN_ON_ONCE(1); 253 } 254 255 return val; 256 } 257 258 static void write_sr_to_cpu(enum vcpu_sysreg reg, u64 val) 259 { 260 switch (reg) { 261 case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); break; 262 case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); break; 263 case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); break; 264 case TTBR1_EL1: write_sysreg_s(val, SYS_TTBR1_EL12); break; 265 case TCR_EL1: write_sysreg_s(val, SYS_TCR_EL12); break; 266 case TCR2_EL1: write_sysreg_s(val, SYS_TCR2_EL12); break; 267 case PIR_EL1: write_sysreg_s(val, SYS_PIR_EL12); break; 268 case PIRE0_EL1: write_sysreg_s(val, SYS_PIRE0_EL12); break; 269 case POR_EL1: write_sysreg_s(val, SYS_POR_EL12); break; 270 case ESR_EL1: write_sysreg_s(val, SYS_ESR_EL12); break; 271 case AFSR0_EL1: write_sysreg_s(val, SYS_AFSR0_EL12); break; 272 case AFSR1_EL1: write_sysreg_s(val, SYS_AFSR1_EL12); break; 273 case FAR_EL1: write_sysreg_s(val, SYS_FAR_EL12); break; 274 case MAIR_EL1: write_sysreg_s(val, SYS_MAIR_EL12); break; 275 case VBAR_EL1: write_sysreg_s(val, SYS_VBAR_EL12); break; 276 case CONTEXTIDR_EL1: write_sysreg_s(val, SYS_CONTEXTIDR_EL12);break; 277 case AMAIR_EL1: write_sysreg_s(val, SYS_AMAIR_EL12); break; 278 case CNTKCTL_EL1: write_sysreg_s(val, SYS_CNTKCTL_EL12); break; 279 case ELR_EL1: write_sysreg_s(val, SYS_ELR_EL12); break; 280 case SPSR_EL1: write_sysreg_s(val, SYS_SPSR_EL12); break; 281 case ZCR_EL1: write_sysreg_s(val, SYS_ZCR_EL12); break; 282 case SCTLR2_EL1: write_sysreg_s(val, SYS_SCTLR2_EL12); break; 283 case TPIDR_EL0: write_sysreg_s(val, SYS_TPIDR_EL0); break; 284 case TPIDRRO_EL0: write_sysreg_s(val, SYS_TPIDRRO_EL0); break; 285 case TPIDR_EL1: write_sysreg_s(val, SYS_TPIDR_EL1); break; 286 case PAR_EL1: write_sysreg_s(val, SYS_PAR_EL1); break; 287 case DACR32_EL2: write_sysreg_s(val, SYS_DACR32_EL2); break; 288 case IFSR32_EL2: write_sysreg_s(val, SYS_IFSR32_EL2); break; 289 case DBGVCR32_EL2: write_sysreg_s(val, SYS_DBGVCR32_EL2); break; 290 default: WARN_ON_ONCE(1); 291 } 292 } 293 294 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, enum vcpu_sysreg reg) 295 { 296 struct sr_loc loc = {}; 297 298 locate_register(vcpu, reg, &loc); 299 300 WARN_ON_ONCE(!has_vhe() && loc.loc != SR_LOC_MEMORY); 301 302 if (loc.loc & SR_LOC_SPECIAL) { 303 u64 val; 304 305 WARN_ON_ONCE(loc.loc & ~SR_LOC_SPECIAL); 306 307 /* 308 * CNTHCTL_EL2 requires some special treatment to account 309 * for the bits that can be set via CNTKCTL_EL1 when E2H==1. 310 */ 311 switch (reg) { 312 case CNTHCTL_EL2: 313 val = read_sysreg_el1(SYS_CNTKCTL); 314 val &= CNTKCTL_VALID_BITS; 315 val |= __vcpu_sys_reg(vcpu, reg) & ~CNTKCTL_VALID_BITS; 316 return val; 317 default: 318 WARN_ON_ONCE(1); 319 } 320 } 321 322 if (loc.loc & SR_LOC_LOADED) { 323 enum vcpu_sysreg map_reg = reg; 324 325 if (loc.loc & SR_LOC_MAPPED) 326 map_reg = loc.map_reg; 327 328 if (!(loc.loc & SR_LOC_XLATED)) { 329 u64 val = read_sr_from_cpu(map_reg); 330 331 if (reg >= __SANITISED_REG_START__) 332 val = kvm_vcpu_apply_reg_masks(vcpu, reg, val); 333 334 return val; 335 } 336 } 337 338 return __vcpu_sys_reg(vcpu, reg); 339 } 340 341 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, enum vcpu_sysreg reg) 342 { 343 struct sr_loc loc = {}; 344 345 locate_register(vcpu, reg, &loc); 346 347 WARN_ON_ONCE(!has_vhe() && loc.loc != SR_LOC_MEMORY); 348 349 if (loc.loc & SR_LOC_SPECIAL) { 350 351 WARN_ON_ONCE(loc.loc & ~SR_LOC_SPECIAL); 352 353 switch (reg) { 354 case CNTHCTL_EL2: 355 /* 356 * If E2H=1, some of the bits are backed by 357 * CNTKCTL_EL1, while the rest is kept in memory. 358 * Yes, this is fun stuff. 359 */ 360 write_sysreg_el1(val, SYS_CNTKCTL); 361 break; 362 default: 363 WARN_ON_ONCE(1); 364 } 365 } 366 367 if (loc.loc & SR_LOC_LOADED) { 368 enum vcpu_sysreg map_reg = reg; 369 u64 xlated_val; 370 371 if (reg >= __SANITISED_REG_START__) 372 val = kvm_vcpu_apply_reg_masks(vcpu, reg, val); 373 374 if (loc.loc & SR_LOC_MAPPED) 375 map_reg = loc.map_reg; 376 377 if (loc.loc & SR_LOC_XLATED) 378 xlated_val = loc.xlate(val); 379 else 380 xlated_val = val; 381 382 write_sr_to_cpu(map_reg, xlated_val); 383 384 /* 385 * Fall through to write the backing store anyway, which 386 * allows translated registers to be directly read without a 387 * reverse translation. 388 */ 389 } 390 391 __vcpu_assign_sys_reg(vcpu, reg, val); 392 } 393 394 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */ 395 #define CSSELR_MAX 14 396 397 /* 398 * Returns the minimum line size for the selected cache, expressed as 399 * Log2(bytes). 400 */ 401 static u8 get_min_cache_line_size(bool icache) 402 { 403 u64 ctr = read_sanitised_ftr_reg(SYS_CTR_EL0); 404 u8 field; 405 406 if (icache) 407 field = SYS_FIELD_GET(CTR_EL0, IminLine, ctr); 408 else 409 field = SYS_FIELD_GET(CTR_EL0, DminLine, ctr); 410 411 /* 412 * Cache line size is represented as Log2(words) in CTR_EL0. 413 * Log2(bytes) can be derived with the following: 414 * 415 * Log2(words) + 2 = Log2(bytes / 4) + 2 416 * = Log2(bytes) - 2 + 2 417 * = Log2(bytes) 418 */ 419 return field + 2; 420 } 421 422 /* Which cache CCSIDR represents depends on CSSELR value. */ 423 static u32 get_ccsidr(struct kvm_vcpu *vcpu, u32 csselr) 424 { 425 u8 line_size; 426 427 if (vcpu->arch.ccsidr) 428 return vcpu->arch.ccsidr[csselr]; 429 430 line_size = get_min_cache_line_size(csselr & CSSELR_EL1_InD); 431 432 /* 433 * Fabricate a CCSIDR value as the overriding value does not exist. 434 * The real CCSIDR value will not be used as it can vary by the 435 * physical CPU which the vcpu currently resides in. 436 * 437 * The line size is determined with get_min_cache_line_size(), which 438 * should be valid for all CPUs even if they have different cache 439 * configuration. 440 * 441 * The associativity bits are cleared, meaning the geometry of all data 442 * and unified caches (which are guaranteed to be PIPT and thus 443 * non-aliasing) are 1 set and 1 way. 444 * Guests should not be doing cache operations by set/way at all, and 445 * for this reason, we trap them and attempt to infer the intent, so 446 * that we can flush the entire guest's address space at the appropriate 447 * time. The exposed geometry minimizes the number of the traps. 448 * [If guests should attempt to infer aliasing properties from the 449 * geometry (which is not permitted by the architecture), they would 450 * only do so for virtually indexed caches.] 451 * 452 * We don't check if the cache level exists as it is allowed to return 453 * an UNKNOWN value if not. 454 */ 455 return SYS_FIELD_PREP(CCSIDR_EL1, LineSize, line_size - 4); 456 } 457 458 static int set_ccsidr(struct kvm_vcpu *vcpu, u32 csselr, u32 val) 459 { 460 u8 line_size = FIELD_GET(CCSIDR_EL1_LineSize, val) + 4; 461 u32 *ccsidr = vcpu->arch.ccsidr; 462 u32 i; 463 464 if ((val & CCSIDR_EL1_RES0) || 465 line_size < get_min_cache_line_size(csselr & CSSELR_EL1_InD)) 466 return -EINVAL; 467 468 if (!ccsidr) { 469 if (val == get_ccsidr(vcpu, csselr)) 470 return 0; 471 472 ccsidr = kmalloc_array(CSSELR_MAX, sizeof(u32), GFP_KERNEL_ACCOUNT); 473 if (!ccsidr) 474 return -ENOMEM; 475 476 for (i = 0; i < CSSELR_MAX; i++) 477 ccsidr[i] = get_ccsidr(vcpu, i); 478 479 vcpu->arch.ccsidr = ccsidr; 480 } 481 482 ccsidr[csselr] = val; 483 484 return 0; 485 } 486 487 static bool access_rw(struct kvm_vcpu *vcpu, 488 struct sys_reg_params *p, 489 const struct sys_reg_desc *r) 490 { 491 if (p->is_write) 492 vcpu_write_sys_reg(vcpu, p->regval, r->reg); 493 else 494 p->regval = vcpu_read_sys_reg(vcpu, r->reg); 495 496 return true; 497 } 498 499 /* 500 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized). 501 */ 502 static bool access_dcsw(struct kvm_vcpu *vcpu, 503 struct sys_reg_params *p, 504 const struct sys_reg_desc *r) 505 { 506 if (!p->is_write) 507 return read_from_write_only(vcpu, p, r); 508 509 /* 510 * Only track S/W ops if we don't have FWB. It still indicates 511 * that the guest is a bit broken (S/W operations should only 512 * be done by firmware, knowing that there is only a single 513 * CPU left in the system, and certainly not from non-secure 514 * software). 515 */ 516 if (!cpus_have_final_cap(ARM64_HAS_STAGE2_FWB)) 517 kvm_set_way_flush(vcpu); 518 519 return true; 520 } 521 522 static bool access_dcgsw(struct kvm_vcpu *vcpu, 523 struct sys_reg_params *p, 524 const struct sys_reg_desc *r) 525 { 526 if (!kvm_has_mte(vcpu->kvm)) 527 return undef_access(vcpu, p, r); 528 529 /* Treat MTE S/W ops as we treat the classic ones: with contempt */ 530 return access_dcsw(vcpu, p, r); 531 } 532 533 static void get_access_mask(const struct sys_reg_desc *r, u64 *mask, u64 *shift) 534 { 535 switch (r->aarch32_map) { 536 case AA32_LO: 537 *mask = GENMASK_ULL(31, 0); 538 *shift = 0; 539 break; 540 case AA32_HI: 541 *mask = GENMASK_ULL(63, 32); 542 *shift = 32; 543 break; 544 default: 545 *mask = GENMASK_ULL(63, 0); 546 *shift = 0; 547 break; 548 } 549 } 550 551 /* 552 * Generic accessor for VM registers. Only called as long as HCR_TVM 553 * is set. If the guest enables the MMU, we stop trapping the VM 554 * sys_regs and leave it in complete control of the caches. 555 */ 556 static bool access_vm_reg(struct kvm_vcpu *vcpu, 557 struct sys_reg_params *p, 558 const struct sys_reg_desc *r) 559 { 560 bool was_enabled = vcpu_has_cache_enabled(vcpu); 561 u64 val, mask, shift; 562 563 BUG_ON(!p->is_write); 564 565 get_access_mask(r, &mask, &shift); 566 567 if (~mask) { 568 val = vcpu_read_sys_reg(vcpu, r->reg); 569 val &= ~mask; 570 } else { 571 val = 0; 572 } 573 574 val |= (p->regval & (mask >> shift)) << shift; 575 vcpu_write_sys_reg(vcpu, val, r->reg); 576 577 kvm_toggle_cache(vcpu, was_enabled); 578 return true; 579 } 580 581 static bool access_actlr(struct kvm_vcpu *vcpu, 582 struct sys_reg_params *p, 583 const struct sys_reg_desc *r) 584 { 585 u64 mask, shift; 586 587 if (p->is_write) 588 return ignore_write(vcpu, p); 589 590 get_access_mask(r, &mask, &shift); 591 p->regval = (vcpu_read_sys_reg(vcpu, r->reg) & mask) >> shift; 592 593 return true; 594 } 595 596 /* 597 * Trap handler for the GICv3 SGI generation system register. 598 * Forward the request to the VGIC emulation. 599 * The cp15_64 code makes sure this automatically works 600 * for both AArch64 and AArch32 accesses. 601 */ 602 static bool access_gic_sgi(struct kvm_vcpu *vcpu, 603 struct sys_reg_params *p, 604 const struct sys_reg_desc *r) 605 { 606 bool g1; 607 608 if (!kvm_has_gicv3(vcpu->kvm)) 609 return undef_access(vcpu, p, r); 610 611 if (!p->is_write) 612 return read_from_write_only(vcpu, p, r); 613 614 /* 615 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates 616 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group, 617 * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively 618 * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure 619 * group. 620 */ 621 if (p->Op0 == 0) { /* AArch32 */ 622 switch (p->Op1) { 623 default: /* Keep GCC quiet */ 624 case 0: /* ICC_SGI1R */ 625 g1 = true; 626 break; 627 case 1: /* ICC_ASGI1R */ 628 case 2: /* ICC_SGI0R */ 629 g1 = false; 630 break; 631 } 632 } else { /* AArch64 */ 633 switch (p->Op2) { 634 default: /* Keep GCC quiet */ 635 case 5: /* ICC_SGI1R_EL1 */ 636 g1 = true; 637 break; 638 case 6: /* ICC_ASGI1R_EL1 */ 639 case 7: /* ICC_SGI0R_EL1 */ 640 g1 = false; 641 break; 642 } 643 } 644 645 vgic_v3_dispatch_sgi(vcpu, p->regval, g1); 646 647 return true; 648 } 649 650 static bool access_gic_sre(struct kvm_vcpu *vcpu, 651 struct sys_reg_params *p, 652 const struct sys_reg_desc *r) 653 { 654 if (!kvm_has_gicv3(vcpu->kvm)) 655 return undef_access(vcpu, p, r); 656 657 if (p->is_write) 658 return ignore_write(vcpu, p); 659 660 if (p->Op1 == 4) { /* ICC_SRE_EL2 */ 661 p->regval = KVM_ICC_SRE_EL2; 662 } else { /* ICC_SRE_EL1 */ 663 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre; 664 } 665 666 return true; 667 } 668 669 static bool trap_raz_wi(struct kvm_vcpu *vcpu, 670 struct sys_reg_params *p, 671 const struct sys_reg_desc *r) 672 { 673 if (p->is_write) 674 return ignore_write(vcpu, p); 675 else 676 return read_zero(vcpu, p); 677 } 678 679 /* 680 * ARMv8.1 mandates at least a trivial LORegion implementation, where all the 681 * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0 682 * system, these registers should UNDEF. LORID_EL1 being a RO register, we 683 * treat it separately. 684 */ 685 static bool trap_loregion(struct kvm_vcpu *vcpu, 686 struct sys_reg_params *p, 687 const struct sys_reg_desc *r) 688 { 689 u32 sr = reg_to_encoding(r); 690 691 if (!kvm_has_feat(vcpu->kvm, ID_AA64MMFR1_EL1, LO, IMP)) 692 return undef_access(vcpu, p, r); 693 694 if (p->is_write && sr == SYS_LORID_EL1) 695 return write_to_read_only(vcpu, p, r); 696 697 return trap_raz_wi(vcpu, p, r); 698 } 699 700 static bool trap_oslar_el1(struct kvm_vcpu *vcpu, 701 struct sys_reg_params *p, 702 const struct sys_reg_desc *r) 703 { 704 if (!p->is_write) 705 return read_from_write_only(vcpu, p, r); 706 707 kvm_debug_handle_oslar(vcpu, p->regval); 708 return true; 709 } 710 711 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu, 712 struct sys_reg_params *p, 713 const struct sys_reg_desc *r) 714 { 715 if (p->is_write) 716 return write_to_read_only(vcpu, p, r); 717 718 p->regval = __vcpu_sys_reg(vcpu, r->reg); 719 return true; 720 } 721 722 static int set_oslsr_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 723 u64 val) 724 { 725 /* 726 * The only modifiable bit is the OSLK bit. Refuse the write if 727 * userspace attempts to change any other bit in the register. 728 */ 729 if ((val ^ rd->val) & ~OSLSR_EL1_OSLK) 730 return -EINVAL; 731 732 __vcpu_assign_sys_reg(vcpu, rd->reg, val); 733 return 0; 734 } 735 736 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu, 737 struct sys_reg_params *p, 738 const struct sys_reg_desc *r) 739 { 740 if (p->is_write) { 741 return ignore_write(vcpu, p); 742 } else { 743 p->regval = read_sysreg(dbgauthstatus_el1); 744 return true; 745 } 746 } 747 748 static bool trap_debug_regs(struct kvm_vcpu *vcpu, 749 struct sys_reg_params *p, 750 const struct sys_reg_desc *r) 751 { 752 access_rw(vcpu, p, r); 753 754 kvm_debug_set_guest_ownership(vcpu); 755 return true; 756 } 757 758 /* 759 * reg_to_dbg/dbg_to_reg 760 * 761 * A 32 bit write to a debug register leave top bits alone 762 * A 32 bit read from a debug register only returns the bottom bits 763 */ 764 static void reg_to_dbg(struct kvm_vcpu *vcpu, 765 struct sys_reg_params *p, 766 const struct sys_reg_desc *rd, 767 u64 *dbg_reg) 768 { 769 u64 mask, shift, val; 770 771 get_access_mask(rd, &mask, &shift); 772 773 val = *dbg_reg; 774 val &= ~mask; 775 val |= (p->regval & (mask >> shift)) << shift; 776 *dbg_reg = val; 777 } 778 779 static void dbg_to_reg(struct kvm_vcpu *vcpu, 780 struct sys_reg_params *p, 781 const struct sys_reg_desc *rd, 782 u64 *dbg_reg) 783 { 784 u64 mask, shift; 785 786 get_access_mask(rd, &mask, &shift); 787 p->regval = (*dbg_reg & mask) >> shift; 788 } 789 790 static u64 *demux_wb_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd) 791 { 792 struct kvm_guest_debug_arch *dbg = &vcpu->arch.vcpu_debug_state; 793 794 switch (rd->Op2) { 795 case 0b100: 796 return &dbg->dbg_bvr[rd->CRm]; 797 case 0b101: 798 return &dbg->dbg_bcr[rd->CRm]; 799 case 0b110: 800 return &dbg->dbg_wvr[rd->CRm]; 801 case 0b111: 802 return &dbg->dbg_wcr[rd->CRm]; 803 default: 804 KVM_BUG_ON(1, vcpu->kvm); 805 return NULL; 806 } 807 } 808 809 static bool trap_dbg_wb_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 810 const struct sys_reg_desc *rd) 811 { 812 u64 *reg = demux_wb_reg(vcpu, rd); 813 814 if (!reg) 815 return false; 816 817 if (p->is_write) 818 reg_to_dbg(vcpu, p, rd, reg); 819 else 820 dbg_to_reg(vcpu, p, rd, reg); 821 822 kvm_debug_set_guest_ownership(vcpu); 823 return true; 824 } 825 826 static int set_dbg_wb_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 827 u64 val) 828 { 829 u64 *reg = demux_wb_reg(vcpu, rd); 830 831 if (!reg) 832 return -EINVAL; 833 834 *reg = val; 835 return 0; 836 } 837 838 static int get_dbg_wb_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 839 u64 *val) 840 { 841 u64 *reg = demux_wb_reg(vcpu, rd); 842 843 if (!reg) 844 return -EINVAL; 845 846 *val = *reg; 847 return 0; 848 } 849 850 static u64 reset_dbg_wb_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd) 851 { 852 u64 *reg = demux_wb_reg(vcpu, rd); 853 854 /* 855 * Bail early if we couldn't find storage for the register, the 856 * KVM_BUG_ON() in demux_wb_reg() will prevent this VM from ever 857 * being run. 858 */ 859 if (!reg) 860 return 0; 861 862 *reg = rd->val; 863 return rd->val; 864 } 865 866 static u64 reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 867 { 868 u64 amair = read_sysreg(amair_el1); 869 vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1); 870 return amair; 871 } 872 873 static u64 reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 874 { 875 u64 actlr = read_sysreg(actlr_el1); 876 vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1); 877 return actlr; 878 } 879 880 static u64 reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 881 { 882 u64 mpidr; 883 884 /* 885 * Map the vcpu_id into the first three affinity level fields of 886 * the MPIDR. We limit the number of VCPUs in level 0 due to a 887 * limitation to 16 CPUs in that level in the ICC_SGIxR registers 888 * of the GICv3 to be able to address each CPU directly when 889 * sending IPIs. 890 */ 891 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0); 892 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1); 893 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2); 894 mpidr |= (1ULL << 31); 895 vcpu_write_sys_reg(vcpu, mpidr, MPIDR_EL1); 896 897 return mpidr; 898 } 899 900 static unsigned int hidden_visibility(const struct kvm_vcpu *vcpu, 901 const struct sys_reg_desc *r) 902 { 903 return REG_HIDDEN; 904 } 905 906 static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu, 907 const struct sys_reg_desc *r) 908 { 909 if (kvm_vcpu_has_pmu(vcpu)) 910 return 0; 911 912 return REG_HIDDEN; 913 } 914 915 static u64 reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 916 { 917 u64 mask = BIT(ARMV8_PMU_CYCLE_IDX); 918 u8 n = vcpu->kvm->arch.nr_pmu_counters; 919 920 if (n) 921 mask |= GENMASK(n - 1, 0); 922 923 reset_unknown(vcpu, r); 924 __vcpu_rmw_sys_reg(vcpu, r->reg, &=, mask); 925 926 return __vcpu_sys_reg(vcpu, r->reg); 927 } 928 929 static u64 reset_pmevcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 930 { 931 reset_unknown(vcpu, r); 932 __vcpu_rmw_sys_reg(vcpu, r->reg, &=, GENMASK(31, 0)); 933 934 return __vcpu_sys_reg(vcpu, r->reg); 935 } 936 937 static u64 reset_pmevtyper(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 938 { 939 /* This thing will UNDEF, who cares about the reset value? */ 940 if (!kvm_vcpu_has_pmu(vcpu)) 941 return 0; 942 943 reset_unknown(vcpu, r); 944 __vcpu_rmw_sys_reg(vcpu, r->reg, &=, kvm_pmu_evtyper_mask(vcpu->kvm)); 945 946 return __vcpu_sys_reg(vcpu, r->reg); 947 } 948 949 static u64 reset_pmselr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 950 { 951 reset_unknown(vcpu, r); 952 __vcpu_rmw_sys_reg(vcpu, r->reg, &=, PMSELR_EL0_SEL_MASK); 953 954 return __vcpu_sys_reg(vcpu, r->reg); 955 } 956 957 static u64 reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 958 { 959 u64 pmcr = 0; 960 961 if (!kvm_supports_32bit_el0()) 962 pmcr |= ARMV8_PMU_PMCR_LC; 963 964 /* 965 * The value of PMCR.N field is included when the 966 * vCPU register is read via kvm_vcpu_read_pmcr(). 967 */ 968 __vcpu_assign_sys_reg(vcpu, r->reg, pmcr); 969 970 return __vcpu_sys_reg(vcpu, r->reg); 971 } 972 973 static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags) 974 { 975 u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0); 976 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu); 977 978 if (!enabled) 979 kvm_inject_undefined(vcpu); 980 981 return !enabled; 982 } 983 984 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu) 985 { 986 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN); 987 } 988 989 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu) 990 { 991 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN); 992 } 993 994 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu) 995 { 996 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN); 997 } 998 999 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu) 1000 { 1001 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN); 1002 } 1003 1004 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1005 const struct sys_reg_desc *r) 1006 { 1007 u64 val; 1008 1009 if (pmu_access_el0_disabled(vcpu)) 1010 return false; 1011 1012 if (p->is_write) { 1013 /* 1014 * Only update writeable bits of PMCR (continuing into 1015 * kvm_pmu_handle_pmcr() as well) 1016 */ 1017 val = kvm_vcpu_read_pmcr(vcpu); 1018 val &= ~ARMV8_PMU_PMCR_MASK; 1019 val |= p->regval & ARMV8_PMU_PMCR_MASK; 1020 if (!kvm_supports_32bit_el0()) 1021 val |= ARMV8_PMU_PMCR_LC; 1022 kvm_pmu_handle_pmcr(vcpu, val); 1023 } else { 1024 /* PMCR.P & PMCR.C are RAZ */ 1025 val = kvm_vcpu_read_pmcr(vcpu) 1026 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C); 1027 p->regval = val; 1028 } 1029 1030 return true; 1031 } 1032 1033 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1034 const struct sys_reg_desc *r) 1035 { 1036 if (pmu_access_event_counter_el0_disabled(vcpu)) 1037 return false; 1038 1039 if (p->is_write) 1040 __vcpu_assign_sys_reg(vcpu, PMSELR_EL0, p->regval); 1041 else 1042 /* return PMSELR.SEL field */ 1043 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0) 1044 & PMSELR_EL0_SEL_MASK; 1045 1046 return true; 1047 } 1048 1049 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1050 const struct sys_reg_desc *r) 1051 { 1052 u64 pmceid, mask, shift; 1053 1054 BUG_ON(p->is_write); 1055 1056 if (pmu_access_el0_disabled(vcpu)) 1057 return false; 1058 1059 get_access_mask(r, &mask, &shift); 1060 1061 pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1)); 1062 pmceid &= mask; 1063 pmceid >>= shift; 1064 1065 p->regval = pmceid; 1066 1067 return true; 1068 } 1069 1070 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx) 1071 { 1072 u64 pmcr, val; 1073 1074 pmcr = kvm_vcpu_read_pmcr(vcpu); 1075 val = FIELD_GET(ARMV8_PMU_PMCR_N, pmcr); 1076 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) { 1077 kvm_inject_undefined(vcpu); 1078 return false; 1079 } 1080 1081 return true; 1082 } 1083 1084 static int get_pmu_evcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 1085 u64 *val) 1086 { 1087 u64 idx; 1088 1089 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 0) 1090 /* PMCCNTR_EL0 */ 1091 idx = ARMV8_PMU_CYCLE_IDX; 1092 else 1093 /* PMEVCNTRn_EL0 */ 1094 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 1095 1096 *val = kvm_pmu_get_counter_value(vcpu, idx); 1097 return 0; 1098 } 1099 1100 static int set_pmu_evcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 1101 u64 val) 1102 { 1103 u64 idx; 1104 1105 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 0) 1106 /* PMCCNTR_EL0 */ 1107 idx = ARMV8_PMU_CYCLE_IDX; 1108 else 1109 /* PMEVCNTRn_EL0 */ 1110 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 1111 1112 kvm_pmu_set_counter_value_user(vcpu, idx, val); 1113 return 0; 1114 } 1115 1116 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu, 1117 struct sys_reg_params *p, 1118 const struct sys_reg_desc *r) 1119 { 1120 u64 idx = ~0UL; 1121 1122 if (r->CRn == 9 && r->CRm == 13) { 1123 if (r->Op2 == 2) { 1124 /* PMXEVCNTR_EL0 */ 1125 if (pmu_access_event_counter_el0_disabled(vcpu)) 1126 return false; 1127 1128 idx = SYS_FIELD_GET(PMSELR_EL0, SEL, 1129 __vcpu_sys_reg(vcpu, PMSELR_EL0)); 1130 } else if (r->Op2 == 0) { 1131 /* PMCCNTR_EL0 */ 1132 if (pmu_access_cycle_counter_el0_disabled(vcpu)) 1133 return false; 1134 1135 idx = ARMV8_PMU_CYCLE_IDX; 1136 } 1137 } else if (r->CRn == 0 && r->CRm == 9) { 1138 /* PMCCNTR */ 1139 if (pmu_access_event_counter_el0_disabled(vcpu)) 1140 return false; 1141 1142 idx = ARMV8_PMU_CYCLE_IDX; 1143 } else if (r->CRn == 14 && (r->CRm & 12) == 8) { 1144 /* PMEVCNTRn_EL0 */ 1145 if (pmu_access_event_counter_el0_disabled(vcpu)) 1146 return false; 1147 1148 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 1149 } 1150 1151 /* Catch any decoding mistake */ 1152 WARN_ON(idx == ~0UL); 1153 1154 if (!pmu_counter_idx_valid(vcpu, idx)) 1155 return false; 1156 1157 if (p->is_write) { 1158 if (pmu_access_el0_disabled(vcpu)) 1159 return false; 1160 1161 kvm_pmu_set_counter_value(vcpu, idx, p->regval); 1162 } else { 1163 p->regval = kvm_pmu_get_counter_value(vcpu, idx); 1164 } 1165 1166 return true; 1167 } 1168 1169 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1170 const struct sys_reg_desc *r) 1171 { 1172 u64 idx, reg; 1173 1174 if (pmu_access_el0_disabled(vcpu)) 1175 return false; 1176 1177 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) { 1178 /* PMXEVTYPER_EL0 */ 1179 idx = SYS_FIELD_GET(PMSELR_EL0, SEL, __vcpu_sys_reg(vcpu, PMSELR_EL0)); 1180 reg = PMEVTYPER0_EL0 + idx; 1181 } else if (r->CRn == 14 && (r->CRm & 12) == 12) { 1182 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 1183 if (idx == ARMV8_PMU_CYCLE_IDX) 1184 reg = PMCCFILTR_EL0; 1185 else 1186 /* PMEVTYPERn_EL0 */ 1187 reg = PMEVTYPER0_EL0 + idx; 1188 } else { 1189 BUG(); 1190 } 1191 1192 if (!pmu_counter_idx_valid(vcpu, idx)) 1193 return false; 1194 1195 if (p->is_write) { 1196 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx); 1197 kvm_vcpu_pmu_restore_guest(vcpu); 1198 } else { 1199 p->regval = __vcpu_sys_reg(vcpu, reg); 1200 } 1201 1202 return true; 1203 } 1204 1205 static int set_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 val) 1206 { 1207 u64 mask = kvm_pmu_accessible_counter_mask(vcpu); 1208 1209 __vcpu_assign_sys_reg(vcpu, r->reg, val & mask); 1210 kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu); 1211 1212 return 0; 1213 } 1214 1215 static int get_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 *val) 1216 { 1217 u64 mask = kvm_pmu_accessible_counter_mask(vcpu); 1218 1219 *val = __vcpu_sys_reg(vcpu, r->reg) & mask; 1220 return 0; 1221 } 1222 1223 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1224 const struct sys_reg_desc *r) 1225 { 1226 u64 val, mask; 1227 1228 if (pmu_access_el0_disabled(vcpu)) 1229 return false; 1230 1231 mask = kvm_pmu_accessible_counter_mask(vcpu); 1232 if (p->is_write) { 1233 val = p->regval & mask; 1234 if (r->Op2 & 0x1) 1235 /* accessing PMCNTENSET_EL0 */ 1236 __vcpu_rmw_sys_reg(vcpu, PMCNTENSET_EL0, |=, val); 1237 else 1238 /* accessing PMCNTENCLR_EL0 */ 1239 __vcpu_rmw_sys_reg(vcpu, PMCNTENSET_EL0, &=, ~val); 1240 1241 kvm_pmu_reprogram_counter_mask(vcpu, val); 1242 } else { 1243 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0); 1244 } 1245 1246 return true; 1247 } 1248 1249 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1250 const struct sys_reg_desc *r) 1251 { 1252 u64 mask = kvm_pmu_accessible_counter_mask(vcpu); 1253 1254 if (check_pmu_access_disabled(vcpu, 0)) 1255 return false; 1256 1257 if (p->is_write) { 1258 u64 val = p->regval & mask; 1259 1260 if (r->Op2 & 0x1) 1261 /* accessing PMINTENSET_EL1 */ 1262 __vcpu_rmw_sys_reg(vcpu, PMINTENSET_EL1, |=, val); 1263 else 1264 /* accessing PMINTENCLR_EL1 */ 1265 __vcpu_rmw_sys_reg(vcpu, PMINTENSET_EL1, &=, ~val); 1266 } else { 1267 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1); 1268 } 1269 1270 return true; 1271 } 1272 1273 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1274 const struct sys_reg_desc *r) 1275 { 1276 u64 mask = kvm_pmu_accessible_counter_mask(vcpu); 1277 1278 if (pmu_access_el0_disabled(vcpu)) 1279 return false; 1280 1281 if (p->is_write) { 1282 if (r->CRm & 0x2) 1283 /* accessing PMOVSSET_EL0 */ 1284 __vcpu_rmw_sys_reg(vcpu, PMOVSSET_EL0, |=, (p->regval & mask)); 1285 else 1286 /* accessing PMOVSCLR_EL0 */ 1287 __vcpu_rmw_sys_reg(vcpu, PMOVSSET_EL0, &=, ~(p->regval & mask)); 1288 } else { 1289 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0); 1290 } 1291 1292 return true; 1293 } 1294 1295 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1296 const struct sys_reg_desc *r) 1297 { 1298 u64 mask; 1299 1300 if (!p->is_write) 1301 return read_from_write_only(vcpu, p, r); 1302 1303 if (pmu_write_swinc_el0_disabled(vcpu)) 1304 return false; 1305 1306 mask = kvm_pmu_accessible_counter_mask(vcpu); 1307 kvm_pmu_software_increment(vcpu, p->regval & mask); 1308 return true; 1309 } 1310 1311 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1312 const struct sys_reg_desc *r) 1313 { 1314 if (p->is_write) { 1315 if (!vcpu_mode_priv(vcpu)) 1316 return undef_access(vcpu, p, r); 1317 1318 __vcpu_assign_sys_reg(vcpu, PMUSERENR_EL0, 1319 (p->regval & ARMV8_PMU_USERENR_MASK)); 1320 } else { 1321 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0) 1322 & ARMV8_PMU_USERENR_MASK; 1323 } 1324 1325 return true; 1326 } 1327 1328 static int get_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 1329 u64 *val) 1330 { 1331 *val = kvm_vcpu_read_pmcr(vcpu); 1332 return 0; 1333 } 1334 1335 static int set_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 1336 u64 val) 1337 { 1338 u8 new_n = FIELD_GET(ARMV8_PMU_PMCR_N, val); 1339 struct kvm *kvm = vcpu->kvm; 1340 1341 mutex_lock(&kvm->arch.config_lock); 1342 1343 /* 1344 * The vCPU can't have more counters than the PMU hardware 1345 * implements. Ignore this error to maintain compatibility 1346 * with the existing KVM behavior. 1347 */ 1348 if (!kvm_vm_has_ran_once(kvm) && 1349 !vcpu_has_nv(vcpu) && 1350 new_n <= kvm_arm_pmu_get_max_counters(kvm)) 1351 kvm->arch.nr_pmu_counters = new_n; 1352 1353 mutex_unlock(&kvm->arch.config_lock); 1354 1355 /* 1356 * Ignore writes to RES0 bits, read only bits that are cleared on 1357 * vCPU reset, and writable bits that KVM doesn't support yet. 1358 * (i.e. only PMCR.N and bits [7:0] are mutable from userspace) 1359 * The LP bit is RES0 when FEAT_PMUv3p5 is not supported on the vCPU. 1360 * But, we leave the bit as it is here, as the vCPU's PMUver might 1361 * be changed later (NOTE: the bit will be cleared on first vCPU run 1362 * if necessary). 1363 */ 1364 val &= ARMV8_PMU_PMCR_MASK; 1365 1366 /* The LC bit is RES1 when AArch32 is not supported */ 1367 if (!kvm_supports_32bit_el0()) 1368 val |= ARMV8_PMU_PMCR_LC; 1369 1370 __vcpu_assign_sys_reg(vcpu, r->reg, val); 1371 kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu); 1372 1373 return 0; 1374 } 1375 1376 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */ 1377 #define DBG_BCR_BVR_WCR_WVR_EL1(n) \ 1378 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \ 1379 trap_dbg_wb_reg, reset_dbg_wb_reg, 0, 0, \ 1380 get_dbg_wb_reg, set_dbg_wb_reg }, \ 1381 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \ 1382 trap_dbg_wb_reg, reset_dbg_wb_reg, 0, 0, \ 1383 get_dbg_wb_reg, set_dbg_wb_reg }, \ 1384 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \ 1385 trap_dbg_wb_reg, reset_dbg_wb_reg, 0, 0, \ 1386 get_dbg_wb_reg, set_dbg_wb_reg }, \ 1387 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \ 1388 trap_dbg_wb_reg, reset_dbg_wb_reg, 0, 0, \ 1389 get_dbg_wb_reg, set_dbg_wb_reg } 1390 1391 #define PMU_SYS_REG(name) \ 1392 SYS_DESC(SYS_##name), .reset = reset_pmu_reg, \ 1393 .visibility = pmu_visibility 1394 1395 /* Macro to expand the PMEVCNTRn_EL0 register */ 1396 #define PMU_PMEVCNTR_EL0(n) \ 1397 { PMU_SYS_REG(PMEVCNTRn_EL0(n)), \ 1398 .reset = reset_pmevcntr, .get_user = get_pmu_evcntr, \ 1399 .set_user = set_pmu_evcntr, \ 1400 .access = access_pmu_evcntr, .reg = (PMEVCNTR0_EL0 + n), } 1401 1402 /* Macro to expand the PMEVTYPERn_EL0 register */ 1403 #define PMU_PMEVTYPER_EL0(n) \ 1404 { PMU_SYS_REG(PMEVTYPERn_EL0(n)), \ 1405 .reset = reset_pmevtyper, \ 1406 .access = access_pmu_evtyper, .reg = (PMEVTYPER0_EL0 + n), } 1407 1408 /* Macro to expand the AMU counter and type registers*/ 1409 #define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), undef_access } 1410 #define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), undef_access } 1411 #define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), undef_access } 1412 #define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), undef_access } 1413 1414 static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu, 1415 const struct sys_reg_desc *rd) 1416 { 1417 return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN; 1418 } 1419 1420 /* 1421 * If we land here on a PtrAuth access, that is because we didn't 1422 * fixup the access on exit by allowing the PtrAuth sysregs. The only 1423 * way this happens is when the guest does not have PtrAuth support 1424 * enabled. 1425 */ 1426 #define __PTRAUTH_KEY(k) \ 1427 { SYS_DESC(SYS_## k), undef_access, reset_unknown, k, \ 1428 .visibility = ptrauth_visibility} 1429 1430 #define PTRAUTH_KEY(k) \ 1431 __PTRAUTH_KEY(k ## KEYLO_EL1), \ 1432 __PTRAUTH_KEY(k ## KEYHI_EL1) 1433 1434 static bool access_arch_timer(struct kvm_vcpu *vcpu, 1435 struct sys_reg_params *p, 1436 const struct sys_reg_desc *r) 1437 { 1438 enum kvm_arch_timers tmr; 1439 enum kvm_arch_timer_regs treg; 1440 u64 reg = reg_to_encoding(r); 1441 1442 switch (reg) { 1443 case SYS_CNTP_TVAL_EL0: 1444 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) 1445 tmr = TIMER_HPTIMER; 1446 else 1447 tmr = TIMER_PTIMER; 1448 treg = TIMER_REG_TVAL; 1449 break; 1450 1451 case SYS_CNTV_TVAL_EL0: 1452 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) 1453 tmr = TIMER_HVTIMER; 1454 else 1455 tmr = TIMER_VTIMER; 1456 treg = TIMER_REG_TVAL; 1457 break; 1458 1459 case SYS_AARCH32_CNTP_TVAL: 1460 case SYS_CNTP_TVAL_EL02: 1461 tmr = TIMER_PTIMER; 1462 treg = TIMER_REG_TVAL; 1463 break; 1464 1465 case SYS_CNTV_TVAL_EL02: 1466 tmr = TIMER_VTIMER; 1467 treg = TIMER_REG_TVAL; 1468 break; 1469 1470 case SYS_CNTHP_TVAL_EL2: 1471 tmr = TIMER_HPTIMER; 1472 treg = TIMER_REG_TVAL; 1473 break; 1474 1475 case SYS_CNTHV_TVAL_EL2: 1476 tmr = TIMER_HVTIMER; 1477 treg = TIMER_REG_TVAL; 1478 break; 1479 1480 case SYS_CNTP_CTL_EL0: 1481 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) 1482 tmr = TIMER_HPTIMER; 1483 else 1484 tmr = TIMER_PTIMER; 1485 treg = TIMER_REG_CTL; 1486 break; 1487 1488 case SYS_CNTV_CTL_EL0: 1489 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) 1490 tmr = TIMER_HVTIMER; 1491 else 1492 tmr = TIMER_VTIMER; 1493 treg = TIMER_REG_CTL; 1494 break; 1495 1496 case SYS_AARCH32_CNTP_CTL: 1497 case SYS_CNTP_CTL_EL02: 1498 tmr = TIMER_PTIMER; 1499 treg = TIMER_REG_CTL; 1500 break; 1501 1502 case SYS_CNTV_CTL_EL02: 1503 tmr = TIMER_VTIMER; 1504 treg = TIMER_REG_CTL; 1505 break; 1506 1507 case SYS_CNTHP_CTL_EL2: 1508 tmr = TIMER_HPTIMER; 1509 treg = TIMER_REG_CTL; 1510 break; 1511 1512 case SYS_CNTHV_CTL_EL2: 1513 tmr = TIMER_HVTIMER; 1514 treg = TIMER_REG_CTL; 1515 break; 1516 1517 case SYS_CNTP_CVAL_EL0: 1518 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) 1519 tmr = TIMER_HPTIMER; 1520 else 1521 tmr = TIMER_PTIMER; 1522 treg = TIMER_REG_CVAL; 1523 break; 1524 1525 case SYS_CNTV_CVAL_EL0: 1526 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) 1527 tmr = TIMER_HVTIMER; 1528 else 1529 tmr = TIMER_VTIMER; 1530 treg = TIMER_REG_CVAL; 1531 break; 1532 1533 case SYS_AARCH32_CNTP_CVAL: 1534 case SYS_CNTP_CVAL_EL02: 1535 tmr = TIMER_PTIMER; 1536 treg = TIMER_REG_CVAL; 1537 break; 1538 1539 case SYS_CNTV_CVAL_EL02: 1540 tmr = TIMER_VTIMER; 1541 treg = TIMER_REG_CVAL; 1542 break; 1543 1544 case SYS_CNTHP_CVAL_EL2: 1545 tmr = TIMER_HPTIMER; 1546 treg = TIMER_REG_CVAL; 1547 break; 1548 1549 case SYS_CNTHV_CVAL_EL2: 1550 tmr = TIMER_HVTIMER; 1551 treg = TIMER_REG_CVAL; 1552 break; 1553 1554 case SYS_CNTPCT_EL0: 1555 case SYS_CNTPCTSS_EL0: 1556 if (is_hyp_ctxt(vcpu)) 1557 tmr = TIMER_HPTIMER; 1558 else 1559 tmr = TIMER_PTIMER; 1560 treg = TIMER_REG_CNT; 1561 break; 1562 1563 case SYS_AARCH32_CNTPCT: 1564 case SYS_AARCH32_CNTPCTSS: 1565 tmr = TIMER_PTIMER; 1566 treg = TIMER_REG_CNT; 1567 break; 1568 1569 case SYS_CNTVCT_EL0: 1570 case SYS_CNTVCTSS_EL0: 1571 if (is_hyp_ctxt(vcpu)) 1572 tmr = TIMER_HVTIMER; 1573 else 1574 tmr = TIMER_VTIMER; 1575 treg = TIMER_REG_CNT; 1576 break; 1577 1578 case SYS_AARCH32_CNTVCT: 1579 case SYS_AARCH32_CNTVCTSS: 1580 tmr = TIMER_VTIMER; 1581 treg = TIMER_REG_CNT; 1582 break; 1583 1584 default: 1585 print_sys_reg_msg(p, "%s", "Unhandled trapped timer register"); 1586 return undef_access(vcpu, p, r); 1587 } 1588 1589 if (p->is_write) 1590 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval); 1591 else 1592 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg); 1593 1594 return true; 1595 } 1596 1597 static int arch_timer_set_user(struct kvm_vcpu *vcpu, 1598 const struct sys_reg_desc *rd, 1599 u64 val) 1600 { 1601 switch (reg_to_encoding(rd)) { 1602 case SYS_CNTV_CTL_EL0: 1603 case SYS_CNTP_CTL_EL0: 1604 case SYS_CNTHV_CTL_EL2: 1605 case SYS_CNTHP_CTL_EL2: 1606 val &= ~ARCH_TIMER_CTRL_IT_STAT; 1607 break; 1608 case SYS_CNTVCT_EL0: 1609 if (!test_bit(KVM_ARCH_FLAG_VM_COUNTER_OFFSET, &vcpu->kvm->arch.flags)) 1610 timer_set_offset(vcpu_vtimer(vcpu), kvm_phys_timer_read() - val); 1611 return 0; 1612 case SYS_CNTPCT_EL0: 1613 if (!test_bit(KVM_ARCH_FLAG_VM_COUNTER_OFFSET, &vcpu->kvm->arch.flags)) 1614 timer_set_offset(vcpu_ptimer(vcpu), kvm_phys_timer_read() - val); 1615 return 0; 1616 } 1617 1618 __vcpu_assign_sys_reg(vcpu, rd->reg, val); 1619 return 0; 1620 } 1621 1622 static int arch_timer_get_user(struct kvm_vcpu *vcpu, 1623 const struct sys_reg_desc *rd, 1624 u64 *val) 1625 { 1626 switch (reg_to_encoding(rd)) { 1627 case SYS_CNTVCT_EL0: 1628 *val = kvm_phys_timer_read() - timer_get_offset(vcpu_vtimer(vcpu)); 1629 break; 1630 case SYS_CNTPCT_EL0: 1631 *val = kvm_phys_timer_read() - timer_get_offset(vcpu_ptimer(vcpu)); 1632 break; 1633 default: 1634 *val = __vcpu_sys_reg(vcpu, rd->reg); 1635 } 1636 1637 return 0; 1638 } 1639 1640 static s64 kvm_arm64_ftr_safe_value(u32 id, const struct arm64_ftr_bits *ftrp, 1641 s64 new, s64 cur) 1642 { 1643 struct arm64_ftr_bits kvm_ftr = *ftrp; 1644 1645 /* Some features have different safe value type in KVM than host features */ 1646 switch (id) { 1647 case SYS_ID_AA64DFR0_EL1: 1648 switch (kvm_ftr.shift) { 1649 case ID_AA64DFR0_EL1_PMUVer_SHIFT: 1650 kvm_ftr.type = FTR_LOWER_SAFE; 1651 break; 1652 case ID_AA64DFR0_EL1_DebugVer_SHIFT: 1653 kvm_ftr.type = FTR_LOWER_SAFE; 1654 break; 1655 } 1656 break; 1657 case SYS_ID_DFR0_EL1: 1658 if (kvm_ftr.shift == ID_DFR0_EL1_PerfMon_SHIFT) 1659 kvm_ftr.type = FTR_LOWER_SAFE; 1660 break; 1661 } 1662 1663 return arm64_ftr_safe_value(&kvm_ftr, new, cur); 1664 } 1665 1666 /* 1667 * arm64_check_features() - Check if a feature register value constitutes 1668 * a subset of features indicated by the idreg's KVM sanitised limit. 1669 * 1670 * This function will check if each feature field of @val is the "safe" value 1671 * against idreg's KVM sanitised limit return from reset() callback. 1672 * If a field value in @val is the same as the one in limit, it is always 1673 * considered the safe value regardless For register fields that are not in 1674 * writable, only the value in limit is considered the safe value. 1675 * 1676 * Return: 0 if all the fields are safe. Otherwise, return negative errno. 1677 */ 1678 static int arm64_check_features(struct kvm_vcpu *vcpu, 1679 const struct sys_reg_desc *rd, 1680 u64 val) 1681 { 1682 const struct arm64_ftr_reg *ftr_reg; 1683 const struct arm64_ftr_bits *ftrp = NULL; 1684 u32 id = reg_to_encoding(rd); 1685 u64 writable_mask = rd->val; 1686 u64 limit = rd->reset(vcpu, rd); 1687 u64 mask = 0; 1688 1689 /* 1690 * Hidden and unallocated ID registers may not have a corresponding 1691 * struct arm64_ftr_reg. Of course, if the register is RAZ we know the 1692 * only safe value is 0. 1693 */ 1694 if (sysreg_visible_as_raz(vcpu, rd)) 1695 return val ? -E2BIG : 0; 1696 1697 ftr_reg = get_arm64_ftr_reg(id); 1698 if (!ftr_reg) 1699 return -EINVAL; 1700 1701 ftrp = ftr_reg->ftr_bits; 1702 1703 for (; ftrp && ftrp->width; ftrp++) { 1704 s64 f_val, f_lim, safe_val; 1705 u64 ftr_mask; 1706 1707 ftr_mask = arm64_ftr_mask(ftrp); 1708 if ((ftr_mask & writable_mask) != ftr_mask) 1709 continue; 1710 1711 f_val = arm64_ftr_value(ftrp, val); 1712 f_lim = arm64_ftr_value(ftrp, limit); 1713 mask |= ftr_mask; 1714 1715 if (f_val == f_lim) 1716 safe_val = f_val; 1717 else 1718 safe_val = kvm_arm64_ftr_safe_value(id, ftrp, f_val, f_lim); 1719 1720 if (safe_val != f_val) 1721 return -E2BIG; 1722 } 1723 1724 /* For fields that are not writable, values in limit are the safe values. */ 1725 if ((val & ~mask) != (limit & ~mask)) 1726 return -E2BIG; 1727 1728 return 0; 1729 } 1730 1731 static u8 pmuver_to_perfmon(u8 pmuver) 1732 { 1733 switch (pmuver) { 1734 case ID_AA64DFR0_EL1_PMUVer_IMP: 1735 return ID_DFR0_EL1_PerfMon_PMUv3; 1736 case ID_AA64DFR0_EL1_PMUVer_IMP_DEF: 1737 return ID_DFR0_EL1_PerfMon_IMPDEF; 1738 default: 1739 /* Anything ARMv8.1+ and NI have the same value. For now. */ 1740 return pmuver; 1741 } 1742 } 1743 1744 static u64 sanitise_id_aa64pfr0_el1(const struct kvm_vcpu *vcpu, u64 val); 1745 static u64 sanitise_id_aa64pfr1_el1(const struct kvm_vcpu *vcpu, u64 val); 1746 static u64 sanitise_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, u64 val); 1747 1748 /* Read a sanitised cpufeature ID register by sys_reg_desc */ 1749 static u64 __kvm_read_sanitised_id_reg(const struct kvm_vcpu *vcpu, 1750 const struct sys_reg_desc *r) 1751 { 1752 u32 id = reg_to_encoding(r); 1753 u64 val; 1754 1755 if (sysreg_visible_as_raz(vcpu, r)) 1756 return 0; 1757 1758 val = read_sanitised_ftr_reg(id); 1759 1760 switch (id) { 1761 case SYS_ID_AA64DFR0_EL1: 1762 val = sanitise_id_aa64dfr0_el1(vcpu, val); 1763 break; 1764 case SYS_ID_AA64PFR0_EL1: 1765 val = sanitise_id_aa64pfr0_el1(vcpu, val); 1766 break; 1767 case SYS_ID_AA64PFR1_EL1: 1768 val = sanitise_id_aa64pfr1_el1(vcpu, val); 1769 break; 1770 case SYS_ID_AA64PFR2_EL1: 1771 val &= ID_AA64PFR2_EL1_FPMR | 1772 (kvm_has_mte(vcpu->kvm) ? 1773 ID_AA64PFR2_EL1_MTEFAR | ID_AA64PFR2_EL1_MTESTOREONLY : 1774 0); 1775 break; 1776 case SYS_ID_AA64ISAR1_EL1: 1777 if (!vcpu_has_ptrauth(vcpu)) 1778 val &= ~(ID_AA64ISAR1_EL1_APA | 1779 ID_AA64ISAR1_EL1_API | 1780 ID_AA64ISAR1_EL1_GPA | 1781 ID_AA64ISAR1_EL1_GPI); 1782 break; 1783 case SYS_ID_AA64ISAR2_EL1: 1784 if (!vcpu_has_ptrauth(vcpu)) 1785 val &= ~(ID_AA64ISAR2_EL1_APA3 | 1786 ID_AA64ISAR2_EL1_GPA3); 1787 if (!cpus_have_final_cap(ARM64_HAS_WFXT) || 1788 has_broken_cntvoff()) 1789 val &= ~ID_AA64ISAR2_EL1_WFxT; 1790 break; 1791 case SYS_ID_AA64ISAR3_EL1: 1792 val &= ID_AA64ISAR3_EL1_FPRCVT | ID_AA64ISAR3_EL1_LSFE | 1793 ID_AA64ISAR3_EL1_FAMINMAX; 1794 break; 1795 case SYS_ID_AA64MMFR2_EL1: 1796 val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK; 1797 val &= ~ID_AA64MMFR2_EL1_NV; 1798 break; 1799 case SYS_ID_AA64MMFR3_EL1: 1800 val &= ID_AA64MMFR3_EL1_TCRX | 1801 ID_AA64MMFR3_EL1_SCTLRX | 1802 ID_AA64MMFR3_EL1_S1POE | 1803 ID_AA64MMFR3_EL1_S1PIE; 1804 break; 1805 case SYS_ID_MMFR4_EL1: 1806 val &= ~ID_MMFR4_EL1_CCIDX; 1807 break; 1808 } 1809 1810 if (vcpu_has_nv(vcpu)) 1811 val = limit_nv_id_reg(vcpu->kvm, id, val); 1812 1813 return val; 1814 } 1815 1816 static u64 kvm_read_sanitised_id_reg(struct kvm_vcpu *vcpu, 1817 const struct sys_reg_desc *r) 1818 { 1819 return __kvm_read_sanitised_id_reg(vcpu, r); 1820 } 1821 1822 static u64 read_id_reg(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 1823 { 1824 return kvm_read_vm_id_reg(vcpu->kvm, reg_to_encoding(r)); 1825 } 1826 1827 static bool is_feature_id_reg(u32 encoding) 1828 { 1829 return (sys_reg_Op0(encoding) == 3 && 1830 (sys_reg_Op1(encoding) < 2 || sys_reg_Op1(encoding) == 3) && 1831 sys_reg_CRn(encoding) == 0 && 1832 sys_reg_CRm(encoding) <= 7); 1833 } 1834 1835 /* 1836 * Return true if the register's (Op0, Op1, CRn, CRm, Op2) is 1837 * (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8, which is the range of ID 1838 * registers KVM maintains on a per-VM basis. 1839 * 1840 * Additionally, the implementation ID registers and CTR_EL0 are handled as 1841 * per-VM registers. 1842 */ 1843 static inline bool is_vm_ftr_id_reg(u32 id) 1844 { 1845 switch (id) { 1846 case SYS_CTR_EL0: 1847 case SYS_MIDR_EL1: 1848 case SYS_REVIDR_EL1: 1849 case SYS_AIDR_EL1: 1850 return true; 1851 default: 1852 return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 && 1853 sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 && 1854 sys_reg_CRm(id) < 8); 1855 1856 } 1857 } 1858 1859 static inline bool is_vcpu_ftr_id_reg(u32 id) 1860 { 1861 return is_feature_id_reg(id) && !is_vm_ftr_id_reg(id); 1862 } 1863 1864 static inline bool is_aa32_id_reg(u32 id) 1865 { 1866 return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 && 1867 sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 && 1868 sys_reg_CRm(id) <= 3); 1869 } 1870 1871 static unsigned int id_visibility(const struct kvm_vcpu *vcpu, 1872 const struct sys_reg_desc *r) 1873 { 1874 u32 id = reg_to_encoding(r); 1875 1876 switch (id) { 1877 case SYS_ID_AA64ZFR0_EL1: 1878 if (!vcpu_has_sve(vcpu)) 1879 return REG_RAZ; 1880 break; 1881 } 1882 1883 return 0; 1884 } 1885 1886 static unsigned int aa32_id_visibility(const struct kvm_vcpu *vcpu, 1887 const struct sys_reg_desc *r) 1888 { 1889 /* 1890 * AArch32 ID registers are UNKNOWN if AArch32 isn't implemented at any 1891 * EL. Promote to RAZ/WI in order to guarantee consistency between 1892 * systems. 1893 */ 1894 if (!kvm_supports_32bit_el0()) 1895 return REG_RAZ | REG_USER_WI; 1896 1897 return id_visibility(vcpu, r); 1898 } 1899 1900 static unsigned int raz_visibility(const struct kvm_vcpu *vcpu, 1901 const struct sys_reg_desc *r) 1902 { 1903 return REG_RAZ; 1904 } 1905 1906 /* cpufeature ID register access trap handlers */ 1907 1908 static bool access_id_reg(struct kvm_vcpu *vcpu, 1909 struct sys_reg_params *p, 1910 const struct sys_reg_desc *r) 1911 { 1912 if (p->is_write) 1913 return write_to_read_only(vcpu, p, r); 1914 1915 p->regval = read_id_reg(vcpu, r); 1916 1917 return true; 1918 } 1919 1920 /* Visibility overrides for SVE-specific control registers */ 1921 static unsigned int sve_visibility(const struct kvm_vcpu *vcpu, 1922 const struct sys_reg_desc *rd) 1923 { 1924 if (vcpu_has_sve(vcpu)) 1925 return 0; 1926 1927 return REG_HIDDEN; 1928 } 1929 1930 static unsigned int sme_visibility(const struct kvm_vcpu *vcpu, 1931 const struct sys_reg_desc *rd) 1932 { 1933 if (kvm_has_feat(vcpu->kvm, ID_AA64PFR1_EL1, SME, IMP)) 1934 return 0; 1935 1936 return REG_HIDDEN; 1937 } 1938 1939 static unsigned int fp8_visibility(const struct kvm_vcpu *vcpu, 1940 const struct sys_reg_desc *rd) 1941 { 1942 if (kvm_has_fpmr(vcpu->kvm)) 1943 return 0; 1944 1945 return REG_HIDDEN; 1946 } 1947 1948 static u64 sanitise_id_aa64pfr0_el1(const struct kvm_vcpu *vcpu, u64 val) 1949 { 1950 if (!vcpu_has_sve(vcpu)) 1951 val &= ~ID_AA64PFR0_EL1_SVE_MASK; 1952 1953 /* 1954 * The default is to expose CSV2 == 1 if the HW isn't affected. 1955 * Although this is a per-CPU feature, we make it global because 1956 * asymmetric systems are just a nuisance. 1957 * 1958 * Userspace can override this as long as it doesn't promise 1959 * the impossible. 1960 */ 1961 if (arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED) { 1962 val &= ~ID_AA64PFR0_EL1_CSV2_MASK; 1963 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV2, IMP); 1964 } 1965 if (arm64_get_meltdown_state() == SPECTRE_UNAFFECTED) { 1966 val &= ~ID_AA64PFR0_EL1_CSV3_MASK; 1967 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV3, IMP); 1968 } 1969 1970 if (vgic_is_v3(vcpu->kvm)) { 1971 val &= ~ID_AA64PFR0_EL1_GIC_MASK; 1972 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, GIC, IMP); 1973 } 1974 1975 val &= ~ID_AA64PFR0_EL1_AMU_MASK; 1976 1977 /* 1978 * MPAM is disabled by default as KVM also needs a set of PARTID to 1979 * program the MPAMVPMx_EL2 PARTID remapping registers with. But some 1980 * older kernels let the guest see the ID bit. 1981 */ 1982 val &= ~ID_AA64PFR0_EL1_MPAM_MASK; 1983 1984 return val; 1985 } 1986 1987 static u64 sanitise_id_aa64pfr1_el1(const struct kvm_vcpu *vcpu, u64 val) 1988 { 1989 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1990 1991 if (!kvm_has_mte(vcpu->kvm)) { 1992 val &= ~ID_AA64PFR1_EL1_MTE; 1993 val &= ~ID_AA64PFR1_EL1_MTE_frac; 1994 } 1995 1996 if (!(cpus_have_final_cap(ARM64_HAS_RASV1P1_EXTN) && 1997 SYS_FIELD_GET(ID_AA64PFR0_EL1, RAS, pfr0) == ID_AA64PFR0_EL1_RAS_IMP)) 1998 val &= ~ID_AA64PFR1_EL1_RAS_frac; 1999 2000 val &= ~ID_AA64PFR1_EL1_SME; 2001 val &= ~ID_AA64PFR1_EL1_RNDR_trap; 2002 val &= ~ID_AA64PFR1_EL1_NMI; 2003 val &= ~ID_AA64PFR1_EL1_GCS; 2004 val &= ~ID_AA64PFR1_EL1_THE; 2005 val &= ~ID_AA64PFR1_EL1_MTEX; 2006 val &= ~ID_AA64PFR1_EL1_PFAR; 2007 val &= ~ID_AA64PFR1_EL1_MPAM_frac; 2008 2009 return val; 2010 } 2011 2012 static u64 sanitise_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, u64 val) 2013 { 2014 val = ID_REG_LIMIT_FIELD_ENUM(val, ID_AA64DFR0_EL1, DebugVer, V8P8); 2015 2016 /* 2017 * Only initialize the PMU version if the vCPU was configured with one. 2018 */ 2019 val &= ~ID_AA64DFR0_EL1_PMUVer_MASK; 2020 if (kvm_vcpu_has_pmu(vcpu)) 2021 val |= SYS_FIELD_PREP(ID_AA64DFR0_EL1, PMUVer, 2022 kvm_arm_pmu_get_pmuver_limit()); 2023 2024 /* Hide SPE from guests */ 2025 val &= ~ID_AA64DFR0_EL1_PMSVer_MASK; 2026 2027 /* Hide BRBE from guests */ 2028 val &= ~ID_AA64DFR0_EL1_BRBE_MASK; 2029 2030 return val; 2031 } 2032 2033 /* 2034 * Older versions of KVM erroneously claim support for FEAT_DoubleLock with 2035 * NV-enabled VMs on unsupporting hardware. Silently ignore the incorrect 2036 * value if it is consistent with the bug. 2037 */ 2038 static bool ignore_feat_doublelock(struct kvm_vcpu *vcpu, u64 val) 2039 { 2040 u8 host, user; 2041 2042 if (!vcpu_has_nv(vcpu)) 2043 return false; 2044 2045 host = SYS_FIELD_GET(ID_AA64DFR0_EL1, DoubleLock, 2046 read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1)); 2047 user = SYS_FIELD_GET(ID_AA64DFR0_EL1, DoubleLock, val); 2048 2049 return host == ID_AA64DFR0_EL1_DoubleLock_NI && 2050 user == ID_AA64DFR0_EL1_DoubleLock_IMP; 2051 } 2052 2053 static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, 2054 const struct sys_reg_desc *rd, 2055 u64 val) 2056 { 2057 u8 debugver = SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, val); 2058 u8 pmuver = SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, val); 2059 2060 /* 2061 * Prior to commit 3d0dba5764b9 ("KVM: arm64: PMU: Move the 2062 * ID_AA64DFR0_EL1.PMUver limit to VM creation"), KVM erroneously 2063 * exposed an IMP_DEF PMU to userspace and the guest on systems w/ 2064 * non-architectural PMUs. Of course, PMUv3 is the only game in town for 2065 * PMU virtualization, so the IMP_DEF value was rather user-hostile. 2066 * 2067 * At minimum, we're on the hook to allow values that were given to 2068 * userspace by KVM. Cover our tracks here and replace the IMP_DEF value 2069 * with a more sensible NI. The value of an ID register changing under 2070 * the nose of the guest is unfortunate, but is certainly no more 2071 * surprising than an ill-guided PMU driver poking at impdef system 2072 * registers that end in an UNDEF... 2073 */ 2074 if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF) 2075 val &= ~ID_AA64DFR0_EL1_PMUVer_MASK; 2076 2077 /* 2078 * ID_AA64DFR0_EL1.DebugVer is one of those awkward fields with a 2079 * nonzero minimum safe value. 2080 */ 2081 if (debugver < ID_AA64DFR0_EL1_DebugVer_IMP) 2082 return -EINVAL; 2083 2084 if (ignore_feat_doublelock(vcpu, val)) { 2085 val &= ~ID_AA64DFR0_EL1_DoubleLock; 2086 val |= SYS_FIELD_PREP_ENUM(ID_AA64DFR0_EL1, DoubleLock, NI); 2087 } 2088 2089 return set_id_reg(vcpu, rd, val); 2090 } 2091 2092 static u64 read_sanitised_id_dfr0_el1(struct kvm_vcpu *vcpu, 2093 const struct sys_reg_desc *rd) 2094 { 2095 u8 perfmon; 2096 u64 val = read_sanitised_ftr_reg(SYS_ID_DFR0_EL1); 2097 2098 val &= ~ID_DFR0_EL1_PerfMon_MASK; 2099 if (kvm_vcpu_has_pmu(vcpu)) { 2100 perfmon = pmuver_to_perfmon(kvm_arm_pmu_get_pmuver_limit()); 2101 val |= SYS_FIELD_PREP(ID_DFR0_EL1, PerfMon, perfmon); 2102 } 2103 2104 val = ID_REG_LIMIT_FIELD_ENUM(val, ID_DFR0_EL1, CopDbg, Debugv8p8); 2105 2106 return val; 2107 } 2108 2109 static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, 2110 const struct sys_reg_desc *rd, 2111 u64 val) 2112 { 2113 u8 perfmon = SYS_FIELD_GET(ID_DFR0_EL1, PerfMon, val); 2114 u8 copdbg = SYS_FIELD_GET(ID_DFR0_EL1, CopDbg, val); 2115 2116 if (perfmon == ID_DFR0_EL1_PerfMon_IMPDEF) { 2117 val &= ~ID_DFR0_EL1_PerfMon_MASK; 2118 perfmon = 0; 2119 } 2120 2121 /* 2122 * Allow DFR0_EL1.PerfMon to be set from userspace as long as 2123 * it doesn't promise more than what the HW gives us on the 2124 * AArch64 side (as everything is emulated with that), and 2125 * that this is a PMUv3. 2126 */ 2127 if (perfmon != 0 && perfmon < ID_DFR0_EL1_PerfMon_PMUv3) 2128 return -EINVAL; 2129 2130 if (copdbg < ID_DFR0_EL1_CopDbg_Armv8) 2131 return -EINVAL; 2132 2133 return set_id_reg(vcpu, rd, val); 2134 } 2135 2136 static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, 2137 const struct sys_reg_desc *rd, u64 user_val) 2138 { 2139 u64 hw_val = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 2140 u64 mpam_mask = ID_AA64PFR0_EL1_MPAM_MASK; 2141 2142 /* 2143 * Commit 011e5f5bf529f ("arm64/cpufeature: Add remaining feature bits 2144 * in ID_AA64PFR0 register") exposed the MPAM field of AA64PFR0_EL1 to 2145 * guests, but didn't add trap handling. KVM doesn't support MPAM and 2146 * always returns an UNDEF for these registers. The guest must see 0 2147 * for this field. 2148 * 2149 * But KVM must also accept values from user-space that were provided 2150 * by KVM. On CPUs that support MPAM, permit user-space to write 2151 * the sanitizied value to ID_AA64PFR0_EL1.MPAM, but ignore this field. 2152 */ 2153 if ((hw_val & mpam_mask) == (user_val & mpam_mask)) 2154 user_val &= ~ID_AA64PFR0_EL1_MPAM_MASK; 2155 2156 /* Fail the guest's request to disable the AA64 ISA at EL{0,1,2} */ 2157 if (!FIELD_GET(ID_AA64PFR0_EL1_EL0, user_val) || 2158 !FIELD_GET(ID_AA64PFR0_EL1_EL1, user_val) || 2159 (vcpu_has_nv(vcpu) && !FIELD_GET(ID_AA64PFR0_EL1_EL2, user_val))) 2160 return -EINVAL; 2161 2162 /* 2163 * If we are running on a GICv5 host and support FEAT_GCIE_LEGACY, then 2164 * we support GICv3. Fail attempts to do anything but set that to IMP. 2165 */ 2166 if (vgic_is_v3_compat(vcpu->kvm) && 2167 FIELD_GET(ID_AA64PFR0_EL1_GIC_MASK, user_val) != ID_AA64PFR0_EL1_GIC_IMP) 2168 return -EINVAL; 2169 2170 return set_id_reg(vcpu, rd, user_val); 2171 } 2172 2173 static int set_id_aa64pfr1_el1(struct kvm_vcpu *vcpu, 2174 const struct sys_reg_desc *rd, u64 user_val) 2175 { 2176 u64 hw_val = read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1); 2177 u64 mpam_mask = ID_AA64PFR1_EL1_MPAM_frac_MASK; 2178 u8 mte = SYS_FIELD_GET(ID_AA64PFR1_EL1, MTE, hw_val); 2179 u8 user_mte_frac = SYS_FIELD_GET(ID_AA64PFR1_EL1, MTE_frac, user_val); 2180 u8 hw_mte_frac = SYS_FIELD_GET(ID_AA64PFR1_EL1, MTE_frac, hw_val); 2181 2182 /* See set_id_aa64pfr0_el1 for comment about MPAM */ 2183 if ((hw_val & mpam_mask) == (user_val & mpam_mask)) 2184 user_val &= ~ID_AA64PFR1_EL1_MPAM_frac_MASK; 2185 2186 /* 2187 * Previously MTE_frac was hidden from guest. However, if the 2188 * hardware supports MTE2 but not MTE_ASYM_FAULT then a value 2189 * of 0 for this field indicates that the hardware supports 2190 * MTE_ASYNC. Whereas, 0xf indicates MTE_ASYNC is not supported. 2191 * 2192 * As KVM must accept values from KVM provided by user-space, 2193 * when ID_AA64PFR1_EL1.MTE is 2 allow user-space to set 2194 * ID_AA64PFR1_EL1.MTE_frac to 0. However, ignore it to avoid 2195 * incorrectly claiming hardware support for MTE_ASYNC in the 2196 * guest. 2197 */ 2198 2199 if (mte == ID_AA64PFR1_EL1_MTE_MTE2 && 2200 hw_mte_frac == ID_AA64PFR1_EL1_MTE_frac_NI && 2201 user_mte_frac == ID_AA64PFR1_EL1_MTE_frac_ASYNC) { 2202 user_val &= ~ID_AA64PFR1_EL1_MTE_frac_MASK; 2203 user_val |= hw_val & ID_AA64PFR1_EL1_MTE_frac_MASK; 2204 } 2205 2206 return set_id_reg(vcpu, rd, user_val); 2207 } 2208 2209 /* 2210 * Allow userspace to de-feature a stage-2 translation granule but prevent it 2211 * from claiming the impossible. 2212 */ 2213 #define tgran2_val_allowed(tg, safe, user) \ 2214 ({ \ 2215 u8 __s = SYS_FIELD_GET(ID_AA64MMFR0_EL1, tg, safe); \ 2216 u8 __u = SYS_FIELD_GET(ID_AA64MMFR0_EL1, tg, user); \ 2217 \ 2218 __s == __u || __u == ID_AA64MMFR0_EL1_##tg##_NI; \ 2219 }) 2220 2221 static int set_id_aa64mmfr0_el1(struct kvm_vcpu *vcpu, 2222 const struct sys_reg_desc *rd, u64 user_val) 2223 { 2224 u64 sanitized_val = kvm_read_sanitised_id_reg(vcpu, rd); 2225 2226 if (!vcpu_has_nv(vcpu)) 2227 return set_id_reg(vcpu, rd, user_val); 2228 2229 if (!tgran2_val_allowed(TGRAN4_2, sanitized_val, user_val) || 2230 !tgran2_val_allowed(TGRAN16_2, sanitized_val, user_val) || 2231 !tgran2_val_allowed(TGRAN64_2, sanitized_val, user_val)) 2232 return -EINVAL; 2233 2234 return set_id_reg(vcpu, rd, user_val); 2235 } 2236 2237 static int set_id_aa64mmfr2_el1(struct kvm_vcpu *vcpu, 2238 const struct sys_reg_desc *rd, u64 user_val) 2239 { 2240 u64 hw_val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR2_EL1); 2241 u64 nv_mask = ID_AA64MMFR2_EL1_NV_MASK; 2242 2243 /* 2244 * We made the mistake to expose the now deprecated NV field, 2245 * so allow userspace to write it, but silently ignore it. 2246 */ 2247 if ((hw_val & nv_mask) == (user_val & nv_mask)) 2248 user_val &= ~nv_mask; 2249 2250 return set_id_reg(vcpu, rd, user_val); 2251 } 2252 2253 static int set_ctr_el0(struct kvm_vcpu *vcpu, 2254 const struct sys_reg_desc *rd, u64 user_val) 2255 { 2256 u8 user_L1Ip = SYS_FIELD_GET(CTR_EL0, L1Ip, user_val); 2257 2258 /* 2259 * Both AIVIVT (0b01) and VPIPT (0b00) are documented as reserved. 2260 * Hence only allow to set VIPT(0b10) or PIPT(0b11) for L1Ip based 2261 * on what hardware reports. 2262 * 2263 * Using a VIPT software model on PIPT will lead to over invalidation, 2264 * but still correct. Hence, we can allow downgrading PIPT to VIPT, 2265 * but not the other way around. This is handled via arm64_ftr_safe_value() 2266 * as CTR_EL0 ftr_bits has L1Ip field with type FTR_EXACT and safe value 2267 * set as VIPT. 2268 */ 2269 switch (user_L1Ip) { 2270 case CTR_EL0_L1Ip_RESERVED_VPIPT: 2271 case CTR_EL0_L1Ip_RESERVED_AIVIVT: 2272 return -EINVAL; 2273 case CTR_EL0_L1Ip_VIPT: 2274 case CTR_EL0_L1Ip_PIPT: 2275 return set_id_reg(vcpu, rd, user_val); 2276 default: 2277 return -ENOENT; 2278 } 2279 } 2280 2281 /* 2282 * cpufeature ID register user accessors 2283 * 2284 * For now, these registers are immutable for userspace, so no values 2285 * are stored, and for set_id_reg() we don't allow the effective value 2286 * to be changed. 2287 */ 2288 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 2289 u64 *val) 2290 { 2291 /* 2292 * Avoid locking if the VM has already started, as the ID registers are 2293 * guaranteed to be invariant at that point. 2294 */ 2295 if (kvm_vm_has_ran_once(vcpu->kvm)) { 2296 *val = read_id_reg(vcpu, rd); 2297 return 0; 2298 } 2299 2300 mutex_lock(&vcpu->kvm->arch.config_lock); 2301 *val = read_id_reg(vcpu, rd); 2302 mutex_unlock(&vcpu->kvm->arch.config_lock); 2303 2304 return 0; 2305 } 2306 2307 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 2308 u64 val) 2309 { 2310 u32 id = reg_to_encoding(rd); 2311 int ret; 2312 2313 mutex_lock(&vcpu->kvm->arch.config_lock); 2314 2315 /* 2316 * Once the VM has started the ID registers are immutable. Reject any 2317 * write that does not match the final register value. 2318 */ 2319 if (kvm_vm_has_ran_once(vcpu->kvm)) { 2320 if (val != read_id_reg(vcpu, rd)) 2321 ret = -EBUSY; 2322 else 2323 ret = 0; 2324 2325 mutex_unlock(&vcpu->kvm->arch.config_lock); 2326 return ret; 2327 } 2328 2329 ret = arm64_check_features(vcpu, rd, val); 2330 if (!ret) 2331 kvm_set_vm_id_reg(vcpu->kvm, id, val); 2332 2333 mutex_unlock(&vcpu->kvm->arch.config_lock); 2334 2335 /* 2336 * arm64_check_features() returns -E2BIG to indicate the register's 2337 * feature set is a superset of the maximally-allowed register value. 2338 * While it would be nice to precisely describe this to userspace, the 2339 * existing UAPI for KVM_SET_ONE_REG has it that invalid register 2340 * writes return -EINVAL. 2341 */ 2342 if (ret == -E2BIG) 2343 ret = -EINVAL; 2344 return ret; 2345 } 2346 2347 void kvm_set_vm_id_reg(struct kvm *kvm, u32 reg, u64 val) 2348 { 2349 u64 *p = __vm_id_reg(&kvm->arch, reg); 2350 2351 lockdep_assert_held(&kvm->arch.config_lock); 2352 2353 if (KVM_BUG_ON(kvm_vm_has_ran_once(kvm) || !p, kvm)) 2354 return; 2355 2356 *p = val; 2357 } 2358 2359 static int get_raz_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 2360 u64 *val) 2361 { 2362 *val = 0; 2363 return 0; 2364 } 2365 2366 static int set_wi_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 2367 u64 val) 2368 { 2369 return 0; 2370 } 2371 2372 static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2373 const struct sys_reg_desc *r) 2374 { 2375 if (p->is_write) 2376 return write_to_read_only(vcpu, p, r); 2377 2378 p->regval = kvm_read_vm_id_reg(vcpu->kvm, SYS_CTR_EL0); 2379 return true; 2380 } 2381 2382 static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2383 const struct sys_reg_desc *r) 2384 { 2385 if (p->is_write) 2386 return write_to_read_only(vcpu, p, r); 2387 2388 p->regval = __vcpu_sys_reg(vcpu, r->reg); 2389 return true; 2390 } 2391 2392 /* 2393 * Fabricate a CLIDR_EL1 value instead of using the real value, which can vary 2394 * by the physical CPU which the vcpu currently resides in. 2395 */ 2396 static u64 reset_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 2397 { 2398 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0); 2399 u64 clidr; 2400 u8 loc; 2401 2402 if ((ctr_el0 & CTR_EL0_IDC)) { 2403 /* 2404 * Data cache clean to the PoU is not required so LoUU and LoUIS 2405 * will not be set and a unified cache, which will be marked as 2406 * LoC, will be added. 2407 * 2408 * If not DIC, let the unified cache L2 so that an instruction 2409 * cache can be added as L1 later. 2410 */ 2411 loc = (ctr_el0 & CTR_EL0_DIC) ? 1 : 2; 2412 clidr = CACHE_TYPE_UNIFIED << CLIDR_CTYPE_SHIFT(loc); 2413 } else { 2414 /* 2415 * Data cache clean to the PoU is required so let L1 have a data 2416 * cache and mark it as LoUU and LoUIS. As L1 has a data cache, 2417 * it can be marked as LoC too. 2418 */ 2419 loc = 1; 2420 clidr = 1 << CLIDR_LOUU_SHIFT; 2421 clidr |= 1 << CLIDR_LOUIS_SHIFT; 2422 clidr |= CACHE_TYPE_DATA << CLIDR_CTYPE_SHIFT(1); 2423 } 2424 2425 /* 2426 * Instruction cache invalidation to the PoU is required so let L1 have 2427 * an instruction cache. If L1 already has a data cache, it will be 2428 * CACHE_TYPE_SEPARATE. 2429 */ 2430 if (!(ctr_el0 & CTR_EL0_DIC)) 2431 clidr |= CACHE_TYPE_INST << CLIDR_CTYPE_SHIFT(1); 2432 2433 clidr |= loc << CLIDR_LOC_SHIFT; 2434 2435 /* 2436 * Add tag cache unified to data cache. Allocation tags and data are 2437 * unified in a cache line so that it looks valid even if there is only 2438 * one cache line. 2439 */ 2440 if (kvm_has_mte(vcpu->kvm)) 2441 clidr |= 2ULL << CLIDR_TTYPE_SHIFT(loc); 2442 2443 __vcpu_assign_sys_reg(vcpu, r->reg, clidr); 2444 2445 return __vcpu_sys_reg(vcpu, r->reg); 2446 } 2447 2448 static int set_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 2449 u64 val) 2450 { 2451 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0); 2452 u64 idc = !CLIDR_LOC(val) || (!CLIDR_LOUIS(val) && !CLIDR_LOUU(val)); 2453 2454 if ((val & CLIDR_EL1_RES0) || (!(ctr_el0 & CTR_EL0_IDC) && idc)) 2455 return -EINVAL; 2456 2457 __vcpu_assign_sys_reg(vcpu, rd->reg, val); 2458 2459 return 0; 2460 } 2461 2462 static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2463 const struct sys_reg_desc *r) 2464 { 2465 int reg = r->reg; 2466 2467 if (p->is_write) 2468 vcpu_write_sys_reg(vcpu, p->regval, reg); 2469 else 2470 p->regval = vcpu_read_sys_reg(vcpu, reg); 2471 return true; 2472 } 2473 2474 static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2475 const struct sys_reg_desc *r) 2476 { 2477 u32 csselr; 2478 2479 if (p->is_write) 2480 return write_to_read_only(vcpu, p, r); 2481 2482 csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1); 2483 csselr &= CSSELR_EL1_Level | CSSELR_EL1_InD; 2484 if (csselr < CSSELR_MAX) 2485 p->regval = get_ccsidr(vcpu, csselr); 2486 2487 return true; 2488 } 2489 2490 static unsigned int mte_visibility(const struct kvm_vcpu *vcpu, 2491 const struct sys_reg_desc *rd) 2492 { 2493 if (kvm_has_mte(vcpu->kvm)) 2494 return 0; 2495 2496 return REG_HIDDEN; 2497 } 2498 2499 #define MTE_REG(name) { \ 2500 SYS_DESC(SYS_##name), \ 2501 .access = undef_access, \ 2502 .reset = reset_unknown, \ 2503 .reg = name, \ 2504 .visibility = mte_visibility, \ 2505 } 2506 2507 static unsigned int el2_visibility(const struct kvm_vcpu *vcpu, 2508 const struct sys_reg_desc *rd) 2509 { 2510 if (vcpu_has_nv(vcpu)) 2511 return 0; 2512 2513 return REG_HIDDEN; 2514 } 2515 2516 static bool bad_vncr_trap(struct kvm_vcpu *vcpu, 2517 struct sys_reg_params *p, 2518 const struct sys_reg_desc *r) 2519 { 2520 /* 2521 * We really shouldn't be here, and this is likely the result 2522 * of a misconfigured trap, as this register should target the 2523 * VNCR page, and nothing else. 2524 */ 2525 return bad_trap(vcpu, p, r, 2526 "trap of VNCR-backed register"); 2527 } 2528 2529 static bool bad_redir_trap(struct kvm_vcpu *vcpu, 2530 struct sys_reg_params *p, 2531 const struct sys_reg_desc *r) 2532 { 2533 /* 2534 * We really shouldn't be here, and this is likely the result 2535 * of a misconfigured trap, as this register should target the 2536 * corresponding EL1, and nothing else. 2537 */ 2538 return bad_trap(vcpu, p, r, 2539 "trap of EL2 register redirected to EL1"); 2540 } 2541 2542 #define SYS_REG_USER_FILTER(name, acc, rst, v, gu, su, filter) { \ 2543 SYS_DESC(SYS_##name), \ 2544 .access = acc, \ 2545 .reset = rst, \ 2546 .reg = name, \ 2547 .get_user = gu, \ 2548 .set_user = su, \ 2549 .visibility = filter, \ 2550 .val = v, \ 2551 } 2552 2553 #define EL2_REG_FILTERED(name, acc, rst, v, filter) \ 2554 SYS_REG_USER_FILTER(name, acc, rst, v, NULL, NULL, filter) 2555 2556 #define EL2_REG(name, acc, rst, v) \ 2557 EL2_REG_FILTERED(name, acc, rst, v, el2_visibility) 2558 2559 #define EL2_REG_VNCR(name, rst, v) EL2_REG(name, bad_vncr_trap, rst, v) 2560 #define EL2_REG_VNCR_FILT(name, vis) \ 2561 EL2_REG_FILTERED(name, bad_vncr_trap, reset_val, 0, vis) 2562 #define EL2_REG_VNCR_GICv3(name) \ 2563 EL2_REG_VNCR_FILT(name, hidden_visibility) 2564 #define EL2_REG_REDIR(name, rst, v) EL2_REG(name, bad_redir_trap, rst, v) 2565 2566 #define TIMER_REG(name, vis) \ 2567 SYS_REG_USER_FILTER(name, access_arch_timer, reset_val, 0, \ 2568 arch_timer_get_user, arch_timer_set_user, vis) 2569 2570 /* 2571 * Since reset() callback and field val are not used for idregs, they will be 2572 * used for specific purposes for idregs. 2573 * The reset() would return KVM sanitised register value. The value would be the 2574 * same as the host kernel sanitised value if there is no KVM sanitisation. 2575 * The val would be used as a mask indicating writable fields for the idreg. 2576 * Only bits with 1 are writable from userspace. This mask might not be 2577 * necessary in the future whenever all ID registers are enabled as writable 2578 * from userspace. 2579 */ 2580 2581 #define ID_DESC_DEFAULT_CALLBACKS \ 2582 .access = access_id_reg, \ 2583 .get_user = get_id_reg, \ 2584 .set_user = set_id_reg, \ 2585 .visibility = id_visibility, \ 2586 .reset = kvm_read_sanitised_id_reg 2587 2588 #define ID_DESC(name) \ 2589 SYS_DESC(SYS_##name), \ 2590 ID_DESC_DEFAULT_CALLBACKS 2591 2592 /* sys_reg_desc initialiser for known cpufeature ID registers */ 2593 #define ID_SANITISED(name) { \ 2594 ID_DESC(name), \ 2595 .val = 0, \ 2596 } 2597 2598 /* sys_reg_desc initialiser for known cpufeature ID registers */ 2599 #define AA32_ID_SANITISED(name) { \ 2600 ID_DESC(name), \ 2601 .visibility = aa32_id_visibility, \ 2602 .val = 0, \ 2603 } 2604 2605 /* sys_reg_desc initialiser for writable ID registers */ 2606 #define ID_WRITABLE(name, mask) { \ 2607 ID_DESC(name), \ 2608 .val = mask, \ 2609 } 2610 2611 /* sys_reg_desc initialiser for cpufeature ID registers that need filtering */ 2612 #define ID_FILTERED(sysreg, name, mask) { \ 2613 ID_DESC(sysreg), \ 2614 .set_user = set_##name, \ 2615 .val = (mask), \ 2616 } 2617 2618 /* 2619 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID 2620 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2 2621 * (1 <= crm < 8, 0 <= Op2 < 8). 2622 */ 2623 #define ID_UNALLOCATED(crm, op2) { \ 2624 .name = "S3_0_0_" #crm "_" #op2, \ 2625 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \ 2626 ID_DESC_DEFAULT_CALLBACKS, \ 2627 .visibility = raz_visibility, \ 2628 .val = 0, \ 2629 } 2630 2631 /* 2632 * sys_reg_desc initialiser for known ID registers that we hide from guests. 2633 * For now, these are exposed just like unallocated ID regs: they appear 2634 * RAZ for the guest. 2635 */ 2636 #define ID_HIDDEN(name) { \ 2637 ID_DESC(name), \ 2638 .visibility = raz_visibility, \ 2639 .val = 0, \ 2640 } 2641 2642 static bool access_sp_el1(struct kvm_vcpu *vcpu, 2643 struct sys_reg_params *p, 2644 const struct sys_reg_desc *r) 2645 { 2646 if (p->is_write) 2647 __vcpu_assign_sys_reg(vcpu, SP_EL1, p->regval); 2648 else 2649 p->regval = __vcpu_sys_reg(vcpu, SP_EL1); 2650 2651 return true; 2652 } 2653 2654 static bool access_elr(struct kvm_vcpu *vcpu, 2655 struct sys_reg_params *p, 2656 const struct sys_reg_desc *r) 2657 { 2658 if (p->is_write) 2659 vcpu_write_sys_reg(vcpu, p->regval, ELR_EL1); 2660 else 2661 p->regval = vcpu_read_sys_reg(vcpu, ELR_EL1); 2662 2663 return true; 2664 } 2665 2666 static bool access_spsr(struct kvm_vcpu *vcpu, 2667 struct sys_reg_params *p, 2668 const struct sys_reg_desc *r) 2669 { 2670 if (p->is_write) 2671 __vcpu_assign_sys_reg(vcpu, SPSR_EL1, p->regval); 2672 else 2673 p->regval = __vcpu_sys_reg(vcpu, SPSR_EL1); 2674 2675 return true; 2676 } 2677 2678 static bool access_cntkctl_el12(struct kvm_vcpu *vcpu, 2679 struct sys_reg_params *p, 2680 const struct sys_reg_desc *r) 2681 { 2682 if (p->is_write) 2683 __vcpu_assign_sys_reg(vcpu, CNTKCTL_EL1, p->regval); 2684 else 2685 p->regval = __vcpu_sys_reg(vcpu, CNTKCTL_EL1); 2686 2687 return true; 2688 } 2689 2690 static u64 reset_hcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 2691 { 2692 u64 val = r->val; 2693 2694 if (!cpus_have_final_cap(ARM64_HAS_HCR_NV1)) 2695 val |= HCR_E2H; 2696 2697 __vcpu_assign_sys_reg(vcpu, r->reg, val); 2698 2699 return __vcpu_sys_reg(vcpu, r->reg); 2700 } 2701 2702 static unsigned int __el2_visibility(const struct kvm_vcpu *vcpu, 2703 const struct sys_reg_desc *rd, 2704 unsigned int (*fn)(const struct kvm_vcpu *, 2705 const struct sys_reg_desc *)) 2706 { 2707 return el2_visibility(vcpu, rd) ?: fn(vcpu, rd); 2708 } 2709 2710 static unsigned int sve_el2_visibility(const struct kvm_vcpu *vcpu, 2711 const struct sys_reg_desc *rd) 2712 { 2713 return __el2_visibility(vcpu, rd, sve_visibility); 2714 } 2715 2716 static unsigned int vncr_el2_visibility(const struct kvm_vcpu *vcpu, 2717 const struct sys_reg_desc *rd) 2718 { 2719 if (el2_visibility(vcpu, rd) == 0 && 2720 kvm_has_feat(vcpu->kvm, ID_AA64MMFR4_EL1, NV_frac, NV2_ONLY)) 2721 return 0; 2722 2723 return REG_HIDDEN; 2724 } 2725 2726 static unsigned int sctlr2_visibility(const struct kvm_vcpu *vcpu, 2727 const struct sys_reg_desc *rd) 2728 { 2729 if (kvm_has_sctlr2(vcpu->kvm)) 2730 return 0; 2731 2732 return REG_HIDDEN; 2733 } 2734 2735 static unsigned int sctlr2_el2_visibility(const struct kvm_vcpu *vcpu, 2736 const struct sys_reg_desc *rd) 2737 { 2738 return __el2_visibility(vcpu, rd, sctlr2_visibility); 2739 } 2740 2741 static bool access_zcr_el2(struct kvm_vcpu *vcpu, 2742 struct sys_reg_params *p, 2743 const struct sys_reg_desc *r) 2744 { 2745 unsigned int vq; 2746 2747 if (guest_hyp_sve_traps_enabled(vcpu)) { 2748 kvm_inject_nested_sve_trap(vcpu); 2749 return false; 2750 } 2751 2752 if (!p->is_write) { 2753 p->regval = __vcpu_sys_reg(vcpu, ZCR_EL2); 2754 return true; 2755 } 2756 2757 vq = SYS_FIELD_GET(ZCR_ELx, LEN, p->regval) + 1; 2758 vq = min(vq, vcpu_sve_max_vq(vcpu)); 2759 __vcpu_assign_sys_reg(vcpu, ZCR_EL2, vq - 1); 2760 return true; 2761 } 2762 2763 static bool access_gic_vtr(struct kvm_vcpu *vcpu, 2764 struct sys_reg_params *p, 2765 const struct sys_reg_desc *r) 2766 { 2767 if (p->is_write) 2768 return write_to_read_only(vcpu, p, r); 2769 2770 p->regval = kvm_get_guest_vtr_el2(); 2771 2772 return true; 2773 } 2774 2775 static bool access_gic_misr(struct kvm_vcpu *vcpu, 2776 struct sys_reg_params *p, 2777 const struct sys_reg_desc *r) 2778 { 2779 if (p->is_write) 2780 return write_to_read_only(vcpu, p, r); 2781 2782 p->regval = vgic_v3_get_misr(vcpu); 2783 2784 return true; 2785 } 2786 2787 static bool access_gic_eisr(struct kvm_vcpu *vcpu, 2788 struct sys_reg_params *p, 2789 const struct sys_reg_desc *r) 2790 { 2791 if (p->is_write) 2792 return write_to_read_only(vcpu, p, r); 2793 2794 p->regval = vgic_v3_get_eisr(vcpu); 2795 2796 return true; 2797 } 2798 2799 static bool access_gic_elrsr(struct kvm_vcpu *vcpu, 2800 struct sys_reg_params *p, 2801 const struct sys_reg_desc *r) 2802 { 2803 if (p->is_write) 2804 return write_to_read_only(vcpu, p, r); 2805 2806 p->regval = vgic_v3_get_elrsr(vcpu); 2807 2808 return true; 2809 } 2810 2811 static unsigned int s1poe_visibility(const struct kvm_vcpu *vcpu, 2812 const struct sys_reg_desc *rd) 2813 { 2814 if (kvm_has_s1poe(vcpu->kvm)) 2815 return 0; 2816 2817 return REG_HIDDEN; 2818 } 2819 2820 static unsigned int s1poe_el2_visibility(const struct kvm_vcpu *vcpu, 2821 const struct sys_reg_desc *rd) 2822 { 2823 return __el2_visibility(vcpu, rd, s1poe_visibility); 2824 } 2825 2826 static unsigned int tcr2_visibility(const struct kvm_vcpu *vcpu, 2827 const struct sys_reg_desc *rd) 2828 { 2829 if (kvm_has_tcr2(vcpu->kvm)) 2830 return 0; 2831 2832 return REG_HIDDEN; 2833 } 2834 2835 static unsigned int tcr2_el2_visibility(const struct kvm_vcpu *vcpu, 2836 const struct sys_reg_desc *rd) 2837 { 2838 return __el2_visibility(vcpu, rd, tcr2_visibility); 2839 } 2840 2841 static unsigned int fgt2_visibility(const struct kvm_vcpu *vcpu, 2842 const struct sys_reg_desc *rd) 2843 { 2844 if (el2_visibility(vcpu, rd) == 0 && 2845 kvm_has_feat(vcpu->kvm, ID_AA64MMFR0_EL1, FGT, FGT2)) 2846 return 0; 2847 2848 return REG_HIDDEN; 2849 } 2850 2851 static unsigned int fgt_visibility(const struct kvm_vcpu *vcpu, 2852 const struct sys_reg_desc *rd) 2853 { 2854 if (el2_visibility(vcpu, rd) == 0 && 2855 kvm_has_feat(vcpu->kvm, ID_AA64MMFR0_EL1, FGT, IMP)) 2856 return 0; 2857 2858 return REG_HIDDEN; 2859 } 2860 2861 static unsigned int s1pie_visibility(const struct kvm_vcpu *vcpu, 2862 const struct sys_reg_desc *rd) 2863 { 2864 if (kvm_has_s1pie(vcpu->kvm)) 2865 return 0; 2866 2867 return REG_HIDDEN; 2868 } 2869 2870 static unsigned int s1pie_el2_visibility(const struct kvm_vcpu *vcpu, 2871 const struct sys_reg_desc *rd) 2872 { 2873 return __el2_visibility(vcpu, rd, s1pie_visibility); 2874 } 2875 2876 static unsigned int cnthv_visibility(const struct kvm_vcpu *vcpu, 2877 const struct sys_reg_desc *rd) 2878 { 2879 if (vcpu_has_nv(vcpu) && 2880 !vcpu_has_feature(vcpu, KVM_ARM_VCPU_HAS_EL2_E2H0)) 2881 return 0; 2882 2883 return REG_HIDDEN; 2884 } 2885 2886 static bool access_mdcr(struct kvm_vcpu *vcpu, 2887 struct sys_reg_params *p, 2888 const struct sys_reg_desc *r) 2889 { 2890 u64 hpmn, val, old = __vcpu_sys_reg(vcpu, MDCR_EL2); 2891 2892 if (!p->is_write) { 2893 p->regval = old; 2894 return true; 2895 } 2896 2897 val = p->regval; 2898 hpmn = FIELD_GET(MDCR_EL2_HPMN, val); 2899 2900 /* 2901 * If HPMN is out of bounds, limit it to what we actually 2902 * support. This matches the UNKNOWN definition of the field 2903 * in that case, and keeps the emulation simple. Sort of. 2904 */ 2905 if (hpmn > vcpu->kvm->arch.nr_pmu_counters) { 2906 hpmn = vcpu->kvm->arch.nr_pmu_counters; 2907 u64p_replace_bits(&val, hpmn, MDCR_EL2_HPMN); 2908 } 2909 2910 __vcpu_assign_sys_reg(vcpu, MDCR_EL2, val); 2911 2912 /* 2913 * Request a reload of the PMU to enable/disable the counters 2914 * affected by HPME. 2915 */ 2916 if ((old ^ val) & MDCR_EL2_HPME) 2917 kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu); 2918 2919 return true; 2920 } 2921 2922 static bool access_ras(struct kvm_vcpu *vcpu, 2923 struct sys_reg_params *p, 2924 const struct sys_reg_desc *r) 2925 { 2926 struct kvm *kvm = vcpu->kvm; 2927 2928 switch(reg_to_encoding(r)) { 2929 case SYS_ERXPFGCDN_EL1: 2930 case SYS_ERXPFGCTL_EL1: 2931 case SYS_ERXPFGF_EL1: 2932 case SYS_ERXMISC2_EL1: 2933 case SYS_ERXMISC3_EL1: 2934 if (!(kvm_has_feat(kvm, ID_AA64PFR0_EL1, RAS, V1P1) || 2935 (kvm_has_feat_enum(kvm, ID_AA64PFR0_EL1, RAS, IMP) && 2936 kvm_has_feat(kvm, ID_AA64PFR1_EL1, RAS_frac, RASv1p1)))) { 2937 kvm_inject_undefined(vcpu); 2938 return false; 2939 } 2940 break; 2941 default: 2942 if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, RAS, IMP)) { 2943 kvm_inject_undefined(vcpu); 2944 return false; 2945 } 2946 } 2947 2948 return trap_raz_wi(vcpu, p, r); 2949 } 2950 2951 /* 2952 * For historical (ahem ABI) reasons, KVM treated MIDR_EL1, REVIDR_EL1, and 2953 * AIDR_EL1 as "invariant" registers, meaning userspace cannot change them. 2954 * The values made visible to userspace were the register values of the boot 2955 * CPU. 2956 * 2957 * At the same time, reads from these registers at EL1 previously were not 2958 * trapped, allowing the guest to read the actual hardware value. On big-little 2959 * machines, this means the VM can see different values depending on where a 2960 * given vCPU got scheduled. 2961 * 2962 * These registers are now trapped as collateral damage from SME, and what 2963 * follows attempts to give a user / guest view consistent with the existing 2964 * ABI. 2965 */ 2966 static bool access_imp_id_reg(struct kvm_vcpu *vcpu, 2967 struct sys_reg_params *p, 2968 const struct sys_reg_desc *r) 2969 { 2970 if (p->is_write) 2971 return write_to_read_only(vcpu, p, r); 2972 2973 /* 2974 * Return the VM-scoped implementation ID register values if userspace 2975 * has made them writable. 2976 */ 2977 if (test_bit(KVM_ARCH_FLAG_WRITABLE_IMP_ID_REGS, &vcpu->kvm->arch.flags)) 2978 return access_id_reg(vcpu, p, r); 2979 2980 /* 2981 * Otherwise, fall back to the old behavior of returning the value of 2982 * the current CPU. 2983 */ 2984 switch (reg_to_encoding(r)) { 2985 case SYS_REVIDR_EL1: 2986 p->regval = read_sysreg(revidr_el1); 2987 break; 2988 case SYS_AIDR_EL1: 2989 p->regval = read_sysreg(aidr_el1); 2990 break; 2991 default: 2992 WARN_ON_ONCE(1); 2993 } 2994 2995 return true; 2996 } 2997 2998 static u64 __ro_after_init boot_cpu_midr_val; 2999 static u64 __ro_after_init boot_cpu_revidr_val; 3000 static u64 __ro_after_init boot_cpu_aidr_val; 3001 3002 static void init_imp_id_regs(void) 3003 { 3004 boot_cpu_midr_val = read_sysreg(midr_el1); 3005 boot_cpu_revidr_val = read_sysreg(revidr_el1); 3006 boot_cpu_aidr_val = read_sysreg(aidr_el1); 3007 } 3008 3009 static u64 reset_imp_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 3010 { 3011 switch (reg_to_encoding(r)) { 3012 case SYS_MIDR_EL1: 3013 return boot_cpu_midr_val; 3014 case SYS_REVIDR_EL1: 3015 return boot_cpu_revidr_val; 3016 case SYS_AIDR_EL1: 3017 return boot_cpu_aidr_val; 3018 default: 3019 KVM_BUG_ON(1, vcpu->kvm); 3020 return 0; 3021 } 3022 } 3023 3024 static int set_imp_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 3025 u64 val) 3026 { 3027 struct kvm *kvm = vcpu->kvm; 3028 u64 expected; 3029 3030 guard(mutex)(&kvm->arch.config_lock); 3031 3032 expected = read_id_reg(vcpu, r); 3033 if (expected == val) 3034 return 0; 3035 3036 if (!test_bit(KVM_ARCH_FLAG_WRITABLE_IMP_ID_REGS, &kvm->arch.flags)) 3037 return -EINVAL; 3038 3039 /* 3040 * Once the VM has started the ID registers are immutable. Reject the 3041 * write if userspace tries to change it. 3042 */ 3043 if (kvm_vm_has_ran_once(kvm)) 3044 return -EBUSY; 3045 3046 /* 3047 * Any value is allowed for the implementation ID registers so long as 3048 * it is within the writable mask. 3049 */ 3050 if ((val & r->val) != val) 3051 return -EINVAL; 3052 3053 kvm_set_vm_id_reg(kvm, reg_to_encoding(r), val); 3054 return 0; 3055 } 3056 3057 #define IMPLEMENTATION_ID(reg, mask) { \ 3058 SYS_DESC(SYS_##reg), \ 3059 .access = access_imp_id_reg, \ 3060 .get_user = get_id_reg, \ 3061 .set_user = set_imp_id_reg, \ 3062 .reset = reset_imp_id_reg, \ 3063 .val = mask, \ 3064 } 3065 3066 static u64 reset_mdcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 3067 { 3068 __vcpu_assign_sys_reg(vcpu, r->reg, vcpu->kvm->arch.nr_pmu_counters); 3069 return vcpu->kvm->arch.nr_pmu_counters; 3070 } 3071 3072 /* 3073 * Architected system registers. 3074 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2 3075 * 3076 * Debug handling: We do trap most, if not all debug related system 3077 * registers. The implementation is good enough to ensure that a guest 3078 * can use these with minimal performance degradation. The drawback is 3079 * that we don't implement any of the external debug architecture. 3080 * This should be revisited if we ever encounter a more demanding 3081 * guest... 3082 */ 3083 static const struct sys_reg_desc sys_reg_descs[] = { 3084 DBG_BCR_BVR_WCR_WVR_EL1(0), 3085 DBG_BCR_BVR_WCR_WVR_EL1(1), 3086 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 }, 3087 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 }, 3088 DBG_BCR_BVR_WCR_WVR_EL1(2), 3089 DBG_BCR_BVR_WCR_WVR_EL1(3), 3090 DBG_BCR_BVR_WCR_WVR_EL1(4), 3091 DBG_BCR_BVR_WCR_WVR_EL1(5), 3092 DBG_BCR_BVR_WCR_WVR_EL1(6), 3093 DBG_BCR_BVR_WCR_WVR_EL1(7), 3094 DBG_BCR_BVR_WCR_WVR_EL1(8), 3095 DBG_BCR_BVR_WCR_WVR_EL1(9), 3096 DBG_BCR_BVR_WCR_WVR_EL1(10), 3097 DBG_BCR_BVR_WCR_WVR_EL1(11), 3098 DBG_BCR_BVR_WCR_WVR_EL1(12), 3099 DBG_BCR_BVR_WCR_WVR_EL1(13), 3100 DBG_BCR_BVR_WCR_WVR_EL1(14), 3101 DBG_BCR_BVR_WCR_WVR_EL1(15), 3102 3103 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi }, 3104 { SYS_DESC(SYS_OSLAR_EL1), trap_oslar_el1 }, 3105 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1, 3106 OSLSR_EL1_OSLM_IMPLEMENTED, .set_user = set_oslsr_el1, }, 3107 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi }, 3108 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi }, 3109 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi }, 3110 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi }, 3111 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 }, 3112 3113 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi }, 3114 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi }, 3115 // DBGDTR[TR]X_EL0 share the same encoding 3116 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi }, 3117 3118 { SYS_DESC(SYS_DBGVCR32_EL2), undef_access, reset_val, DBGVCR32_EL2, 0 }, 3119 3120 IMPLEMENTATION_ID(MIDR_EL1, GENMASK_ULL(31, 0)), 3121 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 }, 3122 IMPLEMENTATION_ID(REVIDR_EL1, GENMASK_ULL(63, 0)), 3123 3124 /* 3125 * ID regs: all ID_SANITISED() entries here must have corresponding 3126 * entries in arm64_ftr_regs[]. 3127 */ 3128 3129 /* AArch64 mappings of the AArch32 ID registers */ 3130 /* CRm=1 */ 3131 AA32_ID_SANITISED(ID_PFR0_EL1), 3132 AA32_ID_SANITISED(ID_PFR1_EL1), 3133 { SYS_DESC(SYS_ID_DFR0_EL1), 3134 .access = access_id_reg, 3135 .get_user = get_id_reg, 3136 .set_user = set_id_dfr0_el1, 3137 .visibility = aa32_id_visibility, 3138 .reset = read_sanitised_id_dfr0_el1, 3139 .val = ID_DFR0_EL1_PerfMon_MASK | 3140 ID_DFR0_EL1_CopDbg_MASK, }, 3141 ID_HIDDEN(ID_AFR0_EL1), 3142 AA32_ID_SANITISED(ID_MMFR0_EL1), 3143 AA32_ID_SANITISED(ID_MMFR1_EL1), 3144 AA32_ID_SANITISED(ID_MMFR2_EL1), 3145 AA32_ID_SANITISED(ID_MMFR3_EL1), 3146 3147 /* CRm=2 */ 3148 AA32_ID_SANITISED(ID_ISAR0_EL1), 3149 AA32_ID_SANITISED(ID_ISAR1_EL1), 3150 AA32_ID_SANITISED(ID_ISAR2_EL1), 3151 AA32_ID_SANITISED(ID_ISAR3_EL1), 3152 AA32_ID_SANITISED(ID_ISAR4_EL1), 3153 AA32_ID_SANITISED(ID_ISAR5_EL1), 3154 AA32_ID_SANITISED(ID_MMFR4_EL1), 3155 AA32_ID_SANITISED(ID_ISAR6_EL1), 3156 3157 /* CRm=3 */ 3158 AA32_ID_SANITISED(MVFR0_EL1), 3159 AA32_ID_SANITISED(MVFR1_EL1), 3160 AA32_ID_SANITISED(MVFR2_EL1), 3161 ID_UNALLOCATED(3,3), 3162 AA32_ID_SANITISED(ID_PFR2_EL1), 3163 ID_HIDDEN(ID_DFR1_EL1), 3164 AA32_ID_SANITISED(ID_MMFR5_EL1), 3165 ID_UNALLOCATED(3,7), 3166 3167 /* AArch64 ID registers */ 3168 /* CRm=4 */ 3169 ID_FILTERED(ID_AA64PFR0_EL1, id_aa64pfr0_el1, 3170 ~(ID_AA64PFR0_EL1_AMU | 3171 ID_AA64PFR0_EL1_MPAM | 3172 ID_AA64PFR0_EL1_SVE | 3173 ID_AA64PFR0_EL1_AdvSIMD | 3174 ID_AA64PFR0_EL1_FP)), 3175 ID_FILTERED(ID_AA64PFR1_EL1, id_aa64pfr1_el1, 3176 ~(ID_AA64PFR1_EL1_PFAR | 3177 ID_AA64PFR1_EL1_MTEX | 3178 ID_AA64PFR1_EL1_THE | 3179 ID_AA64PFR1_EL1_GCS | 3180 ID_AA64PFR1_EL1_MTE_frac | 3181 ID_AA64PFR1_EL1_NMI | 3182 ID_AA64PFR1_EL1_RNDR_trap | 3183 ID_AA64PFR1_EL1_SME | 3184 ID_AA64PFR1_EL1_RES0 | 3185 ID_AA64PFR1_EL1_MPAM_frac | 3186 ID_AA64PFR1_EL1_MTE)), 3187 ID_WRITABLE(ID_AA64PFR2_EL1, 3188 ID_AA64PFR2_EL1_FPMR | 3189 ID_AA64PFR2_EL1_MTEFAR | 3190 ID_AA64PFR2_EL1_MTESTOREONLY), 3191 ID_UNALLOCATED(4,3), 3192 ID_WRITABLE(ID_AA64ZFR0_EL1, ~ID_AA64ZFR0_EL1_RES0), 3193 ID_HIDDEN(ID_AA64SMFR0_EL1), 3194 ID_UNALLOCATED(4,6), 3195 ID_WRITABLE(ID_AA64FPFR0_EL1, ~ID_AA64FPFR0_EL1_RES0), 3196 3197 /* CRm=5 */ 3198 /* 3199 * Prior to FEAT_Debugv8.9, the architecture defines context-aware 3200 * breakpoints (CTX_CMPs) as the highest numbered breakpoints (BRPs). 3201 * KVM does not trap + emulate the breakpoint registers, and as such 3202 * cannot support a layout that misaligns with the underlying hardware. 3203 * While it may be possible to describe a subset that aligns with 3204 * hardware, just prevent changes to BRPs and CTX_CMPs altogether for 3205 * simplicity. 3206 * 3207 * See DDI0487K.a, section D2.8.3 Breakpoint types and linking 3208 * of breakpoints for more details. 3209 */ 3210 ID_FILTERED(ID_AA64DFR0_EL1, id_aa64dfr0_el1, 3211 ID_AA64DFR0_EL1_DoubleLock_MASK | 3212 ID_AA64DFR0_EL1_WRPs_MASK | 3213 ID_AA64DFR0_EL1_PMUVer_MASK | 3214 ID_AA64DFR0_EL1_DebugVer_MASK), 3215 ID_SANITISED(ID_AA64DFR1_EL1), 3216 ID_UNALLOCATED(5,2), 3217 ID_UNALLOCATED(5,3), 3218 ID_HIDDEN(ID_AA64AFR0_EL1), 3219 ID_HIDDEN(ID_AA64AFR1_EL1), 3220 ID_UNALLOCATED(5,6), 3221 ID_UNALLOCATED(5,7), 3222 3223 /* CRm=6 */ 3224 ID_WRITABLE(ID_AA64ISAR0_EL1, ~ID_AA64ISAR0_EL1_RES0), 3225 ID_WRITABLE(ID_AA64ISAR1_EL1, ~(ID_AA64ISAR1_EL1_GPI | 3226 ID_AA64ISAR1_EL1_GPA | 3227 ID_AA64ISAR1_EL1_API | 3228 ID_AA64ISAR1_EL1_APA)), 3229 ID_WRITABLE(ID_AA64ISAR2_EL1, ~(ID_AA64ISAR2_EL1_RES0 | 3230 ID_AA64ISAR2_EL1_APA3 | 3231 ID_AA64ISAR2_EL1_GPA3)), 3232 ID_WRITABLE(ID_AA64ISAR3_EL1, (ID_AA64ISAR3_EL1_FPRCVT | 3233 ID_AA64ISAR3_EL1_LSFE | 3234 ID_AA64ISAR3_EL1_FAMINMAX)), 3235 ID_UNALLOCATED(6,4), 3236 ID_UNALLOCATED(6,5), 3237 ID_UNALLOCATED(6,6), 3238 ID_UNALLOCATED(6,7), 3239 3240 /* CRm=7 */ 3241 ID_FILTERED(ID_AA64MMFR0_EL1, id_aa64mmfr0_el1, 3242 ~(ID_AA64MMFR0_EL1_RES0 | 3243 ID_AA64MMFR0_EL1_ASIDBITS)), 3244 ID_WRITABLE(ID_AA64MMFR1_EL1, ~(ID_AA64MMFR1_EL1_RES0 | 3245 ID_AA64MMFR1_EL1_XNX | 3246 ID_AA64MMFR1_EL1_VH | 3247 ID_AA64MMFR1_EL1_VMIDBits)), 3248 ID_FILTERED(ID_AA64MMFR2_EL1, 3249 id_aa64mmfr2_el1, ~(ID_AA64MMFR2_EL1_RES0 | 3250 ID_AA64MMFR2_EL1_EVT | 3251 ID_AA64MMFR2_EL1_FWB | 3252 ID_AA64MMFR2_EL1_IDS | 3253 ID_AA64MMFR2_EL1_NV | 3254 ID_AA64MMFR2_EL1_CCIDX)), 3255 ID_WRITABLE(ID_AA64MMFR3_EL1, (ID_AA64MMFR3_EL1_TCRX | 3256 ID_AA64MMFR3_EL1_SCTLRX | 3257 ID_AA64MMFR3_EL1_S1PIE | 3258 ID_AA64MMFR3_EL1_S1POE)), 3259 ID_WRITABLE(ID_AA64MMFR4_EL1, ID_AA64MMFR4_EL1_NV_frac), 3260 ID_UNALLOCATED(7,5), 3261 ID_UNALLOCATED(7,6), 3262 ID_UNALLOCATED(7,7), 3263 3264 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 }, 3265 { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 }, 3266 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 }, 3267 { SYS_DESC(SYS_SCTLR2_EL1), access_vm_reg, reset_val, SCTLR2_EL1, 0, 3268 .visibility = sctlr2_visibility }, 3269 3270 MTE_REG(RGSR_EL1), 3271 MTE_REG(GCR_EL1), 3272 3273 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility }, 3274 { SYS_DESC(SYS_TRFCR_EL1), undef_access }, 3275 { SYS_DESC(SYS_SMPRI_EL1), undef_access }, 3276 { SYS_DESC(SYS_SMCR_EL1), undef_access }, 3277 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 }, 3278 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 }, 3279 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 }, 3280 { SYS_DESC(SYS_TCR2_EL1), access_vm_reg, reset_val, TCR2_EL1, 0, 3281 .visibility = tcr2_visibility }, 3282 3283 PTRAUTH_KEY(APIA), 3284 PTRAUTH_KEY(APIB), 3285 PTRAUTH_KEY(APDA), 3286 PTRAUTH_KEY(APDB), 3287 PTRAUTH_KEY(APGA), 3288 3289 { SYS_DESC(SYS_SPSR_EL1), access_spsr}, 3290 { SYS_DESC(SYS_ELR_EL1), access_elr}, 3291 3292 { SYS_DESC(SYS_ICC_PMR_EL1), undef_access }, 3293 3294 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 }, 3295 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 }, 3296 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 }, 3297 3298 { SYS_DESC(SYS_ERRIDR_EL1), access_ras }, 3299 { SYS_DESC(SYS_ERRSELR_EL1), access_ras }, 3300 { SYS_DESC(SYS_ERXFR_EL1), access_ras }, 3301 { SYS_DESC(SYS_ERXCTLR_EL1), access_ras }, 3302 { SYS_DESC(SYS_ERXSTATUS_EL1), access_ras }, 3303 { SYS_DESC(SYS_ERXADDR_EL1), access_ras }, 3304 { SYS_DESC(SYS_ERXPFGF_EL1), access_ras }, 3305 { SYS_DESC(SYS_ERXPFGCTL_EL1), access_ras }, 3306 { SYS_DESC(SYS_ERXPFGCDN_EL1), access_ras }, 3307 { SYS_DESC(SYS_ERXMISC0_EL1), access_ras }, 3308 { SYS_DESC(SYS_ERXMISC1_EL1), access_ras }, 3309 { SYS_DESC(SYS_ERXMISC2_EL1), access_ras }, 3310 { SYS_DESC(SYS_ERXMISC3_EL1), access_ras }, 3311 3312 MTE_REG(TFSR_EL1), 3313 MTE_REG(TFSRE0_EL1), 3314 3315 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 }, 3316 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 }, 3317 3318 { SYS_DESC(SYS_PMSCR_EL1), undef_access }, 3319 { SYS_DESC(SYS_PMSNEVFR_EL1), undef_access }, 3320 { SYS_DESC(SYS_PMSICR_EL1), undef_access }, 3321 { SYS_DESC(SYS_PMSIRR_EL1), undef_access }, 3322 { SYS_DESC(SYS_PMSFCR_EL1), undef_access }, 3323 { SYS_DESC(SYS_PMSEVFR_EL1), undef_access }, 3324 { SYS_DESC(SYS_PMSLATFR_EL1), undef_access }, 3325 { SYS_DESC(SYS_PMSIDR_EL1), undef_access }, 3326 { SYS_DESC(SYS_PMBLIMITR_EL1), undef_access }, 3327 { SYS_DESC(SYS_PMBPTR_EL1), undef_access }, 3328 { SYS_DESC(SYS_PMBSR_EL1), undef_access }, 3329 { SYS_DESC(SYS_PMSDSFR_EL1), undef_access }, 3330 /* PMBIDR_EL1 is not trapped */ 3331 3332 { PMU_SYS_REG(PMINTENSET_EL1), 3333 .access = access_pminten, .reg = PMINTENSET_EL1, 3334 .get_user = get_pmreg, .set_user = set_pmreg }, 3335 { PMU_SYS_REG(PMINTENCLR_EL1), 3336 .access = access_pminten, .reg = PMINTENSET_EL1, 3337 .get_user = get_pmreg, .set_user = set_pmreg }, 3338 { SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi }, 3339 3340 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 }, 3341 { SYS_DESC(SYS_PIRE0_EL1), NULL, reset_unknown, PIRE0_EL1, 3342 .visibility = s1pie_visibility }, 3343 { SYS_DESC(SYS_PIR_EL1), NULL, reset_unknown, PIR_EL1, 3344 .visibility = s1pie_visibility }, 3345 { SYS_DESC(SYS_POR_EL1), NULL, reset_unknown, POR_EL1, 3346 .visibility = s1poe_visibility }, 3347 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 }, 3348 3349 { SYS_DESC(SYS_LORSA_EL1), trap_loregion }, 3350 { SYS_DESC(SYS_LOREA_EL1), trap_loregion }, 3351 { SYS_DESC(SYS_LORN_EL1), trap_loregion }, 3352 { SYS_DESC(SYS_LORC_EL1), trap_loregion }, 3353 { SYS_DESC(SYS_MPAMIDR_EL1), undef_access }, 3354 { SYS_DESC(SYS_LORID_EL1), trap_loregion }, 3355 3356 { SYS_DESC(SYS_MPAM1_EL1), undef_access }, 3357 { SYS_DESC(SYS_MPAM0_EL1), undef_access }, 3358 { SYS_DESC(SYS_VBAR_EL1), access_rw, reset_val, VBAR_EL1, 0 }, 3359 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 }, 3360 3361 { SYS_DESC(SYS_ICC_IAR0_EL1), undef_access }, 3362 { SYS_DESC(SYS_ICC_EOIR0_EL1), undef_access }, 3363 { SYS_DESC(SYS_ICC_HPPIR0_EL1), undef_access }, 3364 { SYS_DESC(SYS_ICC_BPR0_EL1), undef_access }, 3365 { SYS_DESC(SYS_ICC_AP0R0_EL1), undef_access }, 3366 { SYS_DESC(SYS_ICC_AP0R1_EL1), undef_access }, 3367 { SYS_DESC(SYS_ICC_AP0R2_EL1), undef_access }, 3368 { SYS_DESC(SYS_ICC_AP0R3_EL1), undef_access }, 3369 { SYS_DESC(SYS_ICC_AP1R0_EL1), undef_access }, 3370 { SYS_DESC(SYS_ICC_AP1R1_EL1), undef_access }, 3371 { SYS_DESC(SYS_ICC_AP1R2_EL1), undef_access }, 3372 { SYS_DESC(SYS_ICC_AP1R3_EL1), undef_access }, 3373 { SYS_DESC(SYS_ICC_DIR_EL1), undef_access }, 3374 { SYS_DESC(SYS_ICC_RPR_EL1), undef_access }, 3375 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi }, 3376 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi }, 3377 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi }, 3378 { SYS_DESC(SYS_ICC_IAR1_EL1), undef_access }, 3379 { SYS_DESC(SYS_ICC_EOIR1_EL1), undef_access }, 3380 { SYS_DESC(SYS_ICC_HPPIR1_EL1), undef_access }, 3381 { SYS_DESC(SYS_ICC_BPR1_EL1), undef_access }, 3382 { SYS_DESC(SYS_ICC_CTLR_EL1), undef_access }, 3383 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre }, 3384 { SYS_DESC(SYS_ICC_IGRPEN0_EL1), undef_access }, 3385 { SYS_DESC(SYS_ICC_IGRPEN1_EL1), undef_access }, 3386 3387 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 }, 3388 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 }, 3389 3390 { SYS_DESC(SYS_ACCDATA_EL1), undef_access }, 3391 3392 { SYS_DESC(SYS_SCXTNUM_EL1), undef_access }, 3393 3394 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0}, 3395 3396 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr }, 3397 { SYS_DESC(SYS_CLIDR_EL1), access_clidr, reset_clidr, CLIDR_EL1, 3398 .set_user = set_clidr, .val = ~CLIDR_EL1_RES0 }, 3399 { SYS_DESC(SYS_CCSIDR2_EL1), undef_access }, 3400 { SYS_DESC(SYS_SMIDR_EL1), undef_access }, 3401 IMPLEMENTATION_ID(AIDR_EL1, GENMASK_ULL(63, 0)), 3402 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, 3403 ID_FILTERED(CTR_EL0, ctr_el0, 3404 CTR_EL0_DIC_MASK | 3405 CTR_EL0_IDC_MASK | 3406 CTR_EL0_DminLine_MASK | 3407 CTR_EL0_L1Ip_MASK | 3408 CTR_EL0_IminLine_MASK), 3409 { SYS_DESC(SYS_SVCR), undef_access, reset_val, SVCR, 0, .visibility = sme_visibility }, 3410 { SYS_DESC(SYS_FPMR), undef_access, reset_val, FPMR, 0, .visibility = fp8_visibility }, 3411 3412 { PMU_SYS_REG(PMCR_EL0), .access = access_pmcr, .reset = reset_pmcr, 3413 .reg = PMCR_EL0, .get_user = get_pmcr, .set_user = set_pmcr }, 3414 { PMU_SYS_REG(PMCNTENSET_EL0), 3415 .access = access_pmcnten, .reg = PMCNTENSET_EL0, 3416 .get_user = get_pmreg, .set_user = set_pmreg }, 3417 { PMU_SYS_REG(PMCNTENCLR_EL0), 3418 .access = access_pmcnten, .reg = PMCNTENSET_EL0, 3419 .get_user = get_pmreg, .set_user = set_pmreg }, 3420 { PMU_SYS_REG(PMOVSCLR_EL0), 3421 .access = access_pmovs, .reg = PMOVSSET_EL0, 3422 .get_user = get_pmreg, .set_user = set_pmreg }, 3423 /* 3424 * PM_SWINC_EL0 is exposed to userspace as RAZ/WI, as it was 3425 * previously (and pointlessly) advertised in the past... 3426 */ 3427 { PMU_SYS_REG(PMSWINC_EL0), 3428 .get_user = get_raz_reg, .set_user = set_wi_reg, 3429 .access = access_pmswinc, .reset = NULL }, 3430 { PMU_SYS_REG(PMSELR_EL0), 3431 .access = access_pmselr, .reset = reset_pmselr, .reg = PMSELR_EL0 }, 3432 { PMU_SYS_REG(PMCEID0_EL0), 3433 .access = access_pmceid, .reset = NULL }, 3434 { PMU_SYS_REG(PMCEID1_EL0), 3435 .access = access_pmceid, .reset = NULL }, 3436 { PMU_SYS_REG(PMCCNTR_EL0), 3437 .access = access_pmu_evcntr, .reset = reset_unknown, 3438 .reg = PMCCNTR_EL0, .get_user = get_pmu_evcntr, 3439 .set_user = set_pmu_evcntr }, 3440 { PMU_SYS_REG(PMXEVTYPER_EL0), 3441 .access = access_pmu_evtyper, .reset = NULL }, 3442 { PMU_SYS_REG(PMXEVCNTR_EL0), 3443 .access = access_pmu_evcntr, .reset = NULL }, 3444 /* 3445 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero 3446 * in 32bit mode. Here we choose to reset it as zero for consistency. 3447 */ 3448 { PMU_SYS_REG(PMUSERENR_EL0), .access = access_pmuserenr, 3449 .reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 }, 3450 { PMU_SYS_REG(PMOVSSET_EL0), 3451 .access = access_pmovs, .reg = PMOVSSET_EL0, 3452 .get_user = get_pmreg, .set_user = set_pmreg }, 3453 3454 { SYS_DESC(SYS_POR_EL0), NULL, reset_unknown, POR_EL0, 3455 .visibility = s1poe_visibility }, 3456 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 }, 3457 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 }, 3458 { SYS_DESC(SYS_TPIDR2_EL0), undef_access }, 3459 3460 { SYS_DESC(SYS_SCXTNUM_EL0), undef_access }, 3461 3462 { SYS_DESC(SYS_AMCR_EL0), undef_access }, 3463 { SYS_DESC(SYS_AMCFGR_EL0), undef_access }, 3464 { SYS_DESC(SYS_AMCGCR_EL0), undef_access }, 3465 { SYS_DESC(SYS_AMUSERENR_EL0), undef_access }, 3466 { SYS_DESC(SYS_AMCNTENCLR0_EL0), undef_access }, 3467 { SYS_DESC(SYS_AMCNTENSET0_EL0), undef_access }, 3468 { SYS_DESC(SYS_AMCNTENCLR1_EL0), undef_access }, 3469 { SYS_DESC(SYS_AMCNTENSET1_EL0), undef_access }, 3470 AMU_AMEVCNTR0_EL0(0), 3471 AMU_AMEVCNTR0_EL0(1), 3472 AMU_AMEVCNTR0_EL0(2), 3473 AMU_AMEVCNTR0_EL0(3), 3474 AMU_AMEVCNTR0_EL0(4), 3475 AMU_AMEVCNTR0_EL0(5), 3476 AMU_AMEVCNTR0_EL0(6), 3477 AMU_AMEVCNTR0_EL0(7), 3478 AMU_AMEVCNTR0_EL0(8), 3479 AMU_AMEVCNTR0_EL0(9), 3480 AMU_AMEVCNTR0_EL0(10), 3481 AMU_AMEVCNTR0_EL0(11), 3482 AMU_AMEVCNTR0_EL0(12), 3483 AMU_AMEVCNTR0_EL0(13), 3484 AMU_AMEVCNTR0_EL0(14), 3485 AMU_AMEVCNTR0_EL0(15), 3486 AMU_AMEVTYPER0_EL0(0), 3487 AMU_AMEVTYPER0_EL0(1), 3488 AMU_AMEVTYPER0_EL0(2), 3489 AMU_AMEVTYPER0_EL0(3), 3490 AMU_AMEVTYPER0_EL0(4), 3491 AMU_AMEVTYPER0_EL0(5), 3492 AMU_AMEVTYPER0_EL0(6), 3493 AMU_AMEVTYPER0_EL0(7), 3494 AMU_AMEVTYPER0_EL0(8), 3495 AMU_AMEVTYPER0_EL0(9), 3496 AMU_AMEVTYPER0_EL0(10), 3497 AMU_AMEVTYPER0_EL0(11), 3498 AMU_AMEVTYPER0_EL0(12), 3499 AMU_AMEVTYPER0_EL0(13), 3500 AMU_AMEVTYPER0_EL0(14), 3501 AMU_AMEVTYPER0_EL0(15), 3502 AMU_AMEVCNTR1_EL0(0), 3503 AMU_AMEVCNTR1_EL0(1), 3504 AMU_AMEVCNTR1_EL0(2), 3505 AMU_AMEVCNTR1_EL0(3), 3506 AMU_AMEVCNTR1_EL0(4), 3507 AMU_AMEVCNTR1_EL0(5), 3508 AMU_AMEVCNTR1_EL0(6), 3509 AMU_AMEVCNTR1_EL0(7), 3510 AMU_AMEVCNTR1_EL0(8), 3511 AMU_AMEVCNTR1_EL0(9), 3512 AMU_AMEVCNTR1_EL0(10), 3513 AMU_AMEVCNTR1_EL0(11), 3514 AMU_AMEVCNTR1_EL0(12), 3515 AMU_AMEVCNTR1_EL0(13), 3516 AMU_AMEVCNTR1_EL0(14), 3517 AMU_AMEVCNTR1_EL0(15), 3518 AMU_AMEVTYPER1_EL0(0), 3519 AMU_AMEVTYPER1_EL0(1), 3520 AMU_AMEVTYPER1_EL0(2), 3521 AMU_AMEVTYPER1_EL0(3), 3522 AMU_AMEVTYPER1_EL0(4), 3523 AMU_AMEVTYPER1_EL0(5), 3524 AMU_AMEVTYPER1_EL0(6), 3525 AMU_AMEVTYPER1_EL0(7), 3526 AMU_AMEVTYPER1_EL0(8), 3527 AMU_AMEVTYPER1_EL0(9), 3528 AMU_AMEVTYPER1_EL0(10), 3529 AMU_AMEVTYPER1_EL0(11), 3530 AMU_AMEVTYPER1_EL0(12), 3531 AMU_AMEVTYPER1_EL0(13), 3532 AMU_AMEVTYPER1_EL0(14), 3533 AMU_AMEVTYPER1_EL0(15), 3534 3535 { SYS_DESC(SYS_CNTPCT_EL0), .access = access_arch_timer, 3536 .get_user = arch_timer_get_user, .set_user = arch_timer_set_user }, 3537 { SYS_DESC(SYS_CNTVCT_EL0), .access = access_arch_timer, 3538 .get_user = arch_timer_get_user, .set_user = arch_timer_set_user }, 3539 { SYS_DESC(SYS_CNTPCTSS_EL0), access_arch_timer }, 3540 { SYS_DESC(SYS_CNTVCTSS_EL0), access_arch_timer }, 3541 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer }, 3542 TIMER_REG(CNTP_CTL_EL0, NULL), 3543 TIMER_REG(CNTP_CVAL_EL0, NULL), 3544 3545 { SYS_DESC(SYS_CNTV_TVAL_EL0), access_arch_timer }, 3546 TIMER_REG(CNTV_CTL_EL0, NULL), 3547 TIMER_REG(CNTV_CVAL_EL0, NULL), 3548 3549 /* PMEVCNTRn_EL0 */ 3550 PMU_PMEVCNTR_EL0(0), 3551 PMU_PMEVCNTR_EL0(1), 3552 PMU_PMEVCNTR_EL0(2), 3553 PMU_PMEVCNTR_EL0(3), 3554 PMU_PMEVCNTR_EL0(4), 3555 PMU_PMEVCNTR_EL0(5), 3556 PMU_PMEVCNTR_EL0(6), 3557 PMU_PMEVCNTR_EL0(7), 3558 PMU_PMEVCNTR_EL0(8), 3559 PMU_PMEVCNTR_EL0(9), 3560 PMU_PMEVCNTR_EL0(10), 3561 PMU_PMEVCNTR_EL0(11), 3562 PMU_PMEVCNTR_EL0(12), 3563 PMU_PMEVCNTR_EL0(13), 3564 PMU_PMEVCNTR_EL0(14), 3565 PMU_PMEVCNTR_EL0(15), 3566 PMU_PMEVCNTR_EL0(16), 3567 PMU_PMEVCNTR_EL0(17), 3568 PMU_PMEVCNTR_EL0(18), 3569 PMU_PMEVCNTR_EL0(19), 3570 PMU_PMEVCNTR_EL0(20), 3571 PMU_PMEVCNTR_EL0(21), 3572 PMU_PMEVCNTR_EL0(22), 3573 PMU_PMEVCNTR_EL0(23), 3574 PMU_PMEVCNTR_EL0(24), 3575 PMU_PMEVCNTR_EL0(25), 3576 PMU_PMEVCNTR_EL0(26), 3577 PMU_PMEVCNTR_EL0(27), 3578 PMU_PMEVCNTR_EL0(28), 3579 PMU_PMEVCNTR_EL0(29), 3580 PMU_PMEVCNTR_EL0(30), 3581 /* PMEVTYPERn_EL0 */ 3582 PMU_PMEVTYPER_EL0(0), 3583 PMU_PMEVTYPER_EL0(1), 3584 PMU_PMEVTYPER_EL0(2), 3585 PMU_PMEVTYPER_EL0(3), 3586 PMU_PMEVTYPER_EL0(4), 3587 PMU_PMEVTYPER_EL0(5), 3588 PMU_PMEVTYPER_EL0(6), 3589 PMU_PMEVTYPER_EL0(7), 3590 PMU_PMEVTYPER_EL0(8), 3591 PMU_PMEVTYPER_EL0(9), 3592 PMU_PMEVTYPER_EL0(10), 3593 PMU_PMEVTYPER_EL0(11), 3594 PMU_PMEVTYPER_EL0(12), 3595 PMU_PMEVTYPER_EL0(13), 3596 PMU_PMEVTYPER_EL0(14), 3597 PMU_PMEVTYPER_EL0(15), 3598 PMU_PMEVTYPER_EL0(16), 3599 PMU_PMEVTYPER_EL0(17), 3600 PMU_PMEVTYPER_EL0(18), 3601 PMU_PMEVTYPER_EL0(19), 3602 PMU_PMEVTYPER_EL0(20), 3603 PMU_PMEVTYPER_EL0(21), 3604 PMU_PMEVTYPER_EL0(22), 3605 PMU_PMEVTYPER_EL0(23), 3606 PMU_PMEVTYPER_EL0(24), 3607 PMU_PMEVTYPER_EL0(25), 3608 PMU_PMEVTYPER_EL0(26), 3609 PMU_PMEVTYPER_EL0(27), 3610 PMU_PMEVTYPER_EL0(28), 3611 PMU_PMEVTYPER_EL0(29), 3612 PMU_PMEVTYPER_EL0(30), 3613 /* 3614 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero 3615 * in 32bit mode. Here we choose to reset it as zero for consistency. 3616 */ 3617 { PMU_SYS_REG(PMCCFILTR_EL0), .access = access_pmu_evtyper, 3618 .reset = reset_val, .reg = PMCCFILTR_EL0, .val = 0 }, 3619 3620 EL2_REG_VNCR(VPIDR_EL2, reset_unknown, 0), 3621 EL2_REG_VNCR(VMPIDR_EL2, reset_unknown, 0), 3622 EL2_REG(SCTLR_EL2, access_rw, reset_val, SCTLR_EL2_RES1), 3623 EL2_REG(ACTLR_EL2, access_rw, reset_val, 0), 3624 EL2_REG_FILTERED(SCTLR2_EL2, access_vm_reg, reset_val, 0, 3625 sctlr2_el2_visibility), 3626 EL2_REG_VNCR(HCR_EL2, reset_hcr, 0), 3627 EL2_REG(MDCR_EL2, access_mdcr, reset_mdcr, 0), 3628 EL2_REG(CPTR_EL2, access_rw, reset_val, CPTR_NVHE_EL2_RES1), 3629 EL2_REG_VNCR(HSTR_EL2, reset_val, 0), 3630 EL2_REG_VNCR_FILT(HFGRTR_EL2, fgt_visibility), 3631 EL2_REG_VNCR_FILT(HFGWTR_EL2, fgt_visibility), 3632 EL2_REG_VNCR(HFGITR_EL2, reset_val, 0), 3633 EL2_REG_VNCR(HACR_EL2, reset_val, 0), 3634 3635 EL2_REG_FILTERED(ZCR_EL2, access_zcr_el2, reset_val, 0, 3636 sve_el2_visibility), 3637 3638 EL2_REG_VNCR(HCRX_EL2, reset_val, 0), 3639 3640 EL2_REG(TTBR0_EL2, access_rw, reset_val, 0), 3641 EL2_REG(TTBR1_EL2, access_rw, reset_val, 0), 3642 EL2_REG(TCR_EL2, access_rw, reset_val, TCR_EL2_RES1), 3643 EL2_REG_FILTERED(TCR2_EL2, access_rw, reset_val, TCR2_EL2_RES1, 3644 tcr2_el2_visibility), 3645 EL2_REG_VNCR(VTTBR_EL2, reset_val, 0), 3646 EL2_REG_VNCR(VTCR_EL2, reset_val, 0), 3647 EL2_REG_FILTERED(VNCR_EL2, bad_vncr_trap, reset_val, 0, 3648 vncr_el2_visibility), 3649 3650 { SYS_DESC(SYS_DACR32_EL2), undef_access, reset_unknown, DACR32_EL2 }, 3651 EL2_REG_VNCR_FILT(HDFGRTR2_EL2, fgt2_visibility), 3652 EL2_REG_VNCR_FILT(HDFGWTR2_EL2, fgt2_visibility), 3653 EL2_REG_VNCR_FILT(HFGRTR2_EL2, fgt2_visibility), 3654 EL2_REG_VNCR_FILT(HFGWTR2_EL2, fgt2_visibility), 3655 EL2_REG_VNCR_FILT(HDFGRTR_EL2, fgt_visibility), 3656 EL2_REG_VNCR_FILT(HDFGWTR_EL2, fgt_visibility), 3657 EL2_REG_VNCR_FILT(HAFGRTR_EL2, fgt_visibility), 3658 EL2_REG_VNCR_FILT(HFGITR2_EL2, fgt2_visibility), 3659 EL2_REG_REDIR(SPSR_EL2, reset_val, 0), 3660 EL2_REG_REDIR(ELR_EL2, reset_val, 0), 3661 { SYS_DESC(SYS_SP_EL1), access_sp_el1}, 3662 3663 /* AArch32 SPSR_* are RES0 if trapped from a NV guest */ 3664 { SYS_DESC(SYS_SPSR_irq), .access = trap_raz_wi }, 3665 { SYS_DESC(SYS_SPSR_abt), .access = trap_raz_wi }, 3666 { SYS_DESC(SYS_SPSR_und), .access = trap_raz_wi }, 3667 { SYS_DESC(SYS_SPSR_fiq), .access = trap_raz_wi }, 3668 3669 { SYS_DESC(SYS_IFSR32_EL2), undef_access, reset_unknown, IFSR32_EL2 }, 3670 EL2_REG(AFSR0_EL2, access_rw, reset_val, 0), 3671 EL2_REG(AFSR1_EL2, access_rw, reset_val, 0), 3672 EL2_REG_REDIR(ESR_EL2, reset_val, 0), 3673 EL2_REG_VNCR(VSESR_EL2, reset_unknown, 0), 3674 { SYS_DESC(SYS_FPEXC32_EL2), undef_access, reset_val, FPEXC32_EL2, 0x700 }, 3675 3676 EL2_REG_REDIR(FAR_EL2, reset_val, 0), 3677 EL2_REG(HPFAR_EL2, access_rw, reset_val, 0), 3678 3679 EL2_REG(MAIR_EL2, access_rw, reset_val, 0), 3680 EL2_REG_FILTERED(PIRE0_EL2, access_rw, reset_val, 0, 3681 s1pie_el2_visibility), 3682 EL2_REG_FILTERED(PIR_EL2, access_rw, reset_val, 0, 3683 s1pie_el2_visibility), 3684 EL2_REG_FILTERED(POR_EL2, access_rw, reset_val, 0, 3685 s1poe_el2_visibility), 3686 EL2_REG(AMAIR_EL2, access_rw, reset_val, 0), 3687 { SYS_DESC(SYS_MPAMHCR_EL2), undef_access }, 3688 { SYS_DESC(SYS_MPAMVPMV_EL2), undef_access }, 3689 { SYS_DESC(SYS_MPAM2_EL2), undef_access }, 3690 { SYS_DESC(SYS_MPAMVPM0_EL2), undef_access }, 3691 { SYS_DESC(SYS_MPAMVPM1_EL2), undef_access }, 3692 { SYS_DESC(SYS_MPAMVPM2_EL2), undef_access }, 3693 { SYS_DESC(SYS_MPAMVPM3_EL2), undef_access }, 3694 { SYS_DESC(SYS_MPAMVPM4_EL2), undef_access }, 3695 { SYS_DESC(SYS_MPAMVPM5_EL2), undef_access }, 3696 { SYS_DESC(SYS_MPAMVPM6_EL2), undef_access }, 3697 { SYS_DESC(SYS_MPAMVPM7_EL2), undef_access }, 3698 3699 EL2_REG(VBAR_EL2, access_rw, reset_val, 0), 3700 { SYS_DESC(SYS_RVBAR_EL2), undef_access }, 3701 { SYS_DESC(SYS_RMR_EL2), undef_access }, 3702 EL2_REG_VNCR(VDISR_EL2, reset_unknown, 0), 3703 3704 EL2_REG_VNCR_GICv3(ICH_AP0R0_EL2), 3705 EL2_REG_VNCR_GICv3(ICH_AP0R1_EL2), 3706 EL2_REG_VNCR_GICv3(ICH_AP0R2_EL2), 3707 EL2_REG_VNCR_GICv3(ICH_AP0R3_EL2), 3708 EL2_REG_VNCR_GICv3(ICH_AP1R0_EL2), 3709 EL2_REG_VNCR_GICv3(ICH_AP1R1_EL2), 3710 EL2_REG_VNCR_GICv3(ICH_AP1R2_EL2), 3711 EL2_REG_VNCR_GICv3(ICH_AP1R3_EL2), 3712 3713 { SYS_DESC(SYS_ICC_SRE_EL2), access_gic_sre }, 3714 3715 EL2_REG_VNCR_GICv3(ICH_HCR_EL2), 3716 { SYS_DESC(SYS_ICH_VTR_EL2), access_gic_vtr }, 3717 { SYS_DESC(SYS_ICH_MISR_EL2), access_gic_misr }, 3718 { SYS_DESC(SYS_ICH_EISR_EL2), access_gic_eisr }, 3719 { SYS_DESC(SYS_ICH_ELRSR_EL2), access_gic_elrsr }, 3720 EL2_REG_VNCR_GICv3(ICH_VMCR_EL2), 3721 3722 EL2_REG_VNCR_GICv3(ICH_LR0_EL2), 3723 EL2_REG_VNCR_GICv3(ICH_LR1_EL2), 3724 EL2_REG_VNCR_GICv3(ICH_LR2_EL2), 3725 EL2_REG_VNCR_GICv3(ICH_LR3_EL2), 3726 EL2_REG_VNCR_GICv3(ICH_LR4_EL2), 3727 EL2_REG_VNCR_GICv3(ICH_LR5_EL2), 3728 EL2_REG_VNCR_GICv3(ICH_LR6_EL2), 3729 EL2_REG_VNCR_GICv3(ICH_LR7_EL2), 3730 EL2_REG_VNCR_GICv3(ICH_LR8_EL2), 3731 EL2_REG_VNCR_GICv3(ICH_LR9_EL2), 3732 EL2_REG_VNCR_GICv3(ICH_LR10_EL2), 3733 EL2_REG_VNCR_GICv3(ICH_LR11_EL2), 3734 EL2_REG_VNCR_GICv3(ICH_LR12_EL2), 3735 EL2_REG_VNCR_GICv3(ICH_LR13_EL2), 3736 EL2_REG_VNCR_GICv3(ICH_LR14_EL2), 3737 EL2_REG_VNCR_GICv3(ICH_LR15_EL2), 3738 3739 EL2_REG(CONTEXTIDR_EL2, access_rw, reset_val, 0), 3740 EL2_REG(TPIDR_EL2, access_rw, reset_val, 0), 3741 3742 EL2_REG_VNCR(CNTVOFF_EL2, reset_val, 0), 3743 EL2_REG(CNTHCTL_EL2, access_rw, reset_val, 0), 3744 { SYS_DESC(SYS_CNTHP_TVAL_EL2), access_arch_timer }, 3745 TIMER_REG(CNTHP_CTL_EL2, el2_visibility), 3746 TIMER_REG(CNTHP_CVAL_EL2, el2_visibility), 3747 3748 { SYS_DESC(SYS_CNTHV_TVAL_EL2), access_arch_timer, .visibility = cnthv_visibility }, 3749 TIMER_REG(CNTHV_CTL_EL2, cnthv_visibility), 3750 TIMER_REG(CNTHV_CVAL_EL2, cnthv_visibility), 3751 3752 { SYS_DESC(SYS_CNTKCTL_EL12), access_cntkctl_el12 }, 3753 3754 { SYS_DESC(SYS_CNTP_TVAL_EL02), access_arch_timer }, 3755 { SYS_DESC(SYS_CNTP_CTL_EL02), access_arch_timer }, 3756 { SYS_DESC(SYS_CNTP_CVAL_EL02), access_arch_timer }, 3757 3758 { SYS_DESC(SYS_CNTV_TVAL_EL02), access_arch_timer }, 3759 { SYS_DESC(SYS_CNTV_CTL_EL02), access_arch_timer }, 3760 { SYS_DESC(SYS_CNTV_CVAL_EL02), access_arch_timer }, 3761 3762 EL2_REG(SP_EL2, NULL, reset_unknown, 0), 3763 }; 3764 3765 static bool handle_at_s1e01(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3766 const struct sys_reg_desc *r) 3767 { 3768 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3769 3770 __kvm_at_s1e01(vcpu, op, p->regval); 3771 3772 return true; 3773 } 3774 3775 static bool handle_at_s1e2(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3776 const struct sys_reg_desc *r) 3777 { 3778 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3779 3780 /* There is no FGT associated with AT S1E2A :-( */ 3781 if (op == OP_AT_S1E2A && 3782 !kvm_has_feat(vcpu->kvm, ID_AA64ISAR2_EL1, ATS1A, IMP)) { 3783 kvm_inject_undefined(vcpu); 3784 return false; 3785 } 3786 3787 __kvm_at_s1e2(vcpu, op, p->regval); 3788 3789 return true; 3790 } 3791 3792 static bool handle_at_s12(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3793 const struct sys_reg_desc *r) 3794 { 3795 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3796 3797 __kvm_at_s12(vcpu, op, p->regval); 3798 3799 return true; 3800 } 3801 3802 static bool kvm_supported_tlbi_s12_op(struct kvm_vcpu *vpcu, u32 instr) 3803 { 3804 struct kvm *kvm = vpcu->kvm; 3805 u8 CRm = sys_reg_CRm(instr); 3806 3807 if (sys_reg_CRn(instr) == TLBI_CRn_nXS && 3808 !kvm_has_feat(kvm, ID_AA64ISAR1_EL1, XS, IMP)) 3809 return false; 3810 3811 if (CRm == TLBI_CRm_nROS && 3812 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 3813 return false; 3814 3815 return true; 3816 } 3817 3818 static bool handle_alle1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3819 const struct sys_reg_desc *r) 3820 { 3821 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3822 3823 if (!kvm_supported_tlbi_s12_op(vcpu, sys_encoding)) 3824 return undef_access(vcpu, p, r); 3825 3826 write_lock(&vcpu->kvm->mmu_lock); 3827 3828 /* 3829 * Drop all shadow S2s, resulting in S1/S2 TLBIs for each of the 3830 * corresponding VMIDs. 3831 */ 3832 kvm_nested_s2_unmap(vcpu->kvm, true); 3833 3834 write_unlock(&vcpu->kvm->mmu_lock); 3835 3836 return true; 3837 } 3838 3839 static bool kvm_supported_tlbi_ipas2_op(struct kvm_vcpu *vpcu, u32 instr) 3840 { 3841 struct kvm *kvm = vpcu->kvm; 3842 u8 CRm = sys_reg_CRm(instr); 3843 u8 Op2 = sys_reg_Op2(instr); 3844 3845 if (sys_reg_CRn(instr) == TLBI_CRn_nXS && 3846 !kvm_has_feat(kvm, ID_AA64ISAR1_EL1, XS, IMP)) 3847 return false; 3848 3849 if (CRm == TLBI_CRm_IPAIS && (Op2 == 2 || Op2 == 6) && 3850 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE)) 3851 return false; 3852 3853 if (CRm == TLBI_CRm_IPAONS && (Op2 == 0 || Op2 == 4) && 3854 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 3855 return false; 3856 3857 if (CRm == TLBI_CRm_IPAONS && (Op2 == 3 || Op2 == 7) && 3858 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE)) 3859 return false; 3860 3861 return true; 3862 } 3863 3864 /* Only defined here as this is an internal "abstraction" */ 3865 union tlbi_info { 3866 struct { 3867 u64 start; 3868 u64 size; 3869 } range; 3870 3871 struct { 3872 u64 addr; 3873 } ipa; 3874 3875 struct { 3876 u64 addr; 3877 u32 encoding; 3878 } va; 3879 }; 3880 3881 static void s2_mmu_unmap_range(struct kvm_s2_mmu *mmu, 3882 const union tlbi_info *info) 3883 { 3884 /* 3885 * The unmap operation is allowed to drop the MMU lock and block, which 3886 * means that @mmu could be used for a different context than the one 3887 * currently being invalidated. 3888 * 3889 * This behavior is still safe, as: 3890 * 3891 * 1) The vCPU(s) that recycled the MMU are responsible for invalidating 3892 * the entire MMU before reusing it, which still honors the intent 3893 * of a TLBI. 3894 * 3895 * 2) Until the guest TLBI instruction is 'retired' (i.e. increment PC 3896 * and ERET to the guest), other vCPUs are allowed to use stale 3897 * translations. 3898 * 3899 * 3) Accidentally unmapping an unrelated MMU context is nonfatal, and 3900 * at worst may cause more aborts for shadow stage-2 fills. 3901 * 3902 * Dropping the MMU lock also implies that shadow stage-2 fills could 3903 * happen behind the back of the TLBI. This is still safe, though, as 3904 * the L1 needs to put its stage-2 in a consistent state before doing 3905 * the TLBI. 3906 */ 3907 kvm_stage2_unmap_range(mmu, info->range.start, info->range.size, true); 3908 } 3909 3910 static bool handle_vmalls12e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3911 const struct sys_reg_desc *r) 3912 { 3913 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3914 u64 limit, vttbr; 3915 3916 if (!kvm_supported_tlbi_s12_op(vcpu, sys_encoding)) 3917 return undef_access(vcpu, p, r); 3918 3919 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 3920 limit = BIT_ULL(kvm_get_pa_bits(vcpu->kvm)); 3921 3922 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 3923 &(union tlbi_info) { 3924 .range = { 3925 .start = 0, 3926 .size = limit, 3927 }, 3928 }, 3929 s2_mmu_unmap_range); 3930 3931 return true; 3932 } 3933 3934 static bool handle_ripas2e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3935 const struct sys_reg_desc *r) 3936 { 3937 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3938 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 3939 u64 base, range; 3940 3941 if (!kvm_supported_tlbi_ipas2_op(vcpu, sys_encoding)) 3942 return undef_access(vcpu, p, r); 3943 3944 /* 3945 * Because the shadow S2 structure doesn't necessarily reflect that 3946 * of the guest's S2 (different base granule size, for example), we 3947 * decide to ignore TTL and only use the described range. 3948 */ 3949 base = decode_range_tlbi(p->regval, &range, NULL); 3950 3951 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 3952 &(union tlbi_info) { 3953 .range = { 3954 .start = base, 3955 .size = range, 3956 }, 3957 }, 3958 s2_mmu_unmap_range); 3959 3960 return true; 3961 } 3962 3963 static void s2_mmu_unmap_ipa(struct kvm_s2_mmu *mmu, 3964 const union tlbi_info *info) 3965 { 3966 unsigned long max_size; 3967 u64 base_addr; 3968 3969 /* 3970 * We drop a number of things from the supplied value: 3971 * 3972 * - NS bit: we're non-secure only. 3973 * 3974 * - IPA[51:48]: We don't support 52bit IPA just yet... 3975 * 3976 * And of course, adjust the IPA to be on an actual address. 3977 */ 3978 base_addr = (info->ipa.addr & GENMASK_ULL(35, 0)) << 12; 3979 max_size = compute_tlb_inval_range(mmu, info->ipa.addr); 3980 base_addr &= ~(max_size - 1); 3981 3982 /* 3983 * See comment in s2_mmu_unmap_range() for why this is allowed to 3984 * reschedule. 3985 */ 3986 kvm_stage2_unmap_range(mmu, base_addr, max_size, true); 3987 } 3988 3989 static bool handle_ipas2e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3990 const struct sys_reg_desc *r) 3991 { 3992 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3993 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 3994 3995 if (!kvm_supported_tlbi_ipas2_op(vcpu, sys_encoding)) 3996 return undef_access(vcpu, p, r); 3997 3998 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 3999 &(union tlbi_info) { 4000 .ipa = { 4001 .addr = p->regval, 4002 }, 4003 }, 4004 s2_mmu_unmap_ipa); 4005 4006 return true; 4007 } 4008 4009 static void s2_mmu_tlbi_s1e1(struct kvm_s2_mmu *mmu, 4010 const union tlbi_info *info) 4011 { 4012 WARN_ON(__kvm_tlbi_s1e2(mmu, info->va.addr, info->va.encoding)); 4013 } 4014 4015 static bool handle_tlbi_el2(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 4016 const struct sys_reg_desc *r) 4017 { 4018 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 4019 4020 if (!kvm_supported_tlbi_s1e2_op(vcpu, sys_encoding)) 4021 return undef_access(vcpu, p, r); 4022 4023 kvm_handle_s1e2_tlbi(vcpu, sys_encoding, p->regval); 4024 return true; 4025 } 4026 4027 static bool handle_tlbi_el1(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 4028 const struct sys_reg_desc *r) 4029 { 4030 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 4031 4032 /* 4033 * If we're here, this is because we've trapped on a EL1 TLBI 4034 * instruction that affects the EL1 translation regime while 4035 * we're running in a context that doesn't allow us to let the 4036 * HW do its thing (aka vEL2): 4037 * 4038 * - HCR_EL2.E2H == 0 : a non-VHE guest 4039 * - HCR_EL2.{E2H,TGE} == { 1, 0 } : a VHE guest in guest mode 4040 * 4041 * Another possibility is that we are invalidating the EL2 context 4042 * using EL1 instructions, but that we landed here because we need 4043 * additional invalidation for structures that are not held in the 4044 * CPU TLBs (such as the VNCR pseudo-TLB and its EL2 mapping). In 4045 * that case, we are guaranteed that HCR_EL2.{E2H,TGE} == { 1, 1 } 4046 * as we don't allow an NV-capable L1 in a nVHE configuration. 4047 * 4048 * We don't expect these helpers to ever be called when running 4049 * in a vEL1 context. 4050 */ 4051 4052 WARN_ON(!vcpu_is_el2(vcpu)); 4053 4054 if (!kvm_supported_tlbi_s1e1_op(vcpu, sys_encoding)) 4055 return undef_access(vcpu, p, r); 4056 4057 if (vcpu_el2_e2h_is_set(vcpu) && vcpu_el2_tge_is_set(vcpu)) { 4058 kvm_handle_s1e2_tlbi(vcpu, sys_encoding, p->regval); 4059 return true; 4060 } 4061 4062 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, 4063 get_vmid(__vcpu_sys_reg(vcpu, VTTBR_EL2)), 4064 &(union tlbi_info) { 4065 .va = { 4066 .addr = p->regval, 4067 .encoding = sys_encoding, 4068 }, 4069 }, 4070 s2_mmu_tlbi_s1e1); 4071 4072 return true; 4073 } 4074 4075 #define SYS_INSN(insn, access_fn) \ 4076 { \ 4077 SYS_DESC(OP_##insn), \ 4078 .access = (access_fn), \ 4079 } 4080 4081 static struct sys_reg_desc sys_insn_descs[] = { 4082 { SYS_DESC(SYS_DC_ISW), access_dcsw }, 4083 { SYS_DESC(SYS_DC_IGSW), access_dcgsw }, 4084 { SYS_DESC(SYS_DC_IGDSW), access_dcgsw }, 4085 4086 SYS_INSN(AT_S1E1R, handle_at_s1e01), 4087 SYS_INSN(AT_S1E1W, handle_at_s1e01), 4088 SYS_INSN(AT_S1E0R, handle_at_s1e01), 4089 SYS_INSN(AT_S1E0W, handle_at_s1e01), 4090 SYS_INSN(AT_S1E1RP, handle_at_s1e01), 4091 SYS_INSN(AT_S1E1WP, handle_at_s1e01), 4092 4093 { SYS_DESC(SYS_DC_CSW), access_dcsw }, 4094 { SYS_DESC(SYS_DC_CGSW), access_dcgsw }, 4095 { SYS_DESC(SYS_DC_CGDSW), access_dcgsw }, 4096 { SYS_DESC(SYS_DC_CISW), access_dcsw }, 4097 { SYS_DESC(SYS_DC_CIGSW), access_dcgsw }, 4098 { SYS_DESC(SYS_DC_CIGDSW), access_dcgsw }, 4099 4100 SYS_INSN(TLBI_VMALLE1OS, handle_tlbi_el1), 4101 SYS_INSN(TLBI_VAE1OS, handle_tlbi_el1), 4102 SYS_INSN(TLBI_ASIDE1OS, handle_tlbi_el1), 4103 SYS_INSN(TLBI_VAAE1OS, handle_tlbi_el1), 4104 SYS_INSN(TLBI_VALE1OS, handle_tlbi_el1), 4105 SYS_INSN(TLBI_VAALE1OS, handle_tlbi_el1), 4106 4107 SYS_INSN(TLBI_RVAE1IS, handle_tlbi_el1), 4108 SYS_INSN(TLBI_RVAAE1IS, handle_tlbi_el1), 4109 SYS_INSN(TLBI_RVALE1IS, handle_tlbi_el1), 4110 SYS_INSN(TLBI_RVAALE1IS, handle_tlbi_el1), 4111 4112 SYS_INSN(TLBI_VMALLE1IS, handle_tlbi_el1), 4113 SYS_INSN(TLBI_VAE1IS, handle_tlbi_el1), 4114 SYS_INSN(TLBI_ASIDE1IS, handle_tlbi_el1), 4115 SYS_INSN(TLBI_VAAE1IS, handle_tlbi_el1), 4116 SYS_INSN(TLBI_VALE1IS, handle_tlbi_el1), 4117 SYS_INSN(TLBI_VAALE1IS, handle_tlbi_el1), 4118 4119 SYS_INSN(TLBI_RVAE1OS, handle_tlbi_el1), 4120 SYS_INSN(TLBI_RVAAE1OS, handle_tlbi_el1), 4121 SYS_INSN(TLBI_RVALE1OS, handle_tlbi_el1), 4122 SYS_INSN(TLBI_RVAALE1OS, handle_tlbi_el1), 4123 4124 SYS_INSN(TLBI_RVAE1, handle_tlbi_el1), 4125 SYS_INSN(TLBI_RVAAE1, handle_tlbi_el1), 4126 SYS_INSN(TLBI_RVALE1, handle_tlbi_el1), 4127 SYS_INSN(TLBI_RVAALE1, handle_tlbi_el1), 4128 4129 SYS_INSN(TLBI_VMALLE1, handle_tlbi_el1), 4130 SYS_INSN(TLBI_VAE1, handle_tlbi_el1), 4131 SYS_INSN(TLBI_ASIDE1, handle_tlbi_el1), 4132 SYS_INSN(TLBI_VAAE1, handle_tlbi_el1), 4133 SYS_INSN(TLBI_VALE1, handle_tlbi_el1), 4134 SYS_INSN(TLBI_VAALE1, handle_tlbi_el1), 4135 4136 SYS_INSN(TLBI_VMALLE1OSNXS, handle_tlbi_el1), 4137 SYS_INSN(TLBI_VAE1OSNXS, handle_tlbi_el1), 4138 SYS_INSN(TLBI_ASIDE1OSNXS, handle_tlbi_el1), 4139 SYS_INSN(TLBI_VAAE1OSNXS, handle_tlbi_el1), 4140 SYS_INSN(TLBI_VALE1OSNXS, handle_tlbi_el1), 4141 SYS_INSN(TLBI_VAALE1OSNXS, handle_tlbi_el1), 4142 4143 SYS_INSN(TLBI_RVAE1ISNXS, handle_tlbi_el1), 4144 SYS_INSN(TLBI_RVAAE1ISNXS, handle_tlbi_el1), 4145 SYS_INSN(TLBI_RVALE1ISNXS, handle_tlbi_el1), 4146 SYS_INSN(TLBI_RVAALE1ISNXS, handle_tlbi_el1), 4147 4148 SYS_INSN(TLBI_VMALLE1ISNXS, handle_tlbi_el1), 4149 SYS_INSN(TLBI_VAE1ISNXS, handle_tlbi_el1), 4150 SYS_INSN(TLBI_ASIDE1ISNXS, handle_tlbi_el1), 4151 SYS_INSN(TLBI_VAAE1ISNXS, handle_tlbi_el1), 4152 SYS_INSN(TLBI_VALE1ISNXS, handle_tlbi_el1), 4153 SYS_INSN(TLBI_VAALE1ISNXS, handle_tlbi_el1), 4154 4155 SYS_INSN(TLBI_RVAE1OSNXS, handle_tlbi_el1), 4156 SYS_INSN(TLBI_RVAAE1OSNXS, handle_tlbi_el1), 4157 SYS_INSN(TLBI_RVALE1OSNXS, handle_tlbi_el1), 4158 SYS_INSN(TLBI_RVAALE1OSNXS, handle_tlbi_el1), 4159 4160 SYS_INSN(TLBI_RVAE1NXS, handle_tlbi_el1), 4161 SYS_INSN(TLBI_RVAAE1NXS, handle_tlbi_el1), 4162 SYS_INSN(TLBI_RVALE1NXS, handle_tlbi_el1), 4163 SYS_INSN(TLBI_RVAALE1NXS, handle_tlbi_el1), 4164 4165 SYS_INSN(TLBI_VMALLE1NXS, handle_tlbi_el1), 4166 SYS_INSN(TLBI_VAE1NXS, handle_tlbi_el1), 4167 SYS_INSN(TLBI_ASIDE1NXS, handle_tlbi_el1), 4168 SYS_INSN(TLBI_VAAE1NXS, handle_tlbi_el1), 4169 SYS_INSN(TLBI_VALE1NXS, handle_tlbi_el1), 4170 SYS_INSN(TLBI_VAALE1NXS, handle_tlbi_el1), 4171 4172 SYS_INSN(AT_S1E2R, handle_at_s1e2), 4173 SYS_INSN(AT_S1E2W, handle_at_s1e2), 4174 SYS_INSN(AT_S12E1R, handle_at_s12), 4175 SYS_INSN(AT_S12E1W, handle_at_s12), 4176 SYS_INSN(AT_S12E0R, handle_at_s12), 4177 SYS_INSN(AT_S12E0W, handle_at_s12), 4178 SYS_INSN(AT_S1E2A, handle_at_s1e2), 4179 4180 SYS_INSN(TLBI_IPAS2E1IS, handle_ipas2e1is), 4181 SYS_INSN(TLBI_RIPAS2E1IS, handle_ripas2e1is), 4182 SYS_INSN(TLBI_IPAS2LE1IS, handle_ipas2e1is), 4183 SYS_INSN(TLBI_RIPAS2LE1IS, handle_ripas2e1is), 4184 4185 SYS_INSN(TLBI_ALLE2OS, handle_tlbi_el2), 4186 SYS_INSN(TLBI_VAE2OS, handle_tlbi_el2), 4187 SYS_INSN(TLBI_ALLE1OS, handle_alle1is), 4188 SYS_INSN(TLBI_VALE2OS, handle_tlbi_el2), 4189 SYS_INSN(TLBI_VMALLS12E1OS, handle_vmalls12e1is), 4190 4191 SYS_INSN(TLBI_RVAE2IS, handle_tlbi_el2), 4192 SYS_INSN(TLBI_RVALE2IS, handle_tlbi_el2), 4193 SYS_INSN(TLBI_ALLE2IS, handle_tlbi_el2), 4194 SYS_INSN(TLBI_VAE2IS, handle_tlbi_el2), 4195 4196 SYS_INSN(TLBI_ALLE1IS, handle_alle1is), 4197 4198 SYS_INSN(TLBI_VALE2IS, handle_tlbi_el2), 4199 4200 SYS_INSN(TLBI_VMALLS12E1IS, handle_vmalls12e1is), 4201 SYS_INSN(TLBI_IPAS2E1OS, handle_ipas2e1is), 4202 SYS_INSN(TLBI_IPAS2E1, handle_ipas2e1is), 4203 SYS_INSN(TLBI_RIPAS2E1, handle_ripas2e1is), 4204 SYS_INSN(TLBI_RIPAS2E1OS, handle_ripas2e1is), 4205 SYS_INSN(TLBI_IPAS2LE1OS, handle_ipas2e1is), 4206 SYS_INSN(TLBI_IPAS2LE1, handle_ipas2e1is), 4207 SYS_INSN(TLBI_RIPAS2LE1, handle_ripas2e1is), 4208 SYS_INSN(TLBI_RIPAS2LE1OS, handle_ripas2e1is), 4209 SYS_INSN(TLBI_RVAE2OS, handle_tlbi_el2), 4210 SYS_INSN(TLBI_RVALE2OS, handle_tlbi_el2), 4211 SYS_INSN(TLBI_RVAE2, handle_tlbi_el2), 4212 SYS_INSN(TLBI_RVALE2, handle_tlbi_el2), 4213 SYS_INSN(TLBI_ALLE2, handle_tlbi_el2), 4214 SYS_INSN(TLBI_VAE2, handle_tlbi_el2), 4215 4216 SYS_INSN(TLBI_ALLE1, handle_alle1is), 4217 4218 SYS_INSN(TLBI_VALE2, handle_tlbi_el2), 4219 4220 SYS_INSN(TLBI_VMALLS12E1, handle_vmalls12e1is), 4221 4222 SYS_INSN(TLBI_IPAS2E1ISNXS, handle_ipas2e1is), 4223 SYS_INSN(TLBI_RIPAS2E1ISNXS, handle_ripas2e1is), 4224 SYS_INSN(TLBI_IPAS2LE1ISNXS, handle_ipas2e1is), 4225 SYS_INSN(TLBI_RIPAS2LE1ISNXS, handle_ripas2e1is), 4226 4227 SYS_INSN(TLBI_ALLE2OSNXS, handle_tlbi_el2), 4228 SYS_INSN(TLBI_VAE2OSNXS, handle_tlbi_el2), 4229 SYS_INSN(TLBI_ALLE1OSNXS, handle_alle1is), 4230 SYS_INSN(TLBI_VALE2OSNXS, handle_tlbi_el2), 4231 SYS_INSN(TLBI_VMALLS12E1OSNXS, handle_vmalls12e1is), 4232 4233 SYS_INSN(TLBI_RVAE2ISNXS, handle_tlbi_el2), 4234 SYS_INSN(TLBI_RVALE2ISNXS, handle_tlbi_el2), 4235 SYS_INSN(TLBI_ALLE2ISNXS, handle_tlbi_el2), 4236 SYS_INSN(TLBI_VAE2ISNXS, handle_tlbi_el2), 4237 4238 SYS_INSN(TLBI_ALLE1ISNXS, handle_alle1is), 4239 SYS_INSN(TLBI_VALE2ISNXS, handle_tlbi_el2), 4240 SYS_INSN(TLBI_VMALLS12E1ISNXS, handle_vmalls12e1is), 4241 SYS_INSN(TLBI_IPAS2E1OSNXS, handle_ipas2e1is), 4242 SYS_INSN(TLBI_IPAS2E1NXS, handle_ipas2e1is), 4243 SYS_INSN(TLBI_RIPAS2E1NXS, handle_ripas2e1is), 4244 SYS_INSN(TLBI_RIPAS2E1OSNXS, handle_ripas2e1is), 4245 SYS_INSN(TLBI_IPAS2LE1OSNXS, handle_ipas2e1is), 4246 SYS_INSN(TLBI_IPAS2LE1NXS, handle_ipas2e1is), 4247 SYS_INSN(TLBI_RIPAS2LE1NXS, handle_ripas2e1is), 4248 SYS_INSN(TLBI_RIPAS2LE1OSNXS, handle_ripas2e1is), 4249 SYS_INSN(TLBI_RVAE2OSNXS, handle_tlbi_el2), 4250 SYS_INSN(TLBI_RVALE2OSNXS, handle_tlbi_el2), 4251 SYS_INSN(TLBI_RVAE2NXS, handle_tlbi_el2), 4252 SYS_INSN(TLBI_RVALE2NXS, handle_tlbi_el2), 4253 SYS_INSN(TLBI_ALLE2NXS, handle_tlbi_el2), 4254 SYS_INSN(TLBI_VAE2NXS, handle_tlbi_el2), 4255 SYS_INSN(TLBI_ALLE1NXS, handle_alle1is), 4256 SYS_INSN(TLBI_VALE2NXS, handle_tlbi_el2), 4257 SYS_INSN(TLBI_VMALLS12E1NXS, handle_vmalls12e1is), 4258 }; 4259 4260 static bool trap_dbgdidr(struct kvm_vcpu *vcpu, 4261 struct sys_reg_params *p, 4262 const struct sys_reg_desc *r) 4263 { 4264 if (p->is_write) { 4265 return ignore_write(vcpu, p); 4266 } else { 4267 u64 dfr = kvm_read_vm_id_reg(vcpu->kvm, SYS_ID_AA64DFR0_EL1); 4268 u32 el3 = kvm_has_feat(vcpu->kvm, ID_AA64PFR0_EL1, EL3, IMP); 4269 4270 p->regval = ((SYS_FIELD_GET(ID_AA64DFR0_EL1, WRPs, dfr) << 28) | 4271 (SYS_FIELD_GET(ID_AA64DFR0_EL1, BRPs, dfr) << 24) | 4272 (SYS_FIELD_GET(ID_AA64DFR0_EL1, CTX_CMPs, dfr) << 20) | 4273 (SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, dfr) << 16) | 4274 (1 << 15) | (el3 << 14) | (el3 << 12)); 4275 return true; 4276 } 4277 } 4278 4279 /* 4280 * AArch32 debug register mappings 4281 * 4282 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0] 4283 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32] 4284 * 4285 * None of the other registers share their location, so treat them as 4286 * if they were 64bit. 4287 */ 4288 #define DBG_BCR_BVR_WCR_WVR(n) \ 4289 /* DBGBVRn */ \ 4290 { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), \ 4291 trap_dbg_wb_reg, NULL, n }, \ 4292 /* DBGBCRn */ \ 4293 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_dbg_wb_reg, NULL, n }, \ 4294 /* DBGWVRn */ \ 4295 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_dbg_wb_reg, NULL, n }, \ 4296 /* DBGWCRn */ \ 4297 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_dbg_wb_reg, NULL, n } 4298 4299 #define DBGBXVR(n) \ 4300 { AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), \ 4301 trap_dbg_wb_reg, NULL, n } 4302 4303 /* 4304 * Trapped cp14 registers. We generally ignore most of the external 4305 * debug, on the principle that they don't really make sense to a 4306 * guest. Revisit this one day, would this principle change. 4307 */ 4308 static const struct sys_reg_desc cp14_regs[] = { 4309 /* DBGDIDR */ 4310 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgdidr }, 4311 /* DBGDTRRXext */ 4312 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi }, 4313 4314 DBG_BCR_BVR_WCR_WVR(0), 4315 /* DBGDSCRint */ 4316 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi }, 4317 DBG_BCR_BVR_WCR_WVR(1), 4318 /* DBGDCCINT */ 4319 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug_regs, NULL, MDCCINT_EL1 }, 4320 /* DBGDSCRext */ 4321 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug_regs, NULL, MDSCR_EL1 }, 4322 DBG_BCR_BVR_WCR_WVR(2), 4323 /* DBGDTR[RT]Xint */ 4324 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi }, 4325 /* DBGDTR[RT]Xext */ 4326 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi }, 4327 DBG_BCR_BVR_WCR_WVR(3), 4328 DBG_BCR_BVR_WCR_WVR(4), 4329 DBG_BCR_BVR_WCR_WVR(5), 4330 /* DBGWFAR */ 4331 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi }, 4332 /* DBGOSECCR */ 4333 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi }, 4334 DBG_BCR_BVR_WCR_WVR(6), 4335 /* DBGVCR */ 4336 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug_regs, NULL, DBGVCR32_EL2 }, 4337 DBG_BCR_BVR_WCR_WVR(7), 4338 DBG_BCR_BVR_WCR_WVR(8), 4339 DBG_BCR_BVR_WCR_WVR(9), 4340 DBG_BCR_BVR_WCR_WVR(10), 4341 DBG_BCR_BVR_WCR_WVR(11), 4342 DBG_BCR_BVR_WCR_WVR(12), 4343 DBG_BCR_BVR_WCR_WVR(13), 4344 DBG_BCR_BVR_WCR_WVR(14), 4345 DBG_BCR_BVR_WCR_WVR(15), 4346 4347 /* DBGDRAR (32bit) */ 4348 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi }, 4349 4350 DBGBXVR(0), 4351 /* DBGOSLAR */ 4352 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_oslar_el1 }, 4353 DBGBXVR(1), 4354 /* DBGOSLSR */ 4355 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1, NULL, OSLSR_EL1 }, 4356 DBGBXVR(2), 4357 DBGBXVR(3), 4358 /* DBGOSDLR */ 4359 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi }, 4360 DBGBXVR(4), 4361 /* DBGPRCR */ 4362 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi }, 4363 DBGBXVR(5), 4364 DBGBXVR(6), 4365 DBGBXVR(7), 4366 DBGBXVR(8), 4367 DBGBXVR(9), 4368 DBGBXVR(10), 4369 DBGBXVR(11), 4370 DBGBXVR(12), 4371 DBGBXVR(13), 4372 DBGBXVR(14), 4373 DBGBXVR(15), 4374 4375 /* DBGDSAR (32bit) */ 4376 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi }, 4377 4378 /* DBGDEVID2 */ 4379 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi }, 4380 /* DBGDEVID1 */ 4381 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi }, 4382 /* DBGDEVID */ 4383 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi }, 4384 /* DBGCLAIMSET */ 4385 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi }, 4386 /* DBGCLAIMCLR */ 4387 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi }, 4388 /* DBGAUTHSTATUS */ 4389 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 }, 4390 }; 4391 4392 /* Trapped cp14 64bit registers */ 4393 static const struct sys_reg_desc cp14_64_regs[] = { 4394 /* DBGDRAR (64bit) */ 4395 { Op1( 0), CRm( 1), .access = trap_raz_wi }, 4396 4397 /* DBGDSAR (64bit) */ 4398 { Op1( 0), CRm( 2), .access = trap_raz_wi }, 4399 }; 4400 4401 #define CP15_PMU_SYS_REG(_map, _Op1, _CRn, _CRm, _Op2) \ 4402 AA32(_map), \ 4403 Op1(_Op1), CRn(_CRn), CRm(_CRm), Op2(_Op2), \ 4404 .visibility = pmu_visibility 4405 4406 /* Macro to expand the PMEVCNTRn register */ 4407 #define PMU_PMEVCNTR(n) \ 4408 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \ 4409 (0b1000 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \ 4410 .access = access_pmu_evcntr } 4411 4412 /* Macro to expand the PMEVTYPERn register */ 4413 #define PMU_PMEVTYPER(n) \ 4414 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \ 4415 (0b1100 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \ 4416 .access = access_pmu_evtyper } 4417 /* 4418 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding, 4419 * depending on the way they are accessed (as a 32bit or a 64bit 4420 * register). 4421 */ 4422 static const struct sys_reg_desc cp15_regs[] = { 4423 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr }, 4424 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, SCTLR_EL1 }, 4425 /* ACTLR */ 4426 { AA32(LO), Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr, NULL, ACTLR_EL1 }, 4427 /* ACTLR2 */ 4428 { AA32(HI), Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr, NULL, ACTLR_EL1 }, 4429 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, 4430 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, TTBR1_EL1 }, 4431 /* TTBCR */ 4432 { AA32(LO), Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 }, 4433 /* TTBCR2 */ 4434 { AA32(HI), Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, TCR_EL1 }, 4435 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, DACR32_EL2 }, 4436 { CP15_SYS_DESC(SYS_ICC_PMR_EL1), undef_access }, 4437 /* DFSR */ 4438 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, ESR_EL1 }, 4439 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, IFSR32_EL2 }, 4440 /* ADFSR */ 4441 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, AFSR0_EL1 }, 4442 /* AIFSR */ 4443 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, AFSR1_EL1 }, 4444 /* DFAR */ 4445 { AA32(LO), Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, FAR_EL1 }, 4446 /* IFAR */ 4447 { AA32(HI), Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, FAR_EL1 }, 4448 4449 /* 4450 * DC{C,I,CI}SW operations: 4451 */ 4452 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw }, 4453 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw }, 4454 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw }, 4455 4456 /* PMU */ 4457 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 0), .access = access_pmcr }, 4458 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 1), .access = access_pmcnten }, 4459 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 2), .access = access_pmcnten }, 4460 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 3), .access = access_pmovs }, 4461 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 4), .access = access_pmswinc }, 4462 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 5), .access = access_pmselr }, 4463 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 6), .access = access_pmceid }, 4464 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 7), .access = access_pmceid }, 4465 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 0), .access = access_pmu_evcntr }, 4466 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 1), .access = access_pmu_evtyper }, 4467 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 2), .access = access_pmu_evcntr }, 4468 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 0), .access = access_pmuserenr }, 4469 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 1), .access = access_pminten }, 4470 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 2), .access = access_pminten }, 4471 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 3), .access = access_pmovs }, 4472 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 4), .access = access_pmceid }, 4473 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 5), .access = access_pmceid }, 4474 /* PMMIR */ 4475 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 6), .access = trap_raz_wi }, 4476 4477 /* PRRR/MAIR0 */ 4478 { AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 }, 4479 /* NMRR/MAIR1 */ 4480 { AA32(HI), Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, MAIR_EL1 }, 4481 /* AMAIR0 */ 4482 { AA32(LO), Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, AMAIR_EL1 }, 4483 /* AMAIR1 */ 4484 { AA32(HI), Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, AMAIR_EL1 }, 4485 4486 { CP15_SYS_DESC(SYS_ICC_IAR0_EL1), undef_access }, 4487 { CP15_SYS_DESC(SYS_ICC_EOIR0_EL1), undef_access }, 4488 { CP15_SYS_DESC(SYS_ICC_HPPIR0_EL1), undef_access }, 4489 { CP15_SYS_DESC(SYS_ICC_BPR0_EL1), undef_access }, 4490 { CP15_SYS_DESC(SYS_ICC_AP0R0_EL1), undef_access }, 4491 { CP15_SYS_DESC(SYS_ICC_AP0R1_EL1), undef_access }, 4492 { CP15_SYS_DESC(SYS_ICC_AP0R2_EL1), undef_access }, 4493 { CP15_SYS_DESC(SYS_ICC_AP0R3_EL1), undef_access }, 4494 { CP15_SYS_DESC(SYS_ICC_AP1R0_EL1), undef_access }, 4495 { CP15_SYS_DESC(SYS_ICC_AP1R1_EL1), undef_access }, 4496 { CP15_SYS_DESC(SYS_ICC_AP1R2_EL1), undef_access }, 4497 { CP15_SYS_DESC(SYS_ICC_AP1R3_EL1), undef_access }, 4498 { CP15_SYS_DESC(SYS_ICC_DIR_EL1), undef_access }, 4499 { CP15_SYS_DESC(SYS_ICC_RPR_EL1), undef_access }, 4500 { CP15_SYS_DESC(SYS_ICC_IAR1_EL1), undef_access }, 4501 { CP15_SYS_DESC(SYS_ICC_EOIR1_EL1), undef_access }, 4502 { CP15_SYS_DESC(SYS_ICC_HPPIR1_EL1), undef_access }, 4503 { CP15_SYS_DESC(SYS_ICC_BPR1_EL1), undef_access }, 4504 { CP15_SYS_DESC(SYS_ICC_CTLR_EL1), undef_access }, 4505 { CP15_SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre }, 4506 { CP15_SYS_DESC(SYS_ICC_IGRPEN0_EL1), undef_access }, 4507 { CP15_SYS_DESC(SYS_ICC_IGRPEN1_EL1), undef_access }, 4508 4509 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, CONTEXTIDR_EL1 }, 4510 4511 /* Arch Tmers */ 4512 { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer }, 4513 { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer }, 4514 4515 /* PMEVCNTRn */ 4516 PMU_PMEVCNTR(0), 4517 PMU_PMEVCNTR(1), 4518 PMU_PMEVCNTR(2), 4519 PMU_PMEVCNTR(3), 4520 PMU_PMEVCNTR(4), 4521 PMU_PMEVCNTR(5), 4522 PMU_PMEVCNTR(6), 4523 PMU_PMEVCNTR(7), 4524 PMU_PMEVCNTR(8), 4525 PMU_PMEVCNTR(9), 4526 PMU_PMEVCNTR(10), 4527 PMU_PMEVCNTR(11), 4528 PMU_PMEVCNTR(12), 4529 PMU_PMEVCNTR(13), 4530 PMU_PMEVCNTR(14), 4531 PMU_PMEVCNTR(15), 4532 PMU_PMEVCNTR(16), 4533 PMU_PMEVCNTR(17), 4534 PMU_PMEVCNTR(18), 4535 PMU_PMEVCNTR(19), 4536 PMU_PMEVCNTR(20), 4537 PMU_PMEVCNTR(21), 4538 PMU_PMEVCNTR(22), 4539 PMU_PMEVCNTR(23), 4540 PMU_PMEVCNTR(24), 4541 PMU_PMEVCNTR(25), 4542 PMU_PMEVCNTR(26), 4543 PMU_PMEVCNTR(27), 4544 PMU_PMEVCNTR(28), 4545 PMU_PMEVCNTR(29), 4546 PMU_PMEVCNTR(30), 4547 /* PMEVTYPERn */ 4548 PMU_PMEVTYPER(0), 4549 PMU_PMEVTYPER(1), 4550 PMU_PMEVTYPER(2), 4551 PMU_PMEVTYPER(3), 4552 PMU_PMEVTYPER(4), 4553 PMU_PMEVTYPER(5), 4554 PMU_PMEVTYPER(6), 4555 PMU_PMEVTYPER(7), 4556 PMU_PMEVTYPER(8), 4557 PMU_PMEVTYPER(9), 4558 PMU_PMEVTYPER(10), 4559 PMU_PMEVTYPER(11), 4560 PMU_PMEVTYPER(12), 4561 PMU_PMEVTYPER(13), 4562 PMU_PMEVTYPER(14), 4563 PMU_PMEVTYPER(15), 4564 PMU_PMEVTYPER(16), 4565 PMU_PMEVTYPER(17), 4566 PMU_PMEVTYPER(18), 4567 PMU_PMEVTYPER(19), 4568 PMU_PMEVTYPER(20), 4569 PMU_PMEVTYPER(21), 4570 PMU_PMEVTYPER(22), 4571 PMU_PMEVTYPER(23), 4572 PMU_PMEVTYPER(24), 4573 PMU_PMEVTYPER(25), 4574 PMU_PMEVTYPER(26), 4575 PMU_PMEVTYPER(27), 4576 PMU_PMEVTYPER(28), 4577 PMU_PMEVTYPER(29), 4578 PMU_PMEVTYPER(30), 4579 /* PMCCFILTR */ 4580 { CP15_PMU_SYS_REG(DIRECT, 0, 14, 15, 7), .access = access_pmu_evtyper }, 4581 4582 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr }, 4583 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr }, 4584 4585 /* CCSIDR2 */ 4586 { Op1(1), CRn( 0), CRm( 0), Op2(2), undef_access }, 4587 4588 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 }, 4589 }; 4590 4591 static const struct sys_reg_desc cp15_64_regs[] = { 4592 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, 4593 { CP15_PMU_SYS_REG(DIRECT, 0, 0, 9, 0), .access = access_pmu_evcntr }, 4594 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */ 4595 { SYS_DESC(SYS_AARCH32_CNTPCT), access_arch_timer }, 4596 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 }, 4597 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */ 4598 { SYS_DESC(SYS_AARCH32_CNTVCT), access_arch_timer }, 4599 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */ 4600 { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer }, 4601 { SYS_DESC(SYS_AARCH32_CNTPCTSS), access_arch_timer }, 4602 { SYS_DESC(SYS_AARCH32_CNTVCTSS), access_arch_timer }, 4603 }; 4604 4605 static bool check_sysreg_table(const struct sys_reg_desc *table, unsigned int n, 4606 bool reset_check) 4607 { 4608 unsigned int i; 4609 4610 for (i = 0; i < n; i++) { 4611 if (reset_check && table[i].reg && !table[i].reset) { 4612 kvm_err("sys_reg table %pS entry %d (%s) lacks reset\n", 4613 &table[i], i, table[i].name); 4614 return false; 4615 } 4616 4617 if (i && cmp_sys_reg(&table[i-1], &table[i]) >= 0) { 4618 kvm_err("sys_reg table %pS entry %d (%s -> %s) out of order\n", 4619 &table[i], i, table[i - 1].name, table[i].name); 4620 return false; 4621 } 4622 } 4623 4624 return true; 4625 } 4626 4627 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu) 4628 { 4629 kvm_inject_undefined(vcpu); 4630 return 1; 4631 } 4632 4633 static void perform_access(struct kvm_vcpu *vcpu, 4634 struct sys_reg_params *params, 4635 const struct sys_reg_desc *r) 4636 { 4637 trace_kvm_sys_access(*vcpu_pc(vcpu), params, r); 4638 4639 /* Check for regs disabled by runtime config */ 4640 if (sysreg_hidden(vcpu, r)) { 4641 kvm_inject_undefined(vcpu); 4642 return; 4643 } 4644 4645 /* 4646 * Not having an accessor means that we have configured a trap 4647 * that we don't know how to handle. This certainly qualifies 4648 * as a gross bug that should be fixed right away. 4649 */ 4650 BUG_ON(!r->access); 4651 4652 /* Skip instruction if instructed so */ 4653 if (likely(r->access(vcpu, params, r))) 4654 kvm_incr_pc(vcpu); 4655 } 4656 4657 /* 4658 * emulate_cp -- tries to match a sys_reg access in a handling table, and 4659 * call the corresponding trap handler. 4660 * 4661 * @params: pointer to the descriptor of the access 4662 * @table: array of trap descriptors 4663 * @num: size of the trap descriptor array 4664 * 4665 * Return true if the access has been handled, false if not. 4666 */ 4667 static bool emulate_cp(struct kvm_vcpu *vcpu, 4668 struct sys_reg_params *params, 4669 const struct sys_reg_desc *table, 4670 size_t num) 4671 { 4672 const struct sys_reg_desc *r; 4673 4674 if (!table) 4675 return false; /* Not handled */ 4676 4677 r = find_reg(params, table, num); 4678 4679 if (r) { 4680 perform_access(vcpu, params, r); 4681 return true; 4682 } 4683 4684 /* Not handled */ 4685 return false; 4686 } 4687 4688 static void unhandled_cp_access(struct kvm_vcpu *vcpu, 4689 struct sys_reg_params *params) 4690 { 4691 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu); 4692 int cp = -1; 4693 4694 switch (esr_ec) { 4695 case ESR_ELx_EC_CP15_32: 4696 case ESR_ELx_EC_CP15_64: 4697 cp = 15; 4698 break; 4699 case ESR_ELx_EC_CP14_MR: 4700 case ESR_ELx_EC_CP14_64: 4701 cp = 14; 4702 break; 4703 default: 4704 WARN_ON(1); 4705 } 4706 4707 print_sys_reg_msg(params, 4708 "Unsupported guest CP%d access at: %08lx [%08lx]\n", 4709 cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 4710 kvm_inject_undefined(vcpu); 4711 } 4712 4713 /** 4714 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access 4715 * @vcpu: The VCPU pointer 4716 * @global: &struct sys_reg_desc 4717 * @nr_global: size of the @global array 4718 */ 4719 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu, 4720 const struct sys_reg_desc *global, 4721 size_t nr_global) 4722 { 4723 struct sys_reg_params params; 4724 u64 esr = kvm_vcpu_get_esr(vcpu); 4725 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4726 int Rt2 = (esr >> 10) & 0x1f; 4727 4728 params.CRm = (esr >> 1) & 0xf; 4729 params.is_write = ((esr & 1) == 0); 4730 4731 params.Op0 = 0; 4732 params.Op1 = (esr >> 16) & 0xf; 4733 params.Op2 = 0; 4734 params.CRn = 0; 4735 4736 /* 4737 * Make a 64-bit value out of Rt and Rt2. As we use the same trap 4738 * backends between AArch32 and AArch64, we get away with it. 4739 */ 4740 if (params.is_write) { 4741 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff; 4742 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32; 4743 } 4744 4745 /* 4746 * If the table contains a handler, handle the 4747 * potential register operation in the case of a read and return 4748 * with success. 4749 */ 4750 if (emulate_cp(vcpu, ¶ms, global, nr_global)) { 4751 /* Split up the value between registers for the read side */ 4752 if (!params.is_write) { 4753 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval)); 4754 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval)); 4755 } 4756 4757 return 1; 4758 } 4759 4760 unhandled_cp_access(vcpu, ¶ms); 4761 return 1; 4762 } 4763 4764 static bool emulate_sys_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *params); 4765 4766 /* 4767 * The CP10 ID registers are architecturally mapped to AArch64 feature 4768 * registers. Abuse that fact so we can rely on the AArch64 handler for accesses 4769 * from AArch32. 4770 */ 4771 static bool kvm_esr_cp10_id_to_sys64(u64 esr, struct sys_reg_params *params) 4772 { 4773 u8 reg_id = (esr >> 10) & 0xf; 4774 bool valid; 4775 4776 params->is_write = ((esr & 1) == 0); 4777 params->Op0 = 3; 4778 params->Op1 = 0; 4779 params->CRn = 0; 4780 params->CRm = 3; 4781 4782 /* CP10 ID registers are read-only */ 4783 valid = !params->is_write; 4784 4785 switch (reg_id) { 4786 /* MVFR0 */ 4787 case 0b0111: 4788 params->Op2 = 0; 4789 break; 4790 /* MVFR1 */ 4791 case 0b0110: 4792 params->Op2 = 1; 4793 break; 4794 /* MVFR2 */ 4795 case 0b0101: 4796 params->Op2 = 2; 4797 break; 4798 default: 4799 valid = false; 4800 } 4801 4802 if (valid) 4803 return true; 4804 4805 kvm_pr_unimpl("Unhandled cp10 register %s: %u\n", 4806 str_write_read(params->is_write), reg_id); 4807 return false; 4808 } 4809 4810 /** 4811 * kvm_handle_cp10_id() - Handles a VMRS trap on guest access to a 'Media and 4812 * VFP Register' from AArch32. 4813 * @vcpu: The vCPU pointer 4814 * 4815 * MVFR{0-2} are architecturally mapped to the AArch64 MVFR{0-2}_EL1 registers. 4816 * Work out the correct AArch64 system register encoding and reroute to the 4817 * AArch64 system register emulation. 4818 */ 4819 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu) 4820 { 4821 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4822 u64 esr = kvm_vcpu_get_esr(vcpu); 4823 struct sys_reg_params params; 4824 4825 /* UNDEF on any unhandled register access */ 4826 if (!kvm_esr_cp10_id_to_sys64(esr, ¶ms)) { 4827 kvm_inject_undefined(vcpu); 4828 return 1; 4829 } 4830 4831 if (emulate_sys_reg(vcpu, ¶ms)) 4832 vcpu_set_reg(vcpu, Rt, params.regval); 4833 4834 return 1; 4835 } 4836 4837 /** 4838 * kvm_emulate_cp15_id_reg() - Handles an MRC trap on a guest CP15 access where 4839 * CRn=0, which corresponds to the AArch32 feature 4840 * registers. 4841 * @vcpu: the vCPU pointer 4842 * @params: the system register access parameters. 4843 * 4844 * Our cp15 system register tables do not enumerate the AArch32 feature 4845 * registers. Conveniently, our AArch64 table does, and the AArch32 system 4846 * register encoding can be trivially remapped into the AArch64 for the feature 4847 * registers: Append op0=3, leaving op1, CRn, CRm, and op2 the same. 4848 * 4849 * According to DDI0487G.b G7.3.1, paragraph "Behavior of VMSAv8-32 32-bit 4850 * System registers with (coproc=0b1111, CRn==c0)", read accesses from this 4851 * range are either UNKNOWN or RES0. Rerouting remains architectural as we 4852 * treat undefined registers in this range as RAZ. 4853 */ 4854 static int kvm_emulate_cp15_id_reg(struct kvm_vcpu *vcpu, 4855 struct sys_reg_params *params) 4856 { 4857 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4858 4859 /* Treat impossible writes to RO registers as UNDEFINED */ 4860 if (params->is_write) { 4861 unhandled_cp_access(vcpu, params); 4862 return 1; 4863 } 4864 4865 params->Op0 = 3; 4866 4867 /* 4868 * All registers where CRm > 3 are known to be UNKNOWN/RAZ from AArch32. 4869 * Avoid conflicting with future expansion of AArch64 feature registers 4870 * and simply treat them as RAZ here. 4871 */ 4872 if (params->CRm > 3) 4873 params->regval = 0; 4874 else if (!emulate_sys_reg(vcpu, params)) 4875 return 1; 4876 4877 vcpu_set_reg(vcpu, Rt, params->regval); 4878 return 1; 4879 } 4880 4881 /** 4882 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access 4883 * @vcpu: The VCPU pointer 4884 * @params: &struct sys_reg_params 4885 * @global: &struct sys_reg_desc 4886 * @nr_global: size of the @global array 4887 */ 4888 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu, 4889 struct sys_reg_params *params, 4890 const struct sys_reg_desc *global, 4891 size_t nr_global) 4892 { 4893 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4894 4895 params->regval = vcpu_get_reg(vcpu, Rt); 4896 4897 if (emulate_cp(vcpu, params, global, nr_global)) { 4898 if (!params->is_write) 4899 vcpu_set_reg(vcpu, Rt, params->regval); 4900 return 1; 4901 } 4902 4903 unhandled_cp_access(vcpu, params); 4904 return 1; 4905 } 4906 4907 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu) 4908 { 4909 return kvm_handle_cp_64(vcpu, cp15_64_regs, ARRAY_SIZE(cp15_64_regs)); 4910 } 4911 4912 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu) 4913 { 4914 struct sys_reg_params params; 4915 4916 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu)); 4917 4918 /* 4919 * Certain AArch32 ID registers are handled by rerouting to the AArch64 4920 * system register table. Registers in the ID range where CRm=0 are 4921 * excluded from this scheme as they do not trivially map into AArch64 4922 * system register encodings, except for AIDR/REVIDR. 4923 */ 4924 if (params.Op1 == 0 && params.CRn == 0 && 4925 (params.CRm || params.Op2 == 6 /* REVIDR */)) 4926 return kvm_emulate_cp15_id_reg(vcpu, ¶ms); 4927 if (params.Op1 == 1 && params.CRn == 0 && 4928 params.CRm == 0 && params.Op2 == 7 /* AIDR */) 4929 return kvm_emulate_cp15_id_reg(vcpu, ¶ms); 4930 4931 return kvm_handle_cp_32(vcpu, ¶ms, cp15_regs, ARRAY_SIZE(cp15_regs)); 4932 } 4933 4934 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu) 4935 { 4936 return kvm_handle_cp_64(vcpu, cp14_64_regs, ARRAY_SIZE(cp14_64_regs)); 4937 } 4938 4939 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu) 4940 { 4941 struct sys_reg_params params; 4942 4943 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu)); 4944 4945 return kvm_handle_cp_32(vcpu, ¶ms, cp14_regs, ARRAY_SIZE(cp14_regs)); 4946 } 4947 4948 /** 4949 * emulate_sys_reg - Emulate a guest access to an AArch64 system register 4950 * @vcpu: The VCPU pointer 4951 * @params: Decoded system register parameters 4952 * 4953 * Return: true if the system register access was successful, false otherwise. 4954 */ 4955 static bool emulate_sys_reg(struct kvm_vcpu *vcpu, 4956 struct sys_reg_params *params) 4957 { 4958 const struct sys_reg_desc *r; 4959 4960 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 4961 if (likely(r)) { 4962 perform_access(vcpu, params, r); 4963 return true; 4964 } 4965 4966 print_sys_reg_msg(params, 4967 "Unsupported guest sys_reg access at: %lx [%08lx]\n", 4968 *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 4969 kvm_inject_undefined(vcpu); 4970 4971 return false; 4972 } 4973 4974 static const struct sys_reg_desc *idregs_debug_find(struct kvm *kvm, u8 pos) 4975 { 4976 unsigned long i, idreg_idx = 0; 4977 4978 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { 4979 const struct sys_reg_desc *r = &sys_reg_descs[i]; 4980 4981 if (!is_vm_ftr_id_reg(reg_to_encoding(r))) 4982 continue; 4983 4984 if (idreg_idx == pos) 4985 return r; 4986 4987 idreg_idx++; 4988 } 4989 4990 return NULL; 4991 } 4992 4993 static void *idregs_debug_start(struct seq_file *s, loff_t *pos) 4994 { 4995 struct kvm *kvm = s->private; 4996 u8 *iter; 4997 4998 mutex_lock(&kvm->arch.config_lock); 4999 5000 iter = &kvm->arch.idreg_debugfs_iter; 5001 if (test_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags) && 5002 *iter == (u8)~0) { 5003 *iter = *pos; 5004 if (!idregs_debug_find(kvm, *iter)) 5005 iter = NULL; 5006 } else { 5007 iter = ERR_PTR(-EBUSY); 5008 } 5009 5010 mutex_unlock(&kvm->arch.config_lock); 5011 5012 return iter; 5013 } 5014 5015 static void *idregs_debug_next(struct seq_file *s, void *v, loff_t *pos) 5016 { 5017 struct kvm *kvm = s->private; 5018 5019 (*pos)++; 5020 5021 if (idregs_debug_find(kvm, kvm->arch.idreg_debugfs_iter + 1)) { 5022 kvm->arch.idreg_debugfs_iter++; 5023 5024 return &kvm->arch.idreg_debugfs_iter; 5025 } 5026 5027 return NULL; 5028 } 5029 5030 static void idregs_debug_stop(struct seq_file *s, void *v) 5031 { 5032 struct kvm *kvm = s->private; 5033 5034 if (IS_ERR(v)) 5035 return; 5036 5037 mutex_lock(&kvm->arch.config_lock); 5038 5039 kvm->arch.idreg_debugfs_iter = ~0; 5040 5041 mutex_unlock(&kvm->arch.config_lock); 5042 } 5043 5044 static int idregs_debug_show(struct seq_file *s, void *v) 5045 { 5046 const struct sys_reg_desc *desc; 5047 struct kvm *kvm = s->private; 5048 5049 desc = idregs_debug_find(kvm, kvm->arch.idreg_debugfs_iter); 5050 5051 if (!desc->name) 5052 return 0; 5053 5054 seq_printf(s, "%20s:\t%016llx\n", 5055 desc->name, kvm_read_vm_id_reg(kvm, reg_to_encoding(desc))); 5056 5057 return 0; 5058 } 5059 5060 static const struct seq_operations idregs_debug_sops = { 5061 .start = idregs_debug_start, 5062 .next = idregs_debug_next, 5063 .stop = idregs_debug_stop, 5064 .show = idregs_debug_show, 5065 }; 5066 5067 DEFINE_SEQ_ATTRIBUTE(idregs_debug); 5068 5069 void kvm_sys_regs_create_debugfs(struct kvm *kvm) 5070 { 5071 kvm->arch.idreg_debugfs_iter = ~0; 5072 5073 debugfs_create_file("idregs", 0444, kvm->debugfs_dentry, kvm, 5074 &idregs_debug_fops); 5075 } 5076 5077 static void reset_vm_ftr_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *reg) 5078 { 5079 u32 id = reg_to_encoding(reg); 5080 struct kvm *kvm = vcpu->kvm; 5081 5082 if (test_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags)) 5083 return; 5084 5085 kvm_set_vm_id_reg(kvm, id, reg->reset(vcpu, reg)); 5086 } 5087 5088 static void reset_vcpu_ftr_id_reg(struct kvm_vcpu *vcpu, 5089 const struct sys_reg_desc *reg) 5090 { 5091 if (kvm_vcpu_initialized(vcpu)) 5092 return; 5093 5094 reg->reset(vcpu, reg); 5095 } 5096 5097 /** 5098 * kvm_reset_sys_regs - sets system registers to reset value 5099 * @vcpu: The VCPU pointer 5100 * 5101 * This function finds the right table above and sets the registers on the 5102 * virtual CPU struct to their architecturally defined reset values. 5103 */ 5104 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu) 5105 { 5106 struct kvm *kvm = vcpu->kvm; 5107 unsigned long i; 5108 5109 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { 5110 const struct sys_reg_desc *r = &sys_reg_descs[i]; 5111 5112 if (!r->reset) 5113 continue; 5114 5115 if (is_vm_ftr_id_reg(reg_to_encoding(r))) 5116 reset_vm_ftr_id_reg(vcpu, r); 5117 else if (is_vcpu_ftr_id_reg(reg_to_encoding(r))) 5118 reset_vcpu_ftr_id_reg(vcpu, r); 5119 else 5120 r->reset(vcpu, r); 5121 5122 if (r->reg >= __SANITISED_REG_START__ && r->reg < NR_SYS_REGS) 5123 __vcpu_rmw_sys_reg(vcpu, r->reg, |=, 0); 5124 } 5125 5126 set_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags); 5127 5128 if (kvm_vcpu_has_pmu(vcpu)) 5129 kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu); 5130 } 5131 5132 /** 5133 * kvm_handle_sys_reg -- handles a system instruction or mrs/msr instruction 5134 * trap on a guest execution 5135 * @vcpu: The VCPU pointer 5136 */ 5137 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu) 5138 { 5139 const struct sys_reg_desc *desc = NULL; 5140 struct sys_reg_params params; 5141 unsigned long esr = kvm_vcpu_get_esr(vcpu); 5142 int Rt = kvm_vcpu_sys_get_rt(vcpu); 5143 int sr_idx; 5144 5145 trace_kvm_handle_sys_reg(esr); 5146 5147 if (triage_sysreg_trap(vcpu, &sr_idx)) 5148 return 1; 5149 5150 params = esr_sys64_to_params(esr); 5151 params.regval = vcpu_get_reg(vcpu, Rt); 5152 5153 /* System registers have Op0=={2,3}, as per DDI487 J.a C5.1.2 */ 5154 if (params.Op0 == 2 || params.Op0 == 3) 5155 desc = &sys_reg_descs[sr_idx]; 5156 else 5157 desc = &sys_insn_descs[sr_idx]; 5158 5159 perform_access(vcpu, ¶ms, desc); 5160 5161 /* Read from system register? */ 5162 if (!params.is_write && 5163 (params.Op0 == 2 || params.Op0 == 3)) 5164 vcpu_set_reg(vcpu, Rt, params.regval); 5165 5166 return 1; 5167 } 5168 5169 /****************************************************************************** 5170 * Userspace API 5171 *****************************************************************************/ 5172 5173 static bool index_to_params(u64 id, struct sys_reg_params *params) 5174 { 5175 switch (id & KVM_REG_SIZE_MASK) { 5176 case KVM_REG_SIZE_U64: 5177 /* Any unused index bits means it's not valid. */ 5178 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK 5179 | KVM_REG_ARM_COPROC_MASK 5180 | KVM_REG_ARM64_SYSREG_OP0_MASK 5181 | KVM_REG_ARM64_SYSREG_OP1_MASK 5182 | KVM_REG_ARM64_SYSREG_CRN_MASK 5183 | KVM_REG_ARM64_SYSREG_CRM_MASK 5184 | KVM_REG_ARM64_SYSREG_OP2_MASK)) 5185 return false; 5186 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK) 5187 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT); 5188 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK) 5189 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT); 5190 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK) 5191 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT); 5192 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK) 5193 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT); 5194 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK) 5195 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT); 5196 return true; 5197 default: 5198 return false; 5199 } 5200 } 5201 5202 const struct sys_reg_desc *get_reg_by_id(u64 id, 5203 const struct sys_reg_desc table[], 5204 unsigned int num) 5205 { 5206 struct sys_reg_params params; 5207 5208 if (!index_to_params(id, ¶ms)) 5209 return NULL; 5210 5211 return find_reg(¶ms, table, num); 5212 } 5213 5214 /* Decode an index value, and find the sys_reg_desc entry. */ 5215 static const struct sys_reg_desc * 5216 id_to_sys_reg_desc(struct kvm_vcpu *vcpu, u64 id, 5217 const struct sys_reg_desc table[], unsigned int num) 5218 5219 { 5220 const struct sys_reg_desc *r; 5221 5222 /* We only do sys_reg for now. */ 5223 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG) 5224 return NULL; 5225 5226 r = get_reg_by_id(id, table, num); 5227 5228 /* Not saved in the sys_reg array and not otherwise accessible? */ 5229 if (r && (!(r->reg || r->get_user) || sysreg_hidden(vcpu, r))) 5230 r = NULL; 5231 5232 return r; 5233 } 5234 5235 static int demux_c15_get(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) 5236 { 5237 u32 val; 5238 u32 __user *uval = uaddr; 5239 5240 /* Fail if we have unknown bits set. */ 5241 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 5242 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 5243 return -ENOENT; 5244 5245 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 5246 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 5247 if (KVM_REG_SIZE(id) != 4) 5248 return -ENOENT; 5249 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 5250 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 5251 if (val >= CSSELR_MAX) 5252 return -ENOENT; 5253 5254 return put_user(get_ccsidr(vcpu, val), uval); 5255 default: 5256 return -ENOENT; 5257 } 5258 } 5259 5260 static int demux_c15_set(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) 5261 { 5262 u32 val, newval; 5263 u32 __user *uval = uaddr; 5264 5265 /* Fail if we have unknown bits set. */ 5266 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 5267 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 5268 return -ENOENT; 5269 5270 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 5271 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 5272 if (KVM_REG_SIZE(id) != 4) 5273 return -ENOENT; 5274 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 5275 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 5276 if (val >= CSSELR_MAX) 5277 return -ENOENT; 5278 5279 if (get_user(newval, uval)) 5280 return -EFAULT; 5281 5282 return set_ccsidr(vcpu, val, newval); 5283 default: 5284 return -ENOENT; 5285 } 5286 } 5287 5288 static u64 kvm_one_reg_to_id(const struct kvm_one_reg *reg) 5289 { 5290 switch(reg->id) { 5291 case KVM_REG_ARM_TIMER_CVAL: 5292 return TO_ARM64_SYS_REG(CNTV_CVAL_EL0); 5293 case KVM_REG_ARM_TIMER_CNT: 5294 return TO_ARM64_SYS_REG(CNTVCT_EL0); 5295 default: 5296 return reg->id; 5297 } 5298 } 5299 5300 int kvm_sys_reg_get_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg, 5301 const struct sys_reg_desc table[], unsigned int num) 5302 { 5303 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr; 5304 const struct sys_reg_desc *r; 5305 u64 id = kvm_one_reg_to_id(reg); 5306 u64 val; 5307 int ret; 5308 5309 r = id_to_sys_reg_desc(vcpu, id, table, num); 5310 if (!r || sysreg_hidden(vcpu, r)) 5311 return -ENOENT; 5312 5313 if (r->get_user) { 5314 ret = (r->get_user)(vcpu, r, &val); 5315 } else { 5316 val = __vcpu_sys_reg(vcpu, r->reg); 5317 ret = 0; 5318 } 5319 5320 if (!ret) 5321 ret = put_user(val, uaddr); 5322 5323 return ret; 5324 } 5325 5326 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 5327 { 5328 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 5329 5330 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 5331 return demux_c15_get(vcpu, reg->id, uaddr); 5332 5333 return kvm_sys_reg_get_user(vcpu, reg, 5334 sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 5335 } 5336 5337 int kvm_sys_reg_set_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg, 5338 const struct sys_reg_desc table[], unsigned int num) 5339 { 5340 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr; 5341 const struct sys_reg_desc *r; 5342 u64 id = kvm_one_reg_to_id(reg); 5343 u64 val; 5344 int ret; 5345 5346 if (get_user(val, uaddr)) 5347 return -EFAULT; 5348 5349 r = id_to_sys_reg_desc(vcpu, id, table, num); 5350 if (!r || sysreg_hidden(vcpu, r)) 5351 return -ENOENT; 5352 5353 if (sysreg_user_write_ignore(vcpu, r)) 5354 return 0; 5355 5356 if (r->set_user) { 5357 ret = (r->set_user)(vcpu, r, val); 5358 } else { 5359 __vcpu_assign_sys_reg(vcpu, r->reg, val); 5360 ret = 0; 5361 } 5362 5363 return ret; 5364 } 5365 5366 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 5367 { 5368 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 5369 5370 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 5371 return demux_c15_set(vcpu, reg->id, uaddr); 5372 5373 return kvm_sys_reg_set_user(vcpu, reg, 5374 sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 5375 } 5376 5377 static unsigned int num_demux_regs(void) 5378 { 5379 return CSSELR_MAX; 5380 } 5381 5382 static int write_demux_regids(u64 __user *uindices) 5383 { 5384 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX; 5385 unsigned int i; 5386 5387 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR; 5388 for (i = 0; i < CSSELR_MAX; i++) { 5389 if (put_user(val | i, uindices)) 5390 return -EFAULT; 5391 uindices++; 5392 } 5393 return 0; 5394 } 5395 5396 static u64 sys_reg_to_index(const struct sys_reg_desc *reg) 5397 { 5398 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | 5399 KVM_REG_ARM64_SYSREG | 5400 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) | 5401 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) | 5402 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) | 5403 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) | 5404 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT)); 5405 } 5406 5407 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind) 5408 { 5409 u64 idx; 5410 5411 if (!*uind) 5412 return true; 5413 5414 switch (reg_to_encoding(reg)) { 5415 case SYS_CNTV_CVAL_EL0: 5416 idx = KVM_REG_ARM_TIMER_CVAL; 5417 break; 5418 case SYS_CNTVCT_EL0: 5419 idx = KVM_REG_ARM_TIMER_CNT; 5420 break; 5421 default: 5422 idx = sys_reg_to_index(reg); 5423 } 5424 5425 if (put_user(idx, *uind)) 5426 return false; 5427 5428 (*uind)++; 5429 return true; 5430 } 5431 5432 static int walk_one_sys_reg(const struct kvm_vcpu *vcpu, 5433 const struct sys_reg_desc *rd, 5434 u64 __user **uind, 5435 unsigned int *total) 5436 { 5437 /* 5438 * Ignore registers we trap but don't save, 5439 * and for which no custom user accessor is provided. 5440 */ 5441 if (!(rd->reg || rd->get_user)) 5442 return 0; 5443 5444 if (sysreg_hidden(vcpu, rd)) 5445 return 0; 5446 5447 if (!copy_reg_to_user(rd, uind)) 5448 return -EFAULT; 5449 5450 (*total)++; 5451 return 0; 5452 } 5453 5454 /* Assumed ordered tables, see kvm_sys_reg_table_init. */ 5455 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind) 5456 { 5457 const struct sys_reg_desc *i2, *end2; 5458 unsigned int total = 0; 5459 int err; 5460 5461 i2 = sys_reg_descs; 5462 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs); 5463 5464 while (i2 != end2) { 5465 err = walk_one_sys_reg(vcpu, i2++, &uind, &total); 5466 if (err) 5467 return err; 5468 } 5469 return total; 5470 } 5471 5472 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu) 5473 { 5474 return num_demux_regs() 5475 + walk_sys_regs(vcpu, (u64 __user *)NULL); 5476 } 5477 5478 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) 5479 { 5480 int err; 5481 5482 err = walk_sys_regs(vcpu, uindices); 5483 if (err < 0) 5484 return err; 5485 uindices += err; 5486 5487 return write_demux_regids(uindices); 5488 } 5489 5490 #define KVM_ARM_FEATURE_ID_RANGE_INDEX(r) \ 5491 KVM_ARM_FEATURE_ID_RANGE_IDX(sys_reg_Op0(r), \ 5492 sys_reg_Op1(r), \ 5493 sys_reg_CRn(r), \ 5494 sys_reg_CRm(r), \ 5495 sys_reg_Op2(r)) 5496 5497 int kvm_vm_ioctl_get_reg_writable_masks(struct kvm *kvm, struct reg_mask_range *range) 5498 { 5499 const void *zero_page = page_to_virt(ZERO_PAGE(0)); 5500 u64 __user *masks = (u64 __user *)range->addr; 5501 5502 /* Only feature id range is supported, reserved[13] must be zero. */ 5503 if (range->range || 5504 memcmp(range->reserved, zero_page, sizeof(range->reserved))) 5505 return -EINVAL; 5506 5507 /* Wipe the whole thing first */ 5508 if (clear_user(masks, KVM_ARM_FEATURE_ID_RANGE_SIZE * sizeof(__u64))) 5509 return -EFAULT; 5510 5511 for (int i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { 5512 const struct sys_reg_desc *reg = &sys_reg_descs[i]; 5513 u32 encoding = reg_to_encoding(reg); 5514 u64 val; 5515 5516 if (!is_feature_id_reg(encoding) || !reg->set_user) 5517 continue; 5518 5519 if (!reg->val || 5520 (is_aa32_id_reg(encoding) && !kvm_supports_32bit_el0())) { 5521 continue; 5522 } 5523 val = reg->val; 5524 5525 if (put_user(val, (masks + KVM_ARM_FEATURE_ID_RANGE_INDEX(encoding)))) 5526 return -EFAULT; 5527 } 5528 5529 return 0; 5530 } 5531 5532 static void vcpu_set_hcr(struct kvm_vcpu *vcpu) 5533 { 5534 struct kvm *kvm = vcpu->kvm; 5535 5536 if (has_vhe() || has_hvhe()) 5537 vcpu->arch.hcr_el2 |= HCR_E2H; 5538 if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN)) { 5539 /* route synchronous external abort exceptions to EL2 */ 5540 vcpu->arch.hcr_el2 |= HCR_TEA; 5541 /* trap error record accesses */ 5542 vcpu->arch.hcr_el2 |= HCR_TERR; 5543 } 5544 5545 if (cpus_have_final_cap(ARM64_HAS_STAGE2_FWB)) 5546 vcpu->arch.hcr_el2 |= HCR_FWB; 5547 5548 if (cpus_have_final_cap(ARM64_HAS_EVT) && 5549 !cpus_have_final_cap(ARM64_MISMATCHED_CACHE_TYPE) && 5550 kvm_read_vm_id_reg(kvm, SYS_CTR_EL0) == read_sanitised_ftr_reg(SYS_CTR_EL0)) 5551 vcpu->arch.hcr_el2 |= HCR_TID4; 5552 else 5553 vcpu->arch.hcr_el2 |= HCR_TID2; 5554 5555 if (vcpu_el1_is_32bit(vcpu)) 5556 vcpu->arch.hcr_el2 &= ~HCR_RW; 5557 5558 if (kvm_has_mte(vcpu->kvm)) 5559 vcpu->arch.hcr_el2 |= HCR_ATA; 5560 5561 /* 5562 * In the absence of FGT, we cannot independently trap TLBI 5563 * Range instructions. This isn't great, but trapping all 5564 * TLBIs would be far worse. Live with it... 5565 */ 5566 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 5567 vcpu->arch.hcr_el2 |= HCR_TTLBOS; 5568 } 5569 5570 void kvm_calculate_traps(struct kvm_vcpu *vcpu) 5571 { 5572 struct kvm *kvm = vcpu->kvm; 5573 5574 mutex_lock(&kvm->arch.config_lock); 5575 vcpu_set_hcr(vcpu); 5576 vcpu_set_ich_hcr(vcpu); 5577 vcpu_set_hcrx(vcpu); 5578 5579 if (test_bit(KVM_ARCH_FLAG_FGU_INITIALIZED, &kvm->arch.flags)) 5580 goto out; 5581 5582 compute_fgu(kvm, HFGRTR_GROUP); 5583 compute_fgu(kvm, HFGITR_GROUP); 5584 compute_fgu(kvm, HDFGRTR_GROUP); 5585 compute_fgu(kvm, HAFGRTR_GROUP); 5586 compute_fgu(kvm, HFGRTR2_GROUP); 5587 compute_fgu(kvm, HFGITR2_GROUP); 5588 compute_fgu(kvm, HDFGRTR2_GROUP); 5589 5590 set_bit(KVM_ARCH_FLAG_FGU_INITIALIZED, &kvm->arch.flags); 5591 out: 5592 mutex_unlock(&kvm->arch.config_lock); 5593 } 5594 5595 /* 5596 * Perform last adjustments to the ID registers that are implied by the 5597 * configuration outside of the ID regs themselves, as well as any 5598 * initialisation that directly depend on these ID registers (such as 5599 * RES0/RES1 behaviours). This is not the place to configure traps though. 5600 * 5601 * Because this can be called once per CPU, changes must be idempotent. 5602 */ 5603 int kvm_finalize_sys_regs(struct kvm_vcpu *vcpu) 5604 { 5605 struct kvm *kvm = vcpu->kvm; 5606 5607 guard(mutex)(&kvm->arch.config_lock); 5608 5609 if (!(static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif) && 5610 irqchip_in_kernel(kvm) && 5611 kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3)) { 5612 kvm->arch.id_regs[IDREG_IDX(SYS_ID_AA64PFR0_EL1)] &= ~ID_AA64PFR0_EL1_GIC_MASK; 5613 kvm->arch.id_regs[IDREG_IDX(SYS_ID_PFR1_EL1)] &= ~ID_PFR1_EL1_GIC_MASK; 5614 } 5615 5616 if (vcpu_has_nv(vcpu)) { 5617 int ret = kvm_init_nv_sysregs(vcpu); 5618 if (ret) 5619 return ret; 5620 } 5621 5622 return 0; 5623 } 5624 5625 int __init kvm_sys_reg_table_init(void) 5626 { 5627 const struct sys_reg_desc *gicv3_regs; 5628 bool valid = true; 5629 unsigned int i, sz; 5630 int ret = 0; 5631 5632 /* Make sure tables are unique and in order. */ 5633 valid &= check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), true); 5634 valid &= check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), false); 5635 valid &= check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), false); 5636 valid &= check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), false); 5637 valid &= check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), false); 5638 valid &= check_sysreg_table(sys_insn_descs, ARRAY_SIZE(sys_insn_descs), false); 5639 5640 gicv3_regs = vgic_v3_get_sysreg_table(&sz); 5641 valid &= check_sysreg_table(gicv3_regs, sz, false); 5642 5643 if (!valid) 5644 return -EINVAL; 5645 5646 init_imp_id_regs(); 5647 5648 ret = populate_nv_trap_config(); 5649 5650 check_feature_map(); 5651 5652 for (i = 0; !ret && i < ARRAY_SIZE(sys_reg_descs); i++) 5653 ret = populate_sysreg_config(sys_reg_descs + i, i); 5654 5655 for (i = 0; !ret && i < ARRAY_SIZE(sys_insn_descs); i++) 5656 ret = populate_sysreg_config(sys_insn_descs + i, i); 5657 5658 return ret; 5659 } 5660