1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/kvm/coproc.c: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Authors: Rusty Russell <rusty@rustcorp.com.au> 9 * Christoffer Dall <c.dall@virtualopensystems.com> 10 */ 11 12 #include <linux/bitfield.h> 13 #include <linux/bsearch.h> 14 #include <linux/cacheinfo.h> 15 #include <linux/debugfs.h> 16 #include <linux/kvm_host.h> 17 #include <linux/mm.h> 18 #include <linux/printk.h> 19 #include <linux/uaccess.h> 20 21 #include <asm/arm_pmuv3.h> 22 #include <asm/cacheflush.h> 23 #include <asm/cputype.h> 24 #include <asm/debug-monitors.h> 25 #include <asm/esr.h> 26 #include <asm/kvm_arm.h> 27 #include <asm/kvm_emulate.h> 28 #include <asm/kvm_hyp.h> 29 #include <asm/kvm_mmu.h> 30 #include <asm/kvm_nested.h> 31 #include <asm/perf_event.h> 32 #include <asm/sysreg.h> 33 34 #include <trace/events/kvm.h> 35 36 #include "sys_regs.h" 37 #include "vgic/vgic.h" 38 39 #include "trace.h" 40 41 /* 42 * For AArch32, we only take care of what is being trapped. Anything 43 * that has to do with init and userspace access has to go via the 44 * 64bit interface. 45 */ 46 47 static u64 sys_reg_to_index(const struct sys_reg_desc *reg); 48 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 49 u64 val); 50 51 static bool undef_access(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 52 const struct sys_reg_desc *r) 53 { 54 kvm_inject_undefined(vcpu); 55 return false; 56 } 57 58 static bool bad_trap(struct kvm_vcpu *vcpu, 59 struct sys_reg_params *params, 60 const struct sys_reg_desc *r, 61 const char *msg) 62 { 63 WARN_ONCE(1, "Unexpected %s\n", msg); 64 print_sys_reg_instr(params); 65 return undef_access(vcpu, params, r); 66 } 67 68 static bool read_from_write_only(struct kvm_vcpu *vcpu, 69 struct sys_reg_params *params, 70 const struct sys_reg_desc *r) 71 { 72 return bad_trap(vcpu, params, r, 73 "sys_reg read to write-only register"); 74 } 75 76 static bool write_to_read_only(struct kvm_vcpu *vcpu, 77 struct sys_reg_params *params, 78 const struct sys_reg_desc *r) 79 { 80 return bad_trap(vcpu, params, r, 81 "sys_reg write to read-only register"); 82 } 83 84 #define PURE_EL2_SYSREG(el2) \ 85 case el2: { \ 86 *el1r = el2; \ 87 return true; \ 88 } 89 90 #define MAPPED_EL2_SYSREG(el2, el1, fn) \ 91 case el2: { \ 92 *xlate = fn; \ 93 *el1r = el1; \ 94 return true; \ 95 } 96 97 static bool get_el2_to_el1_mapping(unsigned int reg, 98 unsigned int *el1r, u64 (**xlate)(u64)) 99 { 100 switch (reg) { 101 PURE_EL2_SYSREG( VPIDR_EL2 ); 102 PURE_EL2_SYSREG( VMPIDR_EL2 ); 103 PURE_EL2_SYSREG( ACTLR_EL2 ); 104 PURE_EL2_SYSREG( HCR_EL2 ); 105 PURE_EL2_SYSREG( MDCR_EL2 ); 106 PURE_EL2_SYSREG( HSTR_EL2 ); 107 PURE_EL2_SYSREG( HACR_EL2 ); 108 PURE_EL2_SYSREG( VTTBR_EL2 ); 109 PURE_EL2_SYSREG( VTCR_EL2 ); 110 PURE_EL2_SYSREG( RVBAR_EL2 ); 111 PURE_EL2_SYSREG( TPIDR_EL2 ); 112 PURE_EL2_SYSREG( HPFAR_EL2 ); 113 PURE_EL2_SYSREG( HCRX_EL2 ); 114 PURE_EL2_SYSREG( HFGRTR_EL2 ); 115 PURE_EL2_SYSREG( HFGWTR_EL2 ); 116 PURE_EL2_SYSREG( HFGITR_EL2 ); 117 PURE_EL2_SYSREG( HDFGRTR_EL2 ); 118 PURE_EL2_SYSREG( HDFGWTR_EL2 ); 119 PURE_EL2_SYSREG( HAFGRTR_EL2 ); 120 PURE_EL2_SYSREG( CNTVOFF_EL2 ); 121 PURE_EL2_SYSREG( CNTHCTL_EL2 ); 122 MAPPED_EL2_SYSREG(SCTLR_EL2, SCTLR_EL1, 123 translate_sctlr_el2_to_sctlr_el1 ); 124 MAPPED_EL2_SYSREG(CPTR_EL2, CPACR_EL1, 125 translate_cptr_el2_to_cpacr_el1 ); 126 MAPPED_EL2_SYSREG(TTBR0_EL2, TTBR0_EL1, 127 translate_ttbr0_el2_to_ttbr0_el1 ); 128 MAPPED_EL2_SYSREG(TTBR1_EL2, TTBR1_EL1, NULL ); 129 MAPPED_EL2_SYSREG(TCR_EL2, TCR_EL1, 130 translate_tcr_el2_to_tcr_el1 ); 131 MAPPED_EL2_SYSREG(VBAR_EL2, VBAR_EL1, NULL ); 132 MAPPED_EL2_SYSREG(AFSR0_EL2, AFSR0_EL1, NULL ); 133 MAPPED_EL2_SYSREG(AFSR1_EL2, AFSR1_EL1, NULL ); 134 MAPPED_EL2_SYSREG(ESR_EL2, ESR_EL1, NULL ); 135 MAPPED_EL2_SYSREG(FAR_EL2, FAR_EL1, NULL ); 136 MAPPED_EL2_SYSREG(MAIR_EL2, MAIR_EL1, NULL ); 137 MAPPED_EL2_SYSREG(TCR2_EL2, TCR2_EL1, NULL ); 138 MAPPED_EL2_SYSREG(PIR_EL2, PIR_EL1, NULL ); 139 MAPPED_EL2_SYSREG(PIRE0_EL2, PIRE0_EL1, NULL ); 140 MAPPED_EL2_SYSREG(POR_EL2, POR_EL1, NULL ); 141 MAPPED_EL2_SYSREG(AMAIR_EL2, AMAIR_EL1, NULL ); 142 MAPPED_EL2_SYSREG(ELR_EL2, ELR_EL1, NULL ); 143 MAPPED_EL2_SYSREG(SPSR_EL2, SPSR_EL1, NULL ); 144 MAPPED_EL2_SYSREG(ZCR_EL2, ZCR_EL1, NULL ); 145 MAPPED_EL2_SYSREG(CONTEXTIDR_EL2, CONTEXTIDR_EL1, NULL ); 146 default: 147 return false; 148 } 149 } 150 151 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg) 152 { 153 u64 val = 0x8badf00d8badf00d; 154 u64 (*xlate)(u64) = NULL; 155 unsigned int el1r; 156 157 if (!vcpu_get_flag(vcpu, SYSREGS_ON_CPU)) 158 goto memory_read; 159 160 if (unlikely(get_el2_to_el1_mapping(reg, &el1r, &xlate))) { 161 if (!is_hyp_ctxt(vcpu)) 162 goto memory_read; 163 164 /* 165 * CNTHCTL_EL2 requires some special treatment to 166 * account for the bits that can be set via CNTKCTL_EL1. 167 */ 168 switch (reg) { 169 case CNTHCTL_EL2: 170 if (vcpu_el2_e2h_is_set(vcpu)) { 171 val = read_sysreg_el1(SYS_CNTKCTL); 172 val &= CNTKCTL_VALID_BITS; 173 val |= __vcpu_sys_reg(vcpu, reg) & ~CNTKCTL_VALID_BITS; 174 return val; 175 } 176 break; 177 } 178 179 /* 180 * If this register does not have an EL1 counterpart, 181 * then read the stored EL2 version. 182 */ 183 if (reg == el1r) 184 goto memory_read; 185 186 /* 187 * If we have a non-VHE guest and that the sysreg 188 * requires translation to be used at EL1, use the 189 * in-memory copy instead. 190 */ 191 if (!vcpu_el2_e2h_is_set(vcpu) && xlate) 192 goto memory_read; 193 194 /* Get the current version of the EL1 counterpart. */ 195 WARN_ON(!__vcpu_read_sys_reg_from_cpu(el1r, &val)); 196 if (reg >= __SANITISED_REG_START__) 197 val = kvm_vcpu_apply_reg_masks(vcpu, reg, val); 198 199 return val; 200 } 201 202 /* EL1 register can't be on the CPU if the guest is in vEL2. */ 203 if (unlikely(is_hyp_ctxt(vcpu))) 204 goto memory_read; 205 206 if (__vcpu_read_sys_reg_from_cpu(reg, &val)) 207 return val; 208 209 memory_read: 210 return __vcpu_sys_reg(vcpu, reg); 211 } 212 213 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg) 214 { 215 u64 (*xlate)(u64) = NULL; 216 unsigned int el1r; 217 218 if (!vcpu_get_flag(vcpu, SYSREGS_ON_CPU)) 219 goto memory_write; 220 221 if (unlikely(get_el2_to_el1_mapping(reg, &el1r, &xlate))) { 222 if (!is_hyp_ctxt(vcpu)) 223 goto memory_write; 224 225 /* 226 * Always store a copy of the write to memory to avoid having 227 * to reverse-translate virtual EL2 system registers for a 228 * non-VHE guest hypervisor. 229 */ 230 __vcpu_sys_reg(vcpu, reg) = val; 231 232 switch (reg) { 233 case CNTHCTL_EL2: 234 /* 235 * If E2H=0, CNHTCTL_EL2 is a pure shadow register. 236 * Otherwise, some of the bits are backed by 237 * CNTKCTL_EL1, while the rest is kept in memory. 238 * Yes, this is fun stuff. 239 */ 240 if (vcpu_el2_e2h_is_set(vcpu)) 241 write_sysreg_el1(val, SYS_CNTKCTL); 242 return; 243 } 244 245 /* No EL1 counterpart? We're done here.? */ 246 if (reg == el1r) 247 return; 248 249 if (!vcpu_el2_e2h_is_set(vcpu) && xlate) 250 val = xlate(val); 251 252 /* Redirect this to the EL1 version of the register. */ 253 WARN_ON(!__vcpu_write_sys_reg_to_cpu(val, el1r)); 254 return; 255 } 256 257 /* EL1 register can't be on the CPU if the guest is in vEL2. */ 258 if (unlikely(is_hyp_ctxt(vcpu))) 259 goto memory_write; 260 261 if (__vcpu_write_sys_reg_to_cpu(val, reg)) 262 return; 263 264 memory_write: 265 __vcpu_sys_reg(vcpu, reg) = val; 266 } 267 268 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */ 269 #define CSSELR_MAX 14 270 271 /* 272 * Returns the minimum line size for the selected cache, expressed as 273 * Log2(bytes). 274 */ 275 static u8 get_min_cache_line_size(bool icache) 276 { 277 u64 ctr = read_sanitised_ftr_reg(SYS_CTR_EL0); 278 u8 field; 279 280 if (icache) 281 field = SYS_FIELD_GET(CTR_EL0, IminLine, ctr); 282 else 283 field = SYS_FIELD_GET(CTR_EL0, DminLine, ctr); 284 285 /* 286 * Cache line size is represented as Log2(words) in CTR_EL0. 287 * Log2(bytes) can be derived with the following: 288 * 289 * Log2(words) + 2 = Log2(bytes / 4) + 2 290 * = Log2(bytes) - 2 + 2 291 * = Log2(bytes) 292 */ 293 return field + 2; 294 } 295 296 /* Which cache CCSIDR represents depends on CSSELR value. */ 297 static u32 get_ccsidr(struct kvm_vcpu *vcpu, u32 csselr) 298 { 299 u8 line_size; 300 301 if (vcpu->arch.ccsidr) 302 return vcpu->arch.ccsidr[csselr]; 303 304 line_size = get_min_cache_line_size(csselr & CSSELR_EL1_InD); 305 306 /* 307 * Fabricate a CCSIDR value as the overriding value does not exist. 308 * The real CCSIDR value will not be used as it can vary by the 309 * physical CPU which the vcpu currently resides in. 310 * 311 * The line size is determined with get_min_cache_line_size(), which 312 * should be valid for all CPUs even if they have different cache 313 * configuration. 314 * 315 * The associativity bits are cleared, meaning the geometry of all data 316 * and unified caches (which are guaranteed to be PIPT and thus 317 * non-aliasing) are 1 set and 1 way. 318 * Guests should not be doing cache operations by set/way at all, and 319 * for this reason, we trap them and attempt to infer the intent, so 320 * that we can flush the entire guest's address space at the appropriate 321 * time. The exposed geometry minimizes the number of the traps. 322 * [If guests should attempt to infer aliasing properties from the 323 * geometry (which is not permitted by the architecture), they would 324 * only do so for virtually indexed caches.] 325 * 326 * We don't check if the cache level exists as it is allowed to return 327 * an UNKNOWN value if not. 328 */ 329 return SYS_FIELD_PREP(CCSIDR_EL1, LineSize, line_size - 4); 330 } 331 332 static int set_ccsidr(struct kvm_vcpu *vcpu, u32 csselr, u32 val) 333 { 334 u8 line_size = FIELD_GET(CCSIDR_EL1_LineSize, val) + 4; 335 u32 *ccsidr = vcpu->arch.ccsidr; 336 u32 i; 337 338 if ((val & CCSIDR_EL1_RES0) || 339 line_size < get_min_cache_line_size(csselr & CSSELR_EL1_InD)) 340 return -EINVAL; 341 342 if (!ccsidr) { 343 if (val == get_ccsidr(vcpu, csselr)) 344 return 0; 345 346 ccsidr = kmalloc_array(CSSELR_MAX, sizeof(u32), GFP_KERNEL_ACCOUNT); 347 if (!ccsidr) 348 return -ENOMEM; 349 350 for (i = 0; i < CSSELR_MAX; i++) 351 ccsidr[i] = get_ccsidr(vcpu, i); 352 353 vcpu->arch.ccsidr = ccsidr; 354 } 355 356 ccsidr[csselr] = val; 357 358 return 0; 359 } 360 361 static bool access_rw(struct kvm_vcpu *vcpu, 362 struct sys_reg_params *p, 363 const struct sys_reg_desc *r) 364 { 365 if (p->is_write) 366 vcpu_write_sys_reg(vcpu, p->regval, r->reg); 367 else 368 p->regval = vcpu_read_sys_reg(vcpu, r->reg); 369 370 return true; 371 } 372 373 /* 374 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized). 375 */ 376 static bool access_dcsw(struct kvm_vcpu *vcpu, 377 struct sys_reg_params *p, 378 const struct sys_reg_desc *r) 379 { 380 if (!p->is_write) 381 return read_from_write_only(vcpu, p, r); 382 383 /* 384 * Only track S/W ops if we don't have FWB. It still indicates 385 * that the guest is a bit broken (S/W operations should only 386 * be done by firmware, knowing that there is only a single 387 * CPU left in the system, and certainly not from non-secure 388 * software). 389 */ 390 if (!cpus_have_final_cap(ARM64_HAS_STAGE2_FWB)) 391 kvm_set_way_flush(vcpu); 392 393 return true; 394 } 395 396 static bool access_dcgsw(struct kvm_vcpu *vcpu, 397 struct sys_reg_params *p, 398 const struct sys_reg_desc *r) 399 { 400 if (!kvm_has_mte(vcpu->kvm)) 401 return undef_access(vcpu, p, r); 402 403 /* Treat MTE S/W ops as we treat the classic ones: with contempt */ 404 return access_dcsw(vcpu, p, r); 405 } 406 407 static void get_access_mask(const struct sys_reg_desc *r, u64 *mask, u64 *shift) 408 { 409 switch (r->aarch32_map) { 410 case AA32_LO: 411 *mask = GENMASK_ULL(31, 0); 412 *shift = 0; 413 break; 414 case AA32_HI: 415 *mask = GENMASK_ULL(63, 32); 416 *shift = 32; 417 break; 418 default: 419 *mask = GENMASK_ULL(63, 0); 420 *shift = 0; 421 break; 422 } 423 } 424 425 /* 426 * Generic accessor for VM registers. Only called as long as HCR_TVM 427 * is set. If the guest enables the MMU, we stop trapping the VM 428 * sys_regs and leave it in complete control of the caches. 429 */ 430 static bool access_vm_reg(struct kvm_vcpu *vcpu, 431 struct sys_reg_params *p, 432 const struct sys_reg_desc *r) 433 { 434 bool was_enabled = vcpu_has_cache_enabled(vcpu); 435 u64 val, mask, shift; 436 437 BUG_ON(!p->is_write); 438 439 get_access_mask(r, &mask, &shift); 440 441 if (~mask) { 442 val = vcpu_read_sys_reg(vcpu, r->reg); 443 val &= ~mask; 444 } else { 445 val = 0; 446 } 447 448 val |= (p->regval & (mask >> shift)) << shift; 449 vcpu_write_sys_reg(vcpu, val, r->reg); 450 451 kvm_toggle_cache(vcpu, was_enabled); 452 return true; 453 } 454 455 static bool access_actlr(struct kvm_vcpu *vcpu, 456 struct sys_reg_params *p, 457 const struct sys_reg_desc *r) 458 { 459 u64 mask, shift; 460 461 if (p->is_write) 462 return ignore_write(vcpu, p); 463 464 get_access_mask(r, &mask, &shift); 465 p->regval = (vcpu_read_sys_reg(vcpu, r->reg) & mask) >> shift; 466 467 return true; 468 } 469 470 /* 471 * Trap handler for the GICv3 SGI generation system register. 472 * Forward the request to the VGIC emulation. 473 * The cp15_64 code makes sure this automatically works 474 * for both AArch64 and AArch32 accesses. 475 */ 476 static bool access_gic_sgi(struct kvm_vcpu *vcpu, 477 struct sys_reg_params *p, 478 const struct sys_reg_desc *r) 479 { 480 bool g1; 481 482 if (!kvm_has_gicv3(vcpu->kvm)) 483 return undef_access(vcpu, p, r); 484 485 if (!p->is_write) 486 return read_from_write_only(vcpu, p, r); 487 488 /* 489 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates 490 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group, 491 * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively 492 * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure 493 * group. 494 */ 495 if (p->Op0 == 0) { /* AArch32 */ 496 switch (p->Op1) { 497 default: /* Keep GCC quiet */ 498 case 0: /* ICC_SGI1R */ 499 g1 = true; 500 break; 501 case 1: /* ICC_ASGI1R */ 502 case 2: /* ICC_SGI0R */ 503 g1 = false; 504 break; 505 } 506 } else { /* AArch64 */ 507 switch (p->Op2) { 508 default: /* Keep GCC quiet */ 509 case 5: /* ICC_SGI1R_EL1 */ 510 g1 = true; 511 break; 512 case 6: /* ICC_ASGI1R_EL1 */ 513 case 7: /* ICC_SGI0R_EL1 */ 514 g1 = false; 515 break; 516 } 517 } 518 519 vgic_v3_dispatch_sgi(vcpu, p->regval, g1); 520 521 return true; 522 } 523 524 static bool access_gic_sre(struct kvm_vcpu *vcpu, 525 struct sys_reg_params *p, 526 const struct sys_reg_desc *r) 527 { 528 if (!kvm_has_gicv3(vcpu->kvm)) 529 return undef_access(vcpu, p, r); 530 531 if (p->is_write) 532 return ignore_write(vcpu, p); 533 534 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre; 535 return true; 536 } 537 538 static bool trap_raz_wi(struct kvm_vcpu *vcpu, 539 struct sys_reg_params *p, 540 const struct sys_reg_desc *r) 541 { 542 if (p->is_write) 543 return ignore_write(vcpu, p); 544 else 545 return read_zero(vcpu, p); 546 } 547 548 /* 549 * ARMv8.1 mandates at least a trivial LORegion implementation, where all the 550 * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0 551 * system, these registers should UNDEF. LORID_EL1 being a RO register, we 552 * treat it separately. 553 */ 554 static bool trap_loregion(struct kvm_vcpu *vcpu, 555 struct sys_reg_params *p, 556 const struct sys_reg_desc *r) 557 { 558 u32 sr = reg_to_encoding(r); 559 560 if (!kvm_has_feat(vcpu->kvm, ID_AA64MMFR1_EL1, LO, IMP)) 561 return undef_access(vcpu, p, r); 562 563 if (p->is_write && sr == SYS_LORID_EL1) 564 return write_to_read_only(vcpu, p, r); 565 566 return trap_raz_wi(vcpu, p, r); 567 } 568 569 static bool trap_oslar_el1(struct kvm_vcpu *vcpu, 570 struct sys_reg_params *p, 571 const struct sys_reg_desc *r) 572 { 573 if (!p->is_write) 574 return read_from_write_only(vcpu, p, r); 575 576 kvm_debug_handle_oslar(vcpu, p->regval); 577 return true; 578 } 579 580 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu, 581 struct sys_reg_params *p, 582 const struct sys_reg_desc *r) 583 { 584 if (p->is_write) 585 return write_to_read_only(vcpu, p, r); 586 587 p->regval = __vcpu_sys_reg(vcpu, r->reg); 588 return true; 589 } 590 591 static int set_oslsr_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 592 u64 val) 593 { 594 /* 595 * The only modifiable bit is the OSLK bit. Refuse the write if 596 * userspace attempts to change any other bit in the register. 597 */ 598 if ((val ^ rd->val) & ~OSLSR_EL1_OSLK) 599 return -EINVAL; 600 601 __vcpu_sys_reg(vcpu, rd->reg) = val; 602 return 0; 603 } 604 605 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu, 606 struct sys_reg_params *p, 607 const struct sys_reg_desc *r) 608 { 609 if (p->is_write) { 610 return ignore_write(vcpu, p); 611 } else { 612 p->regval = read_sysreg(dbgauthstatus_el1); 613 return true; 614 } 615 } 616 617 static bool trap_debug_regs(struct kvm_vcpu *vcpu, 618 struct sys_reg_params *p, 619 const struct sys_reg_desc *r) 620 { 621 access_rw(vcpu, p, r); 622 623 kvm_debug_set_guest_ownership(vcpu); 624 return true; 625 } 626 627 /* 628 * reg_to_dbg/dbg_to_reg 629 * 630 * A 32 bit write to a debug register leave top bits alone 631 * A 32 bit read from a debug register only returns the bottom bits 632 */ 633 static void reg_to_dbg(struct kvm_vcpu *vcpu, 634 struct sys_reg_params *p, 635 const struct sys_reg_desc *rd, 636 u64 *dbg_reg) 637 { 638 u64 mask, shift, val; 639 640 get_access_mask(rd, &mask, &shift); 641 642 val = *dbg_reg; 643 val &= ~mask; 644 val |= (p->regval & (mask >> shift)) << shift; 645 *dbg_reg = val; 646 } 647 648 static void dbg_to_reg(struct kvm_vcpu *vcpu, 649 struct sys_reg_params *p, 650 const struct sys_reg_desc *rd, 651 u64 *dbg_reg) 652 { 653 u64 mask, shift; 654 655 get_access_mask(rd, &mask, &shift); 656 p->regval = (*dbg_reg & mask) >> shift; 657 } 658 659 static u64 *demux_wb_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd) 660 { 661 struct kvm_guest_debug_arch *dbg = &vcpu->arch.vcpu_debug_state; 662 663 switch (rd->Op2) { 664 case 0b100: 665 return &dbg->dbg_bvr[rd->CRm]; 666 case 0b101: 667 return &dbg->dbg_bcr[rd->CRm]; 668 case 0b110: 669 return &dbg->dbg_wvr[rd->CRm]; 670 case 0b111: 671 return &dbg->dbg_wcr[rd->CRm]; 672 default: 673 KVM_BUG_ON(1, vcpu->kvm); 674 return NULL; 675 } 676 } 677 678 static bool trap_dbg_wb_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 679 const struct sys_reg_desc *rd) 680 { 681 u64 *reg = demux_wb_reg(vcpu, rd); 682 683 if (!reg) 684 return false; 685 686 if (p->is_write) 687 reg_to_dbg(vcpu, p, rd, reg); 688 else 689 dbg_to_reg(vcpu, p, rd, reg); 690 691 kvm_debug_set_guest_ownership(vcpu); 692 return true; 693 } 694 695 static int set_dbg_wb_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 696 u64 val) 697 { 698 u64 *reg = demux_wb_reg(vcpu, rd); 699 700 if (!reg) 701 return -EINVAL; 702 703 *reg = val; 704 return 0; 705 } 706 707 static int get_dbg_wb_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 708 u64 *val) 709 { 710 u64 *reg = demux_wb_reg(vcpu, rd); 711 712 if (!reg) 713 return -EINVAL; 714 715 *val = *reg; 716 return 0; 717 } 718 719 static u64 reset_dbg_wb_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd) 720 { 721 u64 *reg = demux_wb_reg(vcpu, rd); 722 723 /* 724 * Bail early if we couldn't find storage for the register, the 725 * KVM_BUG_ON() in demux_wb_reg() will prevent this VM from ever 726 * being run. 727 */ 728 if (!reg) 729 return 0; 730 731 *reg = rd->val; 732 return rd->val; 733 } 734 735 static u64 reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 736 { 737 u64 amair = read_sysreg(amair_el1); 738 vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1); 739 return amair; 740 } 741 742 static u64 reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 743 { 744 u64 actlr = read_sysreg(actlr_el1); 745 vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1); 746 return actlr; 747 } 748 749 static u64 reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 750 { 751 u64 mpidr; 752 753 /* 754 * Map the vcpu_id into the first three affinity level fields of 755 * the MPIDR. We limit the number of VCPUs in level 0 due to a 756 * limitation to 16 CPUs in that level in the ICC_SGIxR registers 757 * of the GICv3 to be able to address each CPU directly when 758 * sending IPIs. 759 */ 760 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0); 761 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1); 762 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2); 763 mpidr |= (1ULL << 31); 764 vcpu_write_sys_reg(vcpu, mpidr, MPIDR_EL1); 765 766 return mpidr; 767 } 768 769 static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu, 770 const struct sys_reg_desc *r) 771 { 772 if (kvm_vcpu_has_pmu(vcpu)) 773 return 0; 774 775 return REG_HIDDEN; 776 } 777 778 static u64 reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 779 { 780 u64 mask = BIT(ARMV8_PMU_CYCLE_IDX); 781 u8 n = vcpu->kvm->arch.pmcr_n; 782 783 if (n) 784 mask |= GENMASK(n - 1, 0); 785 786 reset_unknown(vcpu, r); 787 __vcpu_sys_reg(vcpu, r->reg) &= mask; 788 789 return __vcpu_sys_reg(vcpu, r->reg); 790 } 791 792 static u64 reset_pmevcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 793 { 794 reset_unknown(vcpu, r); 795 __vcpu_sys_reg(vcpu, r->reg) &= GENMASK(31, 0); 796 797 return __vcpu_sys_reg(vcpu, r->reg); 798 } 799 800 static u64 reset_pmevtyper(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 801 { 802 /* This thing will UNDEF, who cares about the reset value? */ 803 if (!kvm_vcpu_has_pmu(vcpu)) 804 return 0; 805 806 reset_unknown(vcpu, r); 807 __vcpu_sys_reg(vcpu, r->reg) &= kvm_pmu_evtyper_mask(vcpu->kvm); 808 809 return __vcpu_sys_reg(vcpu, r->reg); 810 } 811 812 static u64 reset_pmselr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 813 { 814 reset_unknown(vcpu, r); 815 __vcpu_sys_reg(vcpu, r->reg) &= PMSELR_EL0_SEL_MASK; 816 817 return __vcpu_sys_reg(vcpu, r->reg); 818 } 819 820 static u64 reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 821 { 822 u64 pmcr = 0; 823 824 if (!kvm_supports_32bit_el0()) 825 pmcr |= ARMV8_PMU_PMCR_LC; 826 827 /* 828 * The value of PMCR.N field is included when the 829 * vCPU register is read via kvm_vcpu_read_pmcr(). 830 */ 831 __vcpu_sys_reg(vcpu, r->reg) = pmcr; 832 833 return __vcpu_sys_reg(vcpu, r->reg); 834 } 835 836 static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags) 837 { 838 u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0); 839 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu); 840 841 if (!enabled) 842 kvm_inject_undefined(vcpu); 843 844 return !enabled; 845 } 846 847 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu) 848 { 849 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN); 850 } 851 852 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu) 853 { 854 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN); 855 } 856 857 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu) 858 { 859 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN); 860 } 861 862 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu) 863 { 864 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN); 865 } 866 867 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 868 const struct sys_reg_desc *r) 869 { 870 u64 val; 871 872 if (pmu_access_el0_disabled(vcpu)) 873 return false; 874 875 if (p->is_write) { 876 /* 877 * Only update writeable bits of PMCR (continuing into 878 * kvm_pmu_handle_pmcr() as well) 879 */ 880 val = kvm_vcpu_read_pmcr(vcpu); 881 val &= ~ARMV8_PMU_PMCR_MASK; 882 val |= p->regval & ARMV8_PMU_PMCR_MASK; 883 if (!kvm_supports_32bit_el0()) 884 val |= ARMV8_PMU_PMCR_LC; 885 kvm_pmu_handle_pmcr(vcpu, val); 886 } else { 887 /* PMCR.P & PMCR.C are RAZ */ 888 val = kvm_vcpu_read_pmcr(vcpu) 889 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C); 890 p->regval = val; 891 } 892 893 return true; 894 } 895 896 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 897 const struct sys_reg_desc *r) 898 { 899 if (pmu_access_event_counter_el0_disabled(vcpu)) 900 return false; 901 902 if (p->is_write) 903 __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval; 904 else 905 /* return PMSELR.SEL field */ 906 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0) 907 & PMSELR_EL0_SEL_MASK; 908 909 return true; 910 } 911 912 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 913 const struct sys_reg_desc *r) 914 { 915 u64 pmceid, mask, shift; 916 917 BUG_ON(p->is_write); 918 919 if (pmu_access_el0_disabled(vcpu)) 920 return false; 921 922 get_access_mask(r, &mask, &shift); 923 924 pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1)); 925 pmceid &= mask; 926 pmceid >>= shift; 927 928 p->regval = pmceid; 929 930 return true; 931 } 932 933 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx) 934 { 935 u64 pmcr, val; 936 937 pmcr = kvm_vcpu_read_pmcr(vcpu); 938 val = FIELD_GET(ARMV8_PMU_PMCR_N, pmcr); 939 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) { 940 kvm_inject_undefined(vcpu); 941 return false; 942 } 943 944 return true; 945 } 946 947 static int get_pmu_evcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 948 u64 *val) 949 { 950 u64 idx; 951 952 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 0) 953 /* PMCCNTR_EL0 */ 954 idx = ARMV8_PMU_CYCLE_IDX; 955 else 956 /* PMEVCNTRn_EL0 */ 957 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 958 959 *val = kvm_pmu_get_counter_value(vcpu, idx); 960 return 0; 961 } 962 963 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu, 964 struct sys_reg_params *p, 965 const struct sys_reg_desc *r) 966 { 967 u64 idx = ~0UL; 968 969 if (r->CRn == 9 && r->CRm == 13) { 970 if (r->Op2 == 2) { 971 /* PMXEVCNTR_EL0 */ 972 if (pmu_access_event_counter_el0_disabled(vcpu)) 973 return false; 974 975 idx = SYS_FIELD_GET(PMSELR_EL0, SEL, 976 __vcpu_sys_reg(vcpu, PMSELR_EL0)); 977 } else if (r->Op2 == 0) { 978 /* PMCCNTR_EL0 */ 979 if (pmu_access_cycle_counter_el0_disabled(vcpu)) 980 return false; 981 982 idx = ARMV8_PMU_CYCLE_IDX; 983 } 984 } else if (r->CRn == 0 && r->CRm == 9) { 985 /* PMCCNTR */ 986 if (pmu_access_event_counter_el0_disabled(vcpu)) 987 return false; 988 989 idx = ARMV8_PMU_CYCLE_IDX; 990 } else if (r->CRn == 14 && (r->CRm & 12) == 8) { 991 /* PMEVCNTRn_EL0 */ 992 if (pmu_access_event_counter_el0_disabled(vcpu)) 993 return false; 994 995 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 996 } 997 998 /* Catch any decoding mistake */ 999 WARN_ON(idx == ~0UL); 1000 1001 if (!pmu_counter_idx_valid(vcpu, idx)) 1002 return false; 1003 1004 if (p->is_write) { 1005 if (pmu_access_el0_disabled(vcpu)) 1006 return false; 1007 1008 kvm_pmu_set_counter_value(vcpu, idx, p->regval); 1009 } else { 1010 p->regval = kvm_pmu_get_counter_value(vcpu, idx); 1011 } 1012 1013 return true; 1014 } 1015 1016 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1017 const struct sys_reg_desc *r) 1018 { 1019 u64 idx, reg; 1020 1021 if (pmu_access_el0_disabled(vcpu)) 1022 return false; 1023 1024 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) { 1025 /* PMXEVTYPER_EL0 */ 1026 idx = SYS_FIELD_GET(PMSELR_EL0, SEL, __vcpu_sys_reg(vcpu, PMSELR_EL0)); 1027 reg = PMEVTYPER0_EL0 + idx; 1028 } else if (r->CRn == 14 && (r->CRm & 12) == 12) { 1029 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 1030 if (idx == ARMV8_PMU_CYCLE_IDX) 1031 reg = PMCCFILTR_EL0; 1032 else 1033 /* PMEVTYPERn_EL0 */ 1034 reg = PMEVTYPER0_EL0 + idx; 1035 } else { 1036 BUG(); 1037 } 1038 1039 if (!pmu_counter_idx_valid(vcpu, idx)) 1040 return false; 1041 1042 if (p->is_write) { 1043 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx); 1044 kvm_vcpu_pmu_restore_guest(vcpu); 1045 } else { 1046 p->regval = __vcpu_sys_reg(vcpu, reg); 1047 } 1048 1049 return true; 1050 } 1051 1052 static int set_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 val) 1053 { 1054 bool set; 1055 1056 val &= kvm_pmu_accessible_counter_mask(vcpu); 1057 1058 switch (r->reg) { 1059 case PMOVSSET_EL0: 1060 /* CRm[1] being set indicates a SET register, and CLR otherwise */ 1061 set = r->CRm & 2; 1062 break; 1063 default: 1064 /* Op2[0] being set indicates a SET register, and CLR otherwise */ 1065 set = r->Op2 & 1; 1066 break; 1067 } 1068 1069 if (set) 1070 __vcpu_sys_reg(vcpu, r->reg) |= val; 1071 else 1072 __vcpu_sys_reg(vcpu, r->reg) &= ~val; 1073 1074 return 0; 1075 } 1076 1077 static int get_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 *val) 1078 { 1079 u64 mask = kvm_pmu_accessible_counter_mask(vcpu); 1080 1081 *val = __vcpu_sys_reg(vcpu, r->reg) & mask; 1082 return 0; 1083 } 1084 1085 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1086 const struct sys_reg_desc *r) 1087 { 1088 u64 val, mask; 1089 1090 if (pmu_access_el0_disabled(vcpu)) 1091 return false; 1092 1093 mask = kvm_pmu_accessible_counter_mask(vcpu); 1094 if (p->is_write) { 1095 val = p->regval & mask; 1096 if (r->Op2 & 0x1) 1097 /* accessing PMCNTENSET_EL0 */ 1098 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val; 1099 else 1100 /* accessing PMCNTENCLR_EL0 */ 1101 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val; 1102 1103 kvm_pmu_reprogram_counter_mask(vcpu, val); 1104 } else { 1105 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0); 1106 } 1107 1108 return true; 1109 } 1110 1111 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1112 const struct sys_reg_desc *r) 1113 { 1114 u64 mask = kvm_pmu_accessible_counter_mask(vcpu); 1115 1116 if (check_pmu_access_disabled(vcpu, 0)) 1117 return false; 1118 1119 if (p->is_write) { 1120 u64 val = p->regval & mask; 1121 1122 if (r->Op2 & 0x1) 1123 /* accessing PMINTENSET_EL1 */ 1124 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val; 1125 else 1126 /* accessing PMINTENCLR_EL1 */ 1127 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val; 1128 } else { 1129 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1); 1130 } 1131 1132 return true; 1133 } 1134 1135 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1136 const struct sys_reg_desc *r) 1137 { 1138 u64 mask = kvm_pmu_accessible_counter_mask(vcpu); 1139 1140 if (pmu_access_el0_disabled(vcpu)) 1141 return false; 1142 1143 if (p->is_write) { 1144 if (r->CRm & 0x2) 1145 /* accessing PMOVSSET_EL0 */ 1146 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask); 1147 else 1148 /* accessing PMOVSCLR_EL0 */ 1149 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask); 1150 } else { 1151 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0); 1152 } 1153 1154 return true; 1155 } 1156 1157 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1158 const struct sys_reg_desc *r) 1159 { 1160 u64 mask; 1161 1162 if (!p->is_write) 1163 return read_from_write_only(vcpu, p, r); 1164 1165 if (pmu_write_swinc_el0_disabled(vcpu)) 1166 return false; 1167 1168 mask = kvm_pmu_accessible_counter_mask(vcpu); 1169 kvm_pmu_software_increment(vcpu, p->regval & mask); 1170 return true; 1171 } 1172 1173 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1174 const struct sys_reg_desc *r) 1175 { 1176 if (p->is_write) { 1177 if (!vcpu_mode_priv(vcpu)) 1178 return undef_access(vcpu, p, r); 1179 1180 __vcpu_sys_reg(vcpu, PMUSERENR_EL0) = 1181 p->regval & ARMV8_PMU_USERENR_MASK; 1182 } else { 1183 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0) 1184 & ARMV8_PMU_USERENR_MASK; 1185 } 1186 1187 return true; 1188 } 1189 1190 static int get_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 1191 u64 *val) 1192 { 1193 *val = kvm_vcpu_read_pmcr(vcpu); 1194 return 0; 1195 } 1196 1197 static int set_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 1198 u64 val) 1199 { 1200 u8 new_n = FIELD_GET(ARMV8_PMU_PMCR_N, val); 1201 struct kvm *kvm = vcpu->kvm; 1202 1203 mutex_lock(&kvm->arch.config_lock); 1204 1205 /* 1206 * The vCPU can't have more counters than the PMU hardware 1207 * implements. Ignore this error to maintain compatibility 1208 * with the existing KVM behavior. 1209 */ 1210 if (!kvm_vm_has_ran_once(kvm) && 1211 new_n <= kvm_arm_pmu_get_max_counters(kvm)) 1212 kvm->arch.pmcr_n = new_n; 1213 1214 mutex_unlock(&kvm->arch.config_lock); 1215 1216 /* 1217 * Ignore writes to RES0 bits, read only bits that are cleared on 1218 * vCPU reset, and writable bits that KVM doesn't support yet. 1219 * (i.e. only PMCR.N and bits [7:0] are mutable from userspace) 1220 * The LP bit is RES0 when FEAT_PMUv3p5 is not supported on the vCPU. 1221 * But, we leave the bit as it is here, as the vCPU's PMUver might 1222 * be changed later (NOTE: the bit will be cleared on first vCPU run 1223 * if necessary). 1224 */ 1225 val &= ARMV8_PMU_PMCR_MASK; 1226 1227 /* The LC bit is RES1 when AArch32 is not supported */ 1228 if (!kvm_supports_32bit_el0()) 1229 val |= ARMV8_PMU_PMCR_LC; 1230 1231 __vcpu_sys_reg(vcpu, r->reg) = val; 1232 return 0; 1233 } 1234 1235 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */ 1236 #define DBG_BCR_BVR_WCR_WVR_EL1(n) \ 1237 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \ 1238 trap_dbg_wb_reg, reset_dbg_wb_reg, 0, 0, \ 1239 get_dbg_wb_reg, set_dbg_wb_reg }, \ 1240 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \ 1241 trap_dbg_wb_reg, reset_dbg_wb_reg, 0, 0, \ 1242 get_dbg_wb_reg, set_dbg_wb_reg }, \ 1243 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \ 1244 trap_dbg_wb_reg, reset_dbg_wb_reg, 0, 0, \ 1245 get_dbg_wb_reg, set_dbg_wb_reg }, \ 1246 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \ 1247 trap_dbg_wb_reg, reset_dbg_wb_reg, 0, 0, \ 1248 get_dbg_wb_reg, set_dbg_wb_reg } 1249 1250 #define PMU_SYS_REG(name) \ 1251 SYS_DESC(SYS_##name), .reset = reset_pmu_reg, \ 1252 .visibility = pmu_visibility 1253 1254 /* Macro to expand the PMEVCNTRn_EL0 register */ 1255 #define PMU_PMEVCNTR_EL0(n) \ 1256 { PMU_SYS_REG(PMEVCNTRn_EL0(n)), \ 1257 .reset = reset_pmevcntr, .get_user = get_pmu_evcntr, \ 1258 .access = access_pmu_evcntr, .reg = (PMEVCNTR0_EL0 + n), } 1259 1260 /* Macro to expand the PMEVTYPERn_EL0 register */ 1261 #define PMU_PMEVTYPER_EL0(n) \ 1262 { PMU_SYS_REG(PMEVTYPERn_EL0(n)), \ 1263 .reset = reset_pmevtyper, \ 1264 .access = access_pmu_evtyper, .reg = (PMEVTYPER0_EL0 + n), } 1265 1266 /* Macro to expand the AMU counter and type registers*/ 1267 #define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), undef_access } 1268 #define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), undef_access } 1269 #define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), undef_access } 1270 #define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), undef_access } 1271 1272 static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu, 1273 const struct sys_reg_desc *rd) 1274 { 1275 return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN; 1276 } 1277 1278 /* 1279 * If we land here on a PtrAuth access, that is because we didn't 1280 * fixup the access on exit by allowing the PtrAuth sysregs. The only 1281 * way this happens is when the guest does not have PtrAuth support 1282 * enabled. 1283 */ 1284 #define __PTRAUTH_KEY(k) \ 1285 { SYS_DESC(SYS_## k), undef_access, reset_unknown, k, \ 1286 .visibility = ptrauth_visibility} 1287 1288 #define PTRAUTH_KEY(k) \ 1289 __PTRAUTH_KEY(k ## KEYLO_EL1), \ 1290 __PTRAUTH_KEY(k ## KEYHI_EL1) 1291 1292 static bool access_arch_timer(struct kvm_vcpu *vcpu, 1293 struct sys_reg_params *p, 1294 const struct sys_reg_desc *r) 1295 { 1296 enum kvm_arch_timers tmr; 1297 enum kvm_arch_timer_regs treg; 1298 u64 reg = reg_to_encoding(r); 1299 1300 switch (reg) { 1301 case SYS_CNTP_TVAL_EL0: 1302 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) 1303 tmr = TIMER_HPTIMER; 1304 else 1305 tmr = TIMER_PTIMER; 1306 treg = TIMER_REG_TVAL; 1307 break; 1308 1309 case SYS_CNTV_TVAL_EL0: 1310 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) 1311 tmr = TIMER_HVTIMER; 1312 else 1313 tmr = TIMER_VTIMER; 1314 treg = TIMER_REG_TVAL; 1315 break; 1316 1317 case SYS_AARCH32_CNTP_TVAL: 1318 case SYS_CNTP_TVAL_EL02: 1319 tmr = TIMER_PTIMER; 1320 treg = TIMER_REG_TVAL; 1321 break; 1322 1323 case SYS_CNTV_TVAL_EL02: 1324 tmr = TIMER_VTIMER; 1325 treg = TIMER_REG_TVAL; 1326 break; 1327 1328 case SYS_CNTHP_TVAL_EL2: 1329 tmr = TIMER_HPTIMER; 1330 treg = TIMER_REG_TVAL; 1331 break; 1332 1333 case SYS_CNTHV_TVAL_EL2: 1334 tmr = TIMER_HVTIMER; 1335 treg = TIMER_REG_TVAL; 1336 break; 1337 1338 case SYS_CNTP_CTL_EL0: 1339 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) 1340 tmr = TIMER_HPTIMER; 1341 else 1342 tmr = TIMER_PTIMER; 1343 treg = TIMER_REG_CTL; 1344 break; 1345 1346 case SYS_CNTV_CTL_EL0: 1347 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) 1348 tmr = TIMER_HVTIMER; 1349 else 1350 tmr = TIMER_VTIMER; 1351 treg = TIMER_REG_CTL; 1352 break; 1353 1354 case SYS_AARCH32_CNTP_CTL: 1355 case SYS_CNTP_CTL_EL02: 1356 tmr = TIMER_PTIMER; 1357 treg = TIMER_REG_CTL; 1358 break; 1359 1360 case SYS_CNTV_CTL_EL02: 1361 tmr = TIMER_VTIMER; 1362 treg = TIMER_REG_CTL; 1363 break; 1364 1365 case SYS_CNTHP_CTL_EL2: 1366 tmr = TIMER_HPTIMER; 1367 treg = TIMER_REG_CTL; 1368 break; 1369 1370 case SYS_CNTHV_CTL_EL2: 1371 tmr = TIMER_HVTIMER; 1372 treg = TIMER_REG_CTL; 1373 break; 1374 1375 case SYS_CNTP_CVAL_EL0: 1376 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) 1377 tmr = TIMER_HPTIMER; 1378 else 1379 tmr = TIMER_PTIMER; 1380 treg = TIMER_REG_CVAL; 1381 break; 1382 1383 case SYS_CNTV_CVAL_EL0: 1384 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) 1385 tmr = TIMER_HVTIMER; 1386 else 1387 tmr = TIMER_VTIMER; 1388 treg = TIMER_REG_CVAL; 1389 break; 1390 1391 case SYS_AARCH32_CNTP_CVAL: 1392 case SYS_CNTP_CVAL_EL02: 1393 tmr = TIMER_PTIMER; 1394 treg = TIMER_REG_CVAL; 1395 break; 1396 1397 case SYS_CNTV_CVAL_EL02: 1398 tmr = TIMER_VTIMER; 1399 treg = TIMER_REG_CVAL; 1400 break; 1401 1402 case SYS_CNTHP_CVAL_EL2: 1403 tmr = TIMER_HPTIMER; 1404 treg = TIMER_REG_CVAL; 1405 break; 1406 1407 case SYS_CNTHV_CVAL_EL2: 1408 tmr = TIMER_HVTIMER; 1409 treg = TIMER_REG_CVAL; 1410 break; 1411 1412 case SYS_CNTPCT_EL0: 1413 case SYS_CNTPCTSS_EL0: 1414 if (is_hyp_ctxt(vcpu)) 1415 tmr = TIMER_HPTIMER; 1416 else 1417 tmr = TIMER_PTIMER; 1418 treg = TIMER_REG_CNT; 1419 break; 1420 1421 case SYS_AARCH32_CNTPCT: 1422 case SYS_AARCH32_CNTPCTSS: 1423 tmr = TIMER_PTIMER; 1424 treg = TIMER_REG_CNT; 1425 break; 1426 1427 case SYS_CNTVCT_EL0: 1428 case SYS_CNTVCTSS_EL0: 1429 if (is_hyp_ctxt(vcpu)) 1430 tmr = TIMER_HVTIMER; 1431 else 1432 tmr = TIMER_VTIMER; 1433 treg = TIMER_REG_CNT; 1434 break; 1435 1436 case SYS_AARCH32_CNTVCT: 1437 case SYS_AARCH32_CNTVCTSS: 1438 tmr = TIMER_VTIMER; 1439 treg = TIMER_REG_CNT; 1440 break; 1441 1442 default: 1443 print_sys_reg_msg(p, "%s", "Unhandled trapped timer register"); 1444 return undef_access(vcpu, p, r); 1445 } 1446 1447 if (p->is_write) 1448 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval); 1449 else 1450 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg); 1451 1452 return true; 1453 } 1454 1455 static bool access_hv_timer(struct kvm_vcpu *vcpu, 1456 struct sys_reg_params *p, 1457 const struct sys_reg_desc *r) 1458 { 1459 if (!vcpu_el2_e2h_is_set(vcpu)) 1460 return undef_access(vcpu, p, r); 1461 1462 return access_arch_timer(vcpu, p, r); 1463 } 1464 1465 static s64 kvm_arm64_ftr_safe_value(u32 id, const struct arm64_ftr_bits *ftrp, 1466 s64 new, s64 cur) 1467 { 1468 struct arm64_ftr_bits kvm_ftr = *ftrp; 1469 1470 /* Some features have different safe value type in KVM than host features */ 1471 switch (id) { 1472 case SYS_ID_AA64DFR0_EL1: 1473 switch (kvm_ftr.shift) { 1474 case ID_AA64DFR0_EL1_PMUVer_SHIFT: 1475 kvm_ftr.type = FTR_LOWER_SAFE; 1476 break; 1477 case ID_AA64DFR0_EL1_DebugVer_SHIFT: 1478 kvm_ftr.type = FTR_LOWER_SAFE; 1479 break; 1480 } 1481 break; 1482 case SYS_ID_DFR0_EL1: 1483 if (kvm_ftr.shift == ID_DFR0_EL1_PerfMon_SHIFT) 1484 kvm_ftr.type = FTR_LOWER_SAFE; 1485 break; 1486 } 1487 1488 return arm64_ftr_safe_value(&kvm_ftr, new, cur); 1489 } 1490 1491 /* 1492 * arm64_check_features() - Check if a feature register value constitutes 1493 * a subset of features indicated by the idreg's KVM sanitised limit. 1494 * 1495 * This function will check if each feature field of @val is the "safe" value 1496 * against idreg's KVM sanitised limit return from reset() callback. 1497 * If a field value in @val is the same as the one in limit, it is always 1498 * considered the safe value regardless For register fields that are not in 1499 * writable, only the value in limit is considered the safe value. 1500 * 1501 * Return: 0 if all the fields are safe. Otherwise, return negative errno. 1502 */ 1503 static int arm64_check_features(struct kvm_vcpu *vcpu, 1504 const struct sys_reg_desc *rd, 1505 u64 val) 1506 { 1507 const struct arm64_ftr_reg *ftr_reg; 1508 const struct arm64_ftr_bits *ftrp = NULL; 1509 u32 id = reg_to_encoding(rd); 1510 u64 writable_mask = rd->val; 1511 u64 limit = rd->reset(vcpu, rd); 1512 u64 mask = 0; 1513 1514 /* 1515 * Hidden and unallocated ID registers may not have a corresponding 1516 * struct arm64_ftr_reg. Of course, if the register is RAZ we know the 1517 * only safe value is 0. 1518 */ 1519 if (sysreg_visible_as_raz(vcpu, rd)) 1520 return val ? -E2BIG : 0; 1521 1522 ftr_reg = get_arm64_ftr_reg(id); 1523 if (!ftr_reg) 1524 return -EINVAL; 1525 1526 ftrp = ftr_reg->ftr_bits; 1527 1528 for (; ftrp && ftrp->width; ftrp++) { 1529 s64 f_val, f_lim, safe_val; 1530 u64 ftr_mask; 1531 1532 ftr_mask = arm64_ftr_mask(ftrp); 1533 if ((ftr_mask & writable_mask) != ftr_mask) 1534 continue; 1535 1536 f_val = arm64_ftr_value(ftrp, val); 1537 f_lim = arm64_ftr_value(ftrp, limit); 1538 mask |= ftr_mask; 1539 1540 if (f_val == f_lim) 1541 safe_val = f_val; 1542 else 1543 safe_val = kvm_arm64_ftr_safe_value(id, ftrp, f_val, f_lim); 1544 1545 if (safe_val != f_val) 1546 return -E2BIG; 1547 } 1548 1549 /* For fields that are not writable, values in limit are the safe values. */ 1550 if ((val & ~mask) != (limit & ~mask)) 1551 return -E2BIG; 1552 1553 return 0; 1554 } 1555 1556 static u8 pmuver_to_perfmon(u8 pmuver) 1557 { 1558 switch (pmuver) { 1559 case ID_AA64DFR0_EL1_PMUVer_IMP: 1560 return ID_DFR0_EL1_PerfMon_PMUv3; 1561 case ID_AA64DFR0_EL1_PMUVer_IMP_DEF: 1562 return ID_DFR0_EL1_PerfMon_IMPDEF; 1563 default: 1564 /* Anything ARMv8.1+ and NI have the same value. For now. */ 1565 return pmuver; 1566 } 1567 } 1568 1569 static u64 sanitise_id_aa64pfr0_el1(const struct kvm_vcpu *vcpu, u64 val); 1570 static u64 sanitise_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, u64 val); 1571 1572 /* Read a sanitised cpufeature ID register by sys_reg_desc */ 1573 static u64 __kvm_read_sanitised_id_reg(const struct kvm_vcpu *vcpu, 1574 const struct sys_reg_desc *r) 1575 { 1576 u32 id = reg_to_encoding(r); 1577 u64 val; 1578 1579 if (sysreg_visible_as_raz(vcpu, r)) 1580 return 0; 1581 1582 val = read_sanitised_ftr_reg(id); 1583 1584 switch (id) { 1585 case SYS_ID_AA64DFR0_EL1: 1586 val = sanitise_id_aa64dfr0_el1(vcpu, val); 1587 break; 1588 case SYS_ID_AA64PFR0_EL1: 1589 val = sanitise_id_aa64pfr0_el1(vcpu, val); 1590 break; 1591 case SYS_ID_AA64PFR1_EL1: 1592 if (!kvm_has_mte(vcpu->kvm)) 1593 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE); 1594 1595 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_SME); 1596 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_RNDR_trap); 1597 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_NMI); 1598 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE_frac); 1599 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_GCS); 1600 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_THE); 1601 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTEX); 1602 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_DF2); 1603 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_PFAR); 1604 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MPAM_frac); 1605 break; 1606 case SYS_ID_AA64PFR2_EL1: 1607 /* We only expose FPMR */ 1608 val &= ID_AA64PFR2_EL1_FPMR; 1609 break; 1610 case SYS_ID_AA64ISAR1_EL1: 1611 if (!vcpu_has_ptrauth(vcpu)) 1612 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) | 1613 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) | 1614 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) | 1615 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI)); 1616 break; 1617 case SYS_ID_AA64ISAR2_EL1: 1618 if (!vcpu_has_ptrauth(vcpu)) 1619 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) | 1620 ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3)); 1621 if (!cpus_have_final_cap(ARM64_HAS_WFXT) || 1622 has_broken_cntvoff()) 1623 val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT); 1624 break; 1625 case SYS_ID_AA64ISAR3_EL1: 1626 val &= ID_AA64ISAR3_EL1_FPRCVT | ID_AA64ISAR3_EL1_FAMINMAX; 1627 break; 1628 case SYS_ID_AA64MMFR2_EL1: 1629 val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK; 1630 break; 1631 case SYS_ID_AA64MMFR3_EL1: 1632 val &= ID_AA64MMFR3_EL1_TCRX | ID_AA64MMFR3_EL1_S1POE | 1633 ID_AA64MMFR3_EL1_S1PIE; 1634 break; 1635 case SYS_ID_MMFR4_EL1: 1636 val &= ~ARM64_FEATURE_MASK(ID_MMFR4_EL1_CCIDX); 1637 break; 1638 } 1639 1640 return val; 1641 } 1642 1643 static u64 kvm_read_sanitised_id_reg(struct kvm_vcpu *vcpu, 1644 const struct sys_reg_desc *r) 1645 { 1646 return __kvm_read_sanitised_id_reg(vcpu, r); 1647 } 1648 1649 static u64 read_id_reg(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 1650 { 1651 return kvm_read_vm_id_reg(vcpu->kvm, reg_to_encoding(r)); 1652 } 1653 1654 static bool is_feature_id_reg(u32 encoding) 1655 { 1656 return (sys_reg_Op0(encoding) == 3 && 1657 (sys_reg_Op1(encoding) < 2 || sys_reg_Op1(encoding) == 3) && 1658 sys_reg_CRn(encoding) == 0 && 1659 sys_reg_CRm(encoding) <= 7); 1660 } 1661 1662 /* 1663 * Return true if the register's (Op0, Op1, CRn, CRm, Op2) is 1664 * (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8, which is the range of ID 1665 * registers KVM maintains on a per-VM basis. 1666 */ 1667 static inline bool is_vm_ftr_id_reg(u32 id) 1668 { 1669 if (id == SYS_CTR_EL0) 1670 return true; 1671 1672 return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 && 1673 sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 && 1674 sys_reg_CRm(id) < 8); 1675 } 1676 1677 static inline bool is_vcpu_ftr_id_reg(u32 id) 1678 { 1679 return is_feature_id_reg(id) && !is_vm_ftr_id_reg(id); 1680 } 1681 1682 static inline bool is_aa32_id_reg(u32 id) 1683 { 1684 return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 && 1685 sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 && 1686 sys_reg_CRm(id) <= 3); 1687 } 1688 1689 static unsigned int id_visibility(const struct kvm_vcpu *vcpu, 1690 const struct sys_reg_desc *r) 1691 { 1692 u32 id = reg_to_encoding(r); 1693 1694 switch (id) { 1695 case SYS_ID_AA64ZFR0_EL1: 1696 if (!vcpu_has_sve(vcpu)) 1697 return REG_RAZ; 1698 break; 1699 } 1700 1701 return 0; 1702 } 1703 1704 static unsigned int aa32_id_visibility(const struct kvm_vcpu *vcpu, 1705 const struct sys_reg_desc *r) 1706 { 1707 /* 1708 * AArch32 ID registers are UNKNOWN if AArch32 isn't implemented at any 1709 * EL. Promote to RAZ/WI in order to guarantee consistency between 1710 * systems. 1711 */ 1712 if (!kvm_supports_32bit_el0()) 1713 return REG_RAZ | REG_USER_WI; 1714 1715 return id_visibility(vcpu, r); 1716 } 1717 1718 static unsigned int raz_visibility(const struct kvm_vcpu *vcpu, 1719 const struct sys_reg_desc *r) 1720 { 1721 return REG_RAZ; 1722 } 1723 1724 /* cpufeature ID register access trap handlers */ 1725 1726 static bool access_id_reg(struct kvm_vcpu *vcpu, 1727 struct sys_reg_params *p, 1728 const struct sys_reg_desc *r) 1729 { 1730 if (p->is_write) 1731 return write_to_read_only(vcpu, p, r); 1732 1733 p->regval = read_id_reg(vcpu, r); 1734 1735 return true; 1736 } 1737 1738 /* Visibility overrides for SVE-specific control registers */ 1739 static unsigned int sve_visibility(const struct kvm_vcpu *vcpu, 1740 const struct sys_reg_desc *rd) 1741 { 1742 if (vcpu_has_sve(vcpu)) 1743 return 0; 1744 1745 return REG_HIDDEN; 1746 } 1747 1748 static unsigned int sme_visibility(const struct kvm_vcpu *vcpu, 1749 const struct sys_reg_desc *rd) 1750 { 1751 if (kvm_has_feat(vcpu->kvm, ID_AA64PFR1_EL1, SME, IMP)) 1752 return 0; 1753 1754 return REG_HIDDEN; 1755 } 1756 1757 static unsigned int fp8_visibility(const struct kvm_vcpu *vcpu, 1758 const struct sys_reg_desc *rd) 1759 { 1760 if (kvm_has_fpmr(vcpu->kvm)) 1761 return 0; 1762 1763 return REG_HIDDEN; 1764 } 1765 1766 static u64 sanitise_id_aa64pfr0_el1(const struct kvm_vcpu *vcpu, u64 val) 1767 { 1768 if (!vcpu_has_sve(vcpu)) 1769 val &= ~ID_AA64PFR0_EL1_SVE_MASK; 1770 1771 /* 1772 * The default is to expose CSV2 == 1 if the HW isn't affected. 1773 * Although this is a per-CPU feature, we make it global because 1774 * asymmetric systems are just a nuisance. 1775 * 1776 * Userspace can override this as long as it doesn't promise 1777 * the impossible. 1778 */ 1779 if (arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED) { 1780 val &= ~ID_AA64PFR0_EL1_CSV2_MASK; 1781 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV2, IMP); 1782 } 1783 if (arm64_get_meltdown_state() == SPECTRE_UNAFFECTED) { 1784 val &= ~ID_AA64PFR0_EL1_CSV3_MASK; 1785 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV3, IMP); 1786 } 1787 1788 if (kvm_vgic_global_state.type == VGIC_V3) { 1789 val &= ~ID_AA64PFR0_EL1_GIC_MASK; 1790 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, GIC, IMP); 1791 } 1792 1793 val &= ~ID_AA64PFR0_EL1_AMU_MASK; 1794 1795 /* 1796 * MPAM is disabled by default as KVM also needs a set of PARTID to 1797 * program the MPAMVPMx_EL2 PARTID remapping registers with. But some 1798 * older kernels let the guest see the ID bit. 1799 */ 1800 val &= ~ID_AA64PFR0_EL1_MPAM_MASK; 1801 1802 return val; 1803 } 1804 1805 #define ID_REG_LIMIT_FIELD_ENUM(val, reg, field, limit) \ 1806 ({ \ 1807 u64 __f_val = FIELD_GET(reg##_##field##_MASK, val); \ 1808 (val) &= ~reg##_##field##_MASK; \ 1809 (val) |= FIELD_PREP(reg##_##field##_MASK, \ 1810 min(__f_val, \ 1811 (u64)SYS_FIELD_VALUE(reg, field, limit))); \ 1812 (val); \ 1813 }) 1814 1815 static u64 sanitise_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, u64 val) 1816 { 1817 val = ID_REG_LIMIT_FIELD_ENUM(val, ID_AA64DFR0_EL1, DebugVer, V8P8); 1818 1819 /* 1820 * Only initialize the PMU version if the vCPU was configured with one. 1821 */ 1822 val &= ~ID_AA64DFR0_EL1_PMUVer_MASK; 1823 if (kvm_vcpu_has_pmu(vcpu)) 1824 val |= SYS_FIELD_PREP(ID_AA64DFR0_EL1, PMUVer, 1825 kvm_arm_pmu_get_pmuver_limit()); 1826 1827 /* Hide SPE from guests */ 1828 val &= ~ID_AA64DFR0_EL1_PMSVer_MASK; 1829 1830 /* Hide BRBE from guests */ 1831 val &= ~ID_AA64DFR0_EL1_BRBE_MASK; 1832 1833 return val; 1834 } 1835 1836 static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, 1837 const struct sys_reg_desc *rd, 1838 u64 val) 1839 { 1840 u8 debugver = SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, val); 1841 u8 pmuver = SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, val); 1842 1843 /* 1844 * Prior to commit 3d0dba5764b9 ("KVM: arm64: PMU: Move the 1845 * ID_AA64DFR0_EL1.PMUver limit to VM creation"), KVM erroneously 1846 * exposed an IMP_DEF PMU to userspace and the guest on systems w/ 1847 * non-architectural PMUs. Of course, PMUv3 is the only game in town for 1848 * PMU virtualization, so the IMP_DEF value was rather user-hostile. 1849 * 1850 * At minimum, we're on the hook to allow values that were given to 1851 * userspace by KVM. Cover our tracks here and replace the IMP_DEF value 1852 * with a more sensible NI. The value of an ID register changing under 1853 * the nose of the guest is unfortunate, but is certainly no more 1854 * surprising than an ill-guided PMU driver poking at impdef system 1855 * registers that end in an UNDEF... 1856 */ 1857 if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF) 1858 val &= ~ID_AA64DFR0_EL1_PMUVer_MASK; 1859 1860 /* 1861 * ID_AA64DFR0_EL1.DebugVer is one of those awkward fields with a 1862 * nonzero minimum safe value. 1863 */ 1864 if (debugver < ID_AA64DFR0_EL1_DebugVer_IMP) 1865 return -EINVAL; 1866 1867 return set_id_reg(vcpu, rd, val); 1868 } 1869 1870 static u64 read_sanitised_id_dfr0_el1(struct kvm_vcpu *vcpu, 1871 const struct sys_reg_desc *rd) 1872 { 1873 u8 perfmon = pmuver_to_perfmon(kvm_arm_pmu_get_pmuver_limit()); 1874 u64 val = read_sanitised_ftr_reg(SYS_ID_DFR0_EL1); 1875 1876 val &= ~ID_DFR0_EL1_PerfMon_MASK; 1877 if (kvm_vcpu_has_pmu(vcpu)) 1878 val |= SYS_FIELD_PREP(ID_DFR0_EL1, PerfMon, perfmon); 1879 1880 val = ID_REG_LIMIT_FIELD_ENUM(val, ID_DFR0_EL1, CopDbg, Debugv8p8); 1881 1882 return val; 1883 } 1884 1885 static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, 1886 const struct sys_reg_desc *rd, 1887 u64 val) 1888 { 1889 u8 perfmon = SYS_FIELD_GET(ID_DFR0_EL1, PerfMon, val); 1890 u8 copdbg = SYS_FIELD_GET(ID_DFR0_EL1, CopDbg, val); 1891 1892 if (perfmon == ID_DFR0_EL1_PerfMon_IMPDEF) { 1893 val &= ~ID_DFR0_EL1_PerfMon_MASK; 1894 perfmon = 0; 1895 } 1896 1897 /* 1898 * Allow DFR0_EL1.PerfMon to be set from userspace as long as 1899 * it doesn't promise more than what the HW gives us on the 1900 * AArch64 side (as everything is emulated with that), and 1901 * that this is a PMUv3. 1902 */ 1903 if (perfmon != 0 && perfmon < ID_DFR0_EL1_PerfMon_PMUv3) 1904 return -EINVAL; 1905 1906 if (copdbg < ID_DFR0_EL1_CopDbg_Armv8) 1907 return -EINVAL; 1908 1909 return set_id_reg(vcpu, rd, val); 1910 } 1911 1912 static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, 1913 const struct sys_reg_desc *rd, u64 user_val) 1914 { 1915 u64 hw_val = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1916 u64 mpam_mask = ID_AA64PFR0_EL1_MPAM_MASK; 1917 1918 /* 1919 * Commit 011e5f5bf529f ("arm64/cpufeature: Add remaining feature bits 1920 * in ID_AA64PFR0 register") exposed the MPAM field of AA64PFR0_EL1 to 1921 * guests, but didn't add trap handling. KVM doesn't support MPAM and 1922 * always returns an UNDEF for these registers. The guest must see 0 1923 * for this field. 1924 * 1925 * But KVM must also accept values from user-space that were provided 1926 * by KVM. On CPUs that support MPAM, permit user-space to write 1927 * the sanitizied value to ID_AA64PFR0_EL1.MPAM, but ignore this field. 1928 */ 1929 if ((hw_val & mpam_mask) == (user_val & mpam_mask)) 1930 user_val &= ~ID_AA64PFR0_EL1_MPAM_MASK; 1931 1932 return set_id_reg(vcpu, rd, user_val); 1933 } 1934 1935 static int set_id_aa64pfr1_el1(struct kvm_vcpu *vcpu, 1936 const struct sys_reg_desc *rd, u64 user_val) 1937 { 1938 u64 hw_val = read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1); 1939 u64 mpam_mask = ID_AA64PFR1_EL1_MPAM_frac_MASK; 1940 1941 /* See set_id_aa64pfr0_el1 for comment about MPAM */ 1942 if ((hw_val & mpam_mask) == (user_val & mpam_mask)) 1943 user_val &= ~ID_AA64PFR1_EL1_MPAM_frac_MASK; 1944 1945 return set_id_reg(vcpu, rd, user_val); 1946 } 1947 1948 static int set_ctr_el0(struct kvm_vcpu *vcpu, 1949 const struct sys_reg_desc *rd, u64 user_val) 1950 { 1951 u8 user_L1Ip = SYS_FIELD_GET(CTR_EL0, L1Ip, user_val); 1952 1953 /* 1954 * Both AIVIVT (0b01) and VPIPT (0b00) are documented as reserved. 1955 * Hence only allow to set VIPT(0b10) or PIPT(0b11) for L1Ip based 1956 * on what hardware reports. 1957 * 1958 * Using a VIPT software model on PIPT will lead to over invalidation, 1959 * but still correct. Hence, we can allow downgrading PIPT to VIPT, 1960 * but not the other way around. This is handled via arm64_ftr_safe_value() 1961 * as CTR_EL0 ftr_bits has L1Ip field with type FTR_EXACT and safe value 1962 * set as VIPT. 1963 */ 1964 switch (user_L1Ip) { 1965 case CTR_EL0_L1Ip_RESERVED_VPIPT: 1966 case CTR_EL0_L1Ip_RESERVED_AIVIVT: 1967 return -EINVAL; 1968 case CTR_EL0_L1Ip_VIPT: 1969 case CTR_EL0_L1Ip_PIPT: 1970 return set_id_reg(vcpu, rd, user_val); 1971 default: 1972 return -ENOENT; 1973 } 1974 } 1975 1976 /* 1977 * cpufeature ID register user accessors 1978 * 1979 * For now, these registers are immutable for userspace, so no values 1980 * are stored, and for set_id_reg() we don't allow the effective value 1981 * to be changed. 1982 */ 1983 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1984 u64 *val) 1985 { 1986 /* 1987 * Avoid locking if the VM has already started, as the ID registers are 1988 * guaranteed to be invariant at that point. 1989 */ 1990 if (kvm_vm_has_ran_once(vcpu->kvm)) { 1991 *val = read_id_reg(vcpu, rd); 1992 return 0; 1993 } 1994 1995 mutex_lock(&vcpu->kvm->arch.config_lock); 1996 *val = read_id_reg(vcpu, rd); 1997 mutex_unlock(&vcpu->kvm->arch.config_lock); 1998 1999 return 0; 2000 } 2001 2002 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 2003 u64 val) 2004 { 2005 u32 id = reg_to_encoding(rd); 2006 int ret; 2007 2008 mutex_lock(&vcpu->kvm->arch.config_lock); 2009 2010 /* 2011 * Once the VM has started the ID registers are immutable. Reject any 2012 * write that does not match the final register value. 2013 */ 2014 if (kvm_vm_has_ran_once(vcpu->kvm)) { 2015 if (val != read_id_reg(vcpu, rd)) 2016 ret = -EBUSY; 2017 else 2018 ret = 0; 2019 2020 mutex_unlock(&vcpu->kvm->arch.config_lock); 2021 return ret; 2022 } 2023 2024 ret = arm64_check_features(vcpu, rd, val); 2025 if (!ret) 2026 kvm_set_vm_id_reg(vcpu->kvm, id, val); 2027 2028 mutex_unlock(&vcpu->kvm->arch.config_lock); 2029 2030 /* 2031 * arm64_check_features() returns -E2BIG to indicate the register's 2032 * feature set is a superset of the maximally-allowed register value. 2033 * While it would be nice to precisely describe this to userspace, the 2034 * existing UAPI for KVM_SET_ONE_REG has it that invalid register 2035 * writes return -EINVAL. 2036 */ 2037 if (ret == -E2BIG) 2038 ret = -EINVAL; 2039 return ret; 2040 } 2041 2042 void kvm_set_vm_id_reg(struct kvm *kvm, u32 reg, u64 val) 2043 { 2044 u64 *p = __vm_id_reg(&kvm->arch, reg); 2045 2046 lockdep_assert_held(&kvm->arch.config_lock); 2047 2048 if (KVM_BUG_ON(kvm_vm_has_ran_once(kvm) || !p, kvm)) 2049 return; 2050 2051 *p = val; 2052 } 2053 2054 static int get_raz_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 2055 u64 *val) 2056 { 2057 *val = 0; 2058 return 0; 2059 } 2060 2061 static int set_wi_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 2062 u64 val) 2063 { 2064 return 0; 2065 } 2066 2067 static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2068 const struct sys_reg_desc *r) 2069 { 2070 if (p->is_write) 2071 return write_to_read_only(vcpu, p, r); 2072 2073 p->regval = kvm_read_vm_id_reg(vcpu->kvm, SYS_CTR_EL0); 2074 return true; 2075 } 2076 2077 static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2078 const struct sys_reg_desc *r) 2079 { 2080 if (p->is_write) 2081 return write_to_read_only(vcpu, p, r); 2082 2083 p->regval = __vcpu_sys_reg(vcpu, r->reg); 2084 return true; 2085 } 2086 2087 /* 2088 * Fabricate a CLIDR_EL1 value instead of using the real value, which can vary 2089 * by the physical CPU which the vcpu currently resides in. 2090 */ 2091 static u64 reset_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 2092 { 2093 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0); 2094 u64 clidr; 2095 u8 loc; 2096 2097 if ((ctr_el0 & CTR_EL0_IDC)) { 2098 /* 2099 * Data cache clean to the PoU is not required so LoUU and LoUIS 2100 * will not be set and a unified cache, which will be marked as 2101 * LoC, will be added. 2102 * 2103 * If not DIC, let the unified cache L2 so that an instruction 2104 * cache can be added as L1 later. 2105 */ 2106 loc = (ctr_el0 & CTR_EL0_DIC) ? 1 : 2; 2107 clidr = CACHE_TYPE_UNIFIED << CLIDR_CTYPE_SHIFT(loc); 2108 } else { 2109 /* 2110 * Data cache clean to the PoU is required so let L1 have a data 2111 * cache and mark it as LoUU and LoUIS. As L1 has a data cache, 2112 * it can be marked as LoC too. 2113 */ 2114 loc = 1; 2115 clidr = 1 << CLIDR_LOUU_SHIFT; 2116 clidr |= 1 << CLIDR_LOUIS_SHIFT; 2117 clidr |= CACHE_TYPE_DATA << CLIDR_CTYPE_SHIFT(1); 2118 } 2119 2120 /* 2121 * Instruction cache invalidation to the PoU is required so let L1 have 2122 * an instruction cache. If L1 already has a data cache, it will be 2123 * CACHE_TYPE_SEPARATE. 2124 */ 2125 if (!(ctr_el0 & CTR_EL0_DIC)) 2126 clidr |= CACHE_TYPE_INST << CLIDR_CTYPE_SHIFT(1); 2127 2128 clidr |= loc << CLIDR_LOC_SHIFT; 2129 2130 /* 2131 * Add tag cache unified to data cache. Allocation tags and data are 2132 * unified in a cache line so that it looks valid even if there is only 2133 * one cache line. 2134 */ 2135 if (kvm_has_mte(vcpu->kvm)) 2136 clidr |= 2ULL << CLIDR_TTYPE_SHIFT(loc); 2137 2138 __vcpu_sys_reg(vcpu, r->reg) = clidr; 2139 2140 return __vcpu_sys_reg(vcpu, r->reg); 2141 } 2142 2143 static int set_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 2144 u64 val) 2145 { 2146 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0); 2147 u64 idc = !CLIDR_LOC(val) || (!CLIDR_LOUIS(val) && !CLIDR_LOUU(val)); 2148 2149 if ((val & CLIDR_EL1_RES0) || (!(ctr_el0 & CTR_EL0_IDC) && idc)) 2150 return -EINVAL; 2151 2152 __vcpu_sys_reg(vcpu, rd->reg) = val; 2153 2154 return 0; 2155 } 2156 2157 static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2158 const struct sys_reg_desc *r) 2159 { 2160 int reg = r->reg; 2161 2162 if (p->is_write) 2163 vcpu_write_sys_reg(vcpu, p->regval, reg); 2164 else 2165 p->regval = vcpu_read_sys_reg(vcpu, reg); 2166 return true; 2167 } 2168 2169 static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2170 const struct sys_reg_desc *r) 2171 { 2172 u32 csselr; 2173 2174 if (p->is_write) 2175 return write_to_read_only(vcpu, p, r); 2176 2177 csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1); 2178 csselr &= CSSELR_EL1_Level | CSSELR_EL1_InD; 2179 if (csselr < CSSELR_MAX) 2180 p->regval = get_ccsidr(vcpu, csselr); 2181 2182 return true; 2183 } 2184 2185 static unsigned int mte_visibility(const struct kvm_vcpu *vcpu, 2186 const struct sys_reg_desc *rd) 2187 { 2188 if (kvm_has_mte(vcpu->kvm)) 2189 return 0; 2190 2191 return REG_HIDDEN; 2192 } 2193 2194 #define MTE_REG(name) { \ 2195 SYS_DESC(SYS_##name), \ 2196 .access = undef_access, \ 2197 .reset = reset_unknown, \ 2198 .reg = name, \ 2199 .visibility = mte_visibility, \ 2200 } 2201 2202 static unsigned int el2_visibility(const struct kvm_vcpu *vcpu, 2203 const struct sys_reg_desc *rd) 2204 { 2205 if (vcpu_has_nv(vcpu)) 2206 return 0; 2207 2208 return REG_HIDDEN; 2209 } 2210 2211 static bool bad_vncr_trap(struct kvm_vcpu *vcpu, 2212 struct sys_reg_params *p, 2213 const struct sys_reg_desc *r) 2214 { 2215 /* 2216 * We really shouldn't be here, and this is likely the result 2217 * of a misconfigured trap, as this register should target the 2218 * VNCR page, and nothing else. 2219 */ 2220 return bad_trap(vcpu, p, r, 2221 "trap of VNCR-backed register"); 2222 } 2223 2224 static bool bad_redir_trap(struct kvm_vcpu *vcpu, 2225 struct sys_reg_params *p, 2226 const struct sys_reg_desc *r) 2227 { 2228 /* 2229 * We really shouldn't be here, and this is likely the result 2230 * of a misconfigured trap, as this register should target the 2231 * corresponding EL1, and nothing else. 2232 */ 2233 return bad_trap(vcpu, p, r, 2234 "trap of EL2 register redirected to EL1"); 2235 } 2236 2237 #define EL2_REG(name, acc, rst, v) { \ 2238 SYS_DESC(SYS_##name), \ 2239 .access = acc, \ 2240 .reset = rst, \ 2241 .reg = name, \ 2242 .visibility = el2_visibility, \ 2243 .val = v, \ 2244 } 2245 2246 #define EL2_REG_FILTERED(name, acc, rst, v, filter) { \ 2247 SYS_DESC(SYS_##name), \ 2248 .access = acc, \ 2249 .reset = rst, \ 2250 .reg = name, \ 2251 .visibility = filter, \ 2252 .val = v, \ 2253 } 2254 2255 #define EL2_REG_VNCR(name, rst, v) EL2_REG(name, bad_vncr_trap, rst, v) 2256 #define EL2_REG_REDIR(name, rst, v) EL2_REG(name, bad_redir_trap, rst, v) 2257 2258 /* 2259 * Since reset() callback and field val are not used for idregs, they will be 2260 * used for specific purposes for idregs. 2261 * The reset() would return KVM sanitised register value. The value would be the 2262 * same as the host kernel sanitised value if there is no KVM sanitisation. 2263 * The val would be used as a mask indicating writable fields for the idreg. 2264 * Only bits with 1 are writable from userspace. This mask might not be 2265 * necessary in the future whenever all ID registers are enabled as writable 2266 * from userspace. 2267 */ 2268 2269 #define ID_DESC(name) \ 2270 SYS_DESC(SYS_##name), \ 2271 .access = access_id_reg, \ 2272 .get_user = get_id_reg \ 2273 2274 /* sys_reg_desc initialiser for known cpufeature ID registers */ 2275 #define ID_SANITISED(name) { \ 2276 ID_DESC(name), \ 2277 .set_user = set_id_reg, \ 2278 .visibility = id_visibility, \ 2279 .reset = kvm_read_sanitised_id_reg, \ 2280 .val = 0, \ 2281 } 2282 2283 /* sys_reg_desc initialiser for known cpufeature ID registers */ 2284 #define AA32_ID_SANITISED(name) { \ 2285 ID_DESC(name), \ 2286 .set_user = set_id_reg, \ 2287 .visibility = aa32_id_visibility, \ 2288 .reset = kvm_read_sanitised_id_reg, \ 2289 .val = 0, \ 2290 } 2291 2292 /* sys_reg_desc initialiser for writable ID registers */ 2293 #define ID_WRITABLE(name, mask) { \ 2294 ID_DESC(name), \ 2295 .set_user = set_id_reg, \ 2296 .visibility = id_visibility, \ 2297 .reset = kvm_read_sanitised_id_reg, \ 2298 .val = mask, \ 2299 } 2300 2301 /* sys_reg_desc initialiser for cpufeature ID registers that need filtering */ 2302 #define ID_FILTERED(sysreg, name, mask) { \ 2303 ID_DESC(sysreg), \ 2304 .set_user = set_##name, \ 2305 .visibility = id_visibility, \ 2306 .reset = kvm_read_sanitised_id_reg, \ 2307 .val = (mask), \ 2308 } 2309 2310 /* 2311 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID 2312 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2 2313 * (1 <= crm < 8, 0 <= Op2 < 8). 2314 */ 2315 #define ID_UNALLOCATED(crm, op2) { \ 2316 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \ 2317 .access = access_id_reg, \ 2318 .get_user = get_id_reg, \ 2319 .set_user = set_id_reg, \ 2320 .visibility = raz_visibility, \ 2321 .reset = kvm_read_sanitised_id_reg, \ 2322 .val = 0, \ 2323 } 2324 2325 /* 2326 * sys_reg_desc initialiser for known ID registers that we hide from guests. 2327 * For now, these are exposed just like unallocated ID regs: they appear 2328 * RAZ for the guest. 2329 */ 2330 #define ID_HIDDEN(name) { \ 2331 ID_DESC(name), \ 2332 .set_user = set_id_reg, \ 2333 .visibility = raz_visibility, \ 2334 .reset = kvm_read_sanitised_id_reg, \ 2335 .val = 0, \ 2336 } 2337 2338 static bool access_sp_el1(struct kvm_vcpu *vcpu, 2339 struct sys_reg_params *p, 2340 const struct sys_reg_desc *r) 2341 { 2342 if (p->is_write) 2343 __vcpu_sys_reg(vcpu, SP_EL1) = p->regval; 2344 else 2345 p->regval = __vcpu_sys_reg(vcpu, SP_EL1); 2346 2347 return true; 2348 } 2349 2350 static bool access_elr(struct kvm_vcpu *vcpu, 2351 struct sys_reg_params *p, 2352 const struct sys_reg_desc *r) 2353 { 2354 if (p->is_write) 2355 vcpu_write_sys_reg(vcpu, p->regval, ELR_EL1); 2356 else 2357 p->regval = vcpu_read_sys_reg(vcpu, ELR_EL1); 2358 2359 return true; 2360 } 2361 2362 static bool access_spsr(struct kvm_vcpu *vcpu, 2363 struct sys_reg_params *p, 2364 const struct sys_reg_desc *r) 2365 { 2366 if (p->is_write) 2367 __vcpu_sys_reg(vcpu, SPSR_EL1) = p->regval; 2368 else 2369 p->regval = __vcpu_sys_reg(vcpu, SPSR_EL1); 2370 2371 return true; 2372 } 2373 2374 static bool access_cntkctl_el12(struct kvm_vcpu *vcpu, 2375 struct sys_reg_params *p, 2376 const struct sys_reg_desc *r) 2377 { 2378 if (p->is_write) 2379 __vcpu_sys_reg(vcpu, CNTKCTL_EL1) = p->regval; 2380 else 2381 p->regval = __vcpu_sys_reg(vcpu, CNTKCTL_EL1); 2382 2383 return true; 2384 } 2385 2386 static u64 reset_hcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 2387 { 2388 u64 val = r->val; 2389 2390 if (!cpus_have_final_cap(ARM64_HAS_HCR_NV1)) 2391 val |= HCR_E2H; 2392 2393 return __vcpu_sys_reg(vcpu, r->reg) = val; 2394 } 2395 2396 static unsigned int __el2_visibility(const struct kvm_vcpu *vcpu, 2397 const struct sys_reg_desc *rd, 2398 unsigned int (*fn)(const struct kvm_vcpu *, 2399 const struct sys_reg_desc *)) 2400 { 2401 return el2_visibility(vcpu, rd) ?: fn(vcpu, rd); 2402 } 2403 2404 static unsigned int sve_el2_visibility(const struct kvm_vcpu *vcpu, 2405 const struct sys_reg_desc *rd) 2406 { 2407 return __el2_visibility(vcpu, rd, sve_visibility); 2408 } 2409 2410 static bool access_zcr_el2(struct kvm_vcpu *vcpu, 2411 struct sys_reg_params *p, 2412 const struct sys_reg_desc *r) 2413 { 2414 unsigned int vq; 2415 2416 if (guest_hyp_sve_traps_enabled(vcpu)) { 2417 kvm_inject_nested_sve_trap(vcpu); 2418 return true; 2419 } 2420 2421 if (!p->is_write) { 2422 p->regval = vcpu_read_sys_reg(vcpu, ZCR_EL2); 2423 return true; 2424 } 2425 2426 vq = SYS_FIELD_GET(ZCR_ELx, LEN, p->regval) + 1; 2427 vq = min(vq, vcpu_sve_max_vq(vcpu)); 2428 vcpu_write_sys_reg(vcpu, vq - 1, ZCR_EL2); 2429 return true; 2430 } 2431 2432 static unsigned int s1poe_visibility(const struct kvm_vcpu *vcpu, 2433 const struct sys_reg_desc *rd) 2434 { 2435 if (kvm_has_s1poe(vcpu->kvm)) 2436 return 0; 2437 2438 return REG_HIDDEN; 2439 } 2440 2441 static unsigned int s1poe_el2_visibility(const struct kvm_vcpu *vcpu, 2442 const struct sys_reg_desc *rd) 2443 { 2444 return __el2_visibility(vcpu, rd, s1poe_visibility); 2445 } 2446 2447 static unsigned int tcr2_visibility(const struct kvm_vcpu *vcpu, 2448 const struct sys_reg_desc *rd) 2449 { 2450 if (kvm_has_tcr2(vcpu->kvm)) 2451 return 0; 2452 2453 return REG_HIDDEN; 2454 } 2455 2456 static unsigned int tcr2_el2_visibility(const struct kvm_vcpu *vcpu, 2457 const struct sys_reg_desc *rd) 2458 { 2459 return __el2_visibility(vcpu, rd, tcr2_visibility); 2460 } 2461 2462 static unsigned int s1pie_visibility(const struct kvm_vcpu *vcpu, 2463 const struct sys_reg_desc *rd) 2464 { 2465 if (kvm_has_s1pie(vcpu->kvm)) 2466 return 0; 2467 2468 return REG_HIDDEN; 2469 } 2470 2471 static unsigned int s1pie_el2_visibility(const struct kvm_vcpu *vcpu, 2472 const struct sys_reg_desc *rd) 2473 { 2474 return __el2_visibility(vcpu, rd, s1pie_visibility); 2475 } 2476 2477 static bool access_mdcr(struct kvm_vcpu *vcpu, 2478 struct sys_reg_params *p, 2479 const struct sys_reg_desc *r) 2480 { 2481 u64 old = __vcpu_sys_reg(vcpu, MDCR_EL2); 2482 2483 if (!access_rw(vcpu, p, r)) 2484 return false; 2485 2486 /* 2487 * Request a reload of the PMU to enable/disable the counters affected 2488 * by HPME. 2489 */ 2490 if ((old ^ __vcpu_sys_reg(vcpu, MDCR_EL2)) & MDCR_EL2_HPME) 2491 kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu); 2492 2493 return true; 2494 } 2495 2496 2497 /* 2498 * Architected system registers. 2499 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2 2500 * 2501 * Debug handling: We do trap most, if not all debug related system 2502 * registers. The implementation is good enough to ensure that a guest 2503 * can use these with minimal performance degradation. The drawback is 2504 * that we don't implement any of the external debug architecture. 2505 * This should be revisited if we ever encounter a more demanding 2506 * guest... 2507 */ 2508 static const struct sys_reg_desc sys_reg_descs[] = { 2509 DBG_BCR_BVR_WCR_WVR_EL1(0), 2510 DBG_BCR_BVR_WCR_WVR_EL1(1), 2511 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 }, 2512 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 }, 2513 DBG_BCR_BVR_WCR_WVR_EL1(2), 2514 DBG_BCR_BVR_WCR_WVR_EL1(3), 2515 DBG_BCR_BVR_WCR_WVR_EL1(4), 2516 DBG_BCR_BVR_WCR_WVR_EL1(5), 2517 DBG_BCR_BVR_WCR_WVR_EL1(6), 2518 DBG_BCR_BVR_WCR_WVR_EL1(7), 2519 DBG_BCR_BVR_WCR_WVR_EL1(8), 2520 DBG_BCR_BVR_WCR_WVR_EL1(9), 2521 DBG_BCR_BVR_WCR_WVR_EL1(10), 2522 DBG_BCR_BVR_WCR_WVR_EL1(11), 2523 DBG_BCR_BVR_WCR_WVR_EL1(12), 2524 DBG_BCR_BVR_WCR_WVR_EL1(13), 2525 DBG_BCR_BVR_WCR_WVR_EL1(14), 2526 DBG_BCR_BVR_WCR_WVR_EL1(15), 2527 2528 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi }, 2529 { SYS_DESC(SYS_OSLAR_EL1), trap_oslar_el1 }, 2530 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1, 2531 OSLSR_EL1_OSLM_IMPLEMENTED, .set_user = set_oslsr_el1, }, 2532 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi }, 2533 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi }, 2534 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi }, 2535 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi }, 2536 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 }, 2537 2538 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi }, 2539 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi }, 2540 // DBGDTR[TR]X_EL0 share the same encoding 2541 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi }, 2542 2543 { SYS_DESC(SYS_DBGVCR32_EL2), undef_access, reset_val, DBGVCR32_EL2, 0 }, 2544 2545 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 }, 2546 2547 /* 2548 * ID regs: all ID_SANITISED() entries here must have corresponding 2549 * entries in arm64_ftr_regs[]. 2550 */ 2551 2552 /* AArch64 mappings of the AArch32 ID registers */ 2553 /* CRm=1 */ 2554 AA32_ID_SANITISED(ID_PFR0_EL1), 2555 AA32_ID_SANITISED(ID_PFR1_EL1), 2556 { SYS_DESC(SYS_ID_DFR0_EL1), 2557 .access = access_id_reg, 2558 .get_user = get_id_reg, 2559 .set_user = set_id_dfr0_el1, 2560 .visibility = aa32_id_visibility, 2561 .reset = read_sanitised_id_dfr0_el1, 2562 .val = ID_DFR0_EL1_PerfMon_MASK | 2563 ID_DFR0_EL1_CopDbg_MASK, }, 2564 ID_HIDDEN(ID_AFR0_EL1), 2565 AA32_ID_SANITISED(ID_MMFR0_EL1), 2566 AA32_ID_SANITISED(ID_MMFR1_EL1), 2567 AA32_ID_SANITISED(ID_MMFR2_EL1), 2568 AA32_ID_SANITISED(ID_MMFR3_EL1), 2569 2570 /* CRm=2 */ 2571 AA32_ID_SANITISED(ID_ISAR0_EL1), 2572 AA32_ID_SANITISED(ID_ISAR1_EL1), 2573 AA32_ID_SANITISED(ID_ISAR2_EL1), 2574 AA32_ID_SANITISED(ID_ISAR3_EL1), 2575 AA32_ID_SANITISED(ID_ISAR4_EL1), 2576 AA32_ID_SANITISED(ID_ISAR5_EL1), 2577 AA32_ID_SANITISED(ID_MMFR4_EL1), 2578 AA32_ID_SANITISED(ID_ISAR6_EL1), 2579 2580 /* CRm=3 */ 2581 AA32_ID_SANITISED(MVFR0_EL1), 2582 AA32_ID_SANITISED(MVFR1_EL1), 2583 AA32_ID_SANITISED(MVFR2_EL1), 2584 ID_UNALLOCATED(3,3), 2585 AA32_ID_SANITISED(ID_PFR2_EL1), 2586 ID_HIDDEN(ID_DFR1_EL1), 2587 AA32_ID_SANITISED(ID_MMFR5_EL1), 2588 ID_UNALLOCATED(3,7), 2589 2590 /* AArch64 ID registers */ 2591 /* CRm=4 */ 2592 ID_FILTERED(ID_AA64PFR0_EL1, id_aa64pfr0_el1, 2593 ~(ID_AA64PFR0_EL1_AMU | 2594 ID_AA64PFR0_EL1_MPAM | 2595 ID_AA64PFR0_EL1_SVE | 2596 ID_AA64PFR0_EL1_RAS | 2597 ID_AA64PFR0_EL1_AdvSIMD | 2598 ID_AA64PFR0_EL1_FP)), 2599 ID_FILTERED(ID_AA64PFR1_EL1, id_aa64pfr1_el1, 2600 ~(ID_AA64PFR1_EL1_PFAR | 2601 ID_AA64PFR1_EL1_DF2 | 2602 ID_AA64PFR1_EL1_MTEX | 2603 ID_AA64PFR1_EL1_THE | 2604 ID_AA64PFR1_EL1_GCS | 2605 ID_AA64PFR1_EL1_MTE_frac | 2606 ID_AA64PFR1_EL1_NMI | 2607 ID_AA64PFR1_EL1_RNDR_trap | 2608 ID_AA64PFR1_EL1_SME | 2609 ID_AA64PFR1_EL1_RES0 | 2610 ID_AA64PFR1_EL1_MPAM_frac | 2611 ID_AA64PFR1_EL1_RAS_frac | 2612 ID_AA64PFR1_EL1_MTE)), 2613 ID_WRITABLE(ID_AA64PFR2_EL1, ID_AA64PFR2_EL1_FPMR), 2614 ID_UNALLOCATED(4,3), 2615 ID_WRITABLE(ID_AA64ZFR0_EL1, ~ID_AA64ZFR0_EL1_RES0), 2616 ID_HIDDEN(ID_AA64SMFR0_EL1), 2617 ID_UNALLOCATED(4,6), 2618 ID_WRITABLE(ID_AA64FPFR0_EL1, ~ID_AA64FPFR0_EL1_RES0), 2619 2620 /* CRm=5 */ 2621 /* 2622 * Prior to FEAT_Debugv8.9, the architecture defines context-aware 2623 * breakpoints (CTX_CMPs) as the highest numbered breakpoints (BRPs). 2624 * KVM does not trap + emulate the breakpoint registers, and as such 2625 * cannot support a layout that misaligns with the underlying hardware. 2626 * While it may be possible to describe a subset that aligns with 2627 * hardware, just prevent changes to BRPs and CTX_CMPs altogether for 2628 * simplicity. 2629 * 2630 * See DDI0487K.a, section D2.8.3 Breakpoint types and linking 2631 * of breakpoints for more details. 2632 */ 2633 ID_FILTERED(ID_AA64DFR0_EL1, id_aa64dfr0_el1, 2634 ID_AA64DFR0_EL1_DoubleLock_MASK | 2635 ID_AA64DFR0_EL1_WRPs_MASK | 2636 ID_AA64DFR0_EL1_PMUVer_MASK | 2637 ID_AA64DFR0_EL1_DebugVer_MASK), 2638 ID_SANITISED(ID_AA64DFR1_EL1), 2639 ID_UNALLOCATED(5,2), 2640 ID_UNALLOCATED(5,3), 2641 ID_HIDDEN(ID_AA64AFR0_EL1), 2642 ID_HIDDEN(ID_AA64AFR1_EL1), 2643 ID_UNALLOCATED(5,6), 2644 ID_UNALLOCATED(5,7), 2645 2646 /* CRm=6 */ 2647 ID_WRITABLE(ID_AA64ISAR0_EL1, ~ID_AA64ISAR0_EL1_RES0), 2648 ID_WRITABLE(ID_AA64ISAR1_EL1, ~(ID_AA64ISAR1_EL1_GPI | 2649 ID_AA64ISAR1_EL1_GPA | 2650 ID_AA64ISAR1_EL1_API | 2651 ID_AA64ISAR1_EL1_APA)), 2652 ID_WRITABLE(ID_AA64ISAR2_EL1, ~(ID_AA64ISAR2_EL1_RES0 | 2653 ID_AA64ISAR2_EL1_APA3 | 2654 ID_AA64ISAR2_EL1_GPA3)), 2655 ID_WRITABLE(ID_AA64ISAR3_EL1, (ID_AA64ISAR3_EL1_FPRCVT | 2656 ID_AA64ISAR3_EL1_FAMINMAX)), 2657 ID_UNALLOCATED(6,4), 2658 ID_UNALLOCATED(6,5), 2659 ID_UNALLOCATED(6,6), 2660 ID_UNALLOCATED(6,7), 2661 2662 /* CRm=7 */ 2663 ID_WRITABLE(ID_AA64MMFR0_EL1, ~(ID_AA64MMFR0_EL1_RES0 | 2664 ID_AA64MMFR0_EL1_TGRAN4_2 | 2665 ID_AA64MMFR0_EL1_TGRAN64_2 | 2666 ID_AA64MMFR0_EL1_TGRAN16_2 | 2667 ID_AA64MMFR0_EL1_ASIDBITS)), 2668 ID_WRITABLE(ID_AA64MMFR1_EL1, ~(ID_AA64MMFR1_EL1_RES0 | 2669 ID_AA64MMFR1_EL1_HCX | 2670 ID_AA64MMFR1_EL1_TWED | 2671 ID_AA64MMFR1_EL1_XNX | 2672 ID_AA64MMFR1_EL1_VH | 2673 ID_AA64MMFR1_EL1_VMIDBits)), 2674 ID_WRITABLE(ID_AA64MMFR2_EL1, ~(ID_AA64MMFR2_EL1_RES0 | 2675 ID_AA64MMFR2_EL1_EVT | 2676 ID_AA64MMFR2_EL1_FWB | 2677 ID_AA64MMFR2_EL1_IDS | 2678 ID_AA64MMFR2_EL1_NV | 2679 ID_AA64MMFR2_EL1_CCIDX)), 2680 ID_WRITABLE(ID_AA64MMFR3_EL1, (ID_AA64MMFR3_EL1_TCRX | 2681 ID_AA64MMFR3_EL1_S1PIE | 2682 ID_AA64MMFR3_EL1_S1POE)), 2683 ID_SANITISED(ID_AA64MMFR4_EL1), 2684 ID_UNALLOCATED(7,5), 2685 ID_UNALLOCATED(7,6), 2686 ID_UNALLOCATED(7,7), 2687 2688 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 }, 2689 { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 }, 2690 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 }, 2691 2692 MTE_REG(RGSR_EL1), 2693 MTE_REG(GCR_EL1), 2694 2695 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility }, 2696 { SYS_DESC(SYS_TRFCR_EL1), undef_access }, 2697 { SYS_DESC(SYS_SMPRI_EL1), undef_access }, 2698 { SYS_DESC(SYS_SMCR_EL1), undef_access }, 2699 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 }, 2700 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 }, 2701 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 }, 2702 { SYS_DESC(SYS_TCR2_EL1), access_vm_reg, reset_val, TCR2_EL1, 0, 2703 .visibility = tcr2_visibility }, 2704 2705 PTRAUTH_KEY(APIA), 2706 PTRAUTH_KEY(APIB), 2707 PTRAUTH_KEY(APDA), 2708 PTRAUTH_KEY(APDB), 2709 PTRAUTH_KEY(APGA), 2710 2711 { SYS_DESC(SYS_SPSR_EL1), access_spsr}, 2712 { SYS_DESC(SYS_ELR_EL1), access_elr}, 2713 2714 { SYS_DESC(SYS_ICC_PMR_EL1), undef_access }, 2715 2716 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 }, 2717 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 }, 2718 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 }, 2719 2720 { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi }, 2721 { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi }, 2722 { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi }, 2723 { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi }, 2724 { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi }, 2725 { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi }, 2726 { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi }, 2727 { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi }, 2728 2729 MTE_REG(TFSR_EL1), 2730 MTE_REG(TFSRE0_EL1), 2731 2732 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 }, 2733 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 }, 2734 2735 { SYS_DESC(SYS_PMSCR_EL1), undef_access }, 2736 { SYS_DESC(SYS_PMSNEVFR_EL1), undef_access }, 2737 { SYS_DESC(SYS_PMSICR_EL1), undef_access }, 2738 { SYS_DESC(SYS_PMSIRR_EL1), undef_access }, 2739 { SYS_DESC(SYS_PMSFCR_EL1), undef_access }, 2740 { SYS_DESC(SYS_PMSEVFR_EL1), undef_access }, 2741 { SYS_DESC(SYS_PMSLATFR_EL1), undef_access }, 2742 { SYS_DESC(SYS_PMSIDR_EL1), undef_access }, 2743 { SYS_DESC(SYS_PMBLIMITR_EL1), undef_access }, 2744 { SYS_DESC(SYS_PMBPTR_EL1), undef_access }, 2745 { SYS_DESC(SYS_PMBSR_EL1), undef_access }, 2746 /* PMBIDR_EL1 is not trapped */ 2747 2748 { PMU_SYS_REG(PMINTENSET_EL1), 2749 .access = access_pminten, .reg = PMINTENSET_EL1, 2750 .get_user = get_pmreg, .set_user = set_pmreg }, 2751 { PMU_SYS_REG(PMINTENCLR_EL1), 2752 .access = access_pminten, .reg = PMINTENSET_EL1, 2753 .get_user = get_pmreg, .set_user = set_pmreg }, 2754 { SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi }, 2755 2756 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 }, 2757 { SYS_DESC(SYS_PIRE0_EL1), NULL, reset_unknown, PIRE0_EL1, 2758 .visibility = s1pie_visibility }, 2759 { SYS_DESC(SYS_PIR_EL1), NULL, reset_unknown, PIR_EL1, 2760 .visibility = s1pie_visibility }, 2761 { SYS_DESC(SYS_POR_EL1), NULL, reset_unknown, POR_EL1, 2762 .visibility = s1poe_visibility }, 2763 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 }, 2764 2765 { SYS_DESC(SYS_LORSA_EL1), trap_loregion }, 2766 { SYS_DESC(SYS_LOREA_EL1), trap_loregion }, 2767 { SYS_DESC(SYS_LORN_EL1), trap_loregion }, 2768 { SYS_DESC(SYS_LORC_EL1), trap_loregion }, 2769 { SYS_DESC(SYS_MPAMIDR_EL1), undef_access }, 2770 { SYS_DESC(SYS_LORID_EL1), trap_loregion }, 2771 2772 { SYS_DESC(SYS_MPAM1_EL1), undef_access }, 2773 { SYS_DESC(SYS_MPAM0_EL1), undef_access }, 2774 { SYS_DESC(SYS_VBAR_EL1), access_rw, reset_val, VBAR_EL1, 0 }, 2775 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 }, 2776 2777 { SYS_DESC(SYS_ICC_IAR0_EL1), undef_access }, 2778 { SYS_DESC(SYS_ICC_EOIR0_EL1), undef_access }, 2779 { SYS_DESC(SYS_ICC_HPPIR0_EL1), undef_access }, 2780 { SYS_DESC(SYS_ICC_BPR0_EL1), undef_access }, 2781 { SYS_DESC(SYS_ICC_AP0R0_EL1), undef_access }, 2782 { SYS_DESC(SYS_ICC_AP0R1_EL1), undef_access }, 2783 { SYS_DESC(SYS_ICC_AP0R2_EL1), undef_access }, 2784 { SYS_DESC(SYS_ICC_AP0R3_EL1), undef_access }, 2785 { SYS_DESC(SYS_ICC_AP1R0_EL1), undef_access }, 2786 { SYS_DESC(SYS_ICC_AP1R1_EL1), undef_access }, 2787 { SYS_DESC(SYS_ICC_AP1R2_EL1), undef_access }, 2788 { SYS_DESC(SYS_ICC_AP1R3_EL1), undef_access }, 2789 { SYS_DESC(SYS_ICC_DIR_EL1), undef_access }, 2790 { SYS_DESC(SYS_ICC_RPR_EL1), undef_access }, 2791 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi }, 2792 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi }, 2793 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi }, 2794 { SYS_DESC(SYS_ICC_IAR1_EL1), undef_access }, 2795 { SYS_DESC(SYS_ICC_EOIR1_EL1), undef_access }, 2796 { SYS_DESC(SYS_ICC_HPPIR1_EL1), undef_access }, 2797 { SYS_DESC(SYS_ICC_BPR1_EL1), undef_access }, 2798 { SYS_DESC(SYS_ICC_CTLR_EL1), undef_access }, 2799 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre }, 2800 { SYS_DESC(SYS_ICC_IGRPEN0_EL1), undef_access }, 2801 { SYS_DESC(SYS_ICC_IGRPEN1_EL1), undef_access }, 2802 2803 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 }, 2804 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 }, 2805 2806 { SYS_DESC(SYS_ACCDATA_EL1), undef_access }, 2807 2808 { SYS_DESC(SYS_SCXTNUM_EL1), undef_access }, 2809 2810 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0}, 2811 2812 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr }, 2813 { SYS_DESC(SYS_CLIDR_EL1), access_clidr, reset_clidr, CLIDR_EL1, 2814 .set_user = set_clidr, .val = ~CLIDR_EL1_RES0 }, 2815 { SYS_DESC(SYS_CCSIDR2_EL1), undef_access }, 2816 { SYS_DESC(SYS_SMIDR_EL1), undef_access }, 2817 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, 2818 ID_FILTERED(CTR_EL0, ctr_el0, 2819 CTR_EL0_DIC_MASK | 2820 CTR_EL0_IDC_MASK | 2821 CTR_EL0_DminLine_MASK | 2822 CTR_EL0_L1Ip_MASK | 2823 CTR_EL0_IminLine_MASK), 2824 { SYS_DESC(SYS_SVCR), undef_access, reset_val, SVCR, 0, .visibility = sme_visibility }, 2825 { SYS_DESC(SYS_FPMR), undef_access, reset_val, FPMR, 0, .visibility = fp8_visibility }, 2826 2827 { PMU_SYS_REG(PMCR_EL0), .access = access_pmcr, .reset = reset_pmcr, 2828 .reg = PMCR_EL0, .get_user = get_pmcr, .set_user = set_pmcr }, 2829 { PMU_SYS_REG(PMCNTENSET_EL0), 2830 .access = access_pmcnten, .reg = PMCNTENSET_EL0, 2831 .get_user = get_pmreg, .set_user = set_pmreg }, 2832 { PMU_SYS_REG(PMCNTENCLR_EL0), 2833 .access = access_pmcnten, .reg = PMCNTENSET_EL0, 2834 .get_user = get_pmreg, .set_user = set_pmreg }, 2835 { PMU_SYS_REG(PMOVSCLR_EL0), 2836 .access = access_pmovs, .reg = PMOVSSET_EL0, 2837 .get_user = get_pmreg, .set_user = set_pmreg }, 2838 /* 2839 * PM_SWINC_EL0 is exposed to userspace as RAZ/WI, as it was 2840 * previously (and pointlessly) advertised in the past... 2841 */ 2842 { PMU_SYS_REG(PMSWINC_EL0), 2843 .get_user = get_raz_reg, .set_user = set_wi_reg, 2844 .access = access_pmswinc, .reset = NULL }, 2845 { PMU_SYS_REG(PMSELR_EL0), 2846 .access = access_pmselr, .reset = reset_pmselr, .reg = PMSELR_EL0 }, 2847 { PMU_SYS_REG(PMCEID0_EL0), 2848 .access = access_pmceid, .reset = NULL }, 2849 { PMU_SYS_REG(PMCEID1_EL0), 2850 .access = access_pmceid, .reset = NULL }, 2851 { PMU_SYS_REG(PMCCNTR_EL0), 2852 .access = access_pmu_evcntr, .reset = reset_unknown, 2853 .reg = PMCCNTR_EL0, .get_user = get_pmu_evcntr}, 2854 { PMU_SYS_REG(PMXEVTYPER_EL0), 2855 .access = access_pmu_evtyper, .reset = NULL }, 2856 { PMU_SYS_REG(PMXEVCNTR_EL0), 2857 .access = access_pmu_evcntr, .reset = NULL }, 2858 /* 2859 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero 2860 * in 32bit mode. Here we choose to reset it as zero for consistency. 2861 */ 2862 { PMU_SYS_REG(PMUSERENR_EL0), .access = access_pmuserenr, 2863 .reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 }, 2864 { PMU_SYS_REG(PMOVSSET_EL0), 2865 .access = access_pmovs, .reg = PMOVSSET_EL0, 2866 .get_user = get_pmreg, .set_user = set_pmreg }, 2867 2868 { SYS_DESC(SYS_POR_EL0), NULL, reset_unknown, POR_EL0, 2869 .visibility = s1poe_visibility }, 2870 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 }, 2871 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 }, 2872 { SYS_DESC(SYS_TPIDR2_EL0), undef_access }, 2873 2874 { SYS_DESC(SYS_SCXTNUM_EL0), undef_access }, 2875 2876 { SYS_DESC(SYS_AMCR_EL0), undef_access }, 2877 { SYS_DESC(SYS_AMCFGR_EL0), undef_access }, 2878 { SYS_DESC(SYS_AMCGCR_EL0), undef_access }, 2879 { SYS_DESC(SYS_AMUSERENR_EL0), undef_access }, 2880 { SYS_DESC(SYS_AMCNTENCLR0_EL0), undef_access }, 2881 { SYS_DESC(SYS_AMCNTENSET0_EL0), undef_access }, 2882 { SYS_DESC(SYS_AMCNTENCLR1_EL0), undef_access }, 2883 { SYS_DESC(SYS_AMCNTENSET1_EL0), undef_access }, 2884 AMU_AMEVCNTR0_EL0(0), 2885 AMU_AMEVCNTR0_EL0(1), 2886 AMU_AMEVCNTR0_EL0(2), 2887 AMU_AMEVCNTR0_EL0(3), 2888 AMU_AMEVCNTR0_EL0(4), 2889 AMU_AMEVCNTR0_EL0(5), 2890 AMU_AMEVCNTR0_EL0(6), 2891 AMU_AMEVCNTR0_EL0(7), 2892 AMU_AMEVCNTR0_EL0(8), 2893 AMU_AMEVCNTR0_EL0(9), 2894 AMU_AMEVCNTR0_EL0(10), 2895 AMU_AMEVCNTR0_EL0(11), 2896 AMU_AMEVCNTR0_EL0(12), 2897 AMU_AMEVCNTR0_EL0(13), 2898 AMU_AMEVCNTR0_EL0(14), 2899 AMU_AMEVCNTR0_EL0(15), 2900 AMU_AMEVTYPER0_EL0(0), 2901 AMU_AMEVTYPER0_EL0(1), 2902 AMU_AMEVTYPER0_EL0(2), 2903 AMU_AMEVTYPER0_EL0(3), 2904 AMU_AMEVTYPER0_EL0(4), 2905 AMU_AMEVTYPER0_EL0(5), 2906 AMU_AMEVTYPER0_EL0(6), 2907 AMU_AMEVTYPER0_EL0(7), 2908 AMU_AMEVTYPER0_EL0(8), 2909 AMU_AMEVTYPER0_EL0(9), 2910 AMU_AMEVTYPER0_EL0(10), 2911 AMU_AMEVTYPER0_EL0(11), 2912 AMU_AMEVTYPER0_EL0(12), 2913 AMU_AMEVTYPER0_EL0(13), 2914 AMU_AMEVTYPER0_EL0(14), 2915 AMU_AMEVTYPER0_EL0(15), 2916 AMU_AMEVCNTR1_EL0(0), 2917 AMU_AMEVCNTR1_EL0(1), 2918 AMU_AMEVCNTR1_EL0(2), 2919 AMU_AMEVCNTR1_EL0(3), 2920 AMU_AMEVCNTR1_EL0(4), 2921 AMU_AMEVCNTR1_EL0(5), 2922 AMU_AMEVCNTR1_EL0(6), 2923 AMU_AMEVCNTR1_EL0(7), 2924 AMU_AMEVCNTR1_EL0(8), 2925 AMU_AMEVCNTR1_EL0(9), 2926 AMU_AMEVCNTR1_EL0(10), 2927 AMU_AMEVCNTR1_EL0(11), 2928 AMU_AMEVCNTR1_EL0(12), 2929 AMU_AMEVCNTR1_EL0(13), 2930 AMU_AMEVCNTR1_EL0(14), 2931 AMU_AMEVCNTR1_EL0(15), 2932 AMU_AMEVTYPER1_EL0(0), 2933 AMU_AMEVTYPER1_EL0(1), 2934 AMU_AMEVTYPER1_EL0(2), 2935 AMU_AMEVTYPER1_EL0(3), 2936 AMU_AMEVTYPER1_EL0(4), 2937 AMU_AMEVTYPER1_EL0(5), 2938 AMU_AMEVTYPER1_EL0(6), 2939 AMU_AMEVTYPER1_EL0(7), 2940 AMU_AMEVTYPER1_EL0(8), 2941 AMU_AMEVTYPER1_EL0(9), 2942 AMU_AMEVTYPER1_EL0(10), 2943 AMU_AMEVTYPER1_EL0(11), 2944 AMU_AMEVTYPER1_EL0(12), 2945 AMU_AMEVTYPER1_EL0(13), 2946 AMU_AMEVTYPER1_EL0(14), 2947 AMU_AMEVTYPER1_EL0(15), 2948 2949 { SYS_DESC(SYS_CNTPCT_EL0), access_arch_timer }, 2950 { SYS_DESC(SYS_CNTVCT_EL0), access_arch_timer }, 2951 { SYS_DESC(SYS_CNTPCTSS_EL0), access_arch_timer }, 2952 { SYS_DESC(SYS_CNTVCTSS_EL0), access_arch_timer }, 2953 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer }, 2954 { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer }, 2955 { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer }, 2956 2957 { SYS_DESC(SYS_CNTV_TVAL_EL0), access_arch_timer }, 2958 { SYS_DESC(SYS_CNTV_CTL_EL0), access_arch_timer }, 2959 { SYS_DESC(SYS_CNTV_CVAL_EL0), access_arch_timer }, 2960 2961 /* PMEVCNTRn_EL0 */ 2962 PMU_PMEVCNTR_EL0(0), 2963 PMU_PMEVCNTR_EL0(1), 2964 PMU_PMEVCNTR_EL0(2), 2965 PMU_PMEVCNTR_EL0(3), 2966 PMU_PMEVCNTR_EL0(4), 2967 PMU_PMEVCNTR_EL0(5), 2968 PMU_PMEVCNTR_EL0(6), 2969 PMU_PMEVCNTR_EL0(7), 2970 PMU_PMEVCNTR_EL0(8), 2971 PMU_PMEVCNTR_EL0(9), 2972 PMU_PMEVCNTR_EL0(10), 2973 PMU_PMEVCNTR_EL0(11), 2974 PMU_PMEVCNTR_EL0(12), 2975 PMU_PMEVCNTR_EL0(13), 2976 PMU_PMEVCNTR_EL0(14), 2977 PMU_PMEVCNTR_EL0(15), 2978 PMU_PMEVCNTR_EL0(16), 2979 PMU_PMEVCNTR_EL0(17), 2980 PMU_PMEVCNTR_EL0(18), 2981 PMU_PMEVCNTR_EL0(19), 2982 PMU_PMEVCNTR_EL0(20), 2983 PMU_PMEVCNTR_EL0(21), 2984 PMU_PMEVCNTR_EL0(22), 2985 PMU_PMEVCNTR_EL0(23), 2986 PMU_PMEVCNTR_EL0(24), 2987 PMU_PMEVCNTR_EL0(25), 2988 PMU_PMEVCNTR_EL0(26), 2989 PMU_PMEVCNTR_EL0(27), 2990 PMU_PMEVCNTR_EL0(28), 2991 PMU_PMEVCNTR_EL0(29), 2992 PMU_PMEVCNTR_EL0(30), 2993 /* PMEVTYPERn_EL0 */ 2994 PMU_PMEVTYPER_EL0(0), 2995 PMU_PMEVTYPER_EL0(1), 2996 PMU_PMEVTYPER_EL0(2), 2997 PMU_PMEVTYPER_EL0(3), 2998 PMU_PMEVTYPER_EL0(4), 2999 PMU_PMEVTYPER_EL0(5), 3000 PMU_PMEVTYPER_EL0(6), 3001 PMU_PMEVTYPER_EL0(7), 3002 PMU_PMEVTYPER_EL0(8), 3003 PMU_PMEVTYPER_EL0(9), 3004 PMU_PMEVTYPER_EL0(10), 3005 PMU_PMEVTYPER_EL0(11), 3006 PMU_PMEVTYPER_EL0(12), 3007 PMU_PMEVTYPER_EL0(13), 3008 PMU_PMEVTYPER_EL0(14), 3009 PMU_PMEVTYPER_EL0(15), 3010 PMU_PMEVTYPER_EL0(16), 3011 PMU_PMEVTYPER_EL0(17), 3012 PMU_PMEVTYPER_EL0(18), 3013 PMU_PMEVTYPER_EL0(19), 3014 PMU_PMEVTYPER_EL0(20), 3015 PMU_PMEVTYPER_EL0(21), 3016 PMU_PMEVTYPER_EL0(22), 3017 PMU_PMEVTYPER_EL0(23), 3018 PMU_PMEVTYPER_EL0(24), 3019 PMU_PMEVTYPER_EL0(25), 3020 PMU_PMEVTYPER_EL0(26), 3021 PMU_PMEVTYPER_EL0(27), 3022 PMU_PMEVTYPER_EL0(28), 3023 PMU_PMEVTYPER_EL0(29), 3024 PMU_PMEVTYPER_EL0(30), 3025 /* 3026 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero 3027 * in 32bit mode. Here we choose to reset it as zero for consistency. 3028 */ 3029 { PMU_SYS_REG(PMCCFILTR_EL0), .access = access_pmu_evtyper, 3030 .reset = reset_val, .reg = PMCCFILTR_EL0, .val = 0 }, 3031 3032 EL2_REG_VNCR(VPIDR_EL2, reset_unknown, 0), 3033 EL2_REG_VNCR(VMPIDR_EL2, reset_unknown, 0), 3034 EL2_REG(SCTLR_EL2, access_rw, reset_val, SCTLR_EL2_RES1), 3035 EL2_REG(ACTLR_EL2, access_rw, reset_val, 0), 3036 EL2_REG_VNCR(HCR_EL2, reset_hcr, 0), 3037 EL2_REG(MDCR_EL2, access_mdcr, reset_val, 0), 3038 EL2_REG(CPTR_EL2, access_rw, reset_val, CPTR_NVHE_EL2_RES1), 3039 EL2_REG_VNCR(HSTR_EL2, reset_val, 0), 3040 EL2_REG_VNCR(HFGRTR_EL2, reset_val, 0), 3041 EL2_REG_VNCR(HFGWTR_EL2, reset_val, 0), 3042 EL2_REG_VNCR(HFGITR_EL2, reset_val, 0), 3043 EL2_REG_VNCR(HACR_EL2, reset_val, 0), 3044 3045 EL2_REG_FILTERED(ZCR_EL2, access_zcr_el2, reset_val, 0, 3046 sve_el2_visibility), 3047 3048 EL2_REG_VNCR(HCRX_EL2, reset_val, 0), 3049 3050 EL2_REG(TTBR0_EL2, access_rw, reset_val, 0), 3051 EL2_REG(TTBR1_EL2, access_rw, reset_val, 0), 3052 EL2_REG(TCR_EL2, access_rw, reset_val, TCR_EL2_RES1), 3053 EL2_REG_FILTERED(TCR2_EL2, access_rw, reset_val, TCR2_EL2_RES1, 3054 tcr2_el2_visibility), 3055 EL2_REG_VNCR(VTTBR_EL2, reset_val, 0), 3056 EL2_REG_VNCR(VTCR_EL2, reset_val, 0), 3057 3058 { SYS_DESC(SYS_DACR32_EL2), undef_access, reset_unknown, DACR32_EL2 }, 3059 EL2_REG_VNCR(HDFGRTR_EL2, reset_val, 0), 3060 EL2_REG_VNCR(HDFGWTR_EL2, reset_val, 0), 3061 EL2_REG_VNCR(HAFGRTR_EL2, reset_val, 0), 3062 EL2_REG_REDIR(SPSR_EL2, reset_val, 0), 3063 EL2_REG_REDIR(ELR_EL2, reset_val, 0), 3064 { SYS_DESC(SYS_SP_EL1), access_sp_el1}, 3065 3066 /* AArch32 SPSR_* are RES0 if trapped from a NV guest */ 3067 { SYS_DESC(SYS_SPSR_irq), .access = trap_raz_wi }, 3068 { SYS_DESC(SYS_SPSR_abt), .access = trap_raz_wi }, 3069 { SYS_DESC(SYS_SPSR_und), .access = trap_raz_wi }, 3070 { SYS_DESC(SYS_SPSR_fiq), .access = trap_raz_wi }, 3071 3072 { SYS_DESC(SYS_IFSR32_EL2), undef_access, reset_unknown, IFSR32_EL2 }, 3073 EL2_REG(AFSR0_EL2, access_rw, reset_val, 0), 3074 EL2_REG(AFSR1_EL2, access_rw, reset_val, 0), 3075 EL2_REG_REDIR(ESR_EL2, reset_val, 0), 3076 { SYS_DESC(SYS_FPEXC32_EL2), undef_access, reset_val, FPEXC32_EL2, 0x700 }, 3077 3078 EL2_REG_REDIR(FAR_EL2, reset_val, 0), 3079 EL2_REG(HPFAR_EL2, access_rw, reset_val, 0), 3080 3081 EL2_REG(MAIR_EL2, access_rw, reset_val, 0), 3082 EL2_REG_FILTERED(PIRE0_EL2, access_rw, reset_val, 0, 3083 s1pie_el2_visibility), 3084 EL2_REG_FILTERED(PIR_EL2, access_rw, reset_val, 0, 3085 s1pie_el2_visibility), 3086 EL2_REG_FILTERED(POR_EL2, access_rw, reset_val, 0, 3087 s1poe_el2_visibility), 3088 EL2_REG(AMAIR_EL2, access_rw, reset_val, 0), 3089 { SYS_DESC(SYS_MPAMHCR_EL2), undef_access }, 3090 { SYS_DESC(SYS_MPAMVPMV_EL2), undef_access }, 3091 { SYS_DESC(SYS_MPAM2_EL2), undef_access }, 3092 { SYS_DESC(SYS_MPAMVPM0_EL2), undef_access }, 3093 { SYS_DESC(SYS_MPAMVPM1_EL2), undef_access }, 3094 { SYS_DESC(SYS_MPAMVPM2_EL2), undef_access }, 3095 { SYS_DESC(SYS_MPAMVPM3_EL2), undef_access }, 3096 { SYS_DESC(SYS_MPAMVPM4_EL2), undef_access }, 3097 { SYS_DESC(SYS_MPAMVPM5_EL2), undef_access }, 3098 { SYS_DESC(SYS_MPAMVPM6_EL2), undef_access }, 3099 { SYS_DESC(SYS_MPAMVPM7_EL2), undef_access }, 3100 3101 EL2_REG(VBAR_EL2, access_rw, reset_val, 0), 3102 EL2_REG(RVBAR_EL2, access_rw, reset_val, 0), 3103 { SYS_DESC(SYS_RMR_EL2), undef_access }, 3104 3105 EL2_REG_VNCR(ICH_HCR_EL2, reset_val, 0), 3106 3107 EL2_REG(CONTEXTIDR_EL2, access_rw, reset_val, 0), 3108 EL2_REG(TPIDR_EL2, access_rw, reset_val, 0), 3109 3110 EL2_REG_VNCR(CNTVOFF_EL2, reset_val, 0), 3111 EL2_REG(CNTHCTL_EL2, access_rw, reset_val, 0), 3112 { SYS_DESC(SYS_CNTHP_TVAL_EL2), access_arch_timer }, 3113 EL2_REG(CNTHP_CTL_EL2, access_arch_timer, reset_val, 0), 3114 EL2_REG(CNTHP_CVAL_EL2, access_arch_timer, reset_val, 0), 3115 3116 { SYS_DESC(SYS_CNTHV_TVAL_EL2), access_hv_timer }, 3117 EL2_REG(CNTHV_CTL_EL2, access_hv_timer, reset_val, 0), 3118 EL2_REG(CNTHV_CVAL_EL2, access_hv_timer, reset_val, 0), 3119 3120 { SYS_DESC(SYS_CNTKCTL_EL12), access_cntkctl_el12 }, 3121 3122 { SYS_DESC(SYS_CNTP_TVAL_EL02), access_arch_timer }, 3123 { SYS_DESC(SYS_CNTP_CTL_EL02), access_arch_timer }, 3124 { SYS_DESC(SYS_CNTP_CVAL_EL02), access_arch_timer }, 3125 3126 { SYS_DESC(SYS_CNTV_TVAL_EL02), access_arch_timer }, 3127 { SYS_DESC(SYS_CNTV_CTL_EL02), access_arch_timer }, 3128 { SYS_DESC(SYS_CNTV_CVAL_EL02), access_arch_timer }, 3129 3130 EL2_REG(SP_EL2, NULL, reset_unknown, 0), 3131 }; 3132 3133 static bool handle_at_s1e01(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3134 const struct sys_reg_desc *r) 3135 { 3136 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3137 3138 __kvm_at_s1e01(vcpu, op, p->regval); 3139 3140 return true; 3141 } 3142 3143 static bool handle_at_s1e2(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3144 const struct sys_reg_desc *r) 3145 { 3146 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3147 3148 /* There is no FGT associated with AT S1E2A :-( */ 3149 if (op == OP_AT_S1E2A && 3150 !kvm_has_feat(vcpu->kvm, ID_AA64ISAR2_EL1, ATS1A, IMP)) { 3151 kvm_inject_undefined(vcpu); 3152 return false; 3153 } 3154 3155 __kvm_at_s1e2(vcpu, op, p->regval); 3156 3157 return true; 3158 } 3159 3160 static bool handle_at_s12(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3161 const struct sys_reg_desc *r) 3162 { 3163 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3164 3165 __kvm_at_s12(vcpu, op, p->regval); 3166 3167 return true; 3168 } 3169 3170 static bool kvm_supported_tlbi_s12_op(struct kvm_vcpu *vpcu, u32 instr) 3171 { 3172 struct kvm *kvm = vpcu->kvm; 3173 u8 CRm = sys_reg_CRm(instr); 3174 3175 if (sys_reg_CRn(instr) == TLBI_CRn_nXS && 3176 !kvm_has_feat(kvm, ID_AA64ISAR1_EL1, XS, IMP)) 3177 return false; 3178 3179 if (CRm == TLBI_CRm_nROS && 3180 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 3181 return false; 3182 3183 return true; 3184 } 3185 3186 static bool handle_alle1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3187 const struct sys_reg_desc *r) 3188 { 3189 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3190 3191 if (!kvm_supported_tlbi_s12_op(vcpu, sys_encoding)) 3192 return undef_access(vcpu, p, r); 3193 3194 write_lock(&vcpu->kvm->mmu_lock); 3195 3196 /* 3197 * Drop all shadow S2s, resulting in S1/S2 TLBIs for each of the 3198 * corresponding VMIDs. 3199 */ 3200 kvm_nested_s2_unmap(vcpu->kvm, true); 3201 3202 write_unlock(&vcpu->kvm->mmu_lock); 3203 3204 return true; 3205 } 3206 3207 static bool kvm_supported_tlbi_ipas2_op(struct kvm_vcpu *vpcu, u32 instr) 3208 { 3209 struct kvm *kvm = vpcu->kvm; 3210 u8 CRm = sys_reg_CRm(instr); 3211 u8 Op2 = sys_reg_Op2(instr); 3212 3213 if (sys_reg_CRn(instr) == TLBI_CRn_nXS && 3214 !kvm_has_feat(kvm, ID_AA64ISAR1_EL1, XS, IMP)) 3215 return false; 3216 3217 if (CRm == TLBI_CRm_IPAIS && (Op2 == 2 || Op2 == 6) && 3218 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE)) 3219 return false; 3220 3221 if (CRm == TLBI_CRm_IPAONS && (Op2 == 0 || Op2 == 4) && 3222 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 3223 return false; 3224 3225 if (CRm == TLBI_CRm_IPAONS && (Op2 == 3 || Op2 == 7) && 3226 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE)) 3227 return false; 3228 3229 return true; 3230 } 3231 3232 /* Only defined here as this is an internal "abstraction" */ 3233 union tlbi_info { 3234 struct { 3235 u64 start; 3236 u64 size; 3237 } range; 3238 3239 struct { 3240 u64 addr; 3241 } ipa; 3242 3243 struct { 3244 u64 addr; 3245 u32 encoding; 3246 } va; 3247 }; 3248 3249 static void s2_mmu_unmap_range(struct kvm_s2_mmu *mmu, 3250 const union tlbi_info *info) 3251 { 3252 /* 3253 * The unmap operation is allowed to drop the MMU lock and block, which 3254 * means that @mmu could be used for a different context than the one 3255 * currently being invalidated. 3256 * 3257 * This behavior is still safe, as: 3258 * 3259 * 1) The vCPU(s) that recycled the MMU are responsible for invalidating 3260 * the entire MMU before reusing it, which still honors the intent 3261 * of a TLBI. 3262 * 3263 * 2) Until the guest TLBI instruction is 'retired' (i.e. increment PC 3264 * and ERET to the guest), other vCPUs are allowed to use stale 3265 * translations. 3266 * 3267 * 3) Accidentally unmapping an unrelated MMU context is nonfatal, and 3268 * at worst may cause more aborts for shadow stage-2 fills. 3269 * 3270 * Dropping the MMU lock also implies that shadow stage-2 fills could 3271 * happen behind the back of the TLBI. This is still safe, though, as 3272 * the L1 needs to put its stage-2 in a consistent state before doing 3273 * the TLBI. 3274 */ 3275 kvm_stage2_unmap_range(mmu, info->range.start, info->range.size, true); 3276 } 3277 3278 static bool handle_vmalls12e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3279 const struct sys_reg_desc *r) 3280 { 3281 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3282 u64 limit, vttbr; 3283 3284 if (!kvm_supported_tlbi_s12_op(vcpu, sys_encoding)) 3285 return undef_access(vcpu, p, r); 3286 3287 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 3288 limit = BIT_ULL(kvm_get_pa_bits(vcpu->kvm)); 3289 3290 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 3291 &(union tlbi_info) { 3292 .range = { 3293 .start = 0, 3294 .size = limit, 3295 }, 3296 }, 3297 s2_mmu_unmap_range); 3298 3299 return true; 3300 } 3301 3302 static bool handle_ripas2e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3303 const struct sys_reg_desc *r) 3304 { 3305 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3306 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 3307 u64 base, range, tg, num, scale; 3308 int shift; 3309 3310 if (!kvm_supported_tlbi_ipas2_op(vcpu, sys_encoding)) 3311 return undef_access(vcpu, p, r); 3312 3313 /* 3314 * Because the shadow S2 structure doesn't necessarily reflect that 3315 * of the guest's S2 (different base granule size, for example), we 3316 * decide to ignore TTL and only use the described range. 3317 */ 3318 tg = FIELD_GET(GENMASK(47, 46), p->regval); 3319 scale = FIELD_GET(GENMASK(45, 44), p->regval); 3320 num = FIELD_GET(GENMASK(43, 39), p->regval); 3321 base = p->regval & GENMASK(36, 0); 3322 3323 switch(tg) { 3324 case 1: 3325 shift = 12; 3326 break; 3327 case 2: 3328 shift = 14; 3329 break; 3330 case 3: 3331 default: /* IMPDEF: handle tg==0 as 64k */ 3332 shift = 16; 3333 break; 3334 } 3335 3336 base <<= shift; 3337 range = __TLBI_RANGE_PAGES(num, scale) << shift; 3338 3339 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 3340 &(union tlbi_info) { 3341 .range = { 3342 .start = base, 3343 .size = range, 3344 }, 3345 }, 3346 s2_mmu_unmap_range); 3347 3348 return true; 3349 } 3350 3351 static void s2_mmu_unmap_ipa(struct kvm_s2_mmu *mmu, 3352 const union tlbi_info *info) 3353 { 3354 unsigned long max_size; 3355 u64 base_addr; 3356 3357 /* 3358 * We drop a number of things from the supplied value: 3359 * 3360 * - NS bit: we're non-secure only. 3361 * 3362 * - IPA[51:48]: We don't support 52bit IPA just yet... 3363 * 3364 * And of course, adjust the IPA to be on an actual address. 3365 */ 3366 base_addr = (info->ipa.addr & GENMASK_ULL(35, 0)) << 12; 3367 max_size = compute_tlb_inval_range(mmu, info->ipa.addr); 3368 base_addr &= ~(max_size - 1); 3369 3370 /* 3371 * See comment in s2_mmu_unmap_range() for why this is allowed to 3372 * reschedule. 3373 */ 3374 kvm_stage2_unmap_range(mmu, base_addr, max_size, true); 3375 } 3376 3377 static bool handle_ipas2e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3378 const struct sys_reg_desc *r) 3379 { 3380 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3381 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 3382 3383 if (!kvm_supported_tlbi_ipas2_op(vcpu, sys_encoding)) 3384 return undef_access(vcpu, p, r); 3385 3386 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 3387 &(union tlbi_info) { 3388 .ipa = { 3389 .addr = p->regval, 3390 }, 3391 }, 3392 s2_mmu_unmap_ipa); 3393 3394 return true; 3395 } 3396 3397 static void s2_mmu_tlbi_s1e1(struct kvm_s2_mmu *mmu, 3398 const union tlbi_info *info) 3399 { 3400 WARN_ON(__kvm_tlbi_s1e2(mmu, info->va.addr, info->va.encoding)); 3401 } 3402 3403 static bool handle_tlbi_el1(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3404 const struct sys_reg_desc *r) 3405 { 3406 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3407 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 3408 3409 /* 3410 * If we're here, this is because we've trapped on a EL1 TLBI 3411 * instruction that affects the EL1 translation regime while 3412 * we're running in a context that doesn't allow us to let the 3413 * HW do its thing (aka vEL2): 3414 * 3415 * - HCR_EL2.E2H == 0 : a non-VHE guest 3416 * - HCR_EL2.{E2H,TGE} == { 1, 0 } : a VHE guest in guest mode 3417 * 3418 * We don't expect these helpers to ever be called when running 3419 * in a vEL1 context. 3420 */ 3421 3422 WARN_ON(!vcpu_is_el2(vcpu)); 3423 3424 if (!kvm_supported_tlbi_s1e1_op(vcpu, sys_encoding)) 3425 return undef_access(vcpu, p, r); 3426 3427 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 3428 &(union tlbi_info) { 3429 .va = { 3430 .addr = p->regval, 3431 .encoding = sys_encoding, 3432 }, 3433 }, 3434 s2_mmu_tlbi_s1e1); 3435 3436 return true; 3437 } 3438 3439 #define SYS_INSN(insn, access_fn) \ 3440 { \ 3441 SYS_DESC(OP_##insn), \ 3442 .access = (access_fn), \ 3443 } 3444 3445 static struct sys_reg_desc sys_insn_descs[] = { 3446 { SYS_DESC(SYS_DC_ISW), access_dcsw }, 3447 { SYS_DESC(SYS_DC_IGSW), access_dcgsw }, 3448 { SYS_DESC(SYS_DC_IGDSW), access_dcgsw }, 3449 3450 SYS_INSN(AT_S1E1R, handle_at_s1e01), 3451 SYS_INSN(AT_S1E1W, handle_at_s1e01), 3452 SYS_INSN(AT_S1E0R, handle_at_s1e01), 3453 SYS_INSN(AT_S1E0W, handle_at_s1e01), 3454 SYS_INSN(AT_S1E1RP, handle_at_s1e01), 3455 SYS_INSN(AT_S1E1WP, handle_at_s1e01), 3456 3457 { SYS_DESC(SYS_DC_CSW), access_dcsw }, 3458 { SYS_DESC(SYS_DC_CGSW), access_dcgsw }, 3459 { SYS_DESC(SYS_DC_CGDSW), access_dcgsw }, 3460 { SYS_DESC(SYS_DC_CISW), access_dcsw }, 3461 { SYS_DESC(SYS_DC_CIGSW), access_dcgsw }, 3462 { SYS_DESC(SYS_DC_CIGDSW), access_dcgsw }, 3463 3464 SYS_INSN(TLBI_VMALLE1OS, handle_tlbi_el1), 3465 SYS_INSN(TLBI_VAE1OS, handle_tlbi_el1), 3466 SYS_INSN(TLBI_ASIDE1OS, handle_tlbi_el1), 3467 SYS_INSN(TLBI_VAAE1OS, handle_tlbi_el1), 3468 SYS_INSN(TLBI_VALE1OS, handle_tlbi_el1), 3469 SYS_INSN(TLBI_VAALE1OS, handle_tlbi_el1), 3470 3471 SYS_INSN(TLBI_RVAE1IS, handle_tlbi_el1), 3472 SYS_INSN(TLBI_RVAAE1IS, handle_tlbi_el1), 3473 SYS_INSN(TLBI_RVALE1IS, handle_tlbi_el1), 3474 SYS_INSN(TLBI_RVAALE1IS, handle_tlbi_el1), 3475 3476 SYS_INSN(TLBI_VMALLE1IS, handle_tlbi_el1), 3477 SYS_INSN(TLBI_VAE1IS, handle_tlbi_el1), 3478 SYS_INSN(TLBI_ASIDE1IS, handle_tlbi_el1), 3479 SYS_INSN(TLBI_VAAE1IS, handle_tlbi_el1), 3480 SYS_INSN(TLBI_VALE1IS, handle_tlbi_el1), 3481 SYS_INSN(TLBI_VAALE1IS, handle_tlbi_el1), 3482 3483 SYS_INSN(TLBI_RVAE1OS, handle_tlbi_el1), 3484 SYS_INSN(TLBI_RVAAE1OS, handle_tlbi_el1), 3485 SYS_INSN(TLBI_RVALE1OS, handle_tlbi_el1), 3486 SYS_INSN(TLBI_RVAALE1OS, handle_tlbi_el1), 3487 3488 SYS_INSN(TLBI_RVAE1, handle_tlbi_el1), 3489 SYS_INSN(TLBI_RVAAE1, handle_tlbi_el1), 3490 SYS_INSN(TLBI_RVALE1, handle_tlbi_el1), 3491 SYS_INSN(TLBI_RVAALE1, handle_tlbi_el1), 3492 3493 SYS_INSN(TLBI_VMALLE1, handle_tlbi_el1), 3494 SYS_INSN(TLBI_VAE1, handle_tlbi_el1), 3495 SYS_INSN(TLBI_ASIDE1, handle_tlbi_el1), 3496 SYS_INSN(TLBI_VAAE1, handle_tlbi_el1), 3497 SYS_INSN(TLBI_VALE1, handle_tlbi_el1), 3498 SYS_INSN(TLBI_VAALE1, handle_tlbi_el1), 3499 3500 SYS_INSN(TLBI_VMALLE1OSNXS, handle_tlbi_el1), 3501 SYS_INSN(TLBI_VAE1OSNXS, handle_tlbi_el1), 3502 SYS_INSN(TLBI_ASIDE1OSNXS, handle_tlbi_el1), 3503 SYS_INSN(TLBI_VAAE1OSNXS, handle_tlbi_el1), 3504 SYS_INSN(TLBI_VALE1OSNXS, handle_tlbi_el1), 3505 SYS_INSN(TLBI_VAALE1OSNXS, handle_tlbi_el1), 3506 3507 SYS_INSN(TLBI_RVAE1ISNXS, handle_tlbi_el1), 3508 SYS_INSN(TLBI_RVAAE1ISNXS, handle_tlbi_el1), 3509 SYS_INSN(TLBI_RVALE1ISNXS, handle_tlbi_el1), 3510 SYS_INSN(TLBI_RVAALE1ISNXS, handle_tlbi_el1), 3511 3512 SYS_INSN(TLBI_VMALLE1ISNXS, handle_tlbi_el1), 3513 SYS_INSN(TLBI_VAE1ISNXS, handle_tlbi_el1), 3514 SYS_INSN(TLBI_ASIDE1ISNXS, handle_tlbi_el1), 3515 SYS_INSN(TLBI_VAAE1ISNXS, handle_tlbi_el1), 3516 SYS_INSN(TLBI_VALE1ISNXS, handle_tlbi_el1), 3517 SYS_INSN(TLBI_VAALE1ISNXS, handle_tlbi_el1), 3518 3519 SYS_INSN(TLBI_RVAE1OSNXS, handle_tlbi_el1), 3520 SYS_INSN(TLBI_RVAAE1OSNXS, handle_tlbi_el1), 3521 SYS_INSN(TLBI_RVALE1OSNXS, handle_tlbi_el1), 3522 SYS_INSN(TLBI_RVAALE1OSNXS, handle_tlbi_el1), 3523 3524 SYS_INSN(TLBI_RVAE1NXS, handle_tlbi_el1), 3525 SYS_INSN(TLBI_RVAAE1NXS, handle_tlbi_el1), 3526 SYS_INSN(TLBI_RVALE1NXS, handle_tlbi_el1), 3527 SYS_INSN(TLBI_RVAALE1NXS, handle_tlbi_el1), 3528 3529 SYS_INSN(TLBI_VMALLE1NXS, handle_tlbi_el1), 3530 SYS_INSN(TLBI_VAE1NXS, handle_tlbi_el1), 3531 SYS_INSN(TLBI_ASIDE1NXS, handle_tlbi_el1), 3532 SYS_INSN(TLBI_VAAE1NXS, handle_tlbi_el1), 3533 SYS_INSN(TLBI_VALE1NXS, handle_tlbi_el1), 3534 SYS_INSN(TLBI_VAALE1NXS, handle_tlbi_el1), 3535 3536 SYS_INSN(AT_S1E2R, handle_at_s1e2), 3537 SYS_INSN(AT_S1E2W, handle_at_s1e2), 3538 SYS_INSN(AT_S12E1R, handle_at_s12), 3539 SYS_INSN(AT_S12E1W, handle_at_s12), 3540 SYS_INSN(AT_S12E0R, handle_at_s12), 3541 SYS_INSN(AT_S12E0W, handle_at_s12), 3542 SYS_INSN(AT_S1E2A, handle_at_s1e2), 3543 3544 SYS_INSN(TLBI_IPAS2E1IS, handle_ipas2e1is), 3545 SYS_INSN(TLBI_RIPAS2E1IS, handle_ripas2e1is), 3546 SYS_INSN(TLBI_IPAS2LE1IS, handle_ipas2e1is), 3547 SYS_INSN(TLBI_RIPAS2LE1IS, handle_ripas2e1is), 3548 3549 SYS_INSN(TLBI_ALLE2OS, undef_access), 3550 SYS_INSN(TLBI_VAE2OS, undef_access), 3551 SYS_INSN(TLBI_ALLE1OS, handle_alle1is), 3552 SYS_INSN(TLBI_VALE2OS, undef_access), 3553 SYS_INSN(TLBI_VMALLS12E1OS, handle_vmalls12e1is), 3554 3555 SYS_INSN(TLBI_RVAE2IS, undef_access), 3556 SYS_INSN(TLBI_RVALE2IS, undef_access), 3557 3558 SYS_INSN(TLBI_ALLE1IS, handle_alle1is), 3559 SYS_INSN(TLBI_VMALLS12E1IS, handle_vmalls12e1is), 3560 SYS_INSN(TLBI_IPAS2E1OS, handle_ipas2e1is), 3561 SYS_INSN(TLBI_IPAS2E1, handle_ipas2e1is), 3562 SYS_INSN(TLBI_RIPAS2E1, handle_ripas2e1is), 3563 SYS_INSN(TLBI_RIPAS2E1OS, handle_ripas2e1is), 3564 SYS_INSN(TLBI_IPAS2LE1OS, handle_ipas2e1is), 3565 SYS_INSN(TLBI_IPAS2LE1, handle_ipas2e1is), 3566 SYS_INSN(TLBI_RIPAS2LE1, handle_ripas2e1is), 3567 SYS_INSN(TLBI_RIPAS2LE1OS, handle_ripas2e1is), 3568 SYS_INSN(TLBI_RVAE2OS, undef_access), 3569 SYS_INSN(TLBI_RVALE2OS, undef_access), 3570 SYS_INSN(TLBI_RVAE2, undef_access), 3571 SYS_INSN(TLBI_RVALE2, undef_access), 3572 SYS_INSN(TLBI_ALLE1, handle_alle1is), 3573 SYS_INSN(TLBI_VMALLS12E1, handle_vmalls12e1is), 3574 3575 SYS_INSN(TLBI_IPAS2E1ISNXS, handle_ipas2e1is), 3576 SYS_INSN(TLBI_RIPAS2E1ISNXS, handle_ripas2e1is), 3577 SYS_INSN(TLBI_IPAS2LE1ISNXS, handle_ipas2e1is), 3578 SYS_INSN(TLBI_RIPAS2LE1ISNXS, handle_ripas2e1is), 3579 3580 SYS_INSN(TLBI_ALLE2OSNXS, undef_access), 3581 SYS_INSN(TLBI_VAE2OSNXS, undef_access), 3582 SYS_INSN(TLBI_ALLE1OSNXS, handle_alle1is), 3583 SYS_INSN(TLBI_VALE2OSNXS, undef_access), 3584 SYS_INSN(TLBI_VMALLS12E1OSNXS, handle_vmalls12e1is), 3585 3586 SYS_INSN(TLBI_RVAE2ISNXS, undef_access), 3587 SYS_INSN(TLBI_RVALE2ISNXS, undef_access), 3588 SYS_INSN(TLBI_ALLE2ISNXS, undef_access), 3589 SYS_INSN(TLBI_VAE2ISNXS, undef_access), 3590 3591 SYS_INSN(TLBI_ALLE1ISNXS, handle_alle1is), 3592 SYS_INSN(TLBI_VALE2ISNXS, undef_access), 3593 SYS_INSN(TLBI_VMALLS12E1ISNXS, handle_vmalls12e1is), 3594 SYS_INSN(TLBI_IPAS2E1OSNXS, handle_ipas2e1is), 3595 SYS_INSN(TLBI_IPAS2E1NXS, handle_ipas2e1is), 3596 SYS_INSN(TLBI_RIPAS2E1NXS, handle_ripas2e1is), 3597 SYS_INSN(TLBI_RIPAS2E1OSNXS, handle_ripas2e1is), 3598 SYS_INSN(TLBI_IPAS2LE1OSNXS, handle_ipas2e1is), 3599 SYS_INSN(TLBI_IPAS2LE1NXS, handle_ipas2e1is), 3600 SYS_INSN(TLBI_RIPAS2LE1NXS, handle_ripas2e1is), 3601 SYS_INSN(TLBI_RIPAS2LE1OSNXS, handle_ripas2e1is), 3602 SYS_INSN(TLBI_RVAE2OSNXS, undef_access), 3603 SYS_INSN(TLBI_RVALE2OSNXS, undef_access), 3604 SYS_INSN(TLBI_RVAE2NXS, undef_access), 3605 SYS_INSN(TLBI_RVALE2NXS, undef_access), 3606 SYS_INSN(TLBI_ALLE2NXS, undef_access), 3607 SYS_INSN(TLBI_VAE2NXS, undef_access), 3608 SYS_INSN(TLBI_ALLE1NXS, handle_alle1is), 3609 SYS_INSN(TLBI_VALE2NXS, undef_access), 3610 SYS_INSN(TLBI_VMALLS12E1NXS, handle_vmalls12e1is), 3611 }; 3612 3613 static bool trap_dbgdidr(struct kvm_vcpu *vcpu, 3614 struct sys_reg_params *p, 3615 const struct sys_reg_desc *r) 3616 { 3617 if (p->is_write) { 3618 return ignore_write(vcpu, p); 3619 } else { 3620 u64 dfr = kvm_read_vm_id_reg(vcpu->kvm, SYS_ID_AA64DFR0_EL1); 3621 u32 el3 = kvm_has_feat(vcpu->kvm, ID_AA64PFR0_EL1, EL3, IMP); 3622 3623 p->regval = ((SYS_FIELD_GET(ID_AA64DFR0_EL1, WRPs, dfr) << 28) | 3624 (SYS_FIELD_GET(ID_AA64DFR0_EL1, BRPs, dfr) << 24) | 3625 (SYS_FIELD_GET(ID_AA64DFR0_EL1, CTX_CMPs, dfr) << 20) | 3626 (SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, dfr) << 16) | 3627 (1 << 15) | (el3 << 14) | (el3 << 12)); 3628 return true; 3629 } 3630 } 3631 3632 /* 3633 * AArch32 debug register mappings 3634 * 3635 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0] 3636 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32] 3637 * 3638 * None of the other registers share their location, so treat them as 3639 * if they were 64bit. 3640 */ 3641 #define DBG_BCR_BVR_WCR_WVR(n) \ 3642 /* DBGBVRn */ \ 3643 { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), \ 3644 trap_dbg_wb_reg, NULL, n }, \ 3645 /* DBGBCRn */ \ 3646 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_dbg_wb_reg, NULL, n }, \ 3647 /* DBGWVRn */ \ 3648 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_dbg_wb_reg, NULL, n }, \ 3649 /* DBGWCRn */ \ 3650 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_dbg_wb_reg, NULL, n } 3651 3652 #define DBGBXVR(n) \ 3653 { AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), \ 3654 trap_dbg_wb_reg, NULL, n } 3655 3656 /* 3657 * Trapped cp14 registers. We generally ignore most of the external 3658 * debug, on the principle that they don't really make sense to a 3659 * guest. Revisit this one day, would this principle change. 3660 */ 3661 static const struct sys_reg_desc cp14_regs[] = { 3662 /* DBGDIDR */ 3663 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgdidr }, 3664 /* DBGDTRRXext */ 3665 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi }, 3666 3667 DBG_BCR_BVR_WCR_WVR(0), 3668 /* DBGDSCRint */ 3669 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi }, 3670 DBG_BCR_BVR_WCR_WVR(1), 3671 /* DBGDCCINT */ 3672 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug_regs, NULL, MDCCINT_EL1 }, 3673 /* DBGDSCRext */ 3674 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug_regs, NULL, MDSCR_EL1 }, 3675 DBG_BCR_BVR_WCR_WVR(2), 3676 /* DBGDTR[RT]Xint */ 3677 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi }, 3678 /* DBGDTR[RT]Xext */ 3679 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi }, 3680 DBG_BCR_BVR_WCR_WVR(3), 3681 DBG_BCR_BVR_WCR_WVR(4), 3682 DBG_BCR_BVR_WCR_WVR(5), 3683 /* DBGWFAR */ 3684 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi }, 3685 /* DBGOSECCR */ 3686 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi }, 3687 DBG_BCR_BVR_WCR_WVR(6), 3688 /* DBGVCR */ 3689 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug_regs, NULL, DBGVCR32_EL2 }, 3690 DBG_BCR_BVR_WCR_WVR(7), 3691 DBG_BCR_BVR_WCR_WVR(8), 3692 DBG_BCR_BVR_WCR_WVR(9), 3693 DBG_BCR_BVR_WCR_WVR(10), 3694 DBG_BCR_BVR_WCR_WVR(11), 3695 DBG_BCR_BVR_WCR_WVR(12), 3696 DBG_BCR_BVR_WCR_WVR(13), 3697 DBG_BCR_BVR_WCR_WVR(14), 3698 DBG_BCR_BVR_WCR_WVR(15), 3699 3700 /* DBGDRAR (32bit) */ 3701 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi }, 3702 3703 DBGBXVR(0), 3704 /* DBGOSLAR */ 3705 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_oslar_el1 }, 3706 DBGBXVR(1), 3707 /* DBGOSLSR */ 3708 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1, NULL, OSLSR_EL1 }, 3709 DBGBXVR(2), 3710 DBGBXVR(3), 3711 /* DBGOSDLR */ 3712 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi }, 3713 DBGBXVR(4), 3714 /* DBGPRCR */ 3715 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi }, 3716 DBGBXVR(5), 3717 DBGBXVR(6), 3718 DBGBXVR(7), 3719 DBGBXVR(8), 3720 DBGBXVR(9), 3721 DBGBXVR(10), 3722 DBGBXVR(11), 3723 DBGBXVR(12), 3724 DBGBXVR(13), 3725 DBGBXVR(14), 3726 DBGBXVR(15), 3727 3728 /* DBGDSAR (32bit) */ 3729 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi }, 3730 3731 /* DBGDEVID2 */ 3732 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi }, 3733 /* DBGDEVID1 */ 3734 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi }, 3735 /* DBGDEVID */ 3736 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi }, 3737 /* DBGCLAIMSET */ 3738 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi }, 3739 /* DBGCLAIMCLR */ 3740 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi }, 3741 /* DBGAUTHSTATUS */ 3742 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 }, 3743 }; 3744 3745 /* Trapped cp14 64bit registers */ 3746 static const struct sys_reg_desc cp14_64_regs[] = { 3747 /* DBGDRAR (64bit) */ 3748 { Op1( 0), CRm( 1), .access = trap_raz_wi }, 3749 3750 /* DBGDSAR (64bit) */ 3751 { Op1( 0), CRm( 2), .access = trap_raz_wi }, 3752 }; 3753 3754 #define CP15_PMU_SYS_REG(_map, _Op1, _CRn, _CRm, _Op2) \ 3755 AA32(_map), \ 3756 Op1(_Op1), CRn(_CRn), CRm(_CRm), Op2(_Op2), \ 3757 .visibility = pmu_visibility 3758 3759 /* Macro to expand the PMEVCNTRn register */ 3760 #define PMU_PMEVCNTR(n) \ 3761 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \ 3762 (0b1000 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \ 3763 .access = access_pmu_evcntr } 3764 3765 /* Macro to expand the PMEVTYPERn register */ 3766 #define PMU_PMEVTYPER(n) \ 3767 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \ 3768 (0b1100 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \ 3769 .access = access_pmu_evtyper } 3770 /* 3771 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding, 3772 * depending on the way they are accessed (as a 32bit or a 64bit 3773 * register). 3774 */ 3775 static const struct sys_reg_desc cp15_regs[] = { 3776 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr }, 3777 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, SCTLR_EL1 }, 3778 /* ACTLR */ 3779 { AA32(LO), Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr, NULL, ACTLR_EL1 }, 3780 /* ACTLR2 */ 3781 { AA32(HI), Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr, NULL, ACTLR_EL1 }, 3782 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, 3783 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, TTBR1_EL1 }, 3784 /* TTBCR */ 3785 { AA32(LO), Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 }, 3786 /* TTBCR2 */ 3787 { AA32(HI), Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, TCR_EL1 }, 3788 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, DACR32_EL2 }, 3789 { CP15_SYS_DESC(SYS_ICC_PMR_EL1), undef_access }, 3790 /* DFSR */ 3791 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, ESR_EL1 }, 3792 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, IFSR32_EL2 }, 3793 /* ADFSR */ 3794 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, AFSR0_EL1 }, 3795 /* AIFSR */ 3796 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, AFSR1_EL1 }, 3797 /* DFAR */ 3798 { AA32(LO), Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, FAR_EL1 }, 3799 /* IFAR */ 3800 { AA32(HI), Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, FAR_EL1 }, 3801 3802 /* 3803 * DC{C,I,CI}SW operations: 3804 */ 3805 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw }, 3806 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw }, 3807 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw }, 3808 3809 /* PMU */ 3810 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 0), .access = access_pmcr }, 3811 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 1), .access = access_pmcnten }, 3812 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 2), .access = access_pmcnten }, 3813 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 3), .access = access_pmovs }, 3814 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 4), .access = access_pmswinc }, 3815 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 5), .access = access_pmselr }, 3816 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 6), .access = access_pmceid }, 3817 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 7), .access = access_pmceid }, 3818 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 0), .access = access_pmu_evcntr }, 3819 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 1), .access = access_pmu_evtyper }, 3820 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 2), .access = access_pmu_evcntr }, 3821 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 0), .access = access_pmuserenr }, 3822 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 1), .access = access_pminten }, 3823 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 2), .access = access_pminten }, 3824 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 3), .access = access_pmovs }, 3825 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 4), .access = access_pmceid }, 3826 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 5), .access = access_pmceid }, 3827 /* PMMIR */ 3828 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 6), .access = trap_raz_wi }, 3829 3830 /* PRRR/MAIR0 */ 3831 { AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 }, 3832 /* NMRR/MAIR1 */ 3833 { AA32(HI), Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, MAIR_EL1 }, 3834 /* AMAIR0 */ 3835 { AA32(LO), Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, AMAIR_EL1 }, 3836 /* AMAIR1 */ 3837 { AA32(HI), Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, AMAIR_EL1 }, 3838 3839 { CP15_SYS_DESC(SYS_ICC_IAR0_EL1), undef_access }, 3840 { CP15_SYS_DESC(SYS_ICC_EOIR0_EL1), undef_access }, 3841 { CP15_SYS_DESC(SYS_ICC_HPPIR0_EL1), undef_access }, 3842 { CP15_SYS_DESC(SYS_ICC_BPR0_EL1), undef_access }, 3843 { CP15_SYS_DESC(SYS_ICC_AP0R0_EL1), undef_access }, 3844 { CP15_SYS_DESC(SYS_ICC_AP0R1_EL1), undef_access }, 3845 { CP15_SYS_DESC(SYS_ICC_AP0R2_EL1), undef_access }, 3846 { CP15_SYS_DESC(SYS_ICC_AP0R3_EL1), undef_access }, 3847 { CP15_SYS_DESC(SYS_ICC_AP1R0_EL1), undef_access }, 3848 { CP15_SYS_DESC(SYS_ICC_AP1R1_EL1), undef_access }, 3849 { CP15_SYS_DESC(SYS_ICC_AP1R2_EL1), undef_access }, 3850 { CP15_SYS_DESC(SYS_ICC_AP1R3_EL1), undef_access }, 3851 { CP15_SYS_DESC(SYS_ICC_DIR_EL1), undef_access }, 3852 { CP15_SYS_DESC(SYS_ICC_RPR_EL1), undef_access }, 3853 { CP15_SYS_DESC(SYS_ICC_IAR1_EL1), undef_access }, 3854 { CP15_SYS_DESC(SYS_ICC_EOIR1_EL1), undef_access }, 3855 { CP15_SYS_DESC(SYS_ICC_HPPIR1_EL1), undef_access }, 3856 { CP15_SYS_DESC(SYS_ICC_BPR1_EL1), undef_access }, 3857 { CP15_SYS_DESC(SYS_ICC_CTLR_EL1), undef_access }, 3858 { CP15_SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre }, 3859 { CP15_SYS_DESC(SYS_ICC_IGRPEN0_EL1), undef_access }, 3860 { CP15_SYS_DESC(SYS_ICC_IGRPEN1_EL1), undef_access }, 3861 3862 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, CONTEXTIDR_EL1 }, 3863 3864 /* Arch Tmers */ 3865 { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer }, 3866 { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer }, 3867 3868 /* PMEVCNTRn */ 3869 PMU_PMEVCNTR(0), 3870 PMU_PMEVCNTR(1), 3871 PMU_PMEVCNTR(2), 3872 PMU_PMEVCNTR(3), 3873 PMU_PMEVCNTR(4), 3874 PMU_PMEVCNTR(5), 3875 PMU_PMEVCNTR(6), 3876 PMU_PMEVCNTR(7), 3877 PMU_PMEVCNTR(8), 3878 PMU_PMEVCNTR(9), 3879 PMU_PMEVCNTR(10), 3880 PMU_PMEVCNTR(11), 3881 PMU_PMEVCNTR(12), 3882 PMU_PMEVCNTR(13), 3883 PMU_PMEVCNTR(14), 3884 PMU_PMEVCNTR(15), 3885 PMU_PMEVCNTR(16), 3886 PMU_PMEVCNTR(17), 3887 PMU_PMEVCNTR(18), 3888 PMU_PMEVCNTR(19), 3889 PMU_PMEVCNTR(20), 3890 PMU_PMEVCNTR(21), 3891 PMU_PMEVCNTR(22), 3892 PMU_PMEVCNTR(23), 3893 PMU_PMEVCNTR(24), 3894 PMU_PMEVCNTR(25), 3895 PMU_PMEVCNTR(26), 3896 PMU_PMEVCNTR(27), 3897 PMU_PMEVCNTR(28), 3898 PMU_PMEVCNTR(29), 3899 PMU_PMEVCNTR(30), 3900 /* PMEVTYPERn */ 3901 PMU_PMEVTYPER(0), 3902 PMU_PMEVTYPER(1), 3903 PMU_PMEVTYPER(2), 3904 PMU_PMEVTYPER(3), 3905 PMU_PMEVTYPER(4), 3906 PMU_PMEVTYPER(5), 3907 PMU_PMEVTYPER(6), 3908 PMU_PMEVTYPER(7), 3909 PMU_PMEVTYPER(8), 3910 PMU_PMEVTYPER(9), 3911 PMU_PMEVTYPER(10), 3912 PMU_PMEVTYPER(11), 3913 PMU_PMEVTYPER(12), 3914 PMU_PMEVTYPER(13), 3915 PMU_PMEVTYPER(14), 3916 PMU_PMEVTYPER(15), 3917 PMU_PMEVTYPER(16), 3918 PMU_PMEVTYPER(17), 3919 PMU_PMEVTYPER(18), 3920 PMU_PMEVTYPER(19), 3921 PMU_PMEVTYPER(20), 3922 PMU_PMEVTYPER(21), 3923 PMU_PMEVTYPER(22), 3924 PMU_PMEVTYPER(23), 3925 PMU_PMEVTYPER(24), 3926 PMU_PMEVTYPER(25), 3927 PMU_PMEVTYPER(26), 3928 PMU_PMEVTYPER(27), 3929 PMU_PMEVTYPER(28), 3930 PMU_PMEVTYPER(29), 3931 PMU_PMEVTYPER(30), 3932 /* PMCCFILTR */ 3933 { CP15_PMU_SYS_REG(DIRECT, 0, 14, 15, 7), .access = access_pmu_evtyper }, 3934 3935 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr }, 3936 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr }, 3937 3938 /* CCSIDR2 */ 3939 { Op1(1), CRn( 0), CRm( 0), Op2(2), undef_access }, 3940 3941 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 }, 3942 }; 3943 3944 static const struct sys_reg_desc cp15_64_regs[] = { 3945 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, 3946 { CP15_PMU_SYS_REG(DIRECT, 0, 0, 9, 0), .access = access_pmu_evcntr }, 3947 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */ 3948 { SYS_DESC(SYS_AARCH32_CNTPCT), access_arch_timer }, 3949 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 }, 3950 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */ 3951 { SYS_DESC(SYS_AARCH32_CNTVCT), access_arch_timer }, 3952 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */ 3953 { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer }, 3954 { SYS_DESC(SYS_AARCH32_CNTPCTSS), access_arch_timer }, 3955 { SYS_DESC(SYS_AARCH32_CNTVCTSS), access_arch_timer }, 3956 }; 3957 3958 static bool check_sysreg_table(const struct sys_reg_desc *table, unsigned int n, 3959 bool is_32) 3960 { 3961 unsigned int i; 3962 3963 for (i = 0; i < n; i++) { 3964 if (!is_32 && table[i].reg && !table[i].reset) { 3965 kvm_err("sys_reg table %pS entry %d (%s) lacks reset\n", 3966 &table[i], i, table[i].name); 3967 return false; 3968 } 3969 3970 if (i && cmp_sys_reg(&table[i-1], &table[i]) >= 0) { 3971 kvm_err("sys_reg table %pS entry %d (%s -> %s) out of order\n", 3972 &table[i], i, table[i - 1].name, table[i].name); 3973 return false; 3974 } 3975 } 3976 3977 return true; 3978 } 3979 3980 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu) 3981 { 3982 kvm_inject_undefined(vcpu); 3983 return 1; 3984 } 3985 3986 static void perform_access(struct kvm_vcpu *vcpu, 3987 struct sys_reg_params *params, 3988 const struct sys_reg_desc *r) 3989 { 3990 trace_kvm_sys_access(*vcpu_pc(vcpu), params, r); 3991 3992 /* Check for regs disabled by runtime config */ 3993 if (sysreg_hidden(vcpu, r)) { 3994 kvm_inject_undefined(vcpu); 3995 return; 3996 } 3997 3998 /* 3999 * Not having an accessor means that we have configured a trap 4000 * that we don't know how to handle. This certainly qualifies 4001 * as a gross bug that should be fixed right away. 4002 */ 4003 BUG_ON(!r->access); 4004 4005 /* Skip instruction if instructed so */ 4006 if (likely(r->access(vcpu, params, r))) 4007 kvm_incr_pc(vcpu); 4008 } 4009 4010 /* 4011 * emulate_cp -- tries to match a sys_reg access in a handling table, and 4012 * call the corresponding trap handler. 4013 * 4014 * @params: pointer to the descriptor of the access 4015 * @table: array of trap descriptors 4016 * @num: size of the trap descriptor array 4017 * 4018 * Return true if the access has been handled, false if not. 4019 */ 4020 static bool emulate_cp(struct kvm_vcpu *vcpu, 4021 struct sys_reg_params *params, 4022 const struct sys_reg_desc *table, 4023 size_t num) 4024 { 4025 const struct sys_reg_desc *r; 4026 4027 if (!table) 4028 return false; /* Not handled */ 4029 4030 r = find_reg(params, table, num); 4031 4032 if (r) { 4033 perform_access(vcpu, params, r); 4034 return true; 4035 } 4036 4037 /* Not handled */ 4038 return false; 4039 } 4040 4041 static void unhandled_cp_access(struct kvm_vcpu *vcpu, 4042 struct sys_reg_params *params) 4043 { 4044 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu); 4045 int cp = -1; 4046 4047 switch (esr_ec) { 4048 case ESR_ELx_EC_CP15_32: 4049 case ESR_ELx_EC_CP15_64: 4050 cp = 15; 4051 break; 4052 case ESR_ELx_EC_CP14_MR: 4053 case ESR_ELx_EC_CP14_64: 4054 cp = 14; 4055 break; 4056 default: 4057 WARN_ON(1); 4058 } 4059 4060 print_sys_reg_msg(params, 4061 "Unsupported guest CP%d access at: %08lx [%08lx]\n", 4062 cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 4063 kvm_inject_undefined(vcpu); 4064 } 4065 4066 /** 4067 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access 4068 * @vcpu: The VCPU pointer 4069 * @global: &struct sys_reg_desc 4070 * @nr_global: size of the @global array 4071 */ 4072 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu, 4073 const struct sys_reg_desc *global, 4074 size_t nr_global) 4075 { 4076 struct sys_reg_params params; 4077 u64 esr = kvm_vcpu_get_esr(vcpu); 4078 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4079 int Rt2 = (esr >> 10) & 0x1f; 4080 4081 params.CRm = (esr >> 1) & 0xf; 4082 params.is_write = ((esr & 1) == 0); 4083 4084 params.Op0 = 0; 4085 params.Op1 = (esr >> 16) & 0xf; 4086 params.Op2 = 0; 4087 params.CRn = 0; 4088 4089 /* 4090 * Make a 64-bit value out of Rt and Rt2. As we use the same trap 4091 * backends between AArch32 and AArch64, we get away with it. 4092 */ 4093 if (params.is_write) { 4094 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff; 4095 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32; 4096 } 4097 4098 /* 4099 * If the table contains a handler, handle the 4100 * potential register operation in the case of a read and return 4101 * with success. 4102 */ 4103 if (emulate_cp(vcpu, ¶ms, global, nr_global)) { 4104 /* Split up the value between registers for the read side */ 4105 if (!params.is_write) { 4106 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval)); 4107 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval)); 4108 } 4109 4110 return 1; 4111 } 4112 4113 unhandled_cp_access(vcpu, ¶ms); 4114 return 1; 4115 } 4116 4117 static bool emulate_sys_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *params); 4118 4119 /* 4120 * The CP10 ID registers are architecturally mapped to AArch64 feature 4121 * registers. Abuse that fact so we can rely on the AArch64 handler for accesses 4122 * from AArch32. 4123 */ 4124 static bool kvm_esr_cp10_id_to_sys64(u64 esr, struct sys_reg_params *params) 4125 { 4126 u8 reg_id = (esr >> 10) & 0xf; 4127 bool valid; 4128 4129 params->is_write = ((esr & 1) == 0); 4130 params->Op0 = 3; 4131 params->Op1 = 0; 4132 params->CRn = 0; 4133 params->CRm = 3; 4134 4135 /* CP10 ID registers are read-only */ 4136 valid = !params->is_write; 4137 4138 switch (reg_id) { 4139 /* MVFR0 */ 4140 case 0b0111: 4141 params->Op2 = 0; 4142 break; 4143 /* MVFR1 */ 4144 case 0b0110: 4145 params->Op2 = 1; 4146 break; 4147 /* MVFR2 */ 4148 case 0b0101: 4149 params->Op2 = 2; 4150 break; 4151 default: 4152 valid = false; 4153 } 4154 4155 if (valid) 4156 return true; 4157 4158 kvm_pr_unimpl("Unhandled cp10 register %s: %u\n", 4159 params->is_write ? "write" : "read", reg_id); 4160 return false; 4161 } 4162 4163 /** 4164 * kvm_handle_cp10_id() - Handles a VMRS trap on guest access to a 'Media and 4165 * VFP Register' from AArch32. 4166 * @vcpu: The vCPU pointer 4167 * 4168 * MVFR{0-2} are architecturally mapped to the AArch64 MVFR{0-2}_EL1 registers. 4169 * Work out the correct AArch64 system register encoding and reroute to the 4170 * AArch64 system register emulation. 4171 */ 4172 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu) 4173 { 4174 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4175 u64 esr = kvm_vcpu_get_esr(vcpu); 4176 struct sys_reg_params params; 4177 4178 /* UNDEF on any unhandled register access */ 4179 if (!kvm_esr_cp10_id_to_sys64(esr, ¶ms)) { 4180 kvm_inject_undefined(vcpu); 4181 return 1; 4182 } 4183 4184 if (emulate_sys_reg(vcpu, ¶ms)) 4185 vcpu_set_reg(vcpu, Rt, params.regval); 4186 4187 return 1; 4188 } 4189 4190 /** 4191 * kvm_emulate_cp15_id_reg() - Handles an MRC trap on a guest CP15 access where 4192 * CRn=0, which corresponds to the AArch32 feature 4193 * registers. 4194 * @vcpu: the vCPU pointer 4195 * @params: the system register access parameters. 4196 * 4197 * Our cp15 system register tables do not enumerate the AArch32 feature 4198 * registers. Conveniently, our AArch64 table does, and the AArch32 system 4199 * register encoding can be trivially remapped into the AArch64 for the feature 4200 * registers: Append op0=3, leaving op1, CRn, CRm, and op2 the same. 4201 * 4202 * According to DDI0487G.b G7.3.1, paragraph "Behavior of VMSAv8-32 32-bit 4203 * System registers with (coproc=0b1111, CRn==c0)", read accesses from this 4204 * range are either UNKNOWN or RES0. Rerouting remains architectural as we 4205 * treat undefined registers in this range as RAZ. 4206 */ 4207 static int kvm_emulate_cp15_id_reg(struct kvm_vcpu *vcpu, 4208 struct sys_reg_params *params) 4209 { 4210 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4211 4212 /* Treat impossible writes to RO registers as UNDEFINED */ 4213 if (params->is_write) { 4214 unhandled_cp_access(vcpu, params); 4215 return 1; 4216 } 4217 4218 params->Op0 = 3; 4219 4220 /* 4221 * All registers where CRm > 3 are known to be UNKNOWN/RAZ from AArch32. 4222 * Avoid conflicting with future expansion of AArch64 feature registers 4223 * and simply treat them as RAZ here. 4224 */ 4225 if (params->CRm > 3) 4226 params->regval = 0; 4227 else if (!emulate_sys_reg(vcpu, params)) 4228 return 1; 4229 4230 vcpu_set_reg(vcpu, Rt, params->regval); 4231 return 1; 4232 } 4233 4234 /** 4235 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access 4236 * @vcpu: The VCPU pointer 4237 * @params: &struct sys_reg_params 4238 * @global: &struct sys_reg_desc 4239 * @nr_global: size of the @global array 4240 */ 4241 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu, 4242 struct sys_reg_params *params, 4243 const struct sys_reg_desc *global, 4244 size_t nr_global) 4245 { 4246 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4247 4248 params->regval = vcpu_get_reg(vcpu, Rt); 4249 4250 if (emulate_cp(vcpu, params, global, nr_global)) { 4251 if (!params->is_write) 4252 vcpu_set_reg(vcpu, Rt, params->regval); 4253 return 1; 4254 } 4255 4256 unhandled_cp_access(vcpu, params); 4257 return 1; 4258 } 4259 4260 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu) 4261 { 4262 return kvm_handle_cp_64(vcpu, cp15_64_regs, ARRAY_SIZE(cp15_64_regs)); 4263 } 4264 4265 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu) 4266 { 4267 struct sys_reg_params params; 4268 4269 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu)); 4270 4271 /* 4272 * Certain AArch32 ID registers are handled by rerouting to the AArch64 4273 * system register table. Registers in the ID range where CRm=0 are 4274 * excluded from this scheme as they do not trivially map into AArch64 4275 * system register encodings. 4276 */ 4277 if (params.Op1 == 0 && params.CRn == 0 && params.CRm) 4278 return kvm_emulate_cp15_id_reg(vcpu, ¶ms); 4279 4280 return kvm_handle_cp_32(vcpu, ¶ms, cp15_regs, ARRAY_SIZE(cp15_regs)); 4281 } 4282 4283 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu) 4284 { 4285 return kvm_handle_cp_64(vcpu, cp14_64_regs, ARRAY_SIZE(cp14_64_regs)); 4286 } 4287 4288 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu) 4289 { 4290 struct sys_reg_params params; 4291 4292 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu)); 4293 4294 return kvm_handle_cp_32(vcpu, ¶ms, cp14_regs, ARRAY_SIZE(cp14_regs)); 4295 } 4296 4297 /** 4298 * emulate_sys_reg - Emulate a guest access to an AArch64 system register 4299 * @vcpu: The VCPU pointer 4300 * @params: Decoded system register parameters 4301 * 4302 * Return: true if the system register access was successful, false otherwise. 4303 */ 4304 static bool emulate_sys_reg(struct kvm_vcpu *vcpu, 4305 struct sys_reg_params *params) 4306 { 4307 const struct sys_reg_desc *r; 4308 4309 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 4310 if (likely(r)) { 4311 perform_access(vcpu, params, r); 4312 return true; 4313 } 4314 4315 print_sys_reg_msg(params, 4316 "Unsupported guest sys_reg access at: %lx [%08lx]\n", 4317 *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 4318 kvm_inject_undefined(vcpu); 4319 4320 return false; 4321 } 4322 4323 static const struct sys_reg_desc *idregs_debug_find(struct kvm *kvm, u8 pos) 4324 { 4325 unsigned long i, idreg_idx = 0; 4326 4327 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { 4328 const struct sys_reg_desc *r = &sys_reg_descs[i]; 4329 4330 if (!is_vm_ftr_id_reg(reg_to_encoding(r))) 4331 continue; 4332 4333 if (idreg_idx == pos) 4334 return r; 4335 4336 idreg_idx++; 4337 } 4338 4339 return NULL; 4340 } 4341 4342 static void *idregs_debug_start(struct seq_file *s, loff_t *pos) 4343 { 4344 struct kvm *kvm = s->private; 4345 u8 *iter; 4346 4347 mutex_lock(&kvm->arch.config_lock); 4348 4349 iter = &kvm->arch.idreg_debugfs_iter; 4350 if (test_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags) && 4351 *iter == (u8)~0) { 4352 *iter = *pos; 4353 if (!idregs_debug_find(kvm, *iter)) 4354 iter = NULL; 4355 } else { 4356 iter = ERR_PTR(-EBUSY); 4357 } 4358 4359 mutex_unlock(&kvm->arch.config_lock); 4360 4361 return iter; 4362 } 4363 4364 static void *idregs_debug_next(struct seq_file *s, void *v, loff_t *pos) 4365 { 4366 struct kvm *kvm = s->private; 4367 4368 (*pos)++; 4369 4370 if (idregs_debug_find(kvm, kvm->arch.idreg_debugfs_iter + 1)) { 4371 kvm->arch.idreg_debugfs_iter++; 4372 4373 return &kvm->arch.idreg_debugfs_iter; 4374 } 4375 4376 return NULL; 4377 } 4378 4379 static void idregs_debug_stop(struct seq_file *s, void *v) 4380 { 4381 struct kvm *kvm = s->private; 4382 4383 if (IS_ERR(v)) 4384 return; 4385 4386 mutex_lock(&kvm->arch.config_lock); 4387 4388 kvm->arch.idreg_debugfs_iter = ~0; 4389 4390 mutex_unlock(&kvm->arch.config_lock); 4391 } 4392 4393 static int idregs_debug_show(struct seq_file *s, void *v) 4394 { 4395 const struct sys_reg_desc *desc; 4396 struct kvm *kvm = s->private; 4397 4398 desc = idregs_debug_find(kvm, kvm->arch.idreg_debugfs_iter); 4399 4400 if (!desc->name) 4401 return 0; 4402 4403 seq_printf(s, "%20s:\t%016llx\n", 4404 desc->name, kvm_read_vm_id_reg(kvm, reg_to_encoding(desc))); 4405 4406 return 0; 4407 } 4408 4409 static const struct seq_operations idregs_debug_sops = { 4410 .start = idregs_debug_start, 4411 .next = idregs_debug_next, 4412 .stop = idregs_debug_stop, 4413 .show = idregs_debug_show, 4414 }; 4415 4416 DEFINE_SEQ_ATTRIBUTE(idregs_debug); 4417 4418 void kvm_sys_regs_create_debugfs(struct kvm *kvm) 4419 { 4420 kvm->arch.idreg_debugfs_iter = ~0; 4421 4422 debugfs_create_file("idregs", 0444, kvm->debugfs_dentry, kvm, 4423 &idregs_debug_fops); 4424 } 4425 4426 static void reset_vm_ftr_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *reg) 4427 { 4428 u32 id = reg_to_encoding(reg); 4429 struct kvm *kvm = vcpu->kvm; 4430 4431 if (test_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags)) 4432 return; 4433 4434 kvm_set_vm_id_reg(kvm, id, reg->reset(vcpu, reg)); 4435 } 4436 4437 static void reset_vcpu_ftr_id_reg(struct kvm_vcpu *vcpu, 4438 const struct sys_reg_desc *reg) 4439 { 4440 if (kvm_vcpu_initialized(vcpu)) 4441 return; 4442 4443 reg->reset(vcpu, reg); 4444 } 4445 4446 /** 4447 * kvm_reset_sys_regs - sets system registers to reset value 4448 * @vcpu: The VCPU pointer 4449 * 4450 * This function finds the right table above and sets the registers on the 4451 * virtual CPU struct to their architecturally defined reset values. 4452 */ 4453 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu) 4454 { 4455 struct kvm *kvm = vcpu->kvm; 4456 unsigned long i; 4457 4458 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { 4459 const struct sys_reg_desc *r = &sys_reg_descs[i]; 4460 4461 if (!r->reset) 4462 continue; 4463 4464 if (is_vm_ftr_id_reg(reg_to_encoding(r))) 4465 reset_vm_ftr_id_reg(vcpu, r); 4466 else if (is_vcpu_ftr_id_reg(reg_to_encoding(r))) 4467 reset_vcpu_ftr_id_reg(vcpu, r); 4468 else 4469 r->reset(vcpu, r); 4470 4471 if (r->reg >= __SANITISED_REG_START__ && r->reg < NR_SYS_REGS) 4472 (void)__vcpu_sys_reg(vcpu, r->reg); 4473 } 4474 4475 set_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags); 4476 } 4477 4478 /** 4479 * kvm_handle_sys_reg -- handles a system instruction or mrs/msr instruction 4480 * trap on a guest execution 4481 * @vcpu: The VCPU pointer 4482 */ 4483 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu) 4484 { 4485 const struct sys_reg_desc *desc = NULL; 4486 struct sys_reg_params params; 4487 unsigned long esr = kvm_vcpu_get_esr(vcpu); 4488 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4489 int sr_idx; 4490 4491 trace_kvm_handle_sys_reg(esr); 4492 4493 if (triage_sysreg_trap(vcpu, &sr_idx)) 4494 return 1; 4495 4496 params = esr_sys64_to_params(esr); 4497 params.regval = vcpu_get_reg(vcpu, Rt); 4498 4499 /* System registers have Op0=={2,3}, as per DDI487 J.a C5.1.2 */ 4500 if (params.Op0 == 2 || params.Op0 == 3) 4501 desc = &sys_reg_descs[sr_idx]; 4502 else 4503 desc = &sys_insn_descs[sr_idx]; 4504 4505 perform_access(vcpu, ¶ms, desc); 4506 4507 /* Read from system register? */ 4508 if (!params.is_write && 4509 (params.Op0 == 2 || params.Op0 == 3)) 4510 vcpu_set_reg(vcpu, Rt, params.regval); 4511 4512 return 1; 4513 } 4514 4515 /****************************************************************************** 4516 * Userspace API 4517 *****************************************************************************/ 4518 4519 static bool index_to_params(u64 id, struct sys_reg_params *params) 4520 { 4521 switch (id & KVM_REG_SIZE_MASK) { 4522 case KVM_REG_SIZE_U64: 4523 /* Any unused index bits means it's not valid. */ 4524 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK 4525 | KVM_REG_ARM_COPROC_MASK 4526 | KVM_REG_ARM64_SYSREG_OP0_MASK 4527 | KVM_REG_ARM64_SYSREG_OP1_MASK 4528 | KVM_REG_ARM64_SYSREG_CRN_MASK 4529 | KVM_REG_ARM64_SYSREG_CRM_MASK 4530 | KVM_REG_ARM64_SYSREG_OP2_MASK)) 4531 return false; 4532 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK) 4533 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT); 4534 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK) 4535 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT); 4536 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK) 4537 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT); 4538 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK) 4539 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT); 4540 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK) 4541 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT); 4542 return true; 4543 default: 4544 return false; 4545 } 4546 } 4547 4548 const struct sys_reg_desc *get_reg_by_id(u64 id, 4549 const struct sys_reg_desc table[], 4550 unsigned int num) 4551 { 4552 struct sys_reg_params params; 4553 4554 if (!index_to_params(id, ¶ms)) 4555 return NULL; 4556 4557 return find_reg(¶ms, table, num); 4558 } 4559 4560 /* Decode an index value, and find the sys_reg_desc entry. */ 4561 static const struct sys_reg_desc * 4562 id_to_sys_reg_desc(struct kvm_vcpu *vcpu, u64 id, 4563 const struct sys_reg_desc table[], unsigned int num) 4564 4565 { 4566 const struct sys_reg_desc *r; 4567 4568 /* We only do sys_reg for now. */ 4569 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG) 4570 return NULL; 4571 4572 r = get_reg_by_id(id, table, num); 4573 4574 /* Not saved in the sys_reg array and not otherwise accessible? */ 4575 if (r && (!(r->reg || r->get_user) || sysreg_hidden(vcpu, r))) 4576 r = NULL; 4577 4578 return r; 4579 } 4580 4581 /* 4582 * These are the invariant sys_reg registers: we let the guest see the 4583 * host versions of these, so they're part of the guest state. 4584 * 4585 * A future CPU may provide a mechanism to present different values to 4586 * the guest, or a future kvm may trap them. 4587 */ 4588 4589 #define FUNCTION_INVARIANT(reg) \ 4590 static u64 reset_##reg(struct kvm_vcpu *v, \ 4591 const struct sys_reg_desc *r) \ 4592 { \ 4593 ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \ 4594 return ((struct sys_reg_desc *)r)->val; \ 4595 } 4596 4597 FUNCTION_INVARIANT(midr_el1) 4598 FUNCTION_INVARIANT(revidr_el1) 4599 FUNCTION_INVARIANT(aidr_el1) 4600 4601 /* ->val is filled in by kvm_sys_reg_table_init() */ 4602 static struct sys_reg_desc invariant_sys_regs[] __ro_after_init = { 4603 { SYS_DESC(SYS_MIDR_EL1), NULL, reset_midr_el1 }, 4604 { SYS_DESC(SYS_REVIDR_EL1), NULL, reset_revidr_el1 }, 4605 { SYS_DESC(SYS_AIDR_EL1), NULL, reset_aidr_el1 }, 4606 }; 4607 4608 static int get_invariant_sys_reg(u64 id, u64 __user *uaddr) 4609 { 4610 const struct sys_reg_desc *r; 4611 4612 r = get_reg_by_id(id, invariant_sys_regs, 4613 ARRAY_SIZE(invariant_sys_regs)); 4614 if (!r) 4615 return -ENOENT; 4616 4617 return put_user(r->val, uaddr); 4618 } 4619 4620 static int set_invariant_sys_reg(u64 id, u64 __user *uaddr) 4621 { 4622 const struct sys_reg_desc *r; 4623 u64 val; 4624 4625 r = get_reg_by_id(id, invariant_sys_regs, 4626 ARRAY_SIZE(invariant_sys_regs)); 4627 if (!r) 4628 return -ENOENT; 4629 4630 if (get_user(val, uaddr)) 4631 return -EFAULT; 4632 4633 /* This is what we mean by invariant: you can't change it. */ 4634 if (r->val != val) 4635 return -EINVAL; 4636 4637 return 0; 4638 } 4639 4640 static int demux_c15_get(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) 4641 { 4642 u32 val; 4643 u32 __user *uval = uaddr; 4644 4645 /* Fail if we have unknown bits set. */ 4646 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 4647 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 4648 return -ENOENT; 4649 4650 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 4651 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 4652 if (KVM_REG_SIZE(id) != 4) 4653 return -ENOENT; 4654 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 4655 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 4656 if (val >= CSSELR_MAX) 4657 return -ENOENT; 4658 4659 return put_user(get_ccsidr(vcpu, val), uval); 4660 default: 4661 return -ENOENT; 4662 } 4663 } 4664 4665 static int demux_c15_set(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) 4666 { 4667 u32 val, newval; 4668 u32 __user *uval = uaddr; 4669 4670 /* Fail if we have unknown bits set. */ 4671 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 4672 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 4673 return -ENOENT; 4674 4675 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 4676 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 4677 if (KVM_REG_SIZE(id) != 4) 4678 return -ENOENT; 4679 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 4680 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 4681 if (val >= CSSELR_MAX) 4682 return -ENOENT; 4683 4684 if (get_user(newval, uval)) 4685 return -EFAULT; 4686 4687 return set_ccsidr(vcpu, val, newval); 4688 default: 4689 return -ENOENT; 4690 } 4691 } 4692 4693 int kvm_sys_reg_get_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg, 4694 const struct sys_reg_desc table[], unsigned int num) 4695 { 4696 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr; 4697 const struct sys_reg_desc *r; 4698 u64 val; 4699 int ret; 4700 4701 r = id_to_sys_reg_desc(vcpu, reg->id, table, num); 4702 if (!r || sysreg_hidden(vcpu, r)) 4703 return -ENOENT; 4704 4705 if (r->get_user) { 4706 ret = (r->get_user)(vcpu, r, &val); 4707 } else { 4708 val = __vcpu_sys_reg(vcpu, r->reg); 4709 ret = 0; 4710 } 4711 4712 if (!ret) 4713 ret = put_user(val, uaddr); 4714 4715 return ret; 4716 } 4717 4718 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 4719 { 4720 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 4721 int err; 4722 4723 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 4724 return demux_c15_get(vcpu, reg->id, uaddr); 4725 4726 err = get_invariant_sys_reg(reg->id, uaddr); 4727 if (err != -ENOENT) 4728 return err; 4729 4730 return kvm_sys_reg_get_user(vcpu, reg, 4731 sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 4732 } 4733 4734 int kvm_sys_reg_set_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg, 4735 const struct sys_reg_desc table[], unsigned int num) 4736 { 4737 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr; 4738 const struct sys_reg_desc *r; 4739 u64 val; 4740 int ret; 4741 4742 if (get_user(val, uaddr)) 4743 return -EFAULT; 4744 4745 r = id_to_sys_reg_desc(vcpu, reg->id, table, num); 4746 if (!r || sysreg_hidden(vcpu, r)) 4747 return -ENOENT; 4748 4749 if (sysreg_user_write_ignore(vcpu, r)) 4750 return 0; 4751 4752 if (r->set_user) { 4753 ret = (r->set_user)(vcpu, r, val); 4754 } else { 4755 __vcpu_sys_reg(vcpu, r->reg) = val; 4756 ret = 0; 4757 } 4758 4759 return ret; 4760 } 4761 4762 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 4763 { 4764 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 4765 int err; 4766 4767 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 4768 return demux_c15_set(vcpu, reg->id, uaddr); 4769 4770 err = set_invariant_sys_reg(reg->id, uaddr); 4771 if (err != -ENOENT) 4772 return err; 4773 4774 return kvm_sys_reg_set_user(vcpu, reg, 4775 sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 4776 } 4777 4778 static unsigned int num_demux_regs(void) 4779 { 4780 return CSSELR_MAX; 4781 } 4782 4783 static int write_demux_regids(u64 __user *uindices) 4784 { 4785 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX; 4786 unsigned int i; 4787 4788 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR; 4789 for (i = 0; i < CSSELR_MAX; i++) { 4790 if (put_user(val | i, uindices)) 4791 return -EFAULT; 4792 uindices++; 4793 } 4794 return 0; 4795 } 4796 4797 static u64 sys_reg_to_index(const struct sys_reg_desc *reg) 4798 { 4799 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | 4800 KVM_REG_ARM64_SYSREG | 4801 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) | 4802 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) | 4803 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) | 4804 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) | 4805 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT)); 4806 } 4807 4808 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind) 4809 { 4810 if (!*uind) 4811 return true; 4812 4813 if (put_user(sys_reg_to_index(reg), *uind)) 4814 return false; 4815 4816 (*uind)++; 4817 return true; 4818 } 4819 4820 static int walk_one_sys_reg(const struct kvm_vcpu *vcpu, 4821 const struct sys_reg_desc *rd, 4822 u64 __user **uind, 4823 unsigned int *total) 4824 { 4825 /* 4826 * Ignore registers we trap but don't save, 4827 * and for which no custom user accessor is provided. 4828 */ 4829 if (!(rd->reg || rd->get_user)) 4830 return 0; 4831 4832 if (sysreg_hidden(vcpu, rd)) 4833 return 0; 4834 4835 if (!copy_reg_to_user(rd, uind)) 4836 return -EFAULT; 4837 4838 (*total)++; 4839 return 0; 4840 } 4841 4842 /* Assumed ordered tables, see kvm_sys_reg_table_init. */ 4843 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind) 4844 { 4845 const struct sys_reg_desc *i2, *end2; 4846 unsigned int total = 0; 4847 int err; 4848 4849 i2 = sys_reg_descs; 4850 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs); 4851 4852 while (i2 != end2) { 4853 err = walk_one_sys_reg(vcpu, i2++, &uind, &total); 4854 if (err) 4855 return err; 4856 } 4857 return total; 4858 } 4859 4860 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu) 4861 { 4862 return ARRAY_SIZE(invariant_sys_regs) 4863 + num_demux_regs() 4864 + walk_sys_regs(vcpu, (u64 __user *)NULL); 4865 } 4866 4867 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) 4868 { 4869 unsigned int i; 4870 int err; 4871 4872 /* Then give them all the invariant registers' indices. */ 4873 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) { 4874 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices)) 4875 return -EFAULT; 4876 uindices++; 4877 } 4878 4879 err = walk_sys_regs(vcpu, uindices); 4880 if (err < 0) 4881 return err; 4882 uindices += err; 4883 4884 return write_demux_regids(uindices); 4885 } 4886 4887 #define KVM_ARM_FEATURE_ID_RANGE_INDEX(r) \ 4888 KVM_ARM_FEATURE_ID_RANGE_IDX(sys_reg_Op0(r), \ 4889 sys_reg_Op1(r), \ 4890 sys_reg_CRn(r), \ 4891 sys_reg_CRm(r), \ 4892 sys_reg_Op2(r)) 4893 4894 int kvm_vm_ioctl_get_reg_writable_masks(struct kvm *kvm, struct reg_mask_range *range) 4895 { 4896 const void *zero_page = page_to_virt(ZERO_PAGE(0)); 4897 u64 __user *masks = (u64 __user *)range->addr; 4898 4899 /* Only feature id range is supported, reserved[13] must be zero. */ 4900 if (range->range || 4901 memcmp(range->reserved, zero_page, sizeof(range->reserved))) 4902 return -EINVAL; 4903 4904 /* Wipe the whole thing first */ 4905 if (clear_user(masks, KVM_ARM_FEATURE_ID_RANGE_SIZE * sizeof(__u64))) 4906 return -EFAULT; 4907 4908 for (int i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { 4909 const struct sys_reg_desc *reg = &sys_reg_descs[i]; 4910 u32 encoding = reg_to_encoding(reg); 4911 u64 val; 4912 4913 if (!is_feature_id_reg(encoding) || !reg->set_user) 4914 continue; 4915 4916 if (!reg->val || 4917 (is_aa32_id_reg(encoding) && !kvm_supports_32bit_el0())) { 4918 continue; 4919 } 4920 val = reg->val; 4921 4922 if (put_user(val, (masks + KVM_ARM_FEATURE_ID_RANGE_INDEX(encoding)))) 4923 return -EFAULT; 4924 } 4925 4926 return 0; 4927 } 4928 4929 static void vcpu_set_hcr(struct kvm_vcpu *vcpu) 4930 { 4931 struct kvm *kvm = vcpu->kvm; 4932 4933 if (has_vhe() || has_hvhe()) 4934 vcpu->arch.hcr_el2 |= HCR_E2H; 4935 if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN)) { 4936 /* route synchronous external abort exceptions to EL2 */ 4937 vcpu->arch.hcr_el2 |= HCR_TEA; 4938 /* trap error record accesses */ 4939 vcpu->arch.hcr_el2 |= HCR_TERR; 4940 } 4941 4942 if (cpus_have_final_cap(ARM64_HAS_STAGE2_FWB)) 4943 vcpu->arch.hcr_el2 |= HCR_FWB; 4944 4945 if (cpus_have_final_cap(ARM64_HAS_EVT) && 4946 !cpus_have_final_cap(ARM64_MISMATCHED_CACHE_TYPE) && 4947 kvm_read_vm_id_reg(kvm, SYS_CTR_EL0) == read_sanitised_ftr_reg(SYS_CTR_EL0)) 4948 vcpu->arch.hcr_el2 |= HCR_TID4; 4949 else 4950 vcpu->arch.hcr_el2 |= HCR_TID2; 4951 4952 if (vcpu_el1_is_32bit(vcpu)) 4953 vcpu->arch.hcr_el2 &= ~HCR_RW; 4954 4955 if (kvm_has_mte(vcpu->kvm)) 4956 vcpu->arch.hcr_el2 |= HCR_ATA; 4957 4958 /* 4959 * In the absence of FGT, we cannot independently trap TLBI 4960 * Range instructions. This isn't great, but trapping all 4961 * TLBIs would be far worse. Live with it... 4962 */ 4963 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 4964 vcpu->arch.hcr_el2 |= HCR_TTLBOS; 4965 } 4966 4967 void kvm_calculate_traps(struct kvm_vcpu *vcpu) 4968 { 4969 struct kvm *kvm = vcpu->kvm; 4970 4971 mutex_lock(&kvm->arch.config_lock); 4972 vcpu_set_hcr(vcpu); 4973 vcpu_set_ich_hcr(vcpu); 4974 4975 if (cpus_have_final_cap(ARM64_HAS_HCX)) { 4976 /* 4977 * In general, all HCRX_EL2 bits are gated by a feature. 4978 * The only reason we can set SMPME without checking any 4979 * feature is that its effects are not directly observable 4980 * from the guest. 4981 */ 4982 vcpu->arch.hcrx_el2 = HCRX_EL2_SMPME; 4983 4984 if (kvm_has_feat(kvm, ID_AA64ISAR2_EL1, MOPS, IMP)) 4985 vcpu->arch.hcrx_el2 |= (HCRX_EL2_MSCEn | HCRX_EL2_MCE2); 4986 4987 if (kvm_has_tcr2(kvm)) 4988 vcpu->arch.hcrx_el2 |= HCRX_EL2_TCR2En; 4989 4990 if (kvm_has_fpmr(kvm)) 4991 vcpu->arch.hcrx_el2 |= HCRX_EL2_EnFPM; 4992 } 4993 4994 if (test_bit(KVM_ARCH_FLAG_FGU_INITIALIZED, &kvm->arch.flags)) 4995 goto out; 4996 4997 kvm->arch.fgu[HFGxTR_GROUP] = (HFGxTR_EL2_nAMAIR2_EL1 | 4998 HFGxTR_EL2_nMAIR2_EL1 | 4999 HFGxTR_EL2_nS2POR_EL1 | 5000 HFGxTR_EL2_nACCDATA_EL1 | 5001 HFGxTR_EL2_nSMPRI_EL1_MASK | 5002 HFGxTR_EL2_nTPIDR2_EL0_MASK); 5003 5004 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 5005 kvm->arch.fgu[HFGITR_GROUP] |= (HFGITR_EL2_TLBIRVAALE1OS| 5006 HFGITR_EL2_TLBIRVALE1OS | 5007 HFGITR_EL2_TLBIRVAAE1OS | 5008 HFGITR_EL2_TLBIRVAE1OS | 5009 HFGITR_EL2_TLBIVAALE1OS | 5010 HFGITR_EL2_TLBIVALE1OS | 5011 HFGITR_EL2_TLBIVAAE1OS | 5012 HFGITR_EL2_TLBIASIDE1OS | 5013 HFGITR_EL2_TLBIVAE1OS | 5014 HFGITR_EL2_TLBIVMALLE1OS); 5015 5016 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE)) 5017 kvm->arch.fgu[HFGITR_GROUP] |= (HFGITR_EL2_TLBIRVAALE1 | 5018 HFGITR_EL2_TLBIRVALE1 | 5019 HFGITR_EL2_TLBIRVAAE1 | 5020 HFGITR_EL2_TLBIRVAE1 | 5021 HFGITR_EL2_TLBIRVAALE1IS| 5022 HFGITR_EL2_TLBIRVALE1IS | 5023 HFGITR_EL2_TLBIRVAAE1IS | 5024 HFGITR_EL2_TLBIRVAE1IS | 5025 HFGITR_EL2_TLBIRVAALE1OS| 5026 HFGITR_EL2_TLBIRVALE1OS | 5027 HFGITR_EL2_TLBIRVAAE1OS | 5028 HFGITR_EL2_TLBIRVAE1OS); 5029 5030 if (!kvm_has_feat(kvm, ID_AA64ISAR2_EL1, ATS1A, IMP)) 5031 kvm->arch.fgu[HFGITR_GROUP] |= HFGITR_EL2_ATS1E1A; 5032 5033 if (!kvm_has_feat(kvm, ID_AA64MMFR1_EL1, PAN, PAN2)) 5034 kvm->arch.fgu[HFGITR_GROUP] |= (HFGITR_EL2_ATS1E1RP | 5035 HFGITR_EL2_ATS1E1WP); 5036 5037 if (!kvm_has_s1pie(kvm)) 5038 kvm->arch.fgu[HFGxTR_GROUP] |= (HFGxTR_EL2_nPIRE0_EL1 | 5039 HFGxTR_EL2_nPIR_EL1); 5040 5041 if (!kvm_has_s1poe(kvm)) 5042 kvm->arch.fgu[HFGxTR_GROUP] |= (HFGxTR_EL2_nPOR_EL1 | 5043 HFGxTR_EL2_nPOR_EL0); 5044 5045 if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, AMU, IMP)) 5046 kvm->arch.fgu[HAFGRTR_GROUP] |= ~(HAFGRTR_EL2_RES0 | 5047 HAFGRTR_EL2_RES1); 5048 5049 if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, BRBE, IMP)) { 5050 kvm->arch.fgu[HDFGRTR_GROUP] |= (HDFGRTR_EL2_nBRBDATA | 5051 HDFGRTR_EL2_nBRBCTL | 5052 HDFGRTR_EL2_nBRBIDR); 5053 kvm->arch.fgu[HFGITR_GROUP] |= (HFGITR_EL2_nBRBINJ | 5054 HFGITR_EL2_nBRBIALL); 5055 } 5056 5057 set_bit(KVM_ARCH_FLAG_FGU_INITIALIZED, &kvm->arch.flags); 5058 out: 5059 mutex_unlock(&kvm->arch.config_lock); 5060 } 5061 5062 /* 5063 * Perform last adjustments to the ID registers that are implied by the 5064 * configuration outside of the ID regs themselves, as well as any 5065 * initialisation that directly depend on these ID registers (such as 5066 * RES0/RES1 behaviours). This is not the place to configure traps though. 5067 * 5068 * Because this can be called once per CPU, changes must be idempotent. 5069 */ 5070 int kvm_finalize_sys_regs(struct kvm_vcpu *vcpu) 5071 { 5072 struct kvm *kvm = vcpu->kvm; 5073 5074 guard(mutex)(&kvm->arch.config_lock); 5075 5076 if (!(static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif) && 5077 irqchip_in_kernel(kvm) && 5078 kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3)) { 5079 kvm->arch.id_regs[IDREG_IDX(SYS_ID_AA64PFR0_EL1)] &= ~ID_AA64PFR0_EL1_GIC_MASK; 5080 kvm->arch.id_regs[IDREG_IDX(SYS_ID_PFR1_EL1)] &= ~ID_PFR1_EL1_GIC_MASK; 5081 } 5082 5083 if (vcpu_has_nv(vcpu)) { 5084 int ret = kvm_init_nv_sysregs(vcpu); 5085 if (ret) 5086 return ret; 5087 } 5088 5089 return 0; 5090 } 5091 5092 int __init kvm_sys_reg_table_init(void) 5093 { 5094 bool valid = true; 5095 unsigned int i; 5096 int ret = 0; 5097 5098 /* Make sure tables are unique and in order. */ 5099 valid &= check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), false); 5100 valid &= check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), true); 5101 valid &= check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), true); 5102 valid &= check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), true); 5103 valid &= check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), true); 5104 valid &= check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs), false); 5105 valid &= check_sysreg_table(sys_insn_descs, ARRAY_SIZE(sys_insn_descs), false); 5106 5107 if (!valid) 5108 return -EINVAL; 5109 5110 /* We abuse the reset function to overwrite the table itself. */ 5111 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) 5112 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]); 5113 5114 ret = populate_nv_trap_config(); 5115 5116 for (i = 0; !ret && i < ARRAY_SIZE(sys_reg_descs); i++) 5117 ret = populate_sysreg_config(sys_reg_descs + i, i); 5118 5119 for (i = 0; !ret && i < ARRAY_SIZE(sys_insn_descs); i++) 5120 ret = populate_sysreg_config(sys_insn_descs + i, i); 5121 5122 return ret; 5123 } 5124