1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2017 - Columbia University and Linaro Ltd. 4 * Author: Jintack Lim <jintack.lim@linaro.org> 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/kvm.h> 9 #include <linux/kvm_host.h> 10 11 #include <asm/kvm_arm.h> 12 #include <asm/kvm_emulate.h> 13 #include <asm/kvm_mmu.h> 14 #include <asm/kvm_nested.h> 15 #include <asm/sysreg.h> 16 17 #include "sys_regs.h" 18 19 /* Protection against the sysreg repainting madness... */ 20 #define NV_FTR(r, f) ID_AA64##r##_EL1_##f 21 22 /* 23 * Ratio of live shadow S2 MMU per vcpu. This is a trade-off between 24 * memory usage and potential number of different sets of S2 PTs in 25 * the guests. Running out of S2 MMUs only affects performance (we 26 * will invalidate them more often). 27 */ 28 #define S2_MMU_PER_VCPU 2 29 30 void kvm_init_nested(struct kvm *kvm) 31 { 32 kvm->arch.nested_mmus = NULL; 33 kvm->arch.nested_mmus_size = 0; 34 } 35 36 static int init_nested_s2_mmu(struct kvm *kvm, struct kvm_s2_mmu *mmu) 37 { 38 /* 39 * We only initialise the IPA range on the canonical MMU, which 40 * defines the contract between KVM and userspace on where the 41 * "hardware" is in the IPA space. This affects the validity of MMIO 42 * exits forwarded to userspace, for example. 43 * 44 * For nested S2s, we use the PARange as exposed to the guest, as it 45 * is allowed to use it at will to expose whatever memory map it 46 * wants to its own guests as it would be on real HW. 47 */ 48 return kvm_init_stage2_mmu(kvm, mmu, kvm_get_pa_bits(kvm)); 49 } 50 51 int kvm_vcpu_init_nested(struct kvm_vcpu *vcpu) 52 { 53 struct kvm *kvm = vcpu->kvm; 54 struct kvm_s2_mmu *tmp; 55 int num_mmus, ret = 0; 56 57 /* 58 * Let's treat memory allocation failures as benign: If we fail to 59 * allocate anything, return an error and keep the allocated array 60 * alive. Userspace may try to recover by intializing the vcpu 61 * again, and there is no reason to affect the whole VM for this. 62 */ 63 num_mmus = atomic_read(&kvm->online_vcpus) * S2_MMU_PER_VCPU; 64 tmp = kvrealloc(kvm->arch.nested_mmus, 65 size_mul(sizeof(*kvm->arch.nested_mmus), num_mmus), 66 GFP_KERNEL_ACCOUNT | __GFP_ZERO); 67 if (!tmp) 68 return -ENOMEM; 69 70 /* 71 * If we went through a realocation, adjust the MMU back-pointers in 72 * the previously initialised kvm_pgtable structures. 73 */ 74 if (kvm->arch.nested_mmus != tmp) 75 for (int i = 0; i < kvm->arch.nested_mmus_size; i++) 76 tmp[i].pgt->mmu = &tmp[i]; 77 78 for (int i = kvm->arch.nested_mmus_size; !ret && i < num_mmus; i++) 79 ret = init_nested_s2_mmu(kvm, &tmp[i]); 80 81 if (ret) { 82 for (int i = kvm->arch.nested_mmus_size; i < num_mmus; i++) 83 kvm_free_stage2_pgd(&tmp[i]); 84 85 return ret; 86 } 87 88 kvm->arch.nested_mmus_size = num_mmus; 89 kvm->arch.nested_mmus = tmp; 90 91 return 0; 92 } 93 94 struct s2_walk_info { 95 int (*read_desc)(phys_addr_t pa, u64 *desc, void *data); 96 void *data; 97 u64 baddr; 98 unsigned int max_oa_bits; 99 unsigned int pgshift; 100 unsigned int sl; 101 unsigned int t0sz; 102 bool be; 103 }; 104 105 static unsigned int ps_to_output_size(unsigned int ps) 106 { 107 switch (ps) { 108 case 0: return 32; 109 case 1: return 36; 110 case 2: return 40; 111 case 3: return 42; 112 case 4: return 44; 113 case 5: 114 default: 115 return 48; 116 } 117 } 118 119 static u32 compute_fsc(int level, u32 fsc) 120 { 121 return fsc | (level & 0x3); 122 } 123 124 static int esr_s2_fault(struct kvm_vcpu *vcpu, int level, u32 fsc) 125 { 126 u32 esr; 127 128 esr = kvm_vcpu_get_esr(vcpu) & ~ESR_ELx_FSC; 129 esr |= compute_fsc(level, fsc); 130 return esr; 131 } 132 133 static int get_ia_size(struct s2_walk_info *wi) 134 { 135 return 64 - wi->t0sz; 136 } 137 138 static int check_base_s2_limits(struct s2_walk_info *wi, 139 int level, int input_size, int stride) 140 { 141 int start_size, ia_size; 142 143 ia_size = get_ia_size(wi); 144 145 /* Check translation limits */ 146 switch (BIT(wi->pgshift)) { 147 case SZ_64K: 148 if (level == 0 || (level == 1 && ia_size <= 42)) 149 return -EFAULT; 150 break; 151 case SZ_16K: 152 if (level == 0 || (level == 1 && ia_size <= 40)) 153 return -EFAULT; 154 break; 155 case SZ_4K: 156 if (level < 0 || (level == 0 && ia_size <= 42)) 157 return -EFAULT; 158 break; 159 } 160 161 /* Check input size limits */ 162 if (input_size > ia_size) 163 return -EFAULT; 164 165 /* Check number of entries in starting level table */ 166 start_size = input_size - ((3 - level) * stride + wi->pgshift); 167 if (start_size < 1 || start_size > stride + 4) 168 return -EFAULT; 169 170 return 0; 171 } 172 173 /* Check if output is within boundaries */ 174 static int check_output_size(struct s2_walk_info *wi, phys_addr_t output) 175 { 176 unsigned int output_size = wi->max_oa_bits; 177 178 if (output_size != 48 && (output & GENMASK_ULL(47, output_size))) 179 return -1; 180 181 return 0; 182 } 183 184 /* 185 * This is essentially a C-version of the pseudo code from the ARM ARM 186 * AArch64.TranslationTableWalk function. I strongly recommend looking at 187 * that pseudocode in trying to understand this. 188 * 189 * Must be called with the kvm->srcu read lock held 190 */ 191 static int walk_nested_s2_pgd(phys_addr_t ipa, 192 struct s2_walk_info *wi, struct kvm_s2_trans *out) 193 { 194 int first_block_level, level, stride, input_size, base_lower_bound; 195 phys_addr_t base_addr; 196 unsigned int addr_top, addr_bottom; 197 u64 desc; /* page table entry */ 198 int ret; 199 phys_addr_t paddr; 200 201 switch (BIT(wi->pgshift)) { 202 default: 203 case SZ_64K: 204 case SZ_16K: 205 level = 3 - wi->sl; 206 first_block_level = 2; 207 break; 208 case SZ_4K: 209 level = 2 - wi->sl; 210 first_block_level = 1; 211 break; 212 } 213 214 stride = wi->pgshift - 3; 215 input_size = get_ia_size(wi); 216 if (input_size > 48 || input_size < 25) 217 return -EFAULT; 218 219 ret = check_base_s2_limits(wi, level, input_size, stride); 220 if (WARN_ON(ret)) 221 return ret; 222 223 base_lower_bound = 3 + input_size - ((3 - level) * stride + 224 wi->pgshift); 225 base_addr = wi->baddr & GENMASK_ULL(47, base_lower_bound); 226 227 if (check_output_size(wi, base_addr)) { 228 out->esr = compute_fsc(level, ESR_ELx_FSC_ADDRSZ); 229 return 1; 230 } 231 232 addr_top = input_size - 1; 233 234 while (1) { 235 phys_addr_t index; 236 237 addr_bottom = (3 - level) * stride + wi->pgshift; 238 index = (ipa & GENMASK_ULL(addr_top, addr_bottom)) 239 >> (addr_bottom - 3); 240 241 paddr = base_addr | index; 242 ret = wi->read_desc(paddr, &desc, wi->data); 243 if (ret < 0) 244 return ret; 245 246 /* 247 * Handle reversedescriptors if endianness differs between the 248 * host and the guest hypervisor. 249 */ 250 if (wi->be) 251 desc = be64_to_cpu((__force __be64)desc); 252 else 253 desc = le64_to_cpu((__force __le64)desc); 254 255 /* Check for valid descriptor at this point */ 256 if (!(desc & 1) || ((desc & 3) == 1 && level == 3)) { 257 out->esr = compute_fsc(level, ESR_ELx_FSC_FAULT); 258 out->upper_attr = desc; 259 return 1; 260 } 261 262 /* We're at the final level or block translation level */ 263 if ((desc & 3) == 1 || level == 3) 264 break; 265 266 if (check_output_size(wi, desc)) { 267 out->esr = compute_fsc(level, ESR_ELx_FSC_ADDRSZ); 268 out->upper_attr = desc; 269 return 1; 270 } 271 272 base_addr = desc & GENMASK_ULL(47, wi->pgshift); 273 274 level += 1; 275 addr_top = addr_bottom - 1; 276 } 277 278 if (level < first_block_level) { 279 out->esr = compute_fsc(level, ESR_ELx_FSC_FAULT); 280 out->upper_attr = desc; 281 return 1; 282 } 283 284 /* 285 * We don't use the contiguous bit in the stage-2 ptes, so skip check 286 * for misprogramming of the contiguous bit. 287 */ 288 289 if (check_output_size(wi, desc)) { 290 out->esr = compute_fsc(level, ESR_ELx_FSC_ADDRSZ); 291 out->upper_attr = desc; 292 return 1; 293 } 294 295 if (!(desc & BIT(10))) { 296 out->esr = compute_fsc(level, ESR_ELx_FSC_ACCESS); 297 out->upper_attr = desc; 298 return 1; 299 } 300 301 /* Calculate and return the result */ 302 paddr = (desc & GENMASK_ULL(47, addr_bottom)) | 303 (ipa & GENMASK_ULL(addr_bottom - 1, 0)); 304 out->output = paddr; 305 out->block_size = 1UL << ((3 - level) * stride + wi->pgshift); 306 out->readable = desc & (0b01 << 6); 307 out->writable = desc & (0b10 << 6); 308 out->level = level; 309 out->upper_attr = desc & GENMASK_ULL(63, 52); 310 return 0; 311 } 312 313 static int read_guest_s2_desc(phys_addr_t pa, u64 *desc, void *data) 314 { 315 struct kvm_vcpu *vcpu = data; 316 317 return kvm_read_guest(vcpu->kvm, pa, desc, sizeof(*desc)); 318 } 319 320 static void vtcr_to_walk_info(u64 vtcr, struct s2_walk_info *wi) 321 { 322 wi->t0sz = vtcr & TCR_EL2_T0SZ_MASK; 323 324 switch (vtcr & VTCR_EL2_TG0_MASK) { 325 case VTCR_EL2_TG0_4K: 326 wi->pgshift = 12; break; 327 case VTCR_EL2_TG0_16K: 328 wi->pgshift = 14; break; 329 case VTCR_EL2_TG0_64K: 330 default: /* IMPDEF: treat any other value as 64k */ 331 wi->pgshift = 16; break; 332 } 333 334 wi->sl = FIELD_GET(VTCR_EL2_SL0_MASK, vtcr); 335 /* Global limit for now, should eventually be per-VM */ 336 wi->max_oa_bits = min(get_kvm_ipa_limit(), 337 ps_to_output_size(FIELD_GET(VTCR_EL2_PS_MASK, vtcr))); 338 } 339 340 int kvm_walk_nested_s2(struct kvm_vcpu *vcpu, phys_addr_t gipa, 341 struct kvm_s2_trans *result) 342 { 343 u64 vtcr = vcpu_read_sys_reg(vcpu, VTCR_EL2); 344 struct s2_walk_info wi; 345 int ret; 346 347 result->esr = 0; 348 349 if (!vcpu_has_nv(vcpu)) 350 return 0; 351 352 wi.read_desc = read_guest_s2_desc; 353 wi.data = vcpu; 354 wi.baddr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 355 356 vtcr_to_walk_info(vtcr, &wi); 357 358 wi.be = vcpu_read_sys_reg(vcpu, SCTLR_EL2) & SCTLR_ELx_EE; 359 360 ret = walk_nested_s2_pgd(gipa, &wi, result); 361 if (ret) 362 result->esr |= (kvm_vcpu_get_esr(vcpu) & ~ESR_ELx_FSC); 363 364 return ret; 365 } 366 367 static unsigned int ttl_to_size(u8 ttl) 368 { 369 int level = ttl & 3; 370 int gran = (ttl >> 2) & 3; 371 unsigned int max_size = 0; 372 373 switch (gran) { 374 case TLBI_TTL_TG_4K: 375 switch (level) { 376 case 0: 377 break; 378 case 1: 379 max_size = SZ_1G; 380 break; 381 case 2: 382 max_size = SZ_2M; 383 break; 384 case 3: 385 max_size = SZ_4K; 386 break; 387 } 388 break; 389 case TLBI_TTL_TG_16K: 390 switch (level) { 391 case 0: 392 case 1: 393 break; 394 case 2: 395 max_size = SZ_32M; 396 break; 397 case 3: 398 max_size = SZ_16K; 399 break; 400 } 401 break; 402 case TLBI_TTL_TG_64K: 403 switch (level) { 404 case 0: 405 case 1: 406 /* No 52bit IPA support */ 407 break; 408 case 2: 409 max_size = SZ_512M; 410 break; 411 case 3: 412 max_size = SZ_64K; 413 break; 414 } 415 break; 416 default: /* No size information */ 417 break; 418 } 419 420 return max_size; 421 } 422 423 /* 424 * Compute the equivalent of the TTL field by parsing the shadow PT. The 425 * granule size is extracted from the cached VTCR_EL2.TG0 while the level is 426 * retrieved from first entry carrying the level as a tag. 427 */ 428 static u8 get_guest_mapping_ttl(struct kvm_s2_mmu *mmu, u64 addr) 429 { 430 u64 tmp, sz = 0, vtcr = mmu->tlb_vtcr; 431 kvm_pte_t pte; 432 u8 ttl, level; 433 434 lockdep_assert_held_write(&kvm_s2_mmu_to_kvm(mmu)->mmu_lock); 435 436 switch (vtcr & VTCR_EL2_TG0_MASK) { 437 case VTCR_EL2_TG0_4K: 438 ttl = (TLBI_TTL_TG_4K << 2); 439 break; 440 case VTCR_EL2_TG0_16K: 441 ttl = (TLBI_TTL_TG_16K << 2); 442 break; 443 case VTCR_EL2_TG0_64K: 444 default: /* IMPDEF: treat any other value as 64k */ 445 ttl = (TLBI_TTL_TG_64K << 2); 446 break; 447 } 448 449 tmp = addr; 450 451 again: 452 /* Iteratively compute the block sizes for a particular granule size */ 453 switch (vtcr & VTCR_EL2_TG0_MASK) { 454 case VTCR_EL2_TG0_4K: 455 if (sz < SZ_4K) sz = SZ_4K; 456 else if (sz < SZ_2M) sz = SZ_2M; 457 else if (sz < SZ_1G) sz = SZ_1G; 458 else sz = 0; 459 break; 460 case VTCR_EL2_TG0_16K: 461 if (sz < SZ_16K) sz = SZ_16K; 462 else if (sz < SZ_32M) sz = SZ_32M; 463 else sz = 0; 464 break; 465 case VTCR_EL2_TG0_64K: 466 default: /* IMPDEF: treat any other value as 64k */ 467 if (sz < SZ_64K) sz = SZ_64K; 468 else if (sz < SZ_512M) sz = SZ_512M; 469 else sz = 0; 470 break; 471 } 472 473 if (sz == 0) 474 return 0; 475 476 tmp &= ~(sz - 1); 477 if (kvm_pgtable_get_leaf(mmu->pgt, tmp, &pte, NULL)) 478 goto again; 479 if (!(pte & PTE_VALID)) 480 goto again; 481 level = FIELD_GET(KVM_NV_GUEST_MAP_SZ, pte); 482 if (!level) 483 goto again; 484 485 ttl |= level; 486 487 /* 488 * We now have found some level information in the shadow S2. Check 489 * that the resulting range is actually including the original IPA. 490 */ 491 sz = ttl_to_size(ttl); 492 if (addr < (tmp + sz)) 493 return ttl; 494 495 return 0; 496 } 497 498 unsigned long compute_tlb_inval_range(struct kvm_s2_mmu *mmu, u64 val) 499 { 500 struct kvm *kvm = kvm_s2_mmu_to_kvm(mmu); 501 unsigned long max_size; 502 u8 ttl; 503 504 ttl = FIELD_GET(TLBI_TTL_MASK, val); 505 506 if (!ttl || !kvm_has_feat(kvm, ID_AA64MMFR2_EL1, TTL, IMP)) { 507 /* No TTL, check the shadow S2 for a hint */ 508 u64 addr = (val & GENMASK_ULL(35, 0)) << 12; 509 ttl = get_guest_mapping_ttl(mmu, addr); 510 } 511 512 max_size = ttl_to_size(ttl); 513 514 if (!max_size) { 515 /* Compute the maximum extent of the invalidation */ 516 switch (mmu->tlb_vtcr & VTCR_EL2_TG0_MASK) { 517 case VTCR_EL2_TG0_4K: 518 max_size = SZ_1G; 519 break; 520 case VTCR_EL2_TG0_16K: 521 max_size = SZ_32M; 522 break; 523 case VTCR_EL2_TG0_64K: 524 default: /* IMPDEF: treat any other value as 64k */ 525 /* 526 * No, we do not support 52bit IPA in nested yet. Once 527 * we do, this should be 4TB. 528 */ 529 max_size = SZ_512M; 530 break; 531 } 532 } 533 534 WARN_ON(!max_size); 535 return max_size; 536 } 537 538 /* 539 * We can have multiple *different* MMU contexts with the same VMID: 540 * 541 * - S2 being enabled or not, hence differing by the HCR_EL2.VM bit 542 * 543 * - Multiple vcpus using private S2s (huh huh...), hence differing by the 544 * VBBTR_EL2.BADDR address 545 * 546 * - A combination of the above... 547 * 548 * We can always identify which MMU context to pick at run-time. However, 549 * TLB invalidation involving a VMID must take action on all the TLBs using 550 * this particular VMID. This translates into applying the same invalidation 551 * operation to all the contexts that are using this VMID. Moar phun! 552 */ 553 void kvm_s2_mmu_iterate_by_vmid(struct kvm *kvm, u16 vmid, 554 const union tlbi_info *info, 555 void (*tlbi_callback)(struct kvm_s2_mmu *, 556 const union tlbi_info *)) 557 { 558 write_lock(&kvm->mmu_lock); 559 560 for (int i = 0; i < kvm->arch.nested_mmus_size; i++) { 561 struct kvm_s2_mmu *mmu = &kvm->arch.nested_mmus[i]; 562 563 if (!kvm_s2_mmu_valid(mmu)) 564 continue; 565 566 if (vmid == get_vmid(mmu->tlb_vttbr)) 567 tlbi_callback(mmu, info); 568 } 569 570 write_unlock(&kvm->mmu_lock); 571 } 572 573 struct kvm_s2_mmu *lookup_s2_mmu(struct kvm_vcpu *vcpu) 574 { 575 struct kvm *kvm = vcpu->kvm; 576 bool nested_stage2_enabled; 577 u64 vttbr, vtcr, hcr; 578 579 lockdep_assert_held_write(&kvm->mmu_lock); 580 581 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 582 vtcr = vcpu_read_sys_reg(vcpu, VTCR_EL2); 583 hcr = vcpu_read_sys_reg(vcpu, HCR_EL2); 584 585 nested_stage2_enabled = hcr & HCR_VM; 586 587 /* Don't consider the CnP bit for the vttbr match */ 588 vttbr &= ~VTTBR_CNP_BIT; 589 590 /* 591 * Two possibilities when looking up a S2 MMU context: 592 * 593 * - either S2 is enabled in the guest, and we need a context that is 594 * S2-enabled and matches the full VTTBR (VMID+BADDR) and VTCR, 595 * which makes it safe from a TLB conflict perspective (a broken 596 * guest won't be able to generate them), 597 * 598 * - or S2 is disabled, and we need a context that is S2-disabled 599 * and matches the VMID only, as all TLBs are tagged by VMID even 600 * if S2 translation is disabled. 601 */ 602 for (int i = 0; i < kvm->arch.nested_mmus_size; i++) { 603 struct kvm_s2_mmu *mmu = &kvm->arch.nested_mmus[i]; 604 605 if (!kvm_s2_mmu_valid(mmu)) 606 continue; 607 608 if (nested_stage2_enabled && 609 mmu->nested_stage2_enabled && 610 vttbr == mmu->tlb_vttbr && 611 vtcr == mmu->tlb_vtcr) 612 return mmu; 613 614 if (!nested_stage2_enabled && 615 !mmu->nested_stage2_enabled && 616 get_vmid(vttbr) == get_vmid(mmu->tlb_vttbr)) 617 return mmu; 618 } 619 return NULL; 620 } 621 622 static struct kvm_s2_mmu *get_s2_mmu_nested(struct kvm_vcpu *vcpu) 623 { 624 struct kvm *kvm = vcpu->kvm; 625 struct kvm_s2_mmu *s2_mmu; 626 int i; 627 628 lockdep_assert_held_write(&vcpu->kvm->mmu_lock); 629 630 s2_mmu = lookup_s2_mmu(vcpu); 631 if (s2_mmu) 632 goto out; 633 634 /* 635 * Make sure we don't always search from the same point, or we 636 * will always reuse a potentially active context, leaving 637 * free contexts unused. 638 */ 639 for (i = kvm->arch.nested_mmus_next; 640 i < (kvm->arch.nested_mmus_size + kvm->arch.nested_mmus_next); 641 i++) { 642 s2_mmu = &kvm->arch.nested_mmus[i % kvm->arch.nested_mmus_size]; 643 644 if (atomic_read(&s2_mmu->refcnt) == 0) 645 break; 646 } 647 BUG_ON(atomic_read(&s2_mmu->refcnt)); /* We have struct MMUs to spare */ 648 649 /* Set the scene for the next search */ 650 kvm->arch.nested_mmus_next = (i + 1) % kvm->arch.nested_mmus_size; 651 652 /* Clear the old state */ 653 if (kvm_s2_mmu_valid(s2_mmu)) 654 kvm_stage2_unmap_range(s2_mmu, 0, kvm_phys_size(s2_mmu)); 655 656 /* 657 * The virtual VMID (modulo CnP) will be used as a key when matching 658 * an existing kvm_s2_mmu. 659 * 660 * We cache VTCR at allocation time, once and for all. It'd be great 661 * if the guest didn't screw that one up, as this is not very 662 * forgiving... 663 */ 664 s2_mmu->tlb_vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2) & ~VTTBR_CNP_BIT; 665 s2_mmu->tlb_vtcr = vcpu_read_sys_reg(vcpu, VTCR_EL2); 666 s2_mmu->nested_stage2_enabled = vcpu_read_sys_reg(vcpu, HCR_EL2) & HCR_VM; 667 668 out: 669 atomic_inc(&s2_mmu->refcnt); 670 return s2_mmu; 671 } 672 673 void kvm_init_nested_s2_mmu(struct kvm_s2_mmu *mmu) 674 { 675 /* CnP being set denotes an invalid entry */ 676 mmu->tlb_vttbr = VTTBR_CNP_BIT; 677 mmu->nested_stage2_enabled = false; 678 atomic_set(&mmu->refcnt, 0); 679 } 680 681 void kvm_vcpu_load_hw_mmu(struct kvm_vcpu *vcpu) 682 { 683 if (is_hyp_ctxt(vcpu)) { 684 vcpu->arch.hw_mmu = &vcpu->kvm->arch.mmu; 685 } else { 686 write_lock(&vcpu->kvm->mmu_lock); 687 vcpu->arch.hw_mmu = get_s2_mmu_nested(vcpu); 688 write_unlock(&vcpu->kvm->mmu_lock); 689 } 690 } 691 692 void kvm_vcpu_put_hw_mmu(struct kvm_vcpu *vcpu) 693 { 694 if (kvm_is_nested_s2_mmu(vcpu->kvm, vcpu->arch.hw_mmu)) { 695 atomic_dec(&vcpu->arch.hw_mmu->refcnt); 696 vcpu->arch.hw_mmu = NULL; 697 } 698 } 699 700 /* 701 * Returns non-zero if permission fault is handled by injecting it to the next 702 * level hypervisor. 703 */ 704 int kvm_s2_handle_perm_fault(struct kvm_vcpu *vcpu, struct kvm_s2_trans *trans) 705 { 706 bool forward_fault = false; 707 708 trans->esr = 0; 709 710 if (!kvm_vcpu_trap_is_permission_fault(vcpu)) 711 return 0; 712 713 if (kvm_vcpu_trap_is_iabt(vcpu)) { 714 forward_fault = !kvm_s2_trans_executable(trans); 715 } else { 716 bool write_fault = kvm_is_write_fault(vcpu); 717 718 forward_fault = ((write_fault && !trans->writable) || 719 (!write_fault && !trans->readable)); 720 } 721 722 if (forward_fault) 723 trans->esr = esr_s2_fault(vcpu, trans->level, ESR_ELx_FSC_PERM); 724 725 return forward_fault; 726 } 727 728 int kvm_inject_s2_fault(struct kvm_vcpu *vcpu, u64 esr_el2) 729 { 730 vcpu_write_sys_reg(vcpu, vcpu->arch.fault.far_el2, FAR_EL2); 731 vcpu_write_sys_reg(vcpu, vcpu->arch.fault.hpfar_el2, HPFAR_EL2); 732 733 return kvm_inject_nested_sync(vcpu, esr_el2); 734 } 735 736 void kvm_nested_s2_wp(struct kvm *kvm) 737 { 738 int i; 739 740 lockdep_assert_held_write(&kvm->mmu_lock); 741 742 for (i = 0; i < kvm->arch.nested_mmus_size; i++) { 743 struct kvm_s2_mmu *mmu = &kvm->arch.nested_mmus[i]; 744 745 if (kvm_s2_mmu_valid(mmu)) 746 kvm_stage2_wp_range(mmu, 0, kvm_phys_size(mmu)); 747 } 748 } 749 750 void kvm_nested_s2_unmap(struct kvm *kvm) 751 { 752 int i; 753 754 lockdep_assert_held_write(&kvm->mmu_lock); 755 756 for (i = 0; i < kvm->arch.nested_mmus_size; i++) { 757 struct kvm_s2_mmu *mmu = &kvm->arch.nested_mmus[i]; 758 759 if (kvm_s2_mmu_valid(mmu)) 760 kvm_stage2_unmap_range(mmu, 0, kvm_phys_size(mmu)); 761 } 762 } 763 764 void kvm_nested_s2_flush(struct kvm *kvm) 765 { 766 int i; 767 768 lockdep_assert_held_write(&kvm->mmu_lock); 769 770 for (i = 0; i < kvm->arch.nested_mmus_size; i++) { 771 struct kvm_s2_mmu *mmu = &kvm->arch.nested_mmus[i]; 772 773 if (kvm_s2_mmu_valid(mmu)) 774 kvm_stage2_flush_range(mmu, 0, kvm_phys_size(mmu)); 775 } 776 } 777 778 void kvm_arch_flush_shadow_all(struct kvm *kvm) 779 { 780 int i; 781 782 for (i = 0; i < kvm->arch.nested_mmus_size; i++) { 783 struct kvm_s2_mmu *mmu = &kvm->arch.nested_mmus[i]; 784 785 if (!WARN_ON(atomic_read(&mmu->refcnt))) 786 kvm_free_stage2_pgd(mmu); 787 } 788 kvfree(kvm->arch.nested_mmus); 789 kvm->arch.nested_mmus = NULL; 790 kvm->arch.nested_mmus_size = 0; 791 kvm_uninit_stage2_mmu(kvm); 792 } 793 794 /* 795 * Our emulated CPU doesn't support all the possible features. For the 796 * sake of simplicity (and probably mental sanity), wipe out a number 797 * of feature bits we don't intend to support for the time being. 798 * This list should get updated as new features get added to the NV 799 * support, and new extension to the architecture. 800 */ 801 static void limit_nv_id_regs(struct kvm *kvm) 802 { 803 u64 val, tmp; 804 805 /* Support everything but TME */ 806 val = kvm_read_vm_id_reg(kvm, SYS_ID_AA64ISAR0_EL1); 807 val &= ~NV_FTR(ISAR0, TME); 808 kvm_set_vm_id_reg(kvm, SYS_ID_AA64ISAR0_EL1, val); 809 810 /* Support everything but Spec Invalidation and LS64 */ 811 val = kvm_read_vm_id_reg(kvm, SYS_ID_AA64ISAR1_EL1); 812 val &= ~(NV_FTR(ISAR1, LS64) | 813 NV_FTR(ISAR1, SPECRES)); 814 kvm_set_vm_id_reg(kvm, SYS_ID_AA64ISAR1_EL1, val); 815 816 /* No AMU, MPAM, S-EL2, or RAS */ 817 val = kvm_read_vm_id_reg(kvm, SYS_ID_AA64PFR0_EL1); 818 val &= ~(GENMASK_ULL(55, 52) | 819 NV_FTR(PFR0, AMU) | 820 NV_FTR(PFR0, MPAM) | 821 NV_FTR(PFR0, SEL2) | 822 NV_FTR(PFR0, RAS) | 823 NV_FTR(PFR0, EL3) | 824 NV_FTR(PFR0, EL2) | 825 NV_FTR(PFR0, EL1)); 826 /* 64bit EL1/EL2/EL3 only */ 827 val |= FIELD_PREP(NV_FTR(PFR0, EL1), 0b0001); 828 val |= FIELD_PREP(NV_FTR(PFR0, EL2), 0b0001); 829 val |= FIELD_PREP(NV_FTR(PFR0, EL3), 0b0001); 830 kvm_set_vm_id_reg(kvm, SYS_ID_AA64PFR0_EL1, val); 831 832 /* Only support BTI, SSBS, CSV2_frac */ 833 val = kvm_read_vm_id_reg(kvm, SYS_ID_AA64PFR1_EL1); 834 val &= (NV_FTR(PFR1, BT) | 835 NV_FTR(PFR1, SSBS) | 836 NV_FTR(PFR1, CSV2_frac)); 837 kvm_set_vm_id_reg(kvm, SYS_ID_AA64PFR1_EL1, val); 838 839 /* Hide ECV, ExS, Secure Memory */ 840 val = kvm_read_vm_id_reg(kvm, SYS_ID_AA64MMFR0_EL1); 841 val &= ~(NV_FTR(MMFR0, ECV) | 842 NV_FTR(MMFR0, EXS) | 843 NV_FTR(MMFR0, TGRAN4_2) | 844 NV_FTR(MMFR0, TGRAN16_2) | 845 NV_FTR(MMFR0, TGRAN64_2) | 846 NV_FTR(MMFR0, SNSMEM)); 847 848 /* Disallow unsupported S2 page sizes */ 849 switch (PAGE_SIZE) { 850 case SZ_64K: 851 val |= FIELD_PREP(NV_FTR(MMFR0, TGRAN16_2), 0b0001); 852 fallthrough; 853 case SZ_16K: 854 val |= FIELD_PREP(NV_FTR(MMFR0, TGRAN4_2), 0b0001); 855 fallthrough; 856 case SZ_4K: 857 /* Support everything */ 858 break; 859 } 860 /* 861 * Since we can't support a guest S2 page size smaller than 862 * the host's own page size (due to KVM only populating its 863 * own S2 using the kernel's page size), advertise the 864 * limitation using FEAT_GTG. 865 */ 866 switch (PAGE_SIZE) { 867 case SZ_4K: 868 val |= FIELD_PREP(NV_FTR(MMFR0, TGRAN4_2), 0b0010); 869 fallthrough; 870 case SZ_16K: 871 val |= FIELD_PREP(NV_FTR(MMFR0, TGRAN16_2), 0b0010); 872 fallthrough; 873 case SZ_64K: 874 val |= FIELD_PREP(NV_FTR(MMFR0, TGRAN64_2), 0b0010); 875 break; 876 } 877 /* Cap PARange to 48bits */ 878 tmp = FIELD_GET(NV_FTR(MMFR0, PARANGE), val); 879 if (tmp > 0b0101) { 880 val &= ~NV_FTR(MMFR0, PARANGE); 881 val |= FIELD_PREP(NV_FTR(MMFR0, PARANGE), 0b0101); 882 } 883 kvm_set_vm_id_reg(kvm, SYS_ID_AA64MMFR0_EL1, val); 884 885 val = kvm_read_vm_id_reg(kvm, SYS_ID_AA64MMFR1_EL1); 886 val &= (NV_FTR(MMFR1, HCX) | 887 NV_FTR(MMFR1, PAN) | 888 NV_FTR(MMFR1, LO) | 889 NV_FTR(MMFR1, HPDS) | 890 NV_FTR(MMFR1, VH) | 891 NV_FTR(MMFR1, VMIDBits)); 892 kvm_set_vm_id_reg(kvm, SYS_ID_AA64MMFR1_EL1, val); 893 894 val = kvm_read_vm_id_reg(kvm, SYS_ID_AA64MMFR2_EL1); 895 val &= ~(NV_FTR(MMFR2, BBM) | 896 NV_FTR(MMFR2, TTL) | 897 GENMASK_ULL(47, 44) | 898 NV_FTR(MMFR2, ST) | 899 NV_FTR(MMFR2, CCIDX) | 900 NV_FTR(MMFR2, VARange)); 901 902 /* Force TTL support */ 903 val |= FIELD_PREP(NV_FTR(MMFR2, TTL), 0b0001); 904 kvm_set_vm_id_reg(kvm, SYS_ID_AA64MMFR2_EL1, val); 905 906 val = 0; 907 if (!cpus_have_final_cap(ARM64_HAS_HCR_NV1)) 908 val |= FIELD_PREP(NV_FTR(MMFR4, E2H0), 909 ID_AA64MMFR4_EL1_E2H0_NI_NV1); 910 kvm_set_vm_id_reg(kvm, SYS_ID_AA64MMFR4_EL1, val); 911 912 /* Only limited support for PMU, Debug, BPs and WPs */ 913 val = kvm_read_vm_id_reg(kvm, SYS_ID_AA64DFR0_EL1); 914 val &= (NV_FTR(DFR0, PMUVer) | 915 NV_FTR(DFR0, WRPs) | 916 NV_FTR(DFR0, BRPs) | 917 NV_FTR(DFR0, DebugVer)); 918 919 /* Cap Debug to ARMv8.1 */ 920 tmp = FIELD_GET(NV_FTR(DFR0, DebugVer), val); 921 if (tmp > 0b0111) { 922 val &= ~NV_FTR(DFR0, DebugVer); 923 val |= FIELD_PREP(NV_FTR(DFR0, DebugVer), 0b0111); 924 } 925 kvm_set_vm_id_reg(kvm, SYS_ID_AA64DFR0_EL1, val); 926 } 927 928 u64 kvm_vcpu_sanitise_vncr_reg(const struct kvm_vcpu *vcpu, enum vcpu_sysreg sr) 929 { 930 u64 v = ctxt_sys_reg(&vcpu->arch.ctxt, sr); 931 struct kvm_sysreg_masks *masks; 932 933 masks = vcpu->kvm->arch.sysreg_masks; 934 935 if (masks) { 936 sr -= __VNCR_START__; 937 938 v &= ~masks->mask[sr].res0; 939 v |= masks->mask[sr].res1; 940 } 941 942 return v; 943 } 944 945 static void set_sysreg_masks(struct kvm *kvm, int sr, u64 res0, u64 res1) 946 { 947 int i = sr - __VNCR_START__; 948 949 kvm->arch.sysreg_masks->mask[i].res0 = res0; 950 kvm->arch.sysreg_masks->mask[i].res1 = res1; 951 } 952 953 int kvm_init_nv_sysregs(struct kvm *kvm) 954 { 955 u64 res0, res1; 956 int ret = 0; 957 958 mutex_lock(&kvm->arch.config_lock); 959 960 if (kvm->arch.sysreg_masks) 961 goto out; 962 963 kvm->arch.sysreg_masks = kzalloc(sizeof(*(kvm->arch.sysreg_masks)), 964 GFP_KERNEL_ACCOUNT); 965 if (!kvm->arch.sysreg_masks) { 966 ret = -ENOMEM; 967 goto out; 968 } 969 970 limit_nv_id_regs(kvm); 971 972 /* VTTBR_EL2 */ 973 res0 = res1 = 0; 974 if (!kvm_has_feat_enum(kvm, ID_AA64MMFR1_EL1, VMIDBits, 16)) 975 res0 |= GENMASK(63, 56); 976 if (!kvm_has_feat(kvm, ID_AA64MMFR2_EL1, CnP, IMP)) 977 res0 |= VTTBR_CNP_BIT; 978 set_sysreg_masks(kvm, VTTBR_EL2, res0, res1); 979 980 /* VTCR_EL2 */ 981 res0 = GENMASK(63, 32) | GENMASK(30, 20); 982 res1 = BIT(31); 983 set_sysreg_masks(kvm, VTCR_EL2, res0, res1); 984 985 /* VMPIDR_EL2 */ 986 res0 = GENMASK(63, 40) | GENMASK(30, 24); 987 res1 = BIT(31); 988 set_sysreg_masks(kvm, VMPIDR_EL2, res0, res1); 989 990 /* HCR_EL2 */ 991 res0 = BIT(48); 992 res1 = HCR_RW; 993 if (!kvm_has_feat(kvm, ID_AA64MMFR1_EL1, TWED, IMP)) 994 res0 |= GENMASK(63, 59); 995 if (!kvm_has_feat(kvm, ID_AA64PFR1_EL1, MTE, MTE2)) 996 res0 |= (HCR_TID5 | HCR_DCT | HCR_ATA); 997 if (!kvm_has_feat(kvm, ID_AA64MMFR2_EL1, EVT, TTLBxS)) 998 res0 |= (HCR_TTLBIS | HCR_TTLBOS); 999 if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, CSV2, CSV2_2) && 1000 !kvm_has_feat(kvm, ID_AA64PFR1_EL1, CSV2_frac, CSV2_1p2)) 1001 res0 |= HCR_ENSCXT; 1002 if (!kvm_has_feat(kvm, ID_AA64MMFR2_EL1, EVT, IMP)) 1003 res0 |= (HCR_TOCU | HCR_TICAB | HCR_TID4); 1004 if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, AMU, V1P1)) 1005 res0 |= HCR_AMVOFFEN; 1006 if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, RAS, V1P1)) 1007 res0 |= HCR_FIEN; 1008 if (!kvm_has_feat(kvm, ID_AA64MMFR2_EL1, FWB, IMP)) 1009 res0 |= HCR_FWB; 1010 if (!kvm_has_feat(kvm, ID_AA64MMFR2_EL1, NV, NV2)) 1011 res0 |= HCR_NV2; 1012 if (!kvm_has_feat(kvm, ID_AA64MMFR2_EL1, NV, IMP)) 1013 res0 |= (HCR_AT | HCR_NV1 | HCR_NV); 1014 if (!(__vcpu_has_feature(&kvm->arch, KVM_ARM_VCPU_PTRAUTH_ADDRESS) && 1015 __vcpu_has_feature(&kvm->arch, KVM_ARM_VCPU_PTRAUTH_GENERIC))) 1016 res0 |= (HCR_API | HCR_APK); 1017 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TME, IMP)) 1018 res0 |= BIT(39); 1019 if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, RAS, IMP)) 1020 res0 |= (HCR_TEA | HCR_TERR); 1021 if (!kvm_has_feat(kvm, ID_AA64MMFR1_EL1, LO, IMP)) 1022 res0 |= HCR_TLOR; 1023 if (!kvm_has_feat(kvm, ID_AA64MMFR4_EL1, E2H0, IMP)) 1024 res1 |= HCR_E2H; 1025 set_sysreg_masks(kvm, HCR_EL2, res0, res1); 1026 1027 /* HCRX_EL2 */ 1028 res0 = HCRX_EL2_RES0; 1029 res1 = HCRX_EL2_RES1; 1030 if (!kvm_has_feat(kvm, ID_AA64ISAR3_EL1, PACM, TRIVIAL_IMP)) 1031 res0 |= HCRX_EL2_PACMEn; 1032 if (!kvm_has_feat(kvm, ID_AA64PFR2_EL1, FPMR, IMP)) 1033 res0 |= HCRX_EL2_EnFPM; 1034 if (!kvm_has_feat(kvm, ID_AA64PFR1_EL1, GCS, IMP)) 1035 res0 |= HCRX_EL2_GCSEn; 1036 if (!kvm_has_feat(kvm, ID_AA64ISAR2_EL1, SYSREG_128, IMP)) 1037 res0 |= HCRX_EL2_EnIDCP128; 1038 if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, ADERR, DEV_ASYNC)) 1039 res0 |= (HCRX_EL2_EnSDERR | HCRX_EL2_EnSNERR); 1040 if (!kvm_has_feat(kvm, ID_AA64PFR1_EL1, DF2, IMP)) 1041 res0 |= HCRX_EL2_TMEA; 1042 if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, D128, IMP)) 1043 res0 |= HCRX_EL2_D128En; 1044 if (!kvm_has_feat(kvm, ID_AA64PFR1_EL1, THE, IMP)) 1045 res0 |= HCRX_EL2_PTTWI; 1046 if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, SCTLRX, IMP)) 1047 res0 |= HCRX_EL2_SCTLR2En; 1048 if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, TCRX, IMP)) 1049 res0 |= HCRX_EL2_TCR2En; 1050 if (!kvm_has_feat(kvm, ID_AA64ISAR2_EL1, MOPS, IMP)) 1051 res0 |= (HCRX_EL2_MSCEn | HCRX_EL2_MCE2); 1052 if (!kvm_has_feat(kvm, ID_AA64MMFR1_EL1, CMOW, IMP)) 1053 res0 |= HCRX_EL2_CMOW; 1054 if (!kvm_has_feat(kvm, ID_AA64PFR1_EL1, NMI, IMP)) 1055 res0 |= (HCRX_EL2_VFNMI | HCRX_EL2_VINMI | HCRX_EL2_TALLINT); 1056 if (!kvm_has_feat(kvm, ID_AA64PFR1_EL1, SME, IMP) || 1057 !(read_sysreg_s(SYS_SMIDR_EL1) & SMIDR_EL1_SMPS)) 1058 res0 |= HCRX_EL2_SMPME; 1059 if (!kvm_has_feat(kvm, ID_AA64ISAR1_EL1, XS, IMP)) 1060 res0 |= (HCRX_EL2_FGTnXS | HCRX_EL2_FnXS); 1061 if (!kvm_has_feat(kvm, ID_AA64ISAR1_EL1, LS64, LS64_V)) 1062 res0 |= HCRX_EL2_EnASR; 1063 if (!kvm_has_feat(kvm, ID_AA64ISAR1_EL1, LS64, LS64)) 1064 res0 |= HCRX_EL2_EnALS; 1065 if (!kvm_has_feat(kvm, ID_AA64ISAR1_EL1, LS64, LS64_ACCDATA)) 1066 res0 |= HCRX_EL2_EnAS0; 1067 set_sysreg_masks(kvm, HCRX_EL2, res0, res1); 1068 1069 /* HFG[RW]TR_EL2 */ 1070 res0 = res1 = 0; 1071 if (!(__vcpu_has_feature(&kvm->arch, KVM_ARM_VCPU_PTRAUTH_ADDRESS) && 1072 __vcpu_has_feature(&kvm->arch, KVM_ARM_VCPU_PTRAUTH_GENERIC))) 1073 res0 |= (HFGxTR_EL2_APDAKey | HFGxTR_EL2_APDBKey | 1074 HFGxTR_EL2_APGAKey | HFGxTR_EL2_APIAKey | 1075 HFGxTR_EL2_APIBKey); 1076 if (!kvm_has_feat(kvm, ID_AA64MMFR1_EL1, LO, IMP)) 1077 res0 |= (HFGxTR_EL2_LORC_EL1 | HFGxTR_EL2_LOREA_EL1 | 1078 HFGxTR_EL2_LORID_EL1 | HFGxTR_EL2_LORN_EL1 | 1079 HFGxTR_EL2_LORSA_EL1); 1080 if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, CSV2, CSV2_2) && 1081 !kvm_has_feat(kvm, ID_AA64PFR1_EL1, CSV2_frac, CSV2_1p2)) 1082 res0 |= (HFGxTR_EL2_SCXTNUM_EL1 | HFGxTR_EL2_SCXTNUM_EL0); 1083 if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, GIC, IMP)) 1084 res0 |= HFGxTR_EL2_ICC_IGRPENn_EL1; 1085 if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, RAS, IMP)) 1086 res0 |= (HFGxTR_EL2_ERRIDR_EL1 | HFGxTR_EL2_ERRSELR_EL1 | 1087 HFGxTR_EL2_ERXFR_EL1 | HFGxTR_EL2_ERXCTLR_EL1 | 1088 HFGxTR_EL2_ERXSTATUS_EL1 | HFGxTR_EL2_ERXMISCn_EL1 | 1089 HFGxTR_EL2_ERXPFGF_EL1 | HFGxTR_EL2_ERXPFGCTL_EL1 | 1090 HFGxTR_EL2_ERXPFGCDN_EL1 | HFGxTR_EL2_ERXADDR_EL1); 1091 if (!kvm_has_feat(kvm, ID_AA64ISAR1_EL1, LS64, LS64_ACCDATA)) 1092 res0 |= HFGxTR_EL2_nACCDATA_EL1; 1093 if (!kvm_has_feat(kvm, ID_AA64PFR1_EL1, GCS, IMP)) 1094 res0 |= (HFGxTR_EL2_nGCS_EL0 | HFGxTR_EL2_nGCS_EL1); 1095 if (!kvm_has_feat(kvm, ID_AA64PFR1_EL1, SME, IMP)) 1096 res0 |= (HFGxTR_EL2_nSMPRI_EL1 | HFGxTR_EL2_nTPIDR2_EL0); 1097 if (!kvm_has_feat(kvm, ID_AA64PFR1_EL1, THE, IMP)) 1098 res0 |= HFGxTR_EL2_nRCWMASK_EL1; 1099 if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, S1PIE, IMP)) 1100 res0 |= (HFGxTR_EL2_nPIRE0_EL1 | HFGxTR_EL2_nPIR_EL1); 1101 if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, S1POE, IMP)) 1102 res0 |= (HFGxTR_EL2_nPOR_EL0 | HFGxTR_EL2_nPOR_EL1); 1103 if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, S2POE, IMP)) 1104 res0 |= HFGxTR_EL2_nS2POR_EL1; 1105 if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, AIE, IMP)) 1106 res0 |= (HFGxTR_EL2_nMAIR2_EL1 | HFGxTR_EL2_nAMAIR2_EL1); 1107 set_sysreg_masks(kvm, HFGRTR_EL2, res0 | __HFGRTR_EL2_RES0, res1); 1108 set_sysreg_masks(kvm, HFGWTR_EL2, res0 | __HFGWTR_EL2_RES0, res1); 1109 1110 /* HDFG[RW]TR_EL2 */ 1111 res0 = res1 = 0; 1112 if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, DoubleLock, IMP)) 1113 res0 |= HDFGRTR_EL2_OSDLR_EL1; 1114 if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMUVer, IMP)) 1115 res0 |= (HDFGRTR_EL2_PMEVCNTRn_EL0 | HDFGRTR_EL2_PMEVTYPERn_EL0 | 1116 HDFGRTR_EL2_PMCCFILTR_EL0 | HDFGRTR_EL2_PMCCNTR_EL0 | 1117 HDFGRTR_EL2_PMCNTEN | HDFGRTR_EL2_PMINTEN | 1118 HDFGRTR_EL2_PMOVS | HDFGRTR_EL2_PMSELR_EL0 | 1119 HDFGRTR_EL2_PMMIR_EL1 | HDFGRTR_EL2_PMUSERENR_EL0 | 1120 HDFGRTR_EL2_PMCEIDn_EL0); 1121 if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMSVer, IMP)) 1122 res0 |= (HDFGRTR_EL2_PMBLIMITR_EL1 | HDFGRTR_EL2_PMBPTR_EL1 | 1123 HDFGRTR_EL2_PMBSR_EL1 | HDFGRTR_EL2_PMSCR_EL1 | 1124 HDFGRTR_EL2_PMSEVFR_EL1 | HDFGRTR_EL2_PMSFCR_EL1 | 1125 HDFGRTR_EL2_PMSICR_EL1 | HDFGRTR_EL2_PMSIDR_EL1 | 1126 HDFGRTR_EL2_PMSIRR_EL1 | HDFGRTR_EL2_PMSLATFR_EL1 | 1127 HDFGRTR_EL2_PMBIDR_EL1); 1128 if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, TraceVer, IMP)) 1129 res0 |= (HDFGRTR_EL2_TRC | HDFGRTR_EL2_TRCAUTHSTATUS | 1130 HDFGRTR_EL2_TRCAUXCTLR | HDFGRTR_EL2_TRCCLAIM | 1131 HDFGRTR_EL2_TRCCNTVRn | HDFGRTR_EL2_TRCID | 1132 HDFGRTR_EL2_TRCIMSPECn | HDFGRTR_EL2_TRCOSLSR | 1133 HDFGRTR_EL2_TRCPRGCTLR | HDFGRTR_EL2_TRCSEQSTR | 1134 HDFGRTR_EL2_TRCSSCSRn | HDFGRTR_EL2_TRCSTATR | 1135 HDFGRTR_EL2_TRCVICTLR); 1136 if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, TraceBuffer, IMP)) 1137 res0 |= (HDFGRTR_EL2_TRBBASER_EL1 | HDFGRTR_EL2_TRBIDR_EL1 | 1138 HDFGRTR_EL2_TRBLIMITR_EL1 | HDFGRTR_EL2_TRBMAR_EL1 | 1139 HDFGRTR_EL2_TRBPTR_EL1 | HDFGRTR_EL2_TRBSR_EL1 | 1140 HDFGRTR_EL2_TRBTRG_EL1); 1141 if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, BRBE, IMP)) 1142 res0 |= (HDFGRTR_EL2_nBRBIDR | HDFGRTR_EL2_nBRBCTL | 1143 HDFGRTR_EL2_nBRBDATA); 1144 if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMSVer, V1P2)) 1145 res0 |= HDFGRTR_EL2_nPMSNEVFR_EL1; 1146 set_sysreg_masks(kvm, HDFGRTR_EL2, res0 | HDFGRTR_EL2_RES0, res1); 1147 1148 /* Reuse the bits from the read-side and add the write-specific stuff */ 1149 if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMUVer, IMP)) 1150 res0 |= (HDFGWTR_EL2_PMCR_EL0 | HDFGWTR_EL2_PMSWINC_EL0); 1151 if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, TraceVer, IMP)) 1152 res0 |= HDFGWTR_EL2_TRCOSLAR; 1153 if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, TraceFilt, IMP)) 1154 res0 |= HDFGWTR_EL2_TRFCR_EL1; 1155 set_sysreg_masks(kvm, HFGWTR_EL2, res0 | HDFGWTR_EL2_RES0, res1); 1156 1157 /* HFGITR_EL2 */ 1158 res0 = HFGITR_EL2_RES0; 1159 res1 = HFGITR_EL2_RES1; 1160 if (!kvm_has_feat(kvm, ID_AA64ISAR1_EL1, DPB, DPB2)) 1161 res0 |= HFGITR_EL2_DCCVADP; 1162 if (!kvm_has_feat(kvm, ID_AA64MMFR1_EL1, PAN, PAN2)) 1163 res0 |= (HFGITR_EL2_ATS1E1RP | HFGITR_EL2_ATS1E1WP); 1164 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 1165 res0 |= (HFGITR_EL2_TLBIRVAALE1OS | HFGITR_EL2_TLBIRVALE1OS | 1166 HFGITR_EL2_TLBIRVAAE1OS | HFGITR_EL2_TLBIRVAE1OS | 1167 HFGITR_EL2_TLBIVAALE1OS | HFGITR_EL2_TLBIVALE1OS | 1168 HFGITR_EL2_TLBIVAAE1OS | HFGITR_EL2_TLBIASIDE1OS | 1169 HFGITR_EL2_TLBIVAE1OS | HFGITR_EL2_TLBIVMALLE1OS); 1170 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE)) 1171 res0 |= (HFGITR_EL2_TLBIRVAALE1 | HFGITR_EL2_TLBIRVALE1 | 1172 HFGITR_EL2_TLBIRVAAE1 | HFGITR_EL2_TLBIRVAE1 | 1173 HFGITR_EL2_TLBIRVAALE1IS | HFGITR_EL2_TLBIRVALE1IS | 1174 HFGITR_EL2_TLBIRVAAE1IS | HFGITR_EL2_TLBIRVAE1IS | 1175 HFGITR_EL2_TLBIRVAALE1OS | HFGITR_EL2_TLBIRVALE1OS | 1176 HFGITR_EL2_TLBIRVAAE1OS | HFGITR_EL2_TLBIRVAE1OS); 1177 if (!kvm_has_feat(kvm, ID_AA64ISAR1_EL1, SPECRES, IMP)) 1178 res0 |= (HFGITR_EL2_CFPRCTX | HFGITR_EL2_DVPRCTX | 1179 HFGITR_EL2_CPPRCTX); 1180 if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, BRBE, IMP)) 1181 res0 |= (HFGITR_EL2_nBRBINJ | HFGITR_EL2_nBRBIALL); 1182 if (!kvm_has_feat(kvm, ID_AA64PFR1_EL1, GCS, IMP)) 1183 res0 |= (HFGITR_EL2_nGCSPUSHM_EL1 | HFGITR_EL2_nGCSSTR_EL1 | 1184 HFGITR_EL2_nGCSEPP); 1185 if (!kvm_has_feat(kvm, ID_AA64ISAR1_EL1, SPECRES, COSP_RCTX)) 1186 res0 |= HFGITR_EL2_COSPRCTX; 1187 if (!kvm_has_feat(kvm, ID_AA64ISAR2_EL1, ATS1A, IMP)) 1188 res0 |= HFGITR_EL2_ATS1E1A; 1189 set_sysreg_masks(kvm, HFGITR_EL2, res0, res1); 1190 1191 /* HAFGRTR_EL2 - not a lot to see here */ 1192 res0 = HAFGRTR_EL2_RES0; 1193 res1 = HAFGRTR_EL2_RES1; 1194 if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, AMU, V1P1)) 1195 res0 |= ~(res0 | res1); 1196 set_sysreg_masks(kvm, HAFGRTR_EL2, res0, res1); 1197 out: 1198 mutex_unlock(&kvm->arch.config_lock); 1199 1200 return ret; 1201 } 1202