1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2017 - Columbia University and Linaro Ltd. 4 * Author: Jintack Lim <jintack.lim@linaro.org> 5 */ 6 7 #include <linux/kvm.h> 8 #include <linux/kvm_host.h> 9 10 #include <asm/kvm_arm.h> 11 #include <asm/kvm_emulate.h> 12 #include <asm/kvm_mmu.h> 13 #include <asm/kvm_nested.h> 14 #include <asm/sysreg.h> 15 16 #include "sys_regs.h" 17 18 /* Protection against the sysreg repainting madness... */ 19 #define NV_FTR(r, f) ID_AA64##r##_EL1_##f 20 21 /* 22 * Ratio of live shadow S2 MMU per vcpu. This is a trade-off between 23 * memory usage and potential number of different sets of S2 PTs in 24 * the guests. Running out of S2 MMUs only affects performance (we 25 * will invalidate them more often). 26 */ 27 #define S2_MMU_PER_VCPU 2 28 29 void kvm_init_nested(struct kvm *kvm) 30 { 31 kvm->arch.nested_mmus = NULL; 32 kvm->arch.nested_mmus_size = 0; 33 } 34 35 static int init_nested_s2_mmu(struct kvm *kvm, struct kvm_s2_mmu *mmu) 36 { 37 /* 38 * We only initialise the IPA range on the canonical MMU, which 39 * defines the contract between KVM and userspace on where the 40 * "hardware" is in the IPA space. This affects the validity of MMIO 41 * exits forwarded to userspace, for example. 42 * 43 * For nested S2s, we use the PARange as exposed to the guest, as it 44 * is allowed to use it at will to expose whatever memory map it 45 * wants to its own guests as it would be on real HW. 46 */ 47 return kvm_init_stage2_mmu(kvm, mmu, kvm_get_pa_bits(kvm)); 48 } 49 50 int kvm_vcpu_init_nested(struct kvm_vcpu *vcpu) 51 { 52 struct kvm *kvm = vcpu->kvm; 53 struct kvm_s2_mmu *tmp; 54 int num_mmus, ret = 0; 55 56 /* 57 * Let's treat memory allocation failures as benign: If we fail to 58 * allocate anything, return an error and keep the allocated array 59 * alive. Userspace may try to recover by intializing the vcpu 60 * again, and there is no reason to affect the whole VM for this. 61 */ 62 num_mmus = atomic_read(&kvm->online_vcpus) * S2_MMU_PER_VCPU; 63 tmp = kvrealloc(kvm->arch.nested_mmus, 64 size_mul(sizeof(*kvm->arch.nested_mmus), kvm->arch.nested_mmus_size), 65 size_mul(sizeof(*kvm->arch.nested_mmus), num_mmus), 66 GFP_KERNEL_ACCOUNT | __GFP_ZERO); 67 if (!tmp) 68 return -ENOMEM; 69 70 /* 71 * If we went through a realocation, adjust the MMU back-pointers in 72 * the previously initialised kvm_pgtable structures. 73 */ 74 if (kvm->arch.nested_mmus != tmp) 75 for (int i = 0; i < kvm->arch.nested_mmus_size; i++) 76 tmp[i].pgt->mmu = &tmp[i]; 77 78 for (int i = kvm->arch.nested_mmus_size; !ret && i < num_mmus; i++) 79 ret = init_nested_s2_mmu(kvm, &tmp[i]); 80 81 if (ret) { 82 for (int i = kvm->arch.nested_mmus_size; i < num_mmus; i++) 83 kvm_free_stage2_pgd(&tmp[i]); 84 85 return ret; 86 } 87 88 kvm->arch.nested_mmus_size = num_mmus; 89 kvm->arch.nested_mmus = tmp; 90 91 return 0; 92 } 93 94 struct s2_walk_info { 95 int (*read_desc)(phys_addr_t pa, u64 *desc, void *data); 96 void *data; 97 u64 baddr; 98 unsigned int max_oa_bits; 99 unsigned int pgshift; 100 unsigned int sl; 101 unsigned int t0sz; 102 bool be; 103 }; 104 105 static unsigned int ps_to_output_size(unsigned int ps) 106 { 107 switch (ps) { 108 case 0: return 32; 109 case 1: return 36; 110 case 2: return 40; 111 case 3: return 42; 112 case 4: return 44; 113 case 5: 114 default: 115 return 48; 116 } 117 } 118 119 static u32 compute_fsc(int level, u32 fsc) 120 { 121 return fsc | (level & 0x3); 122 } 123 124 static int esr_s2_fault(struct kvm_vcpu *vcpu, int level, u32 fsc) 125 { 126 u32 esr; 127 128 esr = kvm_vcpu_get_esr(vcpu) & ~ESR_ELx_FSC; 129 esr |= compute_fsc(level, fsc); 130 return esr; 131 } 132 133 static int get_ia_size(struct s2_walk_info *wi) 134 { 135 return 64 - wi->t0sz; 136 } 137 138 static int check_base_s2_limits(struct s2_walk_info *wi, 139 int level, int input_size, int stride) 140 { 141 int start_size, ia_size; 142 143 ia_size = get_ia_size(wi); 144 145 /* Check translation limits */ 146 switch (BIT(wi->pgshift)) { 147 case SZ_64K: 148 if (level == 0 || (level == 1 && ia_size <= 42)) 149 return -EFAULT; 150 break; 151 case SZ_16K: 152 if (level == 0 || (level == 1 && ia_size <= 40)) 153 return -EFAULT; 154 break; 155 case SZ_4K: 156 if (level < 0 || (level == 0 && ia_size <= 42)) 157 return -EFAULT; 158 break; 159 } 160 161 /* Check input size limits */ 162 if (input_size > ia_size) 163 return -EFAULT; 164 165 /* Check number of entries in starting level table */ 166 start_size = input_size - ((3 - level) * stride + wi->pgshift); 167 if (start_size < 1 || start_size > stride + 4) 168 return -EFAULT; 169 170 return 0; 171 } 172 173 /* Check if output is within boundaries */ 174 static int check_output_size(struct s2_walk_info *wi, phys_addr_t output) 175 { 176 unsigned int output_size = wi->max_oa_bits; 177 178 if (output_size != 48 && (output & GENMASK_ULL(47, output_size))) 179 return -1; 180 181 return 0; 182 } 183 184 /* 185 * This is essentially a C-version of the pseudo code from the ARM ARM 186 * AArch64.TranslationTableWalk function. I strongly recommend looking at 187 * that pseudocode in trying to understand this. 188 * 189 * Must be called with the kvm->srcu read lock held 190 */ 191 static int walk_nested_s2_pgd(phys_addr_t ipa, 192 struct s2_walk_info *wi, struct kvm_s2_trans *out) 193 { 194 int first_block_level, level, stride, input_size, base_lower_bound; 195 phys_addr_t base_addr; 196 unsigned int addr_top, addr_bottom; 197 u64 desc; /* page table entry */ 198 int ret; 199 phys_addr_t paddr; 200 201 switch (BIT(wi->pgshift)) { 202 default: 203 case SZ_64K: 204 case SZ_16K: 205 level = 3 - wi->sl; 206 first_block_level = 2; 207 break; 208 case SZ_4K: 209 level = 2 - wi->sl; 210 first_block_level = 1; 211 break; 212 } 213 214 stride = wi->pgshift - 3; 215 input_size = get_ia_size(wi); 216 if (input_size > 48 || input_size < 25) 217 return -EFAULT; 218 219 ret = check_base_s2_limits(wi, level, input_size, stride); 220 if (WARN_ON(ret)) 221 return ret; 222 223 base_lower_bound = 3 + input_size - ((3 - level) * stride + 224 wi->pgshift); 225 base_addr = wi->baddr & GENMASK_ULL(47, base_lower_bound); 226 227 if (check_output_size(wi, base_addr)) { 228 out->esr = compute_fsc(level, ESR_ELx_FSC_ADDRSZ); 229 return 1; 230 } 231 232 addr_top = input_size - 1; 233 234 while (1) { 235 phys_addr_t index; 236 237 addr_bottom = (3 - level) * stride + wi->pgshift; 238 index = (ipa & GENMASK_ULL(addr_top, addr_bottom)) 239 >> (addr_bottom - 3); 240 241 paddr = base_addr | index; 242 ret = wi->read_desc(paddr, &desc, wi->data); 243 if (ret < 0) 244 return ret; 245 246 /* 247 * Handle reversedescriptors if endianness differs between the 248 * host and the guest hypervisor. 249 */ 250 if (wi->be) 251 desc = be64_to_cpu((__force __be64)desc); 252 else 253 desc = le64_to_cpu((__force __le64)desc); 254 255 /* Check for valid descriptor at this point */ 256 if (!(desc & 1) || ((desc & 3) == 1 && level == 3)) { 257 out->esr = compute_fsc(level, ESR_ELx_FSC_FAULT); 258 out->upper_attr = desc; 259 return 1; 260 } 261 262 /* We're at the final level or block translation level */ 263 if ((desc & 3) == 1 || level == 3) 264 break; 265 266 if (check_output_size(wi, desc)) { 267 out->esr = compute_fsc(level, ESR_ELx_FSC_ADDRSZ); 268 out->upper_attr = desc; 269 return 1; 270 } 271 272 base_addr = desc & GENMASK_ULL(47, wi->pgshift); 273 274 level += 1; 275 addr_top = addr_bottom - 1; 276 } 277 278 if (level < first_block_level) { 279 out->esr = compute_fsc(level, ESR_ELx_FSC_FAULT); 280 out->upper_attr = desc; 281 return 1; 282 } 283 284 /* 285 * We don't use the contiguous bit in the stage-2 ptes, so skip check 286 * for misprogramming of the contiguous bit. 287 */ 288 289 if (check_output_size(wi, desc)) { 290 out->esr = compute_fsc(level, ESR_ELx_FSC_ADDRSZ); 291 out->upper_attr = desc; 292 return 1; 293 } 294 295 if (!(desc & BIT(10))) { 296 out->esr = compute_fsc(level, ESR_ELx_FSC_ACCESS); 297 out->upper_attr = desc; 298 return 1; 299 } 300 301 /* Calculate and return the result */ 302 paddr = (desc & GENMASK_ULL(47, addr_bottom)) | 303 (ipa & GENMASK_ULL(addr_bottom - 1, 0)); 304 out->output = paddr; 305 out->block_size = 1UL << ((3 - level) * stride + wi->pgshift); 306 out->readable = desc & (0b01 << 6); 307 out->writable = desc & (0b10 << 6); 308 out->level = level; 309 out->upper_attr = desc & GENMASK_ULL(63, 52); 310 return 0; 311 } 312 313 static int read_guest_s2_desc(phys_addr_t pa, u64 *desc, void *data) 314 { 315 struct kvm_vcpu *vcpu = data; 316 317 return kvm_read_guest(vcpu->kvm, pa, desc, sizeof(*desc)); 318 } 319 320 static void vtcr_to_walk_info(u64 vtcr, struct s2_walk_info *wi) 321 { 322 wi->t0sz = vtcr & TCR_EL2_T0SZ_MASK; 323 324 switch (vtcr & VTCR_EL2_TG0_MASK) { 325 case VTCR_EL2_TG0_4K: 326 wi->pgshift = 12; break; 327 case VTCR_EL2_TG0_16K: 328 wi->pgshift = 14; break; 329 case VTCR_EL2_TG0_64K: 330 default: /* IMPDEF: treat any other value as 64k */ 331 wi->pgshift = 16; break; 332 } 333 334 wi->sl = FIELD_GET(VTCR_EL2_SL0_MASK, vtcr); 335 /* Global limit for now, should eventually be per-VM */ 336 wi->max_oa_bits = min(get_kvm_ipa_limit(), 337 ps_to_output_size(FIELD_GET(VTCR_EL2_PS_MASK, vtcr))); 338 } 339 340 int kvm_walk_nested_s2(struct kvm_vcpu *vcpu, phys_addr_t gipa, 341 struct kvm_s2_trans *result) 342 { 343 u64 vtcr = vcpu_read_sys_reg(vcpu, VTCR_EL2); 344 struct s2_walk_info wi; 345 int ret; 346 347 result->esr = 0; 348 349 if (!vcpu_has_nv(vcpu)) 350 return 0; 351 352 wi.read_desc = read_guest_s2_desc; 353 wi.data = vcpu; 354 wi.baddr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 355 356 vtcr_to_walk_info(vtcr, &wi); 357 358 wi.be = vcpu_read_sys_reg(vcpu, SCTLR_EL2) & SCTLR_ELx_EE; 359 360 ret = walk_nested_s2_pgd(gipa, &wi, result); 361 if (ret) 362 result->esr |= (kvm_vcpu_get_esr(vcpu) & ~ESR_ELx_FSC); 363 364 return ret; 365 } 366 367 struct kvm_s2_mmu *lookup_s2_mmu(struct kvm_vcpu *vcpu) 368 { 369 struct kvm *kvm = vcpu->kvm; 370 bool nested_stage2_enabled; 371 u64 vttbr, vtcr, hcr; 372 373 lockdep_assert_held_write(&kvm->mmu_lock); 374 375 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 376 vtcr = vcpu_read_sys_reg(vcpu, VTCR_EL2); 377 hcr = vcpu_read_sys_reg(vcpu, HCR_EL2); 378 379 nested_stage2_enabled = hcr & HCR_VM; 380 381 /* Don't consider the CnP bit for the vttbr match */ 382 vttbr &= ~VTTBR_CNP_BIT; 383 384 /* 385 * Two possibilities when looking up a S2 MMU context: 386 * 387 * - either S2 is enabled in the guest, and we need a context that is 388 * S2-enabled and matches the full VTTBR (VMID+BADDR) and VTCR, 389 * which makes it safe from a TLB conflict perspective (a broken 390 * guest won't be able to generate them), 391 * 392 * - or S2 is disabled, and we need a context that is S2-disabled 393 * and matches the VMID only, as all TLBs are tagged by VMID even 394 * if S2 translation is disabled. 395 */ 396 for (int i = 0; i < kvm->arch.nested_mmus_size; i++) { 397 struct kvm_s2_mmu *mmu = &kvm->arch.nested_mmus[i]; 398 399 if (!kvm_s2_mmu_valid(mmu)) 400 continue; 401 402 if (nested_stage2_enabled && 403 mmu->nested_stage2_enabled && 404 vttbr == mmu->tlb_vttbr && 405 vtcr == mmu->tlb_vtcr) 406 return mmu; 407 408 if (!nested_stage2_enabled && 409 !mmu->nested_stage2_enabled && 410 get_vmid(vttbr) == get_vmid(mmu->tlb_vttbr)) 411 return mmu; 412 } 413 return NULL; 414 } 415 416 static struct kvm_s2_mmu *get_s2_mmu_nested(struct kvm_vcpu *vcpu) 417 { 418 struct kvm *kvm = vcpu->kvm; 419 struct kvm_s2_mmu *s2_mmu; 420 int i; 421 422 lockdep_assert_held_write(&vcpu->kvm->mmu_lock); 423 424 s2_mmu = lookup_s2_mmu(vcpu); 425 if (s2_mmu) 426 goto out; 427 428 /* 429 * Make sure we don't always search from the same point, or we 430 * will always reuse a potentially active context, leaving 431 * free contexts unused. 432 */ 433 for (i = kvm->arch.nested_mmus_next; 434 i < (kvm->arch.nested_mmus_size + kvm->arch.nested_mmus_next); 435 i++) { 436 s2_mmu = &kvm->arch.nested_mmus[i % kvm->arch.nested_mmus_size]; 437 438 if (atomic_read(&s2_mmu->refcnt) == 0) 439 break; 440 } 441 BUG_ON(atomic_read(&s2_mmu->refcnt)); /* We have struct MMUs to spare */ 442 443 /* Set the scene for the next search */ 444 kvm->arch.nested_mmus_next = (i + 1) % kvm->arch.nested_mmus_size; 445 446 /* Clear the old state */ 447 if (kvm_s2_mmu_valid(s2_mmu)) 448 kvm_stage2_unmap_range(s2_mmu, 0, kvm_phys_size(s2_mmu)); 449 450 /* 451 * The virtual VMID (modulo CnP) will be used as a key when matching 452 * an existing kvm_s2_mmu. 453 * 454 * We cache VTCR at allocation time, once and for all. It'd be great 455 * if the guest didn't screw that one up, as this is not very 456 * forgiving... 457 */ 458 s2_mmu->tlb_vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2) & ~VTTBR_CNP_BIT; 459 s2_mmu->tlb_vtcr = vcpu_read_sys_reg(vcpu, VTCR_EL2); 460 s2_mmu->nested_stage2_enabled = vcpu_read_sys_reg(vcpu, HCR_EL2) & HCR_VM; 461 462 out: 463 atomic_inc(&s2_mmu->refcnt); 464 return s2_mmu; 465 } 466 467 void kvm_init_nested_s2_mmu(struct kvm_s2_mmu *mmu) 468 { 469 /* CnP being set denotes an invalid entry */ 470 mmu->tlb_vttbr = VTTBR_CNP_BIT; 471 mmu->nested_stage2_enabled = false; 472 atomic_set(&mmu->refcnt, 0); 473 } 474 475 void kvm_vcpu_load_hw_mmu(struct kvm_vcpu *vcpu) 476 { 477 if (is_hyp_ctxt(vcpu)) { 478 vcpu->arch.hw_mmu = &vcpu->kvm->arch.mmu; 479 } else { 480 write_lock(&vcpu->kvm->mmu_lock); 481 vcpu->arch.hw_mmu = get_s2_mmu_nested(vcpu); 482 write_unlock(&vcpu->kvm->mmu_lock); 483 } 484 } 485 486 void kvm_vcpu_put_hw_mmu(struct kvm_vcpu *vcpu) 487 { 488 if (kvm_is_nested_s2_mmu(vcpu->kvm, vcpu->arch.hw_mmu)) { 489 atomic_dec(&vcpu->arch.hw_mmu->refcnt); 490 vcpu->arch.hw_mmu = NULL; 491 } 492 } 493 494 /* 495 * Returns non-zero if permission fault is handled by injecting it to the next 496 * level hypervisor. 497 */ 498 int kvm_s2_handle_perm_fault(struct kvm_vcpu *vcpu, struct kvm_s2_trans *trans) 499 { 500 bool forward_fault = false; 501 502 trans->esr = 0; 503 504 if (!kvm_vcpu_trap_is_permission_fault(vcpu)) 505 return 0; 506 507 if (kvm_vcpu_trap_is_iabt(vcpu)) { 508 forward_fault = !kvm_s2_trans_executable(trans); 509 } else { 510 bool write_fault = kvm_is_write_fault(vcpu); 511 512 forward_fault = ((write_fault && !trans->writable) || 513 (!write_fault && !trans->readable)); 514 } 515 516 if (forward_fault) 517 trans->esr = esr_s2_fault(vcpu, trans->level, ESR_ELx_FSC_PERM); 518 519 return forward_fault; 520 } 521 522 int kvm_inject_s2_fault(struct kvm_vcpu *vcpu, u64 esr_el2) 523 { 524 vcpu_write_sys_reg(vcpu, vcpu->arch.fault.far_el2, FAR_EL2); 525 vcpu_write_sys_reg(vcpu, vcpu->arch.fault.hpfar_el2, HPFAR_EL2); 526 527 return kvm_inject_nested_sync(vcpu, esr_el2); 528 } 529 530 void kvm_nested_s2_wp(struct kvm *kvm) 531 { 532 int i; 533 534 lockdep_assert_held_write(&kvm->mmu_lock); 535 536 for (i = 0; i < kvm->arch.nested_mmus_size; i++) { 537 struct kvm_s2_mmu *mmu = &kvm->arch.nested_mmus[i]; 538 539 if (kvm_s2_mmu_valid(mmu)) 540 kvm_stage2_wp_range(mmu, 0, kvm_phys_size(mmu)); 541 } 542 } 543 544 void kvm_nested_s2_unmap(struct kvm *kvm) 545 { 546 int i; 547 548 lockdep_assert_held_write(&kvm->mmu_lock); 549 550 for (i = 0; i < kvm->arch.nested_mmus_size; i++) { 551 struct kvm_s2_mmu *mmu = &kvm->arch.nested_mmus[i]; 552 553 if (kvm_s2_mmu_valid(mmu)) 554 kvm_stage2_unmap_range(mmu, 0, kvm_phys_size(mmu)); 555 } 556 } 557 558 void kvm_nested_s2_flush(struct kvm *kvm) 559 { 560 int i; 561 562 lockdep_assert_held_write(&kvm->mmu_lock); 563 564 for (i = 0; i < kvm->arch.nested_mmus_size; i++) { 565 struct kvm_s2_mmu *mmu = &kvm->arch.nested_mmus[i]; 566 567 if (kvm_s2_mmu_valid(mmu)) 568 kvm_stage2_flush_range(mmu, 0, kvm_phys_size(mmu)); 569 } 570 } 571 572 void kvm_arch_flush_shadow_all(struct kvm *kvm) 573 { 574 int i; 575 576 for (i = 0; i < kvm->arch.nested_mmus_size; i++) { 577 struct kvm_s2_mmu *mmu = &kvm->arch.nested_mmus[i]; 578 579 if (!WARN_ON(atomic_read(&mmu->refcnt))) 580 kvm_free_stage2_pgd(mmu); 581 } 582 kfree(kvm->arch.nested_mmus); 583 kvm->arch.nested_mmus = NULL; 584 kvm->arch.nested_mmus_size = 0; 585 kvm_uninit_stage2_mmu(kvm); 586 } 587 588 /* 589 * Our emulated CPU doesn't support all the possible features. For the 590 * sake of simplicity (and probably mental sanity), wipe out a number 591 * of feature bits we don't intend to support for the time being. 592 * This list should get updated as new features get added to the NV 593 * support, and new extension to the architecture. 594 */ 595 static u64 limit_nv_id_reg(u32 id, u64 val) 596 { 597 u64 tmp; 598 599 switch (id) { 600 case SYS_ID_AA64ISAR0_EL1: 601 /* Support everything but TME, O.S. and Range TLBIs */ 602 val &= ~(NV_FTR(ISAR0, TLB) | 603 NV_FTR(ISAR0, TME)); 604 break; 605 606 case SYS_ID_AA64ISAR1_EL1: 607 /* Support everything but Spec Invalidation */ 608 val &= ~(GENMASK_ULL(63, 56) | 609 NV_FTR(ISAR1, SPECRES)); 610 break; 611 612 case SYS_ID_AA64PFR0_EL1: 613 /* No AMU, MPAM, S-EL2, RAS or SVE */ 614 val &= ~(GENMASK_ULL(55, 52) | 615 NV_FTR(PFR0, AMU) | 616 NV_FTR(PFR0, MPAM) | 617 NV_FTR(PFR0, SEL2) | 618 NV_FTR(PFR0, RAS) | 619 NV_FTR(PFR0, SVE) | 620 NV_FTR(PFR0, EL3) | 621 NV_FTR(PFR0, EL2) | 622 NV_FTR(PFR0, EL1)); 623 /* 64bit EL1/EL2/EL3 only */ 624 val |= FIELD_PREP(NV_FTR(PFR0, EL1), 0b0001); 625 val |= FIELD_PREP(NV_FTR(PFR0, EL2), 0b0001); 626 val |= FIELD_PREP(NV_FTR(PFR0, EL3), 0b0001); 627 break; 628 629 case SYS_ID_AA64PFR1_EL1: 630 /* Only support BTI, SSBS, CSV2_frac */ 631 val &= (NV_FTR(PFR1, BT) | 632 NV_FTR(PFR1, SSBS) | 633 NV_FTR(PFR1, CSV2_frac)); 634 break; 635 636 case SYS_ID_AA64MMFR0_EL1: 637 /* Hide ECV, ExS, Secure Memory */ 638 val &= ~(NV_FTR(MMFR0, ECV) | 639 NV_FTR(MMFR0, EXS) | 640 NV_FTR(MMFR0, TGRAN4_2) | 641 NV_FTR(MMFR0, TGRAN16_2) | 642 NV_FTR(MMFR0, TGRAN64_2) | 643 NV_FTR(MMFR0, SNSMEM)); 644 645 /* Disallow unsupported S2 page sizes */ 646 switch (PAGE_SIZE) { 647 case SZ_64K: 648 val |= FIELD_PREP(NV_FTR(MMFR0, TGRAN16_2), 0b0001); 649 fallthrough; 650 case SZ_16K: 651 val |= FIELD_PREP(NV_FTR(MMFR0, TGRAN4_2), 0b0001); 652 fallthrough; 653 case SZ_4K: 654 /* Support everything */ 655 break; 656 } 657 /* 658 * Since we can't support a guest S2 page size smaller than 659 * the host's own page size (due to KVM only populating its 660 * own S2 using the kernel's page size), advertise the 661 * limitation using FEAT_GTG. 662 */ 663 switch (PAGE_SIZE) { 664 case SZ_4K: 665 val |= FIELD_PREP(NV_FTR(MMFR0, TGRAN4_2), 0b0010); 666 fallthrough; 667 case SZ_16K: 668 val |= FIELD_PREP(NV_FTR(MMFR0, TGRAN16_2), 0b0010); 669 fallthrough; 670 case SZ_64K: 671 val |= FIELD_PREP(NV_FTR(MMFR0, TGRAN64_2), 0b0010); 672 break; 673 } 674 /* Cap PARange to 48bits */ 675 tmp = FIELD_GET(NV_FTR(MMFR0, PARANGE), val); 676 if (tmp > 0b0101) { 677 val &= ~NV_FTR(MMFR0, PARANGE); 678 val |= FIELD_PREP(NV_FTR(MMFR0, PARANGE), 0b0101); 679 } 680 break; 681 682 case SYS_ID_AA64MMFR1_EL1: 683 val &= (NV_FTR(MMFR1, HCX) | 684 NV_FTR(MMFR1, PAN) | 685 NV_FTR(MMFR1, LO) | 686 NV_FTR(MMFR1, HPDS) | 687 NV_FTR(MMFR1, VH) | 688 NV_FTR(MMFR1, VMIDBits)); 689 break; 690 691 case SYS_ID_AA64MMFR2_EL1: 692 val &= ~(NV_FTR(MMFR2, BBM) | 693 NV_FTR(MMFR2, TTL) | 694 GENMASK_ULL(47, 44) | 695 NV_FTR(MMFR2, ST) | 696 NV_FTR(MMFR2, CCIDX) | 697 NV_FTR(MMFR2, VARange)); 698 699 /* Force TTL support */ 700 val |= FIELD_PREP(NV_FTR(MMFR2, TTL), 0b0001); 701 break; 702 703 case SYS_ID_AA64MMFR4_EL1: 704 val = 0; 705 if (!cpus_have_final_cap(ARM64_HAS_HCR_NV1)) 706 val |= FIELD_PREP(NV_FTR(MMFR4, E2H0), 707 ID_AA64MMFR4_EL1_E2H0_NI_NV1); 708 break; 709 710 case SYS_ID_AA64DFR0_EL1: 711 /* Only limited support for PMU, Debug, BPs and WPs */ 712 val &= (NV_FTR(DFR0, PMUVer) | 713 NV_FTR(DFR0, WRPs) | 714 NV_FTR(DFR0, BRPs) | 715 NV_FTR(DFR0, DebugVer)); 716 717 /* Cap Debug to ARMv8.1 */ 718 tmp = FIELD_GET(NV_FTR(DFR0, DebugVer), val); 719 if (tmp > 0b0111) { 720 val &= ~NV_FTR(DFR0, DebugVer); 721 val |= FIELD_PREP(NV_FTR(DFR0, DebugVer), 0b0111); 722 } 723 break; 724 725 default: 726 /* Unknown register, just wipe it clean */ 727 val = 0; 728 break; 729 } 730 731 return val; 732 } 733 734 u64 kvm_vcpu_sanitise_vncr_reg(const struct kvm_vcpu *vcpu, enum vcpu_sysreg sr) 735 { 736 u64 v = ctxt_sys_reg(&vcpu->arch.ctxt, sr); 737 struct kvm_sysreg_masks *masks; 738 739 masks = vcpu->kvm->arch.sysreg_masks; 740 741 if (masks) { 742 sr -= __VNCR_START__; 743 744 v &= ~masks->mask[sr].res0; 745 v |= masks->mask[sr].res1; 746 } 747 748 return v; 749 } 750 751 static void set_sysreg_masks(struct kvm *kvm, int sr, u64 res0, u64 res1) 752 { 753 int i = sr - __VNCR_START__; 754 755 kvm->arch.sysreg_masks->mask[i].res0 = res0; 756 kvm->arch.sysreg_masks->mask[i].res1 = res1; 757 } 758 759 int kvm_init_nv_sysregs(struct kvm *kvm) 760 { 761 u64 res0, res1; 762 int ret = 0; 763 764 mutex_lock(&kvm->arch.config_lock); 765 766 if (kvm->arch.sysreg_masks) 767 goto out; 768 769 kvm->arch.sysreg_masks = kzalloc(sizeof(*(kvm->arch.sysreg_masks)), 770 GFP_KERNEL); 771 if (!kvm->arch.sysreg_masks) { 772 ret = -ENOMEM; 773 goto out; 774 } 775 776 for (int i = 0; i < KVM_ARM_ID_REG_NUM; i++) 777 kvm->arch.id_regs[i] = limit_nv_id_reg(IDX_IDREG(i), 778 kvm->arch.id_regs[i]); 779 780 /* VTTBR_EL2 */ 781 res0 = res1 = 0; 782 if (!kvm_has_feat_enum(kvm, ID_AA64MMFR1_EL1, VMIDBits, 16)) 783 res0 |= GENMASK(63, 56); 784 if (!kvm_has_feat(kvm, ID_AA64MMFR2_EL1, CnP, IMP)) 785 res0 |= VTTBR_CNP_BIT; 786 set_sysreg_masks(kvm, VTTBR_EL2, res0, res1); 787 788 /* VTCR_EL2 */ 789 res0 = GENMASK(63, 32) | GENMASK(30, 20); 790 res1 = BIT(31); 791 set_sysreg_masks(kvm, VTCR_EL2, res0, res1); 792 793 /* VMPIDR_EL2 */ 794 res0 = GENMASK(63, 40) | GENMASK(30, 24); 795 res1 = BIT(31); 796 set_sysreg_masks(kvm, VMPIDR_EL2, res0, res1); 797 798 /* HCR_EL2 */ 799 res0 = BIT(48); 800 res1 = HCR_RW; 801 if (!kvm_has_feat(kvm, ID_AA64MMFR1_EL1, TWED, IMP)) 802 res0 |= GENMASK(63, 59); 803 if (!kvm_has_feat(kvm, ID_AA64PFR1_EL1, MTE, MTE2)) 804 res0 |= (HCR_TID5 | HCR_DCT | HCR_ATA); 805 if (!kvm_has_feat(kvm, ID_AA64MMFR2_EL1, EVT, TTLBxS)) 806 res0 |= (HCR_TTLBIS | HCR_TTLBOS); 807 if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, CSV2, CSV2_2) && 808 !kvm_has_feat(kvm, ID_AA64PFR1_EL1, CSV2_frac, CSV2_1p2)) 809 res0 |= HCR_ENSCXT; 810 if (!kvm_has_feat(kvm, ID_AA64MMFR2_EL1, EVT, IMP)) 811 res0 |= (HCR_TOCU | HCR_TICAB | HCR_TID4); 812 if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, AMU, V1P1)) 813 res0 |= HCR_AMVOFFEN; 814 if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, RAS, V1P1)) 815 res0 |= HCR_FIEN; 816 if (!kvm_has_feat(kvm, ID_AA64MMFR2_EL1, FWB, IMP)) 817 res0 |= HCR_FWB; 818 if (!kvm_has_feat(kvm, ID_AA64MMFR2_EL1, NV, NV2)) 819 res0 |= HCR_NV2; 820 if (!kvm_has_feat(kvm, ID_AA64MMFR2_EL1, NV, IMP)) 821 res0 |= (HCR_AT | HCR_NV1 | HCR_NV); 822 if (!(__vcpu_has_feature(&kvm->arch, KVM_ARM_VCPU_PTRAUTH_ADDRESS) && 823 __vcpu_has_feature(&kvm->arch, KVM_ARM_VCPU_PTRAUTH_GENERIC))) 824 res0 |= (HCR_API | HCR_APK); 825 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TME, IMP)) 826 res0 |= BIT(39); 827 if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, RAS, IMP)) 828 res0 |= (HCR_TEA | HCR_TERR); 829 if (!kvm_has_feat(kvm, ID_AA64MMFR1_EL1, LO, IMP)) 830 res0 |= HCR_TLOR; 831 if (!kvm_has_feat(kvm, ID_AA64MMFR4_EL1, E2H0, IMP)) 832 res1 |= HCR_E2H; 833 set_sysreg_masks(kvm, HCR_EL2, res0, res1); 834 835 /* HCRX_EL2 */ 836 res0 = HCRX_EL2_RES0; 837 res1 = HCRX_EL2_RES1; 838 if (!kvm_has_feat(kvm, ID_AA64ISAR3_EL1, PACM, TRIVIAL_IMP)) 839 res0 |= HCRX_EL2_PACMEn; 840 if (!kvm_has_feat(kvm, ID_AA64PFR2_EL1, FPMR, IMP)) 841 res0 |= HCRX_EL2_EnFPM; 842 if (!kvm_has_feat(kvm, ID_AA64PFR1_EL1, GCS, IMP)) 843 res0 |= HCRX_EL2_GCSEn; 844 if (!kvm_has_feat(kvm, ID_AA64ISAR2_EL1, SYSREG_128, IMP)) 845 res0 |= HCRX_EL2_EnIDCP128; 846 if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, ADERR, DEV_ASYNC)) 847 res0 |= (HCRX_EL2_EnSDERR | HCRX_EL2_EnSNERR); 848 if (!kvm_has_feat(kvm, ID_AA64PFR1_EL1, DF2, IMP)) 849 res0 |= HCRX_EL2_TMEA; 850 if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, D128, IMP)) 851 res0 |= HCRX_EL2_D128En; 852 if (!kvm_has_feat(kvm, ID_AA64PFR1_EL1, THE, IMP)) 853 res0 |= HCRX_EL2_PTTWI; 854 if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, SCTLRX, IMP)) 855 res0 |= HCRX_EL2_SCTLR2En; 856 if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, TCRX, IMP)) 857 res0 |= HCRX_EL2_TCR2En; 858 if (!kvm_has_feat(kvm, ID_AA64ISAR2_EL1, MOPS, IMP)) 859 res0 |= (HCRX_EL2_MSCEn | HCRX_EL2_MCE2); 860 if (!kvm_has_feat(kvm, ID_AA64MMFR1_EL1, CMOW, IMP)) 861 res0 |= HCRX_EL2_CMOW; 862 if (!kvm_has_feat(kvm, ID_AA64PFR1_EL1, NMI, IMP)) 863 res0 |= (HCRX_EL2_VFNMI | HCRX_EL2_VINMI | HCRX_EL2_TALLINT); 864 if (!kvm_has_feat(kvm, ID_AA64PFR1_EL1, SME, IMP) || 865 !(read_sysreg_s(SYS_SMIDR_EL1) & SMIDR_EL1_SMPS)) 866 res0 |= HCRX_EL2_SMPME; 867 if (!kvm_has_feat(kvm, ID_AA64ISAR1_EL1, XS, IMP)) 868 res0 |= (HCRX_EL2_FGTnXS | HCRX_EL2_FnXS); 869 if (!kvm_has_feat(kvm, ID_AA64ISAR1_EL1, LS64, LS64_V)) 870 res0 |= HCRX_EL2_EnASR; 871 if (!kvm_has_feat(kvm, ID_AA64ISAR1_EL1, LS64, LS64)) 872 res0 |= HCRX_EL2_EnALS; 873 if (!kvm_has_feat(kvm, ID_AA64ISAR1_EL1, LS64, LS64_ACCDATA)) 874 res0 |= HCRX_EL2_EnAS0; 875 set_sysreg_masks(kvm, HCRX_EL2, res0, res1); 876 877 /* HFG[RW]TR_EL2 */ 878 res0 = res1 = 0; 879 if (!(__vcpu_has_feature(&kvm->arch, KVM_ARM_VCPU_PTRAUTH_ADDRESS) && 880 __vcpu_has_feature(&kvm->arch, KVM_ARM_VCPU_PTRAUTH_GENERIC))) 881 res0 |= (HFGxTR_EL2_APDAKey | HFGxTR_EL2_APDBKey | 882 HFGxTR_EL2_APGAKey | HFGxTR_EL2_APIAKey | 883 HFGxTR_EL2_APIBKey); 884 if (!kvm_has_feat(kvm, ID_AA64MMFR1_EL1, LO, IMP)) 885 res0 |= (HFGxTR_EL2_LORC_EL1 | HFGxTR_EL2_LOREA_EL1 | 886 HFGxTR_EL2_LORID_EL1 | HFGxTR_EL2_LORN_EL1 | 887 HFGxTR_EL2_LORSA_EL1); 888 if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, CSV2, CSV2_2) && 889 !kvm_has_feat(kvm, ID_AA64PFR1_EL1, CSV2_frac, CSV2_1p2)) 890 res0 |= (HFGxTR_EL2_SCXTNUM_EL1 | HFGxTR_EL2_SCXTNUM_EL0); 891 if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, GIC, IMP)) 892 res0 |= HFGxTR_EL2_ICC_IGRPENn_EL1; 893 if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, RAS, IMP)) 894 res0 |= (HFGxTR_EL2_ERRIDR_EL1 | HFGxTR_EL2_ERRSELR_EL1 | 895 HFGxTR_EL2_ERXFR_EL1 | HFGxTR_EL2_ERXCTLR_EL1 | 896 HFGxTR_EL2_ERXSTATUS_EL1 | HFGxTR_EL2_ERXMISCn_EL1 | 897 HFGxTR_EL2_ERXPFGF_EL1 | HFGxTR_EL2_ERXPFGCTL_EL1 | 898 HFGxTR_EL2_ERXPFGCDN_EL1 | HFGxTR_EL2_ERXADDR_EL1); 899 if (!kvm_has_feat(kvm, ID_AA64ISAR1_EL1, LS64, LS64_ACCDATA)) 900 res0 |= HFGxTR_EL2_nACCDATA_EL1; 901 if (!kvm_has_feat(kvm, ID_AA64PFR1_EL1, GCS, IMP)) 902 res0 |= (HFGxTR_EL2_nGCS_EL0 | HFGxTR_EL2_nGCS_EL1); 903 if (!kvm_has_feat(kvm, ID_AA64PFR1_EL1, SME, IMP)) 904 res0 |= (HFGxTR_EL2_nSMPRI_EL1 | HFGxTR_EL2_nTPIDR2_EL0); 905 if (!kvm_has_feat(kvm, ID_AA64PFR1_EL1, THE, IMP)) 906 res0 |= HFGxTR_EL2_nRCWMASK_EL1; 907 if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, S1PIE, IMP)) 908 res0 |= (HFGxTR_EL2_nPIRE0_EL1 | HFGxTR_EL2_nPIR_EL1); 909 if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, S1POE, IMP)) 910 res0 |= (HFGxTR_EL2_nPOR_EL0 | HFGxTR_EL2_nPOR_EL1); 911 if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, S2POE, IMP)) 912 res0 |= HFGxTR_EL2_nS2POR_EL1; 913 if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, AIE, IMP)) 914 res0 |= (HFGxTR_EL2_nMAIR2_EL1 | HFGxTR_EL2_nAMAIR2_EL1); 915 set_sysreg_masks(kvm, HFGRTR_EL2, res0 | __HFGRTR_EL2_RES0, res1); 916 set_sysreg_masks(kvm, HFGWTR_EL2, res0 | __HFGWTR_EL2_RES0, res1); 917 918 /* HDFG[RW]TR_EL2 */ 919 res0 = res1 = 0; 920 if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, DoubleLock, IMP)) 921 res0 |= HDFGRTR_EL2_OSDLR_EL1; 922 if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMUVer, IMP)) 923 res0 |= (HDFGRTR_EL2_PMEVCNTRn_EL0 | HDFGRTR_EL2_PMEVTYPERn_EL0 | 924 HDFGRTR_EL2_PMCCFILTR_EL0 | HDFGRTR_EL2_PMCCNTR_EL0 | 925 HDFGRTR_EL2_PMCNTEN | HDFGRTR_EL2_PMINTEN | 926 HDFGRTR_EL2_PMOVS | HDFGRTR_EL2_PMSELR_EL0 | 927 HDFGRTR_EL2_PMMIR_EL1 | HDFGRTR_EL2_PMUSERENR_EL0 | 928 HDFGRTR_EL2_PMCEIDn_EL0); 929 if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMSVer, IMP)) 930 res0 |= (HDFGRTR_EL2_PMBLIMITR_EL1 | HDFGRTR_EL2_PMBPTR_EL1 | 931 HDFGRTR_EL2_PMBSR_EL1 | HDFGRTR_EL2_PMSCR_EL1 | 932 HDFGRTR_EL2_PMSEVFR_EL1 | HDFGRTR_EL2_PMSFCR_EL1 | 933 HDFGRTR_EL2_PMSICR_EL1 | HDFGRTR_EL2_PMSIDR_EL1 | 934 HDFGRTR_EL2_PMSIRR_EL1 | HDFGRTR_EL2_PMSLATFR_EL1 | 935 HDFGRTR_EL2_PMBIDR_EL1); 936 if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, TraceVer, IMP)) 937 res0 |= (HDFGRTR_EL2_TRC | HDFGRTR_EL2_TRCAUTHSTATUS | 938 HDFGRTR_EL2_TRCAUXCTLR | HDFGRTR_EL2_TRCCLAIM | 939 HDFGRTR_EL2_TRCCNTVRn | HDFGRTR_EL2_TRCID | 940 HDFGRTR_EL2_TRCIMSPECn | HDFGRTR_EL2_TRCOSLSR | 941 HDFGRTR_EL2_TRCPRGCTLR | HDFGRTR_EL2_TRCSEQSTR | 942 HDFGRTR_EL2_TRCSSCSRn | HDFGRTR_EL2_TRCSTATR | 943 HDFGRTR_EL2_TRCVICTLR); 944 if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, TraceBuffer, IMP)) 945 res0 |= (HDFGRTR_EL2_TRBBASER_EL1 | HDFGRTR_EL2_TRBIDR_EL1 | 946 HDFGRTR_EL2_TRBLIMITR_EL1 | HDFGRTR_EL2_TRBMAR_EL1 | 947 HDFGRTR_EL2_TRBPTR_EL1 | HDFGRTR_EL2_TRBSR_EL1 | 948 HDFGRTR_EL2_TRBTRG_EL1); 949 if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, BRBE, IMP)) 950 res0 |= (HDFGRTR_EL2_nBRBIDR | HDFGRTR_EL2_nBRBCTL | 951 HDFGRTR_EL2_nBRBDATA); 952 if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMSVer, V1P2)) 953 res0 |= HDFGRTR_EL2_nPMSNEVFR_EL1; 954 set_sysreg_masks(kvm, HDFGRTR_EL2, res0 | HDFGRTR_EL2_RES0, res1); 955 956 /* Reuse the bits from the read-side and add the write-specific stuff */ 957 if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMUVer, IMP)) 958 res0 |= (HDFGWTR_EL2_PMCR_EL0 | HDFGWTR_EL2_PMSWINC_EL0); 959 if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, TraceVer, IMP)) 960 res0 |= HDFGWTR_EL2_TRCOSLAR; 961 if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, TraceFilt, IMP)) 962 res0 |= HDFGWTR_EL2_TRFCR_EL1; 963 set_sysreg_masks(kvm, HFGWTR_EL2, res0 | HDFGWTR_EL2_RES0, res1); 964 965 /* HFGITR_EL2 */ 966 res0 = HFGITR_EL2_RES0; 967 res1 = HFGITR_EL2_RES1; 968 if (!kvm_has_feat(kvm, ID_AA64ISAR1_EL1, DPB, DPB2)) 969 res0 |= HFGITR_EL2_DCCVADP; 970 if (!kvm_has_feat(kvm, ID_AA64MMFR1_EL1, PAN, PAN2)) 971 res0 |= (HFGITR_EL2_ATS1E1RP | HFGITR_EL2_ATS1E1WP); 972 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 973 res0 |= (HFGITR_EL2_TLBIRVAALE1OS | HFGITR_EL2_TLBIRVALE1OS | 974 HFGITR_EL2_TLBIRVAAE1OS | HFGITR_EL2_TLBIRVAE1OS | 975 HFGITR_EL2_TLBIVAALE1OS | HFGITR_EL2_TLBIVALE1OS | 976 HFGITR_EL2_TLBIVAAE1OS | HFGITR_EL2_TLBIASIDE1OS | 977 HFGITR_EL2_TLBIVAE1OS | HFGITR_EL2_TLBIVMALLE1OS); 978 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE)) 979 res0 |= (HFGITR_EL2_TLBIRVAALE1 | HFGITR_EL2_TLBIRVALE1 | 980 HFGITR_EL2_TLBIRVAAE1 | HFGITR_EL2_TLBIRVAE1 | 981 HFGITR_EL2_TLBIRVAALE1IS | HFGITR_EL2_TLBIRVALE1IS | 982 HFGITR_EL2_TLBIRVAAE1IS | HFGITR_EL2_TLBIRVAE1IS | 983 HFGITR_EL2_TLBIRVAALE1OS | HFGITR_EL2_TLBIRVALE1OS | 984 HFGITR_EL2_TLBIRVAAE1OS | HFGITR_EL2_TLBIRVAE1OS); 985 if (!kvm_has_feat(kvm, ID_AA64ISAR1_EL1, SPECRES, IMP)) 986 res0 |= (HFGITR_EL2_CFPRCTX | HFGITR_EL2_DVPRCTX | 987 HFGITR_EL2_CPPRCTX); 988 if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, BRBE, IMP)) 989 res0 |= (HFGITR_EL2_nBRBINJ | HFGITR_EL2_nBRBIALL); 990 if (!kvm_has_feat(kvm, ID_AA64PFR1_EL1, GCS, IMP)) 991 res0 |= (HFGITR_EL2_nGCSPUSHM_EL1 | HFGITR_EL2_nGCSSTR_EL1 | 992 HFGITR_EL2_nGCSEPP); 993 if (!kvm_has_feat(kvm, ID_AA64ISAR1_EL1, SPECRES, COSP_RCTX)) 994 res0 |= HFGITR_EL2_COSPRCTX; 995 if (!kvm_has_feat(kvm, ID_AA64ISAR2_EL1, ATS1A, IMP)) 996 res0 |= HFGITR_EL2_ATS1E1A; 997 set_sysreg_masks(kvm, HFGITR_EL2, res0, res1); 998 999 /* HAFGRTR_EL2 - not a lot to see here */ 1000 res0 = HAFGRTR_EL2_RES0; 1001 res1 = HAFGRTR_EL2_RES1; 1002 if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, AMU, V1P1)) 1003 res0 |= ~(res0 | res1); 1004 set_sysreg_masks(kvm, HAFGRTR_EL2, res0, res1); 1005 out: 1006 mutex_unlock(&kvm->arch.config_lock); 1007 1008 return ret; 1009 } 1010