1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2017 - Columbia University and Linaro Ltd. 4 * Author: Jintack Lim <jintack.lim@linaro.org> 5 */ 6 7 #include <linux/kvm.h> 8 #include <linux/kvm_host.h> 9 10 #include <asm/kvm_emulate.h> 11 #include <asm/kvm_nested.h> 12 #include <asm/sysreg.h> 13 14 #include "sys_regs.h" 15 16 /* Protection against the sysreg repainting madness... */ 17 #define NV_FTR(r, f) ID_AA64##r##_EL1_##f 18 19 /* 20 * Our emulated CPU doesn't support all the possible features. For the 21 * sake of simplicity (and probably mental sanity), wipe out a number 22 * of feature bits we don't intend to support for the time being. 23 * This list should get updated as new features get added to the NV 24 * support, and new extension to the architecture. 25 */ 26 static u64 limit_nv_id_reg(u32 id, u64 val) 27 { 28 u64 tmp; 29 30 switch (id) { 31 case SYS_ID_AA64ISAR0_EL1: 32 /* Support everything but TME, O.S. and Range TLBIs */ 33 val &= ~(NV_FTR(ISAR0, TLB) | 34 NV_FTR(ISAR0, TME)); 35 break; 36 37 case SYS_ID_AA64ISAR1_EL1: 38 /* Support everything but Spec Invalidation */ 39 val &= ~(GENMASK_ULL(63, 56) | 40 NV_FTR(ISAR1, SPECRES)); 41 break; 42 43 case SYS_ID_AA64PFR0_EL1: 44 /* No AMU, MPAM, S-EL2, RAS or SVE */ 45 val &= ~(GENMASK_ULL(55, 52) | 46 NV_FTR(PFR0, AMU) | 47 NV_FTR(PFR0, MPAM) | 48 NV_FTR(PFR0, SEL2) | 49 NV_FTR(PFR0, RAS) | 50 NV_FTR(PFR0, SVE) | 51 NV_FTR(PFR0, EL3) | 52 NV_FTR(PFR0, EL2) | 53 NV_FTR(PFR0, EL1)); 54 /* 64bit EL1/EL2/EL3 only */ 55 val |= FIELD_PREP(NV_FTR(PFR0, EL1), 0b0001); 56 val |= FIELD_PREP(NV_FTR(PFR0, EL2), 0b0001); 57 val |= FIELD_PREP(NV_FTR(PFR0, EL3), 0b0001); 58 break; 59 60 case SYS_ID_AA64PFR1_EL1: 61 /* Only support SSBS */ 62 val &= NV_FTR(PFR1, SSBS); 63 break; 64 65 case SYS_ID_AA64MMFR0_EL1: 66 /* Hide ECV, ExS, Secure Memory */ 67 val &= ~(NV_FTR(MMFR0, ECV) | 68 NV_FTR(MMFR0, EXS) | 69 NV_FTR(MMFR0, TGRAN4_2) | 70 NV_FTR(MMFR0, TGRAN16_2) | 71 NV_FTR(MMFR0, TGRAN64_2) | 72 NV_FTR(MMFR0, SNSMEM)); 73 74 /* Disallow unsupported S2 page sizes */ 75 switch (PAGE_SIZE) { 76 case SZ_64K: 77 val |= FIELD_PREP(NV_FTR(MMFR0, TGRAN16_2), 0b0001); 78 fallthrough; 79 case SZ_16K: 80 val |= FIELD_PREP(NV_FTR(MMFR0, TGRAN4_2), 0b0001); 81 fallthrough; 82 case SZ_4K: 83 /* Support everything */ 84 break; 85 } 86 /* 87 * Since we can't support a guest S2 page size smaller than 88 * the host's own page size (due to KVM only populating its 89 * own S2 using the kernel's page size), advertise the 90 * limitation using FEAT_GTG. 91 */ 92 switch (PAGE_SIZE) { 93 case SZ_4K: 94 val |= FIELD_PREP(NV_FTR(MMFR0, TGRAN4_2), 0b0010); 95 fallthrough; 96 case SZ_16K: 97 val |= FIELD_PREP(NV_FTR(MMFR0, TGRAN16_2), 0b0010); 98 fallthrough; 99 case SZ_64K: 100 val |= FIELD_PREP(NV_FTR(MMFR0, TGRAN64_2), 0b0010); 101 break; 102 } 103 /* Cap PARange to 48bits */ 104 tmp = FIELD_GET(NV_FTR(MMFR0, PARANGE), val); 105 if (tmp > 0b0101) { 106 val &= ~NV_FTR(MMFR0, PARANGE); 107 val |= FIELD_PREP(NV_FTR(MMFR0, PARANGE), 0b0101); 108 } 109 break; 110 111 case SYS_ID_AA64MMFR1_EL1: 112 val &= (NV_FTR(MMFR1, HCX) | 113 NV_FTR(MMFR1, PAN) | 114 NV_FTR(MMFR1, LO) | 115 NV_FTR(MMFR1, HPDS) | 116 NV_FTR(MMFR1, VH) | 117 NV_FTR(MMFR1, VMIDBits)); 118 break; 119 120 case SYS_ID_AA64MMFR2_EL1: 121 val &= ~(NV_FTR(MMFR2, BBM) | 122 NV_FTR(MMFR2, TTL) | 123 GENMASK_ULL(47, 44) | 124 NV_FTR(MMFR2, ST) | 125 NV_FTR(MMFR2, CCIDX) | 126 NV_FTR(MMFR2, VARange)); 127 128 /* Force TTL support */ 129 val |= FIELD_PREP(NV_FTR(MMFR2, TTL), 0b0001); 130 break; 131 132 case SYS_ID_AA64MMFR4_EL1: 133 val = 0; 134 if (!cpus_have_final_cap(ARM64_HAS_HCR_NV1)) 135 val |= FIELD_PREP(NV_FTR(MMFR4, E2H0), 136 ID_AA64MMFR4_EL1_E2H0_NI_NV1); 137 break; 138 139 case SYS_ID_AA64DFR0_EL1: 140 /* Only limited support for PMU, Debug, BPs and WPs */ 141 val &= (NV_FTR(DFR0, PMUVer) | 142 NV_FTR(DFR0, WRPs) | 143 NV_FTR(DFR0, BRPs) | 144 NV_FTR(DFR0, DebugVer)); 145 146 /* Cap Debug to ARMv8.1 */ 147 tmp = FIELD_GET(NV_FTR(DFR0, DebugVer), val); 148 if (tmp > 0b0111) { 149 val &= ~NV_FTR(DFR0, DebugVer); 150 val |= FIELD_PREP(NV_FTR(DFR0, DebugVer), 0b0111); 151 } 152 break; 153 154 default: 155 /* Unknown register, just wipe it clean */ 156 val = 0; 157 break; 158 } 159 160 return val; 161 } 162 163 u64 kvm_vcpu_sanitise_vncr_reg(const struct kvm_vcpu *vcpu, enum vcpu_sysreg sr) 164 { 165 u64 v = ctxt_sys_reg(&vcpu->arch.ctxt, sr); 166 struct kvm_sysreg_masks *masks; 167 168 masks = vcpu->kvm->arch.sysreg_masks; 169 170 if (masks) { 171 sr -= __VNCR_START__; 172 173 v &= ~masks->mask[sr].res0; 174 v |= masks->mask[sr].res1; 175 } 176 177 return v; 178 } 179 180 static void set_sysreg_masks(struct kvm *kvm, int sr, u64 res0, u64 res1) 181 { 182 int i = sr - __VNCR_START__; 183 184 kvm->arch.sysreg_masks->mask[i].res0 = res0; 185 kvm->arch.sysreg_masks->mask[i].res1 = res1; 186 } 187 188 int kvm_init_nv_sysregs(struct kvm *kvm) 189 { 190 u64 res0, res1; 191 int ret = 0; 192 193 mutex_lock(&kvm->arch.config_lock); 194 195 if (kvm->arch.sysreg_masks) 196 goto out; 197 198 kvm->arch.sysreg_masks = kzalloc(sizeof(*(kvm->arch.sysreg_masks)), 199 GFP_KERNEL); 200 if (!kvm->arch.sysreg_masks) { 201 ret = -ENOMEM; 202 goto out; 203 } 204 205 for (int i = 0; i < KVM_ARM_ID_REG_NUM; i++) 206 kvm->arch.id_regs[i] = limit_nv_id_reg(IDX_IDREG(i), 207 kvm->arch.id_regs[i]); 208 209 /* VTTBR_EL2 */ 210 res0 = res1 = 0; 211 if (!kvm_has_feat_enum(kvm, ID_AA64MMFR1_EL1, VMIDBits, 16)) 212 res0 |= GENMASK(63, 56); 213 if (!kvm_has_feat(kvm, ID_AA64MMFR2_EL1, CnP, IMP)) 214 res0 |= VTTBR_CNP_BIT; 215 set_sysreg_masks(kvm, VTTBR_EL2, res0, res1); 216 217 /* VTCR_EL2 */ 218 res0 = GENMASK(63, 32) | GENMASK(30, 20); 219 res1 = BIT(31); 220 set_sysreg_masks(kvm, VTCR_EL2, res0, res1); 221 222 /* VMPIDR_EL2 */ 223 res0 = GENMASK(63, 40) | GENMASK(30, 24); 224 res1 = BIT(31); 225 set_sysreg_masks(kvm, VMPIDR_EL2, res0, res1); 226 227 /* HCR_EL2 */ 228 res0 = BIT(48); 229 res1 = HCR_RW; 230 if (!kvm_has_feat(kvm, ID_AA64MMFR1_EL1, TWED, IMP)) 231 res0 |= GENMASK(63, 59); 232 if (!kvm_has_feat(kvm, ID_AA64PFR1_EL1, MTE, MTE2)) 233 res0 |= (HCR_TID5 | HCR_DCT | HCR_ATA); 234 if (!kvm_has_feat(kvm, ID_AA64MMFR2_EL1, EVT, TTLBxS)) 235 res0 |= (HCR_TTLBIS | HCR_TTLBOS); 236 if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, CSV2, CSV2_2) && 237 !kvm_has_feat(kvm, ID_AA64PFR1_EL1, CSV2_frac, CSV2_1p2)) 238 res0 |= HCR_ENSCXT; 239 if (!kvm_has_feat(kvm, ID_AA64MMFR2_EL1, EVT, IMP)) 240 res0 |= (HCR_TOCU | HCR_TICAB | HCR_TID4); 241 if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, AMU, V1P1)) 242 res0 |= HCR_AMVOFFEN; 243 if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, RAS, V1P1)) 244 res0 |= HCR_FIEN; 245 if (!kvm_has_feat(kvm, ID_AA64MMFR2_EL1, FWB, IMP)) 246 res0 |= HCR_FWB; 247 if (!kvm_has_feat(kvm, ID_AA64MMFR2_EL1, NV, NV2)) 248 res0 |= HCR_NV2; 249 if (!kvm_has_feat(kvm, ID_AA64MMFR2_EL1, NV, IMP)) 250 res0 |= (HCR_AT | HCR_NV1 | HCR_NV); 251 if (!(__vcpu_has_feature(&kvm->arch, KVM_ARM_VCPU_PTRAUTH_ADDRESS) && 252 __vcpu_has_feature(&kvm->arch, KVM_ARM_VCPU_PTRAUTH_GENERIC))) 253 res0 |= (HCR_API | HCR_APK); 254 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TME, IMP)) 255 res0 |= BIT(39); 256 if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, RAS, IMP)) 257 res0 |= (HCR_TEA | HCR_TERR); 258 if (!kvm_has_feat(kvm, ID_AA64MMFR1_EL1, LO, IMP)) 259 res0 |= HCR_TLOR; 260 if (!kvm_has_feat(kvm, ID_AA64MMFR4_EL1, E2H0, IMP)) 261 res1 |= HCR_E2H; 262 set_sysreg_masks(kvm, HCR_EL2, res0, res1); 263 264 /* HCRX_EL2 */ 265 res0 = HCRX_EL2_RES0; 266 res1 = HCRX_EL2_RES1; 267 if (!kvm_has_feat(kvm, ID_AA64ISAR3_EL1, PACM, TRIVIAL_IMP)) 268 res0 |= HCRX_EL2_PACMEn; 269 if (!kvm_has_feat(kvm, ID_AA64PFR2_EL1, FPMR, IMP)) 270 res0 |= HCRX_EL2_EnFPM; 271 if (!kvm_has_feat(kvm, ID_AA64PFR1_EL1, GCS, IMP)) 272 res0 |= HCRX_EL2_GCSEn; 273 if (!kvm_has_feat(kvm, ID_AA64ISAR2_EL1, SYSREG_128, IMP)) 274 res0 |= HCRX_EL2_EnIDCP128; 275 if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, ADERR, DEV_ASYNC)) 276 res0 |= (HCRX_EL2_EnSDERR | HCRX_EL2_EnSNERR); 277 if (!kvm_has_feat(kvm, ID_AA64PFR1_EL1, DF2, IMP)) 278 res0 |= HCRX_EL2_TMEA; 279 if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, D128, IMP)) 280 res0 |= HCRX_EL2_D128En; 281 if (!kvm_has_feat(kvm, ID_AA64PFR1_EL1, THE, IMP)) 282 res0 |= HCRX_EL2_PTTWI; 283 if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, SCTLRX, IMP)) 284 res0 |= HCRX_EL2_SCTLR2En; 285 if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, TCRX, IMP)) 286 res0 |= HCRX_EL2_TCR2En; 287 if (!kvm_has_feat(kvm, ID_AA64ISAR2_EL1, MOPS, IMP)) 288 res0 |= (HCRX_EL2_MSCEn | HCRX_EL2_MCE2); 289 if (!kvm_has_feat(kvm, ID_AA64MMFR1_EL1, CMOW, IMP)) 290 res0 |= HCRX_EL2_CMOW; 291 if (!kvm_has_feat(kvm, ID_AA64PFR1_EL1, NMI, IMP)) 292 res0 |= (HCRX_EL2_VFNMI | HCRX_EL2_VINMI | HCRX_EL2_TALLINT); 293 if (!kvm_has_feat(kvm, ID_AA64PFR1_EL1, SME, IMP) || 294 !(read_sysreg_s(SYS_SMIDR_EL1) & SMIDR_EL1_SMPS)) 295 res0 |= HCRX_EL2_SMPME; 296 if (!kvm_has_feat(kvm, ID_AA64ISAR1_EL1, XS, IMP)) 297 res0 |= (HCRX_EL2_FGTnXS | HCRX_EL2_FnXS); 298 if (!kvm_has_feat(kvm, ID_AA64ISAR1_EL1, LS64, LS64_V)) 299 res0 |= HCRX_EL2_EnASR; 300 if (!kvm_has_feat(kvm, ID_AA64ISAR1_EL1, LS64, LS64)) 301 res0 |= HCRX_EL2_EnALS; 302 if (!kvm_has_feat(kvm, ID_AA64ISAR1_EL1, LS64, LS64_ACCDATA)) 303 res0 |= HCRX_EL2_EnAS0; 304 set_sysreg_masks(kvm, HCRX_EL2, res0, res1); 305 306 /* HFG[RW]TR_EL2 */ 307 res0 = res1 = 0; 308 if (!(__vcpu_has_feature(&kvm->arch, KVM_ARM_VCPU_PTRAUTH_ADDRESS) && 309 __vcpu_has_feature(&kvm->arch, KVM_ARM_VCPU_PTRAUTH_GENERIC))) 310 res0 |= (HFGxTR_EL2_APDAKey | HFGxTR_EL2_APDBKey | 311 HFGxTR_EL2_APGAKey | HFGxTR_EL2_APIAKey | 312 HFGxTR_EL2_APIBKey); 313 if (!kvm_has_feat(kvm, ID_AA64MMFR1_EL1, LO, IMP)) 314 res0 |= (HFGxTR_EL2_LORC_EL1 | HFGxTR_EL2_LOREA_EL1 | 315 HFGxTR_EL2_LORID_EL1 | HFGxTR_EL2_LORN_EL1 | 316 HFGxTR_EL2_LORSA_EL1); 317 if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, CSV2, CSV2_2) && 318 !kvm_has_feat(kvm, ID_AA64PFR1_EL1, CSV2_frac, CSV2_1p2)) 319 res0 |= (HFGxTR_EL2_SCXTNUM_EL1 | HFGxTR_EL2_SCXTNUM_EL0); 320 if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, GIC, IMP)) 321 res0 |= HFGxTR_EL2_ICC_IGRPENn_EL1; 322 if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, RAS, IMP)) 323 res0 |= (HFGxTR_EL2_ERRIDR_EL1 | HFGxTR_EL2_ERRSELR_EL1 | 324 HFGxTR_EL2_ERXFR_EL1 | HFGxTR_EL2_ERXCTLR_EL1 | 325 HFGxTR_EL2_ERXSTATUS_EL1 | HFGxTR_EL2_ERXMISCn_EL1 | 326 HFGxTR_EL2_ERXPFGF_EL1 | HFGxTR_EL2_ERXPFGCTL_EL1 | 327 HFGxTR_EL2_ERXPFGCDN_EL1 | HFGxTR_EL2_ERXADDR_EL1); 328 if (!kvm_has_feat(kvm, ID_AA64ISAR1_EL1, LS64, LS64_ACCDATA)) 329 res0 |= HFGxTR_EL2_nACCDATA_EL1; 330 if (!kvm_has_feat(kvm, ID_AA64PFR1_EL1, GCS, IMP)) 331 res0 |= (HFGxTR_EL2_nGCS_EL0 | HFGxTR_EL2_nGCS_EL1); 332 if (!kvm_has_feat(kvm, ID_AA64PFR1_EL1, SME, IMP)) 333 res0 |= (HFGxTR_EL2_nSMPRI_EL1 | HFGxTR_EL2_nTPIDR2_EL0); 334 if (!kvm_has_feat(kvm, ID_AA64PFR1_EL1, THE, IMP)) 335 res0 |= HFGxTR_EL2_nRCWMASK_EL1; 336 if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, S1PIE, IMP)) 337 res0 |= (HFGxTR_EL2_nPIRE0_EL1 | HFGxTR_EL2_nPIR_EL1); 338 if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, S1POE, IMP)) 339 res0 |= (HFGxTR_EL2_nPOR_EL0 | HFGxTR_EL2_nPOR_EL1); 340 if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, S2POE, IMP)) 341 res0 |= HFGxTR_EL2_nS2POR_EL1; 342 if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, AIE, IMP)) 343 res0 |= (HFGxTR_EL2_nMAIR2_EL1 | HFGxTR_EL2_nAMAIR2_EL1); 344 set_sysreg_masks(kvm, HFGRTR_EL2, res0 | __HFGRTR_EL2_RES0, res1); 345 set_sysreg_masks(kvm, HFGWTR_EL2, res0 | __HFGWTR_EL2_RES0, res1); 346 347 /* HDFG[RW]TR_EL2 */ 348 res0 = res1 = 0; 349 if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, DoubleLock, IMP)) 350 res0 |= HDFGRTR_EL2_OSDLR_EL1; 351 if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMUVer, IMP)) 352 res0 |= (HDFGRTR_EL2_PMEVCNTRn_EL0 | HDFGRTR_EL2_PMEVTYPERn_EL0 | 353 HDFGRTR_EL2_PMCCFILTR_EL0 | HDFGRTR_EL2_PMCCNTR_EL0 | 354 HDFGRTR_EL2_PMCNTEN | HDFGRTR_EL2_PMINTEN | 355 HDFGRTR_EL2_PMOVS | HDFGRTR_EL2_PMSELR_EL0 | 356 HDFGRTR_EL2_PMMIR_EL1 | HDFGRTR_EL2_PMUSERENR_EL0 | 357 HDFGRTR_EL2_PMCEIDn_EL0); 358 if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMSVer, IMP)) 359 res0 |= (HDFGRTR_EL2_PMBLIMITR_EL1 | HDFGRTR_EL2_PMBPTR_EL1 | 360 HDFGRTR_EL2_PMBSR_EL1 | HDFGRTR_EL2_PMSCR_EL1 | 361 HDFGRTR_EL2_PMSEVFR_EL1 | HDFGRTR_EL2_PMSFCR_EL1 | 362 HDFGRTR_EL2_PMSICR_EL1 | HDFGRTR_EL2_PMSIDR_EL1 | 363 HDFGRTR_EL2_PMSIRR_EL1 | HDFGRTR_EL2_PMSLATFR_EL1 | 364 HDFGRTR_EL2_PMBIDR_EL1); 365 if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, TraceVer, IMP)) 366 res0 |= (HDFGRTR_EL2_TRC | HDFGRTR_EL2_TRCAUTHSTATUS | 367 HDFGRTR_EL2_TRCAUXCTLR | HDFGRTR_EL2_TRCCLAIM | 368 HDFGRTR_EL2_TRCCNTVRn | HDFGRTR_EL2_TRCID | 369 HDFGRTR_EL2_TRCIMSPECn | HDFGRTR_EL2_TRCOSLSR | 370 HDFGRTR_EL2_TRCPRGCTLR | HDFGRTR_EL2_TRCSEQSTR | 371 HDFGRTR_EL2_TRCSSCSRn | HDFGRTR_EL2_TRCSTATR | 372 HDFGRTR_EL2_TRCVICTLR); 373 if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, TraceBuffer, IMP)) 374 res0 |= (HDFGRTR_EL2_TRBBASER_EL1 | HDFGRTR_EL2_TRBIDR_EL1 | 375 HDFGRTR_EL2_TRBLIMITR_EL1 | HDFGRTR_EL2_TRBMAR_EL1 | 376 HDFGRTR_EL2_TRBPTR_EL1 | HDFGRTR_EL2_TRBSR_EL1 | 377 HDFGRTR_EL2_TRBTRG_EL1); 378 if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, BRBE, IMP)) 379 res0 |= (HDFGRTR_EL2_nBRBIDR | HDFGRTR_EL2_nBRBCTL | 380 HDFGRTR_EL2_nBRBDATA); 381 if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMSVer, V1P2)) 382 res0 |= HDFGRTR_EL2_nPMSNEVFR_EL1; 383 set_sysreg_masks(kvm, HDFGRTR_EL2, res0 | HDFGRTR_EL2_RES0, res1); 384 385 /* Reuse the bits from the read-side and add the write-specific stuff */ 386 if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMUVer, IMP)) 387 res0 |= (HDFGWTR_EL2_PMCR_EL0 | HDFGWTR_EL2_PMSWINC_EL0); 388 if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, TraceVer, IMP)) 389 res0 |= HDFGWTR_EL2_TRCOSLAR; 390 if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, TraceFilt, IMP)) 391 res0 |= HDFGWTR_EL2_TRFCR_EL1; 392 set_sysreg_masks(kvm, HFGWTR_EL2, res0 | HDFGWTR_EL2_RES0, res1); 393 394 /* HFGITR_EL2 */ 395 res0 = HFGITR_EL2_RES0; 396 res1 = HFGITR_EL2_RES1; 397 if (!kvm_has_feat(kvm, ID_AA64ISAR1_EL1, DPB, DPB2)) 398 res0 |= HFGITR_EL2_DCCVADP; 399 if (!kvm_has_feat(kvm, ID_AA64MMFR1_EL1, PAN, PAN2)) 400 res0 |= (HFGITR_EL2_ATS1E1RP | HFGITR_EL2_ATS1E1WP); 401 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 402 res0 |= (HFGITR_EL2_TLBIRVAALE1OS | HFGITR_EL2_TLBIRVALE1OS | 403 HFGITR_EL2_TLBIRVAAE1OS | HFGITR_EL2_TLBIRVAE1OS | 404 HFGITR_EL2_TLBIVAALE1OS | HFGITR_EL2_TLBIVALE1OS | 405 HFGITR_EL2_TLBIVAAE1OS | HFGITR_EL2_TLBIASIDE1OS | 406 HFGITR_EL2_TLBIVAE1OS | HFGITR_EL2_TLBIVMALLE1OS); 407 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE)) 408 res0 |= (HFGITR_EL2_TLBIRVAALE1 | HFGITR_EL2_TLBIRVALE1 | 409 HFGITR_EL2_TLBIRVAAE1 | HFGITR_EL2_TLBIRVAE1 | 410 HFGITR_EL2_TLBIRVAALE1IS | HFGITR_EL2_TLBIRVALE1IS | 411 HFGITR_EL2_TLBIRVAAE1IS | HFGITR_EL2_TLBIRVAE1IS | 412 HFGITR_EL2_TLBIRVAALE1OS | HFGITR_EL2_TLBIRVALE1OS | 413 HFGITR_EL2_TLBIRVAAE1OS | HFGITR_EL2_TLBIRVAE1OS); 414 if (!kvm_has_feat(kvm, ID_AA64ISAR1_EL1, SPECRES, IMP)) 415 res0 |= (HFGITR_EL2_CFPRCTX | HFGITR_EL2_DVPRCTX | 416 HFGITR_EL2_CPPRCTX); 417 if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, BRBE, IMP)) 418 res0 |= (HFGITR_EL2_nBRBINJ | HFGITR_EL2_nBRBIALL); 419 if (!kvm_has_feat(kvm, ID_AA64PFR1_EL1, GCS, IMP)) 420 res0 |= (HFGITR_EL2_nGCSPUSHM_EL1 | HFGITR_EL2_nGCSSTR_EL1 | 421 HFGITR_EL2_nGCSEPP); 422 if (!kvm_has_feat(kvm, ID_AA64ISAR1_EL1, SPECRES, COSP_RCTX)) 423 res0 |= HFGITR_EL2_COSPRCTX; 424 if (!kvm_has_feat(kvm, ID_AA64ISAR2_EL1, ATS1A, IMP)) 425 res0 |= HFGITR_EL2_ATS1E1A; 426 set_sysreg_masks(kvm, HFGITR_EL2, res0, res1); 427 428 /* HAFGRTR_EL2 - not a lot to see here */ 429 res0 = HAFGRTR_EL2_RES0; 430 res1 = HAFGRTR_EL2_RES1; 431 if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, AMU, V1P1)) 432 res0 |= ~(res0 | res1); 433 set_sysreg_masks(kvm, HAFGRTR_EL2, res0, res1); 434 out: 435 mutex_unlock(&kvm->arch.config_lock); 436 437 return ret; 438 } 439