1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7 #include <linux/irqflags.h> 8 9 #include <asm/kvm_hyp.h> 10 #include <asm/kvm_mmu.h> 11 #include <asm/tlbflush.h> 12 13 struct tlb_inv_context { 14 struct kvm_s2_mmu *mmu; 15 unsigned long flags; 16 u64 tcr; 17 u64 sctlr; 18 }; 19 20 static void enter_vmid_context(struct kvm_s2_mmu *mmu, 21 struct tlb_inv_context *cxt) 22 { 23 struct kvm_vcpu *vcpu = kvm_get_running_vcpu(); 24 u64 val; 25 26 local_irq_save(cxt->flags); 27 28 if (vcpu && mmu != vcpu->arch.hw_mmu) 29 cxt->mmu = vcpu->arch.hw_mmu; 30 else 31 cxt->mmu = NULL; 32 33 if (cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) { 34 /* 35 * For CPUs that are affected by ARM errata 1165522 or 1530923, 36 * we cannot trust stage-1 to be in a correct state at that 37 * point. Since we do not want to force a full load of the 38 * vcpu state, we prevent the EL1 page-table walker to 39 * allocate new TLBs. This is done by setting the EPD bits 40 * in the TCR_EL1 register. We also need to prevent it to 41 * allocate IPA->PA walks, so we enable the S1 MMU... 42 */ 43 val = cxt->tcr = read_sysreg_el1(SYS_TCR); 44 val |= TCR_EPD1_MASK | TCR_EPD0_MASK; 45 write_sysreg_el1(val, SYS_TCR); 46 val = cxt->sctlr = read_sysreg_el1(SYS_SCTLR); 47 val |= SCTLR_ELx_M; 48 write_sysreg_el1(val, SYS_SCTLR); 49 } 50 51 /* 52 * With VHE enabled, we have HCR_EL2.{E2H,TGE} = {1,1}, and 53 * most TLB operations target EL2/EL0. In order to affect the 54 * guest TLBs (EL1/EL0), we need to change one of these two 55 * bits. Changing E2H is impossible (goodbye TTBR1_EL2), so 56 * let's flip TGE before executing the TLB operation. 57 * 58 * ARM erratum 1165522 requires some special handling (again), 59 * as we need to make sure both stages of translation are in 60 * place before clearing TGE. __load_stage2() already 61 * has an ISB in order to deal with this. 62 */ 63 __load_stage2(mmu, mmu->arch); 64 val = read_sysreg(hcr_el2); 65 val &= ~HCR_TGE; 66 write_sysreg_hcr(val); 67 isb(); 68 } 69 70 static void exit_vmid_context(struct tlb_inv_context *cxt) 71 { 72 /* 73 * We're done with the TLB operation, let's restore the host's 74 * view of HCR_EL2. 75 */ 76 write_sysreg_hcr(HCR_HOST_VHE_FLAGS); 77 isb(); 78 79 /* ... and the stage-2 MMU context that we switched away from */ 80 if (cxt->mmu) 81 __load_stage2(cxt->mmu, cxt->mmu->arch); 82 83 if (cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) { 84 /* Restore the registers to what they were */ 85 write_sysreg_el1(cxt->tcr, SYS_TCR); 86 write_sysreg_el1(cxt->sctlr, SYS_SCTLR); 87 } 88 89 local_irq_restore(cxt->flags); 90 } 91 92 void __kvm_tlb_flush_vmid_ipa(struct kvm_s2_mmu *mmu, 93 phys_addr_t ipa, int level) 94 { 95 struct tlb_inv_context cxt; 96 97 dsb(ishst); 98 99 /* Switch to requested VMID */ 100 enter_vmid_context(mmu, &cxt); 101 102 /* 103 * We could do so much better if we had the VA as well. 104 * Instead, we invalidate Stage-2 for this IPA, and the 105 * whole of Stage-1. Weep... 106 */ 107 __tlbi_level(ipas2e1is, ipa, level); 108 109 /* 110 * We have to ensure completion of the invalidation at Stage-2, 111 * since a table walk on another CPU could refill a TLB with a 112 * complete (S1 + S2) walk based on the old Stage-2 mapping if 113 * the Stage-1 invalidation happened first. 114 */ 115 dsb(ish); 116 __tlbi(vmalle1is); 117 __tlbi_sync_s1ish_hyp(); 118 isb(); 119 120 exit_vmid_context(&cxt); 121 } 122 123 void __kvm_tlb_flush_vmid_ipa_nsh(struct kvm_s2_mmu *mmu, 124 phys_addr_t ipa, int level) 125 { 126 struct tlb_inv_context cxt; 127 128 dsb(nshst); 129 130 /* Switch to requested VMID */ 131 enter_vmid_context(mmu, &cxt); 132 133 /* 134 * We could do so much better if we had the VA as well. 135 * Instead, we invalidate Stage-2 for this IPA, and the 136 * whole of Stage-1. Weep... 137 */ 138 __tlbi_level(ipas2e1, ipa, level); 139 140 /* 141 * We have to ensure completion of the invalidation at Stage-2, 142 * since a table walk on another CPU could refill a TLB with a 143 * complete (S1 + S2) walk based on the old Stage-2 mapping if 144 * the Stage-1 invalidation happened first. 145 */ 146 dsb(nsh); 147 __tlbi(vmalle1); 148 dsb(nsh); 149 isb(); 150 151 exit_vmid_context(&cxt); 152 } 153 154 void __kvm_tlb_flush_vmid_range(struct kvm_s2_mmu *mmu, 155 phys_addr_t start, unsigned long pages) 156 { 157 struct tlb_inv_context cxt; 158 unsigned long stride; 159 160 /* 161 * Since the range of addresses may not be mapped at 162 * the same level, assume the worst case as PAGE_SIZE 163 */ 164 stride = PAGE_SIZE; 165 start = round_down(start, stride); 166 167 dsb(ishst); 168 169 /* Switch to requested VMID */ 170 enter_vmid_context(mmu, &cxt); 171 172 __flush_s2_tlb_range_op(ipas2e1is, start, pages, stride, 173 TLBI_TTL_UNKNOWN); 174 175 dsb(ish); 176 __tlbi(vmalle1is); 177 __tlbi_sync_s1ish_hyp(); 178 isb(); 179 180 exit_vmid_context(&cxt); 181 } 182 183 void __kvm_tlb_flush_vmid(struct kvm_s2_mmu *mmu) 184 { 185 struct tlb_inv_context cxt; 186 187 dsb(ishst); 188 189 /* Switch to requested VMID */ 190 enter_vmid_context(mmu, &cxt); 191 192 __tlbi(vmalls12e1is); 193 __tlbi_sync_s1ish_hyp(); 194 isb(); 195 196 exit_vmid_context(&cxt); 197 } 198 199 void __kvm_flush_cpu_context(struct kvm_s2_mmu *mmu) 200 { 201 struct tlb_inv_context cxt; 202 203 /* Switch to requested VMID */ 204 enter_vmid_context(mmu, &cxt); 205 206 __tlbi(vmalle1); 207 asm volatile("ic iallu"); 208 dsb(nsh); 209 isb(); 210 211 exit_vmid_context(&cxt); 212 } 213 214 void __kvm_flush_vm_context(void) 215 { 216 dsb(ishst); 217 __tlbi(alle1is); 218 __tlbi_sync_s1ish_hyp(); 219 } 220 221 /* 222 * TLB invalidation emulation for NV. For any given instruction, we 223 * perform the following transformtions: 224 * 225 * - a TLBI targeting EL2 S1 is remapped to EL1 S1 226 * - a non-shareable TLBI is upgraded to being inner-shareable 227 * - an outer-shareable TLBI is also mapped to inner-shareable 228 * - an nXS TLBI is upgraded to XS 229 */ 230 int __kvm_tlbi_s1e2(struct kvm_s2_mmu *mmu, u64 va, u64 sys_encoding) 231 { 232 struct tlb_inv_context cxt; 233 int ret = 0; 234 235 /* 236 * The guest will have provided its own DSB ISHST before trapping. 237 * If it hasn't, that's its own problem, and we won't paper over it 238 * (plus, there is plenty of extra synchronisation before we even 239 * get here...). 240 */ 241 242 if (mmu) 243 enter_vmid_context(mmu, &cxt); 244 245 switch (sys_encoding) { 246 case OP_TLBI_ALLE2: 247 case OP_TLBI_ALLE2IS: 248 case OP_TLBI_ALLE2OS: 249 case OP_TLBI_VMALLE1: 250 case OP_TLBI_VMALLE1IS: 251 case OP_TLBI_VMALLE1OS: 252 case OP_TLBI_ALLE2NXS: 253 case OP_TLBI_ALLE2ISNXS: 254 case OP_TLBI_ALLE2OSNXS: 255 case OP_TLBI_VMALLE1NXS: 256 case OP_TLBI_VMALLE1ISNXS: 257 case OP_TLBI_VMALLE1OSNXS: 258 __tlbi(vmalle1is); 259 break; 260 case OP_TLBI_VAE2: 261 case OP_TLBI_VAE2IS: 262 case OP_TLBI_VAE2OS: 263 case OP_TLBI_VAE1: 264 case OP_TLBI_VAE1IS: 265 case OP_TLBI_VAE1OS: 266 case OP_TLBI_VAE2NXS: 267 case OP_TLBI_VAE2ISNXS: 268 case OP_TLBI_VAE2OSNXS: 269 case OP_TLBI_VAE1NXS: 270 case OP_TLBI_VAE1ISNXS: 271 case OP_TLBI_VAE1OSNXS: 272 __tlbi(vae1is, va); 273 break; 274 case OP_TLBI_VALE2: 275 case OP_TLBI_VALE2IS: 276 case OP_TLBI_VALE2OS: 277 case OP_TLBI_VALE1: 278 case OP_TLBI_VALE1IS: 279 case OP_TLBI_VALE1OS: 280 case OP_TLBI_VALE2NXS: 281 case OP_TLBI_VALE2ISNXS: 282 case OP_TLBI_VALE2OSNXS: 283 case OP_TLBI_VALE1NXS: 284 case OP_TLBI_VALE1ISNXS: 285 case OP_TLBI_VALE1OSNXS: 286 __tlbi(vale1is, va); 287 break; 288 case OP_TLBI_ASIDE1: 289 case OP_TLBI_ASIDE1IS: 290 case OP_TLBI_ASIDE1OS: 291 case OP_TLBI_ASIDE1NXS: 292 case OP_TLBI_ASIDE1ISNXS: 293 case OP_TLBI_ASIDE1OSNXS: 294 __tlbi(aside1is, va); 295 break; 296 case OP_TLBI_VAAE1: 297 case OP_TLBI_VAAE1IS: 298 case OP_TLBI_VAAE1OS: 299 case OP_TLBI_VAAE1NXS: 300 case OP_TLBI_VAAE1ISNXS: 301 case OP_TLBI_VAAE1OSNXS: 302 __tlbi(vaae1is, va); 303 break; 304 case OP_TLBI_VAALE1: 305 case OP_TLBI_VAALE1IS: 306 case OP_TLBI_VAALE1OS: 307 case OP_TLBI_VAALE1NXS: 308 case OP_TLBI_VAALE1ISNXS: 309 case OP_TLBI_VAALE1OSNXS: 310 __tlbi(vaale1is, va); 311 break; 312 case OP_TLBI_RVAE2: 313 case OP_TLBI_RVAE2IS: 314 case OP_TLBI_RVAE2OS: 315 case OP_TLBI_RVAE1: 316 case OP_TLBI_RVAE1IS: 317 case OP_TLBI_RVAE1OS: 318 case OP_TLBI_RVAE2NXS: 319 case OP_TLBI_RVAE2ISNXS: 320 case OP_TLBI_RVAE2OSNXS: 321 case OP_TLBI_RVAE1NXS: 322 case OP_TLBI_RVAE1ISNXS: 323 case OP_TLBI_RVAE1OSNXS: 324 __tlbi(rvae1is, va); 325 break; 326 case OP_TLBI_RVALE2: 327 case OP_TLBI_RVALE2IS: 328 case OP_TLBI_RVALE2OS: 329 case OP_TLBI_RVALE1: 330 case OP_TLBI_RVALE1IS: 331 case OP_TLBI_RVALE1OS: 332 case OP_TLBI_RVALE2NXS: 333 case OP_TLBI_RVALE2ISNXS: 334 case OP_TLBI_RVALE2OSNXS: 335 case OP_TLBI_RVALE1NXS: 336 case OP_TLBI_RVALE1ISNXS: 337 case OP_TLBI_RVALE1OSNXS: 338 __tlbi(rvale1is, va); 339 break; 340 case OP_TLBI_RVAAE1: 341 case OP_TLBI_RVAAE1IS: 342 case OP_TLBI_RVAAE1OS: 343 case OP_TLBI_RVAAE1NXS: 344 case OP_TLBI_RVAAE1ISNXS: 345 case OP_TLBI_RVAAE1OSNXS: 346 __tlbi(rvaae1is, va); 347 break; 348 case OP_TLBI_RVAALE1: 349 case OP_TLBI_RVAALE1IS: 350 case OP_TLBI_RVAALE1OS: 351 case OP_TLBI_RVAALE1NXS: 352 case OP_TLBI_RVAALE1ISNXS: 353 case OP_TLBI_RVAALE1OSNXS: 354 __tlbi(rvaale1is, va); 355 break; 356 default: 357 ret = -EINVAL; 358 } 359 __tlbi_sync_s1ish_hyp(); 360 isb(); 361 362 if (mmu) 363 exit_vmid_context(&cxt); 364 365 return ret; 366 } 367