1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012-2015 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7 #include <hyp/sysreg-sr.h> 8 9 #include <linux/compiler.h> 10 #include <linux/kvm_host.h> 11 12 #include <asm/kprobes.h> 13 #include <asm/kvm_asm.h> 14 #include <asm/kvm_emulate.h> 15 #include <asm/kvm_hyp.h> 16 #include <asm/kvm_nested.h> 17 18 static void __sysreg_save_vel2_state(struct kvm_vcpu *vcpu) 19 { 20 /* These registers are common with EL1 */ 21 __vcpu_sys_reg(vcpu, PAR_EL1) = read_sysreg(par_el1); 22 __vcpu_sys_reg(vcpu, TPIDR_EL1) = read_sysreg(tpidr_el1); 23 24 __vcpu_sys_reg(vcpu, ESR_EL2) = read_sysreg_el1(SYS_ESR); 25 __vcpu_sys_reg(vcpu, AFSR0_EL2) = read_sysreg_el1(SYS_AFSR0); 26 __vcpu_sys_reg(vcpu, AFSR1_EL2) = read_sysreg_el1(SYS_AFSR1); 27 __vcpu_sys_reg(vcpu, FAR_EL2) = read_sysreg_el1(SYS_FAR); 28 __vcpu_sys_reg(vcpu, MAIR_EL2) = read_sysreg_el1(SYS_MAIR); 29 __vcpu_sys_reg(vcpu, VBAR_EL2) = read_sysreg_el1(SYS_VBAR); 30 __vcpu_sys_reg(vcpu, CONTEXTIDR_EL2) = read_sysreg_el1(SYS_CONTEXTIDR); 31 __vcpu_sys_reg(vcpu, AMAIR_EL2) = read_sysreg_el1(SYS_AMAIR); 32 33 /* 34 * In VHE mode those registers are compatible between EL1 and EL2, 35 * and the guest uses the _EL1 versions on the CPU naturally. 36 * So we save them into their _EL2 versions here. 37 * For nVHE mode we trap accesses to those registers, so our 38 * _EL2 copy in sys_regs[] is always up-to-date and we don't need 39 * to save anything here. 40 */ 41 if (vcpu_el2_e2h_is_set(vcpu)) { 42 u64 val; 43 44 /* 45 * We don't save CPTR_EL2, as accesses to CPACR_EL1 46 * are always trapped, ensuring that the in-memory 47 * copy is always up-to-date. A small blessing... 48 */ 49 __vcpu_sys_reg(vcpu, SCTLR_EL2) = read_sysreg_el1(SYS_SCTLR); 50 __vcpu_sys_reg(vcpu, TTBR0_EL2) = read_sysreg_el1(SYS_TTBR0); 51 __vcpu_sys_reg(vcpu, TTBR1_EL2) = read_sysreg_el1(SYS_TTBR1); 52 __vcpu_sys_reg(vcpu, TCR_EL2) = read_sysreg_el1(SYS_TCR); 53 54 if (ctxt_has_tcrx(&vcpu->arch.ctxt)) { 55 __vcpu_sys_reg(vcpu, TCR2_EL2) = read_sysreg_el1(SYS_TCR2); 56 57 if (ctxt_has_s1pie(&vcpu->arch.ctxt)) { 58 __vcpu_sys_reg(vcpu, PIRE0_EL2) = read_sysreg_el1(SYS_PIRE0); 59 __vcpu_sys_reg(vcpu, PIR_EL2) = read_sysreg_el1(SYS_PIR); 60 } 61 } 62 63 /* 64 * The EL1 view of CNTKCTL_EL1 has a bunch of RES0 bits where 65 * the interesting CNTHCTL_EL2 bits live. So preserve these 66 * bits when reading back the guest-visible value. 67 */ 68 val = read_sysreg_el1(SYS_CNTKCTL); 69 val &= CNTKCTL_VALID_BITS; 70 __vcpu_sys_reg(vcpu, CNTHCTL_EL2) &= ~CNTKCTL_VALID_BITS; 71 __vcpu_sys_reg(vcpu, CNTHCTL_EL2) |= val; 72 } 73 74 __vcpu_sys_reg(vcpu, SP_EL2) = read_sysreg(sp_el1); 75 __vcpu_sys_reg(vcpu, ELR_EL2) = read_sysreg_el1(SYS_ELR); 76 __vcpu_sys_reg(vcpu, SPSR_EL2) = read_sysreg_el1(SYS_SPSR); 77 } 78 79 static void __sysreg_restore_vel2_state(struct kvm_vcpu *vcpu) 80 { 81 u64 val; 82 83 /* These registers are common with EL1 */ 84 write_sysreg(__vcpu_sys_reg(vcpu, PAR_EL1), par_el1); 85 write_sysreg(__vcpu_sys_reg(vcpu, TPIDR_EL1), tpidr_el1); 86 87 write_sysreg(__vcpu_sys_reg(vcpu, MPIDR_EL1), vmpidr_el2); 88 write_sysreg_el1(__vcpu_sys_reg(vcpu, MAIR_EL2), SYS_MAIR); 89 write_sysreg_el1(__vcpu_sys_reg(vcpu, VBAR_EL2), SYS_VBAR); 90 write_sysreg_el1(__vcpu_sys_reg(vcpu, CONTEXTIDR_EL2), SYS_CONTEXTIDR); 91 write_sysreg_el1(__vcpu_sys_reg(vcpu, AMAIR_EL2), SYS_AMAIR); 92 93 if (vcpu_el2_e2h_is_set(vcpu)) { 94 /* 95 * In VHE mode those registers are compatible between 96 * EL1 and EL2. 97 */ 98 write_sysreg_el1(__vcpu_sys_reg(vcpu, SCTLR_EL2), SYS_SCTLR); 99 write_sysreg_el1(__vcpu_sys_reg(vcpu, CPTR_EL2), SYS_CPACR); 100 write_sysreg_el1(__vcpu_sys_reg(vcpu, TTBR0_EL2), SYS_TTBR0); 101 write_sysreg_el1(__vcpu_sys_reg(vcpu, TTBR1_EL2), SYS_TTBR1); 102 write_sysreg_el1(__vcpu_sys_reg(vcpu, TCR_EL2), SYS_TCR); 103 write_sysreg_el1(__vcpu_sys_reg(vcpu, CNTHCTL_EL2), SYS_CNTKCTL); 104 } else { 105 /* 106 * CNTHCTL_EL2 only affects EL1 when running nVHE, so 107 * no need to restore it. 108 */ 109 val = translate_sctlr_el2_to_sctlr_el1(__vcpu_sys_reg(vcpu, SCTLR_EL2)); 110 write_sysreg_el1(val, SYS_SCTLR); 111 val = translate_cptr_el2_to_cpacr_el1(__vcpu_sys_reg(vcpu, CPTR_EL2)); 112 write_sysreg_el1(val, SYS_CPACR); 113 val = translate_ttbr0_el2_to_ttbr0_el1(__vcpu_sys_reg(vcpu, TTBR0_EL2)); 114 write_sysreg_el1(val, SYS_TTBR0); 115 val = translate_tcr_el2_to_tcr_el1(__vcpu_sys_reg(vcpu, TCR_EL2)); 116 write_sysreg_el1(val, SYS_TCR); 117 } 118 119 if (ctxt_has_tcrx(&vcpu->arch.ctxt)) { 120 write_sysreg_el1(__vcpu_sys_reg(vcpu, TCR2_EL2), SYS_TCR2); 121 122 if (ctxt_has_s1pie(&vcpu->arch.ctxt)) { 123 write_sysreg_el1(__vcpu_sys_reg(vcpu, PIR_EL2), SYS_PIR); 124 write_sysreg_el1(__vcpu_sys_reg(vcpu, PIRE0_EL2), SYS_PIRE0); 125 } 126 } 127 128 write_sysreg_el1(__vcpu_sys_reg(vcpu, ESR_EL2), SYS_ESR); 129 write_sysreg_el1(__vcpu_sys_reg(vcpu, AFSR0_EL2), SYS_AFSR0); 130 write_sysreg_el1(__vcpu_sys_reg(vcpu, AFSR1_EL2), SYS_AFSR1); 131 write_sysreg_el1(__vcpu_sys_reg(vcpu, FAR_EL2), SYS_FAR); 132 write_sysreg(__vcpu_sys_reg(vcpu, SP_EL2), sp_el1); 133 write_sysreg_el1(__vcpu_sys_reg(vcpu, ELR_EL2), SYS_ELR); 134 write_sysreg_el1(__vcpu_sys_reg(vcpu, SPSR_EL2), SYS_SPSR); 135 } 136 137 /* 138 * VHE: Host and guest must save mdscr_el1 and sp_el0 (and the PC and 139 * pstate, which are handled as part of the el2 return state) on every 140 * switch (sp_el0 is being dealt with in the assembly code). 141 * tpidr_el0 and tpidrro_el0 only need to be switched when going 142 * to host userspace or a different VCPU. EL1 registers only need to be 143 * switched when potentially going to run a different VCPU. The latter two 144 * classes are handled as part of kvm_arch_vcpu_load and kvm_arch_vcpu_put. 145 */ 146 147 void sysreg_save_host_state_vhe(struct kvm_cpu_context *ctxt) 148 { 149 __sysreg_save_common_state(ctxt); 150 } 151 NOKPROBE_SYMBOL(sysreg_save_host_state_vhe); 152 153 void sysreg_save_guest_state_vhe(struct kvm_cpu_context *ctxt) 154 { 155 __sysreg_save_common_state(ctxt); 156 __sysreg_save_el2_return_state(ctxt); 157 } 158 NOKPROBE_SYMBOL(sysreg_save_guest_state_vhe); 159 160 void sysreg_restore_host_state_vhe(struct kvm_cpu_context *ctxt) 161 { 162 __sysreg_restore_common_state(ctxt); 163 } 164 NOKPROBE_SYMBOL(sysreg_restore_host_state_vhe); 165 166 void sysreg_restore_guest_state_vhe(struct kvm_cpu_context *ctxt) 167 { 168 __sysreg_restore_common_state(ctxt); 169 __sysreg_restore_el2_return_state(ctxt); 170 } 171 NOKPROBE_SYMBOL(sysreg_restore_guest_state_vhe); 172 173 /** 174 * __vcpu_load_switch_sysregs - Load guest system registers to the physical CPU 175 * 176 * @vcpu: The VCPU pointer 177 * 178 * Load system registers that do not affect the host's execution, for 179 * example EL1 system registers on a VHE system where the host kernel 180 * runs at EL2. This function is called from KVM's vcpu_load() function 181 * and loading system register state early avoids having to load them on 182 * every entry to the VM. 183 */ 184 void __vcpu_load_switch_sysregs(struct kvm_vcpu *vcpu) 185 { 186 struct kvm_cpu_context *guest_ctxt = &vcpu->arch.ctxt; 187 struct kvm_cpu_context *host_ctxt; 188 u64 mpidr; 189 190 host_ctxt = host_data_ptr(host_ctxt); 191 __sysreg_save_user_state(host_ctxt); 192 193 /* 194 * When running a normal EL1 guest, we only load a new vcpu 195 * after a context switch, which imvolves a DSB, so all 196 * speculative EL1&0 walks will have already completed. 197 * If running NV, the vcpu may transition between vEL1 and 198 * vEL2 without a context switch, so make sure we complete 199 * those walks before loading a new context. 200 */ 201 if (vcpu_has_nv(vcpu)) 202 dsb(nsh); 203 204 /* 205 * Load guest EL1 and user state 206 * 207 * We must restore the 32-bit state before the sysregs, thanks 208 * to erratum #852523 (Cortex-A57) or #853709 (Cortex-A72). 209 */ 210 __sysreg32_restore_state(vcpu); 211 __sysreg_restore_user_state(guest_ctxt); 212 213 if (unlikely(__is_hyp_ctxt(guest_ctxt))) { 214 __sysreg_restore_vel2_state(vcpu); 215 } else { 216 if (vcpu_has_nv(vcpu)) { 217 /* 218 * Use the guest hypervisor's VPIDR_EL2 when in a 219 * nested state. The hardware value of MIDR_EL1 gets 220 * restored on put. 221 */ 222 write_sysreg(ctxt_sys_reg(guest_ctxt, VPIDR_EL2), vpidr_el2); 223 224 /* 225 * As we're restoring a nested guest, set the value 226 * provided by the guest hypervisor. 227 */ 228 mpidr = ctxt_sys_reg(guest_ctxt, VMPIDR_EL2); 229 } else { 230 mpidr = ctxt_sys_reg(guest_ctxt, MPIDR_EL1); 231 } 232 233 __sysreg_restore_el1_state(guest_ctxt, mpidr); 234 } 235 236 vcpu_set_flag(vcpu, SYSREGS_ON_CPU); 237 } 238 239 /** 240 * __vcpu_put_switch_sysregs - Restore host system registers to the physical CPU 241 * 242 * @vcpu: The VCPU pointer 243 * 244 * Save guest system registers that do not affect the host's execution, for 245 * example EL1 system registers on a VHE system where the host kernel 246 * runs at EL2. This function is called from KVM's vcpu_put() function 247 * and deferring saving system register state until we're no longer running the 248 * VCPU avoids having to save them on every exit from the VM. 249 */ 250 void __vcpu_put_switch_sysregs(struct kvm_vcpu *vcpu) 251 { 252 struct kvm_cpu_context *guest_ctxt = &vcpu->arch.ctxt; 253 struct kvm_cpu_context *host_ctxt; 254 255 host_ctxt = host_data_ptr(host_ctxt); 256 257 if (unlikely(__is_hyp_ctxt(guest_ctxt))) 258 __sysreg_save_vel2_state(vcpu); 259 else 260 __sysreg_save_el1_state(guest_ctxt); 261 262 __sysreg_save_user_state(guest_ctxt); 263 __sysreg32_save_state(vcpu); 264 265 /* Restore host user state */ 266 __sysreg_restore_user_state(host_ctxt); 267 268 /* If leaving a nesting guest, restore MIDR_EL1 default view */ 269 if (vcpu_has_nv(vcpu)) 270 write_sysreg(read_cpuid_id(), vpidr_el2); 271 272 vcpu_clear_flag(vcpu, SYSREGS_ON_CPU); 273 } 274