1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7 #include <hyp/switch.h> 8 9 #include <linux/arm-smccc.h> 10 #include <linux/kvm_host.h> 11 #include <linux/types.h> 12 #include <linux/jump_label.h> 13 #include <linux/percpu.h> 14 #include <uapi/linux/psci.h> 15 16 #include <kvm/arm_psci.h> 17 18 #include <asm/barrier.h> 19 #include <asm/cpufeature.h> 20 #include <asm/kprobes.h> 21 #include <asm/kvm_asm.h> 22 #include <asm/kvm_emulate.h> 23 #include <asm/kvm_hyp.h> 24 #include <asm/kvm_mmu.h> 25 #include <asm/fpsimd.h> 26 #include <asm/debug-monitors.h> 27 #include <asm/processor.h> 28 #include <asm/thread_info.h> 29 #include <asm/vectors.h> 30 31 /* VHE specific context */ 32 DEFINE_PER_CPU(struct kvm_host_data, kvm_host_data); 33 DEFINE_PER_CPU(struct kvm_cpu_context, kvm_hyp_ctxt); 34 DEFINE_PER_CPU(unsigned long, kvm_hyp_vector); 35 36 /* 37 * HCR_EL2 bits that the NV guest can freely change (no RES0/RES1 38 * semantics, irrespective of the configuration), but that cannot be 39 * applied to the actual HW as things would otherwise break badly. 40 * 41 * - TGE: we want the guest to use EL1, which is incompatible with 42 * this bit being set 43 * 44 * - API/APK: they are already accounted for by vcpu_load(), and can 45 * only take effect across a load/put cycle (such as ERET) 46 */ 47 #define NV_HCR_GUEST_EXCLUDE (HCR_TGE | HCR_API | HCR_APK) 48 49 static u64 __compute_hcr(struct kvm_vcpu *vcpu) 50 { 51 u64 hcr = vcpu->arch.hcr_el2; 52 53 if (!vcpu_has_nv(vcpu)) 54 return hcr; 55 56 if (is_hyp_ctxt(vcpu)) { 57 hcr |= HCR_NV | HCR_NV2 | HCR_AT | HCR_TTLB; 58 59 if (!vcpu_el2_e2h_is_set(vcpu)) 60 hcr |= HCR_NV1; 61 62 write_sysreg_s(vcpu->arch.ctxt.vncr_array, SYS_VNCR_EL2); 63 } 64 65 return hcr | (__vcpu_sys_reg(vcpu, HCR_EL2) & ~NV_HCR_GUEST_EXCLUDE); 66 } 67 68 static void __activate_traps(struct kvm_vcpu *vcpu) 69 { 70 u64 val; 71 72 ___activate_traps(vcpu, __compute_hcr(vcpu)); 73 74 if (has_cntpoff()) { 75 struct timer_map map; 76 77 get_timer_map(vcpu, &map); 78 79 /* 80 * We're entrering the guest. Reload the correct 81 * values from memory now that TGE is clear. 82 */ 83 if (map.direct_ptimer == vcpu_ptimer(vcpu)) 84 val = __vcpu_sys_reg(vcpu, CNTP_CVAL_EL0); 85 if (map.direct_ptimer == vcpu_hptimer(vcpu)) 86 val = __vcpu_sys_reg(vcpu, CNTHP_CVAL_EL2); 87 88 if (map.direct_ptimer) { 89 write_sysreg_el0(val, SYS_CNTP_CVAL); 90 isb(); 91 } 92 } 93 94 val = read_sysreg(cpacr_el1); 95 val |= CPACR_ELx_TTA; 96 val &= ~(CPACR_EL1_ZEN_EL0EN | CPACR_EL1_ZEN_EL1EN | 97 CPACR_EL1_SMEN_EL0EN | CPACR_EL1_SMEN_EL1EN); 98 99 /* 100 * With VHE (HCR.E2H == 1), accesses to CPACR_EL1 are routed to 101 * CPTR_EL2. In general, CPACR_EL1 has the same layout as CPTR_EL2, 102 * except for some missing controls, such as TAM. 103 * In this case, CPTR_EL2.TAM has the same position with or without 104 * VHE (HCR.E2H == 1) which allows us to use here the CPTR_EL2.TAM 105 * shift value for trapping the AMU accesses. 106 */ 107 108 val |= CPTR_EL2_TAM; 109 110 if (guest_owns_fp_regs()) { 111 if (vcpu_has_sve(vcpu)) 112 val |= CPACR_EL1_ZEN_EL0EN | CPACR_EL1_ZEN_EL1EN; 113 } else { 114 val &= ~(CPACR_EL1_FPEN_EL0EN | CPACR_EL1_FPEN_EL1EN); 115 __activate_traps_fpsimd32(vcpu); 116 } 117 118 write_sysreg(val, cpacr_el1); 119 120 write_sysreg(__this_cpu_read(kvm_hyp_vector), vbar_el1); 121 } 122 NOKPROBE_SYMBOL(__activate_traps); 123 124 static void __deactivate_traps(struct kvm_vcpu *vcpu) 125 { 126 const char *host_vectors = vectors; 127 128 ___deactivate_traps(vcpu); 129 130 write_sysreg(HCR_HOST_VHE_FLAGS, hcr_el2); 131 132 if (has_cntpoff()) { 133 struct timer_map map; 134 u64 val, offset; 135 136 get_timer_map(vcpu, &map); 137 138 /* 139 * We're exiting the guest. Save the latest CVAL value 140 * to memory and apply the offset now that TGE is set. 141 */ 142 val = read_sysreg_el0(SYS_CNTP_CVAL); 143 if (map.direct_ptimer == vcpu_ptimer(vcpu)) 144 __vcpu_sys_reg(vcpu, CNTP_CVAL_EL0) = val; 145 if (map.direct_ptimer == vcpu_hptimer(vcpu)) 146 __vcpu_sys_reg(vcpu, CNTHP_CVAL_EL2) = val; 147 148 offset = read_sysreg_s(SYS_CNTPOFF_EL2); 149 150 if (map.direct_ptimer && offset) { 151 write_sysreg_el0(val + offset, SYS_CNTP_CVAL); 152 isb(); 153 } 154 } 155 156 /* 157 * ARM errata 1165522 and 1530923 require the actual execution of the 158 * above before we can switch to the EL2/EL0 translation regime used by 159 * the host. 160 */ 161 asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT)); 162 163 kvm_reset_cptr_el2(vcpu); 164 165 if (!arm64_kernel_unmapped_at_el0()) 166 host_vectors = __this_cpu_read(this_cpu_vector); 167 write_sysreg(host_vectors, vbar_el1); 168 } 169 NOKPROBE_SYMBOL(__deactivate_traps); 170 171 /* 172 * Disable IRQs in __vcpu_{load,put}_{activate,deactivate}_traps() to 173 * prevent a race condition between context switching of PMUSERENR_EL0 174 * in __{activate,deactivate}_traps_common() and IPIs that attempts to 175 * update PMUSERENR_EL0. See also kvm_set_pmuserenr(). 176 */ 177 static void __vcpu_load_activate_traps(struct kvm_vcpu *vcpu) 178 { 179 unsigned long flags; 180 181 local_irq_save(flags); 182 __activate_traps_common(vcpu); 183 local_irq_restore(flags); 184 } 185 186 static void __vcpu_put_deactivate_traps(struct kvm_vcpu *vcpu) 187 { 188 unsigned long flags; 189 190 local_irq_save(flags); 191 __deactivate_traps_common(vcpu); 192 local_irq_restore(flags); 193 } 194 195 void kvm_vcpu_load_vhe(struct kvm_vcpu *vcpu) 196 { 197 host_data_ptr(host_ctxt)->__hyp_running_vcpu = vcpu; 198 199 __vcpu_load_switch_sysregs(vcpu); 200 __vcpu_load_activate_traps(vcpu); 201 __load_stage2(vcpu->arch.hw_mmu, vcpu->arch.hw_mmu->arch); 202 } 203 204 void kvm_vcpu_put_vhe(struct kvm_vcpu *vcpu) 205 { 206 __vcpu_put_deactivate_traps(vcpu); 207 __vcpu_put_switch_sysregs(vcpu); 208 209 host_data_ptr(host_ctxt)->__hyp_running_vcpu = NULL; 210 } 211 212 static bool kvm_hyp_handle_eret(struct kvm_vcpu *vcpu, u64 *exit_code) 213 { 214 u64 esr = kvm_vcpu_get_esr(vcpu); 215 u64 spsr, elr, mode; 216 217 /* 218 * Going through the whole put/load motions is a waste of time 219 * if this is a VHE guest hypervisor returning to its own 220 * userspace, or the hypervisor performing a local exception 221 * return. No need to save/restore registers, no need to 222 * switch S2 MMU. Just do the canonical ERET. 223 * 224 * Unless the trap has to be forwarded further down the line, 225 * of course... 226 */ 227 if ((__vcpu_sys_reg(vcpu, HCR_EL2) & HCR_NV) || 228 (__vcpu_sys_reg(vcpu, HFGITR_EL2) & HFGITR_EL2_ERET)) 229 return false; 230 231 spsr = read_sysreg_el1(SYS_SPSR); 232 mode = spsr & (PSR_MODE_MASK | PSR_MODE32_BIT); 233 234 switch (mode) { 235 case PSR_MODE_EL0t: 236 if (!(vcpu_el2_e2h_is_set(vcpu) && vcpu_el2_tge_is_set(vcpu))) 237 return false; 238 break; 239 case PSR_MODE_EL2t: 240 mode = PSR_MODE_EL1t; 241 break; 242 case PSR_MODE_EL2h: 243 mode = PSR_MODE_EL1h; 244 break; 245 default: 246 return false; 247 } 248 249 /* If ERETAx fails, take the slow path */ 250 if (esr_iss_is_eretax(esr)) { 251 if (!(vcpu_has_ptrauth(vcpu) && kvm_auth_eretax(vcpu, &elr))) 252 return false; 253 } else { 254 elr = read_sysreg_el1(SYS_ELR); 255 } 256 257 spsr = (spsr & ~(PSR_MODE_MASK | PSR_MODE32_BIT)) | mode; 258 259 write_sysreg_el2(spsr, SYS_SPSR); 260 write_sysreg_el2(elr, SYS_ELR); 261 262 return true; 263 } 264 265 static void kvm_hyp_save_fpsimd_host(struct kvm_vcpu *vcpu) 266 { 267 __fpsimd_save_state(*host_data_ptr(fpsimd_state)); 268 } 269 270 static const exit_handler_fn hyp_exit_handlers[] = { 271 [0 ... ESR_ELx_EC_MAX] = NULL, 272 [ESR_ELx_EC_CP15_32] = kvm_hyp_handle_cp15_32, 273 [ESR_ELx_EC_SYS64] = kvm_hyp_handle_sysreg, 274 [ESR_ELx_EC_SVE] = kvm_hyp_handle_fpsimd, 275 [ESR_ELx_EC_FP_ASIMD] = kvm_hyp_handle_fpsimd, 276 [ESR_ELx_EC_IABT_LOW] = kvm_hyp_handle_iabt_low, 277 [ESR_ELx_EC_DABT_LOW] = kvm_hyp_handle_dabt_low, 278 [ESR_ELx_EC_WATCHPT_LOW] = kvm_hyp_handle_watchpt_low, 279 [ESR_ELx_EC_ERET] = kvm_hyp_handle_eret, 280 [ESR_ELx_EC_MOPS] = kvm_hyp_handle_mops, 281 }; 282 283 static const exit_handler_fn *kvm_get_exit_handler_array(struct kvm_vcpu *vcpu) 284 { 285 return hyp_exit_handlers; 286 } 287 288 static void early_exit_filter(struct kvm_vcpu *vcpu, u64 *exit_code) 289 { 290 /* 291 * If we were in HYP context on entry, adjust the PSTATE view 292 * so that the usual helpers work correctly. 293 */ 294 if (vcpu_has_nv(vcpu) && (read_sysreg(hcr_el2) & HCR_NV)) { 295 u64 mode = *vcpu_cpsr(vcpu) & (PSR_MODE_MASK | PSR_MODE32_BIT); 296 297 switch (mode) { 298 case PSR_MODE_EL1t: 299 mode = PSR_MODE_EL2t; 300 break; 301 case PSR_MODE_EL1h: 302 mode = PSR_MODE_EL2h; 303 break; 304 } 305 306 *vcpu_cpsr(vcpu) &= ~(PSR_MODE_MASK | PSR_MODE32_BIT); 307 *vcpu_cpsr(vcpu) |= mode; 308 } 309 } 310 311 /* Switch to the guest for VHE systems running in EL2 */ 312 static int __kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu) 313 { 314 struct kvm_cpu_context *host_ctxt; 315 struct kvm_cpu_context *guest_ctxt; 316 u64 exit_code; 317 318 host_ctxt = host_data_ptr(host_ctxt); 319 guest_ctxt = &vcpu->arch.ctxt; 320 321 sysreg_save_host_state_vhe(host_ctxt); 322 323 /* 324 * Note that ARM erratum 1165522 requires us to configure both stage 1 325 * and stage 2 translation for the guest context before we clear 326 * HCR_EL2.TGE. The stage 1 and stage 2 guest context has already been 327 * loaded on the CPU in kvm_vcpu_load_vhe(). 328 */ 329 __activate_traps(vcpu); 330 331 __kvm_adjust_pc(vcpu); 332 333 sysreg_restore_guest_state_vhe(guest_ctxt); 334 __debug_switch_to_guest(vcpu); 335 336 do { 337 /* Jump in the fire! */ 338 exit_code = __guest_enter(vcpu); 339 340 /* And we're baaack! */ 341 } while (fixup_guest_exit(vcpu, &exit_code)); 342 343 sysreg_save_guest_state_vhe(guest_ctxt); 344 345 __deactivate_traps(vcpu); 346 347 sysreg_restore_host_state_vhe(host_ctxt); 348 349 if (guest_owns_fp_regs()) 350 __fpsimd_save_fpexc32(vcpu); 351 352 __debug_switch_to_host(vcpu); 353 354 return exit_code; 355 } 356 NOKPROBE_SYMBOL(__kvm_vcpu_run_vhe); 357 358 int __kvm_vcpu_run(struct kvm_vcpu *vcpu) 359 { 360 int ret; 361 362 local_daif_mask(); 363 364 /* 365 * Having IRQs masked via PMR when entering the guest means the GIC 366 * will not signal the CPU of interrupts of lower priority, and the 367 * only way to get out will be via guest exceptions. 368 * Naturally, we want to avoid this. 369 * 370 * local_daif_mask() already sets GIC_PRIO_PSR_I_SET, we just need a 371 * dsb to ensure the redistributor is forwards EL2 IRQs to the CPU. 372 */ 373 pmr_sync(); 374 375 ret = __kvm_vcpu_run_vhe(vcpu); 376 377 /* 378 * local_daif_restore() takes care to properly restore PSTATE.DAIF 379 * and the GIC PMR if the host is using IRQ priorities. 380 */ 381 local_daif_restore(DAIF_PROCCTX_NOIRQ); 382 383 /* 384 * When we exit from the guest we change a number of CPU configuration 385 * parameters, such as traps. We rely on the isb() in kvm_call_hyp*() 386 * to make sure these changes take effect before running the host or 387 * additional guests. 388 */ 389 return ret; 390 } 391 392 static void __hyp_call_panic(u64 spsr, u64 elr, u64 par) 393 { 394 struct kvm_cpu_context *host_ctxt; 395 struct kvm_vcpu *vcpu; 396 397 host_ctxt = host_data_ptr(host_ctxt); 398 vcpu = host_ctxt->__hyp_running_vcpu; 399 400 __deactivate_traps(vcpu); 401 sysreg_restore_host_state_vhe(host_ctxt); 402 403 panic("HYP panic:\nPS:%08llx PC:%016llx ESR:%08llx\nFAR:%016llx HPFAR:%016llx PAR:%016llx\nVCPU:%p\n", 404 spsr, elr, 405 read_sysreg_el2(SYS_ESR), read_sysreg_el2(SYS_FAR), 406 read_sysreg(hpfar_el2), par, vcpu); 407 } 408 NOKPROBE_SYMBOL(__hyp_call_panic); 409 410 void __noreturn hyp_panic(void) 411 { 412 u64 spsr = read_sysreg_el2(SYS_SPSR); 413 u64 elr = read_sysreg_el2(SYS_ELR); 414 u64 par = read_sysreg_par(); 415 416 __hyp_call_panic(spsr, elr, par); 417 unreachable(); 418 } 419 420 asmlinkage void kvm_unexpected_el2_exception(void) 421 { 422 __kvm_unexpected_el2_exception(); 423 } 424