1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7 #include <hyp/switch.h> 8 9 #include <linux/arm-smccc.h> 10 #include <linux/kvm_host.h> 11 #include <linux/types.h> 12 #include <linux/jump_label.h> 13 #include <linux/percpu.h> 14 #include <uapi/linux/psci.h> 15 16 #include <kvm/arm_psci.h> 17 18 #include <asm/barrier.h> 19 #include <asm/cpufeature.h> 20 #include <asm/kprobes.h> 21 #include <asm/kvm_asm.h> 22 #include <asm/kvm_emulate.h> 23 #include <asm/kvm_hyp.h> 24 #include <asm/kvm_mmu.h> 25 #include <asm/fpsimd.h> 26 #include <asm/debug-monitors.h> 27 #include <asm/processor.h> 28 #include <asm/thread_info.h> 29 #include <asm/vectors.h> 30 31 /* VHE specific context */ 32 DEFINE_PER_CPU(struct kvm_host_data, kvm_host_data); 33 DEFINE_PER_CPU(struct kvm_cpu_context, kvm_hyp_ctxt); 34 DEFINE_PER_CPU(unsigned long, kvm_hyp_vector); 35 36 static void __activate_traps(struct kvm_vcpu *vcpu) 37 { 38 u64 val; 39 40 ___activate_traps(vcpu); 41 42 val = read_sysreg(cpacr_el1); 43 val |= CPACR_ELx_TTA; 44 val &= ~(CPACR_EL1_ZEN_EL0EN | CPACR_EL1_ZEN_EL1EN | 45 CPACR_EL1_SMEN_EL0EN | CPACR_EL1_SMEN_EL1EN); 46 47 /* 48 * With VHE (HCR.E2H == 1), accesses to CPACR_EL1 are routed to 49 * CPTR_EL2. In general, CPACR_EL1 has the same layout as CPTR_EL2, 50 * except for some missing controls, such as TAM. 51 * In this case, CPTR_EL2.TAM has the same position with or without 52 * VHE (HCR.E2H == 1) which allows us to use here the CPTR_EL2.TAM 53 * shift value for trapping the AMU accesses. 54 */ 55 56 val |= CPTR_EL2_TAM; 57 58 if (guest_owns_fp_regs(vcpu)) { 59 if (vcpu_has_sve(vcpu)) 60 val |= CPACR_EL1_ZEN_EL0EN | CPACR_EL1_ZEN_EL1EN; 61 } else { 62 val &= ~(CPACR_EL1_FPEN_EL0EN | CPACR_EL1_FPEN_EL1EN); 63 __activate_traps_fpsimd32(vcpu); 64 } 65 66 write_sysreg(val, cpacr_el1); 67 68 write_sysreg(__this_cpu_read(kvm_hyp_vector), vbar_el1); 69 } 70 NOKPROBE_SYMBOL(__activate_traps); 71 72 static void __deactivate_traps(struct kvm_vcpu *vcpu) 73 { 74 const char *host_vectors = vectors; 75 76 ___deactivate_traps(vcpu); 77 78 write_sysreg(HCR_HOST_VHE_FLAGS, hcr_el2); 79 80 /* 81 * ARM errata 1165522 and 1530923 require the actual execution of the 82 * above before we can switch to the EL2/EL0 translation regime used by 83 * the host. 84 */ 85 asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT)); 86 87 kvm_reset_cptr_el2(vcpu); 88 89 if (!arm64_kernel_unmapped_at_el0()) 90 host_vectors = __this_cpu_read(this_cpu_vector); 91 write_sysreg(host_vectors, vbar_el1); 92 } 93 NOKPROBE_SYMBOL(__deactivate_traps); 94 95 /* 96 * Disable IRQs in {activate,deactivate}_traps_vhe_{load,put}() to 97 * prevent a race condition between context switching of PMUSERENR_EL0 98 * in __{activate,deactivate}_traps_common() and IPIs that attempts to 99 * update PMUSERENR_EL0. See also kvm_set_pmuserenr(). 100 */ 101 void activate_traps_vhe_load(struct kvm_vcpu *vcpu) 102 { 103 unsigned long flags; 104 105 local_irq_save(flags); 106 __activate_traps_common(vcpu); 107 local_irq_restore(flags); 108 } 109 110 void deactivate_traps_vhe_put(struct kvm_vcpu *vcpu) 111 { 112 unsigned long flags; 113 114 local_irq_save(flags); 115 __deactivate_traps_common(vcpu); 116 local_irq_restore(flags); 117 } 118 119 static const exit_handler_fn hyp_exit_handlers[] = { 120 [0 ... ESR_ELx_EC_MAX] = NULL, 121 [ESR_ELx_EC_CP15_32] = kvm_hyp_handle_cp15_32, 122 [ESR_ELx_EC_SYS64] = kvm_hyp_handle_sysreg, 123 [ESR_ELx_EC_SVE] = kvm_hyp_handle_fpsimd, 124 [ESR_ELx_EC_FP_ASIMD] = kvm_hyp_handle_fpsimd, 125 [ESR_ELx_EC_IABT_LOW] = kvm_hyp_handle_iabt_low, 126 [ESR_ELx_EC_DABT_LOW] = kvm_hyp_handle_dabt_low, 127 [ESR_ELx_EC_WATCHPT_LOW] = kvm_hyp_handle_watchpt_low, 128 [ESR_ELx_EC_PAC] = kvm_hyp_handle_ptrauth, 129 }; 130 131 static const exit_handler_fn *kvm_get_exit_handler_array(struct kvm_vcpu *vcpu) 132 { 133 return hyp_exit_handlers; 134 } 135 136 static void early_exit_filter(struct kvm_vcpu *vcpu, u64 *exit_code) 137 { 138 /* 139 * If we were in HYP context on entry, adjust the PSTATE view 140 * so that the usual helpers work correctly. 141 */ 142 if (unlikely(vcpu_get_flag(vcpu, VCPU_HYP_CONTEXT))) { 143 u64 mode = *vcpu_cpsr(vcpu) & (PSR_MODE_MASK | PSR_MODE32_BIT); 144 145 switch (mode) { 146 case PSR_MODE_EL1t: 147 mode = PSR_MODE_EL2t; 148 break; 149 case PSR_MODE_EL1h: 150 mode = PSR_MODE_EL2h; 151 break; 152 } 153 154 *vcpu_cpsr(vcpu) &= ~(PSR_MODE_MASK | PSR_MODE32_BIT); 155 *vcpu_cpsr(vcpu) |= mode; 156 } 157 } 158 159 /* Switch to the guest for VHE systems running in EL2 */ 160 static int __kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu) 161 { 162 struct kvm_cpu_context *host_ctxt; 163 struct kvm_cpu_context *guest_ctxt; 164 u64 exit_code; 165 166 host_ctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt; 167 host_ctxt->__hyp_running_vcpu = vcpu; 168 guest_ctxt = &vcpu->arch.ctxt; 169 170 sysreg_save_host_state_vhe(host_ctxt); 171 172 /* 173 * ARM erratum 1165522 requires us to configure both stage 1 and 174 * stage 2 translation for the guest context before we clear 175 * HCR_EL2.TGE. 176 * 177 * We have already configured the guest's stage 1 translation in 178 * kvm_vcpu_load_sysregs_vhe above. We must now call 179 * __load_stage2 before __activate_traps, because 180 * __load_stage2 configures stage 2 translation, and 181 * __activate_traps clear HCR_EL2.TGE (among other things). 182 */ 183 __load_stage2(vcpu->arch.hw_mmu, vcpu->arch.hw_mmu->arch); 184 __activate_traps(vcpu); 185 186 __kvm_adjust_pc(vcpu); 187 188 sysreg_restore_guest_state_vhe(guest_ctxt); 189 __debug_switch_to_guest(vcpu); 190 191 if (is_hyp_ctxt(vcpu)) 192 vcpu_set_flag(vcpu, VCPU_HYP_CONTEXT); 193 else 194 vcpu_clear_flag(vcpu, VCPU_HYP_CONTEXT); 195 196 do { 197 /* Jump in the fire! */ 198 exit_code = __guest_enter(vcpu); 199 200 /* And we're baaack! */ 201 } while (fixup_guest_exit(vcpu, &exit_code)); 202 203 sysreg_save_guest_state_vhe(guest_ctxt); 204 205 __deactivate_traps(vcpu); 206 207 sysreg_restore_host_state_vhe(host_ctxt); 208 209 if (vcpu->arch.fp_state == FP_STATE_GUEST_OWNED) 210 __fpsimd_save_fpexc32(vcpu); 211 212 __debug_switch_to_host(vcpu); 213 214 return exit_code; 215 } 216 NOKPROBE_SYMBOL(__kvm_vcpu_run_vhe); 217 218 int __kvm_vcpu_run(struct kvm_vcpu *vcpu) 219 { 220 int ret; 221 222 local_daif_mask(); 223 224 /* 225 * Having IRQs masked via PMR when entering the guest means the GIC 226 * will not signal the CPU of interrupts of lower priority, and the 227 * only way to get out will be via guest exceptions. 228 * Naturally, we want to avoid this. 229 * 230 * local_daif_mask() already sets GIC_PRIO_PSR_I_SET, we just need a 231 * dsb to ensure the redistributor is forwards EL2 IRQs to the CPU. 232 */ 233 pmr_sync(); 234 235 ret = __kvm_vcpu_run_vhe(vcpu); 236 237 /* 238 * local_daif_restore() takes care to properly restore PSTATE.DAIF 239 * and the GIC PMR if the host is using IRQ priorities. 240 */ 241 local_daif_restore(DAIF_PROCCTX_NOIRQ); 242 243 /* 244 * When we exit from the guest we change a number of CPU configuration 245 * parameters, such as traps. We rely on the isb() in kvm_call_hyp*() 246 * to make sure these changes take effect before running the host or 247 * additional guests. 248 */ 249 return ret; 250 } 251 252 static void __hyp_call_panic(u64 spsr, u64 elr, u64 par) 253 { 254 struct kvm_cpu_context *host_ctxt; 255 struct kvm_vcpu *vcpu; 256 257 host_ctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt; 258 vcpu = host_ctxt->__hyp_running_vcpu; 259 260 __deactivate_traps(vcpu); 261 sysreg_restore_host_state_vhe(host_ctxt); 262 263 panic("HYP panic:\nPS:%08llx PC:%016llx ESR:%08llx\nFAR:%016llx HPFAR:%016llx PAR:%016llx\nVCPU:%p\n", 264 spsr, elr, 265 read_sysreg_el2(SYS_ESR), read_sysreg_el2(SYS_FAR), 266 read_sysreg(hpfar_el2), par, vcpu); 267 } 268 NOKPROBE_SYMBOL(__hyp_call_panic); 269 270 void __noreturn hyp_panic(void) 271 { 272 u64 spsr = read_sysreg_el2(SYS_SPSR); 273 u64 elr = read_sysreg_el2(SYS_ELR); 274 u64 par = read_sysreg_par(); 275 276 __hyp_call_panic(spsr, elr, par); 277 unreachable(); 278 } 279 280 asmlinkage void kvm_unexpected_el2_exception(void) 281 { 282 __kvm_unexpected_el2_exception(); 283 } 284