1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7 #include <hyp/switch.h> 8 9 #include <linux/arm-smccc.h> 10 #include <linux/kvm_host.h> 11 #include <linux/types.h> 12 #include <linux/jump_label.h> 13 #include <linux/percpu.h> 14 #include <uapi/linux/psci.h> 15 16 #include <kvm/arm_psci.h> 17 18 #include <asm/barrier.h> 19 #include <asm/cpufeature.h> 20 #include <asm/kprobes.h> 21 #include <asm/kvm_asm.h> 22 #include <asm/kvm_emulate.h> 23 #include <asm/kvm_hyp.h> 24 #include <asm/kvm_mmu.h> 25 #include <asm/fpsimd.h> 26 #include <asm/debug-monitors.h> 27 #include <asm/processor.h> 28 #include <asm/thread_info.h> 29 #include <asm/vectors.h> 30 31 /* VHE specific context */ 32 DEFINE_PER_CPU(struct kvm_host_data, kvm_host_data); 33 DEFINE_PER_CPU(struct kvm_cpu_context, kvm_hyp_ctxt); 34 DEFINE_PER_CPU(unsigned long, kvm_hyp_vector); 35 36 /* 37 * HCR_EL2 bits that the NV guest can freely change (no RES0/RES1 38 * semantics, irrespective of the configuration), but that cannot be 39 * applied to the actual HW as things would otherwise break badly. 40 * 41 * - TGE: we want the guest to use EL1, which is incompatible with 42 * this bit being set 43 * 44 * - API/APK: they are already accounted for by vcpu_load(), and can 45 * only take effect across a load/put cycle (such as ERET) 46 * 47 * - FIEN: no way we let a guest have access to the RAS "Common Fault 48 * Injection" thing, whatever that does 49 */ 50 #define NV_HCR_GUEST_EXCLUDE (HCR_TGE | HCR_API | HCR_APK | HCR_FIEN) 51 52 static u64 __compute_hcr(struct kvm_vcpu *vcpu) 53 { 54 u64 guest_hcr, hcr = vcpu->arch.hcr_el2; 55 56 if (!vcpu_has_nv(vcpu)) 57 return hcr; 58 59 /* 60 * We rely on the invariant that a vcpu entered from HYP 61 * context must also exit in the same context, as only an ERET 62 * instruction can kick us out of it, and we obviously trap 63 * that sucker. PSTATE.M will get fixed-up on exit. 64 */ 65 if (is_hyp_ctxt(vcpu)) { 66 host_data_set_flag(VCPU_IN_HYP_CONTEXT); 67 68 hcr |= HCR_NV | HCR_NV2 | HCR_AT | HCR_TTLB; 69 70 if (!vcpu_el2_e2h_is_set(vcpu)) 71 hcr |= HCR_NV1; 72 73 /* 74 * Nothing in HCR_EL2 should impact running in hypervisor 75 * context, apart from bits we have defined as RESx (E2H, 76 * HCD and co), or that cannot be set directly (the EXCLUDE 77 * bits). Given that we OR the guest's view with the host's, 78 * we can use the 0 value as the starting point, and only 79 * use the config-driven RES1 bits. 80 */ 81 guest_hcr = kvm_vcpu_apply_reg_masks(vcpu, HCR_EL2, 0); 82 83 write_sysreg_s(vcpu->arch.ctxt.vncr_array, SYS_VNCR_EL2); 84 } else { 85 host_data_clear_flag(VCPU_IN_HYP_CONTEXT); 86 87 guest_hcr = __vcpu_sys_reg(vcpu, HCR_EL2); 88 if (guest_hcr & HCR_NV) { 89 u64 va = __fix_to_virt(vncr_fixmap(smp_processor_id())); 90 91 /* Inherit the low bits from the actual register */ 92 va |= __vcpu_sys_reg(vcpu, VNCR_EL2) & GENMASK(PAGE_SHIFT - 1, 0); 93 write_sysreg_s(va, SYS_VNCR_EL2); 94 95 /* Force NV2 in case the guest is forgetful... */ 96 guest_hcr |= HCR_NV2; 97 } 98 } 99 100 BUG_ON(host_data_test_flag(VCPU_IN_HYP_CONTEXT) && 101 host_data_test_flag(L1_VNCR_MAPPED)); 102 103 return hcr | (guest_hcr & ~NV_HCR_GUEST_EXCLUDE); 104 } 105 106 static void __activate_traps(struct kvm_vcpu *vcpu) 107 { 108 u64 val; 109 110 ___activate_traps(vcpu, __compute_hcr(vcpu)); 111 112 if (has_cntpoff()) { 113 struct timer_map map; 114 115 get_timer_map(vcpu, &map); 116 117 /* 118 * We're entrering the guest. Reload the correct 119 * values from memory now that TGE is clear. 120 */ 121 if (map.direct_ptimer == vcpu_ptimer(vcpu)) 122 val = __vcpu_sys_reg(vcpu, CNTP_CVAL_EL0); 123 if (map.direct_ptimer == vcpu_hptimer(vcpu)) 124 val = __vcpu_sys_reg(vcpu, CNTHP_CVAL_EL2); 125 126 if (map.direct_ptimer) { 127 write_sysreg_el0(val, SYS_CNTP_CVAL); 128 isb(); 129 } 130 } 131 132 __activate_cptr_traps(vcpu); 133 134 write_sysreg(__this_cpu_read(kvm_hyp_vector), vbar_el1); 135 } 136 NOKPROBE_SYMBOL(__activate_traps); 137 138 static void __deactivate_traps(struct kvm_vcpu *vcpu) 139 { 140 const char *host_vectors = vectors; 141 142 ___deactivate_traps(vcpu); 143 144 write_sysreg_hcr(HCR_HOST_VHE_FLAGS); 145 146 if (has_cntpoff()) { 147 struct timer_map map; 148 u64 val, offset; 149 150 get_timer_map(vcpu, &map); 151 152 /* 153 * We're exiting the guest. Save the latest CVAL value 154 * to memory and apply the offset now that TGE is set. 155 */ 156 val = read_sysreg_el0(SYS_CNTP_CVAL); 157 if (map.direct_ptimer == vcpu_ptimer(vcpu)) 158 __vcpu_assign_sys_reg(vcpu, CNTP_CVAL_EL0, val); 159 if (map.direct_ptimer == vcpu_hptimer(vcpu)) 160 __vcpu_assign_sys_reg(vcpu, CNTHP_CVAL_EL2, val); 161 162 offset = read_sysreg_s(SYS_CNTPOFF_EL2); 163 164 if (map.direct_ptimer && offset) { 165 write_sysreg_el0(val + offset, SYS_CNTP_CVAL); 166 isb(); 167 } 168 } 169 170 /* 171 * ARM errata 1165522 and 1530923 require the actual execution of the 172 * above before we can switch to the EL2/EL0 translation regime used by 173 * the host. 174 */ 175 asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT)); 176 177 __deactivate_cptr_traps(vcpu); 178 179 if (!arm64_kernel_unmapped_at_el0()) 180 host_vectors = __this_cpu_read(this_cpu_vector); 181 write_sysreg(host_vectors, vbar_el1); 182 } 183 NOKPROBE_SYMBOL(__deactivate_traps); 184 185 /* 186 * Disable IRQs in __vcpu_{load,put}_{activate,deactivate}_traps() to 187 * prevent a race condition between context switching of PMUSERENR_EL0 188 * in __{activate,deactivate}_traps_common() and IPIs that attempts to 189 * update PMUSERENR_EL0. See also kvm_set_pmuserenr(). 190 */ 191 static void __vcpu_load_activate_traps(struct kvm_vcpu *vcpu) 192 { 193 unsigned long flags; 194 195 local_irq_save(flags); 196 __activate_traps_common(vcpu); 197 local_irq_restore(flags); 198 } 199 200 static void __vcpu_put_deactivate_traps(struct kvm_vcpu *vcpu) 201 { 202 unsigned long flags; 203 204 local_irq_save(flags); 205 __deactivate_traps_common(vcpu); 206 local_irq_restore(flags); 207 } 208 209 void kvm_vcpu_load_vhe(struct kvm_vcpu *vcpu) 210 { 211 host_data_ptr(host_ctxt)->__hyp_running_vcpu = vcpu; 212 213 __vcpu_load_switch_sysregs(vcpu); 214 __vcpu_load_activate_traps(vcpu); 215 __load_stage2(vcpu->arch.hw_mmu, vcpu->arch.hw_mmu->arch); 216 } 217 218 void kvm_vcpu_put_vhe(struct kvm_vcpu *vcpu) 219 { 220 __vcpu_put_deactivate_traps(vcpu); 221 __vcpu_put_switch_sysregs(vcpu); 222 223 host_data_ptr(host_ctxt)->__hyp_running_vcpu = NULL; 224 } 225 226 static u64 compute_emulated_cntx_ctl_el0(struct kvm_vcpu *vcpu, 227 enum vcpu_sysreg reg) 228 { 229 unsigned long ctl; 230 u64 cval, cnt; 231 bool stat; 232 233 switch (reg) { 234 case CNTP_CTL_EL0: 235 cval = __vcpu_sys_reg(vcpu, CNTP_CVAL_EL0); 236 ctl = __vcpu_sys_reg(vcpu, CNTP_CTL_EL0); 237 cnt = compute_counter_value(vcpu_ptimer(vcpu)); 238 break; 239 case CNTV_CTL_EL0: 240 cval = __vcpu_sys_reg(vcpu, CNTV_CVAL_EL0); 241 ctl = __vcpu_sys_reg(vcpu, CNTV_CTL_EL0); 242 cnt = compute_counter_value(vcpu_vtimer(vcpu)); 243 break; 244 default: 245 BUG(); 246 } 247 248 stat = cval <= cnt; 249 __assign_bit(__ffs(ARCH_TIMER_CTRL_IT_STAT), &ctl, stat); 250 251 return ctl; 252 } 253 254 static bool kvm_hyp_handle_timer(struct kvm_vcpu *vcpu, u64 *exit_code) 255 { 256 u64 esr, val; 257 258 /* 259 * Having FEAT_ECV allows for a better quality of timer emulation. 260 * However, this comes at a huge cost in terms of traps. Try and 261 * satisfy the reads from guest's hypervisor context without 262 * returning to the kernel if we can. 263 */ 264 if (!is_hyp_ctxt(vcpu)) 265 return false; 266 267 esr = kvm_vcpu_get_esr(vcpu); 268 if ((esr & ESR_ELx_SYS64_ISS_DIR_MASK) != ESR_ELx_SYS64_ISS_DIR_READ) 269 return false; 270 271 switch (esr_sys64_to_sysreg(esr)) { 272 case SYS_CNTP_CTL_EL02: 273 val = compute_emulated_cntx_ctl_el0(vcpu, CNTP_CTL_EL0); 274 break; 275 case SYS_CNTP_CTL_EL0: 276 if (vcpu_el2_e2h_is_set(vcpu)) 277 val = read_sysreg_el0(SYS_CNTP_CTL); 278 else 279 val = compute_emulated_cntx_ctl_el0(vcpu, CNTP_CTL_EL0); 280 break; 281 case SYS_CNTP_CVAL_EL02: 282 val = __vcpu_sys_reg(vcpu, CNTP_CVAL_EL0); 283 break; 284 case SYS_CNTP_CVAL_EL0: 285 if (vcpu_el2_e2h_is_set(vcpu)) { 286 val = read_sysreg_el0(SYS_CNTP_CVAL); 287 288 if (!has_cntpoff()) 289 val -= timer_get_offset(vcpu_hptimer(vcpu)); 290 } else { 291 val = __vcpu_sys_reg(vcpu, CNTP_CVAL_EL0); 292 } 293 break; 294 case SYS_CNTPCT_EL0: 295 case SYS_CNTPCTSS_EL0: 296 val = compute_counter_value(vcpu_hptimer(vcpu)); 297 break; 298 case SYS_CNTV_CTL_EL02: 299 val = compute_emulated_cntx_ctl_el0(vcpu, CNTV_CTL_EL0); 300 break; 301 case SYS_CNTV_CTL_EL0: 302 if (vcpu_el2_e2h_is_set(vcpu)) 303 val = read_sysreg_el0(SYS_CNTV_CTL); 304 else 305 val = compute_emulated_cntx_ctl_el0(vcpu, CNTV_CTL_EL0); 306 break; 307 case SYS_CNTV_CVAL_EL02: 308 val = __vcpu_sys_reg(vcpu, CNTV_CVAL_EL0); 309 break; 310 case SYS_CNTV_CVAL_EL0: 311 if (vcpu_el2_e2h_is_set(vcpu)) 312 val = read_sysreg_el0(SYS_CNTV_CVAL); 313 else 314 val = __vcpu_sys_reg(vcpu, CNTV_CVAL_EL0); 315 break; 316 case SYS_CNTVCT_EL0: 317 case SYS_CNTVCTSS_EL0: 318 val = compute_counter_value(vcpu_hvtimer(vcpu)); 319 break; 320 default: 321 return false; 322 } 323 324 vcpu_set_reg(vcpu, kvm_vcpu_sys_get_rt(vcpu), val); 325 __kvm_skip_instr(vcpu); 326 327 return true; 328 } 329 330 static bool kvm_hyp_handle_eret(struct kvm_vcpu *vcpu, u64 *exit_code) 331 { 332 u64 esr = kvm_vcpu_get_esr(vcpu); 333 u64 spsr, elr, mode; 334 335 /* 336 * Going through the whole put/load motions is a waste of time 337 * if this is a VHE guest hypervisor returning to its own 338 * userspace, or the hypervisor performing a local exception 339 * return. No need to save/restore registers, no need to 340 * switch S2 MMU. Just do the canonical ERET. 341 * 342 * Unless the trap has to be forwarded further down the line, 343 * of course... 344 */ 345 if ((__vcpu_sys_reg(vcpu, HCR_EL2) & HCR_NV) || 346 (__vcpu_sys_reg(vcpu, HFGITR_EL2) & HFGITR_EL2_ERET)) 347 return false; 348 349 spsr = read_sysreg_el1(SYS_SPSR); 350 mode = spsr & (PSR_MODE_MASK | PSR_MODE32_BIT); 351 352 switch (mode) { 353 case PSR_MODE_EL0t: 354 if (!(vcpu_el2_e2h_is_set(vcpu) && vcpu_el2_tge_is_set(vcpu))) 355 return false; 356 break; 357 case PSR_MODE_EL2t: 358 mode = PSR_MODE_EL1t; 359 break; 360 case PSR_MODE_EL2h: 361 mode = PSR_MODE_EL1h; 362 break; 363 default: 364 return false; 365 } 366 367 /* If ERETAx fails, take the slow path */ 368 if (esr_iss_is_eretax(esr)) { 369 if (!(vcpu_has_ptrauth(vcpu) && kvm_auth_eretax(vcpu, &elr))) 370 return false; 371 } else { 372 elr = read_sysreg_el1(SYS_ELR); 373 } 374 375 spsr = (spsr & ~(PSR_MODE_MASK | PSR_MODE32_BIT)) | mode; 376 377 write_sysreg_el2(spsr, SYS_SPSR); 378 write_sysreg_el2(elr, SYS_ELR); 379 380 return true; 381 } 382 383 static bool kvm_hyp_handle_tlbi_el2(struct kvm_vcpu *vcpu, u64 *exit_code) 384 { 385 int ret = -EINVAL; 386 u32 instr; 387 u64 val; 388 389 /* 390 * Ideally, we would never trap on EL2 S1 TLB invalidations using 391 * the EL1 instructions when the guest's HCR_EL2.{E2H,TGE}=={1,1}. 392 * But "thanks" to FEAT_NV2, we don't trap writes to HCR_EL2, 393 * meaning that we can't track changes to the virtual TGE bit. So we 394 * have to leave HCR_EL2.TTLB set on the host. Oopsie... 395 * 396 * Try and handle these invalidation as quickly as possible, without 397 * fully exiting. Note that we don't need to consider any forwarding 398 * here, as having E2H+TGE set is the very definition of being 399 * InHost. 400 * 401 * For the lesser hypervisors out there that have failed to get on 402 * with the VHE program, we can also handle the nVHE style of EL2 403 * invalidation. 404 */ 405 if (!(is_hyp_ctxt(vcpu))) 406 return false; 407 408 instr = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu)); 409 val = vcpu_get_reg(vcpu, kvm_vcpu_sys_get_rt(vcpu)); 410 411 if ((kvm_supported_tlbi_s1e1_op(vcpu, instr) && 412 vcpu_el2_e2h_is_set(vcpu) && vcpu_el2_tge_is_set(vcpu)) || 413 kvm_supported_tlbi_s1e2_op (vcpu, instr)) 414 ret = __kvm_tlbi_s1e2(NULL, val, instr); 415 416 if (ret) 417 return false; 418 419 /* 420 * If we have to check for any VNCR mapping being invalidated, 421 * go back to the slow path for further processing. 422 */ 423 if (vcpu_el2_e2h_is_set(vcpu) && vcpu_el2_tge_is_set(vcpu) && 424 atomic_read(&vcpu->kvm->arch.vncr_map_count)) 425 return false; 426 427 __kvm_skip_instr(vcpu); 428 429 return true; 430 } 431 432 static bool kvm_hyp_handle_cpacr_el1(struct kvm_vcpu *vcpu, u64 *exit_code) 433 { 434 u64 esr = kvm_vcpu_get_esr(vcpu); 435 int rt; 436 437 if (!is_hyp_ctxt(vcpu) || esr_sys64_to_sysreg(esr) != SYS_CPACR_EL1) 438 return false; 439 440 rt = kvm_vcpu_sys_get_rt(vcpu); 441 442 if ((esr & ESR_ELx_SYS64_ISS_DIR_MASK) == ESR_ELx_SYS64_ISS_DIR_READ) { 443 vcpu_set_reg(vcpu, rt, __vcpu_sys_reg(vcpu, CPTR_EL2)); 444 } else { 445 vcpu_write_sys_reg(vcpu, vcpu_get_reg(vcpu, rt), CPTR_EL2); 446 __activate_cptr_traps(vcpu); 447 } 448 449 __kvm_skip_instr(vcpu); 450 451 return true; 452 } 453 454 static bool kvm_hyp_handle_zcr_el2(struct kvm_vcpu *vcpu, u64 *exit_code) 455 { 456 u32 sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu)); 457 458 if (!vcpu_has_nv(vcpu)) 459 return false; 460 461 if (sysreg != SYS_ZCR_EL2) 462 return false; 463 464 if (guest_owns_fp_regs()) 465 return false; 466 467 /* 468 * ZCR_EL2 traps are handled in the slow path, with the expectation 469 * that the guest's FP context has already been loaded onto the CPU. 470 * 471 * Load the guest's FP context and unconditionally forward to the 472 * slow path for handling (i.e. return false). 473 */ 474 kvm_hyp_handle_fpsimd(vcpu, exit_code); 475 return false; 476 } 477 478 static bool kvm_hyp_handle_sysreg_vhe(struct kvm_vcpu *vcpu, u64 *exit_code) 479 { 480 if (kvm_hyp_handle_tlbi_el2(vcpu, exit_code)) 481 return true; 482 483 if (kvm_hyp_handle_timer(vcpu, exit_code)) 484 return true; 485 486 if (kvm_hyp_handle_cpacr_el1(vcpu, exit_code)) 487 return true; 488 489 if (kvm_hyp_handle_zcr_el2(vcpu, exit_code)) 490 return true; 491 492 return kvm_hyp_handle_sysreg(vcpu, exit_code); 493 } 494 495 static bool kvm_hyp_handle_impdef(struct kvm_vcpu *vcpu, u64 *exit_code) 496 { 497 u64 iss; 498 499 if (!cpus_have_final_cap(ARM64_WORKAROUND_PMUV3_IMPDEF_TRAPS)) 500 return false; 501 502 /* 503 * Compute a synthetic ESR for a sysreg trap. Conveniently, AFSR1_EL2 504 * is populated with a correct ISS for a sysreg trap. These fruity 505 * parts are 64bit only, so unconditionally set IL. 506 */ 507 iss = ESR_ELx_ISS(read_sysreg_s(SYS_AFSR1_EL2)); 508 vcpu->arch.fault.esr_el2 = FIELD_PREP(ESR_ELx_EC_MASK, ESR_ELx_EC_SYS64) | 509 FIELD_PREP(ESR_ELx_ISS_MASK, iss) | 510 ESR_ELx_IL; 511 return false; 512 } 513 514 static const exit_handler_fn hyp_exit_handlers[] = { 515 [0 ... ESR_ELx_EC_MAX] = NULL, 516 [ESR_ELx_EC_CP15_32] = kvm_hyp_handle_cp15_32, 517 [ESR_ELx_EC_SYS64] = kvm_hyp_handle_sysreg_vhe, 518 [ESR_ELx_EC_SVE] = kvm_hyp_handle_fpsimd, 519 [ESR_ELx_EC_FP_ASIMD] = kvm_hyp_handle_fpsimd, 520 [ESR_ELx_EC_IABT_LOW] = kvm_hyp_handle_iabt_low, 521 [ESR_ELx_EC_DABT_LOW] = kvm_hyp_handle_dabt_low, 522 [ESR_ELx_EC_WATCHPT_LOW] = kvm_hyp_handle_watchpt_low, 523 [ESR_ELx_EC_ERET] = kvm_hyp_handle_eret, 524 [ESR_ELx_EC_MOPS] = kvm_hyp_handle_mops, 525 526 /* Apple shenanigans */ 527 [0x3F] = kvm_hyp_handle_impdef, 528 }; 529 530 static inline bool fixup_guest_exit(struct kvm_vcpu *vcpu, u64 *exit_code) 531 { 532 synchronize_vcpu_pstate(vcpu, exit_code); 533 534 /* 535 * If we were in HYP context on entry, adjust the PSTATE view 536 * so that the usual helpers work correctly. This enforces our 537 * invariant that the guest's HYP context status is preserved 538 * across a run. 539 */ 540 if (vcpu_has_nv(vcpu) && 541 unlikely(host_data_test_flag(VCPU_IN_HYP_CONTEXT))) { 542 u64 mode = *vcpu_cpsr(vcpu) & (PSR_MODE_MASK | PSR_MODE32_BIT); 543 544 switch (mode) { 545 case PSR_MODE_EL1t: 546 mode = PSR_MODE_EL2t; 547 break; 548 case PSR_MODE_EL1h: 549 mode = PSR_MODE_EL2h; 550 break; 551 } 552 553 *vcpu_cpsr(vcpu) &= ~(PSR_MODE_MASK | PSR_MODE32_BIT); 554 *vcpu_cpsr(vcpu) |= mode; 555 } 556 557 /* Apply extreme paranoia! */ 558 BUG_ON(vcpu_has_nv(vcpu) && 559 !!host_data_test_flag(VCPU_IN_HYP_CONTEXT) != is_hyp_ctxt(vcpu)); 560 561 return __fixup_guest_exit(vcpu, exit_code, hyp_exit_handlers); 562 } 563 564 /* Switch to the guest for VHE systems running in EL2 */ 565 static int __kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu) 566 { 567 struct kvm_cpu_context *host_ctxt; 568 struct kvm_cpu_context *guest_ctxt; 569 u64 exit_code; 570 571 host_ctxt = host_data_ptr(host_ctxt); 572 guest_ctxt = &vcpu->arch.ctxt; 573 574 fpsimd_lazy_switch_to_guest(vcpu); 575 576 sysreg_save_host_state_vhe(host_ctxt); 577 578 /* 579 * Note that ARM erratum 1165522 requires us to configure both stage 1 580 * and stage 2 translation for the guest context before we clear 581 * HCR_EL2.TGE. The stage 1 and stage 2 guest context has already been 582 * loaded on the CPU in kvm_vcpu_load_vhe(). 583 */ 584 __activate_traps(vcpu); 585 586 __kvm_adjust_pc(vcpu); 587 588 sysreg_restore_guest_state_vhe(guest_ctxt); 589 __debug_switch_to_guest(vcpu); 590 591 do { 592 /* Jump in the fire! */ 593 exit_code = __guest_enter(vcpu); 594 595 /* And we're baaack! */ 596 } while (fixup_guest_exit(vcpu, &exit_code)); 597 598 sysreg_save_guest_state_vhe(guest_ctxt); 599 600 __deactivate_traps(vcpu); 601 602 sysreg_restore_host_state_vhe(host_ctxt); 603 604 __debug_switch_to_host(vcpu); 605 606 /* 607 * Ensure that all system register writes above have taken effect 608 * before returning to the host. In VHE mode, CPTR traps for 609 * FPSIMD/SVE/SME also apply to EL2, so FPSIMD/SVE/SME state must be 610 * manipulated after the ISB. 611 */ 612 isb(); 613 614 fpsimd_lazy_switch_to_host(vcpu); 615 616 if (guest_owns_fp_regs()) 617 __fpsimd_save_fpexc32(vcpu); 618 619 return exit_code; 620 } 621 NOKPROBE_SYMBOL(__kvm_vcpu_run_vhe); 622 623 int __kvm_vcpu_run(struct kvm_vcpu *vcpu) 624 { 625 int ret; 626 627 local_daif_mask(); 628 629 /* 630 * Having IRQs masked via PMR when entering the guest means the GIC 631 * will not signal the CPU of interrupts of lower priority, and the 632 * only way to get out will be via guest exceptions. 633 * Naturally, we want to avoid this. 634 * 635 * local_daif_mask() already sets GIC_PRIO_PSR_I_SET, we just need a 636 * dsb to ensure the redistributor is forwards EL2 IRQs to the CPU. 637 */ 638 pmr_sync(); 639 640 ret = __kvm_vcpu_run_vhe(vcpu); 641 642 /* 643 * local_daif_restore() takes care to properly restore PSTATE.DAIF 644 * and the GIC PMR if the host is using IRQ priorities. 645 */ 646 local_daif_restore(DAIF_PROCCTX_NOIRQ); 647 648 return ret; 649 } 650 651 static void __noreturn __hyp_call_panic(u64 spsr, u64 elr, u64 par) 652 { 653 struct kvm_cpu_context *host_ctxt; 654 struct kvm_vcpu *vcpu; 655 656 host_ctxt = host_data_ptr(host_ctxt); 657 vcpu = host_ctxt->__hyp_running_vcpu; 658 659 __deactivate_traps(vcpu); 660 sysreg_restore_host_state_vhe(host_ctxt); 661 662 panic("HYP panic:\nPS:%08llx PC:%016llx ESR:%08llx\nFAR:%016llx HPFAR:%016llx PAR:%016llx\nVCPU:%p\n", 663 spsr, elr, 664 read_sysreg_el2(SYS_ESR), read_sysreg_el2(SYS_FAR), 665 read_sysreg(hpfar_el2), par, vcpu); 666 } 667 NOKPROBE_SYMBOL(__hyp_call_panic); 668 669 void __noreturn hyp_panic(void) 670 { 671 u64 spsr = read_sysreg_el2(SYS_SPSR); 672 u64 elr = read_sysreg_el2(SYS_ELR); 673 u64 par = read_sysreg_par(); 674 675 __hyp_call_panic(spsr, elr, par); 676 } 677 678 asmlinkage void kvm_unexpected_el2_exception(void) 679 { 680 __kvm_unexpected_el2_exception(); 681 } 682