1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7 #include <hyp/switch.h> 8 9 #include <linux/arm-smccc.h> 10 #include <linux/kvm_host.h> 11 #include <linux/types.h> 12 #include <linux/jump_label.h> 13 #include <linux/percpu.h> 14 #include <uapi/linux/psci.h> 15 16 #include <kvm/arm_psci.h> 17 18 #include <asm/barrier.h> 19 #include <asm/cpufeature.h> 20 #include <asm/kprobes.h> 21 #include <asm/kvm_asm.h> 22 #include <asm/kvm_emulate.h> 23 #include <asm/kvm_hyp.h> 24 #include <asm/kvm_mmu.h> 25 #include <asm/fpsimd.h> 26 #include <asm/debug-monitors.h> 27 #include <asm/processor.h> 28 #include <asm/thread_info.h> 29 #include <asm/vectors.h> 30 31 /* VHE specific context */ 32 DEFINE_PER_CPU(struct kvm_host_data, kvm_host_data); 33 DEFINE_PER_CPU(struct kvm_cpu_context, kvm_hyp_ctxt); 34 DEFINE_PER_CPU(unsigned long, kvm_hyp_vector); 35 36 /* 37 * HCR_EL2 bits that the NV guest can freely change (no RES0/RES1 38 * semantics, irrespective of the configuration), but that cannot be 39 * applied to the actual HW as things would otherwise break badly. 40 * 41 * - TGE: we want the guest to use EL1, which is incompatible with 42 * this bit being set 43 * 44 * - API/APK: they are already accounted for by vcpu_load(), and can 45 * only take effect across a load/put cycle (such as ERET) 46 */ 47 #define NV_HCR_GUEST_EXCLUDE (HCR_TGE | HCR_API | HCR_APK) 48 49 static u64 __compute_hcr(struct kvm_vcpu *vcpu) 50 { 51 u64 hcr = vcpu->arch.hcr_el2; 52 53 if (!vcpu_has_nv(vcpu)) 54 return hcr; 55 56 if (is_hyp_ctxt(vcpu)) { 57 hcr |= HCR_NV | HCR_NV2 | HCR_AT | HCR_TTLB; 58 59 if (!vcpu_el2_e2h_is_set(vcpu)) 60 hcr |= HCR_NV1; 61 62 write_sysreg_s(vcpu->arch.ctxt.vncr_array, SYS_VNCR_EL2); 63 } 64 65 return hcr | (__vcpu_sys_reg(vcpu, HCR_EL2) & ~NV_HCR_GUEST_EXCLUDE); 66 } 67 68 static void __activate_traps(struct kvm_vcpu *vcpu) 69 { 70 u64 val; 71 72 ___activate_traps(vcpu, __compute_hcr(vcpu)); 73 74 if (has_cntpoff()) { 75 struct timer_map map; 76 77 get_timer_map(vcpu, &map); 78 79 /* 80 * We're entrering the guest. Reload the correct 81 * values from memory now that TGE is clear. 82 */ 83 if (map.direct_ptimer == vcpu_ptimer(vcpu)) 84 val = __vcpu_sys_reg(vcpu, CNTP_CVAL_EL0); 85 if (map.direct_ptimer == vcpu_hptimer(vcpu)) 86 val = __vcpu_sys_reg(vcpu, CNTHP_CVAL_EL2); 87 88 if (map.direct_ptimer) { 89 write_sysreg_el0(val, SYS_CNTP_CVAL); 90 isb(); 91 } 92 } 93 94 val = read_sysreg(cpacr_el1); 95 val |= CPACR_ELx_TTA; 96 val &= ~(CPACR_ELx_ZEN | CPACR_ELx_SMEN); 97 98 /* 99 * With VHE (HCR.E2H == 1), accesses to CPACR_EL1 are routed to 100 * CPTR_EL2. In general, CPACR_EL1 has the same layout as CPTR_EL2, 101 * except for some missing controls, such as TAM. 102 * In this case, CPTR_EL2.TAM has the same position with or without 103 * VHE (HCR.E2H == 1) which allows us to use here the CPTR_EL2.TAM 104 * shift value for trapping the AMU accesses. 105 */ 106 107 val |= CPTR_EL2_TAM; 108 109 if (guest_owns_fp_regs()) { 110 if (vcpu_has_sve(vcpu)) 111 val |= CPACR_ELx_ZEN; 112 } else { 113 val &= ~CPACR_ELx_FPEN; 114 __activate_traps_fpsimd32(vcpu); 115 } 116 117 write_sysreg(val, cpacr_el1); 118 119 write_sysreg(__this_cpu_read(kvm_hyp_vector), vbar_el1); 120 } 121 NOKPROBE_SYMBOL(__activate_traps); 122 123 static void __deactivate_traps(struct kvm_vcpu *vcpu) 124 { 125 const char *host_vectors = vectors; 126 127 ___deactivate_traps(vcpu); 128 129 write_sysreg(HCR_HOST_VHE_FLAGS, hcr_el2); 130 131 if (has_cntpoff()) { 132 struct timer_map map; 133 u64 val, offset; 134 135 get_timer_map(vcpu, &map); 136 137 /* 138 * We're exiting the guest. Save the latest CVAL value 139 * to memory and apply the offset now that TGE is set. 140 */ 141 val = read_sysreg_el0(SYS_CNTP_CVAL); 142 if (map.direct_ptimer == vcpu_ptimer(vcpu)) 143 __vcpu_sys_reg(vcpu, CNTP_CVAL_EL0) = val; 144 if (map.direct_ptimer == vcpu_hptimer(vcpu)) 145 __vcpu_sys_reg(vcpu, CNTHP_CVAL_EL2) = val; 146 147 offset = read_sysreg_s(SYS_CNTPOFF_EL2); 148 149 if (map.direct_ptimer && offset) { 150 write_sysreg_el0(val + offset, SYS_CNTP_CVAL); 151 isb(); 152 } 153 } 154 155 /* 156 * ARM errata 1165522 and 1530923 require the actual execution of the 157 * above before we can switch to the EL2/EL0 translation regime used by 158 * the host. 159 */ 160 asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT)); 161 162 kvm_reset_cptr_el2(vcpu); 163 164 if (!arm64_kernel_unmapped_at_el0()) 165 host_vectors = __this_cpu_read(this_cpu_vector); 166 write_sysreg(host_vectors, vbar_el1); 167 } 168 NOKPROBE_SYMBOL(__deactivate_traps); 169 170 /* 171 * Disable IRQs in __vcpu_{load,put}_{activate,deactivate}_traps() to 172 * prevent a race condition between context switching of PMUSERENR_EL0 173 * in __{activate,deactivate}_traps_common() and IPIs that attempts to 174 * update PMUSERENR_EL0. See also kvm_set_pmuserenr(). 175 */ 176 static void __vcpu_load_activate_traps(struct kvm_vcpu *vcpu) 177 { 178 unsigned long flags; 179 180 local_irq_save(flags); 181 __activate_traps_common(vcpu); 182 local_irq_restore(flags); 183 } 184 185 static void __vcpu_put_deactivate_traps(struct kvm_vcpu *vcpu) 186 { 187 unsigned long flags; 188 189 local_irq_save(flags); 190 __deactivate_traps_common(vcpu); 191 local_irq_restore(flags); 192 } 193 194 void kvm_vcpu_load_vhe(struct kvm_vcpu *vcpu) 195 { 196 host_data_ptr(host_ctxt)->__hyp_running_vcpu = vcpu; 197 198 __vcpu_load_switch_sysregs(vcpu); 199 __vcpu_load_activate_traps(vcpu); 200 __load_stage2(vcpu->arch.hw_mmu, vcpu->arch.hw_mmu->arch); 201 } 202 203 void kvm_vcpu_put_vhe(struct kvm_vcpu *vcpu) 204 { 205 __vcpu_put_deactivate_traps(vcpu); 206 __vcpu_put_switch_sysregs(vcpu); 207 208 host_data_ptr(host_ctxt)->__hyp_running_vcpu = NULL; 209 } 210 211 static bool kvm_hyp_handle_eret(struct kvm_vcpu *vcpu, u64 *exit_code) 212 { 213 u64 esr = kvm_vcpu_get_esr(vcpu); 214 u64 spsr, elr, mode; 215 216 /* 217 * Going through the whole put/load motions is a waste of time 218 * if this is a VHE guest hypervisor returning to its own 219 * userspace, or the hypervisor performing a local exception 220 * return. No need to save/restore registers, no need to 221 * switch S2 MMU. Just do the canonical ERET. 222 * 223 * Unless the trap has to be forwarded further down the line, 224 * of course... 225 */ 226 if ((__vcpu_sys_reg(vcpu, HCR_EL2) & HCR_NV) || 227 (__vcpu_sys_reg(vcpu, HFGITR_EL2) & HFGITR_EL2_ERET)) 228 return false; 229 230 spsr = read_sysreg_el1(SYS_SPSR); 231 mode = spsr & (PSR_MODE_MASK | PSR_MODE32_BIT); 232 233 switch (mode) { 234 case PSR_MODE_EL0t: 235 if (!(vcpu_el2_e2h_is_set(vcpu) && vcpu_el2_tge_is_set(vcpu))) 236 return false; 237 break; 238 case PSR_MODE_EL2t: 239 mode = PSR_MODE_EL1t; 240 break; 241 case PSR_MODE_EL2h: 242 mode = PSR_MODE_EL1h; 243 break; 244 default: 245 return false; 246 } 247 248 /* If ERETAx fails, take the slow path */ 249 if (esr_iss_is_eretax(esr)) { 250 if (!(vcpu_has_ptrauth(vcpu) && kvm_auth_eretax(vcpu, &elr))) 251 return false; 252 } else { 253 elr = read_sysreg_el1(SYS_ELR); 254 } 255 256 spsr = (spsr & ~(PSR_MODE_MASK | PSR_MODE32_BIT)) | mode; 257 258 write_sysreg_el2(spsr, SYS_SPSR); 259 write_sysreg_el2(elr, SYS_ELR); 260 261 return true; 262 } 263 264 static void kvm_hyp_save_fpsimd_host(struct kvm_vcpu *vcpu) 265 { 266 __fpsimd_save_state(*host_data_ptr(fpsimd_state)); 267 } 268 269 static const exit_handler_fn hyp_exit_handlers[] = { 270 [0 ... ESR_ELx_EC_MAX] = NULL, 271 [ESR_ELx_EC_CP15_32] = kvm_hyp_handle_cp15_32, 272 [ESR_ELx_EC_SYS64] = kvm_hyp_handle_sysreg, 273 [ESR_ELx_EC_SVE] = kvm_hyp_handle_fpsimd, 274 [ESR_ELx_EC_FP_ASIMD] = kvm_hyp_handle_fpsimd, 275 [ESR_ELx_EC_IABT_LOW] = kvm_hyp_handle_iabt_low, 276 [ESR_ELx_EC_DABT_LOW] = kvm_hyp_handle_dabt_low, 277 [ESR_ELx_EC_WATCHPT_LOW] = kvm_hyp_handle_watchpt_low, 278 [ESR_ELx_EC_ERET] = kvm_hyp_handle_eret, 279 [ESR_ELx_EC_MOPS] = kvm_hyp_handle_mops, 280 }; 281 282 static const exit_handler_fn *kvm_get_exit_handler_array(struct kvm_vcpu *vcpu) 283 { 284 return hyp_exit_handlers; 285 } 286 287 static void early_exit_filter(struct kvm_vcpu *vcpu, u64 *exit_code) 288 { 289 /* 290 * If we were in HYP context on entry, adjust the PSTATE view 291 * so that the usual helpers work correctly. 292 */ 293 if (vcpu_has_nv(vcpu) && (read_sysreg(hcr_el2) & HCR_NV)) { 294 u64 mode = *vcpu_cpsr(vcpu) & (PSR_MODE_MASK | PSR_MODE32_BIT); 295 296 switch (mode) { 297 case PSR_MODE_EL1t: 298 mode = PSR_MODE_EL2t; 299 break; 300 case PSR_MODE_EL1h: 301 mode = PSR_MODE_EL2h; 302 break; 303 } 304 305 *vcpu_cpsr(vcpu) &= ~(PSR_MODE_MASK | PSR_MODE32_BIT); 306 *vcpu_cpsr(vcpu) |= mode; 307 } 308 } 309 310 /* Switch to the guest for VHE systems running in EL2 */ 311 static int __kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu) 312 { 313 struct kvm_cpu_context *host_ctxt; 314 struct kvm_cpu_context *guest_ctxt; 315 u64 exit_code; 316 317 host_ctxt = host_data_ptr(host_ctxt); 318 guest_ctxt = &vcpu->arch.ctxt; 319 320 sysreg_save_host_state_vhe(host_ctxt); 321 322 /* 323 * Note that ARM erratum 1165522 requires us to configure both stage 1 324 * and stage 2 translation for the guest context before we clear 325 * HCR_EL2.TGE. The stage 1 and stage 2 guest context has already been 326 * loaded on the CPU in kvm_vcpu_load_vhe(). 327 */ 328 __activate_traps(vcpu); 329 330 __kvm_adjust_pc(vcpu); 331 332 sysreg_restore_guest_state_vhe(guest_ctxt); 333 __debug_switch_to_guest(vcpu); 334 335 do { 336 /* Jump in the fire! */ 337 exit_code = __guest_enter(vcpu); 338 339 /* And we're baaack! */ 340 } while (fixup_guest_exit(vcpu, &exit_code)); 341 342 sysreg_save_guest_state_vhe(guest_ctxt); 343 344 __deactivate_traps(vcpu); 345 346 sysreg_restore_host_state_vhe(host_ctxt); 347 348 if (guest_owns_fp_regs()) 349 __fpsimd_save_fpexc32(vcpu); 350 351 __debug_switch_to_host(vcpu); 352 353 return exit_code; 354 } 355 NOKPROBE_SYMBOL(__kvm_vcpu_run_vhe); 356 357 int __kvm_vcpu_run(struct kvm_vcpu *vcpu) 358 { 359 int ret; 360 361 local_daif_mask(); 362 363 /* 364 * Having IRQs masked via PMR when entering the guest means the GIC 365 * will not signal the CPU of interrupts of lower priority, and the 366 * only way to get out will be via guest exceptions. 367 * Naturally, we want to avoid this. 368 * 369 * local_daif_mask() already sets GIC_PRIO_PSR_I_SET, we just need a 370 * dsb to ensure the redistributor is forwards EL2 IRQs to the CPU. 371 */ 372 pmr_sync(); 373 374 ret = __kvm_vcpu_run_vhe(vcpu); 375 376 /* 377 * local_daif_restore() takes care to properly restore PSTATE.DAIF 378 * and the GIC PMR if the host is using IRQ priorities. 379 */ 380 local_daif_restore(DAIF_PROCCTX_NOIRQ); 381 382 /* 383 * When we exit from the guest we change a number of CPU configuration 384 * parameters, such as traps. We rely on the isb() in kvm_call_hyp*() 385 * to make sure these changes take effect before running the host or 386 * additional guests. 387 */ 388 return ret; 389 } 390 391 static void __hyp_call_panic(u64 spsr, u64 elr, u64 par) 392 { 393 struct kvm_cpu_context *host_ctxt; 394 struct kvm_vcpu *vcpu; 395 396 host_ctxt = host_data_ptr(host_ctxt); 397 vcpu = host_ctxt->__hyp_running_vcpu; 398 399 __deactivate_traps(vcpu); 400 sysreg_restore_host_state_vhe(host_ctxt); 401 402 panic("HYP panic:\nPS:%08llx PC:%016llx ESR:%08llx\nFAR:%016llx HPFAR:%016llx PAR:%016llx\nVCPU:%p\n", 403 spsr, elr, 404 read_sysreg_el2(SYS_ESR), read_sysreg_el2(SYS_FAR), 405 read_sysreg(hpfar_el2), par, vcpu); 406 } 407 NOKPROBE_SYMBOL(__hyp_call_panic); 408 409 void __noreturn hyp_panic(void) 410 { 411 u64 spsr = read_sysreg_el2(SYS_SPSR); 412 u64 elr = read_sysreg_el2(SYS_ELR); 413 u64 par = read_sysreg_par(); 414 415 __hyp_call_panic(spsr, elr, par); 416 unreachable(); 417 } 418 419 asmlinkage void kvm_unexpected_el2_exception(void) 420 { 421 __kvm_unexpected_el2_exception(); 422 } 423