1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7 #include <hyp/switch.h> 8 9 #include <linux/arm-smccc.h> 10 #include <linux/kvm_host.h> 11 #include <linux/types.h> 12 #include <linux/jump_label.h> 13 #include <linux/percpu.h> 14 #include <uapi/linux/psci.h> 15 16 #include <kvm/arm_psci.h> 17 18 #include <asm/barrier.h> 19 #include <asm/cpufeature.h> 20 #include <asm/kprobes.h> 21 #include <asm/kvm_asm.h> 22 #include <asm/kvm_emulate.h> 23 #include <asm/kvm_hyp.h> 24 #include <asm/kvm_mmu.h> 25 #include <asm/fpsimd.h> 26 #include <asm/debug-monitors.h> 27 #include <asm/processor.h> 28 #include <asm/thread_info.h> 29 #include <asm/vectors.h> 30 31 /* VHE specific context */ 32 DEFINE_PER_CPU(struct kvm_host_data, kvm_host_data); 33 DEFINE_PER_CPU(struct kvm_cpu_context, kvm_hyp_ctxt); 34 DEFINE_PER_CPU(unsigned long, kvm_hyp_vector); 35 36 static void __activate_traps(struct kvm_vcpu *vcpu) 37 { 38 u64 val; 39 40 ___activate_traps(vcpu); 41 42 val = read_sysreg(cpacr_el1); 43 val |= CPACR_EL1_TTA; 44 val &= ~(CPACR_EL1_ZEN_EL0EN | CPACR_EL1_ZEN_EL1EN); 45 46 /* 47 * With VHE (HCR.E2H == 1), accesses to CPACR_EL1 are routed to 48 * CPTR_EL2. In general, CPACR_EL1 has the same layout as CPTR_EL2, 49 * except for some missing controls, such as TAM. 50 * In this case, CPTR_EL2.TAM has the same position with or without 51 * VHE (HCR.E2H == 1) which allows us to use here the CPTR_EL2.TAM 52 * shift value for trapping the AMU accesses. 53 */ 54 55 val |= CPTR_EL2_TAM; 56 57 if (update_fp_enabled(vcpu)) { 58 if (vcpu_has_sve(vcpu)) 59 val |= CPACR_EL1_ZEN_EL0EN | CPACR_EL1_ZEN_EL1EN; 60 } else { 61 val &= ~(CPACR_EL1_FPEN_EL0EN | CPACR_EL1_FPEN_EL1EN); 62 __activate_traps_fpsimd32(vcpu); 63 } 64 65 write_sysreg(val, cpacr_el1); 66 67 write_sysreg(__this_cpu_read(kvm_hyp_vector), vbar_el1); 68 } 69 NOKPROBE_SYMBOL(__activate_traps); 70 71 static void __deactivate_traps(struct kvm_vcpu *vcpu) 72 { 73 const char *host_vectors = vectors; 74 75 ___deactivate_traps(vcpu); 76 77 write_sysreg(HCR_HOST_VHE_FLAGS, hcr_el2); 78 79 /* 80 * ARM errata 1165522 and 1530923 require the actual execution of the 81 * above before we can switch to the EL2/EL0 translation regime used by 82 * the host. 83 */ 84 asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT)); 85 86 write_sysreg(CPACR_EL1_DEFAULT, cpacr_el1); 87 88 if (!arm64_kernel_unmapped_at_el0()) 89 host_vectors = __this_cpu_read(this_cpu_vector); 90 write_sysreg(host_vectors, vbar_el1); 91 } 92 NOKPROBE_SYMBOL(__deactivate_traps); 93 94 void activate_traps_vhe_load(struct kvm_vcpu *vcpu) 95 { 96 __activate_traps_common(vcpu); 97 } 98 99 void deactivate_traps_vhe_put(struct kvm_vcpu *vcpu) 100 { 101 __deactivate_traps_common(vcpu); 102 } 103 104 static const exit_handler_fn hyp_exit_handlers[] = { 105 [0 ... ESR_ELx_EC_MAX] = NULL, 106 [ESR_ELx_EC_CP15_32] = kvm_hyp_handle_cp15_32, 107 [ESR_ELx_EC_SYS64] = kvm_hyp_handle_sysreg, 108 [ESR_ELx_EC_SVE] = kvm_hyp_handle_fpsimd, 109 [ESR_ELx_EC_FP_ASIMD] = kvm_hyp_handle_fpsimd, 110 [ESR_ELx_EC_IABT_LOW] = kvm_hyp_handle_iabt_low, 111 [ESR_ELx_EC_DABT_LOW] = kvm_hyp_handle_dabt_low, 112 [ESR_ELx_EC_PAC] = kvm_hyp_handle_ptrauth, 113 }; 114 115 static const exit_handler_fn *kvm_get_exit_handler_array(struct kvm_vcpu *vcpu) 116 { 117 return hyp_exit_handlers; 118 } 119 120 static void early_exit_filter(struct kvm_vcpu *vcpu, u64 *exit_code) 121 { 122 } 123 124 /* Switch to the guest for VHE systems running in EL2 */ 125 static int __kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu) 126 { 127 struct kvm_cpu_context *host_ctxt; 128 struct kvm_cpu_context *guest_ctxt; 129 u64 exit_code; 130 131 host_ctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt; 132 host_ctxt->__hyp_running_vcpu = vcpu; 133 guest_ctxt = &vcpu->arch.ctxt; 134 135 sysreg_save_host_state_vhe(host_ctxt); 136 137 /* 138 * ARM erratum 1165522 requires us to configure both stage 1 and 139 * stage 2 translation for the guest context before we clear 140 * HCR_EL2.TGE. 141 * 142 * We have already configured the guest's stage 1 translation in 143 * kvm_vcpu_load_sysregs_vhe above. We must now call 144 * __load_stage2 before __activate_traps, because 145 * __load_stage2 configures stage 2 translation, and 146 * __activate_traps clear HCR_EL2.TGE (among other things). 147 */ 148 __load_stage2(vcpu->arch.hw_mmu, vcpu->arch.hw_mmu->arch); 149 __activate_traps(vcpu); 150 151 __kvm_adjust_pc(vcpu); 152 153 sysreg_restore_guest_state_vhe(guest_ctxt); 154 __debug_switch_to_guest(vcpu); 155 156 do { 157 /* Jump in the fire! */ 158 exit_code = __guest_enter(vcpu); 159 160 /* And we're baaack! */ 161 } while (fixup_guest_exit(vcpu, &exit_code)); 162 163 sysreg_save_guest_state_vhe(guest_ctxt); 164 165 __deactivate_traps(vcpu); 166 167 sysreg_restore_host_state_vhe(host_ctxt); 168 169 if (vcpu->arch.flags & KVM_ARM64_FP_ENABLED) 170 __fpsimd_save_fpexc32(vcpu); 171 172 __debug_switch_to_host(vcpu); 173 174 return exit_code; 175 } 176 NOKPROBE_SYMBOL(__kvm_vcpu_run_vhe); 177 178 int __kvm_vcpu_run(struct kvm_vcpu *vcpu) 179 { 180 int ret; 181 182 local_daif_mask(); 183 184 /* 185 * Having IRQs masked via PMR when entering the guest means the GIC 186 * will not signal the CPU of interrupts of lower priority, and the 187 * only way to get out will be via guest exceptions. 188 * Naturally, we want to avoid this. 189 * 190 * local_daif_mask() already sets GIC_PRIO_PSR_I_SET, we just need a 191 * dsb to ensure the redistributor is forwards EL2 IRQs to the CPU. 192 */ 193 pmr_sync(); 194 195 ret = __kvm_vcpu_run_vhe(vcpu); 196 197 /* 198 * local_daif_restore() takes care to properly restore PSTATE.DAIF 199 * and the GIC PMR if the host is using IRQ priorities. 200 */ 201 local_daif_restore(DAIF_PROCCTX_NOIRQ); 202 203 /* 204 * When we exit from the guest we change a number of CPU configuration 205 * parameters, such as traps. Make sure these changes take effect 206 * before running the host or additional guests. 207 */ 208 isb(); 209 210 return ret; 211 } 212 213 static void __hyp_call_panic(u64 spsr, u64 elr, u64 par) 214 { 215 struct kvm_cpu_context *host_ctxt; 216 struct kvm_vcpu *vcpu; 217 218 host_ctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt; 219 vcpu = host_ctxt->__hyp_running_vcpu; 220 221 __deactivate_traps(vcpu); 222 sysreg_restore_host_state_vhe(host_ctxt); 223 224 panic("HYP panic:\nPS:%08llx PC:%016llx ESR:%08llx\nFAR:%016llx HPFAR:%016llx PAR:%016llx\nVCPU:%p\n", 225 spsr, elr, 226 read_sysreg_el2(SYS_ESR), read_sysreg_el2(SYS_FAR), 227 read_sysreg(hpfar_el2), par, vcpu); 228 } 229 NOKPROBE_SYMBOL(__hyp_call_panic); 230 231 void __noreturn hyp_panic(void) 232 { 233 u64 spsr = read_sysreg_el2(SYS_SPSR); 234 u64 elr = read_sysreg_el2(SYS_ELR); 235 u64 par = read_sysreg_par(); 236 237 __hyp_call_panic(spsr, elr, par); 238 unreachable(); 239 } 240 241 asmlinkage void kvm_unexpected_el2_exception(void) 242 { 243 return __kvm_unexpected_el2_exception(); 244 } 245