1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2021 Google LLC 4 * Author: Fuad Tabba <tabba@google.com> 5 */ 6 7 #include <linux/irqchip/arm-gic-v3.h> 8 9 #include <asm/kvm_asm.h> 10 #include <asm/kvm_mmu.h> 11 12 #include <hyp/adjust_pc.h> 13 14 #include <nvhe/pkvm.h> 15 16 #include "../../sys_regs.h" 17 18 /* 19 * Copies of the host's CPU features registers holding sanitized values at hyp. 20 */ 21 u64 id_aa64pfr0_el1_sys_val; 22 u64 id_aa64pfr1_el1_sys_val; 23 u64 id_aa64pfr2_el1_sys_val; 24 u64 id_aa64isar0_el1_sys_val; 25 u64 id_aa64isar1_el1_sys_val; 26 u64 id_aa64isar2_el1_sys_val; 27 u64 id_aa64mmfr0_el1_sys_val; 28 u64 id_aa64mmfr1_el1_sys_val; 29 u64 id_aa64mmfr2_el1_sys_val; 30 u64 id_aa64smfr0_el1_sys_val; 31 32 struct pvm_ftr_bits { 33 bool sign; 34 u8 shift; 35 u8 width; 36 u8 max_val; 37 bool (*vm_supported)(const struct kvm *kvm); 38 }; 39 40 #define __MAX_FEAT_FUNC(id, fld, max, func, sgn) \ 41 { \ 42 .sign = sgn, \ 43 .shift = id##_##fld##_SHIFT, \ 44 .width = id##_##fld##_WIDTH, \ 45 .max_val = id##_##fld##_##max, \ 46 .vm_supported = func, \ 47 } 48 49 #define MAX_FEAT_FUNC(id, fld, max, func) \ 50 __MAX_FEAT_FUNC(id, fld, max, func, id##_##fld##_SIGNED) 51 52 #define MAX_FEAT(id, fld, max) \ 53 MAX_FEAT_FUNC(id, fld, max, NULL) 54 55 #define MAX_FEAT_ENUM(id, fld, max) \ 56 __MAX_FEAT_FUNC(id, fld, max, NULL, false) 57 58 #define FEAT_END { .width = 0, } 59 60 static bool vm_has_ptrauth(const struct kvm *kvm) 61 { 62 if (!IS_ENABLED(CONFIG_ARM64_PTR_AUTH)) 63 return false; 64 65 return (cpus_have_final_cap(ARM64_HAS_ADDRESS_AUTH) || 66 cpus_have_final_cap(ARM64_HAS_GENERIC_AUTH)) && 67 kvm_vcpu_has_feature(kvm, KVM_ARM_VCPU_PTRAUTH_GENERIC); 68 } 69 70 static bool vm_has_sve(const struct kvm *kvm) 71 { 72 return system_supports_sve() && kvm_vcpu_has_feature(kvm, KVM_ARM_VCPU_SVE); 73 } 74 75 /* 76 * Definitions for features to be allowed or restricted for protected guests. 77 * 78 * Each field in the masks represents the highest supported value for the 79 * feature. If a feature field is not present, it is not supported. Moreover, 80 * these are used to generate the guest's view of the feature registers. 81 * 82 * The approach for protected VMs is to at least support features that are: 83 * - Needed by common Linux distributions (e.g., floating point) 84 * - Trivial to support, e.g., supporting the feature does not introduce or 85 * require tracking of additional state in KVM 86 * - Cannot be trapped or prevent the guest from using anyway 87 */ 88 89 static const struct pvm_ftr_bits pvmid_aa64pfr0[] = { 90 MAX_FEAT(ID_AA64PFR0_EL1, EL0, IMP), 91 MAX_FEAT(ID_AA64PFR0_EL1, EL1, IMP), 92 MAX_FEAT(ID_AA64PFR0_EL1, EL2, IMP), 93 MAX_FEAT(ID_AA64PFR0_EL1, EL3, IMP), 94 MAX_FEAT(ID_AA64PFR0_EL1, FP, FP16), 95 MAX_FEAT(ID_AA64PFR0_EL1, AdvSIMD, FP16), 96 MAX_FEAT(ID_AA64PFR0_EL1, GIC, IMP), 97 MAX_FEAT_FUNC(ID_AA64PFR0_EL1, SVE, IMP, vm_has_sve), 98 MAX_FEAT(ID_AA64PFR0_EL1, RAS, IMP), 99 MAX_FEAT(ID_AA64PFR0_EL1, DIT, IMP), 100 MAX_FEAT(ID_AA64PFR0_EL1, CSV2, IMP), 101 MAX_FEAT(ID_AA64PFR0_EL1, CSV3, IMP), 102 FEAT_END 103 }; 104 105 static const struct pvm_ftr_bits pvmid_aa64pfr1[] = { 106 MAX_FEAT(ID_AA64PFR1_EL1, BT, IMP), 107 MAX_FEAT(ID_AA64PFR1_EL1, SSBS, SSBS2), 108 MAX_FEAT_ENUM(ID_AA64PFR1_EL1, MTE_frac, NI), 109 FEAT_END 110 }; 111 112 static const struct pvm_ftr_bits pvmid_aa64pfr2[] = { 113 MAX_FEAT(ID_AA64PFR2_EL1, GCIE, NI), 114 FEAT_END 115 }; 116 117 static const struct pvm_ftr_bits pvmid_aa64mmfr0[] = { 118 MAX_FEAT_ENUM(ID_AA64MMFR0_EL1, PARANGE, 40), 119 MAX_FEAT_ENUM(ID_AA64MMFR0_EL1, ASIDBITS, 16), 120 MAX_FEAT(ID_AA64MMFR0_EL1, BIGEND, IMP), 121 MAX_FEAT(ID_AA64MMFR0_EL1, SNSMEM, IMP), 122 MAX_FEAT(ID_AA64MMFR0_EL1, BIGENDEL0, IMP), 123 MAX_FEAT(ID_AA64MMFR0_EL1, EXS, IMP), 124 FEAT_END 125 }; 126 127 static const struct pvm_ftr_bits pvmid_aa64mmfr1[] = { 128 MAX_FEAT(ID_AA64MMFR1_EL1, HAFDBS, DBM), 129 MAX_FEAT_ENUM(ID_AA64MMFR1_EL1, VMIDBits, 16), 130 MAX_FEAT(ID_AA64MMFR1_EL1, HPDS, HPDS2), 131 MAX_FEAT(ID_AA64MMFR1_EL1, PAN, PAN3), 132 MAX_FEAT(ID_AA64MMFR1_EL1, SpecSEI, IMP), 133 MAX_FEAT(ID_AA64MMFR1_EL1, ETS, IMP), 134 MAX_FEAT(ID_AA64MMFR1_EL1, CMOW, IMP), 135 FEAT_END 136 }; 137 138 static const struct pvm_ftr_bits pvmid_aa64mmfr2[] = { 139 MAX_FEAT(ID_AA64MMFR2_EL1, CnP, IMP), 140 MAX_FEAT(ID_AA64MMFR2_EL1, UAO, IMP), 141 MAX_FEAT(ID_AA64MMFR2_EL1, IESB, IMP), 142 MAX_FEAT(ID_AA64MMFR2_EL1, AT, IMP), 143 MAX_FEAT(ID_AA64MMFR2_EL1, IDS, IMP), 144 MAX_FEAT(ID_AA64MMFR2_EL1, TTL, IMP), 145 MAX_FEAT(ID_AA64MMFR2_EL1, BBM, 2), 146 MAX_FEAT(ID_AA64MMFR2_EL1, E0PD, IMP), 147 FEAT_END 148 }; 149 150 static const struct pvm_ftr_bits pvmid_aa64isar1[] = { 151 MAX_FEAT(ID_AA64ISAR1_EL1, DPB, DPB2), 152 MAX_FEAT_FUNC(ID_AA64ISAR1_EL1, APA, PAuth, vm_has_ptrauth), 153 MAX_FEAT_FUNC(ID_AA64ISAR1_EL1, API, PAuth, vm_has_ptrauth), 154 MAX_FEAT(ID_AA64ISAR1_EL1, JSCVT, IMP), 155 MAX_FEAT(ID_AA64ISAR1_EL1, FCMA, IMP), 156 MAX_FEAT(ID_AA64ISAR1_EL1, LRCPC, LRCPC3), 157 MAX_FEAT(ID_AA64ISAR1_EL1, GPA, IMP), 158 MAX_FEAT(ID_AA64ISAR1_EL1, GPI, IMP), 159 MAX_FEAT(ID_AA64ISAR1_EL1, FRINTTS, IMP), 160 MAX_FEAT(ID_AA64ISAR1_EL1, SB, IMP), 161 MAX_FEAT(ID_AA64ISAR1_EL1, SPECRES, COSP_RCTX), 162 MAX_FEAT(ID_AA64ISAR1_EL1, BF16, EBF16), 163 MAX_FEAT(ID_AA64ISAR1_EL1, DGH, IMP), 164 MAX_FEAT(ID_AA64ISAR1_EL1, I8MM, IMP), 165 FEAT_END 166 }; 167 168 static const struct pvm_ftr_bits pvmid_aa64isar2[] = { 169 MAX_FEAT_FUNC(ID_AA64ISAR2_EL1, GPA3, IMP, vm_has_ptrauth), 170 MAX_FEAT_FUNC(ID_AA64ISAR2_EL1, APA3, PAuth, vm_has_ptrauth), 171 MAX_FEAT(ID_AA64ISAR2_EL1, ATS1A, IMP), 172 FEAT_END 173 }; 174 175 /* 176 * None of the features in ID_AA64DFR0_EL1 nor ID_AA64MMFR4_EL1 are supported. 177 * However, both have Not-Implemented values that are non-zero. Define them 178 * so they can be used when getting the value of these registers. 179 */ 180 #define ID_AA64DFR0_EL1_NONZERO_NI \ 181 ( \ 182 SYS_FIELD_PREP_ENUM(ID_AA64DFR0_EL1, DoubleLock, NI) | \ 183 SYS_FIELD_PREP_ENUM(ID_AA64DFR0_EL1, MTPMU, NI) \ 184 ) 185 186 #define ID_AA64MMFR4_EL1_NONZERO_NI \ 187 SYS_FIELD_PREP_ENUM(ID_AA64MMFR4_EL1, E2H0, NI) 188 189 /* 190 * Returns the value of the feature registers based on the system register 191 * value, the vcpu support for the revelant features, and the additional 192 * restrictions for protected VMs. 193 */ 194 static u64 get_restricted_features(const struct kvm_vcpu *vcpu, 195 u64 sys_reg_val, 196 const struct pvm_ftr_bits restrictions[]) 197 { 198 u64 val = 0UL; 199 int i; 200 201 for (i = 0; restrictions[i].width != 0; i++) { 202 bool (*vm_supported)(const struct kvm *) = restrictions[i].vm_supported; 203 bool sign = restrictions[i].sign; 204 int shift = restrictions[i].shift; 205 int width = restrictions[i].width; 206 u64 min_signed = (1UL << width) - 1UL; 207 u64 sign_bit = 1UL << (width - 1); 208 u64 mask = GENMASK_ULL(width + shift - 1, shift); 209 u64 sys_val = (sys_reg_val & mask) >> shift; 210 u64 pvm_max = restrictions[i].max_val; 211 212 if (vm_supported && !vm_supported(vcpu->kvm)) 213 val |= (sign ? min_signed : 0) << shift; 214 else if (sign && (sys_val >= sign_bit || pvm_max >= sign_bit)) 215 val |= max(sys_val, pvm_max) << shift; 216 else 217 val |= min(sys_val, pvm_max) << shift; 218 } 219 220 return val; 221 } 222 223 static u64 pvm_calc_id_reg(const struct kvm_vcpu *vcpu, u32 id) 224 { 225 switch (id) { 226 case SYS_ID_AA64PFR0_EL1: 227 return get_restricted_features(vcpu, id_aa64pfr0_el1_sys_val, pvmid_aa64pfr0); 228 case SYS_ID_AA64PFR1_EL1: 229 return get_restricted_features(vcpu, id_aa64pfr1_el1_sys_val, pvmid_aa64pfr1); 230 case SYS_ID_AA64PFR2_EL1: 231 return get_restricted_features(vcpu, id_aa64pfr2_el1_sys_val, pvmid_aa64pfr2); 232 case SYS_ID_AA64ISAR0_EL1: 233 return id_aa64isar0_el1_sys_val; 234 case SYS_ID_AA64ISAR1_EL1: 235 return get_restricted_features(vcpu, id_aa64isar1_el1_sys_val, pvmid_aa64isar1); 236 case SYS_ID_AA64ISAR2_EL1: 237 return get_restricted_features(vcpu, id_aa64isar2_el1_sys_val, pvmid_aa64isar2); 238 case SYS_ID_AA64MMFR0_EL1: 239 return get_restricted_features(vcpu, id_aa64mmfr0_el1_sys_val, pvmid_aa64mmfr0); 240 case SYS_ID_AA64MMFR1_EL1: 241 return get_restricted_features(vcpu, id_aa64mmfr1_el1_sys_val, pvmid_aa64mmfr1); 242 case SYS_ID_AA64MMFR2_EL1: 243 return get_restricted_features(vcpu, id_aa64mmfr2_el1_sys_val, pvmid_aa64mmfr2); 244 case SYS_ID_AA64DFR0_EL1: 245 return ID_AA64DFR0_EL1_NONZERO_NI; 246 case SYS_ID_AA64MMFR4_EL1: 247 return ID_AA64MMFR4_EL1_NONZERO_NI; 248 default: 249 /* Unhandled ID register, RAZ */ 250 return 0; 251 } 252 } 253 254 static void inject_sync64(struct kvm_vcpu *vcpu, u64 esr) 255 { 256 *vcpu_pc(vcpu) = read_sysreg_el2(SYS_ELR); 257 *vcpu_cpsr(vcpu) = read_sysreg_el2(SYS_SPSR); 258 259 /* 260 * Make sure we have the latest update to VBAR_EL1, as pKVM 261 * handles traps very early, before sysregs are resync'ed 262 */ 263 __vcpu_assign_sys_reg(vcpu, VBAR_EL1, read_sysreg_el1(SYS_VBAR)); 264 265 kvm_pend_exception(vcpu, EXCEPT_AA64_EL1_SYNC); 266 267 __kvm_adjust_pc(vcpu); 268 269 write_sysreg_el1(esr, SYS_ESR); 270 write_sysreg_el1(read_sysreg_el2(SYS_ELR), SYS_ELR); 271 write_sysreg_el2(*vcpu_pc(vcpu), SYS_ELR); 272 write_sysreg_el2(*vcpu_cpsr(vcpu), SYS_SPSR); 273 } 274 275 /* 276 * Inject an unknown/undefined exception to an AArch64 guest while most of its 277 * sysregs are live. 278 */ 279 static void inject_undef64(struct kvm_vcpu *vcpu) 280 { 281 inject_sync64(vcpu, (ESR_ELx_EC_UNKNOWN << ESR_ELx_EC_SHIFT)); 282 } 283 284 static u64 read_id_reg(const struct kvm_vcpu *vcpu, 285 struct sys_reg_desc const *r) 286 { 287 struct kvm *kvm = vcpu->kvm; 288 u32 reg = reg_to_encoding(r); 289 290 if (WARN_ON_ONCE(!test_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags))) 291 return 0; 292 293 if (reg >= sys_reg(3, 0, 0, 1, 0) && reg <= sys_reg(3, 0, 0, 7, 7)) 294 return kvm->arch.id_regs[IDREG_IDX(reg)]; 295 296 return 0; 297 } 298 299 /* Handler to RAZ/WI sysregs */ 300 static bool pvm_access_raz_wi(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 301 const struct sys_reg_desc *r) 302 { 303 if (!p->is_write) 304 p->regval = 0; 305 306 return true; 307 } 308 309 /* 310 * Accessor for AArch32 feature id registers. 311 * 312 * The value of these registers is "unknown" according to the spec if AArch32 313 * isn't supported. 314 */ 315 static bool pvm_access_id_aarch32(struct kvm_vcpu *vcpu, 316 struct sys_reg_params *p, 317 const struct sys_reg_desc *r) 318 { 319 if (p->is_write) { 320 inject_undef64(vcpu); 321 return false; 322 } 323 324 return pvm_access_raz_wi(vcpu, p, r); 325 } 326 327 /* 328 * Accessor for AArch64 feature id registers. 329 * 330 * If access is allowed, set the regval to the protected VM's view of the 331 * register and return true. 332 * Otherwise, inject an undefined exception and return false. 333 */ 334 static bool pvm_access_id_aarch64(struct kvm_vcpu *vcpu, 335 struct sys_reg_params *p, 336 const struct sys_reg_desc *r) 337 { 338 if (p->is_write) { 339 inject_undef64(vcpu); 340 return false; 341 } 342 343 p->regval = read_id_reg(vcpu, r); 344 return true; 345 } 346 347 static bool pvm_gic_read_sre(struct kvm_vcpu *vcpu, 348 struct sys_reg_params *p, 349 const struct sys_reg_desc *r) 350 { 351 /* pVMs only support GICv3. 'nuf said. */ 352 if (!p->is_write) 353 p->regval = ICC_SRE_EL1_DIB | ICC_SRE_EL1_DFB | ICC_SRE_EL1_SRE; 354 355 return true; 356 } 357 358 static bool pvm_idst_access(struct kvm_vcpu *vcpu, 359 struct sys_reg_params *p, 360 const struct sys_reg_desc *r) 361 { 362 if (kvm_has_feat(vcpu->kvm, ID_AA64MMFR2_EL1, IDS, IMP)) 363 inject_sync64(vcpu, kvm_vcpu_get_esr(vcpu)); 364 else 365 inject_undef64(vcpu); 366 367 return false; 368 } 369 370 /* Mark the specified system register as an AArch32 feature id register. */ 371 #define AARCH32(REG) { SYS_DESC(REG), .access = pvm_access_id_aarch32 } 372 373 /* Mark the specified system register as an AArch64 feature id register. */ 374 #define AARCH64(REG) { SYS_DESC(REG), .access = pvm_access_id_aarch64 } 375 376 /* 377 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID 378 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2 379 * (1 <= crm < 8, 0 <= Op2 < 8). 380 */ 381 #define ID_UNALLOCATED(crm, op2) { \ 382 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \ 383 .access = pvm_access_id_aarch64, \ 384 } 385 386 /* Mark the specified system register as Read-As-Zero/Write-Ignored */ 387 #define RAZ_WI(REG) { SYS_DESC(REG), .access = pvm_access_raz_wi } 388 389 /* Mark the specified system register as not being handled in hyp. */ 390 #define HOST_HANDLED(REG) { SYS_DESC(REG), .access = NULL } 391 392 /* 393 * Architected system registers. 394 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2 395 * 396 * NOTE: Anything not explicitly listed here is *restricted by default*, i.e., 397 * it will lead to injecting an exception into the guest. 398 */ 399 static const struct sys_reg_desc pvm_sys_reg_descs[] = { 400 /* Cache maintenance by set/way operations are restricted. */ 401 402 /* Debug and Trace Registers are restricted. */ 403 RAZ_WI(SYS_DBGBVRn_EL1(0)), 404 RAZ_WI(SYS_DBGBCRn_EL1(0)), 405 RAZ_WI(SYS_DBGWVRn_EL1(0)), 406 RAZ_WI(SYS_DBGWCRn_EL1(0)), 407 RAZ_WI(SYS_MDSCR_EL1), 408 RAZ_WI(SYS_OSLAR_EL1), 409 RAZ_WI(SYS_OSLSR_EL1), 410 RAZ_WI(SYS_OSDLR_EL1), 411 412 /* Group 1 ID registers */ 413 HOST_HANDLED(SYS_REVIDR_EL1), 414 415 /* AArch64 mappings of the AArch32 ID registers */ 416 /* CRm=1 */ 417 AARCH32(SYS_ID_PFR0_EL1), 418 AARCH32(SYS_ID_PFR1_EL1), 419 AARCH32(SYS_ID_DFR0_EL1), 420 AARCH32(SYS_ID_AFR0_EL1), 421 AARCH32(SYS_ID_MMFR0_EL1), 422 AARCH32(SYS_ID_MMFR1_EL1), 423 AARCH32(SYS_ID_MMFR2_EL1), 424 AARCH32(SYS_ID_MMFR3_EL1), 425 426 /* CRm=2 */ 427 AARCH32(SYS_ID_ISAR0_EL1), 428 AARCH32(SYS_ID_ISAR1_EL1), 429 AARCH32(SYS_ID_ISAR2_EL1), 430 AARCH32(SYS_ID_ISAR3_EL1), 431 AARCH32(SYS_ID_ISAR4_EL1), 432 AARCH32(SYS_ID_ISAR5_EL1), 433 AARCH32(SYS_ID_MMFR4_EL1), 434 AARCH32(SYS_ID_ISAR6_EL1), 435 436 /* CRm=3 */ 437 AARCH32(SYS_MVFR0_EL1), 438 AARCH32(SYS_MVFR1_EL1), 439 AARCH32(SYS_MVFR2_EL1), 440 ID_UNALLOCATED(3,3), 441 AARCH32(SYS_ID_PFR2_EL1), 442 AARCH32(SYS_ID_DFR1_EL1), 443 AARCH32(SYS_ID_MMFR5_EL1), 444 ID_UNALLOCATED(3,7), 445 446 /* AArch64 ID registers */ 447 /* CRm=4 */ 448 AARCH64(SYS_ID_AA64PFR0_EL1), 449 AARCH64(SYS_ID_AA64PFR1_EL1), 450 AARCH64(SYS_ID_AA64PFR2_EL1), 451 ID_UNALLOCATED(4,3), 452 AARCH64(SYS_ID_AA64ZFR0_EL1), 453 ID_UNALLOCATED(4,5), 454 ID_UNALLOCATED(4,6), 455 ID_UNALLOCATED(4,7), 456 AARCH64(SYS_ID_AA64DFR0_EL1), 457 AARCH64(SYS_ID_AA64DFR1_EL1), 458 ID_UNALLOCATED(5,2), 459 ID_UNALLOCATED(5,3), 460 AARCH64(SYS_ID_AA64AFR0_EL1), 461 AARCH64(SYS_ID_AA64AFR1_EL1), 462 ID_UNALLOCATED(5,6), 463 ID_UNALLOCATED(5,7), 464 AARCH64(SYS_ID_AA64ISAR0_EL1), 465 AARCH64(SYS_ID_AA64ISAR1_EL1), 466 AARCH64(SYS_ID_AA64ISAR2_EL1), 467 ID_UNALLOCATED(6,3), 468 ID_UNALLOCATED(6,4), 469 ID_UNALLOCATED(6,5), 470 ID_UNALLOCATED(6,6), 471 ID_UNALLOCATED(6,7), 472 AARCH64(SYS_ID_AA64MMFR0_EL1), 473 AARCH64(SYS_ID_AA64MMFR1_EL1), 474 AARCH64(SYS_ID_AA64MMFR2_EL1), 475 ID_UNALLOCATED(7,3), 476 ID_UNALLOCATED(7,4), 477 ID_UNALLOCATED(7,5), 478 ID_UNALLOCATED(7,6), 479 ID_UNALLOCATED(7,7), 480 481 /* Scalable Vector Registers are restricted. */ 482 483 HOST_HANDLED(SYS_ICC_PMR_EL1), 484 485 RAZ_WI(SYS_ERRIDR_EL1), 486 RAZ_WI(SYS_ERRSELR_EL1), 487 RAZ_WI(SYS_ERXFR_EL1), 488 RAZ_WI(SYS_ERXCTLR_EL1), 489 RAZ_WI(SYS_ERXSTATUS_EL1), 490 RAZ_WI(SYS_ERXADDR_EL1), 491 RAZ_WI(SYS_ERXMISC0_EL1), 492 RAZ_WI(SYS_ERXMISC1_EL1), 493 494 /* Performance Monitoring Registers are restricted. */ 495 496 /* Limited Ordering Regions Registers are restricted. */ 497 498 HOST_HANDLED(SYS_ICC_DIR_EL1), 499 HOST_HANDLED(SYS_ICC_RPR_EL1), 500 HOST_HANDLED(SYS_ICC_SGI1R_EL1), 501 HOST_HANDLED(SYS_ICC_ASGI1R_EL1), 502 HOST_HANDLED(SYS_ICC_SGI0R_EL1), 503 HOST_HANDLED(SYS_ICC_CTLR_EL1), 504 { SYS_DESC(SYS_ICC_SRE_EL1), .access = pvm_gic_read_sre, }, 505 506 HOST_HANDLED(SYS_CCSIDR_EL1), 507 HOST_HANDLED(SYS_CLIDR_EL1), 508 { SYS_DESC(SYS_CCSIDR2_EL1), .access = pvm_idst_access }, 509 { SYS_DESC(SYS_GMID_EL1), .access = pvm_idst_access }, 510 { SYS_DESC(SYS_SMIDR_EL1), .access = pvm_idst_access }, 511 HOST_HANDLED(SYS_AIDR_EL1), 512 HOST_HANDLED(SYS_CSSELR_EL1), 513 HOST_HANDLED(SYS_CTR_EL0), 514 515 /* Performance Monitoring Registers are restricted. */ 516 517 /* Activity Monitoring Registers are restricted. */ 518 519 HOST_HANDLED(SYS_CNTP_TVAL_EL0), 520 HOST_HANDLED(SYS_CNTP_CTL_EL0), 521 HOST_HANDLED(SYS_CNTP_CVAL_EL0), 522 523 /* Performance Monitoring Registers are restricted. */ 524 }; 525 526 /* 527 * Initializes feature registers for protected vms. 528 */ 529 void kvm_init_pvm_id_regs(struct kvm_vcpu *vcpu) 530 { 531 struct kvm *kvm = vcpu->kvm; 532 struct kvm_arch *ka = &kvm->arch; 533 u32 r; 534 535 hyp_assert_lock_held(&vm_table_lock); 536 537 if (test_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags)) 538 return; 539 540 /* 541 * Initialize only AArch64 id registers since AArch32 isn't supported 542 * for protected VMs. 543 */ 544 for (r = sys_reg(3, 0, 0, 4, 0); r <= sys_reg(3, 0, 0, 7, 7); r += sys_reg(0, 0, 0, 0, 1)) 545 ka->id_regs[IDREG_IDX(r)] = pvm_calc_id_reg(vcpu, r); 546 547 set_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags); 548 } 549 550 /* 551 * Checks that the sysreg table is unique and in-order. 552 * 553 * Returns 0 if the table is consistent, or 1 otherwise. 554 */ 555 int kvm_check_pvm_sysreg_table(void) 556 { 557 unsigned int i; 558 559 for (i = 1; i < ARRAY_SIZE(pvm_sys_reg_descs); i++) { 560 if (cmp_sys_reg(&pvm_sys_reg_descs[i-1], &pvm_sys_reg_descs[i]) >= 0) 561 return 1; 562 } 563 564 return 0; 565 } 566 567 /* 568 * Handler for protected VM MSR, MRS or System instruction execution. 569 * 570 * Returns true if the hypervisor has handled the exit, and control should go 571 * back to the guest, or false if it hasn't, to be handled by the host. 572 */ 573 bool kvm_handle_pvm_sysreg(struct kvm_vcpu *vcpu, u64 *exit_code) 574 { 575 const struct sys_reg_desc *r; 576 struct sys_reg_params params; 577 unsigned long esr = kvm_vcpu_get_esr(vcpu); 578 int Rt = kvm_vcpu_sys_get_rt(vcpu); 579 580 params = esr_sys64_to_params(esr); 581 params.regval = vcpu_get_reg(vcpu, Rt); 582 583 r = find_reg(¶ms, pvm_sys_reg_descs, ARRAY_SIZE(pvm_sys_reg_descs)); 584 585 /* Undefined (RESTRICTED). */ 586 if (r == NULL) { 587 inject_undef64(vcpu); 588 return true; 589 } 590 591 /* Handled by the host (HOST_HANDLED) */ 592 if (r->access == NULL) 593 return false; 594 595 /* Handled by hyp: skip instruction if instructed to do so. */ 596 if (r->access(vcpu, ¶ms, r)) 597 __kvm_skip_instr(vcpu); 598 599 if (!params.is_write) 600 vcpu_set_reg(vcpu, Rt, params.regval); 601 602 return true; 603 } 604 605 /* 606 * Handler for protected VM restricted exceptions. 607 * 608 * Inject an undefined exception into the guest and return true to indicate that 609 * the hypervisor has handled the exit, and control should go back to the guest. 610 */ 611 bool kvm_handle_pvm_restricted(struct kvm_vcpu *vcpu, u64 *exit_code) 612 { 613 inject_undef64(vcpu); 614 return true; 615 } 616