1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2020 - Google Inc 4 * Author: Andrew Scull <ascull@google.com> 5 */ 6 7 #include <hyp/adjust_pc.h> 8 9 #include <asm/pgtable-types.h> 10 #include <asm/kvm_asm.h> 11 #include <asm/kvm_emulate.h> 12 #include <asm/kvm_host.h> 13 #include <asm/kvm_hyp.h> 14 #include <asm/kvm_mmu.h> 15 16 #include <nvhe/ffa.h> 17 #include <nvhe/mem_protect.h> 18 #include <nvhe/mm.h> 19 #include <nvhe/pkvm.h> 20 #include <nvhe/trap_handler.h> 21 22 DEFINE_PER_CPU(struct kvm_nvhe_init_params, kvm_init_params); 23 24 void __kvm_hyp_host_forward_smc(struct kvm_cpu_context *host_ctxt); 25 26 static void __hyp_sve_save_guest(struct kvm_vcpu *vcpu) 27 { 28 __vcpu_sys_reg(vcpu, ZCR_EL1) = read_sysreg_el1(SYS_ZCR); 29 /* 30 * On saving/restoring guest sve state, always use the maximum VL for 31 * the guest. The layout of the data when saving the sve state depends 32 * on the VL, so use a consistent (i.e., the maximum) guest VL. 33 */ 34 sve_cond_update_zcr_vq(vcpu_sve_max_vq(vcpu) - 1, SYS_ZCR_EL2); 35 __sve_save_state(vcpu_sve_pffr(vcpu), &vcpu->arch.ctxt.fp_regs.fpsr, true); 36 write_sysreg_s(ZCR_ELx_LEN_MASK, SYS_ZCR_EL2); 37 } 38 39 static void __hyp_sve_restore_host(void) 40 { 41 struct cpu_sve_state *sve_state = *host_data_ptr(sve_state); 42 43 /* 44 * On saving/restoring host sve state, always use the maximum VL for 45 * the host. The layout of the data when saving the sve state depends 46 * on the VL, so use a consistent (i.e., the maximum) host VL. 47 * 48 * Setting ZCR_EL2 to ZCR_ELx_LEN_MASK sets the effective length 49 * supported by the system (or limited at EL3). 50 */ 51 write_sysreg_s(ZCR_ELx_LEN_MASK, SYS_ZCR_EL2); 52 __sve_restore_state(sve_state->sve_regs + sve_ffr_offset(kvm_host_sve_max_vl), 53 &sve_state->fpsr, 54 true); 55 write_sysreg_el1(sve_state->zcr_el1, SYS_ZCR); 56 } 57 58 static void fpsimd_sve_flush(void) 59 { 60 *host_data_ptr(fp_owner) = FP_STATE_HOST_OWNED; 61 } 62 63 static void fpsimd_sve_sync(struct kvm_vcpu *vcpu) 64 { 65 if (!guest_owns_fp_regs()) 66 return; 67 68 cpacr_clear_set(0, CPACR_ELx_FPEN | CPACR_ELx_ZEN); 69 isb(); 70 71 if (vcpu_has_sve(vcpu)) 72 __hyp_sve_save_guest(vcpu); 73 else 74 __fpsimd_save_state(&vcpu->arch.ctxt.fp_regs); 75 76 if (system_supports_sve()) 77 __hyp_sve_restore_host(); 78 else 79 __fpsimd_restore_state(*host_data_ptr(fpsimd_state)); 80 81 *host_data_ptr(fp_owner) = FP_STATE_HOST_OWNED; 82 } 83 84 static void flush_hyp_vcpu(struct pkvm_hyp_vcpu *hyp_vcpu) 85 { 86 struct kvm_vcpu *host_vcpu = hyp_vcpu->host_vcpu; 87 88 fpsimd_sve_flush(); 89 90 hyp_vcpu->vcpu.arch.ctxt = host_vcpu->arch.ctxt; 91 92 hyp_vcpu->vcpu.arch.sve_state = kern_hyp_va(host_vcpu->arch.sve_state); 93 /* Limit guest vector length to the maximum supported by the host. */ 94 hyp_vcpu->vcpu.arch.sve_max_vl = min(host_vcpu->arch.sve_max_vl, kvm_host_sve_max_vl); 95 96 hyp_vcpu->vcpu.arch.hw_mmu = host_vcpu->arch.hw_mmu; 97 98 hyp_vcpu->vcpu.arch.hcr_el2 = host_vcpu->arch.hcr_el2; 99 hyp_vcpu->vcpu.arch.mdcr_el2 = host_vcpu->arch.mdcr_el2; 100 101 hyp_vcpu->vcpu.arch.iflags = host_vcpu->arch.iflags; 102 103 hyp_vcpu->vcpu.arch.debug_ptr = kern_hyp_va(host_vcpu->arch.debug_ptr); 104 105 hyp_vcpu->vcpu.arch.vsesr_el2 = host_vcpu->arch.vsesr_el2; 106 107 hyp_vcpu->vcpu.arch.vgic_cpu.vgic_v3 = host_vcpu->arch.vgic_cpu.vgic_v3; 108 } 109 110 static void sync_hyp_vcpu(struct pkvm_hyp_vcpu *hyp_vcpu) 111 { 112 struct kvm_vcpu *host_vcpu = hyp_vcpu->host_vcpu; 113 struct vgic_v3_cpu_if *hyp_cpu_if = &hyp_vcpu->vcpu.arch.vgic_cpu.vgic_v3; 114 struct vgic_v3_cpu_if *host_cpu_if = &host_vcpu->arch.vgic_cpu.vgic_v3; 115 unsigned int i; 116 117 fpsimd_sve_sync(&hyp_vcpu->vcpu); 118 119 host_vcpu->arch.ctxt = hyp_vcpu->vcpu.arch.ctxt; 120 121 host_vcpu->arch.hcr_el2 = hyp_vcpu->vcpu.arch.hcr_el2; 122 123 host_vcpu->arch.fault = hyp_vcpu->vcpu.arch.fault; 124 125 host_vcpu->arch.iflags = hyp_vcpu->vcpu.arch.iflags; 126 127 host_cpu_if->vgic_hcr = hyp_cpu_if->vgic_hcr; 128 for (i = 0; i < hyp_cpu_if->used_lrs; ++i) 129 host_cpu_if->vgic_lr[i] = hyp_cpu_if->vgic_lr[i]; 130 } 131 132 static void handle___kvm_vcpu_run(struct kvm_cpu_context *host_ctxt) 133 { 134 DECLARE_REG(struct kvm_vcpu *, host_vcpu, host_ctxt, 1); 135 int ret; 136 137 host_vcpu = kern_hyp_va(host_vcpu); 138 139 if (unlikely(is_protected_kvm_enabled())) { 140 struct pkvm_hyp_vcpu *hyp_vcpu; 141 struct kvm *host_kvm; 142 143 host_kvm = kern_hyp_va(host_vcpu->kvm); 144 hyp_vcpu = pkvm_load_hyp_vcpu(host_kvm->arch.pkvm.handle, 145 host_vcpu->vcpu_idx); 146 if (!hyp_vcpu) { 147 ret = -EINVAL; 148 goto out; 149 } 150 151 flush_hyp_vcpu(hyp_vcpu); 152 153 ret = __kvm_vcpu_run(&hyp_vcpu->vcpu); 154 155 sync_hyp_vcpu(hyp_vcpu); 156 pkvm_put_hyp_vcpu(hyp_vcpu); 157 } else { 158 /* The host is fully trusted, run its vCPU directly. */ 159 ret = __kvm_vcpu_run(host_vcpu); 160 } 161 162 out: 163 cpu_reg(host_ctxt, 1) = ret; 164 } 165 166 static void handle___kvm_adjust_pc(struct kvm_cpu_context *host_ctxt) 167 { 168 DECLARE_REG(struct kvm_vcpu *, vcpu, host_ctxt, 1); 169 170 __kvm_adjust_pc(kern_hyp_va(vcpu)); 171 } 172 173 static void handle___kvm_flush_vm_context(struct kvm_cpu_context *host_ctxt) 174 { 175 __kvm_flush_vm_context(); 176 } 177 178 static void handle___kvm_tlb_flush_vmid_ipa(struct kvm_cpu_context *host_ctxt) 179 { 180 DECLARE_REG(struct kvm_s2_mmu *, mmu, host_ctxt, 1); 181 DECLARE_REG(phys_addr_t, ipa, host_ctxt, 2); 182 DECLARE_REG(int, level, host_ctxt, 3); 183 184 __kvm_tlb_flush_vmid_ipa(kern_hyp_va(mmu), ipa, level); 185 } 186 187 static void handle___kvm_tlb_flush_vmid_ipa_nsh(struct kvm_cpu_context *host_ctxt) 188 { 189 DECLARE_REG(struct kvm_s2_mmu *, mmu, host_ctxt, 1); 190 DECLARE_REG(phys_addr_t, ipa, host_ctxt, 2); 191 DECLARE_REG(int, level, host_ctxt, 3); 192 193 __kvm_tlb_flush_vmid_ipa_nsh(kern_hyp_va(mmu), ipa, level); 194 } 195 196 static void 197 handle___kvm_tlb_flush_vmid_range(struct kvm_cpu_context *host_ctxt) 198 { 199 DECLARE_REG(struct kvm_s2_mmu *, mmu, host_ctxt, 1); 200 DECLARE_REG(phys_addr_t, start, host_ctxt, 2); 201 DECLARE_REG(unsigned long, pages, host_ctxt, 3); 202 203 __kvm_tlb_flush_vmid_range(kern_hyp_va(mmu), start, pages); 204 } 205 206 static void handle___kvm_tlb_flush_vmid(struct kvm_cpu_context *host_ctxt) 207 { 208 DECLARE_REG(struct kvm_s2_mmu *, mmu, host_ctxt, 1); 209 210 __kvm_tlb_flush_vmid(kern_hyp_va(mmu)); 211 } 212 213 static void handle___kvm_flush_cpu_context(struct kvm_cpu_context *host_ctxt) 214 { 215 DECLARE_REG(struct kvm_s2_mmu *, mmu, host_ctxt, 1); 216 217 __kvm_flush_cpu_context(kern_hyp_va(mmu)); 218 } 219 220 static void handle___kvm_timer_set_cntvoff(struct kvm_cpu_context *host_ctxt) 221 { 222 __kvm_timer_set_cntvoff(cpu_reg(host_ctxt, 1)); 223 } 224 225 static void handle___kvm_enable_ssbs(struct kvm_cpu_context *host_ctxt) 226 { 227 u64 tmp; 228 229 tmp = read_sysreg_el2(SYS_SCTLR); 230 tmp |= SCTLR_ELx_DSSBS; 231 write_sysreg_el2(tmp, SYS_SCTLR); 232 } 233 234 static void handle___vgic_v3_get_gic_config(struct kvm_cpu_context *host_ctxt) 235 { 236 cpu_reg(host_ctxt, 1) = __vgic_v3_get_gic_config(); 237 } 238 239 static void handle___vgic_v3_init_lrs(struct kvm_cpu_context *host_ctxt) 240 { 241 __vgic_v3_init_lrs(); 242 } 243 244 static void handle___kvm_get_mdcr_el2(struct kvm_cpu_context *host_ctxt) 245 { 246 cpu_reg(host_ctxt, 1) = __kvm_get_mdcr_el2(); 247 } 248 249 static void handle___vgic_v3_save_vmcr_aprs(struct kvm_cpu_context *host_ctxt) 250 { 251 DECLARE_REG(struct vgic_v3_cpu_if *, cpu_if, host_ctxt, 1); 252 253 __vgic_v3_save_vmcr_aprs(kern_hyp_va(cpu_if)); 254 } 255 256 static void handle___vgic_v3_restore_vmcr_aprs(struct kvm_cpu_context *host_ctxt) 257 { 258 DECLARE_REG(struct vgic_v3_cpu_if *, cpu_if, host_ctxt, 1); 259 260 __vgic_v3_restore_vmcr_aprs(kern_hyp_va(cpu_if)); 261 } 262 263 static void handle___pkvm_init(struct kvm_cpu_context *host_ctxt) 264 { 265 DECLARE_REG(phys_addr_t, phys, host_ctxt, 1); 266 DECLARE_REG(unsigned long, size, host_ctxt, 2); 267 DECLARE_REG(unsigned long, nr_cpus, host_ctxt, 3); 268 DECLARE_REG(unsigned long *, per_cpu_base, host_ctxt, 4); 269 DECLARE_REG(u32, hyp_va_bits, host_ctxt, 5); 270 271 /* 272 * __pkvm_init() will return only if an error occurred, otherwise it 273 * will tail-call in __pkvm_init_finalise() which will have to deal 274 * with the host context directly. 275 */ 276 cpu_reg(host_ctxt, 1) = __pkvm_init(phys, size, nr_cpus, per_cpu_base, 277 hyp_va_bits); 278 } 279 280 static void handle___pkvm_cpu_set_vector(struct kvm_cpu_context *host_ctxt) 281 { 282 DECLARE_REG(enum arm64_hyp_spectre_vector, slot, host_ctxt, 1); 283 284 cpu_reg(host_ctxt, 1) = pkvm_cpu_set_vector(slot); 285 } 286 287 static void handle___pkvm_host_share_hyp(struct kvm_cpu_context *host_ctxt) 288 { 289 DECLARE_REG(u64, pfn, host_ctxt, 1); 290 291 cpu_reg(host_ctxt, 1) = __pkvm_host_share_hyp(pfn); 292 } 293 294 static void handle___pkvm_host_unshare_hyp(struct kvm_cpu_context *host_ctxt) 295 { 296 DECLARE_REG(u64, pfn, host_ctxt, 1); 297 298 cpu_reg(host_ctxt, 1) = __pkvm_host_unshare_hyp(pfn); 299 } 300 301 static void handle___pkvm_create_private_mapping(struct kvm_cpu_context *host_ctxt) 302 { 303 DECLARE_REG(phys_addr_t, phys, host_ctxt, 1); 304 DECLARE_REG(size_t, size, host_ctxt, 2); 305 DECLARE_REG(enum kvm_pgtable_prot, prot, host_ctxt, 3); 306 307 /* 308 * __pkvm_create_private_mapping() populates a pointer with the 309 * hypervisor start address of the allocation. 310 * 311 * However, handle___pkvm_create_private_mapping() hypercall crosses the 312 * EL1/EL2 boundary so the pointer would not be valid in this context. 313 * 314 * Instead pass the allocation address as the return value (or return 315 * ERR_PTR() on failure). 316 */ 317 unsigned long haddr; 318 int err = __pkvm_create_private_mapping(phys, size, prot, &haddr); 319 320 if (err) 321 haddr = (unsigned long)ERR_PTR(err); 322 323 cpu_reg(host_ctxt, 1) = haddr; 324 } 325 326 static void handle___pkvm_prot_finalize(struct kvm_cpu_context *host_ctxt) 327 { 328 cpu_reg(host_ctxt, 1) = __pkvm_prot_finalize(); 329 } 330 331 static void handle___pkvm_vcpu_init_traps(struct kvm_cpu_context *host_ctxt) 332 { 333 DECLARE_REG(struct kvm_vcpu *, vcpu, host_ctxt, 1); 334 335 __pkvm_vcpu_init_traps(kern_hyp_va(vcpu)); 336 } 337 338 static void handle___pkvm_init_vm(struct kvm_cpu_context *host_ctxt) 339 { 340 DECLARE_REG(struct kvm *, host_kvm, host_ctxt, 1); 341 DECLARE_REG(unsigned long, vm_hva, host_ctxt, 2); 342 DECLARE_REG(unsigned long, pgd_hva, host_ctxt, 3); 343 344 host_kvm = kern_hyp_va(host_kvm); 345 cpu_reg(host_ctxt, 1) = __pkvm_init_vm(host_kvm, vm_hva, pgd_hva); 346 } 347 348 static void handle___pkvm_init_vcpu(struct kvm_cpu_context *host_ctxt) 349 { 350 DECLARE_REG(pkvm_handle_t, handle, host_ctxt, 1); 351 DECLARE_REG(struct kvm_vcpu *, host_vcpu, host_ctxt, 2); 352 DECLARE_REG(unsigned long, vcpu_hva, host_ctxt, 3); 353 354 host_vcpu = kern_hyp_va(host_vcpu); 355 cpu_reg(host_ctxt, 1) = __pkvm_init_vcpu(handle, host_vcpu, vcpu_hva); 356 } 357 358 static void handle___pkvm_teardown_vm(struct kvm_cpu_context *host_ctxt) 359 { 360 DECLARE_REG(pkvm_handle_t, handle, host_ctxt, 1); 361 362 cpu_reg(host_ctxt, 1) = __pkvm_teardown_vm(handle); 363 } 364 365 typedef void (*hcall_t)(struct kvm_cpu_context *); 366 367 #define HANDLE_FUNC(x) [__KVM_HOST_SMCCC_FUNC_##x] = (hcall_t)handle_##x 368 369 static const hcall_t host_hcall[] = { 370 /* ___kvm_hyp_init */ 371 HANDLE_FUNC(__kvm_get_mdcr_el2), 372 HANDLE_FUNC(__pkvm_init), 373 HANDLE_FUNC(__pkvm_create_private_mapping), 374 HANDLE_FUNC(__pkvm_cpu_set_vector), 375 HANDLE_FUNC(__kvm_enable_ssbs), 376 HANDLE_FUNC(__vgic_v3_init_lrs), 377 HANDLE_FUNC(__vgic_v3_get_gic_config), 378 HANDLE_FUNC(__pkvm_prot_finalize), 379 380 HANDLE_FUNC(__pkvm_host_share_hyp), 381 HANDLE_FUNC(__pkvm_host_unshare_hyp), 382 HANDLE_FUNC(__kvm_adjust_pc), 383 HANDLE_FUNC(__kvm_vcpu_run), 384 HANDLE_FUNC(__kvm_flush_vm_context), 385 HANDLE_FUNC(__kvm_tlb_flush_vmid_ipa), 386 HANDLE_FUNC(__kvm_tlb_flush_vmid_ipa_nsh), 387 HANDLE_FUNC(__kvm_tlb_flush_vmid), 388 HANDLE_FUNC(__kvm_tlb_flush_vmid_range), 389 HANDLE_FUNC(__kvm_flush_cpu_context), 390 HANDLE_FUNC(__kvm_timer_set_cntvoff), 391 HANDLE_FUNC(__vgic_v3_save_vmcr_aprs), 392 HANDLE_FUNC(__vgic_v3_restore_vmcr_aprs), 393 HANDLE_FUNC(__pkvm_vcpu_init_traps), 394 HANDLE_FUNC(__pkvm_init_vm), 395 HANDLE_FUNC(__pkvm_init_vcpu), 396 HANDLE_FUNC(__pkvm_teardown_vm), 397 }; 398 399 static void handle_host_hcall(struct kvm_cpu_context *host_ctxt) 400 { 401 DECLARE_REG(unsigned long, id, host_ctxt, 0); 402 unsigned long hcall_min = 0; 403 hcall_t hfn; 404 405 /* 406 * If pKVM has been initialised then reject any calls to the 407 * early "privileged" hypercalls. Note that we cannot reject 408 * calls to __pkvm_prot_finalize for two reasons: (1) The static 409 * key used to determine initialisation must be toggled prior to 410 * finalisation and (2) finalisation is performed on a per-CPU 411 * basis. This is all fine, however, since __pkvm_prot_finalize 412 * returns -EPERM after the first call for a given CPU. 413 */ 414 if (static_branch_unlikely(&kvm_protected_mode_initialized)) 415 hcall_min = __KVM_HOST_SMCCC_FUNC___pkvm_prot_finalize; 416 417 id &= ~ARM_SMCCC_CALL_HINTS; 418 id -= KVM_HOST_SMCCC_ID(0); 419 420 if (unlikely(id < hcall_min || id >= ARRAY_SIZE(host_hcall))) 421 goto inval; 422 423 hfn = host_hcall[id]; 424 if (unlikely(!hfn)) 425 goto inval; 426 427 cpu_reg(host_ctxt, 0) = SMCCC_RET_SUCCESS; 428 hfn(host_ctxt); 429 430 return; 431 inval: 432 cpu_reg(host_ctxt, 0) = SMCCC_RET_NOT_SUPPORTED; 433 } 434 435 static void default_host_smc_handler(struct kvm_cpu_context *host_ctxt) 436 { 437 __kvm_hyp_host_forward_smc(host_ctxt); 438 } 439 440 static void handle_host_smc(struct kvm_cpu_context *host_ctxt) 441 { 442 DECLARE_REG(u64, func_id, host_ctxt, 0); 443 bool handled; 444 445 func_id &= ~ARM_SMCCC_CALL_HINTS; 446 447 handled = kvm_host_psci_handler(host_ctxt, func_id); 448 if (!handled) 449 handled = kvm_host_ffa_handler(host_ctxt, func_id); 450 if (!handled) 451 default_host_smc_handler(host_ctxt); 452 453 /* SMC was trapped, move ELR past the current PC. */ 454 kvm_skip_host_instr(); 455 } 456 457 void handle_trap(struct kvm_cpu_context *host_ctxt) 458 { 459 u64 esr = read_sysreg_el2(SYS_ESR); 460 461 switch (ESR_ELx_EC(esr)) { 462 case ESR_ELx_EC_HVC64: 463 handle_host_hcall(host_ctxt); 464 break; 465 case ESR_ELx_EC_SMC64: 466 handle_host_smc(host_ctxt); 467 break; 468 case ESR_ELx_EC_SVE: 469 cpacr_clear_set(0, CPACR_ELx_ZEN); 470 isb(); 471 sve_cond_update_zcr_vq(ZCR_ELx_LEN_MASK, SYS_ZCR_EL2); 472 break; 473 case ESR_ELx_EC_IABT_LOW: 474 case ESR_ELx_EC_DABT_LOW: 475 handle_host_mem_abort(host_ctxt); 476 break; 477 default: 478 BUG(); 479 } 480 } 481