1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Fault injection for both 32 and 64bit guests. 4 * 5 * Copyright (C) 2012,2013 - ARM Ltd 6 * Author: Marc Zyngier <marc.zyngier@arm.com> 7 * 8 * Based on arch/arm/kvm/emulate.c 9 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 10 * Author: Christoffer Dall <c.dall@virtualopensystems.com> 11 */ 12 13 #include <hyp/adjust_pc.h> 14 #include <linux/kvm_host.h> 15 #include <asm/kvm_emulate.h> 16 #include <asm/kvm_mmu.h> 17 #include <asm/kvm_nested.h> 18 19 #if !defined (__KVM_NVHE_HYPERVISOR__) && !defined (__KVM_VHE_HYPERVISOR__) 20 #error Hypervisor code only! 21 #endif 22 23 static void __vcpu_write_spsr(struct kvm_vcpu *vcpu, unsigned long target_mode, 24 u64 val) 25 { 26 if (has_vhe()) { 27 if (target_mode == PSR_MODE_EL1h) 28 vcpu_write_sys_reg(vcpu, val, SPSR_EL1); 29 else 30 vcpu_write_sys_reg(vcpu, val, SPSR_EL2); 31 } else { 32 __vcpu_assign_sys_reg(vcpu, SPSR_EL1, val); 33 } 34 } 35 36 static void __vcpu_write_spsr_abt(struct kvm_vcpu *vcpu, u64 val) 37 { 38 if (has_vhe() && vcpu_get_flag(vcpu, SYSREGS_ON_CPU)) 39 write_sysreg(val, spsr_abt); 40 else 41 vcpu->arch.ctxt.spsr_abt = val; 42 } 43 44 static void __vcpu_write_spsr_und(struct kvm_vcpu *vcpu, u64 val) 45 { 46 if (has_vhe() && vcpu_get_flag(vcpu, SYSREGS_ON_CPU)) 47 write_sysreg(val, spsr_und); 48 else 49 vcpu->arch.ctxt.spsr_und = val; 50 } 51 52 /* 53 * This performs the exception entry at a given EL (@target_mode), stashing PC 54 * and PSTATE into ELR and SPSR respectively, and compute the new PC/PSTATE. 55 * The EL passed to this function *must* be a non-secure, privileged mode with 56 * bit 0 being set (PSTATE.SP == 1). 57 * 58 * When an exception is taken, most PSTATE fields are left unchanged in the 59 * handler. However, some are explicitly overridden (e.g. M[4:0]). Luckily all 60 * of the inherited bits have the same position in the AArch64/AArch32 SPSR_ELx 61 * layouts, so we don't need to shuffle these for exceptions from AArch32 EL0. 62 * 63 * For the SPSR_ELx layout for AArch64, see ARM DDI 0487E.a page C5-429. 64 * For the SPSR_ELx layout for AArch32, see ARM DDI 0487E.a page C5-426. 65 * 66 * Here we manipulate the fields in order of the AArch64 SPSR_ELx layout, from 67 * MSB to LSB. 68 */ 69 static void enter_exception64(struct kvm_vcpu *vcpu, unsigned long target_mode, 70 enum exception_type type) 71 { 72 unsigned long sctlr, vbar, old, new, mode; 73 struct kvm *kvm; 74 u64 exc_offset; 75 76 mode = *vcpu_cpsr(vcpu) & (PSR_MODE_MASK | PSR_MODE32_BIT); 77 78 if (mode == target_mode) 79 exc_offset = CURRENT_EL_SP_ELx_VECTOR; 80 else if ((mode | PSR_MODE_THREAD_BIT) == target_mode) 81 exc_offset = CURRENT_EL_SP_EL0_VECTOR; 82 else if (!(mode & PSR_MODE32_BIT)) 83 exc_offset = LOWER_EL_AArch64_VECTOR; 84 else 85 exc_offset = LOWER_EL_AArch32_VECTOR; 86 87 switch (target_mode) { 88 case PSR_MODE_EL1h: 89 vbar = vcpu_read_sys_reg(vcpu, VBAR_EL1); 90 sctlr = vcpu_read_sys_reg(vcpu, SCTLR_EL1); 91 vcpu_write_sys_reg(vcpu, *vcpu_pc(vcpu), ELR_EL1); 92 break; 93 case PSR_MODE_EL2h: 94 vbar = vcpu_read_sys_reg(vcpu, VBAR_EL2); 95 sctlr = vcpu_read_sys_reg(vcpu, SCTLR_EL2); 96 vcpu_write_sys_reg(vcpu, *vcpu_pc(vcpu), ELR_EL2); 97 break; 98 default: 99 /* Don't do that */ 100 BUG(); 101 } 102 103 *vcpu_pc(vcpu) = vbar + exc_offset + type; 104 105 old = *vcpu_cpsr(vcpu); 106 new = 0; 107 108 new |= (old & PSR_N_BIT); 109 new |= (old & PSR_Z_BIT); 110 new |= (old & PSR_C_BIT); 111 new |= (old & PSR_V_BIT); 112 113 kvm = vcpu_get_kvm(vcpu); 114 if (kvm && kvm_has_mte(kvm)) 115 new |= PSR_TCO_BIT; 116 vcpu_put_kvm(vcpu, kvm); 117 118 new |= (old & PSR_DIT_BIT); 119 120 // PSTATE.UAO is set to zero upon any exception to AArch64 121 // See ARM DDI 0487E.a, page D5-2579. 122 123 // PSTATE.PAN is unchanged unless SCTLR_ELx.SPAN == 0b0 124 // SCTLR_ELx.SPAN is RES1 when ARMv8.1-PAN is not implemented 125 // See ARM DDI 0487E.a, page D5-2578. 126 new |= (old & PSR_PAN_BIT); 127 if (!(sctlr & SCTLR_EL1_SPAN)) 128 new |= PSR_PAN_BIT; 129 130 // PSTATE.SS is set to zero upon any exception to AArch64 131 // See ARM DDI 0487E.a, page D2-2452. 132 133 // PSTATE.IL is set to zero upon any exception to AArch64 134 // See ARM DDI 0487E.a, page D1-2306. 135 136 // PSTATE.SSBS is set to SCTLR_ELx.DSSBS upon any exception to AArch64 137 // See ARM DDI 0487E.a, page D13-3258 138 if (sctlr & SCTLR_ELx_DSSBS) 139 new |= PSR_SSBS_BIT; 140 141 // PSTATE.BTYPE is set to zero upon any exception to AArch64 142 // See ARM DDI 0487E.a, pages D1-2293 to D1-2294. 143 144 new |= PSR_D_BIT; 145 new |= PSR_A_BIT; 146 new |= PSR_I_BIT; 147 new |= PSR_F_BIT; 148 149 new |= target_mode; 150 151 *vcpu_cpsr(vcpu) = new; 152 __vcpu_write_spsr(vcpu, target_mode, old); 153 } 154 155 /* 156 * When an exception is taken, most CPSR fields are left unchanged in the 157 * handler. However, some are explicitly overridden (e.g. M[4:0]). 158 * 159 * The SPSR/SPSR_ELx layouts differ, and the below is intended to work with 160 * either format. Note: SPSR.J bit doesn't exist in SPSR_ELx, but this bit was 161 * obsoleted by the ARMv7 virtualization extensions and is RES0. 162 * 163 * For the SPSR layout seen from AArch32, see: 164 * - ARM DDI 0406C.d, page B1-1148 165 * - ARM DDI 0487E.a, page G8-6264 166 * 167 * For the SPSR_ELx layout for AArch32 seen from AArch64, see: 168 * - ARM DDI 0487E.a, page C5-426 169 * 170 * Here we manipulate the fields in order of the AArch32 SPSR_ELx layout, from 171 * MSB to LSB. 172 */ 173 static unsigned long get_except32_cpsr(struct kvm_vcpu *vcpu, u32 mode) 174 { 175 u32 sctlr = vcpu_read_sys_reg(vcpu, SCTLR_EL1); 176 unsigned long old, new; 177 178 old = *vcpu_cpsr(vcpu); 179 new = 0; 180 181 new |= (old & PSR_AA32_N_BIT); 182 new |= (old & PSR_AA32_Z_BIT); 183 new |= (old & PSR_AA32_C_BIT); 184 new |= (old & PSR_AA32_V_BIT); 185 new |= (old & PSR_AA32_Q_BIT); 186 187 // CPSR.IT[7:0] are set to zero upon any exception 188 // See ARM DDI 0487E.a, section G1.12.3 189 // See ARM DDI 0406C.d, section B1.8.3 190 191 new |= (old & PSR_AA32_DIT_BIT); 192 193 // CPSR.SSBS is set to SCTLR.DSSBS upon any exception 194 // See ARM DDI 0487E.a, page G8-6244 195 if (sctlr & BIT(31)) 196 new |= PSR_AA32_SSBS_BIT; 197 198 // CPSR.PAN is unchanged unless SCTLR.SPAN == 0b0 199 // SCTLR.SPAN is RES1 when ARMv8.1-PAN is not implemented 200 // See ARM DDI 0487E.a, page G8-6246 201 new |= (old & PSR_AA32_PAN_BIT); 202 if (!(sctlr & BIT(23))) 203 new |= PSR_AA32_PAN_BIT; 204 205 // SS does not exist in AArch32, so ignore 206 207 // CPSR.IL is set to zero upon any exception 208 // See ARM DDI 0487E.a, page G1-5527 209 210 new |= (old & PSR_AA32_GE_MASK); 211 212 // CPSR.IT[7:0] are set to zero upon any exception 213 // See prior comment above 214 215 // CPSR.E is set to SCTLR.EE upon any exception 216 // See ARM DDI 0487E.a, page G8-6245 217 // See ARM DDI 0406C.d, page B4-1701 218 if (sctlr & BIT(25)) 219 new |= PSR_AA32_E_BIT; 220 221 // CPSR.A is unchanged upon an exception to Undefined, Supervisor 222 // CPSR.A is set upon an exception to other modes 223 // See ARM DDI 0487E.a, pages G1-5515 to G1-5516 224 // See ARM DDI 0406C.d, page B1-1182 225 new |= (old & PSR_AA32_A_BIT); 226 if (mode != PSR_AA32_MODE_UND && mode != PSR_AA32_MODE_SVC) 227 new |= PSR_AA32_A_BIT; 228 229 // CPSR.I is set upon any exception 230 // See ARM DDI 0487E.a, pages G1-5515 to G1-5516 231 // See ARM DDI 0406C.d, page B1-1182 232 new |= PSR_AA32_I_BIT; 233 234 // CPSR.F is set upon an exception to FIQ 235 // CPSR.F is unchanged upon an exception to other modes 236 // See ARM DDI 0487E.a, pages G1-5515 to G1-5516 237 // See ARM DDI 0406C.d, page B1-1182 238 new |= (old & PSR_AA32_F_BIT); 239 if (mode == PSR_AA32_MODE_FIQ) 240 new |= PSR_AA32_F_BIT; 241 242 // CPSR.T is set to SCTLR.TE upon any exception 243 // See ARM DDI 0487E.a, page G8-5514 244 // See ARM DDI 0406C.d, page B1-1181 245 if (sctlr & BIT(30)) 246 new |= PSR_AA32_T_BIT; 247 248 new |= mode; 249 250 return new; 251 } 252 253 /* 254 * Table taken from ARMv8 ARM DDI0487B-B, table G1-10. 255 */ 256 static const u8 return_offsets[8][2] = { 257 [0] = { 0, 0 }, /* Reset, unused */ 258 [1] = { 4, 2 }, /* Undefined */ 259 [2] = { 0, 0 }, /* SVC, unused */ 260 [3] = { 4, 4 }, /* Prefetch abort */ 261 [4] = { 8, 8 }, /* Data abort */ 262 [5] = { 0, 0 }, /* HVC, unused */ 263 [6] = { 4, 4 }, /* IRQ, unused */ 264 [7] = { 4, 4 }, /* FIQ, unused */ 265 }; 266 267 static void enter_exception32(struct kvm_vcpu *vcpu, u32 mode, u32 vect_offset) 268 { 269 unsigned long spsr = *vcpu_cpsr(vcpu); 270 bool is_thumb = (spsr & PSR_AA32_T_BIT); 271 u32 sctlr = vcpu_read_sys_reg(vcpu, SCTLR_EL1); 272 u32 return_address; 273 274 *vcpu_cpsr(vcpu) = get_except32_cpsr(vcpu, mode); 275 return_address = *vcpu_pc(vcpu); 276 return_address += return_offsets[vect_offset >> 2][is_thumb]; 277 278 /* KVM only enters the ABT and UND modes, so only deal with those */ 279 switch(mode) { 280 case PSR_AA32_MODE_ABT: 281 __vcpu_write_spsr_abt(vcpu, host_spsr_to_spsr32(spsr)); 282 vcpu_gp_regs(vcpu)[__compat_lr_abt] = return_address; 283 break; 284 285 case PSR_AA32_MODE_UND: 286 __vcpu_write_spsr_und(vcpu, host_spsr_to_spsr32(spsr)); 287 vcpu_gp_regs(vcpu)[__compat_lr_und] = return_address; 288 break; 289 } 290 291 /* Branch to exception vector */ 292 if (sctlr & (1 << 13)) 293 vect_offset += 0xffff0000; 294 else /* always have security exceptions */ 295 vect_offset += vcpu_read_sys_reg(vcpu, VBAR_EL1); 296 297 *vcpu_pc(vcpu) = vect_offset; 298 } 299 300 static void kvm_inject_exception(struct kvm_vcpu *vcpu) 301 { 302 if (vcpu_el1_is_32bit(vcpu)) { 303 switch (vcpu_get_flag(vcpu, EXCEPT_MASK)) { 304 case unpack_vcpu_flag(EXCEPT_AA32_UND): 305 enter_exception32(vcpu, PSR_AA32_MODE_UND, 4); 306 break; 307 case unpack_vcpu_flag(EXCEPT_AA32_IABT): 308 enter_exception32(vcpu, PSR_AA32_MODE_ABT, 12); 309 break; 310 case unpack_vcpu_flag(EXCEPT_AA32_DABT): 311 enter_exception32(vcpu, PSR_AA32_MODE_ABT, 16); 312 break; 313 default: 314 /* Err... */ 315 break; 316 } 317 } else { 318 switch (vcpu_get_flag(vcpu, EXCEPT_MASK)) { 319 case unpack_vcpu_flag(EXCEPT_AA64_EL1_SYNC): 320 enter_exception64(vcpu, PSR_MODE_EL1h, except_type_sync); 321 break; 322 323 case unpack_vcpu_flag(EXCEPT_AA64_EL1_SERR): 324 enter_exception64(vcpu, PSR_MODE_EL1h, except_type_serror); 325 break; 326 327 case unpack_vcpu_flag(EXCEPT_AA64_EL2_SYNC): 328 enter_exception64(vcpu, PSR_MODE_EL2h, except_type_sync); 329 break; 330 331 case unpack_vcpu_flag(EXCEPT_AA64_EL2_IRQ): 332 enter_exception64(vcpu, PSR_MODE_EL2h, except_type_irq); 333 break; 334 335 case unpack_vcpu_flag(EXCEPT_AA64_EL2_SERR): 336 enter_exception64(vcpu, PSR_MODE_EL2h, except_type_serror); 337 break; 338 339 default: 340 /* 341 * Only EL1_{SYNC,SERR} and EL2_{SYNC,IRQ,SERR} makes 342 * sense so far. Everything else gets silently 343 * ignored. 344 */ 345 break; 346 } 347 } 348 } 349 350 /* 351 * Adjust the guest PC (and potentially exception state) depending on 352 * flags provided by the emulation code. 353 */ 354 void __kvm_adjust_pc(struct kvm_vcpu *vcpu) 355 { 356 struct kvm_vcpu *target = kvm_adjust_pc_get(vcpu); 357 358 if (!target) 359 return; 360 361 if (vcpu_get_flag(target, PENDING_EXCEPTION)) { 362 kvm_inject_exception(target); 363 vcpu_clear_flag(target, PENDING_EXCEPTION); 364 vcpu_clear_flag(target, EXCEPT_MASK); 365 } else if (vcpu_get_flag(target, INCREMENT_PC)) { 366 kvm_skip_instr(target); 367 vcpu_clear_flag(target, INCREMENT_PC); 368 } 369 370 kvm_adjust_pc_put(vcpu, target); 371 } 372