1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright (C) 2015 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7#include <linux/linkage.h> 8 9#include <asm/alternative.h> 10#include <asm/assembler.h> 11#include <asm/kvm.h> 12#include <asm/kvm_arm.h> 13#include <asm/kvm_asm.h> 14#include <asm/kvm_mmu.h> 15#include <asm/kvm_mte.h> 16#include <asm/kvm_ptrauth.h> 17 18 .text 19 20/* 21 * u64 __guest_enter(struct kvm_vcpu *vcpu); 22 */ 23SYM_FUNC_START(__guest_enter) 24 // x0: vcpu 25 // x1-x17: clobbered by macros 26 // x29: guest context 27 28 adr_this_cpu x1, kvm_hyp_ctxt, x2 29 30 // Store the hyp regs 31 save_callee_saved_regs x1 32 33 // Save hyp's sp_el0 34 save_sp_el0 x1, x2 35 36 // Now the hyp state is stored if we have a pending RAS SError it must 37 // affect the host or hyp. If any asynchronous exception is pending we 38 // defer the guest entry. The DSB isn't necessary before v8.2 as any 39 // SError would be fatal. 40alternative_if ARM64_HAS_RAS_EXTN 41 dsb nshst 42 isb 43alternative_else_nop_endif 44 mrs x1, isr_el1 45 cbz x1, 1f 46 47 // Ensure that __guest_enter() always provides a context 48 // synchronization event so that callers don't need ISBs for anything 49 // that would usually be synchonized by the ERET. 50 isb 51 mov x0, #ARM_EXCEPTION_IRQ 52 ret 53 541: 55 set_loaded_vcpu x0, x1, x2 56 57 add x29, x0, #VCPU_CONTEXT 58 59 // mte_switch_to_guest(g_ctxt, h_ctxt, tmp1) 60 mte_switch_to_guest x29, x1, x2 61 62 // Macro ptrauth_switch_to_guest format: 63 // ptrauth_switch_to_guest(guest cxt, tmp1, tmp2, tmp3) 64 // The below macro to restore guest keys is not implemented in C code 65 // as it may cause Pointer Authentication key signing mismatch errors 66 // when this feature is enabled for kernel code. 67 ptrauth_switch_to_guest x29, x0, x1, x2 68 69 // Restore the guest's sp_el0 70 restore_sp_el0 x29, x0 71 72 // Restore guest regs x0-x17 73 ldp x0, x1, [x29, #CPU_XREG_OFFSET(0)] 74 ldp x2, x3, [x29, #CPU_XREG_OFFSET(2)] 75 ldp x4, x5, [x29, #CPU_XREG_OFFSET(4)] 76 ldp x6, x7, [x29, #CPU_XREG_OFFSET(6)] 77 ldp x8, x9, [x29, #CPU_XREG_OFFSET(8)] 78 ldp x10, x11, [x29, #CPU_XREG_OFFSET(10)] 79 ldp x12, x13, [x29, #CPU_XREG_OFFSET(12)] 80 ldp x14, x15, [x29, #CPU_XREG_OFFSET(14)] 81 ldp x16, x17, [x29, #CPU_XREG_OFFSET(16)] 82 83 // Restore guest regs x18-x29, lr 84 restore_callee_saved_regs x29 85 86 // Do not touch any register after this! 87 eret 88 sb 89 90SYM_INNER_LABEL(__guest_exit_restore_elr_and_panic, SYM_L_GLOBAL) 91 // x2-x29,lr: vcpu regs 92 // vcpu x0-x1 on the stack 93 94 adr_this_cpu x0, kvm_hyp_ctxt, x1 95 ldr x0, [x0, #CPU_ELR_EL2] 96 msr elr_el2, x0 97 98SYM_INNER_LABEL(__guest_exit_panic, SYM_L_GLOBAL) 99 // x2-x29,lr: vcpu regs 100 // vcpu x0-x1 on the stack 101 102 // If the hyp context is loaded, go straight to hyp_panic 103 get_loaded_vcpu x0, x1 104 cbnz x0, 1f 105 b hyp_panic 106 1071: 108 // The hyp context is saved so make sure it is restored to allow 109 // hyp_panic to run at hyp and, subsequently, panic to run in the host. 110 // This makes use of __guest_exit to avoid duplication but sets the 111 // return address to tail call into hyp_panic. As a side effect, the 112 // current state is saved to the guest context but it will only be 113 // accurate if the guest had been completely restored. 114 adr_this_cpu x0, kvm_hyp_ctxt, x1 115 adr_l x1, hyp_panic 116 str x1, [x0, #CPU_XREG_OFFSET(30)] 117 118 get_vcpu_ptr x1, x0 119 120SYM_INNER_LABEL(__guest_exit, SYM_L_GLOBAL) 121 // x0: return code 122 // x1: vcpu 123 // x2-x29,lr: vcpu regs 124 // vcpu x0-x1 on the stack 125 126 add x1, x1, #VCPU_CONTEXT 127 128 ALTERNATIVE(nop, SET_PSTATE_PAN(1), ARM64_HAS_PAN) 129 130 // Store the guest regs x2 and x3 131 stp x2, x3, [x1, #CPU_XREG_OFFSET(2)] 132 133 // Retrieve the guest regs x0-x1 from the stack 134 ldp x2, x3, [sp], #16 // x0, x1 135 136 // Store the guest regs x0-x1 and x4-x17 137 stp x2, x3, [x1, #CPU_XREG_OFFSET(0)] 138 stp x4, x5, [x1, #CPU_XREG_OFFSET(4)] 139 stp x6, x7, [x1, #CPU_XREG_OFFSET(6)] 140 stp x8, x9, [x1, #CPU_XREG_OFFSET(8)] 141 stp x10, x11, [x1, #CPU_XREG_OFFSET(10)] 142 stp x12, x13, [x1, #CPU_XREG_OFFSET(12)] 143 stp x14, x15, [x1, #CPU_XREG_OFFSET(14)] 144 stp x16, x17, [x1, #CPU_XREG_OFFSET(16)] 145 146 // Store the guest regs x18-x29, lr 147 save_callee_saved_regs x1 148 149 // Store the guest's sp_el0 150 save_sp_el0 x1, x2 151 152 adr_this_cpu x2, kvm_hyp_ctxt, x3 153 154 // Macro ptrauth_switch_to_hyp format: 155 // ptrauth_switch_to_hyp(guest cxt, host cxt, tmp1, tmp2, tmp3) 156 // The below macro to save/restore keys is not implemented in C code 157 // as it may cause Pointer Authentication key signing mismatch errors 158 // when this feature is enabled for kernel code. 159 ptrauth_switch_to_hyp x1, x2, x3, x4, x5 160 161 // mte_switch_to_hyp(g_ctxt, h_ctxt, reg1) 162 mte_switch_to_hyp x1, x2, x3 163 164 // Restore hyp's sp_el0 165 restore_sp_el0 x2, x3 166 167 // Now restore the hyp regs 168 restore_callee_saved_regs x2 169 170 set_loaded_vcpu xzr, x2, x3 171 172alternative_if ARM64_HAS_RAS_EXTN 173 // If we have the RAS extensions we can consume a pending error 174 // without an unmask-SError and isb. The ESB-instruction consumed any 175 // pending guest error when we took the exception from the guest. 176 mrs_s x2, SYS_DISR_EL1 177 str x2, [x1, #(VCPU_FAULT_DISR - VCPU_CONTEXT)] 178 cbz x2, 1f 179 msr_s SYS_DISR_EL1, xzr 180 orr x0, x0, #(1<<ARM_EXIT_WITH_SERROR_BIT) 1811: ret 182alternative_else 183 dsb sy // Synchronize against in-flight ld/st 184 isb // Prevent an early read of side-effect free ISR 185 mrs x2, isr_el1 186 tbnz x2, #ISR_EL1_A_SHIFT, 2f 187 ret 188 nop 1892: 190alternative_endif 191 // We know we have a pending asynchronous abort, now is the 192 // time to flush it out. From your VAXorcist book, page 666: 193 // "Threaten me not, oh Evil one! For I speak with 194 // the power of DEC, and I command thee to show thyself!" 195 mrs x2, elr_el2 196 mrs x3, esr_el2 197 mrs x4, spsr_el2 198 mov x5, x0 199 200 msr daifclr, #4 // Unmask aborts 201 202 // This is our single instruction exception window. A pending 203 // SError is guaranteed to occur at the earliest when we unmask 204 // it, and at the latest just after the ISB. 205abort_guest_exit_start: 206 207 isb 208 209abort_guest_exit_end: 210 211 msr daifset, #4 // Mask aborts 212 ret 213 214 _kvm_extable abort_guest_exit_start, 9997f 215 _kvm_extable abort_guest_exit_end, 9997f 2169997: 217 msr daifset, #4 // Mask aborts 218 mov x0, #(1 << ARM_EXIT_WITH_SERROR_BIT) 219 220 // restore the EL1 exception context so that we can report some 221 // information. Merge the exception code with the SError pending bit. 222 msr elr_el2, x2 223 msr esr_el2, x3 224 msr spsr_el2, x4 225 orr x0, x0, x5 2261: ret 227SYM_FUNC_END(__guest_enter) 228