1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/kvm/handle_exit.c: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Author: Christoffer Dall <c.dall@virtualopensystems.com> 9 */ 10 11 #include <linux/kvm.h> 12 #include <linux/kvm_host.h> 13 14 #include <asm/esr.h> 15 #include <asm/exception.h> 16 #include <asm/kvm_asm.h> 17 #include <asm/kvm_emulate.h> 18 #include <asm/kvm_mmu.h> 19 #include <asm/kvm_nested.h> 20 #include <asm/debug-monitors.h> 21 #include <asm/stacktrace/nvhe.h> 22 #include <asm/traps.h> 23 24 #include <kvm/arm_hypercalls.h> 25 26 #define CREATE_TRACE_POINTS 27 #include "trace_handle_exit.h" 28 29 typedef int (*exit_handle_fn)(struct kvm_vcpu *); 30 31 static void kvm_handle_guest_serror(struct kvm_vcpu *vcpu, u64 esr) 32 { 33 if (!arm64_is_ras_serror(esr) || arm64_is_fatal_ras_serror(NULL, esr)) 34 kvm_inject_vabt(vcpu); 35 } 36 37 static int handle_hvc(struct kvm_vcpu *vcpu) 38 { 39 trace_kvm_hvc_arm64(*vcpu_pc(vcpu), vcpu_get_reg(vcpu, 0), 40 kvm_vcpu_hvc_get_imm(vcpu)); 41 vcpu->stat.hvc_exit_stat++; 42 43 /* Forward hvc instructions to the virtual EL2 if the guest has EL2. */ 44 if (vcpu_has_nv(vcpu)) { 45 if (vcpu_read_sys_reg(vcpu, HCR_EL2) & HCR_HCD) 46 kvm_inject_undefined(vcpu); 47 else 48 kvm_inject_nested_sync(vcpu, kvm_vcpu_get_esr(vcpu)); 49 50 return 1; 51 } 52 53 return kvm_smccc_call_handler(vcpu); 54 } 55 56 static int handle_smc(struct kvm_vcpu *vcpu) 57 { 58 /* 59 * Forward this trapped smc instruction to the virtual EL2 if 60 * the guest has asked for it. 61 */ 62 if (forward_smc_trap(vcpu)) 63 return 1; 64 65 /* 66 * "If an SMC instruction executed at Non-secure EL1 is 67 * trapped to EL2 because HCR_EL2.TSC is 1, the exception is a 68 * Trap exception, not a Secure Monitor Call exception [...]" 69 * 70 * We need to advance the PC after the trap, as it would 71 * otherwise return to the same address. Furthermore, pre-incrementing 72 * the PC before potentially exiting to userspace maintains the same 73 * abstraction for both SMCs and HVCs. 74 */ 75 kvm_incr_pc(vcpu); 76 77 /* 78 * SMCs with a nonzero immediate are reserved according to DEN0028E 2.9 79 * "SMC and HVC immediate value". 80 */ 81 if (kvm_vcpu_hvc_get_imm(vcpu)) { 82 vcpu_set_reg(vcpu, 0, ~0UL); 83 return 1; 84 } 85 86 /* 87 * If imm is zero then it is likely an SMCCC call. 88 * 89 * Note that on ARMv8.3, even if EL3 is not implemented, SMC executed 90 * at Non-secure EL1 is trapped to EL2 if HCR_EL2.TSC==1, rather than 91 * being treated as UNDEFINED. 92 */ 93 return kvm_smccc_call_handler(vcpu); 94 } 95 96 /* 97 * Guest access to FP/ASIMD registers are routed to this handler only 98 * when the system doesn't support FP/ASIMD. 99 */ 100 static int handle_no_fpsimd(struct kvm_vcpu *vcpu) 101 { 102 kvm_inject_undefined(vcpu); 103 return 1; 104 } 105 106 /** 107 * kvm_handle_wfx - handle a wait-for-interrupts or wait-for-event 108 * instruction executed by a guest 109 * 110 * @vcpu: the vcpu pointer 111 * 112 * WFE[T]: Yield the CPU and come back to this vcpu when the scheduler 113 * decides to. 114 * WFI: Simply call kvm_vcpu_halt(), which will halt execution of 115 * world-switches and schedule other host processes until there is an 116 * incoming IRQ or FIQ to the VM. 117 * WFIT: Same as WFI, with a timed wakeup implemented as a background timer 118 * 119 * WF{I,E}T can immediately return if the deadline has already expired. 120 */ 121 static int kvm_handle_wfx(struct kvm_vcpu *vcpu) 122 { 123 u64 esr = kvm_vcpu_get_esr(vcpu); 124 125 if (esr & ESR_ELx_WFx_ISS_WFE) { 126 trace_kvm_wfx_arm64(*vcpu_pc(vcpu), true); 127 vcpu->stat.wfe_exit_stat++; 128 } else { 129 trace_kvm_wfx_arm64(*vcpu_pc(vcpu), false); 130 vcpu->stat.wfi_exit_stat++; 131 } 132 133 if (esr & ESR_ELx_WFx_ISS_WFxT) { 134 if (esr & ESR_ELx_WFx_ISS_RV) { 135 u64 val, now; 136 137 now = kvm_arm_timer_get_reg(vcpu, KVM_REG_ARM_TIMER_CNT); 138 val = vcpu_get_reg(vcpu, kvm_vcpu_sys_get_rt(vcpu)); 139 140 if (now >= val) 141 goto out; 142 } else { 143 /* Treat WFxT as WFx if RN is invalid */ 144 esr &= ~ESR_ELx_WFx_ISS_WFxT; 145 } 146 } 147 148 if (esr & ESR_ELx_WFx_ISS_WFE) { 149 kvm_vcpu_on_spin(vcpu, vcpu_mode_priv(vcpu)); 150 } else { 151 if (esr & ESR_ELx_WFx_ISS_WFxT) 152 vcpu_set_flag(vcpu, IN_WFIT); 153 154 kvm_vcpu_wfi(vcpu); 155 } 156 out: 157 kvm_incr_pc(vcpu); 158 159 return 1; 160 } 161 162 /** 163 * kvm_handle_guest_debug - handle a debug exception instruction 164 * 165 * @vcpu: the vcpu pointer 166 * 167 * We route all debug exceptions through the same handler. If both the 168 * guest and host are using the same debug facilities it will be up to 169 * userspace to re-inject the correct exception for guest delivery. 170 * 171 * @return: 0 (while setting vcpu->run->exit_reason) 172 */ 173 static int kvm_handle_guest_debug(struct kvm_vcpu *vcpu) 174 { 175 struct kvm_run *run = vcpu->run; 176 u64 esr = kvm_vcpu_get_esr(vcpu); 177 178 run->exit_reason = KVM_EXIT_DEBUG; 179 run->debug.arch.hsr = lower_32_bits(esr); 180 run->debug.arch.hsr_high = upper_32_bits(esr); 181 run->flags = KVM_DEBUG_ARCH_HSR_HIGH_VALID; 182 183 switch (ESR_ELx_EC(esr)) { 184 case ESR_ELx_EC_WATCHPT_LOW: 185 run->debug.arch.far = vcpu->arch.fault.far_el2; 186 break; 187 case ESR_ELx_EC_SOFTSTP_LOW: 188 vcpu_clear_flag(vcpu, DBG_SS_ACTIVE_PENDING); 189 break; 190 } 191 192 return 0; 193 } 194 195 static int kvm_handle_unknown_ec(struct kvm_vcpu *vcpu) 196 { 197 u64 esr = kvm_vcpu_get_esr(vcpu); 198 199 kvm_pr_unimpl("Unknown exception class: esr: %#016llx -- %s\n", 200 esr, esr_get_class_string(esr)); 201 202 kvm_inject_undefined(vcpu); 203 return 1; 204 } 205 206 /* 207 * Guest access to SVE registers should be routed to this handler only 208 * when the system doesn't support SVE. 209 */ 210 static int handle_sve(struct kvm_vcpu *vcpu) 211 { 212 kvm_inject_undefined(vcpu); 213 return 1; 214 } 215 216 /* 217 * Two possibilities to handle a trapping ptrauth instruction: 218 * 219 * - Guest usage of a ptrauth instruction (which the guest EL1 did not 220 * turn into a NOP). If we get here, it is because we didn't enable 221 * ptrauth for the guest. This results in an UNDEF, as it isn't 222 * supposed to use ptrauth without being told it could. 223 * 224 * - Running an L2 NV guest while L1 has left HCR_EL2.API==0, and for 225 * which we reinject the exception into L1. 226 * 227 * Anything else is an emulation bug (hence the WARN_ON + UNDEF). 228 */ 229 static int kvm_handle_ptrauth(struct kvm_vcpu *vcpu) 230 { 231 if (!vcpu_has_ptrauth(vcpu)) { 232 kvm_inject_undefined(vcpu); 233 return 1; 234 } 235 236 if (vcpu_has_nv(vcpu) && !is_hyp_ctxt(vcpu)) { 237 kvm_inject_nested_sync(vcpu, kvm_vcpu_get_esr(vcpu)); 238 return 1; 239 } 240 241 /* Really shouldn't be here! */ 242 WARN_ON_ONCE(1); 243 kvm_inject_undefined(vcpu); 244 return 1; 245 } 246 247 static int kvm_handle_eret(struct kvm_vcpu *vcpu) 248 { 249 if (esr_iss_is_eretax(kvm_vcpu_get_esr(vcpu)) && 250 !vcpu_has_ptrauth(vcpu)) 251 return kvm_handle_ptrauth(vcpu); 252 253 /* 254 * If we got here, two possibilities: 255 * 256 * - the guest is in EL2, and we need to fully emulate ERET 257 * 258 * - the guest is in EL1, and we need to reinject the 259 * exception into the L1 hypervisor. 260 * 261 * If KVM ever traps ERET for its own use, we'll have to 262 * revisit this. 263 */ 264 if (is_hyp_ctxt(vcpu)) 265 kvm_emulate_nested_eret(vcpu); 266 else 267 kvm_inject_nested_sync(vcpu, kvm_vcpu_get_esr(vcpu)); 268 269 return 1; 270 } 271 272 static int handle_svc(struct kvm_vcpu *vcpu) 273 { 274 /* 275 * So far, SVC traps only for NV via HFGITR_EL2. A SVC from a 276 * 32bit guest would be caught by vpcu_mode_is_bad_32bit(), so 277 * we should only have to deal with a 64 bit exception. 278 */ 279 kvm_inject_nested_sync(vcpu, kvm_vcpu_get_esr(vcpu)); 280 return 1; 281 } 282 283 static exit_handle_fn arm_exit_handlers[] = { 284 [0 ... ESR_ELx_EC_MAX] = kvm_handle_unknown_ec, 285 [ESR_ELx_EC_WFx] = kvm_handle_wfx, 286 [ESR_ELx_EC_CP15_32] = kvm_handle_cp15_32, 287 [ESR_ELx_EC_CP15_64] = kvm_handle_cp15_64, 288 [ESR_ELx_EC_CP14_MR] = kvm_handle_cp14_32, 289 [ESR_ELx_EC_CP14_LS] = kvm_handle_cp14_load_store, 290 [ESR_ELx_EC_CP10_ID] = kvm_handle_cp10_id, 291 [ESR_ELx_EC_CP14_64] = kvm_handle_cp14_64, 292 [ESR_ELx_EC_HVC32] = handle_hvc, 293 [ESR_ELx_EC_SMC32] = handle_smc, 294 [ESR_ELx_EC_HVC64] = handle_hvc, 295 [ESR_ELx_EC_SMC64] = handle_smc, 296 [ESR_ELx_EC_SVC64] = handle_svc, 297 [ESR_ELx_EC_SYS64] = kvm_handle_sys_reg, 298 [ESR_ELx_EC_SVE] = handle_sve, 299 [ESR_ELx_EC_ERET] = kvm_handle_eret, 300 [ESR_ELx_EC_IABT_LOW] = kvm_handle_guest_abort, 301 [ESR_ELx_EC_DABT_LOW] = kvm_handle_guest_abort, 302 [ESR_ELx_EC_SOFTSTP_LOW]= kvm_handle_guest_debug, 303 [ESR_ELx_EC_WATCHPT_LOW]= kvm_handle_guest_debug, 304 [ESR_ELx_EC_BREAKPT_LOW]= kvm_handle_guest_debug, 305 [ESR_ELx_EC_BKPT32] = kvm_handle_guest_debug, 306 [ESR_ELx_EC_BRK64] = kvm_handle_guest_debug, 307 [ESR_ELx_EC_FP_ASIMD] = handle_no_fpsimd, 308 [ESR_ELx_EC_PAC] = kvm_handle_ptrauth, 309 }; 310 311 static exit_handle_fn kvm_get_exit_handler(struct kvm_vcpu *vcpu) 312 { 313 u64 esr = kvm_vcpu_get_esr(vcpu); 314 u8 esr_ec = ESR_ELx_EC(esr); 315 316 return arm_exit_handlers[esr_ec]; 317 } 318 319 /* 320 * We may be single-stepping an emulated instruction. If the emulation 321 * has been completed in the kernel, we can return to userspace with a 322 * KVM_EXIT_DEBUG, otherwise userspace needs to complete its 323 * emulation first. 324 */ 325 static int handle_trap_exceptions(struct kvm_vcpu *vcpu) 326 { 327 int handled; 328 329 /* 330 * See ARM ARM B1.14.1: "Hyp traps on instructions 331 * that fail their condition code check" 332 */ 333 if (!kvm_condition_valid(vcpu)) { 334 kvm_incr_pc(vcpu); 335 handled = 1; 336 } else { 337 exit_handle_fn exit_handler; 338 339 exit_handler = kvm_get_exit_handler(vcpu); 340 handled = exit_handler(vcpu); 341 } 342 343 return handled; 344 } 345 346 /* 347 * Return > 0 to return to guest, < 0 on error, 0 (and set exit_reason) on 348 * proper exit to userspace. 349 */ 350 int handle_exit(struct kvm_vcpu *vcpu, int exception_index) 351 { 352 struct kvm_run *run = vcpu->run; 353 354 if (ARM_SERROR_PENDING(exception_index)) { 355 /* 356 * The SError is handled by handle_exit_early(). If the guest 357 * survives it will re-execute the original instruction. 358 */ 359 return 1; 360 } 361 362 exception_index = ARM_EXCEPTION_CODE(exception_index); 363 364 switch (exception_index) { 365 case ARM_EXCEPTION_IRQ: 366 return 1; 367 case ARM_EXCEPTION_EL1_SERROR: 368 return 1; 369 case ARM_EXCEPTION_TRAP: 370 return handle_trap_exceptions(vcpu); 371 case ARM_EXCEPTION_HYP_GONE: 372 /* 373 * EL2 has been reset to the hyp-stub. This happens when a guest 374 * is pre-emptied by kvm_reboot()'s shutdown call. 375 */ 376 run->exit_reason = KVM_EXIT_FAIL_ENTRY; 377 return 0; 378 case ARM_EXCEPTION_IL: 379 /* 380 * We attempted an illegal exception return. Guest state must 381 * have been corrupted somehow. Give up. 382 */ 383 run->exit_reason = KVM_EXIT_FAIL_ENTRY; 384 return -EINVAL; 385 default: 386 kvm_pr_unimpl("Unsupported exception type: %d", 387 exception_index); 388 run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 389 return 0; 390 } 391 } 392 393 /* For exit types that need handling before we can be preempted */ 394 void handle_exit_early(struct kvm_vcpu *vcpu, int exception_index) 395 { 396 if (ARM_SERROR_PENDING(exception_index)) { 397 if (this_cpu_has_cap(ARM64_HAS_RAS_EXTN)) { 398 u64 disr = kvm_vcpu_get_disr(vcpu); 399 400 kvm_handle_guest_serror(vcpu, disr_to_esr(disr)); 401 } else { 402 kvm_inject_vabt(vcpu); 403 } 404 405 return; 406 } 407 408 exception_index = ARM_EXCEPTION_CODE(exception_index); 409 410 if (exception_index == ARM_EXCEPTION_EL1_SERROR) 411 kvm_handle_guest_serror(vcpu, kvm_vcpu_get_esr(vcpu)); 412 } 413 414 void __noreturn __cold nvhe_hyp_panic_handler(u64 esr, u64 spsr, 415 u64 elr_virt, u64 elr_phys, 416 u64 par, uintptr_t vcpu, 417 u64 far, u64 hpfar) { 418 u64 elr_in_kimg = __phys_to_kimg(elr_phys); 419 u64 hyp_offset = elr_in_kimg - kaslr_offset() - elr_virt; 420 u64 mode = spsr & PSR_MODE_MASK; 421 u64 panic_addr = elr_virt + hyp_offset; 422 423 if (mode != PSR_MODE_EL2t && mode != PSR_MODE_EL2h) { 424 kvm_err("Invalid host exception to nVHE hyp!\n"); 425 } else if (ESR_ELx_EC(esr) == ESR_ELx_EC_BRK64 && 426 (esr & ESR_ELx_BRK64_ISS_COMMENT_MASK) == BUG_BRK_IMM) { 427 const char *file = NULL; 428 unsigned int line = 0; 429 430 /* All hyp bugs, including warnings, are treated as fatal. */ 431 if (!is_protected_kvm_enabled() || 432 IS_ENABLED(CONFIG_NVHE_EL2_DEBUG)) { 433 struct bug_entry *bug = find_bug(elr_in_kimg); 434 435 if (bug) 436 bug_get_file_line(bug, &file, &line); 437 } 438 439 if (file) 440 kvm_err("nVHE hyp BUG at: %s:%u!\n", file, line); 441 else 442 kvm_err("nVHE hyp BUG at: [<%016llx>] %pB!\n", panic_addr, 443 (void *)(panic_addr + kaslr_offset())); 444 } else { 445 kvm_err("nVHE hyp panic at: [<%016llx>] %pB!\n", panic_addr, 446 (void *)(panic_addr + kaslr_offset())); 447 } 448 449 /* Dump the nVHE hypervisor backtrace */ 450 kvm_nvhe_dump_backtrace(hyp_offset); 451 452 /* 453 * Hyp has panicked and we're going to handle that by panicking the 454 * kernel. The kernel offset will be revealed in the panic so we're 455 * also safe to reveal the hyp offset as a debugging aid for translating 456 * hyp VAs to vmlinux addresses. 457 */ 458 kvm_err("Hyp Offset: 0x%llx\n", hyp_offset); 459 460 panic("HYP panic:\nPS:%08llx PC:%016llx ESR:%016llx\nFAR:%016llx HPFAR:%016llx PAR:%016llx\nVCPU:%016lx\n", 461 spsr, elr_virt, esr, far, hpfar, par, vcpu); 462 } 463