1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2016 - Linaro and Columbia University 4 * Author: Jintack Lim <jintack.lim@linaro.org> 5 */ 6 7 #include <linux/kvm.h> 8 #include <linux/kvm_host.h> 9 10 #include <asm/kvm_emulate.h> 11 #include <asm/kvm_nested.h> 12 13 #include "hyp/include/hyp/adjust_pc.h" 14 15 #include "trace.h" 16 17 enum trap_behaviour { 18 BEHAVE_HANDLE_LOCALLY = 0, 19 BEHAVE_FORWARD_READ = BIT(0), 20 BEHAVE_FORWARD_WRITE = BIT(1), 21 BEHAVE_FORWARD_ANY = BEHAVE_FORWARD_READ | BEHAVE_FORWARD_WRITE, 22 }; 23 24 struct trap_bits { 25 const enum vcpu_sysreg index; 26 const enum trap_behaviour behaviour; 27 const u64 value; 28 const u64 mask; 29 }; 30 31 /* Coarse Grained Trap definitions */ 32 enum cgt_group_id { 33 /* Indicates no coarse trap control */ 34 __RESERVED__, 35 36 /* 37 * The first batch of IDs denote coarse trapping that are used 38 * on their own instead of being part of a combination of 39 * trap controls. 40 */ 41 CGT_HCR_TID1, 42 CGT_HCR_TID2, 43 CGT_HCR_TID3, 44 CGT_HCR_IMO, 45 CGT_HCR_FMO, 46 CGT_HCR_TIDCP, 47 CGT_HCR_TACR, 48 CGT_HCR_TSW, 49 CGT_HCR_TPC, 50 CGT_HCR_TPU, 51 CGT_HCR_TTLB, 52 CGT_HCR_TVM, 53 CGT_HCR_TDZ, 54 CGT_HCR_TRVM, 55 CGT_HCR_TLOR, 56 CGT_HCR_TERR, 57 CGT_HCR_APK, 58 CGT_HCR_NV, 59 CGT_HCR_NV_nNV2, 60 CGT_HCR_NV1_nNV2, 61 CGT_HCR_AT, 62 CGT_HCR_nFIEN, 63 CGT_HCR_TID4, 64 CGT_HCR_TICAB, 65 CGT_HCR_TOCU, 66 CGT_HCR_ENSCXT, 67 CGT_HCR_TTLBIS, 68 CGT_HCR_TTLBOS, 69 70 CGT_MDCR_TPMCR, 71 CGT_MDCR_TPM, 72 CGT_MDCR_TDE, 73 CGT_MDCR_TDA, 74 CGT_MDCR_TDOSA, 75 CGT_MDCR_TDRA, 76 CGT_MDCR_E2PB, 77 CGT_MDCR_TPMS, 78 CGT_MDCR_TTRF, 79 CGT_MDCR_E2TB, 80 CGT_MDCR_TDCC, 81 82 CGT_CPACR_E0POE, 83 CGT_CPTR_TAM, 84 CGT_CPTR_TCPAC, 85 86 CGT_HCRX_EnFPM, 87 CGT_HCRX_TCR2En, 88 89 CGT_ICH_HCR_TC, 90 CGT_ICH_HCR_TALL0, 91 CGT_ICH_HCR_TALL1, 92 CGT_ICH_HCR_TDIR, 93 94 /* 95 * Anything after this point is a combination of coarse trap 96 * controls, which must all be evaluated to decide what to do. 97 */ 98 __MULTIPLE_CONTROL_BITS__, 99 CGT_HCR_IMO_FMO_ICH_HCR_TC = __MULTIPLE_CONTROL_BITS__, 100 CGT_HCR_TID2_TID4, 101 CGT_HCR_TTLB_TTLBIS, 102 CGT_HCR_TTLB_TTLBOS, 103 CGT_HCR_TVM_TRVM, 104 CGT_HCR_TVM_TRVM_HCRX_TCR2En, 105 CGT_HCR_TPU_TICAB, 106 CGT_HCR_TPU_TOCU, 107 CGT_HCR_NV1_nNV2_ENSCXT, 108 CGT_MDCR_TPM_TPMCR, 109 CGT_MDCR_TDE_TDA, 110 CGT_MDCR_TDE_TDOSA, 111 CGT_MDCR_TDE_TDRA, 112 CGT_MDCR_TDCC_TDE_TDA, 113 114 CGT_ICH_HCR_TC_TDIR, 115 116 /* 117 * Anything after this point requires a callback evaluating a 118 * complex trap condition. Ugly stuff. 119 */ 120 __COMPLEX_CONDITIONS__, 121 CGT_CNTHCTL_EL1PCTEN = __COMPLEX_CONDITIONS__, 122 CGT_CNTHCTL_EL1PTEN, 123 124 CGT_CPTR_TTA, 125 126 /* Must be last */ 127 __NR_CGT_GROUP_IDS__ 128 }; 129 130 static const struct trap_bits coarse_trap_bits[] = { 131 [CGT_HCR_TID1] = { 132 .index = HCR_EL2, 133 .value = HCR_TID1, 134 .mask = HCR_TID1, 135 .behaviour = BEHAVE_FORWARD_READ, 136 }, 137 [CGT_HCR_TID2] = { 138 .index = HCR_EL2, 139 .value = HCR_TID2, 140 .mask = HCR_TID2, 141 .behaviour = BEHAVE_FORWARD_ANY, 142 }, 143 [CGT_HCR_TID3] = { 144 .index = HCR_EL2, 145 .value = HCR_TID3, 146 .mask = HCR_TID3, 147 .behaviour = BEHAVE_FORWARD_READ, 148 }, 149 [CGT_HCR_IMO] = { 150 .index = HCR_EL2, 151 .value = HCR_IMO, 152 .mask = HCR_IMO, 153 .behaviour = BEHAVE_FORWARD_WRITE, 154 }, 155 [CGT_HCR_FMO] = { 156 .index = HCR_EL2, 157 .value = HCR_FMO, 158 .mask = HCR_FMO, 159 .behaviour = BEHAVE_FORWARD_WRITE, 160 }, 161 [CGT_HCR_TIDCP] = { 162 .index = HCR_EL2, 163 .value = HCR_TIDCP, 164 .mask = HCR_TIDCP, 165 .behaviour = BEHAVE_FORWARD_ANY, 166 }, 167 [CGT_HCR_TACR] = { 168 .index = HCR_EL2, 169 .value = HCR_TACR, 170 .mask = HCR_TACR, 171 .behaviour = BEHAVE_FORWARD_ANY, 172 }, 173 [CGT_HCR_TSW] = { 174 .index = HCR_EL2, 175 .value = HCR_TSW, 176 .mask = HCR_TSW, 177 .behaviour = BEHAVE_FORWARD_ANY, 178 }, 179 [CGT_HCR_TPC] = { /* Also called TCPC when FEAT_DPB is implemented */ 180 .index = HCR_EL2, 181 .value = HCR_TPC, 182 .mask = HCR_TPC, 183 .behaviour = BEHAVE_FORWARD_ANY, 184 }, 185 [CGT_HCR_TPU] = { 186 .index = HCR_EL2, 187 .value = HCR_TPU, 188 .mask = HCR_TPU, 189 .behaviour = BEHAVE_FORWARD_ANY, 190 }, 191 [CGT_HCR_TTLB] = { 192 .index = HCR_EL2, 193 .value = HCR_TTLB, 194 .mask = HCR_TTLB, 195 .behaviour = BEHAVE_FORWARD_ANY, 196 }, 197 [CGT_HCR_TVM] = { 198 .index = HCR_EL2, 199 .value = HCR_TVM, 200 .mask = HCR_TVM, 201 .behaviour = BEHAVE_FORWARD_WRITE, 202 }, 203 [CGT_HCR_TDZ] = { 204 .index = HCR_EL2, 205 .value = HCR_TDZ, 206 .mask = HCR_TDZ, 207 .behaviour = BEHAVE_FORWARD_ANY, 208 }, 209 [CGT_HCR_TRVM] = { 210 .index = HCR_EL2, 211 .value = HCR_TRVM, 212 .mask = HCR_TRVM, 213 .behaviour = BEHAVE_FORWARD_READ, 214 }, 215 [CGT_HCR_TLOR] = { 216 .index = HCR_EL2, 217 .value = HCR_TLOR, 218 .mask = HCR_TLOR, 219 .behaviour = BEHAVE_FORWARD_ANY, 220 }, 221 [CGT_HCR_TERR] = { 222 .index = HCR_EL2, 223 .value = HCR_TERR, 224 .mask = HCR_TERR, 225 .behaviour = BEHAVE_FORWARD_ANY, 226 }, 227 [CGT_HCR_APK] = { 228 .index = HCR_EL2, 229 .value = 0, 230 .mask = HCR_APK, 231 .behaviour = BEHAVE_FORWARD_ANY, 232 }, 233 [CGT_HCR_NV] = { 234 .index = HCR_EL2, 235 .value = HCR_NV, 236 .mask = HCR_NV, 237 .behaviour = BEHAVE_FORWARD_ANY, 238 }, 239 [CGT_HCR_NV_nNV2] = { 240 .index = HCR_EL2, 241 .value = HCR_NV, 242 .mask = HCR_NV | HCR_NV2, 243 .behaviour = BEHAVE_FORWARD_ANY, 244 }, 245 [CGT_HCR_NV1_nNV2] = { 246 .index = HCR_EL2, 247 .value = HCR_NV | HCR_NV1, 248 .mask = HCR_NV | HCR_NV1 | HCR_NV2, 249 .behaviour = BEHAVE_FORWARD_ANY, 250 }, 251 [CGT_HCR_AT] = { 252 .index = HCR_EL2, 253 .value = HCR_AT, 254 .mask = HCR_AT, 255 .behaviour = BEHAVE_FORWARD_ANY, 256 }, 257 [CGT_HCR_nFIEN] = { 258 .index = HCR_EL2, 259 .value = 0, 260 .mask = HCR_FIEN, 261 .behaviour = BEHAVE_FORWARD_ANY, 262 }, 263 [CGT_HCR_TID4] = { 264 .index = HCR_EL2, 265 .value = HCR_TID4, 266 .mask = HCR_TID4, 267 .behaviour = BEHAVE_FORWARD_ANY, 268 }, 269 [CGT_HCR_TICAB] = { 270 .index = HCR_EL2, 271 .value = HCR_TICAB, 272 .mask = HCR_TICAB, 273 .behaviour = BEHAVE_FORWARD_ANY, 274 }, 275 [CGT_HCR_TOCU] = { 276 .index = HCR_EL2, 277 .value = HCR_TOCU, 278 .mask = HCR_TOCU, 279 .behaviour = BEHAVE_FORWARD_ANY, 280 }, 281 [CGT_HCR_ENSCXT] = { 282 .index = HCR_EL2, 283 .value = 0, 284 .mask = HCR_ENSCXT, 285 .behaviour = BEHAVE_FORWARD_ANY, 286 }, 287 [CGT_HCR_TTLBIS] = { 288 .index = HCR_EL2, 289 .value = HCR_TTLBIS, 290 .mask = HCR_TTLBIS, 291 .behaviour = BEHAVE_FORWARD_ANY, 292 }, 293 [CGT_HCR_TTLBOS] = { 294 .index = HCR_EL2, 295 .value = HCR_TTLBOS, 296 .mask = HCR_TTLBOS, 297 .behaviour = BEHAVE_FORWARD_ANY, 298 }, 299 [CGT_MDCR_TPMCR] = { 300 .index = MDCR_EL2, 301 .value = MDCR_EL2_TPMCR, 302 .mask = MDCR_EL2_TPMCR, 303 .behaviour = BEHAVE_FORWARD_ANY, 304 }, 305 [CGT_MDCR_TPM] = { 306 .index = MDCR_EL2, 307 .value = MDCR_EL2_TPM, 308 .mask = MDCR_EL2_TPM, 309 .behaviour = BEHAVE_FORWARD_ANY, 310 }, 311 [CGT_MDCR_TDE] = { 312 .index = MDCR_EL2, 313 .value = MDCR_EL2_TDE, 314 .mask = MDCR_EL2_TDE, 315 .behaviour = BEHAVE_FORWARD_ANY, 316 }, 317 [CGT_MDCR_TDA] = { 318 .index = MDCR_EL2, 319 .value = MDCR_EL2_TDA, 320 .mask = MDCR_EL2_TDA, 321 .behaviour = BEHAVE_FORWARD_ANY, 322 }, 323 [CGT_MDCR_TDOSA] = { 324 .index = MDCR_EL2, 325 .value = MDCR_EL2_TDOSA, 326 .mask = MDCR_EL2_TDOSA, 327 .behaviour = BEHAVE_FORWARD_ANY, 328 }, 329 [CGT_MDCR_TDRA] = { 330 .index = MDCR_EL2, 331 .value = MDCR_EL2_TDRA, 332 .mask = MDCR_EL2_TDRA, 333 .behaviour = BEHAVE_FORWARD_ANY, 334 }, 335 [CGT_MDCR_E2PB] = { 336 .index = MDCR_EL2, 337 .value = 0, 338 .mask = BIT(MDCR_EL2_E2PB_SHIFT), 339 .behaviour = BEHAVE_FORWARD_ANY, 340 }, 341 [CGT_MDCR_TPMS] = { 342 .index = MDCR_EL2, 343 .value = MDCR_EL2_TPMS, 344 .mask = MDCR_EL2_TPMS, 345 .behaviour = BEHAVE_FORWARD_ANY, 346 }, 347 [CGT_MDCR_TTRF] = { 348 .index = MDCR_EL2, 349 .value = MDCR_EL2_TTRF, 350 .mask = MDCR_EL2_TTRF, 351 .behaviour = BEHAVE_FORWARD_ANY, 352 }, 353 [CGT_MDCR_E2TB] = { 354 .index = MDCR_EL2, 355 .value = 0, 356 .mask = BIT(MDCR_EL2_E2TB_SHIFT), 357 .behaviour = BEHAVE_FORWARD_ANY, 358 }, 359 [CGT_MDCR_TDCC] = { 360 .index = MDCR_EL2, 361 .value = MDCR_EL2_TDCC, 362 .mask = MDCR_EL2_TDCC, 363 .behaviour = BEHAVE_FORWARD_ANY, 364 }, 365 [CGT_CPACR_E0POE] = { 366 .index = CPTR_EL2, 367 .value = CPACR_ELx_E0POE, 368 .mask = CPACR_ELx_E0POE, 369 .behaviour = BEHAVE_FORWARD_ANY, 370 }, 371 [CGT_CPTR_TAM] = { 372 .index = CPTR_EL2, 373 .value = CPTR_EL2_TAM, 374 .mask = CPTR_EL2_TAM, 375 .behaviour = BEHAVE_FORWARD_ANY, 376 }, 377 [CGT_CPTR_TCPAC] = { 378 .index = CPTR_EL2, 379 .value = CPTR_EL2_TCPAC, 380 .mask = CPTR_EL2_TCPAC, 381 .behaviour = BEHAVE_FORWARD_ANY, 382 }, 383 [CGT_HCRX_EnFPM] = { 384 .index = HCRX_EL2, 385 .value = 0, 386 .mask = HCRX_EL2_EnFPM, 387 .behaviour = BEHAVE_FORWARD_ANY, 388 }, 389 [CGT_HCRX_TCR2En] = { 390 .index = HCRX_EL2, 391 .value = 0, 392 .mask = HCRX_EL2_TCR2En, 393 .behaviour = BEHAVE_FORWARD_ANY, 394 }, 395 [CGT_ICH_HCR_TC] = { 396 .index = ICH_HCR_EL2, 397 .value = ICH_HCR_TC, 398 .mask = ICH_HCR_TC, 399 .behaviour = BEHAVE_FORWARD_ANY, 400 }, 401 [CGT_ICH_HCR_TALL0] = { 402 .index = ICH_HCR_EL2, 403 .value = ICH_HCR_TALL0, 404 .mask = ICH_HCR_TALL0, 405 .behaviour = BEHAVE_FORWARD_ANY, 406 }, 407 [CGT_ICH_HCR_TALL1] = { 408 .index = ICH_HCR_EL2, 409 .value = ICH_HCR_TALL1, 410 .mask = ICH_HCR_TALL1, 411 .behaviour = BEHAVE_FORWARD_ANY, 412 }, 413 [CGT_ICH_HCR_TDIR] = { 414 .index = ICH_HCR_EL2, 415 .value = ICH_HCR_TDIR, 416 .mask = ICH_HCR_TDIR, 417 .behaviour = BEHAVE_FORWARD_ANY, 418 }, 419 }; 420 421 #define MCB(id, ...) \ 422 [id - __MULTIPLE_CONTROL_BITS__] = \ 423 (const enum cgt_group_id[]){ \ 424 __VA_ARGS__, __RESERVED__ \ 425 } 426 427 static const enum cgt_group_id *coarse_control_combo[] = { 428 MCB(CGT_HCR_TID2_TID4, CGT_HCR_TID2, CGT_HCR_TID4), 429 MCB(CGT_HCR_TTLB_TTLBIS, CGT_HCR_TTLB, CGT_HCR_TTLBIS), 430 MCB(CGT_HCR_TTLB_TTLBOS, CGT_HCR_TTLB, CGT_HCR_TTLBOS), 431 MCB(CGT_HCR_TVM_TRVM, CGT_HCR_TVM, CGT_HCR_TRVM), 432 MCB(CGT_HCR_TVM_TRVM_HCRX_TCR2En, 433 CGT_HCR_TVM, CGT_HCR_TRVM, CGT_HCRX_TCR2En), 434 MCB(CGT_HCR_TPU_TICAB, CGT_HCR_TPU, CGT_HCR_TICAB), 435 MCB(CGT_HCR_TPU_TOCU, CGT_HCR_TPU, CGT_HCR_TOCU), 436 MCB(CGT_HCR_NV1_nNV2_ENSCXT, CGT_HCR_NV1_nNV2, CGT_HCR_ENSCXT), 437 MCB(CGT_MDCR_TPM_TPMCR, CGT_MDCR_TPM, CGT_MDCR_TPMCR), 438 MCB(CGT_MDCR_TDE_TDA, CGT_MDCR_TDE, CGT_MDCR_TDA), 439 MCB(CGT_MDCR_TDE_TDOSA, CGT_MDCR_TDE, CGT_MDCR_TDOSA), 440 MCB(CGT_MDCR_TDE_TDRA, CGT_MDCR_TDE, CGT_MDCR_TDRA), 441 MCB(CGT_MDCR_TDCC_TDE_TDA, CGT_MDCR_TDCC, CGT_MDCR_TDE, CGT_MDCR_TDA), 442 443 MCB(CGT_HCR_IMO_FMO_ICH_HCR_TC, CGT_HCR_IMO, CGT_HCR_FMO, CGT_ICH_HCR_TC), 444 MCB(CGT_ICH_HCR_TC_TDIR, CGT_ICH_HCR_TC, CGT_ICH_HCR_TDIR), 445 }; 446 447 typedef enum trap_behaviour (*complex_condition_check)(struct kvm_vcpu *); 448 449 /* 450 * Warning, maximum confusion ahead. 451 * 452 * When E2H=0, CNTHCTL_EL2[1:0] are defined as EL1PCEN:EL1PCTEN 453 * When E2H=1, CNTHCTL_EL2[11:10] are defined as EL1PTEN:EL1PCTEN 454 * 455 * Note the single letter difference? Yet, the bits have the same 456 * function despite a different layout and a different name. 457 * 458 * We don't try to reconcile this mess. We just use the E2H=0 bits 459 * to generate something that is in the E2H=1 format, and live with 460 * it. You're welcome. 461 */ 462 static u64 get_sanitized_cnthctl(struct kvm_vcpu *vcpu) 463 { 464 u64 val = __vcpu_sys_reg(vcpu, CNTHCTL_EL2); 465 466 if (!vcpu_el2_e2h_is_set(vcpu)) 467 val = (val & (CNTHCTL_EL1PCEN | CNTHCTL_EL1PCTEN)) << 10; 468 469 return val & ((CNTHCTL_EL1PCEN | CNTHCTL_EL1PCTEN) << 10); 470 } 471 472 static enum trap_behaviour check_cnthctl_el1pcten(struct kvm_vcpu *vcpu) 473 { 474 if (get_sanitized_cnthctl(vcpu) & (CNTHCTL_EL1PCTEN << 10)) 475 return BEHAVE_HANDLE_LOCALLY; 476 477 return BEHAVE_FORWARD_ANY; 478 } 479 480 static enum trap_behaviour check_cnthctl_el1pten(struct kvm_vcpu *vcpu) 481 { 482 if (get_sanitized_cnthctl(vcpu) & (CNTHCTL_EL1PCEN << 10)) 483 return BEHAVE_HANDLE_LOCALLY; 484 485 return BEHAVE_FORWARD_ANY; 486 } 487 488 static enum trap_behaviour check_cptr_tta(struct kvm_vcpu *vcpu) 489 { 490 u64 val = __vcpu_sys_reg(vcpu, CPTR_EL2); 491 492 if (!vcpu_el2_e2h_is_set(vcpu)) 493 val = translate_cptr_el2_to_cpacr_el1(val); 494 495 if (val & CPACR_ELx_TTA) 496 return BEHAVE_FORWARD_ANY; 497 498 return BEHAVE_HANDLE_LOCALLY; 499 } 500 501 #define CCC(id, fn) \ 502 [id - __COMPLEX_CONDITIONS__] = fn 503 504 static const complex_condition_check ccc[] = { 505 CCC(CGT_CNTHCTL_EL1PCTEN, check_cnthctl_el1pcten), 506 CCC(CGT_CNTHCTL_EL1PTEN, check_cnthctl_el1pten), 507 CCC(CGT_CPTR_TTA, check_cptr_tta), 508 }; 509 510 /* 511 * Bit assignment for the trap controls. We use a 64bit word with the 512 * following layout for each trapped sysreg: 513 * 514 * [9:0] enum cgt_group_id (10 bits) 515 * [13:10] enum fgt_group_id (4 bits) 516 * [19:14] bit number in the FGT register (6 bits) 517 * [20] trap polarity (1 bit) 518 * [25:21] FG filter (5 bits) 519 * [35:26] Main SysReg table index (10 bits) 520 * [62:36] Unused (27 bits) 521 * [63] RES0 - Must be zero, as lost on insertion in the xarray 522 */ 523 #define TC_CGT_BITS 10 524 #define TC_FGT_BITS 4 525 #define TC_FGF_BITS 5 526 #define TC_SRI_BITS 10 527 528 union trap_config { 529 u64 val; 530 struct { 531 unsigned long cgt:TC_CGT_BITS; /* Coarse Grained Trap id */ 532 unsigned long fgt:TC_FGT_BITS; /* Fine Grained Trap id */ 533 unsigned long bit:6; /* Bit number */ 534 unsigned long pol:1; /* Polarity */ 535 unsigned long fgf:TC_FGF_BITS; /* Fine Grained Filter */ 536 unsigned long sri:TC_SRI_BITS; /* SysReg Index */ 537 unsigned long unused:27; /* Unused, should be zero */ 538 unsigned long mbz:1; /* Must Be Zero */ 539 }; 540 }; 541 542 struct encoding_to_trap_config { 543 const u32 encoding; 544 const u32 end; 545 const union trap_config tc; 546 const unsigned int line; 547 }; 548 549 #define SR_RANGE_TRAP(sr_start, sr_end, trap_id) \ 550 { \ 551 .encoding = sr_start, \ 552 .end = sr_end, \ 553 .tc = { \ 554 .cgt = trap_id, \ 555 }, \ 556 .line = __LINE__, \ 557 } 558 559 #define SR_TRAP(sr, trap_id) SR_RANGE_TRAP(sr, sr, trap_id) 560 561 /* 562 * Map encoding to trap bits for exception reported with EC=0x18. 563 * These must only be evaluated when running a nested hypervisor, but 564 * that the current context is not a hypervisor context. When the 565 * trapped access matches one of the trap controls, the exception is 566 * re-injected in the nested hypervisor. 567 */ 568 static const struct encoding_to_trap_config encoding_to_cgt[] __initconst = { 569 SR_TRAP(SYS_REVIDR_EL1, CGT_HCR_TID1), 570 SR_TRAP(SYS_AIDR_EL1, CGT_HCR_TID1), 571 SR_TRAP(SYS_SMIDR_EL1, CGT_HCR_TID1), 572 SR_TRAP(SYS_CTR_EL0, CGT_HCR_TID2), 573 SR_TRAP(SYS_CCSIDR_EL1, CGT_HCR_TID2_TID4), 574 SR_TRAP(SYS_CCSIDR2_EL1, CGT_HCR_TID2_TID4), 575 SR_TRAP(SYS_CLIDR_EL1, CGT_HCR_TID2_TID4), 576 SR_TRAP(SYS_CSSELR_EL1, CGT_HCR_TID2_TID4), 577 SR_RANGE_TRAP(SYS_ID_PFR0_EL1, 578 sys_reg(3, 0, 0, 7, 7), CGT_HCR_TID3), 579 SR_TRAP(SYS_ICC_SGI0R_EL1, CGT_HCR_IMO_FMO_ICH_HCR_TC), 580 SR_TRAP(SYS_ICC_ASGI1R_EL1, CGT_HCR_IMO_FMO_ICH_HCR_TC), 581 SR_TRAP(SYS_ICC_SGI1R_EL1, CGT_HCR_IMO_FMO_ICH_HCR_TC), 582 SR_RANGE_TRAP(sys_reg(3, 0, 11, 0, 0), 583 sys_reg(3, 0, 11, 15, 7), CGT_HCR_TIDCP), 584 SR_RANGE_TRAP(sys_reg(3, 1, 11, 0, 0), 585 sys_reg(3, 1, 11, 15, 7), CGT_HCR_TIDCP), 586 SR_RANGE_TRAP(sys_reg(3, 2, 11, 0, 0), 587 sys_reg(3, 2, 11, 15, 7), CGT_HCR_TIDCP), 588 SR_RANGE_TRAP(sys_reg(3, 3, 11, 0, 0), 589 sys_reg(3, 3, 11, 15, 7), CGT_HCR_TIDCP), 590 SR_RANGE_TRAP(sys_reg(3, 4, 11, 0, 0), 591 sys_reg(3, 4, 11, 15, 7), CGT_HCR_TIDCP), 592 SR_RANGE_TRAP(sys_reg(3, 5, 11, 0, 0), 593 sys_reg(3, 5, 11, 15, 7), CGT_HCR_TIDCP), 594 SR_RANGE_TRAP(sys_reg(3, 6, 11, 0, 0), 595 sys_reg(3, 6, 11, 15, 7), CGT_HCR_TIDCP), 596 SR_RANGE_TRAP(sys_reg(3, 7, 11, 0, 0), 597 sys_reg(3, 7, 11, 15, 7), CGT_HCR_TIDCP), 598 SR_RANGE_TRAP(sys_reg(3, 0, 15, 0, 0), 599 sys_reg(3, 0, 15, 15, 7), CGT_HCR_TIDCP), 600 SR_RANGE_TRAP(sys_reg(3, 1, 15, 0, 0), 601 sys_reg(3, 1, 15, 15, 7), CGT_HCR_TIDCP), 602 SR_RANGE_TRAP(sys_reg(3, 2, 15, 0, 0), 603 sys_reg(3, 2, 15, 15, 7), CGT_HCR_TIDCP), 604 SR_RANGE_TRAP(sys_reg(3, 3, 15, 0, 0), 605 sys_reg(3, 3, 15, 15, 7), CGT_HCR_TIDCP), 606 SR_RANGE_TRAP(sys_reg(3, 4, 15, 0, 0), 607 sys_reg(3, 4, 15, 15, 7), CGT_HCR_TIDCP), 608 SR_RANGE_TRAP(sys_reg(3, 5, 15, 0, 0), 609 sys_reg(3, 5, 15, 15, 7), CGT_HCR_TIDCP), 610 SR_RANGE_TRAP(sys_reg(3, 6, 15, 0, 0), 611 sys_reg(3, 6, 15, 15, 7), CGT_HCR_TIDCP), 612 SR_RANGE_TRAP(sys_reg(3, 7, 15, 0, 0), 613 sys_reg(3, 7, 15, 15, 7), CGT_HCR_TIDCP), 614 SR_TRAP(SYS_ACTLR_EL1, CGT_HCR_TACR), 615 SR_TRAP(SYS_DC_ISW, CGT_HCR_TSW), 616 SR_TRAP(SYS_DC_CSW, CGT_HCR_TSW), 617 SR_TRAP(SYS_DC_CISW, CGT_HCR_TSW), 618 SR_TRAP(SYS_DC_IGSW, CGT_HCR_TSW), 619 SR_TRAP(SYS_DC_IGDSW, CGT_HCR_TSW), 620 SR_TRAP(SYS_DC_CGSW, CGT_HCR_TSW), 621 SR_TRAP(SYS_DC_CGDSW, CGT_HCR_TSW), 622 SR_TRAP(SYS_DC_CIGSW, CGT_HCR_TSW), 623 SR_TRAP(SYS_DC_CIGDSW, CGT_HCR_TSW), 624 SR_TRAP(SYS_DC_CIVAC, CGT_HCR_TPC), 625 SR_TRAP(SYS_DC_CVAC, CGT_HCR_TPC), 626 SR_TRAP(SYS_DC_CVAP, CGT_HCR_TPC), 627 SR_TRAP(SYS_DC_CVADP, CGT_HCR_TPC), 628 SR_TRAP(SYS_DC_IVAC, CGT_HCR_TPC), 629 SR_TRAP(SYS_DC_CIGVAC, CGT_HCR_TPC), 630 SR_TRAP(SYS_DC_CIGDVAC, CGT_HCR_TPC), 631 SR_TRAP(SYS_DC_IGVAC, CGT_HCR_TPC), 632 SR_TRAP(SYS_DC_IGDVAC, CGT_HCR_TPC), 633 SR_TRAP(SYS_DC_CGVAC, CGT_HCR_TPC), 634 SR_TRAP(SYS_DC_CGDVAC, CGT_HCR_TPC), 635 SR_TRAP(SYS_DC_CGVAP, CGT_HCR_TPC), 636 SR_TRAP(SYS_DC_CGDVAP, CGT_HCR_TPC), 637 SR_TRAP(SYS_DC_CGVADP, CGT_HCR_TPC), 638 SR_TRAP(SYS_DC_CGDVADP, CGT_HCR_TPC), 639 SR_TRAP(SYS_IC_IVAU, CGT_HCR_TPU_TOCU), 640 SR_TRAP(SYS_IC_IALLU, CGT_HCR_TPU_TOCU), 641 SR_TRAP(SYS_IC_IALLUIS, CGT_HCR_TPU_TICAB), 642 SR_TRAP(SYS_DC_CVAU, CGT_HCR_TPU_TOCU), 643 SR_TRAP(OP_TLBI_RVAE1, CGT_HCR_TTLB), 644 SR_TRAP(OP_TLBI_RVAAE1, CGT_HCR_TTLB), 645 SR_TRAP(OP_TLBI_RVALE1, CGT_HCR_TTLB), 646 SR_TRAP(OP_TLBI_RVAALE1, CGT_HCR_TTLB), 647 SR_TRAP(OP_TLBI_VMALLE1, CGT_HCR_TTLB), 648 SR_TRAP(OP_TLBI_VAE1, CGT_HCR_TTLB), 649 SR_TRAP(OP_TLBI_ASIDE1, CGT_HCR_TTLB), 650 SR_TRAP(OP_TLBI_VAAE1, CGT_HCR_TTLB), 651 SR_TRAP(OP_TLBI_VALE1, CGT_HCR_TTLB), 652 SR_TRAP(OP_TLBI_VAALE1, CGT_HCR_TTLB), 653 SR_TRAP(OP_TLBI_RVAE1NXS, CGT_HCR_TTLB), 654 SR_TRAP(OP_TLBI_RVAAE1NXS, CGT_HCR_TTLB), 655 SR_TRAP(OP_TLBI_RVALE1NXS, CGT_HCR_TTLB), 656 SR_TRAP(OP_TLBI_RVAALE1NXS, CGT_HCR_TTLB), 657 SR_TRAP(OP_TLBI_VMALLE1NXS, CGT_HCR_TTLB), 658 SR_TRAP(OP_TLBI_VAE1NXS, CGT_HCR_TTLB), 659 SR_TRAP(OP_TLBI_ASIDE1NXS, CGT_HCR_TTLB), 660 SR_TRAP(OP_TLBI_VAAE1NXS, CGT_HCR_TTLB), 661 SR_TRAP(OP_TLBI_VALE1NXS, CGT_HCR_TTLB), 662 SR_TRAP(OP_TLBI_VAALE1NXS, CGT_HCR_TTLB), 663 SR_TRAP(OP_TLBI_RVAE1IS, CGT_HCR_TTLB_TTLBIS), 664 SR_TRAP(OP_TLBI_RVAAE1IS, CGT_HCR_TTLB_TTLBIS), 665 SR_TRAP(OP_TLBI_RVALE1IS, CGT_HCR_TTLB_TTLBIS), 666 SR_TRAP(OP_TLBI_RVAALE1IS, CGT_HCR_TTLB_TTLBIS), 667 SR_TRAP(OP_TLBI_VMALLE1IS, CGT_HCR_TTLB_TTLBIS), 668 SR_TRAP(OP_TLBI_VAE1IS, CGT_HCR_TTLB_TTLBIS), 669 SR_TRAP(OP_TLBI_ASIDE1IS, CGT_HCR_TTLB_TTLBIS), 670 SR_TRAP(OP_TLBI_VAAE1IS, CGT_HCR_TTLB_TTLBIS), 671 SR_TRAP(OP_TLBI_VALE1IS, CGT_HCR_TTLB_TTLBIS), 672 SR_TRAP(OP_TLBI_VAALE1IS, CGT_HCR_TTLB_TTLBIS), 673 SR_TRAP(OP_TLBI_RVAE1ISNXS, CGT_HCR_TTLB_TTLBIS), 674 SR_TRAP(OP_TLBI_RVAAE1ISNXS, CGT_HCR_TTLB_TTLBIS), 675 SR_TRAP(OP_TLBI_RVALE1ISNXS, CGT_HCR_TTLB_TTLBIS), 676 SR_TRAP(OP_TLBI_RVAALE1ISNXS, CGT_HCR_TTLB_TTLBIS), 677 SR_TRAP(OP_TLBI_VMALLE1ISNXS, CGT_HCR_TTLB_TTLBIS), 678 SR_TRAP(OP_TLBI_VAE1ISNXS, CGT_HCR_TTLB_TTLBIS), 679 SR_TRAP(OP_TLBI_ASIDE1ISNXS, CGT_HCR_TTLB_TTLBIS), 680 SR_TRAP(OP_TLBI_VAAE1ISNXS, CGT_HCR_TTLB_TTLBIS), 681 SR_TRAP(OP_TLBI_VALE1ISNXS, CGT_HCR_TTLB_TTLBIS), 682 SR_TRAP(OP_TLBI_VAALE1ISNXS, CGT_HCR_TTLB_TTLBIS), 683 SR_TRAP(OP_TLBI_VMALLE1OS, CGT_HCR_TTLB_TTLBOS), 684 SR_TRAP(OP_TLBI_VAE1OS, CGT_HCR_TTLB_TTLBOS), 685 SR_TRAP(OP_TLBI_ASIDE1OS, CGT_HCR_TTLB_TTLBOS), 686 SR_TRAP(OP_TLBI_VAAE1OS, CGT_HCR_TTLB_TTLBOS), 687 SR_TRAP(OP_TLBI_VALE1OS, CGT_HCR_TTLB_TTLBOS), 688 SR_TRAP(OP_TLBI_VAALE1OS, CGT_HCR_TTLB_TTLBOS), 689 SR_TRAP(OP_TLBI_RVAE1OS, CGT_HCR_TTLB_TTLBOS), 690 SR_TRAP(OP_TLBI_RVAAE1OS, CGT_HCR_TTLB_TTLBOS), 691 SR_TRAP(OP_TLBI_RVALE1OS, CGT_HCR_TTLB_TTLBOS), 692 SR_TRAP(OP_TLBI_RVAALE1OS, CGT_HCR_TTLB_TTLBOS), 693 SR_TRAP(OP_TLBI_VMALLE1OSNXS, CGT_HCR_TTLB_TTLBOS), 694 SR_TRAP(OP_TLBI_VAE1OSNXS, CGT_HCR_TTLB_TTLBOS), 695 SR_TRAP(OP_TLBI_ASIDE1OSNXS, CGT_HCR_TTLB_TTLBOS), 696 SR_TRAP(OP_TLBI_VAAE1OSNXS, CGT_HCR_TTLB_TTLBOS), 697 SR_TRAP(OP_TLBI_VALE1OSNXS, CGT_HCR_TTLB_TTLBOS), 698 SR_TRAP(OP_TLBI_VAALE1OSNXS, CGT_HCR_TTLB_TTLBOS), 699 SR_TRAP(OP_TLBI_RVAE1OSNXS, CGT_HCR_TTLB_TTLBOS), 700 SR_TRAP(OP_TLBI_RVAAE1OSNXS, CGT_HCR_TTLB_TTLBOS), 701 SR_TRAP(OP_TLBI_RVALE1OSNXS, CGT_HCR_TTLB_TTLBOS), 702 SR_TRAP(OP_TLBI_RVAALE1OSNXS, CGT_HCR_TTLB_TTLBOS), 703 SR_TRAP(SYS_SCTLR_EL1, CGT_HCR_TVM_TRVM), 704 SR_TRAP(SYS_TTBR0_EL1, CGT_HCR_TVM_TRVM), 705 SR_TRAP(SYS_TTBR1_EL1, CGT_HCR_TVM_TRVM), 706 SR_TRAP(SYS_TCR_EL1, CGT_HCR_TVM_TRVM), 707 SR_TRAP(SYS_ESR_EL1, CGT_HCR_TVM_TRVM), 708 SR_TRAP(SYS_FAR_EL1, CGT_HCR_TVM_TRVM), 709 SR_TRAP(SYS_AFSR0_EL1, CGT_HCR_TVM_TRVM), 710 SR_TRAP(SYS_AFSR1_EL1, CGT_HCR_TVM_TRVM), 711 SR_TRAP(SYS_MAIR_EL1, CGT_HCR_TVM_TRVM), 712 SR_TRAP(SYS_AMAIR_EL1, CGT_HCR_TVM_TRVM), 713 SR_TRAP(SYS_CONTEXTIDR_EL1, CGT_HCR_TVM_TRVM), 714 SR_TRAP(SYS_TCR2_EL1, CGT_HCR_TVM_TRVM_HCRX_TCR2En), 715 SR_TRAP(SYS_DC_ZVA, CGT_HCR_TDZ), 716 SR_TRAP(SYS_DC_GVA, CGT_HCR_TDZ), 717 SR_TRAP(SYS_DC_GZVA, CGT_HCR_TDZ), 718 SR_TRAP(SYS_LORSA_EL1, CGT_HCR_TLOR), 719 SR_TRAP(SYS_LOREA_EL1, CGT_HCR_TLOR), 720 SR_TRAP(SYS_LORN_EL1, CGT_HCR_TLOR), 721 SR_TRAP(SYS_LORC_EL1, CGT_HCR_TLOR), 722 SR_TRAP(SYS_LORID_EL1, CGT_HCR_TLOR), 723 SR_TRAP(SYS_ERRIDR_EL1, CGT_HCR_TERR), 724 SR_TRAP(SYS_ERRSELR_EL1, CGT_HCR_TERR), 725 SR_TRAP(SYS_ERXADDR_EL1, CGT_HCR_TERR), 726 SR_TRAP(SYS_ERXCTLR_EL1, CGT_HCR_TERR), 727 SR_TRAP(SYS_ERXFR_EL1, CGT_HCR_TERR), 728 SR_TRAP(SYS_ERXMISC0_EL1, CGT_HCR_TERR), 729 SR_TRAP(SYS_ERXMISC1_EL1, CGT_HCR_TERR), 730 SR_TRAP(SYS_ERXMISC2_EL1, CGT_HCR_TERR), 731 SR_TRAP(SYS_ERXMISC3_EL1, CGT_HCR_TERR), 732 SR_TRAP(SYS_ERXSTATUS_EL1, CGT_HCR_TERR), 733 SR_TRAP(SYS_APIAKEYLO_EL1, CGT_HCR_APK), 734 SR_TRAP(SYS_APIAKEYHI_EL1, CGT_HCR_APK), 735 SR_TRAP(SYS_APIBKEYLO_EL1, CGT_HCR_APK), 736 SR_TRAP(SYS_APIBKEYHI_EL1, CGT_HCR_APK), 737 SR_TRAP(SYS_APDAKEYLO_EL1, CGT_HCR_APK), 738 SR_TRAP(SYS_APDAKEYHI_EL1, CGT_HCR_APK), 739 SR_TRAP(SYS_APDBKEYLO_EL1, CGT_HCR_APK), 740 SR_TRAP(SYS_APDBKEYHI_EL1, CGT_HCR_APK), 741 SR_TRAP(SYS_APGAKEYLO_EL1, CGT_HCR_APK), 742 SR_TRAP(SYS_APGAKEYHI_EL1, CGT_HCR_APK), 743 /* All _EL2 registers */ 744 SR_TRAP(SYS_BRBCR_EL2, CGT_HCR_NV), 745 SR_TRAP(SYS_VPIDR_EL2, CGT_HCR_NV), 746 SR_TRAP(SYS_VMPIDR_EL2, CGT_HCR_NV), 747 SR_TRAP(SYS_SCTLR_EL2, CGT_HCR_NV), 748 SR_TRAP(SYS_ACTLR_EL2, CGT_HCR_NV), 749 SR_TRAP(SYS_SCTLR2_EL2, CGT_HCR_NV), 750 SR_RANGE_TRAP(SYS_HCR_EL2, 751 SYS_HCRX_EL2, CGT_HCR_NV), 752 SR_TRAP(SYS_SMPRIMAP_EL2, CGT_HCR_NV), 753 SR_TRAP(SYS_SMCR_EL2, CGT_HCR_NV), 754 SR_RANGE_TRAP(SYS_TTBR0_EL2, 755 SYS_TCR2_EL2, CGT_HCR_NV), 756 SR_TRAP(SYS_VTTBR_EL2, CGT_HCR_NV), 757 SR_TRAP(SYS_VTCR_EL2, CGT_HCR_NV), 758 SR_TRAP(SYS_VNCR_EL2, CGT_HCR_NV), 759 SR_RANGE_TRAP(SYS_HDFGRTR_EL2, 760 SYS_HAFGRTR_EL2, CGT_HCR_NV), 761 /* Skip the SP_EL1 encoding... */ 762 SR_TRAP(SYS_SPSR_EL2, CGT_HCR_NV), 763 SR_TRAP(SYS_ELR_EL2, CGT_HCR_NV), 764 /* Skip SPSR_irq, SPSR_abt, SPSR_und, SPSR_fiq */ 765 SR_TRAP(SYS_AFSR0_EL2, CGT_HCR_NV), 766 SR_TRAP(SYS_AFSR1_EL2, CGT_HCR_NV), 767 SR_TRAP(SYS_ESR_EL2, CGT_HCR_NV), 768 SR_TRAP(SYS_VSESR_EL2, CGT_HCR_NV), 769 SR_TRAP(SYS_TFSR_EL2, CGT_HCR_NV), 770 SR_TRAP(SYS_FAR_EL2, CGT_HCR_NV), 771 SR_TRAP(SYS_HPFAR_EL2, CGT_HCR_NV), 772 SR_TRAP(SYS_PMSCR_EL2, CGT_HCR_NV), 773 SR_TRAP(SYS_MAIR_EL2, CGT_HCR_NV), 774 SR_TRAP(SYS_AMAIR_EL2, CGT_HCR_NV), 775 SR_TRAP(SYS_MPAMHCR_EL2, CGT_HCR_NV), 776 SR_TRAP(SYS_MPAMVPMV_EL2, CGT_HCR_NV), 777 SR_TRAP(SYS_MPAM2_EL2, CGT_HCR_NV), 778 SR_RANGE_TRAP(SYS_MPAMVPM0_EL2, 779 SYS_MPAMVPM7_EL2, CGT_HCR_NV), 780 /* 781 * Note that the spec. describes a group of MEC registers 782 * whose access should not trap, therefore skip the following: 783 * MECID_A0_EL2, MECID_A1_EL2, MECID_P0_EL2, 784 * MECID_P1_EL2, MECIDR_EL2, VMECID_A_EL2, 785 * VMECID_P_EL2. 786 */ 787 SR_RANGE_TRAP(SYS_VBAR_EL2, 788 SYS_RMR_EL2, CGT_HCR_NV), 789 SR_TRAP(SYS_VDISR_EL2, CGT_HCR_NV), 790 /* ICH_AP0R<m>_EL2 */ 791 SR_RANGE_TRAP(SYS_ICH_AP0R0_EL2, 792 SYS_ICH_AP0R3_EL2, CGT_HCR_NV), 793 /* ICH_AP1R<m>_EL2 */ 794 SR_RANGE_TRAP(SYS_ICH_AP1R0_EL2, 795 SYS_ICH_AP1R3_EL2, CGT_HCR_NV), 796 SR_TRAP(SYS_ICC_SRE_EL2, CGT_HCR_NV), 797 SR_RANGE_TRAP(SYS_ICH_HCR_EL2, 798 SYS_ICH_EISR_EL2, CGT_HCR_NV), 799 SR_TRAP(SYS_ICH_ELRSR_EL2, CGT_HCR_NV), 800 SR_TRAP(SYS_ICH_VMCR_EL2, CGT_HCR_NV), 801 /* ICH_LR<m>_EL2 */ 802 SR_RANGE_TRAP(SYS_ICH_LR0_EL2, 803 SYS_ICH_LR15_EL2, CGT_HCR_NV), 804 SR_TRAP(SYS_CONTEXTIDR_EL2, CGT_HCR_NV), 805 SR_TRAP(SYS_TPIDR_EL2, CGT_HCR_NV), 806 SR_TRAP(SYS_SCXTNUM_EL2, CGT_HCR_NV), 807 /* AMEVCNTVOFF0<n>_EL2, AMEVCNTVOFF1<n>_EL2 */ 808 SR_RANGE_TRAP(SYS_AMEVCNTVOFF0n_EL2(0), 809 SYS_AMEVCNTVOFF1n_EL2(15), CGT_HCR_NV), 810 /* CNT*_EL2 */ 811 SR_TRAP(SYS_CNTVOFF_EL2, CGT_HCR_NV), 812 SR_TRAP(SYS_CNTPOFF_EL2, CGT_HCR_NV), 813 SR_TRAP(SYS_CNTHCTL_EL2, CGT_HCR_NV), 814 SR_RANGE_TRAP(SYS_CNTHP_TVAL_EL2, 815 SYS_CNTHP_CVAL_EL2, CGT_HCR_NV), 816 SR_RANGE_TRAP(SYS_CNTHV_TVAL_EL2, 817 SYS_CNTHV_CVAL_EL2, CGT_HCR_NV), 818 /* All _EL02, _EL12 registers */ 819 SR_RANGE_TRAP(sys_reg(3, 5, 0, 0, 0), 820 sys_reg(3, 5, 10, 15, 7), CGT_HCR_NV), 821 SR_RANGE_TRAP(sys_reg(3, 5, 12, 0, 0), 822 sys_reg(3, 5, 14, 15, 7), CGT_HCR_NV), 823 SR_TRAP(OP_AT_S1E2R, CGT_HCR_NV), 824 SR_TRAP(OP_AT_S1E2W, CGT_HCR_NV), 825 SR_TRAP(OP_AT_S12E1R, CGT_HCR_NV), 826 SR_TRAP(OP_AT_S12E1W, CGT_HCR_NV), 827 SR_TRAP(OP_AT_S12E0R, CGT_HCR_NV), 828 SR_TRAP(OP_AT_S12E0W, CGT_HCR_NV), 829 SR_TRAP(OP_AT_S1E2A, CGT_HCR_NV), 830 SR_TRAP(OP_TLBI_IPAS2E1, CGT_HCR_NV), 831 SR_TRAP(OP_TLBI_RIPAS2E1, CGT_HCR_NV), 832 SR_TRAP(OP_TLBI_IPAS2LE1, CGT_HCR_NV), 833 SR_TRAP(OP_TLBI_RIPAS2LE1, CGT_HCR_NV), 834 SR_TRAP(OP_TLBI_RVAE2, CGT_HCR_NV), 835 SR_TRAP(OP_TLBI_RVALE2, CGT_HCR_NV), 836 SR_TRAP(OP_TLBI_ALLE2, CGT_HCR_NV), 837 SR_TRAP(OP_TLBI_VAE2, CGT_HCR_NV), 838 SR_TRAP(OP_TLBI_ALLE1, CGT_HCR_NV), 839 SR_TRAP(OP_TLBI_VALE2, CGT_HCR_NV), 840 SR_TRAP(OP_TLBI_VMALLS12E1, CGT_HCR_NV), 841 SR_TRAP(OP_TLBI_IPAS2E1NXS, CGT_HCR_NV), 842 SR_TRAP(OP_TLBI_RIPAS2E1NXS, CGT_HCR_NV), 843 SR_TRAP(OP_TLBI_IPAS2LE1NXS, CGT_HCR_NV), 844 SR_TRAP(OP_TLBI_RIPAS2LE1NXS, CGT_HCR_NV), 845 SR_TRAP(OP_TLBI_RVAE2NXS, CGT_HCR_NV), 846 SR_TRAP(OP_TLBI_RVALE2NXS, CGT_HCR_NV), 847 SR_TRAP(OP_TLBI_ALLE2NXS, CGT_HCR_NV), 848 SR_TRAP(OP_TLBI_VAE2NXS, CGT_HCR_NV), 849 SR_TRAP(OP_TLBI_ALLE1NXS, CGT_HCR_NV), 850 SR_TRAP(OP_TLBI_VALE2NXS, CGT_HCR_NV), 851 SR_TRAP(OP_TLBI_VMALLS12E1NXS, CGT_HCR_NV), 852 SR_TRAP(OP_TLBI_IPAS2E1IS, CGT_HCR_NV), 853 SR_TRAP(OP_TLBI_RIPAS2E1IS, CGT_HCR_NV), 854 SR_TRAP(OP_TLBI_IPAS2LE1IS, CGT_HCR_NV), 855 SR_TRAP(OP_TLBI_RIPAS2LE1IS, CGT_HCR_NV), 856 SR_TRAP(OP_TLBI_RVAE2IS, CGT_HCR_NV), 857 SR_TRAP(OP_TLBI_RVALE2IS, CGT_HCR_NV), 858 SR_TRAP(OP_TLBI_ALLE2IS, CGT_HCR_NV), 859 SR_TRAP(OP_TLBI_VAE2IS, CGT_HCR_NV), 860 SR_TRAP(OP_TLBI_ALLE1IS, CGT_HCR_NV), 861 SR_TRAP(OP_TLBI_VALE2IS, CGT_HCR_NV), 862 SR_TRAP(OP_TLBI_VMALLS12E1IS, CGT_HCR_NV), 863 SR_TRAP(OP_TLBI_IPAS2E1ISNXS, CGT_HCR_NV), 864 SR_TRAP(OP_TLBI_RIPAS2E1ISNXS, CGT_HCR_NV), 865 SR_TRAP(OP_TLBI_IPAS2LE1ISNXS, CGT_HCR_NV), 866 SR_TRAP(OP_TLBI_RIPAS2LE1ISNXS, CGT_HCR_NV), 867 SR_TRAP(OP_TLBI_RVAE2ISNXS, CGT_HCR_NV), 868 SR_TRAP(OP_TLBI_RVALE2ISNXS, CGT_HCR_NV), 869 SR_TRAP(OP_TLBI_ALLE2ISNXS, CGT_HCR_NV), 870 SR_TRAP(OP_TLBI_VAE2ISNXS, CGT_HCR_NV), 871 SR_TRAP(OP_TLBI_ALLE1ISNXS, CGT_HCR_NV), 872 SR_TRAP(OP_TLBI_VALE2ISNXS, CGT_HCR_NV), 873 SR_TRAP(OP_TLBI_VMALLS12E1ISNXS,CGT_HCR_NV), 874 SR_TRAP(OP_TLBI_ALLE2OS, CGT_HCR_NV), 875 SR_TRAP(OP_TLBI_VAE2OS, CGT_HCR_NV), 876 SR_TRAP(OP_TLBI_ALLE1OS, CGT_HCR_NV), 877 SR_TRAP(OP_TLBI_VALE2OS, CGT_HCR_NV), 878 SR_TRAP(OP_TLBI_VMALLS12E1OS, CGT_HCR_NV), 879 SR_TRAP(OP_TLBI_IPAS2E1OS, CGT_HCR_NV), 880 SR_TRAP(OP_TLBI_RIPAS2E1OS, CGT_HCR_NV), 881 SR_TRAP(OP_TLBI_IPAS2LE1OS, CGT_HCR_NV), 882 SR_TRAP(OP_TLBI_RIPAS2LE1OS, CGT_HCR_NV), 883 SR_TRAP(OP_TLBI_RVAE2OS, CGT_HCR_NV), 884 SR_TRAP(OP_TLBI_RVALE2OS, CGT_HCR_NV), 885 SR_TRAP(OP_TLBI_ALLE2OSNXS, CGT_HCR_NV), 886 SR_TRAP(OP_TLBI_VAE2OSNXS, CGT_HCR_NV), 887 SR_TRAP(OP_TLBI_ALLE1OSNXS, CGT_HCR_NV), 888 SR_TRAP(OP_TLBI_VALE2OSNXS, CGT_HCR_NV), 889 SR_TRAP(OP_TLBI_VMALLS12E1OSNXS,CGT_HCR_NV), 890 SR_TRAP(OP_TLBI_IPAS2E1OSNXS, CGT_HCR_NV), 891 SR_TRAP(OP_TLBI_RIPAS2E1OSNXS, CGT_HCR_NV), 892 SR_TRAP(OP_TLBI_IPAS2LE1OSNXS, CGT_HCR_NV), 893 SR_TRAP(OP_TLBI_RIPAS2LE1OSNXS, CGT_HCR_NV), 894 SR_TRAP(OP_TLBI_RVAE2OSNXS, CGT_HCR_NV), 895 SR_TRAP(OP_TLBI_RVALE2OSNXS, CGT_HCR_NV), 896 SR_TRAP(OP_CPP_RCTX, CGT_HCR_NV), 897 SR_TRAP(OP_DVP_RCTX, CGT_HCR_NV), 898 SR_TRAP(OP_CFP_RCTX, CGT_HCR_NV), 899 SR_TRAP(SYS_SP_EL1, CGT_HCR_NV_nNV2), 900 SR_TRAP(SYS_VBAR_EL1, CGT_HCR_NV1_nNV2), 901 SR_TRAP(SYS_ELR_EL1, CGT_HCR_NV1_nNV2), 902 SR_TRAP(SYS_SPSR_EL1, CGT_HCR_NV1_nNV2), 903 SR_TRAP(SYS_SCXTNUM_EL1, CGT_HCR_NV1_nNV2_ENSCXT), 904 SR_TRAP(SYS_SCXTNUM_EL0, CGT_HCR_ENSCXT), 905 SR_TRAP(OP_AT_S1E1R, CGT_HCR_AT), 906 SR_TRAP(OP_AT_S1E1W, CGT_HCR_AT), 907 SR_TRAP(OP_AT_S1E0R, CGT_HCR_AT), 908 SR_TRAP(OP_AT_S1E0W, CGT_HCR_AT), 909 SR_TRAP(OP_AT_S1E1RP, CGT_HCR_AT), 910 SR_TRAP(OP_AT_S1E1WP, CGT_HCR_AT), 911 SR_TRAP(OP_AT_S1E1A, CGT_HCR_AT), 912 SR_TRAP(SYS_ERXPFGF_EL1, CGT_HCR_nFIEN), 913 SR_TRAP(SYS_ERXPFGCTL_EL1, CGT_HCR_nFIEN), 914 SR_TRAP(SYS_ERXPFGCDN_EL1, CGT_HCR_nFIEN), 915 SR_TRAP(SYS_PMCR_EL0, CGT_MDCR_TPM_TPMCR), 916 SR_TRAP(SYS_PMCNTENSET_EL0, CGT_MDCR_TPM), 917 SR_TRAP(SYS_PMCNTENCLR_EL0, CGT_MDCR_TPM), 918 SR_TRAP(SYS_PMOVSSET_EL0, CGT_MDCR_TPM), 919 SR_TRAP(SYS_PMOVSCLR_EL0, CGT_MDCR_TPM), 920 SR_TRAP(SYS_PMCEID0_EL0, CGT_MDCR_TPM), 921 SR_TRAP(SYS_PMCEID1_EL0, CGT_MDCR_TPM), 922 SR_TRAP(SYS_PMXEVTYPER_EL0, CGT_MDCR_TPM), 923 SR_TRAP(SYS_PMSWINC_EL0, CGT_MDCR_TPM), 924 SR_TRAP(SYS_PMSELR_EL0, CGT_MDCR_TPM), 925 SR_TRAP(SYS_PMXEVCNTR_EL0, CGT_MDCR_TPM), 926 SR_TRAP(SYS_PMCCNTR_EL0, CGT_MDCR_TPM), 927 SR_TRAP(SYS_PMUSERENR_EL0, CGT_MDCR_TPM), 928 SR_TRAP(SYS_PMINTENSET_EL1, CGT_MDCR_TPM), 929 SR_TRAP(SYS_PMINTENCLR_EL1, CGT_MDCR_TPM), 930 SR_TRAP(SYS_PMMIR_EL1, CGT_MDCR_TPM), 931 SR_TRAP(SYS_PMEVCNTRn_EL0(0), CGT_MDCR_TPM), 932 SR_TRAP(SYS_PMEVCNTRn_EL0(1), CGT_MDCR_TPM), 933 SR_TRAP(SYS_PMEVCNTRn_EL0(2), CGT_MDCR_TPM), 934 SR_TRAP(SYS_PMEVCNTRn_EL0(3), CGT_MDCR_TPM), 935 SR_TRAP(SYS_PMEVCNTRn_EL0(4), CGT_MDCR_TPM), 936 SR_TRAP(SYS_PMEVCNTRn_EL0(5), CGT_MDCR_TPM), 937 SR_TRAP(SYS_PMEVCNTRn_EL0(6), CGT_MDCR_TPM), 938 SR_TRAP(SYS_PMEVCNTRn_EL0(7), CGT_MDCR_TPM), 939 SR_TRAP(SYS_PMEVCNTRn_EL0(8), CGT_MDCR_TPM), 940 SR_TRAP(SYS_PMEVCNTRn_EL0(9), CGT_MDCR_TPM), 941 SR_TRAP(SYS_PMEVCNTRn_EL0(10), CGT_MDCR_TPM), 942 SR_TRAP(SYS_PMEVCNTRn_EL0(11), CGT_MDCR_TPM), 943 SR_TRAP(SYS_PMEVCNTRn_EL0(12), CGT_MDCR_TPM), 944 SR_TRAP(SYS_PMEVCNTRn_EL0(13), CGT_MDCR_TPM), 945 SR_TRAP(SYS_PMEVCNTRn_EL0(14), CGT_MDCR_TPM), 946 SR_TRAP(SYS_PMEVCNTRn_EL0(15), CGT_MDCR_TPM), 947 SR_TRAP(SYS_PMEVCNTRn_EL0(16), CGT_MDCR_TPM), 948 SR_TRAP(SYS_PMEVCNTRn_EL0(17), CGT_MDCR_TPM), 949 SR_TRAP(SYS_PMEVCNTRn_EL0(18), CGT_MDCR_TPM), 950 SR_TRAP(SYS_PMEVCNTRn_EL0(19), CGT_MDCR_TPM), 951 SR_TRAP(SYS_PMEVCNTRn_EL0(20), CGT_MDCR_TPM), 952 SR_TRAP(SYS_PMEVCNTRn_EL0(21), CGT_MDCR_TPM), 953 SR_TRAP(SYS_PMEVCNTRn_EL0(22), CGT_MDCR_TPM), 954 SR_TRAP(SYS_PMEVCNTRn_EL0(23), CGT_MDCR_TPM), 955 SR_TRAP(SYS_PMEVCNTRn_EL0(24), CGT_MDCR_TPM), 956 SR_TRAP(SYS_PMEVCNTRn_EL0(25), CGT_MDCR_TPM), 957 SR_TRAP(SYS_PMEVCNTRn_EL0(26), CGT_MDCR_TPM), 958 SR_TRAP(SYS_PMEVCNTRn_EL0(27), CGT_MDCR_TPM), 959 SR_TRAP(SYS_PMEVCNTRn_EL0(28), CGT_MDCR_TPM), 960 SR_TRAP(SYS_PMEVCNTRn_EL0(29), CGT_MDCR_TPM), 961 SR_TRAP(SYS_PMEVCNTRn_EL0(30), CGT_MDCR_TPM), 962 SR_TRAP(SYS_PMEVTYPERn_EL0(0), CGT_MDCR_TPM), 963 SR_TRAP(SYS_PMEVTYPERn_EL0(1), CGT_MDCR_TPM), 964 SR_TRAP(SYS_PMEVTYPERn_EL0(2), CGT_MDCR_TPM), 965 SR_TRAP(SYS_PMEVTYPERn_EL0(3), CGT_MDCR_TPM), 966 SR_TRAP(SYS_PMEVTYPERn_EL0(4), CGT_MDCR_TPM), 967 SR_TRAP(SYS_PMEVTYPERn_EL0(5), CGT_MDCR_TPM), 968 SR_TRAP(SYS_PMEVTYPERn_EL0(6), CGT_MDCR_TPM), 969 SR_TRAP(SYS_PMEVTYPERn_EL0(7), CGT_MDCR_TPM), 970 SR_TRAP(SYS_PMEVTYPERn_EL0(8), CGT_MDCR_TPM), 971 SR_TRAP(SYS_PMEVTYPERn_EL0(9), CGT_MDCR_TPM), 972 SR_TRAP(SYS_PMEVTYPERn_EL0(10), CGT_MDCR_TPM), 973 SR_TRAP(SYS_PMEVTYPERn_EL0(11), CGT_MDCR_TPM), 974 SR_TRAP(SYS_PMEVTYPERn_EL0(12), CGT_MDCR_TPM), 975 SR_TRAP(SYS_PMEVTYPERn_EL0(13), CGT_MDCR_TPM), 976 SR_TRAP(SYS_PMEVTYPERn_EL0(14), CGT_MDCR_TPM), 977 SR_TRAP(SYS_PMEVTYPERn_EL0(15), CGT_MDCR_TPM), 978 SR_TRAP(SYS_PMEVTYPERn_EL0(16), CGT_MDCR_TPM), 979 SR_TRAP(SYS_PMEVTYPERn_EL0(17), CGT_MDCR_TPM), 980 SR_TRAP(SYS_PMEVTYPERn_EL0(18), CGT_MDCR_TPM), 981 SR_TRAP(SYS_PMEVTYPERn_EL0(19), CGT_MDCR_TPM), 982 SR_TRAP(SYS_PMEVTYPERn_EL0(20), CGT_MDCR_TPM), 983 SR_TRAP(SYS_PMEVTYPERn_EL0(21), CGT_MDCR_TPM), 984 SR_TRAP(SYS_PMEVTYPERn_EL0(22), CGT_MDCR_TPM), 985 SR_TRAP(SYS_PMEVTYPERn_EL0(23), CGT_MDCR_TPM), 986 SR_TRAP(SYS_PMEVTYPERn_EL0(24), CGT_MDCR_TPM), 987 SR_TRAP(SYS_PMEVTYPERn_EL0(25), CGT_MDCR_TPM), 988 SR_TRAP(SYS_PMEVTYPERn_EL0(26), CGT_MDCR_TPM), 989 SR_TRAP(SYS_PMEVTYPERn_EL0(27), CGT_MDCR_TPM), 990 SR_TRAP(SYS_PMEVTYPERn_EL0(28), CGT_MDCR_TPM), 991 SR_TRAP(SYS_PMEVTYPERn_EL0(29), CGT_MDCR_TPM), 992 SR_TRAP(SYS_PMEVTYPERn_EL0(30), CGT_MDCR_TPM), 993 SR_TRAP(SYS_PMCCFILTR_EL0, CGT_MDCR_TPM), 994 SR_TRAP(SYS_MDCCSR_EL0, CGT_MDCR_TDCC_TDE_TDA), 995 SR_TRAP(SYS_MDCCINT_EL1, CGT_MDCR_TDCC_TDE_TDA), 996 SR_TRAP(SYS_OSDTRRX_EL1, CGT_MDCR_TDCC_TDE_TDA), 997 SR_TRAP(SYS_OSDTRTX_EL1, CGT_MDCR_TDCC_TDE_TDA), 998 SR_TRAP(SYS_DBGDTR_EL0, CGT_MDCR_TDCC_TDE_TDA), 999 /* 1000 * Also covers DBGDTRRX_EL0, which has the same encoding as 1001 * SYS_DBGDTRTX_EL0... 1002 */ 1003 SR_TRAP(SYS_DBGDTRTX_EL0, CGT_MDCR_TDCC_TDE_TDA), 1004 SR_TRAP(SYS_MDSCR_EL1, CGT_MDCR_TDE_TDA), 1005 SR_TRAP(SYS_OSECCR_EL1, CGT_MDCR_TDE_TDA), 1006 SR_TRAP(SYS_DBGBVRn_EL1(0), CGT_MDCR_TDE_TDA), 1007 SR_TRAP(SYS_DBGBVRn_EL1(1), CGT_MDCR_TDE_TDA), 1008 SR_TRAP(SYS_DBGBVRn_EL1(2), CGT_MDCR_TDE_TDA), 1009 SR_TRAP(SYS_DBGBVRn_EL1(3), CGT_MDCR_TDE_TDA), 1010 SR_TRAP(SYS_DBGBVRn_EL1(4), CGT_MDCR_TDE_TDA), 1011 SR_TRAP(SYS_DBGBVRn_EL1(5), CGT_MDCR_TDE_TDA), 1012 SR_TRAP(SYS_DBGBVRn_EL1(6), CGT_MDCR_TDE_TDA), 1013 SR_TRAP(SYS_DBGBVRn_EL1(7), CGT_MDCR_TDE_TDA), 1014 SR_TRAP(SYS_DBGBVRn_EL1(8), CGT_MDCR_TDE_TDA), 1015 SR_TRAP(SYS_DBGBVRn_EL1(9), CGT_MDCR_TDE_TDA), 1016 SR_TRAP(SYS_DBGBVRn_EL1(10), CGT_MDCR_TDE_TDA), 1017 SR_TRAP(SYS_DBGBVRn_EL1(11), CGT_MDCR_TDE_TDA), 1018 SR_TRAP(SYS_DBGBVRn_EL1(12), CGT_MDCR_TDE_TDA), 1019 SR_TRAP(SYS_DBGBVRn_EL1(13), CGT_MDCR_TDE_TDA), 1020 SR_TRAP(SYS_DBGBVRn_EL1(14), CGT_MDCR_TDE_TDA), 1021 SR_TRAP(SYS_DBGBVRn_EL1(15), CGT_MDCR_TDE_TDA), 1022 SR_TRAP(SYS_DBGBCRn_EL1(0), CGT_MDCR_TDE_TDA), 1023 SR_TRAP(SYS_DBGBCRn_EL1(1), CGT_MDCR_TDE_TDA), 1024 SR_TRAP(SYS_DBGBCRn_EL1(2), CGT_MDCR_TDE_TDA), 1025 SR_TRAP(SYS_DBGBCRn_EL1(3), CGT_MDCR_TDE_TDA), 1026 SR_TRAP(SYS_DBGBCRn_EL1(4), CGT_MDCR_TDE_TDA), 1027 SR_TRAP(SYS_DBGBCRn_EL1(5), CGT_MDCR_TDE_TDA), 1028 SR_TRAP(SYS_DBGBCRn_EL1(6), CGT_MDCR_TDE_TDA), 1029 SR_TRAP(SYS_DBGBCRn_EL1(7), CGT_MDCR_TDE_TDA), 1030 SR_TRAP(SYS_DBGBCRn_EL1(8), CGT_MDCR_TDE_TDA), 1031 SR_TRAP(SYS_DBGBCRn_EL1(9), CGT_MDCR_TDE_TDA), 1032 SR_TRAP(SYS_DBGBCRn_EL1(10), CGT_MDCR_TDE_TDA), 1033 SR_TRAP(SYS_DBGBCRn_EL1(11), CGT_MDCR_TDE_TDA), 1034 SR_TRAP(SYS_DBGBCRn_EL1(12), CGT_MDCR_TDE_TDA), 1035 SR_TRAP(SYS_DBGBCRn_EL1(13), CGT_MDCR_TDE_TDA), 1036 SR_TRAP(SYS_DBGBCRn_EL1(14), CGT_MDCR_TDE_TDA), 1037 SR_TRAP(SYS_DBGBCRn_EL1(15), CGT_MDCR_TDE_TDA), 1038 SR_TRAP(SYS_DBGWVRn_EL1(0), CGT_MDCR_TDE_TDA), 1039 SR_TRAP(SYS_DBGWVRn_EL1(1), CGT_MDCR_TDE_TDA), 1040 SR_TRAP(SYS_DBGWVRn_EL1(2), CGT_MDCR_TDE_TDA), 1041 SR_TRAP(SYS_DBGWVRn_EL1(3), CGT_MDCR_TDE_TDA), 1042 SR_TRAP(SYS_DBGWVRn_EL1(4), CGT_MDCR_TDE_TDA), 1043 SR_TRAP(SYS_DBGWVRn_EL1(5), CGT_MDCR_TDE_TDA), 1044 SR_TRAP(SYS_DBGWVRn_EL1(6), CGT_MDCR_TDE_TDA), 1045 SR_TRAP(SYS_DBGWVRn_EL1(7), CGT_MDCR_TDE_TDA), 1046 SR_TRAP(SYS_DBGWVRn_EL1(8), CGT_MDCR_TDE_TDA), 1047 SR_TRAP(SYS_DBGWVRn_EL1(9), CGT_MDCR_TDE_TDA), 1048 SR_TRAP(SYS_DBGWVRn_EL1(10), CGT_MDCR_TDE_TDA), 1049 SR_TRAP(SYS_DBGWVRn_EL1(11), CGT_MDCR_TDE_TDA), 1050 SR_TRAP(SYS_DBGWVRn_EL1(12), CGT_MDCR_TDE_TDA), 1051 SR_TRAP(SYS_DBGWVRn_EL1(13), CGT_MDCR_TDE_TDA), 1052 SR_TRAP(SYS_DBGWVRn_EL1(14), CGT_MDCR_TDE_TDA), 1053 SR_TRAP(SYS_DBGWVRn_EL1(15), CGT_MDCR_TDE_TDA), 1054 SR_TRAP(SYS_DBGWCRn_EL1(0), CGT_MDCR_TDE_TDA), 1055 SR_TRAP(SYS_DBGWCRn_EL1(1), CGT_MDCR_TDE_TDA), 1056 SR_TRAP(SYS_DBGWCRn_EL1(2), CGT_MDCR_TDE_TDA), 1057 SR_TRAP(SYS_DBGWCRn_EL1(3), CGT_MDCR_TDE_TDA), 1058 SR_TRAP(SYS_DBGWCRn_EL1(4), CGT_MDCR_TDE_TDA), 1059 SR_TRAP(SYS_DBGWCRn_EL1(5), CGT_MDCR_TDE_TDA), 1060 SR_TRAP(SYS_DBGWCRn_EL1(6), CGT_MDCR_TDE_TDA), 1061 SR_TRAP(SYS_DBGWCRn_EL1(7), CGT_MDCR_TDE_TDA), 1062 SR_TRAP(SYS_DBGWCRn_EL1(8), CGT_MDCR_TDE_TDA), 1063 SR_TRAP(SYS_DBGWCRn_EL1(9), CGT_MDCR_TDE_TDA), 1064 SR_TRAP(SYS_DBGWCRn_EL1(10), CGT_MDCR_TDE_TDA), 1065 SR_TRAP(SYS_DBGWCRn_EL1(11), CGT_MDCR_TDE_TDA), 1066 SR_TRAP(SYS_DBGWCRn_EL1(12), CGT_MDCR_TDE_TDA), 1067 SR_TRAP(SYS_DBGWCRn_EL1(13), CGT_MDCR_TDE_TDA), 1068 SR_TRAP(SYS_DBGWCRn_EL1(14), CGT_MDCR_TDE_TDA), 1069 SR_TRAP(SYS_DBGCLAIMSET_EL1, CGT_MDCR_TDE_TDA), 1070 SR_TRAP(SYS_DBGCLAIMCLR_EL1, CGT_MDCR_TDE_TDA), 1071 SR_TRAP(SYS_DBGAUTHSTATUS_EL1, CGT_MDCR_TDE_TDA), 1072 SR_TRAP(SYS_OSLAR_EL1, CGT_MDCR_TDE_TDOSA), 1073 SR_TRAP(SYS_OSLSR_EL1, CGT_MDCR_TDE_TDOSA), 1074 SR_TRAP(SYS_OSDLR_EL1, CGT_MDCR_TDE_TDOSA), 1075 SR_TRAP(SYS_DBGPRCR_EL1, CGT_MDCR_TDE_TDOSA), 1076 SR_TRAP(SYS_MDRAR_EL1, CGT_MDCR_TDE_TDRA), 1077 SR_TRAP(SYS_PMBLIMITR_EL1, CGT_MDCR_E2PB), 1078 SR_TRAP(SYS_PMBPTR_EL1, CGT_MDCR_E2PB), 1079 SR_TRAP(SYS_PMBSR_EL1, CGT_MDCR_E2PB), 1080 SR_TRAP(SYS_PMSCR_EL1, CGT_MDCR_TPMS), 1081 SR_TRAP(SYS_PMSEVFR_EL1, CGT_MDCR_TPMS), 1082 SR_TRAP(SYS_PMSFCR_EL1, CGT_MDCR_TPMS), 1083 SR_TRAP(SYS_PMSICR_EL1, CGT_MDCR_TPMS), 1084 SR_TRAP(SYS_PMSIDR_EL1, CGT_MDCR_TPMS), 1085 SR_TRAP(SYS_PMSIRR_EL1, CGT_MDCR_TPMS), 1086 SR_TRAP(SYS_PMSLATFR_EL1, CGT_MDCR_TPMS), 1087 SR_TRAP(SYS_PMSNEVFR_EL1, CGT_MDCR_TPMS), 1088 SR_TRAP(SYS_TRFCR_EL1, CGT_MDCR_TTRF), 1089 SR_TRAP(SYS_TRBBASER_EL1, CGT_MDCR_E2TB), 1090 SR_TRAP(SYS_TRBLIMITR_EL1, CGT_MDCR_E2TB), 1091 SR_TRAP(SYS_TRBMAR_EL1, CGT_MDCR_E2TB), 1092 SR_TRAP(SYS_TRBPTR_EL1, CGT_MDCR_E2TB), 1093 SR_TRAP(SYS_TRBSR_EL1, CGT_MDCR_E2TB), 1094 SR_TRAP(SYS_TRBTRG_EL1, CGT_MDCR_E2TB), 1095 SR_TRAP(SYS_CPACR_EL1, CGT_CPTR_TCPAC), 1096 SR_TRAP(SYS_AMUSERENR_EL0, CGT_CPTR_TAM), 1097 SR_TRAP(SYS_AMCFGR_EL0, CGT_CPTR_TAM), 1098 SR_TRAP(SYS_AMCGCR_EL0, CGT_CPTR_TAM), 1099 SR_TRAP(SYS_AMCNTENCLR0_EL0, CGT_CPTR_TAM), 1100 SR_TRAP(SYS_AMCNTENCLR1_EL0, CGT_CPTR_TAM), 1101 SR_TRAP(SYS_AMCNTENSET0_EL0, CGT_CPTR_TAM), 1102 SR_TRAP(SYS_AMCNTENSET1_EL0, CGT_CPTR_TAM), 1103 SR_TRAP(SYS_AMCR_EL0, CGT_CPTR_TAM), 1104 SR_TRAP(SYS_AMEVCNTR0_EL0(0), CGT_CPTR_TAM), 1105 SR_TRAP(SYS_AMEVCNTR0_EL0(1), CGT_CPTR_TAM), 1106 SR_TRAP(SYS_AMEVCNTR0_EL0(2), CGT_CPTR_TAM), 1107 SR_TRAP(SYS_AMEVCNTR0_EL0(3), CGT_CPTR_TAM), 1108 SR_TRAP(SYS_AMEVCNTR1_EL0(0), CGT_CPTR_TAM), 1109 SR_TRAP(SYS_AMEVCNTR1_EL0(1), CGT_CPTR_TAM), 1110 SR_TRAP(SYS_AMEVCNTR1_EL0(2), CGT_CPTR_TAM), 1111 SR_TRAP(SYS_AMEVCNTR1_EL0(3), CGT_CPTR_TAM), 1112 SR_TRAP(SYS_AMEVCNTR1_EL0(4), CGT_CPTR_TAM), 1113 SR_TRAP(SYS_AMEVCNTR1_EL0(5), CGT_CPTR_TAM), 1114 SR_TRAP(SYS_AMEVCNTR1_EL0(6), CGT_CPTR_TAM), 1115 SR_TRAP(SYS_AMEVCNTR1_EL0(7), CGT_CPTR_TAM), 1116 SR_TRAP(SYS_AMEVCNTR1_EL0(8), CGT_CPTR_TAM), 1117 SR_TRAP(SYS_AMEVCNTR1_EL0(9), CGT_CPTR_TAM), 1118 SR_TRAP(SYS_AMEVCNTR1_EL0(10), CGT_CPTR_TAM), 1119 SR_TRAP(SYS_AMEVCNTR1_EL0(11), CGT_CPTR_TAM), 1120 SR_TRAP(SYS_AMEVCNTR1_EL0(12), CGT_CPTR_TAM), 1121 SR_TRAP(SYS_AMEVCNTR1_EL0(13), CGT_CPTR_TAM), 1122 SR_TRAP(SYS_AMEVCNTR1_EL0(14), CGT_CPTR_TAM), 1123 SR_TRAP(SYS_AMEVCNTR1_EL0(15), CGT_CPTR_TAM), 1124 SR_TRAP(SYS_AMEVTYPER0_EL0(0), CGT_CPTR_TAM), 1125 SR_TRAP(SYS_AMEVTYPER0_EL0(1), CGT_CPTR_TAM), 1126 SR_TRAP(SYS_AMEVTYPER0_EL0(2), CGT_CPTR_TAM), 1127 SR_TRAP(SYS_AMEVTYPER0_EL0(3), CGT_CPTR_TAM), 1128 SR_TRAP(SYS_AMEVTYPER1_EL0(0), CGT_CPTR_TAM), 1129 SR_TRAP(SYS_AMEVTYPER1_EL0(1), CGT_CPTR_TAM), 1130 SR_TRAP(SYS_AMEVTYPER1_EL0(2), CGT_CPTR_TAM), 1131 SR_TRAP(SYS_AMEVTYPER1_EL0(3), CGT_CPTR_TAM), 1132 SR_TRAP(SYS_AMEVTYPER1_EL0(4), CGT_CPTR_TAM), 1133 SR_TRAP(SYS_AMEVTYPER1_EL0(5), CGT_CPTR_TAM), 1134 SR_TRAP(SYS_AMEVTYPER1_EL0(6), CGT_CPTR_TAM), 1135 SR_TRAP(SYS_AMEVTYPER1_EL0(7), CGT_CPTR_TAM), 1136 SR_TRAP(SYS_AMEVTYPER1_EL0(8), CGT_CPTR_TAM), 1137 SR_TRAP(SYS_AMEVTYPER1_EL0(9), CGT_CPTR_TAM), 1138 SR_TRAP(SYS_AMEVTYPER1_EL0(10), CGT_CPTR_TAM), 1139 SR_TRAP(SYS_AMEVTYPER1_EL0(11), CGT_CPTR_TAM), 1140 SR_TRAP(SYS_AMEVTYPER1_EL0(12), CGT_CPTR_TAM), 1141 SR_TRAP(SYS_AMEVTYPER1_EL0(13), CGT_CPTR_TAM), 1142 SR_TRAP(SYS_AMEVTYPER1_EL0(14), CGT_CPTR_TAM), 1143 SR_TRAP(SYS_AMEVTYPER1_EL0(15), CGT_CPTR_TAM), 1144 SR_TRAP(SYS_POR_EL0, CGT_CPACR_E0POE), 1145 /* op0=2, op1=1, and CRn<0b1000 */ 1146 SR_RANGE_TRAP(sys_reg(2, 1, 0, 0, 0), 1147 sys_reg(2, 1, 7, 15, 7), CGT_CPTR_TTA), 1148 SR_TRAP(SYS_CNTP_TVAL_EL0, CGT_CNTHCTL_EL1PTEN), 1149 SR_TRAP(SYS_CNTP_CVAL_EL0, CGT_CNTHCTL_EL1PTEN), 1150 SR_TRAP(SYS_CNTP_CTL_EL0, CGT_CNTHCTL_EL1PTEN), 1151 SR_TRAP(SYS_CNTPCT_EL0, CGT_CNTHCTL_EL1PCTEN), 1152 SR_TRAP(SYS_CNTPCTSS_EL0, CGT_CNTHCTL_EL1PCTEN), 1153 SR_TRAP(SYS_FPMR, CGT_HCRX_EnFPM), 1154 /* 1155 * IMPDEF choice: 1156 * We treat ICC_SRE_EL2.{SRE,Enable) and ICV_SRE_EL1.SRE as 1157 * RAO/WI. We therefore never consider ICC_SRE_EL2.Enable for 1158 * ICC_SRE_EL1 access, and always handle it locally. 1159 */ 1160 SR_TRAP(SYS_ICC_AP0R0_EL1, CGT_ICH_HCR_TALL0), 1161 SR_TRAP(SYS_ICC_AP0R1_EL1, CGT_ICH_HCR_TALL0), 1162 SR_TRAP(SYS_ICC_AP0R2_EL1, CGT_ICH_HCR_TALL0), 1163 SR_TRAP(SYS_ICC_AP0R3_EL1, CGT_ICH_HCR_TALL0), 1164 SR_TRAP(SYS_ICC_AP1R0_EL1, CGT_ICH_HCR_TALL1), 1165 SR_TRAP(SYS_ICC_AP1R1_EL1, CGT_ICH_HCR_TALL1), 1166 SR_TRAP(SYS_ICC_AP1R2_EL1, CGT_ICH_HCR_TALL1), 1167 SR_TRAP(SYS_ICC_AP1R3_EL1, CGT_ICH_HCR_TALL1), 1168 SR_TRAP(SYS_ICC_BPR0_EL1, CGT_ICH_HCR_TALL0), 1169 SR_TRAP(SYS_ICC_BPR1_EL1, CGT_ICH_HCR_TALL1), 1170 SR_TRAP(SYS_ICC_CTLR_EL1, CGT_ICH_HCR_TC), 1171 SR_TRAP(SYS_ICC_DIR_EL1, CGT_ICH_HCR_TC_TDIR), 1172 SR_TRAP(SYS_ICC_EOIR0_EL1, CGT_ICH_HCR_TALL0), 1173 SR_TRAP(SYS_ICC_EOIR1_EL1, CGT_ICH_HCR_TALL1), 1174 SR_TRAP(SYS_ICC_HPPIR0_EL1, CGT_ICH_HCR_TALL0), 1175 SR_TRAP(SYS_ICC_HPPIR1_EL1, CGT_ICH_HCR_TALL1), 1176 SR_TRAP(SYS_ICC_IAR0_EL1, CGT_ICH_HCR_TALL0), 1177 SR_TRAP(SYS_ICC_IAR1_EL1, CGT_ICH_HCR_TALL1), 1178 SR_TRAP(SYS_ICC_IGRPEN0_EL1, CGT_ICH_HCR_TALL0), 1179 SR_TRAP(SYS_ICC_IGRPEN1_EL1, CGT_ICH_HCR_TALL1), 1180 SR_TRAP(SYS_ICC_PMR_EL1, CGT_ICH_HCR_TC), 1181 SR_TRAP(SYS_ICC_RPR_EL1, CGT_ICH_HCR_TC), 1182 }; 1183 1184 static DEFINE_XARRAY(sr_forward_xa); 1185 1186 enum fg_filter_id { 1187 __NO_FGF__, 1188 HCRX_FGTnXS, 1189 1190 /* Must be last */ 1191 __NR_FG_FILTER_IDS__ 1192 }; 1193 1194 #define SR_FGF(sr, g, b, p, f) \ 1195 { \ 1196 .encoding = sr, \ 1197 .end = sr, \ 1198 .tc = { \ 1199 .fgt = g ## _GROUP, \ 1200 .bit = g ## _EL2_ ## b ## _SHIFT, \ 1201 .pol = p, \ 1202 .fgf = f, \ 1203 }, \ 1204 .line = __LINE__, \ 1205 } 1206 1207 #define SR_FGT(sr, g, b, p) SR_FGF(sr, g, b, p, __NO_FGF__) 1208 1209 static const struct encoding_to_trap_config encoding_to_fgt[] __initconst = { 1210 /* HFGRTR_EL2, HFGWTR_EL2 */ 1211 SR_FGT(SYS_AMAIR2_EL1, HFGxTR, nAMAIR2_EL1, 0), 1212 SR_FGT(SYS_MAIR2_EL1, HFGxTR, nMAIR2_EL1, 0), 1213 SR_FGT(SYS_S2POR_EL1, HFGxTR, nS2POR_EL1, 0), 1214 SR_FGT(SYS_POR_EL1, HFGxTR, nPOR_EL1, 0), 1215 SR_FGT(SYS_POR_EL0, HFGxTR, nPOR_EL0, 0), 1216 SR_FGT(SYS_PIR_EL1, HFGxTR, nPIR_EL1, 0), 1217 SR_FGT(SYS_PIRE0_EL1, HFGxTR, nPIRE0_EL1, 0), 1218 SR_FGT(SYS_RCWMASK_EL1, HFGxTR, nRCWMASK_EL1, 0), 1219 SR_FGT(SYS_TPIDR2_EL0, HFGxTR, nTPIDR2_EL0, 0), 1220 SR_FGT(SYS_SMPRI_EL1, HFGxTR, nSMPRI_EL1, 0), 1221 SR_FGT(SYS_GCSCR_EL1, HFGxTR, nGCS_EL1, 0), 1222 SR_FGT(SYS_GCSPR_EL1, HFGxTR, nGCS_EL1, 0), 1223 SR_FGT(SYS_GCSCRE0_EL1, HFGxTR, nGCS_EL0, 0), 1224 SR_FGT(SYS_GCSPR_EL0, HFGxTR, nGCS_EL0, 0), 1225 SR_FGT(SYS_ACCDATA_EL1, HFGxTR, nACCDATA_EL1, 0), 1226 SR_FGT(SYS_ERXADDR_EL1, HFGxTR, ERXADDR_EL1, 1), 1227 SR_FGT(SYS_ERXPFGCDN_EL1, HFGxTR, ERXPFGCDN_EL1, 1), 1228 SR_FGT(SYS_ERXPFGCTL_EL1, HFGxTR, ERXPFGCTL_EL1, 1), 1229 SR_FGT(SYS_ERXPFGF_EL1, HFGxTR, ERXPFGF_EL1, 1), 1230 SR_FGT(SYS_ERXMISC0_EL1, HFGxTR, ERXMISCn_EL1, 1), 1231 SR_FGT(SYS_ERXMISC1_EL1, HFGxTR, ERXMISCn_EL1, 1), 1232 SR_FGT(SYS_ERXMISC2_EL1, HFGxTR, ERXMISCn_EL1, 1), 1233 SR_FGT(SYS_ERXMISC3_EL1, HFGxTR, ERXMISCn_EL1, 1), 1234 SR_FGT(SYS_ERXSTATUS_EL1, HFGxTR, ERXSTATUS_EL1, 1), 1235 SR_FGT(SYS_ERXCTLR_EL1, HFGxTR, ERXCTLR_EL1, 1), 1236 SR_FGT(SYS_ERXFR_EL1, HFGxTR, ERXFR_EL1, 1), 1237 SR_FGT(SYS_ERRSELR_EL1, HFGxTR, ERRSELR_EL1, 1), 1238 SR_FGT(SYS_ERRIDR_EL1, HFGxTR, ERRIDR_EL1, 1), 1239 SR_FGT(SYS_ICC_IGRPEN0_EL1, HFGxTR, ICC_IGRPENn_EL1, 1), 1240 SR_FGT(SYS_ICC_IGRPEN1_EL1, HFGxTR, ICC_IGRPENn_EL1, 1), 1241 SR_FGT(SYS_VBAR_EL1, HFGxTR, VBAR_EL1, 1), 1242 SR_FGT(SYS_TTBR1_EL1, HFGxTR, TTBR1_EL1, 1), 1243 SR_FGT(SYS_TTBR0_EL1, HFGxTR, TTBR0_EL1, 1), 1244 SR_FGT(SYS_TPIDR_EL0, HFGxTR, TPIDR_EL0, 1), 1245 SR_FGT(SYS_TPIDRRO_EL0, HFGxTR, TPIDRRO_EL0, 1), 1246 SR_FGT(SYS_TPIDR_EL1, HFGxTR, TPIDR_EL1, 1), 1247 SR_FGT(SYS_TCR_EL1, HFGxTR, TCR_EL1, 1), 1248 SR_FGT(SYS_TCR2_EL1, HFGxTR, TCR_EL1, 1), 1249 SR_FGT(SYS_SCXTNUM_EL0, HFGxTR, SCXTNUM_EL0, 1), 1250 SR_FGT(SYS_SCXTNUM_EL1, HFGxTR, SCXTNUM_EL1, 1), 1251 SR_FGT(SYS_SCTLR_EL1, HFGxTR, SCTLR_EL1, 1), 1252 SR_FGT(SYS_REVIDR_EL1, HFGxTR, REVIDR_EL1, 1), 1253 SR_FGT(SYS_PAR_EL1, HFGxTR, PAR_EL1, 1), 1254 SR_FGT(SYS_MPIDR_EL1, HFGxTR, MPIDR_EL1, 1), 1255 SR_FGT(SYS_MIDR_EL1, HFGxTR, MIDR_EL1, 1), 1256 SR_FGT(SYS_MAIR_EL1, HFGxTR, MAIR_EL1, 1), 1257 SR_FGT(SYS_LORSA_EL1, HFGxTR, LORSA_EL1, 1), 1258 SR_FGT(SYS_LORN_EL1, HFGxTR, LORN_EL1, 1), 1259 SR_FGT(SYS_LORID_EL1, HFGxTR, LORID_EL1, 1), 1260 SR_FGT(SYS_LOREA_EL1, HFGxTR, LOREA_EL1, 1), 1261 SR_FGT(SYS_LORC_EL1, HFGxTR, LORC_EL1, 1), 1262 SR_FGT(SYS_ISR_EL1, HFGxTR, ISR_EL1, 1), 1263 SR_FGT(SYS_FAR_EL1, HFGxTR, FAR_EL1, 1), 1264 SR_FGT(SYS_ESR_EL1, HFGxTR, ESR_EL1, 1), 1265 SR_FGT(SYS_DCZID_EL0, HFGxTR, DCZID_EL0, 1), 1266 SR_FGT(SYS_CTR_EL0, HFGxTR, CTR_EL0, 1), 1267 SR_FGT(SYS_CSSELR_EL1, HFGxTR, CSSELR_EL1, 1), 1268 SR_FGT(SYS_CPACR_EL1, HFGxTR, CPACR_EL1, 1), 1269 SR_FGT(SYS_CONTEXTIDR_EL1, HFGxTR, CONTEXTIDR_EL1, 1), 1270 SR_FGT(SYS_CLIDR_EL1, HFGxTR, CLIDR_EL1, 1), 1271 SR_FGT(SYS_CCSIDR_EL1, HFGxTR, CCSIDR_EL1, 1), 1272 SR_FGT(SYS_APIBKEYLO_EL1, HFGxTR, APIBKey, 1), 1273 SR_FGT(SYS_APIBKEYHI_EL1, HFGxTR, APIBKey, 1), 1274 SR_FGT(SYS_APIAKEYLO_EL1, HFGxTR, APIAKey, 1), 1275 SR_FGT(SYS_APIAKEYHI_EL1, HFGxTR, APIAKey, 1), 1276 SR_FGT(SYS_APGAKEYLO_EL1, HFGxTR, APGAKey, 1), 1277 SR_FGT(SYS_APGAKEYHI_EL1, HFGxTR, APGAKey, 1), 1278 SR_FGT(SYS_APDBKEYLO_EL1, HFGxTR, APDBKey, 1), 1279 SR_FGT(SYS_APDBKEYHI_EL1, HFGxTR, APDBKey, 1), 1280 SR_FGT(SYS_APDAKEYLO_EL1, HFGxTR, APDAKey, 1), 1281 SR_FGT(SYS_APDAKEYHI_EL1, HFGxTR, APDAKey, 1), 1282 SR_FGT(SYS_AMAIR_EL1, HFGxTR, AMAIR_EL1, 1), 1283 SR_FGT(SYS_AIDR_EL1, HFGxTR, AIDR_EL1, 1), 1284 SR_FGT(SYS_AFSR1_EL1, HFGxTR, AFSR1_EL1, 1), 1285 SR_FGT(SYS_AFSR0_EL1, HFGxTR, AFSR0_EL1, 1), 1286 /* HFGITR_EL2 */ 1287 SR_FGT(OP_AT_S1E1A, HFGITR, ATS1E1A, 1), 1288 SR_FGT(OP_COSP_RCTX, HFGITR, COSPRCTX, 1), 1289 SR_FGT(OP_GCSPUSHX, HFGITR, nGCSEPP, 0), 1290 SR_FGT(OP_GCSPOPX, HFGITR, nGCSEPP, 0), 1291 SR_FGT(OP_GCSPUSHM, HFGITR, nGCSPUSHM_EL1, 0), 1292 SR_FGT(OP_BRB_IALL, HFGITR, nBRBIALL, 0), 1293 SR_FGT(OP_BRB_INJ, HFGITR, nBRBINJ, 0), 1294 SR_FGT(SYS_DC_CVAC, HFGITR, DCCVAC, 1), 1295 SR_FGT(SYS_DC_CGVAC, HFGITR, DCCVAC, 1), 1296 SR_FGT(SYS_DC_CGDVAC, HFGITR, DCCVAC, 1), 1297 SR_FGT(OP_CPP_RCTX, HFGITR, CPPRCTX, 1), 1298 SR_FGT(OP_DVP_RCTX, HFGITR, DVPRCTX, 1), 1299 SR_FGT(OP_CFP_RCTX, HFGITR, CFPRCTX, 1), 1300 SR_FGT(OP_TLBI_VAALE1, HFGITR, TLBIVAALE1, 1), 1301 SR_FGT(OP_TLBI_VALE1, HFGITR, TLBIVALE1, 1), 1302 SR_FGT(OP_TLBI_VAAE1, HFGITR, TLBIVAAE1, 1), 1303 SR_FGT(OP_TLBI_ASIDE1, HFGITR, TLBIASIDE1, 1), 1304 SR_FGT(OP_TLBI_VAE1, HFGITR, TLBIVAE1, 1), 1305 SR_FGT(OP_TLBI_VMALLE1, HFGITR, TLBIVMALLE1, 1), 1306 SR_FGT(OP_TLBI_RVAALE1, HFGITR, TLBIRVAALE1, 1), 1307 SR_FGT(OP_TLBI_RVALE1, HFGITR, TLBIRVALE1, 1), 1308 SR_FGT(OP_TLBI_RVAAE1, HFGITR, TLBIRVAAE1, 1), 1309 SR_FGT(OP_TLBI_RVAE1, HFGITR, TLBIRVAE1, 1), 1310 SR_FGT(OP_TLBI_RVAALE1IS, HFGITR, TLBIRVAALE1IS, 1), 1311 SR_FGT(OP_TLBI_RVALE1IS, HFGITR, TLBIRVALE1IS, 1), 1312 SR_FGT(OP_TLBI_RVAAE1IS, HFGITR, TLBIRVAAE1IS, 1), 1313 SR_FGT(OP_TLBI_RVAE1IS, HFGITR, TLBIRVAE1IS, 1), 1314 SR_FGT(OP_TLBI_VAALE1IS, HFGITR, TLBIVAALE1IS, 1), 1315 SR_FGT(OP_TLBI_VALE1IS, HFGITR, TLBIVALE1IS, 1), 1316 SR_FGT(OP_TLBI_VAAE1IS, HFGITR, TLBIVAAE1IS, 1), 1317 SR_FGT(OP_TLBI_ASIDE1IS, HFGITR, TLBIASIDE1IS, 1), 1318 SR_FGT(OP_TLBI_VAE1IS, HFGITR, TLBIVAE1IS, 1), 1319 SR_FGT(OP_TLBI_VMALLE1IS, HFGITR, TLBIVMALLE1IS, 1), 1320 SR_FGT(OP_TLBI_RVAALE1OS, HFGITR, TLBIRVAALE1OS, 1), 1321 SR_FGT(OP_TLBI_RVALE1OS, HFGITR, TLBIRVALE1OS, 1), 1322 SR_FGT(OP_TLBI_RVAAE1OS, HFGITR, TLBIRVAAE1OS, 1), 1323 SR_FGT(OP_TLBI_RVAE1OS, HFGITR, TLBIRVAE1OS, 1), 1324 SR_FGT(OP_TLBI_VAALE1OS, HFGITR, TLBIVAALE1OS, 1), 1325 SR_FGT(OP_TLBI_VALE1OS, HFGITR, TLBIVALE1OS, 1), 1326 SR_FGT(OP_TLBI_VAAE1OS, HFGITR, TLBIVAAE1OS, 1), 1327 SR_FGT(OP_TLBI_ASIDE1OS, HFGITR, TLBIASIDE1OS, 1), 1328 SR_FGT(OP_TLBI_VAE1OS, HFGITR, TLBIVAE1OS, 1), 1329 SR_FGT(OP_TLBI_VMALLE1OS, HFGITR, TLBIVMALLE1OS, 1), 1330 /* nXS variants must be checked against HCRX_EL2.FGTnXS */ 1331 SR_FGF(OP_TLBI_VAALE1NXS, HFGITR, TLBIVAALE1, 1, HCRX_FGTnXS), 1332 SR_FGF(OP_TLBI_VALE1NXS, HFGITR, TLBIVALE1, 1, HCRX_FGTnXS), 1333 SR_FGF(OP_TLBI_VAAE1NXS, HFGITR, TLBIVAAE1, 1, HCRX_FGTnXS), 1334 SR_FGF(OP_TLBI_ASIDE1NXS, HFGITR, TLBIASIDE1, 1, HCRX_FGTnXS), 1335 SR_FGF(OP_TLBI_VAE1NXS, HFGITR, TLBIVAE1, 1, HCRX_FGTnXS), 1336 SR_FGF(OP_TLBI_VMALLE1NXS, HFGITR, TLBIVMALLE1, 1, HCRX_FGTnXS), 1337 SR_FGF(OP_TLBI_RVAALE1NXS, HFGITR, TLBIRVAALE1, 1, HCRX_FGTnXS), 1338 SR_FGF(OP_TLBI_RVALE1NXS, HFGITR, TLBIRVALE1, 1, HCRX_FGTnXS), 1339 SR_FGF(OP_TLBI_RVAAE1NXS, HFGITR, TLBIRVAAE1, 1, HCRX_FGTnXS), 1340 SR_FGF(OP_TLBI_RVAE1NXS, HFGITR, TLBIRVAE1, 1, HCRX_FGTnXS), 1341 SR_FGF(OP_TLBI_RVAALE1ISNXS, HFGITR, TLBIRVAALE1IS, 1, HCRX_FGTnXS), 1342 SR_FGF(OP_TLBI_RVALE1ISNXS, HFGITR, TLBIRVALE1IS, 1, HCRX_FGTnXS), 1343 SR_FGF(OP_TLBI_RVAAE1ISNXS, HFGITR, TLBIRVAAE1IS, 1, HCRX_FGTnXS), 1344 SR_FGF(OP_TLBI_RVAE1ISNXS, HFGITR, TLBIRVAE1IS, 1, HCRX_FGTnXS), 1345 SR_FGF(OP_TLBI_VAALE1ISNXS, HFGITR, TLBIVAALE1IS, 1, HCRX_FGTnXS), 1346 SR_FGF(OP_TLBI_VALE1ISNXS, HFGITR, TLBIVALE1IS, 1, HCRX_FGTnXS), 1347 SR_FGF(OP_TLBI_VAAE1ISNXS, HFGITR, TLBIVAAE1IS, 1, HCRX_FGTnXS), 1348 SR_FGF(OP_TLBI_ASIDE1ISNXS, HFGITR, TLBIASIDE1IS, 1, HCRX_FGTnXS), 1349 SR_FGF(OP_TLBI_VAE1ISNXS, HFGITR, TLBIVAE1IS, 1, HCRX_FGTnXS), 1350 SR_FGF(OP_TLBI_VMALLE1ISNXS, HFGITR, TLBIVMALLE1IS, 1, HCRX_FGTnXS), 1351 SR_FGF(OP_TLBI_RVAALE1OSNXS, HFGITR, TLBIRVAALE1OS, 1, HCRX_FGTnXS), 1352 SR_FGF(OP_TLBI_RVALE1OSNXS, HFGITR, TLBIRVALE1OS, 1, HCRX_FGTnXS), 1353 SR_FGF(OP_TLBI_RVAAE1OSNXS, HFGITR, TLBIRVAAE1OS, 1, HCRX_FGTnXS), 1354 SR_FGF(OP_TLBI_RVAE1OSNXS, HFGITR, TLBIRVAE1OS, 1, HCRX_FGTnXS), 1355 SR_FGF(OP_TLBI_VAALE1OSNXS, HFGITR, TLBIVAALE1OS, 1, HCRX_FGTnXS), 1356 SR_FGF(OP_TLBI_VALE1OSNXS, HFGITR, TLBIVALE1OS, 1, HCRX_FGTnXS), 1357 SR_FGF(OP_TLBI_VAAE1OSNXS, HFGITR, TLBIVAAE1OS, 1, HCRX_FGTnXS), 1358 SR_FGF(OP_TLBI_ASIDE1OSNXS, HFGITR, TLBIASIDE1OS, 1, HCRX_FGTnXS), 1359 SR_FGF(OP_TLBI_VAE1OSNXS, HFGITR, TLBIVAE1OS, 1, HCRX_FGTnXS), 1360 SR_FGF(OP_TLBI_VMALLE1OSNXS, HFGITR, TLBIVMALLE1OS, 1, HCRX_FGTnXS), 1361 SR_FGT(OP_AT_S1E1WP, HFGITR, ATS1E1WP, 1), 1362 SR_FGT(OP_AT_S1E1RP, HFGITR, ATS1E1RP, 1), 1363 SR_FGT(OP_AT_S1E0W, HFGITR, ATS1E0W, 1), 1364 SR_FGT(OP_AT_S1E0R, HFGITR, ATS1E0R, 1), 1365 SR_FGT(OP_AT_S1E1W, HFGITR, ATS1E1W, 1), 1366 SR_FGT(OP_AT_S1E1R, HFGITR, ATS1E1R, 1), 1367 SR_FGT(SYS_DC_ZVA, HFGITR, DCZVA, 1), 1368 SR_FGT(SYS_DC_GVA, HFGITR, DCZVA, 1), 1369 SR_FGT(SYS_DC_GZVA, HFGITR, DCZVA, 1), 1370 SR_FGT(SYS_DC_CIVAC, HFGITR, DCCIVAC, 1), 1371 SR_FGT(SYS_DC_CIGVAC, HFGITR, DCCIVAC, 1), 1372 SR_FGT(SYS_DC_CIGDVAC, HFGITR, DCCIVAC, 1), 1373 SR_FGT(SYS_DC_CVADP, HFGITR, DCCVADP, 1), 1374 SR_FGT(SYS_DC_CGVADP, HFGITR, DCCVADP, 1), 1375 SR_FGT(SYS_DC_CGDVADP, HFGITR, DCCVADP, 1), 1376 SR_FGT(SYS_DC_CVAP, HFGITR, DCCVAP, 1), 1377 SR_FGT(SYS_DC_CGVAP, HFGITR, DCCVAP, 1), 1378 SR_FGT(SYS_DC_CGDVAP, HFGITR, DCCVAP, 1), 1379 SR_FGT(SYS_DC_CVAU, HFGITR, DCCVAU, 1), 1380 SR_FGT(SYS_DC_CISW, HFGITR, DCCISW, 1), 1381 SR_FGT(SYS_DC_CIGSW, HFGITR, DCCISW, 1), 1382 SR_FGT(SYS_DC_CIGDSW, HFGITR, DCCISW, 1), 1383 SR_FGT(SYS_DC_CSW, HFGITR, DCCSW, 1), 1384 SR_FGT(SYS_DC_CGSW, HFGITR, DCCSW, 1), 1385 SR_FGT(SYS_DC_CGDSW, HFGITR, DCCSW, 1), 1386 SR_FGT(SYS_DC_ISW, HFGITR, DCISW, 1), 1387 SR_FGT(SYS_DC_IGSW, HFGITR, DCISW, 1), 1388 SR_FGT(SYS_DC_IGDSW, HFGITR, DCISW, 1), 1389 SR_FGT(SYS_DC_IVAC, HFGITR, DCIVAC, 1), 1390 SR_FGT(SYS_DC_IGVAC, HFGITR, DCIVAC, 1), 1391 SR_FGT(SYS_DC_IGDVAC, HFGITR, DCIVAC, 1), 1392 SR_FGT(SYS_IC_IVAU, HFGITR, ICIVAU, 1), 1393 SR_FGT(SYS_IC_IALLU, HFGITR, ICIALLU, 1), 1394 SR_FGT(SYS_IC_IALLUIS, HFGITR, ICIALLUIS, 1), 1395 /* HDFGRTR_EL2 */ 1396 SR_FGT(SYS_PMBIDR_EL1, HDFGRTR, PMBIDR_EL1, 1), 1397 SR_FGT(SYS_PMSNEVFR_EL1, HDFGRTR, nPMSNEVFR_EL1, 0), 1398 SR_FGT(SYS_BRBINF_EL1(0), HDFGRTR, nBRBDATA, 0), 1399 SR_FGT(SYS_BRBINF_EL1(1), HDFGRTR, nBRBDATA, 0), 1400 SR_FGT(SYS_BRBINF_EL1(2), HDFGRTR, nBRBDATA, 0), 1401 SR_FGT(SYS_BRBINF_EL1(3), HDFGRTR, nBRBDATA, 0), 1402 SR_FGT(SYS_BRBINF_EL1(4), HDFGRTR, nBRBDATA, 0), 1403 SR_FGT(SYS_BRBINF_EL1(5), HDFGRTR, nBRBDATA, 0), 1404 SR_FGT(SYS_BRBINF_EL1(6), HDFGRTR, nBRBDATA, 0), 1405 SR_FGT(SYS_BRBINF_EL1(7), HDFGRTR, nBRBDATA, 0), 1406 SR_FGT(SYS_BRBINF_EL1(8), HDFGRTR, nBRBDATA, 0), 1407 SR_FGT(SYS_BRBINF_EL1(9), HDFGRTR, nBRBDATA, 0), 1408 SR_FGT(SYS_BRBINF_EL1(10), HDFGRTR, nBRBDATA, 0), 1409 SR_FGT(SYS_BRBINF_EL1(11), HDFGRTR, nBRBDATA, 0), 1410 SR_FGT(SYS_BRBINF_EL1(12), HDFGRTR, nBRBDATA, 0), 1411 SR_FGT(SYS_BRBINF_EL1(13), HDFGRTR, nBRBDATA, 0), 1412 SR_FGT(SYS_BRBINF_EL1(14), HDFGRTR, nBRBDATA, 0), 1413 SR_FGT(SYS_BRBINF_EL1(15), HDFGRTR, nBRBDATA, 0), 1414 SR_FGT(SYS_BRBINF_EL1(16), HDFGRTR, nBRBDATA, 0), 1415 SR_FGT(SYS_BRBINF_EL1(17), HDFGRTR, nBRBDATA, 0), 1416 SR_FGT(SYS_BRBINF_EL1(18), HDFGRTR, nBRBDATA, 0), 1417 SR_FGT(SYS_BRBINF_EL1(19), HDFGRTR, nBRBDATA, 0), 1418 SR_FGT(SYS_BRBINF_EL1(20), HDFGRTR, nBRBDATA, 0), 1419 SR_FGT(SYS_BRBINF_EL1(21), HDFGRTR, nBRBDATA, 0), 1420 SR_FGT(SYS_BRBINF_EL1(22), HDFGRTR, nBRBDATA, 0), 1421 SR_FGT(SYS_BRBINF_EL1(23), HDFGRTR, nBRBDATA, 0), 1422 SR_FGT(SYS_BRBINF_EL1(24), HDFGRTR, nBRBDATA, 0), 1423 SR_FGT(SYS_BRBINF_EL1(25), HDFGRTR, nBRBDATA, 0), 1424 SR_FGT(SYS_BRBINF_EL1(26), HDFGRTR, nBRBDATA, 0), 1425 SR_FGT(SYS_BRBINF_EL1(27), HDFGRTR, nBRBDATA, 0), 1426 SR_FGT(SYS_BRBINF_EL1(28), HDFGRTR, nBRBDATA, 0), 1427 SR_FGT(SYS_BRBINF_EL1(29), HDFGRTR, nBRBDATA, 0), 1428 SR_FGT(SYS_BRBINF_EL1(30), HDFGRTR, nBRBDATA, 0), 1429 SR_FGT(SYS_BRBINF_EL1(31), HDFGRTR, nBRBDATA, 0), 1430 SR_FGT(SYS_BRBINFINJ_EL1, HDFGRTR, nBRBDATA, 0), 1431 SR_FGT(SYS_BRBSRC_EL1(0), HDFGRTR, nBRBDATA, 0), 1432 SR_FGT(SYS_BRBSRC_EL1(1), HDFGRTR, nBRBDATA, 0), 1433 SR_FGT(SYS_BRBSRC_EL1(2), HDFGRTR, nBRBDATA, 0), 1434 SR_FGT(SYS_BRBSRC_EL1(3), HDFGRTR, nBRBDATA, 0), 1435 SR_FGT(SYS_BRBSRC_EL1(4), HDFGRTR, nBRBDATA, 0), 1436 SR_FGT(SYS_BRBSRC_EL1(5), HDFGRTR, nBRBDATA, 0), 1437 SR_FGT(SYS_BRBSRC_EL1(6), HDFGRTR, nBRBDATA, 0), 1438 SR_FGT(SYS_BRBSRC_EL1(7), HDFGRTR, nBRBDATA, 0), 1439 SR_FGT(SYS_BRBSRC_EL1(8), HDFGRTR, nBRBDATA, 0), 1440 SR_FGT(SYS_BRBSRC_EL1(9), HDFGRTR, nBRBDATA, 0), 1441 SR_FGT(SYS_BRBSRC_EL1(10), HDFGRTR, nBRBDATA, 0), 1442 SR_FGT(SYS_BRBSRC_EL1(11), HDFGRTR, nBRBDATA, 0), 1443 SR_FGT(SYS_BRBSRC_EL1(12), HDFGRTR, nBRBDATA, 0), 1444 SR_FGT(SYS_BRBSRC_EL1(13), HDFGRTR, nBRBDATA, 0), 1445 SR_FGT(SYS_BRBSRC_EL1(14), HDFGRTR, nBRBDATA, 0), 1446 SR_FGT(SYS_BRBSRC_EL1(15), HDFGRTR, nBRBDATA, 0), 1447 SR_FGT(SYS_BRBSRC_EL1(16), HDFGRTR, nBRBDATA, 0), 1448 SR_FGT(SYS_BRBSRC_EL1(17), HDFGRTR, nBRBDATA, 0), 1449 SR_FGT(SYS_BRBSRC_EL1(18), HDFGRTR, nBRBDATA, 0), 1450 SR_FGT(SYS_BRBSRC_EL1(19), HDFGRTR, nBRBDATA, 0), 1451 SR_FGT(SYS_BRBSRC_EL1(20), HDFGRTR, nBRBDATA, 0), 1452 SR_FGT(SYS_BRBSRC_EL1(21), HDFGRTR, nBRBDATA, 0), 1453 SR_FGT(SYS_BRBSRC_EL1(22), HDFGRTR, nBRBDATA, 0), 1454 SR_FGT(SYS_BRBSRC_EL1(23), HDFGRTR, nBRBDATA, 0), 1455 SR_FGT(SYS_BRBSRC_EL1(24), HDFGRTR, nBRBDATA, 0), 1456 SR_FGT(SYS_BRBSRC_EL1(25), HDFGRTR, nBRBDATA, 0), 1457 SR_FGT(SYS_BRBSRC_EL1(26), HDFGRTR, nBRBDATA, 0), 1458 SR_FGT(SYS_BRBSRC_EL1(27), HDFGRTR, nBRBDATA, 0), 1459 SR_FGT(SYS_BRBSRC_EL1(28), HDFGRTR, nBRBDATA, 0), 1460 SR_FGT(SYS_BRBSRC_EL1(29), HDFGRTR, nBRBDATA, 0), 1461 SR_FGT(SYS_BRBSRC_EL1(30), HDFGRTR, nBRBDATA, 0), 1462 SR_FGT(SYS_BRBSRC_EL1(31), HDFGRTR, nBRBDATA, 0), 1463 SR_FGT(SYS_BRBSRCINJ_EL1, HDFGRTR, nBRBDATA, 0), 1464 SR_FGT(SYS_BRBTGT_EL1(0), HDFGRTR, nBRBDATA, 0), 1465 SR_FGT(SYS_BRBTGT_EL1(1), HDFGRTR, nBRBDATA, 0), 1466 SR_FGT(SYS_BRBTGT_EL1(2), HDFGRTR, nBRBDATA, 0), 1467 SR_FGT(SYS_BRBTGT_EL1(3), HDFGRTR, nBRBDATA, 0), 1468 SR_FGT(SYS_BRBTGT_EL1(4), HDFGRTR, nBRBDATA, 0), 1469 SR_FGT(SYS_BRBTGT_EL1(5), HDFGRTR, nBRBDATA, 0), 1470 SR_FGT(SYS_BRBTGT_EL1(6), HDFGRTR, nBRBDATA, 0), 1471 SR_FGT(SYS_BRBTGT_EL1(7), HDFGRTR, nBRBDATA, 0), 1472 SR_FGT(SYS_BRBTGT_EL1(8), HDFGRTR, nBRBDATA, 0), 1473 SR_FGT(SYS_BRBTGT_EL1(9), HDFGRTR, nBRBDATA, 0), 1474 SR_FGT(SYS_BRBTGT_EL1(10), HDFGRTR, nBRBDATA, 0), 1475 SR_FGT(SYS_BRBTGT_EL1(11), HDFGRTR, nBRBDATA, 0), 1476 SR_FGT(SYS_BRBTGT_EL1(12), HDFGRTR, nBRBDATA, 0), 1477 SR_FGT(SYS_BRBTGT_EL1(13), HDFGRTR, nBRBDATA, 0), 1478 SR_FGT(SYS_BRBTGT_EL1(14), HDFGRTR, nBRBDATA, 0), 1479 SR_FGT(SYS_BRBTGT_EL1(15), HDFGRTR, nBRBDATA, 0), 1480 SR_FGT(SYS_BRBTGT_EL1(16), HDFGRTR, nBRBDATA, 0), 1481 SR_FGT(SYS_BRBTGT_EL1(17), HDFGRTR, nBRBDATA, 0), 1482 SR_FGT(SYS_BRBTGT_EL1(18), HDFGRTR, nBRBDATA, 0), 1483 SR_FGT(SYS_BRBTGT_EL1(19), HDFGRTR, nBRBDATA, 0), 1484 SR_FGT(SYS_BRBTGT_EL1(20), HDFGRTR, nBRBDATA, 0), 1485 SR_FGT(SYS_BRBTGT_EL1(21), HDFGRTR, nBRBDATA, 0), 1486 SR_FGT(SYS_BRBTGT_EL1(22), HDFGRTR, nBRBDATA, 0), 1487 SR_FGT(SYS_BRBTGT_EL1(23), HDFGRTR, nBRBDATA, 0), 1488 SR_FGT(SYS_BRBTGT_EL1(24), HDFGRTR, nBRBDATA, 0), 1489 SR_FGT(SYS_BRBTGT_EL1(25), HDFGRTR, nBRBDATA, 0), 1490 SR_FGT(SYS_BRBTGT_EL1(26), HDFGRTR, nBRBDATA, 0), 1491 SR_FGT(SYS_BRBTGT_EL1(27), HDFGRTR, nBRBDATA, 0), 1492 SR_FGT(SYS_BRBTGT_EL1(28), HDFGRTR, nBRBDATA, 0), 1493 SR_FGT(SYS_BRBTGT_EL1(29), HDFGRTR, nBRBDATA, 0), 1494 SR_FGT(SYS_BRBTGT_EL1(30), HDFGRTR, nBRBDATA, 0), 1495 SR_FGT(SYS_BRBTGT_EL1(31), HDFGRTR, nBRBDATA, 0), 1496 SR_FGT(SYS_BRBTGTINJ_EL1, HDFGRTR, nBRBDATA, 0), 1497 SR_FGT(SYS_BRBTS_EL1, HDFGRTR, nBRBDATA, 0), 1498 SR_FGT(SYS_BRBCR_EL1, HDFGRTR, nBRBCTL, 0), 1499 SR_FGT(SYS_BRBFCR_EL1, HDFGRTR, nBRBCTL, 0), 1500 SR_FGT(SYS_BRBIDR0_EL1, HDFGRTR, nBRBIDR, 0), 1501 SR_FGT(SYS_PMCEID0_EL0, HDFGRTR, PMCEIDn_EL0, 1), 1502 SR_FGT(SYS_PMCEID1_EL0, HDFGRTR, PMCEIDn_EL0, 1), 1503 SR_FGT(SYS_PMUSERENR_EL0, HDFGRTR, PMUSERENR_EL0, 1), 1504 SR_FGT(SYS_TRBTRG_EL1, HDFGRTR, TRBTRG_EL1, 1), 1505 SR_FGT(SYS_TRBSR_EL1, HDFGRTR, TRBSR_EL1, 1), 1506 SR_FGT(SYS_TRBPTR_EL1, HDFGRTR, TRBPTR_EL1, 1), 1507 SR_FGT(SYS_TRBMAR_EL1, HDFGRTR, TRBMAR_EL1, 1), 1508 SR_FGT(SYS_TRBLIMITR_EL1, HDFGRTR, TRBLIMITR_EL1, 1), 1509 SR_FGT(SYS_TRBIDR_EL1, HDFGRTR, TRBIDR_EL1, 1), 1510 SR_FGT(SYS_TRBBASER_EL1, HDFGRTR, TRBBASER_EL1, 1), 1511 SR_FGT(SYS_TRCVICTLR, HDFGRTR, TRCVICTLR, 1), 1512 SR_FGT(SYS_TRCSTATR, HDFGRTR, TRCSTATR, 1), 1513 SR_FGT(SYS_TRCSSCSR(0), HDFGRTR, TRCSSCSRn, 1), 1514 SR_FGT(SYS_TRCSSCSR(1), HDFGRTR, TRCSSCSRn, 1), 1515 SR_FGT(SYS_TRCSSCSR(2), HDFGRTR, TRCSSCSRn, 1), 1516 SR_FGT(SYS_TRCSSCSR(3), HDFGRTR, TRCSSCSRn, 1), 1517 SR_FGT(SYS_TRCSSCSR(4), HDFGRTR, TRCSSCSRn, 1), 1518 SR_FGT(SYS_TRCSSCSR(5), HDFGRTR, TRCSSCSRn, 1), 1519 SR_FGT(SYS_TRCSSCSR(6), HDFGRTR, TRCSSCSRn, 1), 1520 SR_FGT(SYS_TRCSSCSR(7), HDFGRTR, TRCSSCSRn, 1), 1521 SR_FGT(SYS_TRCSEQSTR, HDFGRTR, TRCSEQSTR, 1), 1522 SR_FGT(SYS_TRCPRGCTLR, HDFGRTR, TRCPRGCTLR, 1), 1523 SR_FGT(SYS_TRCOSLSR, HDFGRTR, TRCOSLSR, 1), 1524 SR_FGT(SYS_TRCIMSPEC(0), HDFGRTR, TRCIMSPECn, 1), 1525 SR_FGT(SYS_TRCIMSPEC(1), HDFGRTR, TRCIMSPECn, 1), 1526 SR_FGT(SYS_TRCIMSPEC(2), HDFGRTR, TRCIMSPECn, 1), 1527 SR_FGT(SYS_TRCIMSPEC(3), HDFGRTR, TRCIMSPECn, 1), 1528 SR_FGT(SYS_TRCIMSPEC(4), HDFGRTR, TRCIMSPECn, 1), 1529 SR_FGT(SYS_TRCIMSPEC(5), HDFGRTR, TRCIMSPECn, 1), 1530 SR_FGT(SYS_TRCIMSPEC(6), HDFGRTR, TRCIMSPECn, 1), 1531 SR_FGT(SYS_TRCIMSPEC(7), HDFGRTR, TRCIMSPECn, 1), 1532 SR_FGT(SYS_TRCDEVARCH, HDFGRTR, TRCID, 1), 1533 SR_FGT(SYS_TRCDEVID, HDFGRTR, TRCID, 1), 1534 SR_FGT(SYS_TRCIDR0, HDFGRTR, TRCID, 1), 1535 SR_FGT(SYS_TRCIDR1, HDFGRTR, TRCID, 1), 1536 SR_FGT(SYS_TRCIDR2, HDFGRTR, TRCID, 1), 1537 SR_FGT(SYS_TRCIDR3, HDFGRTR, TRCID, 1), 1538 SR_FGT(SYS_TRCIDR4, HDFGRTR, TRCID, 1), 1539 SR_FGT(SYS_TRCIDR5, HDFGRTR, TRCID, 1), 1540 SR_FGT(SYS_TRCIDR6, HDFGRTR, TRCID, 1), 1541 SR_FGT(SYS_TRCIDR7, HDFGRTR, TRCID, 1), 1542 SR_FGT(SYS_TRCIDR8, HDFGRTR, TRCID, 1), 1543 SR_FGT(SYS_TRCIDR9, HDFGRTR, TRCID, 1), 1544 SR_FGT(SYS_TRCIDR10, HDFGRTR, TRCID, 1), 1545 SR_FGT(SYS_TRCIDR11, HDFGRTR, TRCID, 1), 1546 SR_FGT(SYS_TRCIDR12, HDFGRTR, TRCID, 1), 1547 SR_FGT(SYS_TRCIDR13, HDFGRTR, TRCID, 1), 1548 SR_FGT(SYS_TRCCNTVR(0), HDFGRTR, TRCCNTVRn, 1), 1549 SR_FGT(SYS_TRCCNTVR(1), HDFGRTR, TRCCNTVRn, 1), 1550 SR_FGT(SYS_TRCCNTVR(2), HDFGRTR, TRCCNTVRn, 1), 1551 SR_FGT(SYS_TRCCNTVR(3), HDFGRTR, TRCCNTVRn, 1), 1552 SR_FGT(SYS_TRCCLAIMCLR, HDFGRTR, TRCCLAIM, 1), 1553 SR_FGT(SYS_TRCCLAIMSET, HDFGRTR, TRCCLAIM, 1), 1554 SR_FGT(SYS_TRCAUXCTLR, HDFGRTR, TRCAUXCTLR, 1), 1555 SR_FGT(SYS_TRCAUTHSTATUS, HDFGRTR, TRCAUTHSTATUS, 1), 1556 SR_FGT(SYS_TRCACATR(0), HDFGRTR, TRC, 1), 1557 SR_FGT(SYS_TRCACATR(1), HDFGRTR, TRC, 1), 1558 SR_FGT(SYS_TRCACATR(2), HDFGRTR, TRC, 1), 1559 SR_FGT(SYS_TRCACATR(3), HDFGRTR, TRC, 1), 1560 SR_FGT(SYS_TRCACATR(4), HDFGRTR, TRC, 1), 1561 SR_FGT(SYS_TRCACATR(5), HDFGRTR, TRC, 1), 1562 SR_FGT(SYS_TRCACATR(6), HDFGRTR, TRC, 1), 1563 SR_FGT(SYS_TRCACATR(7), HDFGRTR, TRC, 1), 1564 SR_FGT(SYS_TRCACATR(8), HDFGRTR, TRC, 1), 1565 SR_FGT(SYS_TRCACATR(9), HDFGRTR, TRC, 1), 1566 SR_FGT(SYS_TRCACATR(10), HDFGRTR, TRC, 1), 1567 SR_FGT(SYS_TRCACATR(11), HDFGRTR, TRC, 1), 1568 SR_FGT(SYS_TRCACATR(12), HDFGRTR, TRC, 1), 1569 SR_FGT(SYS_TRCACATR(13), HDFGRTR, TRC, 1), 1570 SR_FGT(SYS_TRCACATR(14), HDFGRTR, TRC, 1), 1571 SR_FGT(SYS_TRCACATR(15), HDFGRTR, TRC, 1), 1572 SR_FGT(SYS_TRCACVR(0), HDFGRTR, TRC, 1), 1573 SR_FGT(SYS_TRCACVR(1), HDFGRTR, TRC, 1), 1574 SR_FGT(SYS_TRCACVR(2), HDFGRTR, TRC, 1), 1575 SR_FGT(SYS_TRCACVR(3), HDFGRTR, TRC, 1), 1576 SR_FGT(SYS_TRCACVR(4), HDFGRTR, TRC, 1), 1577 SR_FGT(SYS_TRCACVR(5), HDFGRTR, TRC, 1), 1578 SR_FGT(SYS_TRCACVR(6), HDFGRTR, TRC, 1), 1579 SR_FGT(SYS_TRCACVR(7), HDFGRTR, TRC, 1), 1580 SR_FGT(SYS_TRCACVR(8), HDFGRTR, TRC, 1), 1581 SR_FGT(SYS_TRCACVR(9), HDFGRTR, TRC, 1), 1582 SR_FGT(SYS_TRCACVR(10), HDFGRTR, TRC, 1), 1583 SR_FGT(SYS_TRCACVR(11), HDFGRTR, TRC, 1), 1584 SR_FGT(SYS_TRCACVR(12), HDFGRTR, TRC, 1), 1585 SR_FGT(SYS_TRCACVR(13), HDFGRTR, TRC, 1), 1586 SR_FGT(SYS_TRCACVR(14), HDFGRTR, TRC, 1), 1587 SR_FGT(SYS_TRCACVR(15), HDFGRTR, TRC, 1), 1588 SR_FGT(SYS_TRCBBCTLR, HDFGRTR, TRC, 1), 1589 SR_FGT(SYS_TRCCCCTLR, HDFGRTR, TRC, 1), 1590 SR_FGT(SYS_TRCCIDCCTLR0, HDFGRTR, TRC, 1), 1591 SR_FGT(SYS_TRCCIDCCTLR1, HDFGRTR, TRC, 1), 1592 SR_FGT(SYS_TRCCIDCVR(0), HDFGRTR, TRC, 1), 1593 SR_FGT(SYS_TRCCIDCVR(1), HDFGRTR, TRC, 1), 1594 SR_FGT(SYS_TRCCIDCVR(2), HDFGRTR, TRC, 1), 1595 SR_FGT(SYS_TRCCIDCVR(3), HDFGRTR, TRC, 1), 1596 SR_FGT(SYS_TRCCIDCVR(4), HDFGRTR, TRC, 1), 1597 SR_FGT(SYS_TRCCIDCVR(5), HDFGRTR, TRC, 1), 1598 SR_FGT(SYS_TRCCIDCVR(6), HDFGRTR, TRC, 1), 1599 SR_FGT(SYS_TRCCIDCVR(7), HDFGRTR, TRC, 1), 1600 SR_FGT(SYS_TRCCNTCTLR(0), HDFGRTR, TRC, 1), 1601 SR_FGT(SYS_TRCCNTCTLR(1), HDFGRTR, TRC, 1), 1602 SR_FGT(SYS_TRCCNTCTLR(2), HDFGRTR, TRC, 1), 1603 SR_FGT(SYS_TRCCNTCTLR(3), HDFGRTR, TRC, 1), 1604 SR_FGT(SYS_TRCCNTRLDVR(0), HDFGRTR, TRC, 1), 1605 SR_FGT(SYS_TRCCNTRLDVR(1), HDFGRTR, TRC, 1), 1606 SR_FGT(SYS_TRCCNTRLDVR(2), HDFGRTR, TRC, 1), 1607 SR_FGT(SYS_TRCCNTRLDVR(3), HDFGRTR, TRC, 1), 1608 SR_FGT(SYS_TRCCONFIGR, HDFGRTR, TRC, 1), 1609 SR_FGT(SYS_TRCEVENTCTL0R, HDFGRTR, TRC, 1), 1610 SR_FGT(SYS_TRCEVENTCTL1R, HDFGRTR, TRC, 1), 1611 SR_FGT(SYS_TRCEXTINSELR(0), HDFGRTR, TRC, 1), 1612 SR_FGT(SYS_TRCEXTINSELR(1), HDFGRTR, TRC, 1), 1613 SR_FGT(SYS_TRCEXTINSELR(2), HDFGRTR, TRC, 1), 1614 SR_FGT(SYS_TRCEXTINSELR(3), HDFGRTR, TRC, 1), 1615 SR_FGT(SYS_TRCQCTLR, HDFGRTR, TRC, 1), 1616 SR_FGT(SYS_TRCRSCTLR(2), HDFGRTR, TRC, 1), 1617 SR_FGT(SYS_TRCRSCTLR(3), HDFGRTR, TRC, 1), 1618 SR_FGT(SYS_TRCRSCTLR(4), HDFGRTR, TRC, 1), 1619 SR_FGT(SYS_TRCRSCTLR(5), HDFGRTR, TRC, 1), 1620 SR_FGT(SYS_TRCRSCTLR(6), HDFGRTR, TRC, 1), 1621 SR_FGT(SYS_TRCRSCTLR(7), HDFGRTR, TRC, 1), 1622 SR_FGT(SYS_TRCRSCTLR(8), HDFGRTR, TRC, 1), 1623 SR_FGT(SYS_TRCRSCTLR(9), HDFGRTR, TRC, 1), 1624 SR_FGT(SYS_TRCRSCTLR(10), HDFGRTR, TRC, 1), 1625 SR_FGT(SYS_TRCRSCTLR(11), HDFGRTR, TRC, 1), 1626 SR_FGT(SYS_TRCRSCTLR(12), HDFGRTR, TRC, 1), 1627 SR_FGT(SYS_TRCRSCTLR(13), HDFGRTR, TRC, 1), 1628 SR_FGT(SYS_TRCRSCTLR(14), HDFGRTR, TRC, 1), 1629 SR_FGT(SYS_TRCRSCTLR(15), HDFGRTR, TRC, 1), 1630 SR_FGT(SYS_TRCRSCTLR(16), HDFGRTR, TRC, 1), 1631 SR_FGT(SYS_TRCRSCTLR(17), HDFGRTR, TRC, 1), 1632 SR_FGT(SYS_TRCRSCTLR(18), HDFGRTR, TRC, 1), 1633 SR_FGT(SYS_TRCRSCTLR(19), HDFGRTR, TRC, 1), 1634 SR_FGT(SYS_TRCRSCTLR(20), HDFGRTR, TRC, 1), 1635 SR_FGT(SYS_TRCRSCTLR(21), HDFGRTR, TRC, 1), 1636 SR_FGT(SYS_TRCRSCTLR(22), HDFGRTR, TRC, 1), 1637 SR_FGT(SYS_TRCRSCTLR(23), HDFGRTR, TRC, 1), 1638 SR_FGT(SYS_TRCRSCTLR(24), HDFGRTR, TRC, 1), 1639 SR_FGT(SYS_TRCRSCTLR(25), HDFGRTR, TRC, 1), 1640 SR_FGT(SYS_TRCRSCTLR(26), HDFGRTR, TRC, 1), 1641 SR_FGT(SYS_TRCRSCTLR(27), HDFGRTR, TRC, 1), 1642 SR_FGT(SYS_TRCRSCTLR(28), HDFGRTR, TRC, 1), 1643 SR_FGT(SYS_TRCRSCTLR(29), HDFGRTR, TRC, 1), 1644 SR_FGT(SYS_TRCRSCTLR(30), HDFGRTR, TRC, 1), 1645 SR_FGT(SYS_TRCRSCTLR(31), HDFGRTR, TRC, 1), 1646 SR_FGT(SYS_TRCRSR, HDFGRTR, TRC, 1), 1647 SR_FGT(SYS_TRCSEQEVR(0), HDFGRTR, TRC, 1), 1648 SR_FGT(SYS_TRCSEQEVR(1), HDFGRTR, TRC, 1), 1649 SR_FGT(SYS_TRCSEQEVR(2), HDFGRTR, TRC, 1), 1650 SR_FGT(SYS_TRCSEQRSTEVR, HDFGRTR, TRC, 1), 1651 SR_FGT(SYS_TRCSSCCR(0), HDFGRTR, TRC, 1), 1652 SR_FGT(SYS_TRCSSCCR(1), HDFGRTR, TRC, 1), 1653 SR_FGT(SYS_TRCSSCCR(2), HDFGRTR, TRC, 1), 1654 SR_FGT(SYS_TRCSSCCR(3), HDFGRTR, TRC, 1), 1655 SR_FGT(SYS_TRCSSCCR(4), HDFGRTR, TRC, 1), 1656 SR_FGT(SYS_TRCSSCCR(5), HDFGRTR, TRC, 1), 1657 SR_FGT(SYS_TRCSSCCR(6), HDFGRTR, TRC, 1), 1658 SR_FGT(SYS_TRCSSCCR(7), HDFGRTR, TRC, 1), 1659 SR_FGT(SYS_TRCSSPCICR(0), HDFGRTR, TRC, 1), 1660 SR_FGT(SYS_TRCSSPCICR(1), HDFGRTR, TRC, 1), 1661 SR_FGT(SYS_TRCSSPCICR(2), HDFGRTR, TRC, 1), 1662 SR_FGT(SYS_TRCSSPCICR(3), HDFGRTR, TRC, 1), 1663 SR_FGT(SYS_TRCSSPCICR(4), HDFGRTR, TRC, 1), 1664 SR_FGT(SYS_TRCSSPCICR(5), HDFGRTR, TRC, 1), 1665 SR_FGT(SYS_TRCSSPCICR(6), HDFGRTR, TRC, 1), 1666 SR_FGT(SYS_TRCSSPCICR(7), HDFGRTR, TRC, 1), 1667 SR_FGT(SYS_TRCSTALLCTLR, HDFGRTR, TRC, 1), 1668 SR_FGT(SYS_TRCSYNCPR, HDFGRTR, TRC, 1), 1669 SR_FGT(SYS_TRCTRACEIDR, HDFGRTR, TRC, 1), 1670 SR_FGT(SYS_TRCTSCTLR, HDFGRTR, TRC, 1), 1671 SR_FGT(SYS_TRCVIIECTLR, HDFGRTR, TRC, 1), 1672 SR_FGT(SYS_TRCVIPCSSCTLR, HDFGRTR, TRC, 1), 1673 SR_FGT(SYS_TRCVISSCTLR, HDFGRTR, TRC, 1), 1674 SR_FGT(SYS_TRCVMIDCCTLR0, HDFGRTR, TRC, 1), 1675 SR_FGT(SYS_TRCVMIDCCTLR1, HDFGRTR, TRC, 1), 1676 SR_FGT(SYS_TRCVMIDCVR(0), HDFGRTR, TRC, 1), 1677 SR_FGT(SYS_TRCVMIDCVR(1), HDFGRTR, TRC, 1), 1678 SR_FGT(SYS_TRCVMIDCVR(2), HDFGRTR, TRC, 1), 1679 SR_FGT(SYS_TRCVMIDCVR(3), HDFGRTR, TRC, 1), 1680 SR_FGT(SYS_TRCVMIDCVR(4), HDFGRTR, TRC, 1), 1681 SR_FGT(SYS_TRCVMIDCVR(5), HDFGRTR, TRC, 1), 1682 SR_FGT(SYS_TRCVMIDCVR(6), HDFGRTR, TRC, 1), 1683 SR_FGT(SYS_TRCVMIDCVR(7), HDFGRTR, TRC, 1), 1684 SR_FGT(SYS_PMSLATFR_EL1, HDFGRTR, PMSLATFR_EL1, 1), 1685 SR_FGT(SYS_PMSIRR_EL1, HDFGRTR, PMSIRR_EL1, 1), 1686 SR_FGT(SYS_PMSIDR_EL1, HDFGRTR, PMSIDR_EL1, 1), 1687 SR_FGT(SYS_PMSICR_EL1, HDFGRTR, PMSICR_EL1, 1), 1688 SR_FGT(SYS_PMSFCR_EL1, HDFGRTR, PMSFCR_EL1, 1), 1689 SR_FGT(SYS_PMSEVFR_EL1, HDFGRTR, PMSEVFR_EL1, 1), 1690 SR_FGT(SYS_PMSCR_EL1, HDFGRTR, PMSCR_EL1, 1), 1691 SR_FGT(SYS_PMBSR_EL1, HDFGRTR, PMBSR_EL1, 1), 1692 SR_FGT(SYS_PMBPTR_EL1, HDFGRTR, PMBPTR_EL1, 1), 1693 SR_FGT(SYS_PMBLIMITR_EL1, HDFGRTR, PMBLIMITR_EL1, 1), 1694 SR_FGT(SYS_PMMIR_EL1, HDFGRTR, PMMIR_EL1, 1), 1695 SR_FGT(SYS_PMSELR_EL0, HDFGRTR, PMSELR_EL0, 1), 1696 SR_FGT(SYS_PMOVSCLR_EL0, HDFGRTR, PMOVS, 1), 1697 SR_FGT(SYS_PMOVSSET_EL0, HDFGRTR, PMOVS, 1), 1698 SR_FGT(SYS_PMINTENCLR_EL1, HDFGRTR, PMINTEN, 1), 1699 SR_FGT(SYS_PMINTENSET_EL1, HDFGRTR, PMINTEN, 1), 1700 SR_FGT(SYS_PMCNTENCLR_EL0, HDFGRTR, PMCNTEN, 1), 1701 SR_FGT(SYS_PMCNTENSET_EL0, HDFGRTR, PMCNTEN, 1), 1702 SR_FGT(SYS_PMCCNTR_EL0, HDFGRTR, PMCCNTR_EL0, 1), 1703 SR_FGT(SYS_PMCCFILTR_EL0, HDFGRTR, PMCCFILTR_EL0, 1), 1704 SR_FGT(SYS_PMEVTYPERn_EL0(0), HDFGRTR, PMEVTYPERn_EL0, 1), 1705 SR_FGT(SYS_PMEVTYPERn_EL0(1), HDFGRTR, PMEVTYPERn_EL0, 1), 1706 SR_FGT(SYS_PMEVTYPERn_EL0(2), HDFGRTR, PMEVTYPERn_EL0, 1), 1707 SR_FGT(SYS_PMEVTYPERn_EL0(3), HDFGRTR, PMEVTYPERn_EL0, 1), 1708 SR_FGT(SYS_PMEVTYPERn_EL0(4), HDFGRTR, PMEVTYPERn_EL0, 1), 1709 SR_FGT(SYS_PMEVTYPERn_EL0(5), HDFGRTR, PMEVTYPERn_EL0, 1), 1710 SR_FGT(SYS_PMEVTYPERn_EL0(6), HDFGRTR, PMEVTYPERn_EL0, 1), 1711 SR_FGT(SYS_PMEVTYPERn_EL0(7), HDFGRTR, PMEVTYPERn_EL0, 1), 1712 SR_FGT(SYS_PMEVTYPERn_EL0(8), HDFGRTR, PMEVTYPERn_EL0, 1), 1713 SR_FGT(SYS_PMEVTYPERn_EL0(9), HDFGRTR, PMEVTYPERn_EL0, 1), 1714 SR_FGT(SYS_PMEVTYPERn_EL0(10), HDFGRTR, PMEVTYPERn_EL0, 1), 1715 SR_FGT(SYS_PMEVTYPERn_EL0(11), HDFGRTR, PMEVTYPERn_EL0, 1), 1716 SR_FGT(SYS_PMEVTYPERn_EL0(12), HDFGRTR, PMEVTYPERn_EL0, 1), 1717 SR_FGT(SYS_PMEVTYPERn_EL0(13), HDFGRTR, PMEVTYPERn_EL0, 1), 1718 SR_FGT(SYS_PMEVTYPERn_EL0(14), HDFGRTR, PMEVTYPERn_EL0, 1), 1719 SR_FGT(SYS_PMEVTYPERn_EL0(15), HDFGRTR, PMEVTYPERn_EL0, 1), 1720 SR_FGT(SYS_PMEVTYPERn_EL0(16), HDFGRTR, PMEVTYPERn_EL0, 1), 1721 SR_FGT(SYS_PMEVTYPERn_EL0(17), HDFGRTR, PMEVTYPERn_EL0, 1), 1722 SR_FGT(SYS_PMEVTYPERn_EL0(18), HDFGRTR, PMEVTYPERn_EL0, 1), 1723 SR_FGT(SYS_PMEVTYPERn_EL0(19), HDFGRTR, PMEVTYPERn_EL0, 1), 1724 SR_FGT(SYS_PMEVTYPERn_EL0(20), HDFGRTR, PMEVTYPERn_EL0, 1), 1725 SR_FGT(SYS_PMEVTYPERn_EL0(21), HDFGRTR, PMEVTYPERn_EL0, 1), 1726 SR_FGT(SYS_PMEVTYPERn_EL0(22), HDFGRTR, PMEVTYPERn_EL0, 1), 1727 SR_FGT(SYS_PMEVTYPERn_EL0(23), HDFGRTR, PMEVTYPERn_EL0, 1), 1728 SR_FGT(SYS_PMEVTYPERn_EL0(24), HDFGRTR, PMEVTYPERn_EL0, 1), 1729 SR_FGT(SYS_PMEVTYPERn_EL0(25), HDFGRTR, PMEVTYPERn_EL0, 1), 1730 SR_FGT(SYS_PMEVTYPERn_EL0(26), HDFGRTR, PMEVTYPERn_EL0, 1), 1731 SR_FGT(SYS_PMEVTYPERn_EL0(27), HDFGRTR, PMEVTYPERn_EL0, 1), 1732 SR_FGT(SYS_PMEVTYPERn_EL0(28), HDFGRTR, PMEVTYPERn_EL0, 1), 1733 SR_FGT(SYS_PMEVTYPERn_EL0(29), HDFGRTR, PMEVTYPERn_EL0, 1), 1734 SR_FGT(SYS_PMEVTYPERn_EL0(30), HDFGRTR, PMEVTYPERn_EL0, 1), 1735 SR_FGT(SYS_PMEVCNTRn_EL0(0), HDFGRTR, PMEVCNTRn_EL0, 1), 1736 SR_FGT(SYS_PMEVCNTRn_EL0(1), HDFGRTR, PMEVCNTRn_EL0, 1), 1737 SR_FGT(SYS_PMEVCNTRn_EL0(2), HDFGRTR, PMEVCNTRn_EL0, 1), 1738 SR_FGT(SYS_PMEVCNTRn_EL0(3), HDFGRTR, PMEVCNTRn_EL0, 1), 1739 SR_FGT(SYS_PMEVCNTRn_EL0(4), HDFGRTR, PMEVCNTRn_EL0, 1), 1740 SR_FGT(SYS_PMEVCNTRn_EL0(5), HDFGRTR, PMEVCNTRn_EL0, 1), 1741 SR_FGT(SYS_PMEVCNTRn_EL0(6), HDFGRTR, PMEVCNTRn_EL0, 1), 1742 SR_FGT(SYS_PMEVCNTRn_EL0(7), HDFGRTR, PMEVCNTRn_EL0, 1), 1743 SR_FGT(SYS_PMEVCNTRn_EL0(8), HDFGRTR, PMEVCNTRn_EL0, 1), 1744 SR_FGT(SYS_PMEVCNTRn_EL0(9), HDFGRTR, PMEVCNTRn_EL0, 1), 1745 SR_FGT(SYS_PMEVCNTRn_EL0(10), HDFGRTR, PMEVCNTRn_EL0, 1), 1746 SR_FGT(SYS_PMEVCNTRn_EL0(11), HDFGRTR, PMEVCNTRn_EL0, 1), 1747 SR_FGT(SYS_PMEVCNTRn_EL0(12), HDFGRTR, PMEVCNTRn_EL0, 1), 1748 SR_FGT(SYS_PMEVCNTRn_EL0(13), HDFGRTR, PMEVCNTRn_EL0, 1), 1749 SR_FGT(SYS_PMEVCNTRn_EL0(14), HDFGRTR, PMEVCNTRn_EL0, 1), 1750 SR_FGT(SYS_PMEVCNTRn_EL0(15), HDFGRTR, PMEVCNTRn_EL0, 1), 1751 SR_FGT(SYS_PMEVCNTRn_EL0(16), HDFGRTR, PMEVCNTRn_EL0, 1), 1752 SR_FGT(SYS_PMEVCNTRn_EL0(17), HDFGRTR, PMEVCNTRn_EL0, 1), 1753 SR_FGT(SYS_PMEVCNTRn_EL0(18), HDFGRTR, PMEVCNTRn_EL0, 1), 1754 SR_FGT(SYS_PMEVCNTRn_EL0(19), HDFGRTR, PMEVCNTRn_EL0, 1), 1755 SR_FGT(SYS_PMEVCNTRn_EL0(20), HDFGRTR, PMEVCNTRn_EL0, 1), 1756 SR_FGT(SYS_PMEVCNTRn_EL0(21), HDFGRTR, PMEVCNTRn_EL0, 1), 1757 SR_FGT(SYS_PMEVCNTRn_EL0(22), HDFGRTR, PMEVCNTRn_EL0, 1), 1758 SR_FGT(SYS_PMEVCNTRn_EL0(23), HDFGRTR, PMEVCNTRn_EL0, 1), 1759 SR_FGT(SYS_PMEVCNTRn_EL0(24), HDFGRTR, PMEVCNTRn_EL0, 1), 1760 SR_FGT(SYS_PMEVCNTRn_EL0(25), HDFGRTR, PMEVCNTRn_EL0, 1), 1761 SR_FGT(SYS_PMEVCNTRn_EL0(26), HDFGRTR, PMEVCNTRn_EL0, 1), 1762 SR_FGT(SYS_PMEVCNTRn_EL0(27), HDFGRTR, PMEVCNTRn_EL0, 1), 1763 SR_FGT(SYS_PMEVCNTRn_EL0(28), HDFGRTR, PMEVCNTRn_EL0, 1), 1764 SR_FGT(SYS_PMEVCNTRn_EL0(29), HDFGRTR, PMEVCNTRn_EL0, 1), 1765 SR_FGT(SYS_PMEVCNTRn_EL0(30), HDFGRTR, PMEVCNTRn_EL0, 1), 1766 SR_FGT(SYS_OSDLR_EL1, HDFGRTR, OSDLR_EL1, 1), 1767 SR_FGT(SYS_OSECCR_EL1, HDFGRTR, OSECCR_EL1, 1), 1768 SR_FGT(SYS_OSLSR_EL1, HDFGRTR, OSLSR_EL1, 1), 1769 SR_FGT(SYS_DBGPRCR_EL1, HDFGRTR, DBGPRCR_EL1, 1), 1770 SR_FGT(SYS_DBGAUTHSTATUS_EL1, HDFGRTR, DBGAUTHSTATUS_EL1, 1), 1771 SR_FGT(SYS_DBGCLAIMSET_EL1, HDFGRTR, DBGCLAIM, 1), 1772 SR_FGT(SYS_DBGCLAIMCLR_EL1, HDFGRTR, DBGCLAIM, 1), 1773 SR_FGT(SYS_MDSCR_EL1, HDFGRTR, MDSCR_EL1, 1), 1774 /* 1775 * The trap bits capture *64* debug registers per bit, but the 1776 * ARM ARM only describes the encoding for the first 16, and 1777 * we don't really support more than that anyway. 1778 */ 1779 SR_FGT(SYS_DBGWVRn_EL1(0), HDFGRTR, DBGWVRn_EL1, 1), 1780 SR_FGT(SYS_DBGWVRn_EL1(1), HDFGRTR, DBGWVRn_EL1, 1), 1781 SR_FGT(SYS_DBGWVRn_EL1(2), HDFGRTR, DBGWVRn_EL1, 1), 1782 SR_FGT(SYS_DBGWVRn_EL1(3), HDFGRTR, DBGWVRn_EL1, 1), 1783 SR_FGT(SYS_DBGWVRn_EL1(4), HDFGRTR, DBGWVRn_EL1, 1), 1784 SR_FGT(SYS_DBGWVRn_EL1(5), HDFGRTR, DBGWVRn_EL1, 1), 1785 SR_FGT(SYS_DBGWVRn_EL1(6), HDFGRTR, DBGWVRn_EL1, 1), 1786 SR_FGT(SYS_DBGWVRn_EL1(7), HDFGRTR, DBGWVRn_EL1, 1), 1787 SR_FGT(SYS_DBGWVRn_EL1(8), HDFGRTR, DBGWVRn_EL1, 1), 1788 SR_FGT(SYS_DBGWVRn_EL1(9), HDFGRTR, DBGWVRn_EL1, 1), 1789 SR_FGT(SYS_DBGWVRn_EL1(10), HDFGRTR, DBGWVRn_EL1, 1), 1790 SR_FGT(SYS_DBGWVRn_EL1(11), HDFGRTR, DBGWVRn_EL1, 1), 1791 SR_FGT(SYS_DBGWVRn_EL1(12), HDFGRTR, DBGWVRn_EL1, 1), 1792 SR_FGT(SYS_DBGWVRn_EL1(13), HDFGRTR, DBGWVRn_EL1, 1), 1793 SR_FGT(SYS_DBGWVRn_EL1(14), HDFGRTR, DBGWVRn_EL1, 1), 1794 SR_FGT(SYS_DBGWVRn_EL1(15), HDFGRTR, DBGWVRn_EL1, 1), 1795 SR_FGT(SYS_DBGWCRn_EL1(0), HDFGRTR, DBGWCRn_EL1, 1), 1796 SR_FGT(SYS_DBGWCRn_EL1(1), HDFGRTR, DBGWCRn_EL1, 1), 1797 SR_FGT(SYS_DBGWCRn_EL1(2), HDFGRTR, DBGWCRn_EL1, 1), 1798 SR_FGT(SYS_DBGWCRn_EL1(3), HDFGRTR, DBGWCRn_EL1, 1), 1799 SR_FGT(SYS_DBGWCRn_EL1(4), HDFGRTR, DBGWCRn_EL1, 1), 1800 SR_FGT(SYS_DBGWCRn_EL1(5), HDFGRTR, DBGWCRn_EL1, 1), 1801 SR_FGT(SYS_DBGWCRn_EL1(6), HDFGRTR, DBGWCRn_EL1, 1), 1802 SR_FGT(SYS_DBGWCRn_EL1(7), HDFGRTR, DBGWCRn_EL1, 1), 1803 SR_FGT(SYS_DBGWCRn_EL1(8), HDFGRTR, DBGWCRn_EL1, 1), 1804 SR_FGT(SYS_DBGWCRn_EL1(9), HDFGRTR, DBGWCRn_EL1, 1), 1805 SR_FGT(SYS_DBGWCRn_EL1(10), HDFGRTR, DBGWCRn_EL1, 1), 1806 SR_FGT(SYS_DBGWCRn_EL1(11), HDFGRTR, DBGWCRn_EL1, 1), 1807 SR_FGT(SYS_DBGWCRn_EL1(12), HDFGRTR, DBGWCRn_EL1, 1), 1808 SR_FGT(SYS_DBGWCRn_EL1(13), HDFGRTR, DBGWCRn_EL1, 1), 1809 SR_FGT(SYS_DBGWCRn_EL1(14), HDFGRTR, DBGWCRn_EL1, 1), 1810 SR_FGT(SYS_DBGWCRn_EL1(15), HDFGRTR, DBGWCRn_EL1, 1), 1811 SR_FGT(SYS_DBGBVRn_EL1(0), HDFGRTR, DBGBVRn_EL1, 1), 1812 SR_FGT(SYS_DBGBVRn_EL1(1), HDFGRTR, DBGBVRn_EL1, 1), 1813 SR_FGT(SYS_DBGBVRn_EL1(2), HDFGRTR, DBGBVRn_EL1, 1), 1814 SR_FGT(SYS_DBGBVRn_EL1(3), HDFGRTR, DBGBVRn_EL1, 1), 1815 SR_FGT(SYS_DBGBVRn_EL1(4), HDFGRTR, DBGBVRn_EL1, 1), 1816 SR_FGT(SYS_DBGBVRn_EL1(5), HDFGRTR, DBGBVRn_EL1, 1), 1817 SR_FGT(SYS_DBGBVRn_EL1(6), HDFGRTR, DBGBVRn_EL1, 1), 1818 SR_FGT(SYS_DBGBVRn_EL1(7), HDFGRTR, DBGBVRn_EL1, 1), 1819 SR_FGT(SYS_DBGBVRn_EL1(8), HDFGRTR, DBGBVRn_EL1, 1), 1820 SR_FGT(SYS_DBGBVRn_EL1(9), HDFGRTR, DBGBVRn_EL1, 1), 1821 SR_FGT(SYS_DBGBVRn_EL1(10), HDFGRTR, DBGBVRn_EL1, 1), 1822 SR_FGT(SYS_DBGBVRn_EL1(11), HDFGRTR, DBGBVRn_EL1, 1), 1823 SR_FGT(SYS_DBGBVRn_EL1(12), HDFGRTR, DBGBVRn_EL1, 1), 1824 SR_FGT(SYS_DBGBVRn_EL1(13), HDFGRTR, DBGBVRn_EL1, 1), 1825 SR_FGT(SYS_DBGBVRn_EL1(14), HDFGRTR, DBGBVRn_EL1, 1), 1826 SR_FGT(SYS_DBGBVRn_EL1(15), HDFGRTR, DBGBVRn_EL1, 1), 1827 SR_FGT(SYS_DBGBCRn_EL1(0), HDFGRTR, DBGBCRn_EL1, 1), 1828 SR_FGT(SYS_DBGBCRn_EL1(1), HDFGRTR, DBGBCRn_EL1, 1), 1829 SR_FGT(SYS_DBGBCRn_EL1(2), HDFGRTR, DBGBCRn_EL1, 1), 1830 SR_FGT(SYS_DBGBCRn_EL1(3), HDFGRTR, DBGBCRn_EL1, 1), 1831 SR_FGT(SYS_DBGBCRn_EL1(4), HDFGRTR, DBGBCRn_EL1, 1), 1832 SR_FGT(SYS_DBGBCRn_EL1(5), HDFGRTR, DBGBCRn_EL1, 1), 1833 SR_FGT(SYS_DBGBCRn_EL1(6), HDFGRTR, DBGBCRn_EL1, 1), 1834 SR_FGT(SYS_DBGBCRn_EL1(7), HDFGRTR, DBGBCRn_EL1, 1), 1835 SR_FGT(SYS_DBGBCRn_EL1(8), HDFGRTR, DBGBCRn_EL1, 1), 1836 SR_FGT(SYS_DBGBCRn_EL1(9), HDFGRTR, DBGBCRn_EL1, 1), 1837 SR_FGT(SYS_DBGBCRn_EL1(10), HDFGRTR, DBGBCRn_EL1, 1), 1838 SR_FGT(SYS_DBGBCRn_EL1(11), HDFGRTR, DBGBCRn_EL1, 1), 1839 SR_FGT(SYS_DBGBCRn_EL1(12), HDFGRTR, DBGBCRn_EL1, 1), 1840 SR_FGT(SYS_DBGBCRn_EL1(13), HDFGRTR, DBGBCRn_EL1, 1), 1841 SR_FGT(SYS_DBGBCRn_EL1(14), HDFGRTR, DBGBCRn_EL1, 1), 1842 SR_FGT(SYS_DBGBCRn_EL1(15), HDFGRTR, DBGBCRn_EL1, 1), 1843 /* 1844 * HDFGWTR_EL2 1845 * 1846 * Although HDFGRTR_EL2 and HDFGWTR_EL2 registers largely 1847 * overlap in their bit assignment, there are a number of bits 1848 * that are RES0 on one side, and an actual trap bit on the 1849 * other. The policy chosen here is to describe all the 1850 * read-side mappings, and only the write-side mappings that 1851 * differ from the read side, and the trap handler will pick 1852 * the correct shadow register based on the access type. 1853 */ 1854 SR_FGT(SYS_TRFCR_EL1, HDFGWTR, TRFCR_EL1, 1), 1855 SR_FGT(SYS_TRCOSLAR, HDFGWTR, TRCOSLAR, 1), 1856 SR_FGT(SYS_PMCR_EL0, HDFGWTR, PMCR_EL0, 1), 1857 SR_FGT(SYS_PMSWINC_EL0, HDFGWTR, PMSWINC_EL0, 1), 1858 SR_FGT(SYS_OSLAR_EL1, HDFGWTR, OSLAR_EL1, 1), 1859 /* 1860 * HAFGRTR_EL2 1861 */ 1862 SR_FGT(SYS_AMEVTYPER1_EL0(15), HAFGRTR, AMEVTYPER115_EL0, 1), 1863 SR_FGT(SYS_AMEVTYPER1_EL0(14), HAFGRTR, AMEVTYPER114_EL0, 1), 1864 SR_FGT(SYS_AMEVTYPER1_EL0(13), HAFGRTR, AMEVTYPER113_EL0, 1), 1865 SR_FGT(SYS_AMEVTYPER1_EL0(12), HAFGRTR, AMEVTYPER112_EL0, 1), 1866 SR_FGT(SYS_AMEVTYPER1_EL0(11), HAFGRTR, AMEVTYPER111_EL0, 1), 1867 SR_FGT(SYS_AMEVTYPER1_EL0(10), HAFGRTR, AMEVTYPER110_EL0, 1), 1868 SR_FGT(SYS_AMEVTYPER1_EL0(9), HAFGRTR, AMEVTYPER19_EL0, 1), 1869 SR_FGT(SYS_AMEVTYPER1_EL0(8), HAFGRTR, AMEVTYPER18_EL0, 1), 1870 SR_FGT(SYS_AMEVTYPER1_EL0(7), HAFGRTR, AMEVTYPER17_EL0, 1), 1871 SR_FGT(SYS_AMEVTYPER1_EL0(6), HAFGRTR, AMEVTYPER16_EL0, 1), 1872 SR_FGT(SYS_AMEVTYPER1_EL0(5), HAFGRTR, AMEVTYPER15_EL0, 1), 1873 SR_FGT(SYS_AMEVTYPER1_EL0(4), HAFGRTR, AMEVTYPER14_EL0, 1), 1874 SR_FGT(SYS_AMEVTYPER1_EL0(3), HAFGRTR, AMEVTYPER13_EL0, 1), 1875 SR_FGT(SYS_AMEVTYPER1_EL0(2), HAFGRTR, AMEVTYPER12_EL0, 1), 1876 SR_FGT(SYS_AMEVTYPER1_EL0(1), HAFGRTR, AMEVTYPER11_EL0, 1), 1877 SR_FGT(SYS_AMEVTYPER1_EL0(0), HAFGRTR, AMEVTYPER10_EL0, 1), 1878 SR_FGT(SYS_AMEVCNTR1_EL0(15), HAFGRTR, AMEVCNTR115_EL0, 1), 1879 SR_FGT(SYS_AMEVCNTR1_EL0(14), HAFGRTR, AMEVCNTR114_EL0, 1), 1880 SR_FGT(SYS_AMEVCNTR1_EL0(13), HAFGRTR, AMEVCNTR113_EL0, 1), 1881 SR_FGT(SYS_AMEVCNTR1_EL0(12), HAFGRTR, AMEVCNTR112_EL0, 1), 1882 SR_FGT(SYS_AMEVCNTR1_EL0(11), HAFGRTR, AMEVCNTR111_EL0, 1), 1883 SR_FGT(SYS_AMEVCNTR1_EL0(10), HAFGRTR, AMEVCNTR110_EL0, 1), 1884 SR_FGT(SYS_AMEVCNTR1_EL0(9), HAFGRTR, AMEVCNTR19_EL0, 1), 1885 SR_FGT(SYS_AMEVCNTR1_EL0(8), HAFGRTR, AMEVCNTR18_EL0, 1), 1886 SR_FGT(SYS_AMEVCNTR1_EL0(7), HAFGRTR, AMEVCNTR17_EL0, 1), 1887 SR_FGT(SYS_AMEVCNTR1_EL0(6), HAFGRTR, AMEVCNTR16_EL0, 1), 1888 SR_FGT(SYS_AMEVCNTR1_EL0(5), HAFGRTR, AMEVCNTR15_EL0, 1), 1889 SR_FGT(SYS_AMEVCNTR1_EL0(4), HAFGRTR, AMEVCNTR14_EL0, 1), 1890 SR_FGT(SYS_AMEVCNTR1_EL0(3), HAFGRTR, AMEVCNTR13_EL0, 1), 1891 SR_FGT(SYS_AMEVCNTR1_EL0(2), HAFGRTR, AMEVCNTR12_EL0, 1), 1892 SR_FGT(SYS_AMEVCNTR1_EL0(1), HAFGRTR, AMEVCNTR11_EL0, 1), 1893 SR_FGT(SYS_AMEVCNTR1_EL0(0), HAFGRTR, AMEVCNTR10_EL0, 1), 1894 SR_FGT(SYS_AMCNTENCLR1_EL0, HAFGRTR, AMCNTEN1, 1), 1895 SR_FGT(SYS_AMCNTENSET1_EL0, HAFGRTR, AMCNTEN1, 1), 1896 SR_FGT(SYS_AMCNTENCLR0_EL0, HAFGRTR, AMCNTEN0, 1), 1897 SR_FGT(SYS_AMCNTENSET0_EL0, HAFGRTR, AMCNTEN0, 1), 1898 SR_FGT(SYS_AMEVCNTR0_EL0(3), HAFGRTR, AMEVCNTR03_EL0, 1), 1899 SR_FGT(SYS_AMEVCNTR0_EL0(2), HAFGRTR, AMEVCNTR02_EL0, 1), 1900 SR_FGT(SYS_AMEVCNTR0_EL0(1), HAFGRTR, AMEVCNTR01_EL0, 1), 1901 SR_FGT(SYS_AMEVCNTR0_EL0(0), HAFGRTR, AMEVCNTR00_EL0, 1), 1902 }; 1903 1904 static union trap_config get_trap_config(u32 sysreg) 1905 { 1906 return (union trap_config) { 1907 .val = xa_to_value(xa_load(&sr_forward_xa, sysreg)), 1908 }; 1909 } 1910 1911 static __init void print_nv_trap_error(const struct encoding_to_trap_config *tc, 1912 const char *type, int err) 1913 { 1914 kvm_err("%s line %d encoding range " 1915 "(%d, %d, %d, %d, %d) - (%d, %d, %d, %d, %d) (err=%d)\n", 1916 type, tc->line, 1917 sys_reg_Op0(tc->encoding), sys_reg_Op1(tc->encoding), 1918 sys_reg_CRn(tc->encoding), sys_reg_CRm(tc->encoding), 1919 sys_reg_Op2(tc->encoding), 1920 sys_reg_Op0(tc->end), sys_reg_Op1(tc->end), 1921 sys_reg_CRn(tc->end), sys_reg_CRm(tc->end), 1922 sys_reg_Op2(tc->end), 1923 err); 1924 } 1925 1926 static u32 encoding_next(u32 encoding) 1927 { 1928 u8 op0, op1, crn, crm, op2; 1929 1930 op0 = sys_reg_Op0(encoding); 1931 op1 = sys_reg_Op1(encoding); 1932 crn = sys_reg_CRn(encoding); 1933 crm = sys_reg_CRm(encoding); 1934 op2 = sys_reg_Op2(encoding); 1935 1936 if (op2 < Op2_mask) 1937 return sys_reg(op0, op1, crn, crm, op2 + 1); 1938 if (crm < CRm_mask) 1939 return sys_reg(op0, op1, crn, crm + 1, 0); 1940 if (crn < CRn_mask) 1941 return sys_reg(op0, op1, crn + 1, 0, 0); 1942 if (op1 < Op1_mask) 1943 return sys_reg(op0, op1 + 1, 0, 0, 0); 1944 1945 return sys_reg(op0 + 1, 0, 0, 0, 0); 1946 } 1947 1948 int __init populate_nv_trap_config(void) 1949 { 1950 int ret = 0; 1951 1952 BUILD_BUG_ON(sizeof(union trap_config) != sizeof(void *)); 1953 BUILD_BUG_ON(__NR_CGT_GROUP_IDS__ > BIT(TC_CGT_BITS)); 1954 BUILD_BUG_ON(__NR_FGT_GROUP_IDS__ > BIT(TC_FGT_BITS)); 1955 BUILD_BUG_ON(__NR_FG_FILTER_IDS__ > BIT(TC_FGF_BITS)); 1956 1957 for (int i = 0; i < ARRAY_SIZE(encoding_to_cgt); i++) { 1958 const struct encoding_to_trap_config *cgt = &encoding_to_cgt[i]; 1959 void *prev; 1960 1961 if (cgt->tc.val & BIT(63)) { 1962 kvm_err("CGT[%d] has MBZ bit set\n", i); 1963 ret = -EINVAL; 1964 } 1965 1966 for (u32 enc = cgt->encoding; enc <= cgt->end; enc = encoding_next(enc)) { 1967 prev = xa_store(&sr_forward_xa, enc, 1968 xa_mk_value(cgt->tc.val), GFP_KERNEL); 1969 if (prev && !xa_is_err(prev)) { 1970 ret = -EINVAL; 1971 print_nv_trap_error(cgt, "Duplicate CGT", ret); 1972 } 1973 1974 if (xa_is_err(prev)) { 1975 ret = xa_err(prev); 1976 print_nv_trap_error(cgt, "Failed CGT insertion", ret); 1977 } 1978 } 1979 } 1980 1981 kvm_info("nv: %ld coarse grained trap handlers\n", 1982 ARRAY_SIZE(encoding_to_cgt)); 1983 1984 if (!cpus_have_final_cap(ARM64_HAS_FGT)) 1985 goto check_mcb; 1986 1987 for (int i = 0; i < ARRAY_SIZE(encoding_to_fgt); i++) { 1988 const struct encoding_to_trap_config *fgt = &encoding_to_fgt[i]; 1989 union trap_config tc; 1990 void *prev; 1991 1992 if (fgt->tc.fgt >= __NR_FGT_GROUP_IDS__) { 1993 ret = -EINVAL; 1994 print_nv_trap_error(fgt, "Invalid FGT", ret); 1995 } 1996 1997 tc = get_trap_config(fgt->encoding); 1998 1999 if (tc.fgt) { 2000 ret = -EINVAL; 2001 print_nv_trap_error(fgt, "Duplicate FGT", ret); 2002 } 2003 2004 tc.val |= fgt->tc.val; 2005 prev = xa_store(&sr_forward_xa, fgt->encoding, 2006 xa_mk_value(tc.val), GFP_KERNEL); 2007 2008 if (xa_is_err(prev)) { 2009 ret = xa_err(prev); 2010 print_nv_trap_error(fgt, "Failed FGT insertion", ret); 2011 } 2012 } 2013 2014 kvm_info("nv: %ld fine grained trap handlers\n", 2015 ARRAY_SIZE(encoding_to_fgt)); 2016 2017 check_mcb: 2018 for (int id = __MULTIPLE_CONTROL_BITS__; id < __COMPLEX_CONDITIONS__; id++) { 2019 const enum cgt_group_id *cgids; 2020 2021 cgids = coarse_control_combo[id - __MULTIPLE_CONTROL_BITS__]; 2022 2023 for (int i = 0; cgids[i] != __RESERVED__; i++) { 2024 if (cgids[i] >= __MULTIPLE_CONTROL_BITS__) { 2025 kvm_err("Recursive MCB %d/%d\n", id, cgids[i]); 2026 ret = -EINVAL; 2027 } 2028 } 2029 } 2030 2031 if (ret) 2032 xa_destroy(&sr_forward_xa); 2033 2034 return ret; 2035 } 2036 2037 int __init populate_sysreg_config(const struct sys_reg_desc *sr, 2038 unsigned int idx) 2039 { 2040 union trap_config tc; 2041 u32 encoding; 2042 void *ret; 2043 2044 /* 2045 * 0 is a valid value for the index, but not for the storage. 2046 * We'll store (idx+1), so check against an offset'd limit. 2047 */ 2048 if (idx >= (BIT(TC_SRI_BITS) - 1)) { 2049 kvm_err("sysreg %s (%d) out of range\n", sr->name, idx); 2050 return -EINVAL; 2051 } 2052 2053 encoding = sys_reg(sr->Op0, sr->Op1, sr->CRn, sr->CRm, sr->Op2); 2054 tc = get_trap_config(encoding); 2055 2056 if (tc.sri) { 2057 kvm_err("sysreg %s (%d) duplicate entry (%d)\n", 2058 sr->name, idx - 1, tc.sri); 2059 return -EINVAL; 2060 } 2061 2062 tc.sri = idx + 1; 2063 ret = xa_store(&sr_forward_xa, encoding, 2064 xa_mk_value(tc.val), GFP_KERNEL); 2065 2066 return xa_err(ret); 2067 } 2068 2069 static enum trap_behaviour get_behaviour(struct kvm_vcpu *vcpu, 2070 const struct trap_bits *tb) 2071 { 2072 enum trap_behaviour b = BEHAVE_HANDLE_LOCALLY; 2073 u64 val; 2074 2075 val = __vcpu_sys_reg(vcpu, tb->index); 2076 if ((val & tb->mask) == tb->value) 2077 b |= tb->behaviour; 2078 2079 return b; 2080 } 2081 2082 static enum trap_behaviour __compute_trap_behaviour(struct kvm_vcpu *vcpu, 2083 const enum cgt_group_id id, 2084 enum trap_behaviour b) 2085 { 2086 switch (id) { 2087 const enum cgt_group_id *cgids; 2088 2089 case __RESERVED__ ... __MULTIPLE_CONTROL_BITS__ - 1: 2090 if (likely(id != __RESERVED__)) 2091 b |= get_behaviour(vcpu, &coarse_trap_bits[id]); 2092 break; 2093 case __MULTIPLE_CONTROL_BITS__ ... __COMPLEX_CONDITIONS__ - 1: 2094 /* Yes, this is recursive. Don't do anything stupid. */ 2095 cgids = coarse_control_combo[id - __MULTIPLE_CONTROL_BITS__]; 2096 for (int i = 0; cgids[i] != __RESERVED__; i++) 2097 b |= __compute_trap_behaviour(vcpu, cgids[i], b); 2098 break; 2099 default: 2100 if (ARRAY_SIZE(ccc)) 2101 b |= ccc[id - __COMPLEX_CONDITIONS__](vcpu); 2102 break; 2103 } 2104 2105 return b; 2106 } 2107 2108 static enum trap_behaviour compute_trap_behaviour(struct kvm_vcpu *vcpu, 2109 const union trap_config tc) 2110 { 2111 enum trap_behaviour b = BEHAVE_HANDLE_LOCALLY; 2112 2113 return __compute_trap_behaviour(vcpu, tc.cgt, b); 2114 } 2115 2116 static u64 kvm_get_sysreg_res0(struct kvm *kvm, enum vcpu_sysreg sr) 2117 { 2118 struct kvm_sysreg_masks *masks; 2119 2120 /* Only handle the VNCR-backed regs for now */ 2121 if (sr < __VNCR_START__) 2122 return 0; 2123 2124 masks = kvm->arch.sysreg_masks; 2125 2126 return masks->mask[sr - __VNCR_START__].res0; 2127 } 2128 2129 static bool check_fgt_bit(struct kvm *kvm, bool is_read, 2130 u64 val, const union trap_config tc) 2131 { 2132 enum vcpu_sysreg sr; 2133 2134 if (tc.pol) 2135 return (val & BIT(tc.bit)); 2136 2137 /* 2138 * FGTs with negative polarities are an absolute nightmare, as 2139 * we need to evaluate the bit in the light of the feature 2140 * that defines it. WTF were they thinking? 2141 * 2142 * So let's check if the bit has been earmarked as RES0, as 2143 * this indicates an unimplemented feature. 2144 */ 2145 if (val & BIT(tc.bit)) 2146 return false; 2147 2148 switch ((enum fgt_group_id)tc.fgt) { 2149 case HFGxTR_GROUP: 2150 sr = is_read ? HFGRTR_EL2 : HFGWTR_EL2; 2151 break; 2152 2153 case HDFGRTR_GROUP: 2154 sr = is_read ? HDFGRTR_EL2 : HDFGWTR_EL2; 2155 break; 2156 2157 case HAFGRTR_GROUP: 2158 sr = HAFGRTR_EL2; 2159 break; 2160 2161 case HFGITR_GROUP: 2162 sr = HFGITR_EL2; 2163 break; 2164 2165 default: 2166 WARN_ONCE(1, "Unhandled FGT group"); 2167 return false; 2168 } 2169 2170 return !(kvm_get_sysreg_res0(kvm, sr) & BIT(tc.bit)); 2171 } 2172 2173 bool triage_sysreg_trap(struct kvm_vcpu *vcpu, int *sr_index) 2174 { 2175 union trap_config tc; 2176 enum trap_behaviour b; 2177 bool is_read; 2178 u32 sysreg; 2179 u64 esr, val; 2180 2181 esr = kvm_vcpu_get_esr(vcpu); 2182 sysreg = esr_sys64_to_sysreg(esr); 2183 is_read = (esr & ESR_ELx_SYS64_ISS_DIR_MASK) == ESR_ELx_SYS64_ISS_DIR_READ; 2184 2185 tc = get_trap_config(sysreg); 2186 2187 /* 2188 * A value of 0 for the whole entry means that we know nothing 2189 * for this sysreg, and that it cannot be re-injected into the 2190 * nested hypervisor. In this situation, let's cut it short. 2191 */ 2192 if (!tc.val) 2193 goto local; 2194 2195 /* 2196 * If a sysreg can be trapped using a FGT, first check whether we 2197 * trap for the purpose of forbidding the feature. In that case, 2198 * inject an UNDEF. 2199 */ 2200 if (tc.fgt != __NO_FGT_GROUP__ && 2201 (vcpu->kvm->arch.fgu[tc.fgt] & BIT(tc.bit))) { 2202 kvm_inject_undefined(vcpu); 2203 return true; 2204 } 2205 2206 /* 2207 * If we're not nesting, immediately return to the caller, with the 2208 * sysreg index, should we have it. 2209 */ 2210 if (!vcpu_has_nv(vcpu) || is_hyp_ctxt(vcpu)) 2211 goto local; 2212 2213 switch ((enum fgt_group_id)tc.fgt) { 2214 case __NO_FGT_GROUP__: 2215 break; 2216 2217 case HFGxTR_GROUP: 2218 if (is_read) 2219 val = __vcpu_sys_reg(vcpu, HFGRTR_EL2); 2220 else 2221 val = __vcpu_sys_reg(vcpu, HFGWTR_EL2); 2222 break; 2223 2224 case HDFGRTR_GROUP: 2225 if (is_read) 2226 val = __vcpu_sys_reg(vcpu, HDFGRTR_EL2); 2227 else 2228 val = __vcpu_sys_reg(vcpu, HDFGWTR_EL2); 2229 break; 2230 2231 case HAFGRTR_GROUP: 2232 val = __vcpu_sys_reg(vcpu, HAFGRTR_EL2); 2233 break; 2234 2235 case HFGITR_GROUP: 2236 val = __vcpu_sys_reg(vcpu, HFGITR_EL2); 2237 switch (tc.fgf) { 2238 u64 tmp; 2239 2240 case __NO_FGF__: 2241 break; 2242 2243 case HCRX_FGTnXS: 2244 tmp = __vcpu_sys_reg(vcpu, HCRX_EL2); 2245 if (tmp & HCRX_EL2_FGTnXS) 2246 tc.fgt = __NO_FGT_GROUP__; 2247 } 2248 break; 2249 2250 case __NR_FGT_GROUP_IDS__: 2251 /* Something is really wrong, bail out */ 2252 WARN_ONCE(1, "__NR_FGT_GROUP_IDS__"); 2253 goto local; 2254 } 2255 2256 if (tc.fgt != __NO_FGT_GROUP__ && check_fgt_bit(vcpu->kvm, is_read, 2257 val, tc)) 2258 goto inject; 2259 2260 b = compute_trap_behaviour(vcpu, tc); 2261 2262 if (((b & BEHAVE_FORWARD_READ) && is_read) || 2263 ((b & BEHAVE_FORWARD_WRITE) && !is_read)) 2264 goto inject; 2265 2266 local: 2267 if (!tc.sri) { 2268 struct sys_reg_params params; 2269 2270 params = esr_sys64_to_params(esr); 2271 2272 /* 2273 * Check for the IMPDEF range, as per DDI0487 J.a, 2274 * D18.3.2 Reserved encodings for IMPLEMENTATION 2275 * DEFINED registers. 2276 */ 2277 if (!(params.Op0 == 3 && (params.CRn & 0b1011) == 0b1011)) 2278 print_sys_reg_msg(¶ms, 2279 "Unsupported guest access at: %lx\n", 2280 *vcpu_pc(vcpu)); 2281 kvm_inject_undefined(vcpu); 2282 return true; 2283 } 2284 2285 *sr_index = tc.sri - 1; 2286 return false; 2287 2288 inject: 2289 trace_kvm_forward_sysreg_trap(vcpu, sysreg, is_read); 2290 2291 kvm_inject_nested_sync(vcpu, kvm_vcpu_get_esr(vcpu)); 2292 return true; 2293 } 2294 2295 static bool forward_traps(struct kvm_vcpu *vcpu, u64 control_bit) 2296 { 2297 bool control_bit_set; 2298 2299 if (!vcpu_has_nv(vcpu)) 2300 return false; 2301 2302 control_bit_set = __vcpu_sys_reg(vcpu, HCR_EL2) & control_bit; 2303 if (!is_hyp_ctxt(vcpu) && control_bit_set) { 2304 kvm_inject_nested_sync(vcpu, kvm_vcpu_get_esr(vcpu)); 2305 return true; 2306 } 2307 return false; 2308 } 2309 2310 bool forward_smc_trap(struct kvm_vcpu *vcpu) 2311 { 2312 return forward_traps(vcpu, HCR_TSC); 2313 } 2314 2315 static u64 kvm_check_illegal_exception_return(struct kvm_vcpu *vcpu, u64 spsr) 2316 { 2317 u64 mode = spsr & PSR_MODE_MASK; 2318 2319 /* 2320 * Possible causes for an Illegal Exception Return from EL2: 2321 * - trying to return to EL3 2322 * - trying to return to an illegal M value 2323 * - trying to return to a 32bit EL 2324 * - trying to return to EL1 with HCR_EL2.TGE set 2325 */ 2326 if (mode == PSR_MODE_EL3t || mode == PSR_MODE_EL3h || 2327 mode == 0b00001 || (mode & BIT(1)) || 2328 (spsr & PSR_MODE32_BIT) || 2329 (vcpu_el2_tge_is_set(vcpu) && (mode == PSR_MODE_EL1t || 2330 mode == PSR_MODE_EL1h))) { 2331 /* 2332 * The guest is playing with our nerves. Preserve EL, SP, 2333 * masks, flags from the existing PSTATE, and set IL. 2334 * The HW will then generate an Illegal State Exception 2335 * immediately after ERET. 2336 */ 2337 spsr = *vcpu_cpsr(vcpu); 2338 2339 spsr &= (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT | 2340 PSR_N_BIT | PSR_Z_BIT | PSR_C_BIT | PSR_V_BIT | 2341 PSR_MODE_MASK | PSR_MODE32_BIT); 2342 spsr |= PSR_IL_BIT; 2343 } 2344 2345 return spsr; 2346 } 2347 2348 void kvm_emulate_nested_eret(struct kvm_vcpu *vcpu) 2349 { 2350 u64 spsr, elr, esr; 2351 2352 /* 2353 * Forward this trap to the virtual EL2 if the virtual 2354 * HCR_EL2.NV bit is set and this is coming from !EL2. 2355 */ 2356 if (forward_traps(vcpu, HCR_NV)) 2357 return; 2358 2359 spsr = vcpu_read_sys_reg(vcpu, SPSR_EL2); 2360 spsr = kvm_check_illegal_exception_return(vcpu, spsr); 2361 2362 /* Check for an ERETAx */ 2363 esr = kvm_vcpu_get_esr(vcpu); 2364 if (esr_iss_is_eretax(esr) && !kvm_auth_eretax(vcpu, &elr)) { 2365 /* 2366 * Oh no, ERETAx failed to authenticate. 2367 * 2368 * If we have FPACCOMBINE and we don't have a pending 2369 * Illegal Execution State exception (which has priority 2370 * over FPAC), deliver an exception right away. 2371 * 2372 * Otherwise, let the mangled ELR value trickle down the 2373 * ERET handling, and the guest will have a little surprise. 2374 */ 2375 if (kvm_has_pauth(vcpu->kvm, FPACCOMBINE) && !(spsr & PSR_IL_BIT)) { 2376 esr &= ESR_ELx_ERET_ISS_ERETA; 2377 esr |= FIELD_PREP(ESR_ELx_EC_MASK, ESR_ELx_EC_FPAC); 2378 kvm_inject_nested_sync(vcpu, esr); 2379 return; 2380 } 2381 } 2382 2383 preempt_disable(); 2384 kvm_arch_vcpu_put(vcpu); 2385 2386 if (!esr_iss_is_eretax(esr)) 2387 elr = __vcpu_sys_reg(vcpu, ELR_EL2); 2388 2389 trace_kvm_nested_eret(vcpu, elr, spsr); 2390 2391 *vcpu_pc(vcpu) = elr; 2392 *vcpu_cpsr(vcpu) = spsr; 2393 2394 kvm_arch_vcpu_load(vcpu, smp_processor_id()); 2395 preempt_enable(); 2396 } 2397 2398 static void kvm_inject_el2_exception(struct kvm_vcpu *vcpu, u64 esr_el2, 2399 enum exception_type type) 2400 { 2401 trace_kvm_inject_nested_exception(vcpu, esr_el2, type); 2402 2403 switch (type) { 2404 case except_type_sync: 2405 kvm_pend_exception(vcpu, EXCEPT_AA64_EL2_SYNC); 2406 vcpu_write_sys_reg(vcpu, esr_el2, ESR_EL2); 2407 break; 2408 case except_type_irq: 2409 kvm_pend_exception(vcpu, EXCEPT_AA64_EL2_IRQ); 2410 break; 2411 default: 2412 WARN_ONCE(1, "Unsupported EL2 exception injection %d\n", type); 2413 } 2414 } 2415 2416 /* 2417 * Emulate taking an exception to EL2. 2418 * See ARM ARM J8.1.2 AArch64.TakeException() 2419 */ 2420 static int kvm_inject_nested(struct kvm_vcpu *vcpu, u64 esr_el2, 2421 enum exception_type type) 2422 { 2423 u64 pstate, mode; 2424 bool direct_inject; 2425 2426 if (!vcpu_has_nv(vcpu)) { 2427 kvm_err("Unexpected call to %s for the non-nesting configuration\n", 2428 __func__); 2429 return -EINVAL; 2430 } 2431 2432 /* 2433 * As for ERET, we can avoid doing too much on the injection path by 2434 * checking that we either took the exception from a VHE host 2435 * userspace or from vEL2. In these cases, there is no change in 2436 * translation regime (or anything else), so let's do as little as 2437 * possible. 2438 */ 2439 pstate = *vcpu_cpsr(vcpu); 2440 mode = pstate & (PSR_MODE_MASK | PSR_MODE32_BIT); 2441 2442 direct_inject = (mode == PSR_MODE_EL0t && 2443 vcpu_el2_e2h_is_set(vcpu) && 2444 vcpu_el2_tge_is_set(vcpu)); 2445 direct_inject |= (mode == PSR_MODE_EL2h || mode == PSR_MODE_EL2t); 2446 2447 if (direct_inject) { 2448 kvm_inject_el2_exception(vcpu, esr_el2, type); 2449 return 1; 2450 } 2451 2452 preempt_disable(); 2453 2454 /* 2455 * We may have an exception or PC update in the EL0/EL1 context. 2456 * Commit it before entering EL2. 2457 */ 2458 __kvm_adjust_pc(vcpu); 2459 2460 kvm_arch_vcpu_put(vcpu); 2461 2462 kvm_inject_el2_exception(vcpu, esr_el2, type); 2463 2464 /* 2465 * A hard requirement is that a switch between EL1 and EL2 2466 * contexts has to happen between a put/load, so that we can 2467 * pick the correct timer and interrupt configuration, among 2468 * other things. 2469 * 2470 * Make sure the exception actually took place before we load 2471 * the new context. 2472 */ 2473 __kvm_adjust_pc(vcpu); 2474 2475 kvm_arch_vcpu_load(vcpu, smp_processor_id()); 2476 preempt_enable(); 2477 2478 return 1; 2479 } 2480 2481 int kvm_inject_nested_sync(struct kvm_vcpu *vcpu, u64 esr_el2) 2482 { 2483 return kvm_inject_nested(vcpu, esr_el2, except_type_sync); 2484 } 2485 2486 int kvm_inject_nested_irq(struct kvm_vcpu *vcpu) 2487 { 2488 /* 2489 * Do not inject an irq if the: 2490 * - Current exception level is EL2, and 2491 * - virtual HCR_EL2.TGE == 0 2492 * - virtual HCR_EL2.IMO == 0 2493 * 2494 * See Table D1-17 "Physical interrupt target and masking when EL3 is 2495 * not implemented and EL2 is implemented" in ARM DDI 0487C.a. 2496 */ 2497 2498 if (vcpu_is_el2(vcpu) && !vcpu_el2_tge_is_set(vcpu) && 2499 !(__vcpu_sys_reg(vcpu, HCR_EL2) & HCR_IMO)) 2500 return 1; 2501 2502 /* esr_el2 value doesn't matter for exits due to irqs. */ 2503 return kvm_inject_nested(vcpu, 0, except_type_irq); 2504 } 2505