1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2016 - Linaro and Columbia University 4 * Author: Jintack Lim <jintack.lim@linaro.org> 5 */ 6 7 #include <linux/kvm.h> 8 #include <linux/kvm_host.h> 9 10 #include <asm/kvm_emulate.h> 11 #include <asm/kvm_nested.h> 12 13 #include "hyp/include/hyp/adjust_pc.h" 14 15 #include "trace.h" 16 17 enum trap_behaviour { 18 BEHAVE_HANDLE_LOCALLY = 0, 19 20 BEHAVE_FORWARD_READ = BIT(0), 21 BEHAVE_FORWARD_WRITE = BIT(1), 22 BEHAVE_FORWARD_RW = BEHAVE_FORWARD_READ | BEHAVE_FORWARD_WRITE, 23 24 /* Traps that take effect in Host EL0, this is rare! */ 25 BEHAVE_FORWARD_IN_HOST_EL0 = BIT(2), 26 }; 27 28 struct trap_bits { 29 const enum vcpu_sysreg index; 30 const enum trap_behaviour behaviour; 31 const u64 value; 32 const u64 mask; 33 }; 34 35 /* Coarse Grained Trap definitions */ 36 enum cgt_group_id { 37 /* Indicates no coarse trap control */ 38 __RESERVED__, 39 40 /* 41 * The first batch of IDs denote coarse trapping that are used 42 * on their own instead of being part of a combination of 43 * trap controls. 44 */ 45 CGT_HCR_TID1, 46 CGT_HCR_TID2, 47 CGT_HCR_TID3, 48 CGT_HCR_IMO, 49 CGT_HCR_FMO, 50 CGT_HCR_TIDCP, 51 CGT_HCR_TACR, 52 CGT_HCR_TSW, 53 CGT_HCR_TPC, 54 CGT_HCR_TPU, 55 CGT_HCR_TTLB, 56 CGT_HCR_TVM, 57 CGT_HCR_TDZ, 58 CGT_HCR_TRVM, 59 CGT_HCR_TLOR, 60 CGT_HCR_TERR, 61 CGT_HCR_APK, 62 CGT_HCR_NV, 63 CGT_HCR_NV_nNV2, 64 CGT_HCR_NV1_nNV2, 65 CGT_HCR_AT, 66 CGT_HCR_nFIEN, 67 CGT_HCR_TID4, 68 CGT_HCR_TICAB, 69 CGT_HCR_TOCU, 70 CGT_HCR_ENSCXT, 71 CGT_HCR_TTLBIS, 72 CGT_HCR_TTLBOS, 73 74 CGT_MDCR_TPMCR, 75 CGT_MDCR_TPM, 76 CGT_MDCR_TDE, 77 CGT_MDCR_TDA, 78 CGT_MDCR_TDOSA, 79 CGT_MDCR_TDRA, 80 CGT_MDCR_E2PB, 81 CGT_MDCR_TPMS, 82 CGT_MDCR_TTRF, 83 CGT_MDCR_E2TB, 84 CGT_MDCR_TDCC, 85 86 CGT_CPTR_TAM, 87 CGT_CPTR_TCPAC, 88 89 CGT_HCRX_EnFPM, 90 CGT_HCRX_TCR2En, 91 92 CGT_ICH_HCR_TC, 93 CGT_ICH_HCR_TALL0, 94 CGT_ICH_HCR_TALL1, 95 CGT_ICH_HCR_TDIR, 96 97 /* 98 * Anything after this point is a combination of coarse trap 99 * controls, which must all be evaluated to decide what to do. 100 */ 101 __MULTIPLE_CONTROL_BITS__, 102 CGT_HCR_IMO_FMO_ICH_HCR_TC = __MULTIPLE_CONTROL_BITS__, 103 CGT_HCR_TID2_TID4, 104 CGT_HCR_TTLB_TTLBIS, 105 CGT_HCR_TTLB_TTLBOS, 106 CGT_HCR_TVM_TRVM, 107 CGT_HCR_TVM_TRVM_HCRX_TCR2En, 108 CGT_HCR_TPU_TICAB, 109 CGT_HCR_TPU_TOCU, 110 CGT_HCR_NV1_nNV2_ENSCXT, 111 CGT_MDCR_TPM_TPMCR, 112 CGT_MDCR_TPM_HPMN, 113 CGT_MDCR_TDE_TDA, 114 CGT_MDCR_TDE_TDOSA, 115 CGT_MDCR_TDE_TDRA, 116 CGT_MDCR_TDCC_TDE_TDA, 117 118 CGT_ICH_HCR_TC_TDIR, 119 120 /* 121 * Anything after this point requires a callback evaluating a 122 * complex trap condition. Ugly stuff. 123 */ 124 __COMPLEX_CONDITIONS__, 125 CGT_CNTHCTL_EL1PCTEN = __COMPLEX_CONDITIONS__, 126 CGT_CNTHCTL_EL1PTEN, 127 128 CGT_CPTR_TTA, 129 CGT_MDCR_HPMN, 130 131 /* Must be last */ 132 __NR_CGT_GROUP_IDS__ 133 }; 134 135 static const struct trap_bits coarse_trap_bits[] = { 136 [CGT_HCR_TID1] = { 137 .index = HCR_EL2, 138 .value = HCR_TID1, 139 .mask = HCR_TID1, 140 .behaviour = BEHAVE_FORWARD_READ, 141 }, 142 [CGT_HCR_TID2] = { 143 .index = HCR_EL2, 144 .value = HCR_TID2, 145 .mask = HCR_TID2, 146 .behaviour = BEHAVE_FORWARD_RW, 147 }, 148 [CGT_HCR_TID3] = { 149 .index = HCR_EL2, 150 .value = HCR_TID3, 151 .mask = HCR_TID3, 152 .behaviour = BEHAVE_FORWARD_READ, 153 }, 154 [CGT_HCR_IMO] = { 155 .index = HCR_EL2, 156 .value = HCR_IMO, 157 .mask = HCR_IMO, 158 .behaviour = BEHAVE_FORWARD_WRITE, 159 }, 160 [CGT_HCR_FMO] = { 161 .index = HCR_EL2, 162 .value = HCR_FMO, 163 .mask = HCR_FMO, 164 .behaviour = BEHAVE_FORWARD_WRITE, 165 }, 166 [CGT_HCR_TIDCP] = { 167 .index = HCR_EL2, 168 .value = HCR_TIDCP, 169 .mask = HCR_TIDCP, 170 .behaviour = BEHAVE_FORWARD_RW, 171 }, 172 [CGT_HCR_TACR] = { 173 .index = HCR_EL2, 174 .value = HCR_TACR, 175 .mask = HCR_TACR, 176 .behaviour = BEHAVE_FORWARD_RW, 177 }, 178 [CGT_HCR_TSW] = { 179 .index = HCR_EL2, 180 .value = HCR_TSW, 181 .mask = HCR_TSW, 182 .behaviour = BEHAVE_FORWARD_RW, 183 }, 184 [CGT_HCR_TPC] = { /* Also called TCPC when FEAT_DPB is implemented */ 185 .index = HCR_EL2, 186 .value = HCR_TPC, 187 .mask = HCR_TPC, 188 .behaviour = BEHAVE_FORWARD_RW, 189 }, 190 [CGT_HCR_TPU] = { 191 .index = HCR_EL2, 192 .value = HCR_TPU, 193 .mask = HCR_TPU, 194 .behaviour = BEHAVE_FORWARD_RW, 195 }, 196 [CGT_HCR_TTLB] = { 197 .index = HCR_EL2, 198 .value = HCR_TTLB, 199 .mask = HCR_TTLB, 200 .behaviour = BEHAVE_FORWARD_RW, 201 }, 202 [CGT_HCR_TVM] = { 203 .index = HCR_EL2, 204 .value = HCR_TVM, 205 .mask = HCR_TVM, 206 .behaviour = BEHAVE_FORWARD_WRITE, 207 }, 208 [CGT_HCR_TDZ] = { 209 .index = HCR_EL2, 210 .value = HCR_TDZ, 211 .mask = HCR_TDZ, 212 .behaviour = BEHAVE_FORWARD_RW, 213 }, 214 [CGT_HCR_TRVM] = { 215 .index = HCR_EL2, 216 .value = HCR_TRVM, 217 .mask = HCR_TRVM, 218 .behaviour = BEHAVE_FORWARD_READ, 219 }, 220 [CGT_HCR_TLOR] = { 221 .index = HCR_EL2, 222 .value = HCR_TLOR, 223 .mask = HCR_TLOR, 224 .behaviour = BEHAVE_FORWARD_RW, 225 }, 226 [CGT_HCR_TERR] = { 227 .index = HCR_EL2, 228 .value = HCR_TERR, 229 .mask = HCR_TERR, 230 .behaviour = BEHAVE_FORWARD_RW, 231 }, 232 [CGT_HCR_APK] = { 233 .index = HCR_EL2, 234 .value = 0, 235 .mask = HCR_APK, 236 .behaviour = BEHAVE_FORWARD_RW, 237 }, 238 [CGT_HCR_NV] = { 239 .index = HCR_EL2, 240 .value = HCR_NV, 241 .mask = HCR_NV, 242 .behaviour = BEHAVE_FORWARD_RW, 243 }, 244 [CGT_HCR_NV_nNV2] = { 245 .index = HCR_EL2, 246 .value = HCR_NV, 247 .mask = HCR_NV | HCR_NV2, 248 .behaviour = BEHAVE_FORWARD_RW, 249 }, 250 [CGT_HCR_NV1_nNV2] = { 251 .index = HCR_EL2, 252 .value = HCR_NV | HCR_NV1, 253 .mask = HCR_NV | HCR_NV1 | HCR_NV2, 254 .behaviour = BEHAVE_FORWARD_RW, 255 }, 256 [CGT_HCR_AT] = { 257 .index = HCR_EL2, 258 .value = HCR_AT, 259 .mask = HCR_AT, 260 .behaviour = BEHAVE_FORWARD_RW, 261 }, 262 [CGT_HCR_nFIEN] = { 263 .index = HCR_EL2, 264 .value = 0, 265 .mask = HCR_FIEN, 266 .behaviour = BEHAVE_FORWARD_RW, 267 }, 268 [CGT_HCR_TID4] = { 269 .index = HCR_EL2, 270 .value = HCR_TID4, 271 .mask = HCR_TID4, 272 .behaviour = BEHAVE_FORWARD_RW, 273 }, 274 [CGT_HCR_TICAB] = { 275 .index = HCR_EL2, 276 .value = HCR_TICAB, 277 .mask = HCR_TICAB, 278 .behaviour = BEHAVE_FORWARD_RW, 279 }, 280 [CGT_HCR_TOCU] = { 281 .index = HCR_EL2, 282 .value = HCR_TOCU, 283 .mask = HCR_TOCU, 284 .behaviour = BEHAVE_FORWARD_RW, 285 }, 286 [CGT_HCR_ENSCXT] = { 287 .index = HCR_EL2, 288 .value = 0, 289 .mask = HCR_ENSCXT, 290 .behaviour = BEHAVE_FORWARD_RW, 291 }, 292 [CGT_HCR_TTLBIS] = { 293 .index = HCR_EL2, 294 .value = HCR_TTLBIS, 295 .mask = HCR_TTLBIS, 296 .behaviour = BEHAVE_FORWARD_RW, 297 }, 298 [CGT_HCR_TTLBOS] = { 299 .index = HCR_EL2, 300 .value = HCR_TTLBOS, 301 .mask = HCR_TTLBOS, 302 .behaviour = BEHAVE_FORWARD_RW, 303 }, 304 [CGT_MDCR_TPMCR] = { 305 .index = MDCR_EL2, 306 .value = MDCR_EL2_TPMCR, 307 .mask = MDCR_EL2_TPMCR, 308 .behaviour = BEHAVE_FORWARD_RW | 309 BEHAVE_FORWARD_IN_HOST_EL0, 310 }, 311 [CGT_MDCR_TPM] = { 312 .index = MDCR_EL2, 313 .value = MDCR_EL2_TPM, 314 .mask = MDCR_EL2_TPM, 315 .behaviour = BEHAVE_FORWARD_RW | 316 BEHAVE_FORWARD_IN_HOST_EL0, 317 }, 318 [CGT_MDCR_TDE] = { 319 .index = MDCR_EL2, 320 .value = MDCR_EL2_TDE, 321 .mask = MDCR_EL2_TDE, 322 .behaviour = BEHAVE_FORWARD_RW, 323 }, 324 [CGT_MDCR_TDA] = { 325 .index = MDCR_EL2, 326 .value = MDCR_EL2_TDA, 327 .mask = MDCR_EL2_TDA, 328 .behaviour = BEHAVE_FORWARD_RW, 329 }, 330 [CGT_MDCR_TDOSA] = { 331 .index = MDCR_EL2, 332 .value = MDCR_EL2_TDOSA, 333 .mask = MDCR_EL2_TDOSA, 334 .behaviour = BEHAVE_FORWARD_RW, 335 }, 336 [CGT_MDCR_TDRA] = { 337 .index = MDCR_EL2, 338 .value = MDCR_EL2_TDRA, 339 .mask = MDCR_EL2_TDRA, 340 .behaviour = BEHAVE_FORWARD_RW, 341 }, 342 [CGT_MDCR_E2PB] = { 343 .index = MDCR_EL2, 344 .value = 0, 345 .mask = BIT(MDCR_EL2_E2PB_SHIFT), 346 .behaviour = BEHAVE_FORWARD_RW, 347 }, 348 [CGT_MDCR_TPMS] = { 349 .index = MDCR_EL2, 350 .value = MDCR_EL2_TPMS, 351 .mask = MDCR_EL2_TPMS, 352 .behaviour = BEHAVE_FORWARD_RW, 353 }, 354 [CGT_MDCR_TTRF] = { 355 .index = MDCR_EL2, 356 .value = MDCR_EL2_TTRF, 357 .mask = MDCR_EL2_TTRF, 358 .behaviour = BEHAVE_FORWARD_RW, 359 }, 360 [CGT_MDCR_E2TB] = { 361 .index = MDCR_EL2, 362 .value = 0, 363 .mask = BIT(MDCR_EL2_E2TB_SHIFT), 364 .behaviour = BEHAVE_FORWARD_RW, 365 }, 366 [CGT_MDCR_TDCC] = { 367 .index = MDCR_EL2, 368 .value = MDCR_EL2_TDCC, 369 .mask = MDCR_EL2_TDCC, 370 .behaviour = BEHAVE_FORWARD_RW, 371 }, 372 [CGT_CPTR_TAM] = { 373 .index = CPTR_EL2, 374 .value = CPTR_EL2_TAM, 375 .mask = CPTR_EL2_TAM, 376 .behaviour = BEHAVE_FORWARD_RW, 377 }, 378 [CGT_CPTR_TCPAC] = { 379 .index = CPTR_EL2, 380 .value = CPTR_EL2_TCPAC, 381 .mask = CPTR_EL2_TCPAC, 382 .behaviour = BEHAVE_FORWARD_RW, 383 }, 384 [CGT_HCRX_EnFPM] = { 385 .index = HCRX_EL2, 386 .value = 0, 387 .mask = HCRX_EL2_EnFPM, 388 .behaviour = BEHAVE_FORWARD_RW, 389 }, 390 [CGT_HCRX_TCR2En] = { 391 .index = HCRX_EL2, 392 .value = 0, 393 .mask = HCRX_EL2_TCR2En, 394 .behaviour = BEHAVE_FORWARD_RW, 395 }, 396 [CGT_ICH_HCR_TC] = { 397 .index = ICH_HCR_EL2, 398 .value = ICH_HCR_TC, 399 .mask = ICH_HCR_TC, 400 .behaviour = BEHAVE_FORWARD_RW, 401 }, 402 [CGT_ICH_HCR_TALL0] = { 403 .index = ICH_HCR_EL2, 404 .value = ICH_HCR_TALL0, 405 .mask = ICH_HCR_TALL0, 406 .behaviour = BEHAVE_FORWARD_RW, 407 }, 408 [CGT_ICH_HCR_TALL1] = { 409 .index = ICH_HCR_EL2, 410 .value = ICH_HCR_TALL1, 411 .mask = ICH_HCR_TALL1, 412 .behaviour = BEHAVE_FORWARD_RW, 413 }, 414 [CGT_ICH_HCR_TDIR] = { 415 .index = ICH_HCR_EL2, 416 .value = ICH_HCR_TDIR, 417 .mask = ICH_HCR_TDIR, 418 .behaviour = BEHAVE_FORWARD_RW, 419 }, 420 }; 421 422 #define MCB(id, ...) \ 423 [id - __MULTIPLE_CONTROL_BITS__] = \ 424 (const enum cgt_group_id[]){ \ 425 __VA_ARGS__, __RESERVED__ \ 426 } 427 428 static const enum cgt_group_id *coarse_control_combo[] = { 429 MCB(CGT_HCR_TID2_TID4, CGT_HCR_TID2, CGT_HCR_TID4), 430 MCB(CGT_HCR_TTLB_TTLBIS, CGT_HCR_TTLB, CGT_HCR_TTLBIS), 431 MCB(CGT_HCR_TTLB_TTLBOS, CGT_HCR_TTLB, CGT_HCR_TTLBOS), 432 MCB(CGT_HCR_TVM_TRVM, CGT_HCR_TVM, CGT_HCR_TRVM), 433 MCB(CGT_HCR_TVM_TRVM_HCRX_TCR2En, 434 CGT_HCR_TVM, CGT_HCR_TRVM, CGT_HCRX_TCR2En), 435 MCB(CGT_HCR_TPU_TICAB, CGT_HCR_TPU, CGT_HCR_TICAB), 436 MCB(CGT_HCR_TPU_TOCU, CGT_HCR_TPU, CGT_HCR_TOCU), 437 MCB(CGT_HCR_NV1_nNV2_ENSCXT, CGT_HCR_NV1_nNV2, CGT_HCR_ENSCXT), 438 MCB(CGT_MDCR_TPM_TPMCR, CGT_MDCR_TPM, CGT_MDCR_TPMCR), 439 MCB(CGT_MDCR_TPM_HPMN, CGT_MDCR_TPM, CGT_MDCR_HPMN), 440 MCB(CGT_MDCR_TDE_TDA, CGT_MDCR_TDE, CGT_MDCR_TDA), 441 MCB(CGT_MDCR_TDE_TDOSA, CGT_MDCR_TDE, CGT_MDCR_TDOSA), 442 MCB(CGT_MDCR_TDE_TDRA, CGT_MDCR_TDE, CGT_MDCR_TDRA), 443 MCB(CGT_MDCR_TDCC_TDE_TDA, CGT_MDCR_TDCC, CGT_MDCR_TDE, CGT_MDCR_TDA), 444 445 MCB(CGT_HCR_IMO_FMO_ICH_HCR_TC, CGT_HCR_IMO, CGT_HCR_FMO, CGT_ICH_HCR_TC), 446 MCB(CGT_ICH_HCR_TC_TDIR, CGT_ICH_HCR_TC, CGT_ICH_HCR_TDIR), 447 }; 448 449 typedef enum trap_behaviour (*complex_condition_check)(struct kvm_vcpu *); 450 451 /* 452 * Warning, maximum confusion ahead. 453 * 454 * When E2H=0, CNTHCTL_EL2[1:0] are defined as EL1PCEN:EL1PCTEN 455 * When E2H=1, CNTHCTL_EL2[11:10] are defined as EL1PTEN:EL1PCTEN 456 * 457 * Note the single letter difference? Yet, the bits have the same 458 * function despite a different layout and a different name. 459 * 460 * We don't try to reconcile this mess. We just use the E2H=0 bits 461 * to generate something that is in the E2H=1 format, and live with 462 * it. You're welcome. 463 */ 464 static u64 get_sanitized_cnthctl(struct kvm_vcpu *vcpu) 465 { 466 u64 val = __vcpu_sys_reg(vcpu, CNTHCTL_EL2); 467 468 if (!vcpu_el2_e2h_is_set(vcpu)) 469 val = (val & (CNTHCTL_EL1PCEN | CNTHCTL_EL1PCTEN)) << 10; 470 471 return val & ((CNTHCTL_EL1PCEN | CNTHCTL_EL1PCTEN) << 10); 472 } 473 474 static enum trap_behaviour check_cnthctl_el1pcten(struct kvm_vcpu *vcpu) 475 { 476 if (get_sanitized_cnthctl(vcpu) & (CNTHCTL_EL1PCTEN << 10)) 477 return BEHAVE_HANDLE_LOCALLY; 478 479 return BEHAVE_FORWARD_RW; 480 } 481 482 static enum trap_behaviour check_cnthctl_el1pten(struct kvm_vcpu *vcpu) 483 { 484 if (get_sanitized_cnthctl(vcpu) & (CNTHCTL_EL1PCEN << 10)) 485 return BEHAVE_HANDLE_LOCALLY; 486 487 return BEHAVE_FORWARD_RW; 488 } 489 490 static enum trap_behaviour check_cptr_tta(struct kvm_vcpu *vcpu) 491 { 492 u64 val = __vcpu_sys_reg(vcpu, CPTR_EL2); 493 494 if (!vcpu_el2_e2h_is_set(vcpu)) 495 val = translate_cptr_el2_to_cpacr_el1(val); 496 497 if (val & CPACR_ELx_TTA) 498 return BEHAVE_FORWARD_RW; 499 500 return BEHAVE_HANDLE_LOCALLY; 501 } 502 503 static enum trap_behaviour check_mdcr_hpmn(struct kvm_vcpu *vcpu) 504 { 505 u32 sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu)); 506 unsigned int idx; 507 508 509 switch (sysreg) { 510 case SYS_PMEVTYPERn_EL0(0) ... SYS_PMEVTYPERn_EL0(30): 511 case SYS_PMEVCNTRn_EL0(0) ... SYS_PMEVCNTRn_EL0(30): 512 idx = (sys_reg_CRm(sysreg) & 0x3) << 3 | sys_reg_Op2(sysreg); 513 break; 514 case SYS_PMXEVTYPER_EL0: 515 case SYS_PMXEVCNTR_EL0: 516 idx = SYS_FIELD_GET(PMSELR_EL0, SEL, 517 __vcpu_sys_reg(vcpu, PMSELR_EL0)); 518 break; 519 default: 520 /* Someone used this trap helper for something else... */ 521 KVM_BUG_ON(1, vcpu->kvm); 522 return BEHAVE_HANDLE_LOCALLY; 523 } 524 525 if (kvm_pmu_counter_is_hyp(vcpu, idx)) 526 return BEHAVE_FORWARD_RW | BEHAVE_FORWARD_IN_HOST_EL0; 527 528 return BEHAVE_HANDLE_LOCALLY; 529 } 530 531 #define CCC(id, fn) \ 532 [id - __COMPLEX_CONDITIONS__] = fn 533 534 static const complex_condition_check ccc[] = { 535 CCC(CGT_CNTHCTL_EL1PCTEN, check_cnthctl_el1pcten), 536 CCC(CGT_CNTHCTL_EL1PTEN, check_cnthctl_el1pten), 537 CCC(CGT_CPTR_TTA, check_cptr_tta), 538 CCC(CGT_MDCR_HPMN, check_mdcr_hpmn), 539 }; 540 541 /* 542 * Bit assignment for the trap controls. We use a 64bit word with the 543 * following layout for each trapped sysreg: 544 * 545 * [9:0] enum cgt_group_id (10 bits) 546 * [13:10] enum fgt_group_id (4 bits) 547 * [19:14] bit number in the FGT register (6 bits) 548 * [20] trap polarity (1 bit) 549 * [25:21] FG filter (5 bits) 550 * [35:26] Main SysReg table index (10 bits) 551 * [62:36] Unused (27 bits) 552 * [63] RES0 - Must be zero, as lost on insertion in the xarray 553 */ 554 #define TC_CGT_BITS 10 555 #define TC_FGT_BITS 4 556 #define TC_FGF_BITS 5 557 #define TC_SRI_BITS 10 558 559 union trap_config { 560 u64 val; 561 struct { 562 unsigned long cgt:TC_CGT_BITS; /* Coarse Grained Trap id */ 563 unsigned long fgt:TC_FGT_BITS; /* Fine Grained Trap id */ 564 unsigned long bit:6; /* Bit number */ 565 unsigned long pol:1; /* Polarity */ 566 unsigned long fgf:TC_FGF_BITS; /* Fine Grained Filter */ 567 unsigned long sri:TC_SRI_BITS; /* SysReg Index */ 568 unsigned long unused:27; /* Unused, should be zero */ 569 unsigned long mbz:1; /* Must Be Zero */ 570 }; 571 }; 572 573 struct encoding_to_trap_config { 574 const u32 encoding; 575 const u32 end; 576 const union trap_config tc; 577 const unsigned int line; 578 }; 579 580 #define SR_RANGE_TRAP(sr_start, sr_end, trap_id) \ 581 { \ 582 .encoding = sr_start, \ 583 .end = sr_end, \ 584 .tc = { \ 585 .cgt = trap_id, \ 586 }, \ 587 .line = __LINE__, \ 588 } 589 590 #define SR_TRAP(sr, trap_id) SR_RANGE_TRAP(sr, sr, trap_id) 591 592 /* 593 * Map encoding to trap bits for exception reported with EC=0x18. 594 * These must only be evaluated when running a nested hypervisor, but 595 * that the current context is not a hypervisor context. When the 596 * trapped access matches one of the trap controls, the exception is 597 * re-injected in the nested hypervisor. 598 */ 599 static const struct encoding_to_trap_config encoding_to_cgt[] __initconst = { 600 SR_TRAP(SYS_REVIDR_EL1, CGT_HCR_TID1), 601 SR_TRAP(SYS_AIDR_EL1, CGT_HCR_TID1), 602 SR_TRAP(SYS_SMIDR_EL1, CGT_HCR_TID1), 603 SR_TRAP(SYS_CTR_EL0, CGT_HCR_TID2), 604 SR_TRAP(SYS_CCSIDR_EL1, CGT_HCR_TID2_TID4), 605 SR_TRAP(SYS_CCSIDR2_EL1, CGT_HCR_TID2_TID4), 606 SR_TRAP(SYS_CLIDR_EL1, CGT_HCR_TID2_TID4), 607 SR_TRAP(SYS_CSSELR_EL1, CGT_HCR_TID2_TID4), 608 SR_RANGE_TRAP(SYS_ID_PFR0_EL1, 609 sys_reg(3, 0, 0, 7, 7), CGT_HCR_TID3), 610 SR_TRAP(SYS_ICC_SGI0R_EL1, CGT_HCR_IMO_FMO_ICH_HCR_TC), 611 SR_TRAP(SYS_ICC_ASGI1R_EL1, CGT_HCR_IMO_FMO_ICH_HCR_TC), 612 SR_TRAP(SYS_ICC_SGI1R_EL1, CGT_HCR_IMO_FMO_ICH_HCR_TC), 613 SR_RANGE_TRAP(sys_reg(3, 0, 11, 0, 0), 614 sys_reg(3, 0, 11, 15, 7), CGT_HCR_TIDCP), 615 SR_RANGE_TRAP(sys_reg(3, 1, 11, 0, 0), 616 sys_reg(3, 1, 11, 15, 7), CGT_HCR_TIDCP), 617 SR_RANGE_TRAP(sys_reg(3, 2, 11, 0, 0), 618 sys_reg(3, 2, 11, 15, 7), CGT_HCR_TIDCP), 619 SR_RANGE_TRAP(sys_reg(3, 3, 11, 0, 0), 620 sys_reg(3, 3, 11, 15, 7), CGT_HCR_TIDCP), 621 SR_RANGE_TRAP(sys_reg(3, 4, 11, 0, 0), 622 sys_reg(3, 4, 11, 15, 7), CGT_HCR_TIDCP), 623 SR_RANGE_TRAP(sys_reg(3, 5, 11, 0, 0), 624 sys_reg(3, 5, 11, 15, 7), CGT_HCR_TIDCP), 625 SR_RANGE_TRAP(sys_reg(3, 6, 11, 0, 0), 626 sys_reg(3, 6, 11, 15, 7), CGT_HCR_TIDCP), 627 SR_RANGE_TRAP(sys_reg(3, 7, 11, 0, 0), 628 sys_reg(3, 7, 11, 15, 7), CGT_HCR_TIDCP), 629 SR_RANGE_TRAP(sys_reg(3, 0, 15, 0, 0), 630 sys_reg(3, 0, 15, 15, 7), CGT_HCR_TIDCP), 631 SR_RANGE_TRAP(sys_reg(3, 1, 15, 0, 0), 632 sys_reg(3, 1, 15, 15, 7), CGT_HCR_TIDCP), 633 SR_RANGE_TRAP(sys_reg(3, 2, 15, 0, 0), 634 sys_reg(3, 2, 15, 15, 7), CGT_HCR_TIDCP), 635 SR_RANGE_TRAP(sys_reg(3, 3, 15, 0, 0), 636 sys_reg(3, 3, 15, 15, 7), CGT_HCR_TIDCP), 637 SR_RANGE_TRAP(sys_reg(3, 4, 15, 0, 0), 638 sys_reg(3, 4, 15, 15, 7), CGT_HCR_TIDCP), 639 SR_RANGE_TRAP(sys_reg(3, 5, 15, 0, 0), 640 sys_reg(3, 5, 15, 15, 7), CGT_HCR_TIDCP), 641 SR_RANGE_TRAP(sys_reg(3, 6, 15, 0, 0), 642 sys_reg(3, 6, 15, 15, 7), CGT_HCR_TIDCP), 643 SR_RANGE_TRAP(sys_reg(3, 7, 15, 0, 0), 644 sys_reg(3, 7, 15, 15, 7), CGT_HCR_TIDCP), 645 SR_TRAP(SYS_ACTLR_EL1, CGT_HCR_TACR), 646 SR_TRAP(SYS_DC_ISW, CGT_HCR_TSW), 647 SR_TRAP(SYS_DC_CSW, CGT_HCR_TSW), 648 SR_TRAP(SYS_DC_CISW, CGT_HCR_TSW), 649 SR_TRAP(SYS_DC_IGSW, CGT_HCR_TSW), 650 SR_TRAP(SYS_DC_IGDSW, CGT_HCR_TSW), 651 SR_TRAP(SYS_DC_CGSW, CGT_HCR_TSW), 652 SR_TRAP(SYS_DC_CGDSW, CGT_HCR_TSW), 653 SR_TRAP(SYS_DC_CIGSW, CGT_HCR_TSW), 654 SR_TRAP(SYS_DC_CIGDSW, CGT_HCR_TSW), 655 SR_TRAP(SYS_DC_CIVAC, CGT_HCR_TPC), 656 SR_TRAP(SYS_DC_CVAC, CGT_HCR_TPC), 657 SR_TRAP(SYS_DC_CVAP, CGT_HCR_TPC), 658 SR_TRAP(SYS_DC_CVADP, CGT_HCR_TPC), 659 SR_TRAP(SYS_DC_IVAC, CGT_HCR_TPC), 660 SR_TRAP(SYS_DC_CIGVAC, CGT_HCR_TPC), 661 SR_TRAP(SYS_DC_CIGDVAC, CGT_HCR_TPC), 662 SR_TRAP(SYS_DC_IGVAC, CGT_HCR_TPC), 663 SR_TRAP(SYS_DC_IGDVAC, CGT_HCR_TPC), 664 SR_TRAP(SYS_DC_CGVAC, CGT_HCR_TPC), 665 SR_TRAP(SYS_DC_CGDVAC, CGT_HCR_TPC), 666 SR_TRAP(SYS_DC_CGVAP, CGT_HCR_TPC), 667 SR_TRAP(SYS_DC_CGDVAP, CGT_HCR_TPC), 668 SR_TRAP(SYS_DC_CGVADP, CGT_HCR_TPC), 669 SR_TRAP(SYS_DC_CGDVADP, CGT_HCR_TPC), 670 SR_TRAP(SYS_IC_IVAU, CGT_HCR_TPU_TOCU), 671 SR_TRAP(SYS_IC_IALLU, CGT_HCR_TPU_TOCU), 672 SR_TRAP(SYS_IC_IALLUIS, CGT_HCR_TPU_TICAB), 673 SR_TRAP(SYS_DC_CVAU, CGT_HCR_TPU_TOCU), 674 SR_TRAP(OP_TLBI_RVAE1, CGT_HCR_TTLB), 675 SR_TRAP(OP_TLBI_RVAAE1, CGT_HCR_TTLB), 676 SR_TRAP(OP_TLBI_RVALE1, CGT_HCR_TTLB), 677 SR_TRAP(OP_TLBI_RVAALE1, CGT_HCR_TTLB), 678 SR_TRAP(OP_TLBI_VMALLE1, CGT_HCR_TTLB), 679 SR_TRAP(OP_TLBI_VAE1, CGT_HCR_TTLB), 680 SR_TRAP(OP_TLBI_ASIDE1, CGT_HCR_TTLB), 681 SR_TRAP(OP_TLBI_VAAE1, CGT_HCR_TTLB), 682 SR_TRAP(OP_TLBI_VALE1, CGT_HCR_TTLB), 683 SR_TRAP(OP_TLBI_VAALE1, CGT_HCR_TTLB), 684 SR_TRAP(OP_TLBI_RVAE1NXS, CGT_HCR_TTLB), 685 SR_TRAP(OP_TLBI_RVAAE1NXS, CGT_HCR_TTLB), 686 SR_TRAP(OP_TLBI_RVALE1NXS, CGT_HCR_TTLB), 687 SR_TRAP(OP_TLBI_RVAALE1NXS, CGT_HCR_TTLB), 688 SR_TRAP(OP_TLBI_VMALLE1NXS, CGT_HCR_TTLB), 689 SR_TRAP(OP_TLBI_VAE1NXS, CGT_HCR_TTLB), 690 SR_TRAP(OP_TLBI_ASIDE1NXS, CGT_HCR_TTLB), 691 SR_TRAP(OP_TLBI_VAAE1NXS, CGT_HCR_TTLB), 692 SR_TRAP(OP_TLBI_VALE1NXS, CGT_HCR_TTLB), 693 SR_TRAP(OP_TLBI_VAALE1NXS, CGT_HCR_TTLB), 694 SR_TRAP(OP_TLBI_RVAE1IS, CGT_HCR_TTLB_TTLBIS), 695 SR_TRAP(OP_TLBI_RVAAE1IS, CGT_HCR_TTLB_TTLBIS), 696 SR_TRAP(OP_TLBI_RVALE1IS, CGT_HCR_TTLB_TTLBIS), 697 SR_TRAP(OP_TLBI_RVAALE1IS, CGT_HCR_TTLB_TTLBIS), 698 SR_TRAP(OP_TLBI_VMALLE1IS, CGT_HCR_TTLB_TTLBIS), 699 SR_TRAP(OP_TLBI_VAE1IS, CGT_HCR_TTLB_TTLBIS), 700 SR_TRAP(OP_TLBI_ASIDE1IS, CGT_HCR_TTLB_TTLBIS), 701 SR_TRAP(OP_TLBI_VAAE1IS, CGT_HCR_TTLB_TTLBIS), 702 SR_TRAP(OP_TLBI_VALE1IS, CGT_HCR_TTLB_TTLBIS), 703 SR_TRAP(OP_TLBI_VAALE1IS, CGT_HCR_TTLB_TTLBIS), 704 SR_TRAP(OP_TLBI_RVAE1ISNXS, CGT_HCR_TTLB_TTLBIS), 705 SR_TRAP(OP_TLBI_RVAAE1ISNXS, CGT_HCR_TTLB_TTLBIS), 706 SR_TRAP(OP_TLBI_RVALE1ISNXS, CGT_HCR_TTLB_TTLBIS), 707 SR_TRAP(OP_TLBI_RVAALE1ISNXS, CGT_HCR_TTLB_TTLBIS), 708 SR_TRAP(OP_TLBI_VMALLE1ISNXS, CGT_HCR_TTLB_TTLBIS), 709 SR_TRAP(OP_TLBI_VAE1ISNXS, CGT_HCR_TTLB_TTLBIS), 710 SR_TRAP(OP_TLBI_ASIDE1ISNXS, CGT_HCR_TTLB_TTLBIS), 711 SR_TRAP(OP_TLBI_VAAE1ISNXS, CGT_HCR_TTLB_TTLBIS), 712 SR_TRAP(OP_TLBI_VALE1ISNXS, CGT_HCR_TTLB_TTLBIS), 713 SR_TRAP(OP_TLBI_VAALE1ISNXS, CGT_HCR_TTLB_TTLBIS), 714 SR_TRAP(OP_TLBI_VMALLE1OS, CGT_HCR_TTLB_TTLBOS), 715 SR_TRAP(OP_TLBI_VAE1OS, CGT_HCR_TTLB_TTLBOS), 716 SR_TRAP(OP_TLBI_ASIDE1OS, CGT_HCR_TTLB_TTLBOS), 717 SR_TRAP(OP_TLBI_VAAE1OS, CGT_HCR_TTLB_TTLBOS), 718 SR_TRAP(OP_TLBI_VALE1OS, CGT_HCR_TTLB_TTLBOS), 719 SR_TRAP(OP_TLBI_VAALE1OS, CGT_HCR_TTLB_TTLBOS), 720 SR_TRAP(OP_TLBI_RVAE1OS, CGT_HCR_TTLB_TTLBOS), 721 SR_TRAP(OP_TLBI_RVAAE1OS, CGT_HCR_TTLB_TTLBOS), 722 SR_TRAP(OP_TLBI_RVALE1OS, CGT_HCR_TTLB_TTLBOS), 723 SR_TRAP(OP_TLBI_RVAALE1OS, CGT_HCR_TTLB_TTLBOS), 724 SR_TRAP(OP_TLBI_VMALLE1OSNXS, CGT_HCR_TTLB_TTLBOS), 725 SR_TRAP(OP_TLBI_VAE1OSNXS, CGT_HCR_TTLB_TTLBOS), 726 SR_TRAP(OP_TLBI_ASIDE1OSNXS, CGT_HCR_TTLB_TTLBOS), 727 SR_TRAP(OP_TLBI_VAAE1OSNXS, CGT_HCR_TTLB_TTLBOS), 728 SR_TRAP(OP_TLBI_VALE1OSNXS, CGT_HCR_TTLB_TTLBOS), 729 SR_TRAP(OP_TLBI_VAALE1OSNXS, CGT_HCR_TTLB_TTLBOS), 730 SR_TRAP(OP_TLBI_RVAE1OSNXS, CGT_HCR_TTLB_TTLBOS), 731 SR_TRAP(OP_TLBI_RVAAE1OSNXS, CGT_HCR_TTLB_TTLBOS), 732 SR_TRAP(OP_TLBI_RVALE1OSNXS, CGT_HCR_TTLB_TTLBOS), 733 SR_TRAP(OP_TLBI_RVAALE1OSNXS, CGT_HCR_TTLB_TTLBOS), 734 SR_TRAP(SYS_SCTLR_EL1, CGT_HCR_TVM_TRVM), 735 SR_TRAP(SYS_TTBR0_EL1, CGT_HCR_TVM_TRVM), 736 SR_TRAP(SYS_TTBR1_EL1, CGT_HCR_TVM_TRVM), 737 SR_TRAP(SYS_TCR_EL1, CGT_HCR_TVM_TRVM), 738 SR_TRAP(SYS_ESR_EL1, CGT_HCR_TVM_TRVM), 739 SR_TRAP(SYS_FAR_EL1, CGT_HCR_TVM_TRVM), 740 SR_TRAP(SYS_AFSR0_EL1, CGT_HCR_TVM_TRVM), 741 SR_TRAP(SYS_AFSR1_EL1, CGT_HCR_TVM_TRVM), 742 SR_TRAP(SYS_MAIR_EL1, CGT_HCR_TVM_TRVM), 743 SR_TRAP(SYS_AMAIR_EL1, CGT_HCR_TVM_TRVM), 744 SR_TRAP(SYS_CONTEXTIDR_EL1, CGT_HCR_TVM_TRVM), 745 SR_TRAP(SYS_PIR_EL1, CGT_HCR_TVM_TRVM), 746 SR_TRAP(SYS_PIRE0_EL1, CGT_HCR_TVM_TRVM), 747 SR_TRAP(SYS_POR_EL0, CGT_HCR_TVM_TRVM), 748 SR_TRAP(SYS_POR_EL1, CGT_HCR_TVM_TRVM), 749 SR_TRAP(SYS_TCR2_EL1, CGT_HCR_TVM_TRVM_HCRX_TCR2En), 750 SR_TRAP(SYS_DC_ZVA, CGT_HCR_TDZ), 751 SR_TRAP(SYS_DC_GVA, CGT_HCR_TDZ), 752 SR_TRAP(SYS_DC_GZVA, CGT_HCR_TDZ), 753 SR_TRAP(SYS_LORSA_EL1, CGT_HCR_TLOR), 754 SR_TRAP(SYS_LOREA_EL1, CGT_HCR_TLOR), 755 SR_TRAP(SYS_LORN_EL1, CGT_HCR_TLOR), 756 SR_TRAP(SYS_LORC_EL1, CGT_HCR_TLOR), 757 SR_TRAP(SYS_LORID_EL1, CGT_HCR_TLOR), 758 SR_TRAP(SYS_ERRIDR_EL1, CGT_HCR_TERR), 759 SR_TRAP(SYS_ERRSELR_EL1, CGT_HCR_TERR), 760 SR_TRAP(SYS_ERXADDR_EL1, CGT_HCR_TERR), 761 SR_TRAP(SYS_ERXCTLR_EL1, CGT_HCR_TERR), 762 SR_TRAP(SYS_ERXFR_EL1, CGT_HCR_TERR), 763 SR_TRAP(SYS_ERXMISC0_EL1, CGT_HCR_TERR), 764 SR_TRAP(SYS_ERXMISC1_EL1, CGT_HCR_TERR), 765 SR_TRAP(SYS_ERXMISC2_EL1, CGT_HCR_TERR), 766 SR_TRAP(SYS_ERXMISC3_EL1, CGT_HCR_TERR), 767 SR_TRAP(SYS_ERXSTATUS_EL1, CGT_HCR_TERR), 768 SR_TRAP(SYS_APIAKEYLO_EL1, CGT_HCR_APK), 769 SR_TRAP(SYS_APIAKEYHI_EL1, CGT_HCR_APK), 770 SR_TRAP(SYS_APIBKEYLO_EL1, CGT_HCR_APK), 771 SR_TRAP(SYS_APIBKEYHI_EL1, CGT_HCR_APK), 772 SR_TRAP(SYS_APDAKEYLO_EL1, CGT_HCR_APK), 773 SR_TRAP(SYS_APDAKEYHI_EL1, CGT_HCR_APK), 774 SR_TRAP(SYS_APDBKEYLO_EL1, CGT_HCR_APK), 775 SR_TRAP(SYS_APDBKEYHI_EL1, CGT_HCR_APK), 776 SR_TRAP(SYS_APGAKEYLO_EL1, CGT_HCR_APK), 777 SR_TRAP(SYS_APGAKEYHI_EL1, CGT_HCR_APK), 778 /* All _EL2 registers */ 779 SR_TRAP(SYS_BRBCR_EL2, CGT_HCR_NV), 780 SR_TRAP(SYS_VPIDR_EL2, CGT_HCR_NV), 781 SR_TRAP(SYS_VMPIDR_EL2, CGT_HCR_NV), 782 SR_TRAP(SYS_SCTLR_EL2, CGT_HCR_NV), 783 SR_TRAP(SYS_ACTLR_EL2, CGT_HCR_NV), 784 SR_TRAP(SYS_SCTLR2_EL2, CGT_HCR_NV), 785 SR_RANGE_TRAP(SYS_HCR_EL2, 786 SYS_HCRX_EL2, CGT_HCR_NV), 787 SR_TRAP(SYS_SMPRIMAP_EL2, CGT_HCR_NV), 788 SR_TRAP(SYS_SMCR_EL2, CGT_HCR_NV), 789 SR_RANGE_TRAP(SYS_TTBR0_EL2, 790 SYS_TCR2_EL2, CGT_HCR_NV), 791 SR_TRAP(SYS_VTTBR_EL2, CGT_HCR_NV), 792 SR_TRAP(SYS_VTCR_EL2, CGT_HCR_NV), 793 SR_TRAP(SYS_VNCR_EL2, CGT_HCR_NV), 794 SR_RANGE_TRAP(SYS_HDFGRTR_EL2, 795 SYS_HAFGRTR_EL2, CGT_HCR_NV), 796 /* Skip the SP_EL1 encoding... */ 797 SR_TRAP(SYS_SPSR_EL2, CGT_HCR_NV), 798 SR_TRAP(SYS_ELR_EL2, CGT_HCR_NV), 799 /* Skip SPSR_irq, SPSR_abt, SPSR_und, SPSR_fiq */ 800 SR_TRAP(SYS_AFSR0_EL2, CGT_HCR_NV), 801 SR_TRAP(SYS_AFSR1_EL2, CGT_HCR_NV), 802 SR_TRAP(SYS_ESR_EL2, CGT_HCR_NV), 803 SR_TRAP(SYS_VSESR_EL2, CGT_HCR_NV), 804 SR_TRAP(SYS_TFSR_EL2, CGT_HCR_NV), 805 SR_TRAP(SYS_FAR_EL2, CGT_HCR_NV), 806 SR_TRAP(SYS_HPFAR_EL2, CGT_HCR_NV), 807 SR_TRAP(SYS_PMSCR_EL2, CGT_HCR_NV), 808 SR_TRAP(SYS_MAIR_EL2, CGT_HCR_NV), 809 SR_TRAP(SYS_AMAIR_EL2, CGT_HCR_NV), 810 SR_TRAP(SYS_MPAMHCR_EL2, CGT_HCR_NV), 811 SR_TRAP(SYS_MPAMVPMV_EL2, CGT_HCR_NV), 812 SR_TRAP(SYS_MPAM2_EL2, CGT_HCR_NV), 813 SR_RANGE_TRAP(SYS_MPAMVPM0_EL2, 814 SYS_MPAMVPM7_EL2, CGT_HCR_NV), 815 /* 816 * Note that the spec. describes a group of MEC registers 817 * whose access should not trap, therefore skip the following: 818 * MECID_A0_EL2, MECID_A1_EL2, MECID_P0_EL2, 819 * MECID_P1_EL2, MECIDR_EL2, VMECID_A_EL2, 820 * VMECID_P_EL2. 821 */ 822 SR_RANGE_TRAP(SYS_VBAR_EL2, 823 SYS_RMR_EL2, CGT_HCR_NV), 824 SR_TRAP(SYS_VDISR_EL2, CGT_HCR_NV), 825 /* ICH_AP0R<m>_EL2 */ 826 SR_RANGE_TRAP(SYS_ICH_AP0R0_EL2, 827 SYS_ICH_AP0R3_EL2, CGT_HCR_NV), 828 /* ICH_AP1R<m>_EL2 */ 829 SR_RANGE_TRAP(SYS_ICH_AP1R0_EL2, 830 SYS_ICH_AP1R3_EL2, CGT_HCR_NV), 831 SR_TRAP(SYS_ICC_SRE_EL2, CGT_HCR_NV), 832 SR_RANGE_TRAP(SYS_ICH_HCR_EL2, 833 SYS_ICH_EISR_EL2, CGT_HCR_NV), 834 SR_TRAP(SYS_ICH_ELRSR_EL2, CGT_HCR_NV), 835 SR_TRAP(SYS_ICH_VMCR_EL2, CGT_HCR_NV), 836 /* ICH_LR<m>_EL2 */ 837 SR_RANGE_TRAP(SYS_ICH_LR0_EL2, 838 SYS_ICH_LR15_EL2, CGT_HCR_NV), 839 SR_TRAP(SYS_CONTEXTIDR_EL2, CGT_HCR_NV), 840 SR_TRAP(SYS_TPIDR_EL2, CGT_HCR_NV), 841 SR_TRAP(SYS_SCXTNUM_EL2, CGT_HCR_NV), 842 /* AMEVCNTVOFF0<n>_EL2, AMEVCNTVOFF1<n>_EL2 */ 843 SR_RANGE_TRAP(SYS_AMEVCNTVOFF0n_EL2(0), 844 SYS_AMEVCNTVOFF1n_EL2(15), CGT_HCR_NV), 845 /* CNT*_EL2 */ 846 SR_TRAP(SYS_CNTVOFF_EL2, CGT_HCR_NV), 847 SR_TRAP(SYS_CNTPOFF_EL2, CGT_HCR_NV), 848 SR_TRAP(SYS_CNTHCTL_EL2, CGT_HCR_NV), 849 SR_RANGE_TRAP(SYS_CNTHP_TVAL_EL2, 850 SYS_CNTHP_CVAL_EL2, CGT_HCR_NV), 851 SR_RANGE_TRAP(SYS_CNTHV_TVAL_EL2, 852 SYS_CNTHV_CVAL_EL2, CGT_HCR_NV), 853 /* All _EL02, _EL12 registers */ 854 SR_RANGE_TRAP(sys_reg(3, 5, 0, 0, 0), 855 sys_reg(3, 5, 10, 15, 7), CGT_HCR_NV), 856 SR_RANGE_TRAP(sys_reg(3, 5, 12, 0, 0), 857 sys_reg(3, 5, 14, 15, 7), CGT_HCR_NV), 858 SR_TRAP(OP_AT_S1E2R, CGT_HCR_NV), 859 SR_TRAP(OP_AT_S1E2W, CGT_HCR_NV), 860 SR_TRAP(OP_AT_S12E1R, CGT_HCR_NV), 861 SR_TRAP(OP_AT_S12E1W, CGT_HCR_NV), 862 SR_TRAP(OP_AT_S12E0R, CGT_HCR_NV), 863 SR_TRAP(OP_AT_S12E0W, CGT_HCR_NV), 864 SR_TRAP(OP_AT_S1E2A, CGT_HCR_NV), 865 SR_TRAP(OP_TLBI_IPAS2E1, CGT_HCR_NV), 866 SR_TRAP(OP_TLBI_RIPAS2E1, CGT_HCR_NV), 867 SR_TRAP(OP_TLBI_IPAS2LE1, CGT_HCR_NV), 868 SR_TRAP(OP_TLBI_RIPAS2LE1, CGT_HCR_NV), 869 SR_TRAP(OP_TLBI_RVAE2, CGT_HCR_NV), 870 SR_TRAP(OP_TLBI_RVALE2, CGT_HCR_NV), 871 SR_TRAP(OP_TLBI_ALLE2, CGT_HCR_NV), 872 SR_TRAP(OP_TLBI_VAE2, CGT_HCR_NV), 873 SR_TRAP(OP_TLBI_ALLE1, CGT_HCR_NV), 874 SR_TRAP(OP_TLBI_VALE2, CGT_HCR_NV), 875 SR_TRAP(OP_TLBI_VMALLS12E1, CGT_HCR_NV), 876 SR_TRAP(OP_TLBI_IPAS2E1NXS, CGT_HCR_NV), 877 SR_TRAP(OP_TLBI_RIPAS2E1NXS, CGT_HCR_NV), 878 SR_TRAP(OP_TLBI_IPAS2LE1NXS, CGT_HCR_NV), 879 SR_TRAP(OP_TLBI_RIPAS2LE1NXS, CGT_HCR_NV), 880 SR_TRAP(OP_TLBI_RVAE2NXS, CGT_HCR_NV), 881 SR_TRAP(OP_TLBI_RVALE2NXS, CGT_HCR_NV), 882 SR_TRAP(OP_TLBI_ALLE2NXS, CGT_HCR_NV), 883 SR_TRAP(OP_TLBI_VAE2NXS, CGT_HCR_NV), 884 SR_TRAP(OP_TLBI_ALLE1NXS, CGT_HCR_NV), 885 SR_TRAP(OP_TLBI_VALE2NXS, CGT_HCR_NV), 886 SR_TRAP(OP_TLBI_VMALLS12E1NXS, CGT_HCR_NV), 887 SR_TRAP(OP_TLBI_IPAS2E1IS, CGT_HCR_NV), 888 SR_TRAP(OP_TLBI_RIPAS2E1IS, CGT_HCR_NV), 889 SR_TRAP(OP_TLBI_IPAS2LE1IS, CGT_HCR_NV), 890 SR_TRAP(OP_TLBI_RIPAS2LE1IS, CGT_HCR_NV), 891 SR_TRAP(OP_TLBI_RVAE2IS, CGT_HCR_NV), 892 SR_TRAP(OP_TLBI_RVALE2IS, CGT_HCR_NV), 893 SR_TRAP(OP_TLBI_ALLE2IS, CGT_HCR_NV), 894 SR_TRAP(OP_TLBI_VAE2IS, CGT_HCR_NV), 895 SR_TRAP(OP_TLBI_ALLE1IS, CGT_HCR_NV), 896 SR_TRAP(OP_TLBI_VALE2IS, CGT_HCR_NV), 897 SR_TRAP(OP_TLBI_VMALLS12E1IS, CGT_HCR_NV), 898 SR_TRAP(OP_TLBI_IPAS2E1ISNXS, CGT_HCR_NV), 899 SR_TRAP(OP_TLBI_RIPAS2E1ISNXS, CGT_HCR_NV), 900 SR_TRAP(OP_TLBI_IPAS2LE1ISNXS, CGT_HCR_NV), 901 SR_TRAP(OP_TLBI_RIPAS2LE1ISNXS, CGT_HCR_NV), 902 SR_TRAP(OP_TLBI_RVAE2ISNXS, CGT_HCR_NV), 903 SR_TRAP(OP_TLBI_RVALE2ISNXS, CGT_HCR_NV), 904 SR_TRAP(OP_TLBI_ALLE2ISNXS, CGT_HCR_NV), 905 SR_TRAP(OP_TLBI_VAE2ISNXS, CGT_HCR_NV), 906 SR_TRAP(OP_TLBI_ALLE1ISNXS, CGT_HCR_NV), 907 SR_TRAP(OP_TLBI_VALE2ISNXS, CGT_HCR_NV), 908 SR_TRAP(OP_TLBI_VMALLS12E1ISNXS,CGT_HCR_NV), 909 SR_TRAP(OP_TLBI_ALLE2OS, CGT_HCR_NV), 910 SR_TRAP(OP_TLBI_VAE2OS, CGT_HCR_NV), 911 SR_TRAP(OP_TLBI_ALLE1OS, CGT_HCR_NV), 912 SR_TRAP(OP_TLBI_VALE2OS, CGT_HCR_NV), 913 SR_TRAP(OP_TLBI_VMALLS12E1OS, CGT_HCR_NV), 914 SR_TRAP(OP_TLBI_IPAS2E1OS, CGT_HCR_NV), 915 SR_TRAP(OP_TLBI_RIPAS2E1OS, CGT_HCR_NV), 916 SR_TRAP(OP_TLBI_IPAS2LE1OS, CGT_HCR_NV), 917 SR_TRAP(OP_TLBI_RIPAS2LE1OS, CGT_HCR_NV), 918 SR_TRAP(OP_TLBI_RVAE2OS, CGT_HCR_NV), 919 SR_TRAP(OP_TLBI_RVALE2OS, CGT_HCR_NV), 920 SR_TRAP(OP_TLBI_ALLE2OSNXS, CGT_HCR_NV), 921 SR_TRAP(OP_TLBI_VAE2OSNXS, CGT_HCR_NV), 922 SR_TRAP(OP_TLBI_ALLE1OSNXS, CGT_HCR_NV), 923 SR_TRAP(OP_TLBI_VALE2OSNXS, CGT_HCR_NV), 924 SR_TRAP(OP_TLBI_VMALLS12E1OSNXS,CGT_HCR_NV), 925 SR_TRAP(OP_TLBI_IPAS2E1OSNXS, CGT_HCR_NV), 926 SR_TRAP(OP_TLBI_RIPAS2E1OSNXS, CGT_HCR_NV), 927 SR_TRAP(OP_TLBI_IPAS2LE1OSNXS, CGT_HCR_NV), 928 SR_TRAP(OP_TLBI_RIPAS2LE1OSNXS, CGT_HCR_NV), 929 SR_TRAP(OP_TLBI_RVAE2OSNXS, CGT_HCR_NV), 930 SR_TRAP(OP_TLBI_RVALE2OSNXS, CGT_HCR_NV), 931 SR_TRAP(OP_CPP_RCTX, CGT_HCR_NV), 932 SR_TRAP(OP_DVP_RCTX, CGT_HCR_NV), 933 SR_TRAP(OP_CFP_RCTX, CGT_HCR_NV), 934 SR_TRAP(SYS_SP_EL1, CGT_HCR_NV_nNV2), 935 SR_TRAP(SYS_VBAR_EL1, CGT_HCR_NV1_nNV2), 936 SR_TRAP(SYS_ELR_EL1, CGT_HCR_NV1_nNV2), 937 SR_TRAP(SYS_SPSR_EL1, CGT_HCR_NV1_nNV2), 938 SR_TRAP(SYS_SCXTNUM_EL1, CGT_HCR_NV1_nNV2_ENSCXT), 939 SR_TRAP(SYS_SCXTNUM_EL0, CGT_HCR_ENSCXT), 940 SR_TRAP(OP_AT_S1E1R, CGT_HCR_AT), 941 SR_TRAP(OP_AT_S1E1W, CGT_HCR_AT), 942 SR_TRAP(OP_AT_S1E0R, CGT_HCR_AT), 943 SR_TRAP(OP_AT_S1E0W, CGT_HCR_AT), 944 SR_TRAP(OP_AT_S1E1RP, CGT_HCR_AT), 945 SR_TRAP(OP_AT_S1E1WP, CGT_HCR_AT), 946 SR_TRAP(OP_AT_S1E1A, CGT_HCR_AT), 947 SR_TRAP(SYS_ERXPFGF_EL1, CGT_HCR_nFIEN), 948 SR_TRAP(SYS_ERXPFGCTL_EL1, CGT_HCR_nFIEN), 949 SR_TRAP(SYS_ERXPFGCDN_EL1, CGT_HCR_nFIEN), 950 SR_TRAP(SYS_PMCR_EL0, CGT_MDCR_TPM_TPMCR), 951 SR_TRAP(SYS_PMCNTENSET_EL0, CGT_MDCR_TPM), 952 SR_TRAP(SYS_PMCNTENCLR_EL0, CGT_MDCR_TPM), 953 SR_TRAP(SYS_PMOVSSET_EL0, CGT_MDCR_TPM), 954 SR_TRAP(SYS_PMOVSCLR_EL0, CGT_MDCR_TPM), 955 SR_TRAP(SYS_PMCEID0_EL0, CGT_MDCR_TPM), 956 SR_TRAP(SYS_PMCEID1_EL0, CGT_MDCR_TPM), 957 SR_TRAP(SYS_PMXEVTYPER_EL0, CGT_MDCR_TPM_HPMN), 958 SR_TRAP(SYS_PMSWINC_EL0, CGT_MDCR_TPM), 959 SR_TRAP(SYS_PMSELR_EL0, CGT_MDCR_TPM), 960 SR_TRAP(SYS_PMXEVCNTR_EL0, CGT_MDCR_TPM_HPMN), 961 SR_TRAP(SYS_PMCCNTR_EL0, CGT_MDCR_TPM), 962 SR_TRAP(SYS_PMUSERENR_EL0, CGT_MDCR_TPM), 963 SR_TRAP(SYS_PMINTENSET_EL1, CGT_MDCR_TPM), 964 SR_TRAP(SYS_PMINTENCLR_EL1, CGT_MDCR_TPM), 965 SR_TRAP(SYS_PMMIR_EL1, CGT_MDCR_TPM), 966 SR_TRAP(SYS_PMEVCNTRn_EL0(0), CGT_MDCR_TPM_HPMN), 967 SR_TRAP(SYS_PMEVCNTRn_EL0(1), CGT_MDCR_TPM_HPMN), 968 SR_TRAP(SYS_PMEVCNTRn_EL0(2), CGT_MDCR_TPM_HPMN), 969 SR_TRAP(SYS_PMEVCNTRn_EL0(3), CGT_MDCR_TPM_HPMN), 970 SR_TRAP(SYS_PMEVCNTRn_EL0(4), CGT_MDCR_TPM_HPMN), 971 SR_TRAP(SYS_PMEVCNTRn_EL0(5), CGT_MDCR_TPM_HPMN), 972 SR_TRAP(SYS_PMEVCNTRn_EL0(6), CGT_MDCR_TPM_HPMN), 973 SR_TRAP(SYS_PMEVCNTRn_EL0(7), CGT_MDCR_TPM_HPMN), 974 SR_TRAP(SYS_PMEVCNTRn_EL0(8), CGT_MDCR_TPM_HPMN), 975 SR_TRAP(SYS_PMEVCNTRn_EL0(9), CGT_MDCR_TPM_HPMN), 976 SR_TRAP(SYS_PMEVCNTRn_EL0(10), CGT_MDCR_TPM_HPMN), 977 SR_TRAP(SYS_PMEVCNTRn_EL0(11), CGT_MDCR_TPM_HPMN), 978 SR_TRAP(SYS_PMEVCNTRn_EL0(12), CGT_MDCR_TPM_HPMN), 979 SR_TRAP(SYS_PMEVCNTRn_EL0(13), CGT_MDCR_TPM_HPMN), 980 SR_TRAP(SYS_PMEVCNTRn_EL0(14), CGT_MDCR_TPM_HPMN), 981 SR_TRAP(SYS_PMEVCNTRn_EL0(15), CGT_MDCR_TPM_HPMN), 982 SR_TRAP(SYS_PMEVCNTRn_EL0(16), CGT_MDCR_TPM_HPMN), 983 SR_TRAP(SYS_PMEVCNTRn_EL0(17), CGT_MDCR_TPM_HPMN), 984 SR_TRAP(SYS_PMEVCNTRn_EL0(18), CGT_MDCR_TPM_HPMN), 985 SR_TRAP(SYS_PMEVCNTRn_EL0(19), CGT_MDCR_TPM_HPMN), 986 SR_TRAP(SYS_PMEVCNTRn_EL0(20), CGT_MDCR_TPM_HPMN), 987 SR_TRAP(SYS_PMEVCNTRn_EL0(21), CGT_MDCR_TPM_HPMN), 988 SR_TRAP(SYS_PMEVCNTRn_EL0(22), CGT_MDCR_TPM_HPMN), 989 SR_TRAP(SYS_PMEVCNTRn_EL0(23), CGT_MDCR_TPM_HPMN), 990 SR_TRAP(SYS_PMEVCNTRn_EL0(24), CGT_MDCR_TPM_HPMN), 991 SR_TRAP(SYS_PMEVCNTRn_EL0(25), CGT_MDCR_TPM_HPMN), 992 SR_TRAP(SYS_PMEVCNTRn_EL0(26), CGT_MDCR_TPM_HPMN), 993 SR_TRAP(SYS_PMEVCNTRn_EL0(27), CGT_MDCR_TPM_HPMN), 994 SR_TRAP(SYS_PMEVCNTRn_EL0(28), CGT_MDCR_TPM_HPMN), 995 SR_TRAP(SYS_PMEVCNTRn_EL0(29), CGT_MDCR_TPM_HPMN), 996 SR_TRAP(SYS_PMEVCNTRn_EL0(30), CGT_MDCR_TPM_HPMN), 997 SR_TRAP(SYS_PMEVTYPERn_EL0(0), CGT_MDCR_TPM_HPMN), 998 SR_TRAP(SYS_PMEVTYPERn_EL0(1), CGT_MDCR_TPM_HPMN), 999 SR_TRAP(SYS_PMEVTYPERn_EL0(2), CGT_MDCR_TPM_HPMN), 1000 SR_TRAP(SYS_PMEVTYPERn_EL0(3), CGT_MDCR_TPM_HPMN), 1001 SR_TRAP(SYS_PMEVTYPERn_EL0(4), CGT_MDCR_TPM_HPMN), 1002 SR_TRAP(SYS_PMEVTYPERn_EL0(5), CGT_MDCR_TPM_HPMN), 1003 SR_TRAP(SYS_PMEVTYPERn_EL0(6), CGT_MDCR_TPM_HPMN), 1004 SR_TRAP(SYS_PMEVTYPERn_EL0(7), CGT_MDCR_TPM_HPMN), 1005 SR_TRAP(SYS_PMEVTYPERn_EL0(8), CGT_MDCR_TPM_HPMN), 1006 SR_TRAP(SYS_PMEVTYPERn_EL0(9), CGT_MDCR_TPM_HPMN), 1007 SR_TRAP(SYS_PMEVTYPERn_EL0(10), CGT_MDCR_TPM_HPMN), 1008 SR_TRAP(SYS_PMEVTYPERn_EL0(11), CGT_MDCR_TPM_HPMN), 1009 SR_TRAP(SYS_PMEVTYPERn_EL0(12), CGT_MDCR_TPM_HPMN), 1010 SR_TRAP(SYS_PMEVTYPERn_EL0(13), CGT_MDCR_TPM_HPMN), 1011 SR_TRAP(SYS_PMEVTYPERn_EL0(14), CGT_MDCR_TPM_HPMN), 1012 SR_TRAP(SYS_PMEVTYPERn_EL0(15), CGT_MDCR_TPM_HPMN), 1013 SR_TRAP(SYS_PMEVTYPERn_EL0(16), CGT_MDCR_TPM_HPMN), 1014 SR_TRAP(SYS_PMEVTYPERn_EL0(17), CGT_MDCR_TPM_HPMN), 1015 SR_TRAP(SYS_PMEVTYPERn_EL0(18), CGT_MDCR_TPM_HPMN), 1016 SR_TRAP(SYS_PMEVTYPERn_EL0(19), CGT_MDCR_TPM_HPMN), 1017 SR_TRAP(SYS_PMEVTYPERn_EL0(20), CGT_MDCR_TPM_HPMN), 1018 SR_TRAP(SYS_PMEVTYPERn_EL0(21), CGT_MDCR_TPM_HPMN), 1019 SR_TRAP(SYS_PMEVTYPERn_EL0(22), CGT_MDCR_TPM_HPMN), 1020 SR_TRAP(SYS_PMEVTYPERn_EL0(23), CGT_MDCR_TPM_HPMN), 1021 SR_TRAP(SYS_PMEVTYPERn_EL0(24), CGT_MDCR_TPM_HPMN), 1022 SR_TRAP(SYS_PMEVTYPERn_EL0(25), CGT_MDCR_TPM_HPMN), 1023 SR_TRAP(SYS_PMEVTYPERn_EL0(26), CGT_MDCR_TPM_HPMN), 1024 SR_TRAP(SYS_PMEVTYPERn_EL0(27), CGT_MDCR_TPM_HPMN), 1025 SR_TRAP(SYS_PMEVTYPERn_EL0(28), CGT_MDCR_TPM_HPMN), 1026 SR_TRAP(SYS_PMEVTYPERn_EL0(29), CGT_MDCR_TPM_HPMN), 1027 SR_TRAP(SYS_PMEVTYPERn_EL0(30), CGT_MDCR_TPM_HPMN), 1028 SR_TRAP(SYS_PMCCFILTR_EL0, CGT_MDCR_TPM), 1029 SR_TRAP(SYS_MDCCSR_EL0, CGT_MDCR_TDCC_TDE_TDA), 1030 SR_TRAP(SYS_MDCCINT_EL1, CGT_MDCR_TDCC_TDE_TDA), 1031 SR_TRAP(SYS_OSDTRRX_EL1, CGT_MDCR_TDCC_TDE_TDA), 1032 SR_TRAP(SYS_OSDTRTX_EL1, CGT_MDCR_TDCC_TDE_TDA), 1033 SR_TRAP(SYS_DBGDTR_EL0, CGT_MDCR_TDCC_TDE_TDA), 1034 /* 1035 * Also covers DBGDTRRX_EL0, which has the same encoding as 1036 * SYS_DBGDTRTX_EL0... 1037 */ 1038 SR_TRAP(SYS_DBGDTRTX_EL0, CGT_MDCR_TDCC_TDE_TDA), 1039 SR_TRAP(SYS_MDSCR_EL1, CGT_MDCR_TDE_TDA), 1040 SR_TRAP(SYS_OSECCR_EL1, CGT_MDCR_TDE_TDA), 1041 SR_TRAP(SYS_DBGBVRn_EL1(0), CGT_MDCR_TDE_TDA), 1042 SR_TRAP(SYS_DBGBVRn_EL1(1), CGT_MDCR_TDE_TDA), 1043 SR_TRAP(SYS_DBGBVRn_EL1(2), CGT_MDCR_TDE_TDA), 1044 SR_TRAP(SYS_DBGBVRn_EL1(3), CGT_MDCR_TDE_TDA), 1045 SR_TRAP(SYS_DBGBVRn_EL1(4), CGT_MDCR_TDE_TDA), 1046 SR_TRAP(SYS_DBGBVRn_EL1(5), CGT_MDCR_TDE_TDA), 1047 SR_TRAP(SYS_DBGBVRn_EL1(6), CGT_MDCR_TDE_TDA), 1048 SR_TRAP(SYS_DBGBVRn_EL1(7), CGT_MDCR_TDE_TDA), 1049 SR_TRAP(SYS_DBGBVRn_EL1(8), CGT_MDCR_TDE_TDA), 1050 SR_TRAP(SYS_DBGBVRn_EL1(9), CGT_MDCR_TDE_TDA), 1051 SR_TRAP(SYS_DBGBVRn_EL1(10), CGT_MDCR_TDE_TDA), 1052 SR_TRAP(SYS_DBGBVRn_EL1(11), CGT_MDCR_TDE_TDA), 1053 SR_TRAP(SYS_DBGBVRn_EL1(12), CGT_MDCR_TDE_TDA), 1054 SR_TRAP(SYS_DBGBVRn_EL1(13), CGT_MDCR_TDE_TDA), 1055 SR_TRAP(SYS_DBGBVRn_EL1(14), CGT_MDCR_TDE_TDA), 1056 SR_TRAP(SYS_DBGBVRn_EL1(15), CGT_MDCR_TDE_TDA), 1057 SR_TRAP(SYS_DBGBCRn_EL1(0), CGT_MDCR_TDE_TDA), 1058 SR_TRAP(SYS_DBGBCRn_EL1(1), CGT_MDCR_TDE_TDA), 1059 SR_TRAP(SYS_DBGBCRn_EL1(2), CGT_MDCR_TDE_TDA), 1060 SR_TRAP(SYS_DBGBCRn_EL1(3), CGT_MDCR_TDE_TDA), 1061 SR_TRAP(SYS_DBGBCRn_EL1(4), CGT_MDCR_TDE_TDA), 1062 SR_TRAP(SYS_DBGBCRn_EL1(5), CGT_MDCR_TDE_TDA), 1063 SR_TRAP(SYS_DBGBCRn_EL1(6), CGT_MDCR_TDE_TDA), 1064 SR_TRAP(SYS_DBGBCRn_EL1(7), CGT_MDCR_TDE_TDA), 1065 SR_TRAP(SYS_DBGBCRn_EL1(8), CGT_MDCR_TDE_TDA), 1066 SR_TRAP(SYS_DBGBCRn_EL1(9), CGT_MDCR_TDE_TDA), 1067 SR_TRAP(SYS_DBGBCRn_EL1(10), CGT_MDCR_TDE_TDA), 1068 SR_TRAP(SYS_DBGBCRn_EL1(11), CGT_MDCR_TDE_TDA), 1069 SR_TRAP(SYS_DBGBCRn_EL1(12), CGT_MDCR_TDE_TDA), 1070 SR_TRAP(SYS_DBGBCRn_EL1(13), CGT_MDCR_TDE_TDA), 1071 SR_TRAP(SYS_DBGBCRn_EL1(14), CGT_MDCR_TDE_TDA), 1072 SR_TRAP(SYS_DBGBCRn_EL1(15), CGT_MDCR_TDE_TDA), 1073 SR_TRAP(SYS_DBGWVRn_EL1(0), CGT_MDCR_TDE_TDA), 1074 SR_TRAP(SYS_DBGWVRn_EL1(1), CGT_MDCR_TDE_TDA), 1075 SR_TRAP(SYS_DBGWVRn_EL1(2), CGT_MDCR_TDE_TDA), 1076 SR_TRAP(SYS_DBGWVRn_EL1(3), CGT_MDCR_TDE_TDA), 1077 SR_TRAP(SYS_DBGWVRn_EL1(4), CGT_MDCR_TDE_TDA), 1078 SR_TRAP(SYS_DBGWVRn_EL1(5), CGT_MDCR_TDE_TDA), 1079 SR_TRAP(SYS_DBGWVRn_EL1(6), CGT_MDCR_TDE_TDA), 1080 SR_TRAP(SYS_DBGWVRn_EL1(7), CGT_MDCR_TDE_TDA), 1081 SR_TRAP(SYS_DBGWVRn_EL1(8), CGT_MDCR_TDE_TDA), 1082 SR_TRAP(SYS_DBGWVRn_EL1(9), CGT_MDCR_TDE_TDA), 1083 SR_TRAP(SYS_DBGWVRn_EL1(10), CGT_MDCR_TDE_TDA), 1084 SR_TRAP(SYS_DBGWVRn_EL1(11), CGT_MDCR_TDE_TDA), 1085 SR_TRAP(SYS_DBGWVRn_EL1(12), CGT_MDCR_TDE_TDA), 1086 SR_TRAP(SYS_DBGWVRn_EL1(13), CGT_MDCR_TDE_TDA), 1087 SR_TRAP(SYS_DBGWVRn_EL1(14), CGT_MDCR_TDE_TDA), 1088 SR_TRAP(SYS_DBGWVRn_EL1(15), CGT_MDCR_TDE_TDA), 1089 SR_TRAP(SYS_DBGWCRn_EL1(0), CGT_MDCR_TDE_TDA), 1090 SR_TRAP(SYS_DBGWCRn_EL1(1), CGT_MDCR_TDE_TDA), 1091 SR_TRAP(SYS_DBGWCRn_EL1(2), CGT_MDCR_TDE_TDA), 1092 SR_TRAP(SYS_DBGWCRn_EL1(3), CGT_MDCR_TDE_TDA), 1093 SR_TRAP(SYS_DBGWCRn_EL1(4), CGT_MDCR_TDE_TDA), 1094 SR_TRAP(SYS_DBGWCRn_EL1(5), CGT_MDCR_TDE_TDA), 1095 SR_TRAP(SYS_DBGWCRn_EL1(6), CGT_MDCR_TDE_TDA), 1096 SR_TRAP(SYS_DBGWCRn_EL1(7), CGT_MDCR_TDE_TDA), 1097 SR_TRAP(SYS_DBGWCRn_EL1(8), CGT_MDCR_TDE_TDA), 1098 SR_TRAP(SYS_DBGWCRn_EL1(9), CGT_MDCR_TDE_TDA), 1099 SR_TRAP(SYS_DBGWCRn_EL1(10), CGT_MDCR_TDE_TDA), 1100 SR_TRAP(SYS_DBGWCRn_EL1(11), CGT_MDCR_TDE_TDA), 1101 SR_TRAP(SYS_DBGWCRn_EL1(12), CGT_MDCR_TDE_TDA), 1102 SR_TRAP(SYS_DBGWCRn_EL1(13), CGT_MDCR_TDE_TDA), 1103 SR_TRAP(SYS_DBGWCRn_EL1(14), CGT_MDCR_TDE_TDA), 1104 SR_TRAP(SYS_DBGCLAIMSET_EL1, CGT_MDCR_TDE_TDA), 1105 SR_TRAP(SYS_DBGCLAIMCLR_EL1, CGT_MDCR_TDE_TDA), 1106 SR_TRAP(SYS_DBGAUTHSTATUS_EL1, CGT_MDCR_TDE_TDA), 1107 SR_TRAP(SYS_OSLAR_EL1, CGT_MDCR_TDE_TDOSA), 1108 SR_TRAP(SYS_OSLSR_EL1, CGT_MDCR_TDE_TDOSA), 1109 SR_TRAP(SYS_OSDLR_EL1, CGT_MDCR_TDE_TDOSA), 1110 SR_TRAP(SYS_DBGPRCR_EL1, CGT_MDCR_TDE_TDOSA), 1111 SR_TRAP(SYS_MDRAR_EL1, CGT_MDCR_TDE_TDRA), 1112 SR_TRAP(SYS_PMBLIMITR_EL1, CGT_MDCR_E2PB), 1113 SR_TRAP(SYS_PMBPTR_EL1, CGT_MDCR_E2PB), 1114 SR_TRAP(SYS_PMBSR_EL1, CGT_MDCR_E2PB), 1115 SR_TRAP(SYS_PMSCR_EL1, CGT_MDCR_TPMS), 1116 SR_TRAP(SYS_PMSEVFR_EL1, CGT_MDCR_TPMS), 1117 SR_TRAP(SYS_PMSFCR_EL1, CGT_MDCR_TPMS), 1118 SR_TRAP(SYS_PMSICR_EL1, CGT_MDCR_TPMS), 1119 SR_TRAP(SYS_PMSIDR_EL1, CGT_MDCR_TPMS), 1120 SR_TRAP(SYS_PMSIRR_EL1, CGT_MDCR_TPMS), 1121 SR_TRAP(SYS_PMSLATFR_EL1, CGT_MDCR_TPMS), 1122 SR_TRAP(SYS_PMSNEVFR_EL1, CGT_MDCR_TPMS), 1123 SR_TRAP(SYS_TRFCR_EL1, CGT_MDCR_TTRF), 1124 SR_TRAP(SYS_TRBBASER_EL1, CGT_MDCR_E2TB), 1125 SR_TRAP(SYS_TRBLIMITR_EL1, CGT_MDCR_E2TB), 1126 SR_TRAP(SYS_TRBMAR_EL1, CGT_MDCR_E2TB), 1127 SR_TRAP(SYS_TRBPTR_EL1, CGT_MDCR_E2TB), 1128 SR_TRAP(SYS_TRBSR_EL1, CGT_MDCR_E2TB), 1129 SR_TRAP(SYS_TRBTRG_EL1, CGT_MDCR_E2TB), 1130 SR_TRAP(SYS_CPACR_EL1, CGT_CPTR_TCPAC), 1131 SR_TRAP(SYS_AMUSERENR_EL0, CGT_CPTR_TAM), 1132 SR_TRAP(SYS_AMCFGR_EL0, CGT_CPTR_TAM), 1133 SR_TRAP(SYS_AMCGCR_EL0, CGT_CPTR_TAM), 1134 SR_TRAP(SYS_AMCNTENCLR0_EL0, CGT_CPTR_TAM), 1135 SR_TRAP(SYS_AMCNTENCLR1_EL0, CGT_CPTR_TAM), 1136 SR_TRAP(SYS_AMCNTENSET0_EL0, CGT_CPTR_TAM), 1137 SR_TRAP(SYS_AMCNTENSET1_EL0, CGT_CPTR_TAM), 1138 SR_TRAP(SYS_AMCR_EL0, CGT_CPTR_TAM), 1139 SR_TRAP(SYS_AMEVCNTR0_EL0(0), CGT_CPTR_TAM), 1140 SR_TRAP(SYS_AMEVCNTR0_EL0(1), CGT_CPTR_TAM), 1141 SR_TRAP(SYS_AMEVCNTR0_EL0(2), CGT_CPTR_TAM), 1142 SR_TRAP(SYS_AMEVCNTR0_EL0(3), CGT_CPTR_TAM), 1143 SR_TRAP(SYS_AMEVCNTR1_EL0(0), CGT_CPTR_TAM), 1144 SR_TRAP(SYS_AMEVCNTR1_EL0(1), CGT_CPTR_TAM), 1145 SR_TRAP(SYS_AMEVCNTR1_EL0(2), CGT_CPTR_TAM), 1146 SR_TRAP(SYS_AMEVCNTR1_EL0(3), CGT_CPTR_TAM), 1147 SR_TRAP(SYS_AMEVCNTR1_EL0(4), CGT_CPTR_TAM), 1148 SR_TRAP(SYS_AMEVCNTR1_EL0(5), CGT_CPTR_TAM), 1149 SR_TRAP(SYS_AMEVCNTR1_EL0(6), CGT_CPTR_TAM), 1150 SR_TRAP(SYS_AMEVCNTR1_EL0(7), CGT_CPTR_TAM), 1151 SR_TRAP(SYS_AMEVCNTR1_EL0(8), CGT_CPTR_TAM), 1152 SR_TRAP(SYS_AMEVCNTR1_EL0(9), CGT_CPTR_TAM), 1153 SR_TRAP(SYS_AMEVCNTR1_EL0(10), CGT_CPTR_TAM), 1154 SR_TRAP(SYS_AMEVCNTR1_EL0(11), CGT_CPTR_TAM), 1155 SR_TRAP(SYS_AMEVCNTR1_EL0(12), CGT_CPTR_TAM), 1156 SR_TRAP(SYS_AMEVCNTR1_EL0(13), CGT_CPTR_TAM), 1157 SR_TRAP(SYS_AMEVCNTR1_EL0(14), CGT_CPTR_TAM), 1158 SR_TRAP(SYS_AMEVCNTR1_EL0(15), CGT_CPTR_TAM), 1159 SR_TRAP(SYS_AMEVTYPER0_EL0(0), CGT_CPTR_TAM), 1160 SR_TRAP(SYS_AMEVTYPER0_EL0(1), CGT_CPTR_TAM), 1161 SR_TRAP(SYS_AMEVTYPER0_EL0(2), CGT_CPTR_TAM), 1162 SR_TRAP(SYS_AMEVTYPER0_EL0(3), CGT_CPTR_TAM), 1163 SR_TRAP(SYS_AMEVTYPER1_EL0(0), CGT_CPTR_TAM), 1164 SR_TRAP(SYS_AMEVTYPER1_EL0(1), CGT_CPTR_TAM), 1165 SR_TRAP(SYS_AMEVTYPER1_EL0(2), CGT_CPTR_TAM), 1166 SR_TRAP(SYS_AMEVTYPER1_EL0(3), CGT_CPTR_TAM), 1167 SR_TRAP(SYS_AMEVTYPER1_EL0(4), CGT_CPTR_TAM), 1168 SR_TRAP(SYS_AMEVTYPER1_EL0(5), CGT_CPTR_TAM), 1169 SR_TRAP(SYS_AMEVTYPER1_EL0(6), CGT_CPTR_TAM), 1170 SR_TRAP(SYS_AMEVTYPER1_EL0(7), CGT_CPTR_TAM), 1171 SR_TRAP(SYS_AMEVTYPER1_EL0(8), CGT_CPTR_TAM), 1172 SR_TRAP(SYS_AMEVTYPER1_EL0(9), CGT_CPTR_TAM), 1173 SR_TRAP(SYS_AMEVTYPER1_EL0(10), CGT_CPTR_TAM), 1174 SR_TRAP(SYS_AMEVTYPER1_EL0(11), CGT_CPTR_TAM), 1175 SR_TRAP(SYS_AMEVTYPER1_EL0(12), CGT_CPTR_TAM), 1176 SR_TRAP(SYS_AMEVTYPER1_EL0(13), CGT_CPTR_TAM), 1177 SR_TRAP(SYS_AMEVTYPER1_EL0(14), CGT_CPTR_TAM), 1178 SR_TRAP(SYS_AMEVTYPER1_EL0(15), CGT_CPTR_TAM), 1179 /* op0=2, op1=1, and CRn<0b1000 */ 1180 SR_RANGE_TRAP(sys_reg(2, 1, 0, 0, 0), 1181 sys_reg(2, 1, 7, 15, 7), CGT_CPTR_TTA), 1182 SR_TRAP(SYS_CNTP_TVAL_EL0, CGT_CNTHCTL_EL1PTEN), 1183 SR_TRAP(SYS_CNTP_CVAL_EL0, CGT_CNTHCTL_EL1PTEN), 1184 SR_TRAP(SYS_CNTP_CTL_EL0, CGT_CNTHCTL_EL1PTEN), 1185 SR_TRAP(SYS_CNTPCT_EL0, CGT_CNTHCTL_EL1PCTEN), 1186 SR_TRAP(SYS_CNTPCTSS_EL0, CGT_CNTHCTL_EL1PCTEN), 1187 SR_TRAP(SYS_FPMR, CGT_HCRX_EnFPM), 1188 /* 1189 * IMPDEF choice: 1190 * We treat ICC_SRE_EL2.{SRE,Enable) and ICV_SRE_EL1.SRE as 1191 * RAO/WI. We therefore never consider ICC_SRE_EL2.Enable for 1192 * ICC_SRE_EL1 access, and always handle it locally. 1193 */ 1194 SR_TRAP(SYS_ICC_AP0R0_EL1, CGT_ICH_HCR_TALL0), 1195 SR_TRAP(SYS_ICC_AP0R1_EL1, CGT_ICH_HCR_TALL0), 1196 SR_TRAP(SYS_ICC_AP0R2_EL1, CGT_ICH_HCR_TALL0), 1197 SR_TRAP(SYS_ICC_AP0R3_EL1, CGT_ICH_HCR_TALL0), 1198 SR_TRAP(SYS_ICC_AP1R0_EL1, CGT_ICH_HCR_TALL1), 1199 SR_TRAP(SYS_ICC_AP1R1_EL1, CGT_ICH_HCR_TALL1), 1200 SR_TRAP(SYS_ICC_AP1R2_EL1, CGT_ICH_HCR_TALL1), 1201 SR_TRAP(SYS_ICC_AP1R3_EL1, CGT_ICH_HCR_TALL1), 1202 SR_TRAP(SYS_ICC_BPR0_EL1, CGT_ICH_HCR_TALL0), 1203 SR_TRAP(SYS_ICC_BPR1_EL1, CGT_ICH_HCR_TALL1), 1204 SR_TRAP(SYS_ICC_CTLR_EL1, CGT_ICH_HCR_TC), 1205 SR_TRAP(SYS_ICC_DIR_EL1, CGT_ICH_HCR_TC_TDIR), 1206 SR_TRAP(SYS_ICC_EOIR0_EL1, CGT_ICH_HCR_TALL0), 1207 SR_TRAP(SYS_ICC_EOIR1_EL1, CGT_ICH_HCR_TALL1), 1208 SR_TRAP(SYS_ICC_HPPIR0_EL1, CGT_ICH_HCR_TALL0), 1209 SR_TRAP(SYS_ICC_HPPIR1_EL1, CGT_ICH_HCR_TALL1), 1210 SR_TRAP(SYS_ICC_IAR0_EL1, CGT_ICH_HCR_TALL0), 1211 SR_TRAP(SYS_ICC_IAR1_EL1, CGT_ICH_HCR_TALL1), 1212 SR_TRAP(SYS_ICC_IGRPEN0_EL1, CGT_ICH_HCR_TALL0), 1213 SR_TRAP(SYS_ICC_IGRPEN1_EL1, CGT_ICH_HCR_TALL1), 1214 SR_TRAP(SYS_ICC_PMR_EL1, CGT_ICH_HCR_TC), 1215 SR_TRAP(SYS_ICC_RPR_EL1, CGT_ICH_HCR_TC), 1216 }; 1217 1218 static DEFINE_XARRAY(sr_forward_xa); 1219 1220 enum fg_filter_id { 1221 __NO_FGF__, 1222 HCRX_FGTnXS, 1223 1224 /* Must be last */ 1225 __NR_FG_FILTER_IDS__ 1226 }; 1227 1228 #define SR_FGF(sr, g, b, p, f) \ 1229 { \ 1230 .encoding = sr, \ 1231 .end = sr, \ 1232 .tc = { \ 1233 .fgt = g ## _GROUP, \ 1234 .bit = g ## _EL2_ ## b ## _SHIFT, \ 1235 .pol = p, \ 1236 .fgf = f, \ 1237 }, \ 1238 .line = __LINE__, \ 1239 } 1240 1241 #define SR_FGT(sr, g, b, p) SR_FGF(sr, g, b, p, __NO_FGF__) 1242 1243 static const struct encoding_to_trap_config encoding_to_fgt[] __initconst = { 1244 /* HFGRTR_EL2, HFGWTR_EL2 */ 1245 SR_FGT(SYS_AMAIR2_EL1, HFGxTR, nAMAIR2_EL1, 0), 1246 SR_FGT(SYS_MAIR2_EL1, HFGxTR, nMAIR2_EL1, 0), 1247 SR_FGT(SYS_S2POR_EL1, HFGxTR, nS2POR_EL1, 0), 1248 SR_FGT(SYS_POR_EL1, HFGxTR, nPOR_EL1, 0), 1249 SR_FGT(SYS_POR_EL0, HFGxTR, nPOR_EL0, 0), 1250 SR_FGT(SYS_PIR_EL1, HFGxTR, nPIR_EL1, 0), 1251 SR_FGT(SYS_PIRE0_EL1, HFGxTR, nPIRE0_EL1, 0), 1252 SR_FGT(SYS_RCWMASK_EL1, HFGxTR, nRCWMASK_EL1, 0), 1253 SR_FGT(SYS_TPIDR2_EL0, HFGxTR, nTPIDR2_EL0, 0), 1254 SR_FGT(SYS_SMPRI_EL1, HFGxTR, nSMPRI_EL1, 0), 1255 SR_FGT(SYS_GCSCR_EL1, HFGxTR, nGCS_EL1, 0), 1256 SR_FGT(SYS_GCSPR_EL1, HFGxTR, nGCS_EL1, 0), 1257 SR_FGT(SYS_GCSCRE0_EL1, HFGxTR, nGCS_EL0, 0), 1258 SR_FGT(SYS_GCSPR_EL0, HFGxTR, nGCS_EL0, 0), 1259 SR_FGT(SYS_ACCDATA_EL1, HFGxTR, nACCDATA_EL1, 0), 1260 SR_FGT(SYS_ERXADDR_EL1, HFGxTR, ERXADDR_EL1, 1), 1261 SR_FGT(SYS_ERXPFGCDN_EL1, HFGxTR, ERXPFGCDN_EL1, 1), 1262 SR_FGT(SYS_ERXPFGCTL_EL1, HFGxTR, ERXPFGCTL_EL1, 1), 1263 SR_FGT(SYS_ERXPFGF_EL1, HFGxTR, ERXPFGF_EL1, 1), 1264 SR_FGT(SYS_ERXMISC0_EL1, HFGxTR, ERXMISCn_EL1, 1), 1265 SR_FGT(SYS_ERXMISC1_EL1, HFGxTR, ERXMISCn_EL1, 1), 1266 SR_FGT(SYS_ERXMISC2_EL1, HFGxTR, ERXMISCn_EL1, 1), 1267 SR_FGT(SYS_ERXMISC3_EL1, HFGxTR, ERXMISCn_EL1, 1), 1268 SR_FGT(SYS_ERXSTATUS_EL1, HFGxTR, ERXSTATUS_EL1, 1), 1269 SR_FGT(SYS_ERXCTLR_EL1, HFGxTR, ERXCTLR_EL1, 1), 1270 SR_FGT(SYS_ERXFR_EL1, HFGxTR, ERXFR_EL1, 1), 1271 SR_FGT(SYS_ERRSELR_EL1, HFGxTR, ERRSELR_EL1, 1), 1272 SR_FGT(SYS_ERRIDR_EL1, HFGxTR, ERRIDR_EL1, 1), 1273 SR_FGT(SYS_ICC_IGRPEN0_EL1, HFGxTR, ICC_IGRPENn_EL1, 1), 1274 SR_FGT(SYS_ICC_IGRPEN1_EL1, HFGxTR, ICC_IGRPENn_EL1, 1), 1275 SR_FGT(SYS_VBAR_EL1, HFGxTR, VBAR_EL1, 1), 1276 SR_FGT(SYS_TTBR1_EL1, HFGxTR, TTBR1_EL1, 1), 1277 SR_FGT(SYS_TTBR0_EL1, HFGxTR, TTBR0_EL1, 1), 1278 SR_FGT(SYS_TPIDR_EL0, HFGxTR, TPIDR_EL0, 1), 1279 SR_FGT(SYS_TPIDRRO_EL0, HFGxTR, TPIDRRO_EL0, 1), 1280 SR_FGT(SYS_TPIDR_EL1, HFGxTR, TPIDR_EL1, 1), 1281 SR_FGT(SYS_TCR_EL1, HFGxTR, TCR_EL1, 1), 1282 SR_FGT(SYS_TCR2_EL1, HFGxTR, TCR_EL1, 1), 1283 SR_FGT(SYS_SCXTNUM_EL0, HFGxTR, SCXTNUM_EL0, 1), 1284 SR_FGT(SYS_SCXTNUM_EL1, HFGxTR, SCXTNUM_EL1, 1), 1285 SR_FGT(SYS_SCTLR_EL1, HFGxTR, SCTLR_EL1, 1), 1286 SR_FGT(SYS_REVIDR_EL1, HFGxTR, REVIDR_EL1, 1), 1287 SR_FGT(SYS_PAR_EL1, HFGxTR, PAR_EL1, 1), 1288 SR_FGT(SYS_MPIDR_EL1, HFGxTR, MPIDR_EL1, 1), 1289 SR_FGT(SYS_MIDR_EL1, HFGxTR, MIDR_EL1, 1), 1290 SR_FGT(SYS_MAIR_EL1, HFGxTR, MAIR_EL1, 1), 1291 SR_FGT(SYS_LORSA_EL1, HFGxTR, LORSA_EL1, 1), 1292 SR_FGT(SYS_LORN_EL1, HFGxTR, LORN_EL1, 1), 1293 SR_FGT(SYS_LORID_EL1, HFGxTR, LORID_EL1, 1), 1294 SR_FGT(SYS_LOREA_EL1, HFGxTR, LOREA_EL1, 1), 1295 SR_FGT(SYS_LORC_EL1, HFGxTR, LORC_EL1, 1), 1296 SR_FGT(SYS_ISR_EL1, HFGxTR, ISR_EL1, 1), 1297 SR_FGT(SYS_FAR_EL1, HFGxTR, FAR_EL1, 1), 1298 SR_FGT(SYS_ESR_EL1, HFGxTR, ESR_EL1, 1), 1299 SR_FGT(SYS_DCZID_EL0, HFGxTR, DCZID_EL0, 1), 1300 SR_FGT(SYS_CTR_EL0, HFGxTR, CTR_EL0, 1), 1301 SR_FGT(SYS_CSSELR_EL1, HFGxTR, CSSELR_EL1, 1), 1302 SR_FGT(SYS_CPACR_EL1, HFGxTR, CPACR_EL1, 1), 1303 SR_FGT(SYS_CONTEXTIDR_EL1, HFGxTR, CONTEXTIDR_EL1, 1), 1304 SR_FGT(SYS_CLIDR_EL1, HFGxTR, CLIDR_EL1, 1), 1305 SR_FGT(SYS_CCSIDR_EL1, HFGxTR, CCSIDR_EL1, 1), 1306 SR_FGT(SYS_APIBKEYLO_EL1, HFGxTR, APIBKey, 1), 1307 SR_FGT(SYS_APIBKEYHI_EL1, HFGxTR, APIBKey, 1), 1308 SR_FGT(SYS_APIAKEYLO_EL1, HFGxTR, APIAKey, 1), 1309 SR_FGT(SYS_APIAKEYHI_EL1, HFGxTR, APIAKey, 1), 1310 SR_FGT(SYS_APGAKEYLO_EL1, HFGxTR, APGAKey, 1), 1311 SR_FGT(SYS_APGAKEYHI_EL1, HFGxTR, APGAKey, 1), 1312 SR_FGT(SYS_APDBKEYLO_EL1, HFGxTR, APDBKey, 1), 1313 SR_FGT(SYS_APDBKEYHI_EL1, HFGxTR, APDBKey, 1), 1314 SR_FGT(SYS_APDAKEYLO_EL1, HFGxTR, APDAKey, 1), 1315 SR_FGT(SYS_APDAKEYHI_EL1, HFGxTR, APDAKey, 1), 1316 SR_FGT(SYS_AMAIR_EL1, HFGxTR, AMAIR_EL1, 1), 1317 SR_FGT(SYS_AIDR_EL1, HFGxTR, AIDR_EL1, 1), 1318 SR_FGT(SYS_AFSR1_EL1, HFGxTR, AFSR1_EL1, 1), 1319 SR_FGT(SYS_AFSR0_EL1, HFGxTR, AFSR0_EL1, 1), 1320 /* HFGITR_EL2 */ 1321 SR_FGT(OP_AT_S1E1A, HFGITR, ATS1E1A, 1), 1322 SR_FGT(OP_COSP_RCTX, HFGITR, COSPRCTX, 1), 1323 SR_FGT(OP_GCSPUSHX, HFGITR, nGCSEPP, 0), 1324 SR_FGT(OP_GCSPOPX, HFGITR, nGCSEPP, 0), 1325 SR_FGT(OP_GCSPUSHM, HFGITR, nGCSPUSHM_EL1, 0), 1326 SR_FGT(OP_BRB_IALL, HFGITR, nBRBIALL, 0), 1327 SR_FGT(OP_BRB_INJ, HFGITR, nBRBINJ, 0), 1328 SR_FGT(SYS_DC_CVAC, HFGITR, DCCVAC, 1), 1329 SR_FGT(SYS_DC_CGVAC, HFGITR, DCCVAC, 1), 1330 SR_FGT(SYS_DC_CGDVAC, HFGITR, DCCVAC, 1), 1331 SR_FGT(OP_CPP_RCTX, HFGITR, CPPRCTX, 1), 1332 SR_FGT(OP_DVP_RCTX, HFGITR, DVPRCTX, 1), 1333 SR_FGT(OP_CFP_RCTX, HFGITR, CFPRCTX, 1), 1334 SR_FGT(OP_TLBI_VAALE1, HFGITR, TLBIVAALE1, 1), 1335 SR_FGT(OP_TLBI_VALE1, HFGITR, TLBIVALE1, 1), 1336 SR_FGT(OP_TLBI_VAAE1, HFGITR, TLBIVAAE1, 1), 1337 SR_FGT(OP_TLBI_ASIDE1, HFGITR, TLBIASIDE1, 1), 1338 SR_FGT(OP_TLBI_VAE1, HFGITR, TLBIVAE1, 1), 1339 SR_FGT(OP_TLBI_VMALLE1, HFGITR, TLBIVMALLE1, 1), 1340 SR_FGT(OP_TLBI_RVAALE1, HFGITR, TLBIRVAALE1, 1), 1341 SR_FGT(OP_TLBI_RVALE1, HFGITR, TLBIRVALE1, 1), 1342 SR_FGT(OP_TLBI_RVAAE1, HFGITR, TLBIRVAAE1, 1), 1343 SR_FGT(OP_TLBI_RVAE1, HFGITR, TLBIRVAE1, 1), 1344 SR_FGT(OP_TLBI_RVAALE1IS, HFGITR, TLBIRVAALE1IS, 1), 1345 SR_FGT(OP_TLBI_RVALE1IS, HFGITR, TLBIRVALE1IS, 1), 1346 SR_FGT(OP_TLBI_RVAAE1IS, HFGITR, TLBIRVAAE1IS, 1), 1347 SR_FGT(OP_TLBI_RVAE1IS, HFGITR, TLBIRVAE1IS, 1), 1348 SR_FGT(OP_TLBI_VAALE1IS, HFGITR, TLBIVAALE1IS, 1), 1349 SR_FGT(OP_TLBI_VALE1IS, HFGITR, TLBIVALE1IS, 1), 1350 SR_FGT(OP_TLBI_VAAE1IS, HFGITR, TLBIVAAE1IS, 1), 1351 SR_FGT(OP_TLBI_ASIDE1IS, HFGITR, TLBIASIDE1IS, 1), 1352 SR_FGT(OP_TLBI_VAE1IS, HFGITR, TLBIVAE1IS, 1), 1353 SR_FGT(OP_TLBI_VMALLE1IS, HFGITR, TLBIVMALLE1IS, 1), 1354 SR_FGT(OP_TLBI_RVAALE1OS, HFGITR, TLBIRVAALE1OS, 1), 1355 SR_FGT(OP_TLBI_RVALE1OS, HFGITR, TLBIRVALE1OS, 1), 1356 SR_FGT(OP_TLBI_RVAAE1OS, HFGITR, TLBIRVAAE1OS, 1), 1357 SR_FGT(OP_TLBI_RVAE1OS, HFGITR, TLBIRVAE1OS, 1), 1358 SR_FGT(OP_TLBI_VAALE1OS, HFGITR, TLBIVAALE1OS, 1), 1359 SR_FGT(OP_TLBI_VALE1OS, HFGITR, TLBIVALE1OS, 1), 1360 SR_FGT(OP_TLBI_VAAE1OS, HFGITR, TLBIVAAE1OS, 1), 1361 SR_FGT(OP_TLBI_ASIDE1OS, HFGITR, TLBIASIDE1OS, 1), 1362 SR_FGT(OP_TLBI_VAE1OS, HFGITR, TLBIVAE1OS, 1), 1363 SR_FGT(OP_TLBI_VMALLE1OS, HFGITR, TLBIVMALLE1OS, 1), 1364 /* nXS variants must be checked against HCRX_EL2.FGTnXS */ 1365 SR_FGF(OP_TLBI_VAALE1NXS, HFGITR, TLBIVAALE1, 1, HCRX_FGTnXS), 1366 SR_FGF(OP_TLBI_VALE1NXS, HFGITR, TLBIVALE1, 1, HCRX_FGTnXS), 1367 SR_FGF(OP_TLBI_VAAE1NXS, HFGITR, TLBIVAAE1, 1, HCRX_FGTnXS), 1368 SR_FGF(OP_TLBI_ASIDE1NXS, HFGITR, TLBIASIDE1, 1, HCRX_FGTnXS), 1369 SR_FGF(OP_TLBI_VAE1NXS, HFGITR, TLBIVAE1, 1, HCRX_FGTnXS), 1370 SR_FGF(OP_TLBI_VMALLE1NXS, HFGITR, TLBIVMALLE1, 1, HCRX_FGTnXS), 1371 SR_FGF(OP_TLBI_RVAALE1NXS, HFGITR, TLBIRVAALE1, 1, HCRX_FGTnXS), 1372 SR_FGF(OP_TLBI_RVALE1NXS, HFGITR, TLBIRVALE1, 1, HCRX_FGTnXS), 1373 SR_FGF(OP_TLBI_RVAAE1NXS, HFGITR, TLBIRVAAE1, 1, HCRX_FGTnXS), 1374 SR_FGF(OP_TLBI_RVAE1NXS, HFGITR, TLBIRVAE1, 1, HCRX_FGTnXS), 1375 SR_FGF(OP_TLBI_RVAALE1ISNXS, HFGITR, TLBIRVAALE1IS, 1, HCRX_FGTnXS), 1376 SR_FGF(OP_TLBI_RVALE1ISNXS, HFGITR, TLBIRVALE1IS, 1, HCRX_FGTnXS), 1377 SR_FGF(OP_TLBI_RVAAE1ISNXS, HFGITR, TLBIRVAAE1IS, 1, HCRX_FGTnXS), 1378 SR_FGF(OP_TLBI_RVAE1ISNXS, HFGITR, TLBIRVAE1IS, 1, HCRX_FGTnXS), 1379 SR_FGF(OP_TLBI_VAALE1ISNXS, HFGITR, TLBIVAALE1IS, 1, HCRX_FGTnXS), 1380 SR_FGF(OP_TLBI_VALE1ISNXS, HFGITR, TLBIVALE1IS, 1, HCRX_FGTnXS), 1381 SR_FGF(OP_TLBI_VAAE1ISNXS, HFGITR, TLBIVAAE1IS, 1, HCRX_FGTnXS), 1382 SR_FGF(OP_TLBI_ASIDE1ISNXS, HFGITR, TLBIASIDE1IS, 1, HCRX_FGTnXS), 1383 SR_FGF(OP_TLBI_VAE1ISNXS, HFGITR, TLBIVAE1IS, 1, HCRX_FGTnXS), 1384 SR_FGF(OP_TLBI_VMALLE1ISNXS, HFGITR, TLBIVMALLE1IS, 1, HCRX_FGTnXS), 1385 SR_FGF(OP_TLBI_RVAALE1OSNXS, HFGITR, TLBIRVAALE1OS, 1, HCRX_FGTnXS), 1386 SR_FGF(OP_TLBI_RVALE1OSNXS, HFGITR, TLBIRVALE1OS, 1, HCRX_FGTnXS), 1387 SR_FGF(OP_TLBI_RVAAE1OSNXS, HFGITR, TLBIRVAAE1OS, 1, HCRX_FGTnXS), 1388 SR_FGF(OP_TLBI_RVAE1OSNXS, HFGITR, TLBIRVAE1OS, 1, HCRX_FGTnXS), 1389 SR_FGF(OP_TLBI_VAALE1OSNXS, HFGITR, TLBIVAALE1OS, 1, HCRX_FGTnXS), 1390 SR_FGF(OP_TLBI_VALE1OSNXS, HFGITR, TLBIVALE1OS, 1, HCRX_FGTnXS), 1391 SR_FGF(OP_TLBI_VAAE1OSNXS, HFGITR, TLBIVAAE1OS, 1, HCRX_FGTnXS), 1392 SR_FGF(OP_TLBI_ASIDE1OSNXS, HFGITR, TLBIASIDE1OS, 1, HCRX_FGTnXS), 1393 SR_FGF(OP_TLBI_VAE1OSNXS, HFGITR, TLBIVAE1OS, 1, HCRX_FGTnXS), 1394 SR_FGF(OP_TLBI_VMALLE1OSNXS, HFGITR, TLBIVMALLE1OS, 1, HCRX_FGTnXS), 1395 SR_FGT(OP_AT_S1E1WP, HFGITR, ATS1E1WP, 1), 1396 SR_FGT(OP_AT_S1E1RP, HFGITR, ATS1E1RP, 1), 1397 SR_FGT(OP_AT_S1E0W, HFGITR, ATS1E0W, 1), 1398 SR_FGT(OP_AT_S1E0R, HFGITR, ATS1E0R, 1), 1399 SR_FGT(OP_AT_S1E1W, HFGITR, ATS1E1W, 1), 1400 SR_FGT(OP_AT_S1E1R, HFGITR, ATS1E1R, 1), 1401 SR_FGT(SYS_DC_ZVA, HFGITR, DCZVA, 1), 1402 SR_FGT(SYS_DC_GVA, HFGITR, DCZVA, 1), 1403 SR_FGT(SYS_DC_GZVA, HFGITR, DCZVA, 1), 1404 SR_FGT(SYS_DC_CIVAC, HFGITR, DCCIVAC, 1), 1405 SR_FGT(SYS_DC_CIGVAC, HFGITR, DCCIVAC, 1), 1406 SR_FGT(SYS_DC_CIGDVAC, HFGITR, DCCIVAC, 1), 1407 SR_FGT(SYS_DC_CVADP, HFGITR, DCCVADP, 1), 1408 SR_FGT(SYS_DC_CGVADP, HFGITR, DCCVADP, 1), 1409 SR_FGT(SYS_DC_CGDVADP, HFGITR, DCCVADP, 1), 1410 SR_FGT(SYS_DC_CVAP, HFGITR, DCCVAP, 1), 1411 SR_FGT(SYS_DC_CGVAP, HFGITR, DCCVAP, 1), 1412 SR_FGT(SYS_DC_CGDVAP, HFGITR, DCCVAP, 1), 1413 SR_FGT(SYS_DC_CVAU, HFGITR, DCCVAU, 1), 1414 SR_FGT(SYS_DC_CISW, HFGITR, DCCISW, 1), 1415 SR_FGT(SYS_DC_CIGSW, HFGITR, DCCISW, 1), 1416 SR_FGT(SYS_DC_CIGDSW, HFGITR, DCCISW, 1), 1417 SR_FGT(SYS_DC_CSW, HFGITR, DCCSW, 1), 1418 SR_FGT(SYS_DC_CGSW, HFGITR, DCCSW, 1), 1419 SR_FGT(SYS_DC_CGDSW, HFGITR, DCCSW, 1), 1420 SR_FGT(SYS_DC_ISW, HFGITR, DCISW, 1), 1421 SR_FGT(SYS_DC_IGSW, HFGITR, DCISW, 1), 1422 SR_FGT(SYS_DC_IGDSW, HFGITR, DCISW, 1), 1423 SR_FGT(SYS_DC_IVAC, HFGITR, DCIVAC, 1), 1424 SR_FGT(SYS_DC_IGVAC, HFGITR, DCIVAC, 1), 1425 SR_FGT(SYS_DC_IGDVAC, HFGITR, DCIVAC, 1), 1426 SR_FGT(SYS_IC_IVAU, HFGITR, ICIVAU, 1), 1427 SR_FGT(SYS_IC_IALLU, HFGITR, ICIALLU, 1), 1428 SR_FGT(SYS_IC_IALLUIS, HFGITR, ICIALLUIS, 1), 1429 /* HDFGRTR_EL2 */ 1430 SR_FGT(SYS_PMBIDR_EL1, HDFGRTR, PMBIDR_EL1, 1), 1431 SR_FGT(SYS_PMSNEVFR_EL1, HDFGRTR, nPMSNEVFR_EL1, 0), 1432 SR_FGT(SYS_BRBINF_EL1(0), HDFGRTR, nBRBDATA, 0), 1433 SR_FGT(SYS_BRBINF_EL1(1), HDFGRTR, nBRBDATA, 0), 1434 SR_FGT(SYS_BRBINF_EL1(2), HDFGRTR, nBRBDATA, 0), 1435 SR_FGT(SYS_BRBINF_EL1(3), HDFGRTR, nBRBDATA, 0), 1436 SR_FGT(SYS_BRBINF_EL1(4), HDFGRTR, nBRBDATA, 0), 1437 SR_FGT(SYS_BRBINF_EL1(5), HDFGRTR, nBRBDATA, 0), 1438 SR_FGT(SYS_BRBINF_EL1(6), HDFGRTR, nBRBDATA, 0), 1439 SR_FGT(SYS_BRBINF_EL1(7), HDFGRTR, nBRBDATA, 0), 1440 SR_FGT(SYS_BRBINF_EL1(8), HDFGRTR, nBRBDATA, 0), 1441 SR_FGT(SYS_BRBINF_EL1(9), HDFGRTR, nBRBDATA, 0), 1442 SR_FGT(SYS_BRBINF_EL1(10), HDFGRTR, nBRBDATA, 0), 1443 SR_FGT(SYS_BRBINF_EL1(11), HDFGRTR, nBRBDATA, 0), 1444 SR_FGT(SYS_BRBINF_EL1(12), HDFGRTR, nBRBDATA, 0), 1445 SR_FGT(SYS_BRBINF_EL1(13), HDFGRTR, nBRBDATA, 0), 1446 SR_FGT(SYS_BRBINF_EL1(14), HDFGRTR, nBRBDATA, 0), 1447 SR_FGT(SYS_BRBINF_EL1(15), HDFGRTR, nBRBDATA, 0), 1448 SR_FGT(SYS_BRBINF_EL1(16), HDFGRTR, nBRBDATA, 0), 1449 SR_FGT(SYS_BRBINF_EL1(17), HDFGRTR, nBRBDATA, 0), 1450 SR_FGT(SYS_BRBINF_EL1(18), HDFGRTR, nBRBDATA, 0), 1451 SR_FGT(SYS_BRBINF_EL1(19), HDFGRTR, nBRBDATA, 0), 1452 SR_FGT(SYS_BRBINF_EL1(20), HDFGRTR, nBRBDATA, 0), 1453 SR_FGT(SYS_BRBINF_EL1(21), HDFGRTR, nBRBDATA, 0), 1454 SR_FGT(SYS_BRBINF_EL1(22), HDFGRTR, nBRBDATA, 0), 1455 SR_FGT(SYS_BRBINF_EL1(23), HDFGRTR, nBRBDATA, 0), 1456 SR_FGT(SYS_BRBINF_EL1(24), HDFGRTR, nBRBDATA, 0), 1457 SR_FGT(SYS_BRBINF_EL1(25), HDFGRTR, nBRBDATA, 0), 1458 SR_FGT(SYS_BRBINF_EL1(26), HDFGRTR, nBRBDATA, 0), 1459 SR_FGT(SYS_BRBINF_EL1(27), HDFGRTR, nBRBDATA, 0), 1460 SR_FGT(SYS_BRBINF_EL1(28), HDFGRTR, nBRBDATA, 0), 1461 SR_FGT(SYS_BRBINF_EL1(29), HDFGRTR, nBRBDATA, 0), 1462 SR_FGT(SYS_BRBINF_EL1(30), HDFGRTR, nBRBDATA, 0), 1463 SR_FGT(SYS_BRBINF_EL1(31), HDFGRTR, nBRBDATA, 0), 1464 SR_FGT(SYS_BRBINFINJ_EL1, HDFGRTR, nBRBDATA, 0), 1465 SR_FGT(SYS_BRBSRC_EL1(0), HDFGRTR, nBRBDATA, 0), 1466 SR_FGT(SYS_BRBSRC_EL1(1), HDFGRTR, nBRBDATA, 0), 1467 SR_FGT(SYS_BRBSRC_EL1(2), HDFGRTR, nBRBDATA, 0), 1468 SR_FGT(SYS_BRBSRC_EL1(3), HDFGRTR, nBRBDATA, 0), 1469 SR_FGT(SYS_BRBSRC_EL1(4), HDFGRTR, nBRBDATA, 0), 1470 SR_FGT(SYS_BRBSRC_EL1(5), HDFGRTR, nBRBDATA, 0), 1471 SR_FGT(SYS_BRBSRC_EL1(6), HDFGRTR, nBRBDATA, 0), 1472 SR_FGT(SYS_BRBSRC_EL1(7), HDFGRTR, nBRBDATA, 0), 1473 SR_FGT(SYS_BRBSRC_EL1(8), HDFGRTR, nBRBDATA, 0), 1474 SR_FGT(SYS_BRBSRC_EL1(9), HDFGRTR, nBRBDATA, 0), 1475 SR_FGT(SYS_BRBSRC_EL1(10), HDFGRTR, nBRBDATA, 0), 1476 SR_FGT(SYS_BRBSRC_EL1(11), HDFGRTR, nBRBDATA, 0), 1477 SR_FGT(SYS_BRBSRC_EL1(12), HDFGRTR, nBRBDATA, 0), 1478 SR_FGT(SYS_BRBSRC_EL1(13), HDFGRTR, nBRBDATA, 0), 1479 SR_FGT(SYS_BRBSRC_EL1(14), HDFGRTR, nBRBDATA, 0), 1480 SR_FGT(SYS_BRBSRC_EL1(15), HDFGRTR, nBRBDATA, 0), 1481 SR_FGT(SYS_BRBSRC_EL1(16), HDFGRTR, nBRBDATA, 0), 1482 SR_FGT(SYS_BRBSRC_EL1(17), HDFGRTR, nBRBDATA, 0), 1483 SR_FGT(SYS_BRBSRC_EL1(18), HDFGRTR, nBRBDATA, 0), 1484 SR_FGT(SYS_BRBSRC_EL1(19), HDFGRTR, nBRBDATA, 0), 1485 SR_FGT(SYS_BRBSRC_EL1(20), HDFGRTR, nBRBDATA, 0), 1486 SR_FGT(SYS_BRBSRC_EL1(21), HDFGRTR, nBRBDATA, 0), 1487 SR_FGT(SYS_BRBSRC_EL1(22), HDFGRTR, nBRBDATA, 0), 1488 SR_FGT(SYS_BRBSRC_EL1(23), HDFGRTR, nBRBDATA, 0), 1489 SR_FGT(SYS_BRBSRC_EL1(24), HDFGRTR, nBRBDATA, 0), 1490 SR_FGT(SYS_BRBSRC_EL1(25), HDFGRTR, nBRBDATA, 0), 1491 SR_FGT(SYS_BRBSRC_EL1(26), HDFGRTR, nBRBDATA, 0), 1492 SR_FGT(SYS_BRBSRC_EL1(27), HDFGRTR, nBRBDATA, 0), 1493 SR_FGT(SYS_BRBSRC_EL1(28), HDFGRTR, nBRBDATA, 0), 1494 SR_FGT(SYS_BRBSRC_EL1(29), HDFGRTR, nBRBDATA, 0), 1495 SR_FGT(SYS_BRBSRC_EL1(30), HDFGRTR, nBRBDATA, 0), 1496 SR_FGT(SYS_BRBSRC_EL1(31), HDFGRTR, nBRBDATA, 0), 1497 SR_FGT(SYS_BRBSRCINJ_EL1, HDFGRTR, nBRBDATA, 0), 1498 SR_FGT(SYS_BRBTGT_EL1(0), HDFGRTR, nBRBDATA, 0), 1499 SR_FGT(SYS_BRBTGT_EL1(1), HDFGRTR, nBRBDATA, 0), 1500 SR_FGT(SYS_BRBTGT_EL1(2), HDFGRTR, nBRBDATA, 0), 1501 SR_FGT(SYS_BRBTGT_EL1(3), HDFGRTR, nBRBDATA, 0), 1502 SR_FGT(SYS_BRBTGT_EL1(4), HDFGRTR, nBRBDATA, 0), 1503 SR_FGT(SYS_BRBTGT_EL1(5), HDFGRTR, nBRBDATA, 0), 1504 SR_FGT(SYS_BRBTGT_EL1(6), HDFGRTR, nBRBDATA, 0), 1505 SR_FGT(SYS_BRBTGT_EL1(7), HDFGRTR, nBRBDATA, 0), 1506 SR_FGT(SYS_BRBTGT_EL1(8), HDFGRTR, nBRBDATA, 0), 1507 SR_FGT(SYS_BRBTGT_EL1(9), HDFGRTR, nBRBDATA, 0), 1508 SR_FGT(SYS_BRBTGT_EL1(10), HDFGRTR, nBRBDATA, 0), 1509 SR_FGT(SYS_BRBTGT_EL1(11), HDFGRTR, nBRBDATA, 0), 1510 SR_FGT(SYS_BRBTGT_EL1(12), HDFGRTR, nBRBDATA, 0), 1511 SR_FGT(SYS_BRBTGT_EL1(13), HDFGRTR, nBRBDATA, 0), 1512 SR_FGT(SYS_BRBTGT_EL1(14), HDFGRTR, nBRBDATA, 0), 1513 SR_FGT(SYS_BRBTGT_EL1(15), HDFGRTR, nBRBDATA, 0), 1514 SR_FGT(SYS_BRBTGT_EL1(16), HDFGRTR, nBRBDATA, 0), 1515 SR_FGT(SYS_BRBTGT_EL1(17), HDFGRTR, nBRBDATA, 0), 1516 SR_FGT(SYS_BRBTGT_EL1(18), HDFGRTR, nBRBDATA, 0), 1517 SR_FGT(SYS_BRBTGT_EL1(19), HDFGRTR, nBRBDATA, 0), 1518 SR_FGT(SYS_BRBTGT_EL1(20), HDFGRTR, nBRBDATA, 0), 1519 SR_FGT(SYS_BRBTGT_EL1(21), HDFGRTR, nBRBDATA, 0), 1520 SR_FGT(SYS_BRBTGT_EL1(22), HDFGRTR, nBRBDATA, 0), 1521 SR_FGT(SYS_BRBTGT_EL1(23), HDFGRTR, nBRBDATA, 0), 1522 SR_FGT(SYS_BRBTGT_EL1(24), HDFGRTR, nBRBDATA, 0), 1523 SR_FGT(SYS_BRBTGT_EL1(25), HDFGRTR, nBRBDATA, 0), 1524 SR_FGT(SYS_BRBTGT_EL1(26), HDFGRTR, nBRBDATA, 0), 1525 SR_FGT(SYS_BRBTGT_EL1(27), HDFGRTR, nBRBDATA, 0), 1526 SR_FGT(SYS_BRBTGT_EL1(28), HDFGRTR, nBRBDATA, 0), 1527 SR_FGT(SYS_BRBTGT_EL1(29), HDFGRTR, nBRBDATA, 0), 1528 SR_FGT(SYS_BRBTGT_EL1(30), HDFGRTR, nBRBDATA, 0), 1529 SR_FGT(SYS_BRBTGT_EL1(31), HDFGRTR, nBRBDATA, 0), 1530 SR_FGT(SYS_BRBTGTINJ_EL1, HDFGRTR, nBRBDATA, 0), 1531 SR_FGT(SYS_BRBTS_EL1, HDFGRTR, nBRBDATA, 0), 1532 SR_FGT(SYS_BRBCR_EL1, HDFGRTR, nBRBCTL, 0), 1533 SR_FGT(SYS_BRBFCR_EL1, HDFGRTR, nBRBCTL, 0), 1534 SR_FGT(SYS_BRBIDR0_EL1, HDFGRTR, nBRBIDR, 0), 1535 SR_FGT(SYS_PMCEID0_EL0, HDFGRTR, PMCEIDn_EL0, 1), 1536 SR_FGT(SYS_PMCEID1_EL0, HDFGRTR, PMCEIDn_EL0, 1), 1537 SR_FGT(SYS_PMUSERENR_EL0, HDFGRTR, PMUSERENR_EL0, 1), 1538 SR_FGT(SYS_TRBTRG_EL1, HDFGRTR, TRBTRG_EL1, 1), 1539 SR_FGT(SYS_TRBSR_EL1, HDFGRTR, TRBSR_EL1, 1), 1540 SR_FGT(SYS_TRBPTR_EL1, HDFGRTR, TRBPTR_EL1, 1), 1541 SR_FGT(SYS_TRBMAR_EL1, HDFGRTR, TRBMAR_EL1, 1), 1542 SR_FGT(SYS_TRBLIMITR_EL1, HDFGRTR, TRBLIMITR_EL1, 1), 1543 SR_FGT(SYS_TRBIDR_EL1, HDFGRTR, TRBIDR_EL1, 1), 1544 SR_FGT(SYS_TRBBASER_EL1, HDFGRTR, TRBBASER_EL1, 1), 1545 SR_FGT(SYS_TRCVICTLR, HDFGRTR, TRCVICTLR, 1), 1546 SR_FGT(SYS_TRCSTATR, HDFGRTR, TRCSTATR, 1), 1547 SR_FGT(SYS_TRCSSCSR(0), HDFGRTR, TRCSSCSRn, 1), 1548 SR_FGT(SYS_TRCSSCSR(1), HDFGRTR, TRCSSCSRn, 1), 1549 SR_FGT(SYS_TRCSSCSR(2), HDFGRTR, TRCSSCSRn, 1), 1550 SR_FGT(SYS_TRCSSCSR(3), HDFGRTR, TRCSSCSRn, 1), 1551 SR_FGT(SYS_TRCSSCSR(4), HDFGRTR, TRCSSCSRn, 1), 1552 SR_FGT(SYS_TRCSSCSR(5), HDFGRTR, TRCSSCSRn, 1), 1553 SR_FGT(SYS_TRCSSCSR(6), HDFGRTR, TRCSSCSRn, 1), 1554 SR_FGT(SYS_TRCSSCSR(7), HDFGRTR, TRCSSCSRn, 1), 1555 SR_FGT(SYS_TRCSEQSTR, HDFGRTR, TRCSEQSTR, 1), 1556 SR_FGT(SYS_TRCPRGCTLR, HDFGRTR, TRCPRGCTLR, 1), 1557 SR_FGT(SYS_TRCOSLSR, HDFGRTR, TRCOSLSR, 1), 1558 SR_FGT(SYS_TRCIMSPEC(0), HDFGRTR, TRCIMSPECn, 1), 1559 SR_FGT(SYS_TRCIMSPEC(1), HDFGRTR, TRCIMSPECn, 1), 1560 SR_FGT(SYS_TRCIMSPEC(2), HDFGRTR, TRCIMSPECn, 1), 1561 SR_FGT(SYS_TRCIMSPEC(3), HDFGRTR, TRCIMSPECn, 1), 1562 SR_FGT(SYS_TRCIMSPEC(4), HDFGRTR, TRCIMSPECn, 1), 1563 SR_FGT(SYS_TRCIMSPEC(5), HDFGRTR, TRCIMSPECn, 1), 1564 SR_FGT(SYS_TRCIMSPEC(6), HDFGRTR, TRCIMSPECn, 1), 1565 SR_FGT(SYS_TRCIMSPEC(7), HDFGRTR, TRCIMSPECn, 1), 1566 SR_FGT(SYS_TRCDEVARCH, HDFGRTR, TRCID, 1), 1567 SR_FGT(SYS_TRCDEVID, HDFGRTR, TRCID, 1), 1568 SR_FGT(SYS_TRCIDR0, HDFGRTR, TRCID, 1), 1569 SR_FGT(SYS_TRCIDR1, HDFGRTR, TRCID, 1), 1570 SR_FGT(SYS_TRCIDR2, HDFGRTR, TRCID, 1), 1571 SR_FGT(SYS_TRCIDR3, HDFGRTR, TRCID, 1), 1572 SR_FGT(SYS_TRCIDR4, HDFGRTR, TRCID, 1), 1573 SR_FGT(SYS_TRCIDR5, HDFGRTR, TRCID, 1), 1574 SR_FGT(SYS_TRCIDR6, HDFGRTR, TRCID, 1), 1575 SR_FGT(SYS_TRCIDR7, HDFGRTR, TRCID, 1), 1576 SR_FGT(SYS_TRCIDR8, HDFGRTR, TRCID, 1), 1577 SR_FGT(SYS_TRCIDR9, HDFGRTR, TRCID, 1), 1578 SR_FGT(SYS_TRCIDR10, HDFGRTR, TRCID, 1), 1579 SR_FGT(SYS_TRCIDR11, HDFGRTR, TRCID, 1), 1580 SR_FGT(SYS_TRCIDR12, HDFGRTR, TRCID, 1), 1581 SR_FGT(SYS_TRCIDR13, HDFGRTR, TRCID, 1), 1582 SR_FGT(SYS_TRCCNTVR(0), HDFGRTR, TRCCNTVRn, 1), 1583 SR_FGT(SYS_TRCCNTVR(1), HDFGRTR, TRCCNTVRn, 1), 1584 SR_FGT(SYS_TRCCNTVR(2), HDFGRTR, TRCCNTVRn, 1), 1585 SR_FGT(SYS_TRCCNTVR(3), HDFGRTR, TRCCNTVRn, 1), 1586 SR_FGT(SYS_TRCCLAIMCLR, HDFGRTR, TRCCLAIM, 1), 1587 SR_FGT(SYS_TRCCLAIMSET, HDFGRTR, TRCCLAIM, 1), 1588 SR_FGT(SYS_TRCAUXCTLR, HDFGRTR, TRCAUXCTLR, 1), 1589 SR_FGT(SYS_TRCAUTHSTATUS, HDFGRTR, TRCAUTHSTATUS, 1), 1590 SR_FGT(SYS_TRCACATR(0), HDFGRTR, TRC, 1), 1591 SR_FGT(SYS_TRCACATR(1), HDFGRTR, TRC, 1), 1592 SR_FGT(SYS_TRCACATR(2), HDFGRTR, TRC, 1), 1593 SR_FGT(SYS_TRCACATR(3), HDFGRTR, TRC, 1), 1594 SR_FGT(SYS_TRCACATR(4), HDFGRTR, TRC, 1), 1595 SR_FGT(SYS_TRCACATR(5), HDFGRTR, TRC, 1), 1596 SR_FGT(SYS_TRCACATR(6), HDFGRTR, TRC, 1), 1597 SR_FGT(SYS_TRCACATR(7), HDFGRTR, TRC, 1), 1598 SR_FGT(SYS_TRCACATR(8), HDFGRTR, TRC, 1), 1599 SR_FGT(SYS_TRCACATR(9), HDFGRTR, TRC, 1), 1600 SR_FGT(SYS_TRCACATR(10), HDFGRTR, TRC, 1), 1601 SR_FGT(SYS_TRCACATR(11), HDFGRTR, TRC, 1), 1602 SR_FGT(SYS_TRCACATR(12), HDFGRTR, TRC, 1), 1603 SR_FGT(SYS_TRCACATR(13), HDFGRTR, TRC, 1), 1604 SR_FGT(SYS_TRCACATR(14), HDFGRTR, TRC, 1), 1605 SR_FGT(SYS_TRCACATR(15), HDFGRTR, TRC, 1), 1606 SR_FGT(SYS_TRCACVR(0), HDFGRTR, TRC, 1), 1607 SR_FGT(SYS_TRCACVR(1), HDFGRTR, TRC, 1), 1608 SR_FGT(SYS_TRCACVR(2), HDFGRTR, TRC, 1), 1609 SR_FGT(SYS_TRCACVR(3), HDFGRTR, TRC, 1), 1610 SR_FGT(SYS_TRCACVR(4), HDFGRTR, TRC, 1), 1611 SR_FGT(SYS_TRCACVR(5), HDFGRTR, TRC, 1), 1612 SR_FGT(SYS_TRCACVR(6), HDFGRTR, TRC, 1), 1613 SR_FGT(SYS_TRCACVR(7), HDFGRTR, TRC, 1), 1614 SR_FGT(SYS_TRCACVR(8), HDFGRTR, TRC, 1), 1615 SR_FGT(SYS_TRCACVR(9), HDFGRTR, TRC, 1), 1616 SR_FGT(SYS_TRCACVR(10), HDFGRTR, TRC, 1), 1617 SR_FGT(SYS_TRCACVR(11), HDFGRTR, TRC, 1), 1618 SR_FGT(SYS_TRCACVR(12), HDFGRTR, TRC, 1), 1619 SR_FGT(SYS_TRCACVR(13), HDFGRTR, TRC, 1), 1620 SR_FGT(SYS_TRCACVR(14), HDFGRTR, TRC, 1), 1621 SR_FGT(SYS_TRCACVR(15), HDFGRTR, TRC, 1), 1622 SR_FGT(SYS_TRCBBCTLR, HDFGRTR, TRC, 1), 1623 SR_FGT(SYS_TRCCCCTLR, HDFGRTR, TRC, 1), 1624 SR_FGT(SYS_TRCCIDCCTLR0, HDFGRTR, TRC, 1), 1625 SR_FGT(SYS_TRCCIDCCTLR1, HDFGRTR, TRC, 1), 1626 SR_FGT(SYS_TRCCIDCVR(0), HDFGRTR, TRC, 1), 1627 SR_FGT(SYS_TRCCIDCVR(1), HDFGRTR, TRC, 1), 1628 SR_FGT(SYS_TRCCIDCVR(2), HDFGRTR, TRC, 1), 1629 SR_FGT(SYS_TRCCIDCVR(3), HDFGRTR, TRC, 1), 1630 SR_FGT(SYS_TRCCIDCVR(4), HDFGRTR, TRC, 1), 1631 SR_FGT(SYS_TRCCIDCVR(5), HDFGRTR, TRC, 1), 1632 SR_FGT(SYS_TRCCIDCVR(6), HDFGRTR, TRC, 1), 1633 SR_FGT(SYS_TRCCIDCVR(7), HDFGRTR, TRC, 1), 1634 SR_FGT(SYS_TRCCNTCTLR(0), HDFGRTR, TRC, 1), 1635 SR_FGT(SYS_TRCCNTCTLR(1), HDFGRTR, TRC, 1), 1636 SR_FGT(SYS_TRCCNTCTLR(2), HDFGRTR, TRC, 1), 1637 SR_FGT(SYS_TRCCNTCTLR(3), HDFGRTR, TRC, 1), 1638 SR_FGT(SYS_TRCCNTRLDVR(0), HDFGRTR, TRC, 1), 1639 SR_FGT(SYS_TRCCNTRLDVR(1), HDFGRTR, TRC, 1), 1640 SR_FGT(SYS_TRCCNTRLDVR(2), HDFGRTR, TRC, 1), 1641 SR_FGT(SYS_TRCCNTRLDVR(3), HDFGRTR, TRC, 1), 1642 SR_FGT(SYS_TRCCONFIGR, HDFGRTR, TRC, 1), 1643 SR_FGT(SYS_TRCEVENTCTL0R, HDFGRTR, TRC, 1), 1644 SR_FGT(SYS_TRCEVENTCTL1R, HDFGRTR, TRC, 1), 1645 SR_FGT(SYS_TRCEXTINSELR(0), HDFGRTR, TRC, 1), 1646 SR_FGT(SYS_TRCEXTINSELR(1), HDFGRTR, TRC, 1), 1647 SR_FGT(SYS_TRCEXTINSELR(2), HDFGRTR, TRC, 1), 1648 SR_FGT(SYS_TRCEXTINSELR(3), HDFGRTR, TRC, 1), 1649 SR_FGT(SYS_TRCQCTLR, HDFGRTR, TRC, 1), 1650 SR_FGT(SYS_TRCRSCTLR(2), HDFGRTR, TRC, 1), 1651 SR_FGT(SYS_TRCRSCTLR(3), HDFGRTR, TRC, 1), 1652 SR_FGT(SYS_TRCRSCTLR(4), HDFGRTR, TRC, 1), 1653 SR_FGT(SYS_TRCRSCTLR(5), HDFGRTR, TRC, 1), 1654 SR_FGT(SYS_TRCRSCTLR(6), HDFGRTR, TRC, 1), 1655 SR_FGT(SYS_TRCRSCTLR(7), HDFGRTR, TRC, 1), 1656 SR_FGT(SYS_TRCRSCTLR(8), HDFGRTR, TRC, 1), 1657 SR_FGT(SYS_TRCRSCTLR(9), HDFGRTR, TRC, 1), 1658 SR_FGT(SYS_TRCRSCTLR(10), HDFGRTR, TRC, 1), 1659 SR_FGT(SYS_TRCRSCTLR(11), HDFGRTR, TRC, 1), 1660 SR_FGT(SYS_TRCRSCTLR(12), HDFGRTR, TRC, 1), 1661 SR_FGT(SYS_TRCRSCTLR(13), HDFGRTR, TRC, 1), 1662 SR_FGT(SYS_TRCRSCTLR(14), HDFGRTR, TRC, 1), 1663 SR_FGT(SYS_TRCRSCTLR(15), HDFGRTR, TRC, 1), 1664 SR_FGT(SYS_TRCRSCTLR(16), HDFGRTR, TRC, 1), 1665 SR_FGT(SYS_TRCRSCTLR(17), HDFGRTR, TRC, 1), 1666 SR_FGT(SYS_TRCRSCTLR(18), HDFGRTR, TRC, 1), 1667 SR_FGT(SYS_TRCRSCTLR(19), HDFGRTR, TRC, 1), 1668 SR_FGT(SYS_TRCRSCTLR(20), HDFGRTR, TRC, 1), 1669 SR_FGT(SYS_TRCRSCTLR(21), HDFGRTR, TRC, 1), 1670 SR_FGT(SYS_TRCRSCTLR(22), HDFGRTR, TRC, 1), 1671 SR_FGT(SYS_TRCRSCTLR(23), HDFGRTR, TRC, 1), 1672 SR_FGT(SYS_TRCRSCTLR(24), HDFGRTR, TRC, 1), 1673 SR_FGT(SYS_TRCRSCTLR(25), HDFGRTR, TRC, 1), 1674 SR_FGT(SYS_TRCRSCTLR(26), HDFGRTR, TRC, 1), 1675 SR_FGT(SYS_TRCRSCTLR(27), HDFGRTR, TRC, 1), 1676 SR_FGT(SYS_TRCRSCTLR(28), HDFGRTR, TRC, 1), 1677 SR_FGT(SYS_TRCRSCTLR(29), HDFGRTR, TRC, 1), 1678 SR_FGT(SYS_TRCRSCTLR(30), HDFGRTR, TRC, 1), 1679 SR_FGT(SYS_TRCRSCTLR(31), HDFGRTR, TRC, 1), 1680 SR_FGT(SYS_TRCRSR, HDFGRTR, TRC, 1), 1681 SR_FGT(SYS_TRCSEQEVR(0), HDFGRTR, TRC, 1), 1682 SR_FGT(SYS_TRCSEQEVR(1), HDFGRTR, TRC, 1), 1683 SR_FGT(SYS_TRCSEQEVR(2), HDFGRTR, TRC, 1), 1684 SR_FGT(SYS_TRCSEQRSTEVR, HDFGRTR, TRC, 1), 1685 SR_FGT(SYS_TRCSSCCR(0), HDFGRTR, TRC, 1), 1686 SR_FGT(SYS_TRCSSCCR(1), HDFGRTR, TRC, 1), 1687 SR_FGT(SYS_TRCSSCCR(2), HDFGRTR, TRC, 1), 1688 SR_FGT(SYS_TRCSSCCR(3), HDFGRTR, TRC, 1), 1689 SR_FGT(SYS_TRCSSCCR(4), HDFGRTR, TRC, 1), 1690 SR_FGT(SYS_TRCSSCCR(5), HDFGRTR, TRC, 1), 1691 SR_FGT(SYS_TRCSSCCR(6), HDFGRTR, TRC, 1), 1692 SR_FGT(SYS_TRCSSCCR(7), HDFGRTR, TRC, 1), 1693 SR_FGT(SYS_TRCSSPCICR(0), HDFGRTR, TRC, 1), 1694 SR_FGT(SYS_TRCSSPCICR(1), HDFGRTR, TRC, 1), 1695 SR_FGT(SYS_TRCSSPCICR(2), HDFGRTR, TRC, 1), 1696 SR_FGT(SYS_TRCSSPCICR(3), HDFGRTR, TRC, 1), 1697 SR_FGT(SYS_TRCSSPCICR(4), HDFGRTR, TRC, 1), 1698 SR_FGT(SYS_TRCSSPCICR(5), HDFGRTR, TRC, 1), 1699 SR_FGT(SYS_TRCSSPCICR(6), HDFGRTR, TRC, 1), 1700 SR_FGT(SYS_TRCSSPCICR(7), HDFGRTR, TRC, 1), 1701 SR_FGT(SYS_TRCSTALLCTLR, HDFGRTR, TRC, 1), 1702 SR_FGT(SYS_TRCSYNCPR, HDFGRTR, TRC, 1), 1703 SR_FGT(SYS_TRCTRACEIDR, HDFGRTR, TRC, 1), 1704 SR_FGT(SYS_TRCTSCTLR, HDFGRTR, TRC, 1), 1705 SR_FGT(SYS_TRCVIIECTLR, HDFGRTR, TRC, 1), 1706 SR_FGT(SYS_TRCVIPCSSCTLR, HDFGRTR, TRC, 1), 1707 SR_FGT(SYS_TRCVISSCTLR, HDFGRTR, TRC, 1), 1708 SR_FGT(SYS_TRCVMIDCCTLR0, HDFGRTR, TRC, 1), 1709 SR_FGT(SYS_TRCVMIDCCTLR1, HDFGRTR, TRC, 1), 1710 SR_FGT(SYS_TRCVMIDCVR(0), HDFGRTR, TRC, 1), 1711 SR_FGT(SYS_TRCVMIDCVR(1), HDFGRTR, TRC, 1), 1712 SR_FGT(SYS_TRCVMIDCVR(2), HDFGRTR, TRC, 1), 1713 SR_FGT(SYS_TRCVMIDCVR(3), HDFGRTR, TRC, 1), 1714 SR_FGT(SYS_TRCVMIDCVR(4), HDFGRTR, TRC, 1), 1715 SR_FGT(SYS_TRCVMIDCVR(5), HDFGRTR, TRC, 1), 1716 SR_FGT(SYS_TRCVMIDCVR(6), HDFGRTR, TRC, 1), 1717 SR_FGT(SYS_TRCVMIDCVR(7), HDFGRTR, TRC, 1), 1718 SR_FGT(SYS_PMSLATFR_EL1, HDFGRTR, PMSLATFR_EL1, 1), 1719 SR_FGT(SYS_PMSIRR_EL1, HDFGRTR, PMSIRR_EL1, 1), 1720 SR_FGT(SYS_PMSIDR_EL1, HDFGRTR, PMSIDR_EL1, 1), 1721 SR_FGT(SYS_PMSICR_EL1, HDFGRTR, PMSICR_EL1, 1), 1722 SR_FGT(SYS_PMSFCR_EL1, HDFGRTR, PMSFCR_EL1, 1), 1723 SR_FGT(SYS_PMSEVFR_EL1, HDFGRTR, PMSEVFR_EL1, 1), 1724 SR_FGT(SYS_PMSCR_EL1, HDFGRTR, PMSCR_EL1, 1), 1725 SR_FGT(SYS_PMBSR_EL1, HDFGRTR, PMBSR_EL1, 1), 1726 SR_FGT(SYS_PMBPTR_EL1, HDFGRTR, PMBPTR_EL1, 1), 1727 SR_FGT(SYS_PMBLIMITR_EL1, HDFGRTR, PMBLIMITR_EL1, 1), 1728 SR_FGT(SYS_PMMIR_EL1, HDFGRTR, PMMIR_EL1, 1), 1729 SR_FGT(SYS_PMSELR_EL0, HDFGRTR, PMSELR_EL0, 1), 1730 SR_FGT(SYS_PMOVSCLR_EL0, HDFGRTR, PMOVS, 1), 1731 SR_FGT(SYS_PMOVSSET_EL0, HDFGRTR, PMOVS, 1), 1732 SR_FGT(SYS_PMINTENCLR_EL1, HDFGRTR, PMINTEN, 1), 1733 SR_FGT(SYS_PMINTENSET_EL1, HDFGRTR, PMINTEN, 1), 1734 SR_FGT(SYS_PMCNTENCLR_EL0, HDFGRTR, PMCNTEN, 1), 1735 SR_FGT(SYS_PMCNTENSET_EL0, HDFGRTR, PMCNTEN, 1), 1736 SR_FGT(SYS_PMCCNTR_EL0, HDFGRTR, PMCCNTR_EL0, 1), 1737 SR_FGT(SYS_PMCCFILTR_EL0, HDFGRTR, PMCCFILTR_EL0, 1), 1738 SR_FGT(SYS_PMEVTYPERn_EL0(0), HDFGRTR, PMEVTYPERn_EL0, 1), 1739 SR_FGT(SYS_PMEVTYPERn_EL0(1), HDFGRTR, PMEVTYPERn_EL0, 1), 1740 SR_FGT(SYS_PMEVTYPERn_EL0(2), HDFGRTR, PMEVTYPERn_EL0, 1), 1741 SR_FGT(SYS_PMEVTYPERn_EL0(3), HDFGRTR, PMEVTYPERn_EL0, 1), 1742 SR_FGT(SYS_PMEVTYPERn_EL0(4), HDFGRTR, PMEVTYPERn_EL0, 1), 1743 SR_FGT(SYS_PMEVTYPERn_EL0(5), HDFGRTR, PMEVTYPERn_EL0, 1), 1744 SR_FGT(SYS_PMEVTYPERn_EL0(6), HDFGRTR, PMEVTYPERn_EL0, 1), 1745 SR_FGT(SYS_PMEVTYPERn_EL0(7), HDFGRTR, PMEVTYPERn_EL0, 1), 1746 SR_FGT(SYS_PMEVTYPERn_EL0(8), HDFGRTR, PMEVTYPERn_EL0, 1), 1747 SR_FGT(SYS_PMEVTYPERn_EL0(9), HDFGRTR, PMEVTYPERn_EL0, 1), 1748 SR_FGT(SYS_PMEVTYPERn_EL0(10), HDFGRTR, PMEVTYPERn_EL0, 1), 1749 SR_FGT(SYS_PMEVTYPERn_EL0(11), HDFGRTR, PMEVTYPERn_EL0, 1), 1750 SR_FGT(SYS_PMEVTYPERn_EL0(12), HDFGRTR, PMEVTYPERn_EL0, 1), 1751 SR_FGT(SYS_PMEVTYPERn_EL0(13), HDFGRTR, PMEVTYPERn_EL0, 1), 1752 SR_FGT(SYS_PMEVTYPERn_EL0(14), HDFGRTR, PMEVTYPERn_EL0, 1), 1753 SR_FGT(SYS_PMEVTYPERn_EL0(15), HDFGRTR, PMEVTYPERn_EL0, 1), 1754 SR_FGT(SYS_PMEVTYPERn_EL0(16), HDFGRTR, PMEVTYPERn_EL0, 1), 1755 SR_FGT(SYS_PMEVTYPERn_EL0(17), HDFGRTR, PMEVTYPERn_EL0, 1), 1756 SR_FGT(SYS_PMEVTYPERn_EL0(18), HDFGRTR, PMEVTYPERn_EL0, 1), 1757 SR_FGT(SYS_PMEVTYPERn_EL0(19), HDFGRTR, PMEVTYPERn_EL0, 1), 1758 SR_FGT(SYS_PMEVTYPERn_EL0(20), HDFGRTR, PMEVTYPERn_EL0, 1), 1759 SR_FGT(SYS_PMEVTYPERn_EL0(21), HDFGRTR, PMEVTYPERn_EL0, 1), 1760 SR_FGT(SYS_PMEVTYPERn_EL0(22), HDFGRTR, PMEVTYPERn_EL0, 1), 1761 SR_FGT(SYS_PMEVTYPERn_EL0(23), HDFGRTR, PMEVTYPERn_EL0, 1), 1762 SR_FGT(SYS_PMEVTYPERn_EL0(24), HDFGRTR, PMEVTYPERn_EL0, 1), 1763 SR_FGT(SYS_PMEVTYPERn_EL0(25), HDFGRTR, PMEVTYPERn_EL0, 1), 1764 SR_FGT(SYS_PMEVTYPERn_EL0(26), HDFGRTR, PMEVTYPERn_EL0, 1), 1765 SR_FGT(SYS_PMEVTYPERn_EL0(27), HDFGRTR, PMEVTYPERn_EL0, 1), 1766 SR_FGT(SYS_PMEVTYPERn_EL0(28), HDFGRTR, PMEVTYPERn_EL0, 1), 1767 SR_FGT(SYS_PMEVTYPERn_EL0(29), HDFGRTR, PMEVTYPERn_EL0, 1), 1768 SR_FGT(SYS_PMEVTYPERn_EL0(30), HDFGRTR, PMEVTYPERn_EL0, 1), 1769 SR_FGT(SYS_PMEVCNTRn_EL0(0), HDFGRTR, PMEVCNTRn_EL0, 1), 1770 SR_FGT(SYS_PMEVCNTRn_EL0(1), HDFGRTR, PMEVCNTRn_EL0, 1), 1771 SR_FGT(SYS_PMEVCNTRn_EL0(2), HDFGRTR, PMEVCNTRn_EL0, 1), 1772 SR_FGT(SYS_PMEVCNTRn_EL0(3), HDFGRTR, PMEVCNTRn_EL0, 1), 1773 SR_FGT(SYS_PMEVCNTRn_EL0(4), HDFGRTR, PMEVCNTRn_EL0, 1), 1774 SR_FGT(SYS_PMEVCNTRn_EL0(5), HDFGRTR, PMEVCNTRn_EL0, 1), 1775 SR_FGT(SYS_PMEVCNTRn_EL0(6), HDFGRTR, PMEVCNTRn_EL0, 1), 1776 SR_FGT(SYS_PMEVCNTRn_EL0(7), HDFGRTR, PMEVCNTRn_EL0, 1), 1777 SR_FGT(SYS_PMEVCNTRn_EL0(8), HDFGRTR, PMEVCNTRn_EL0, 1), 1778 SR_FGT(SYS_PMEVCNTRn_EL0(9), HDFGRTR, PMEVCNTRn_EL0, 1), 1779 SR_FGT(SYS_PMEVCNTRn_EL0(10), HDFGRTR, PMEVCNTRn_EL0, 1), 1780 SR_FGT(SYS_PMEVCNTRn_EL0(11), HDFGRTR, PMEVCNTRn_EL0, 1), 1781 SR_FGT(SYS_PMEVCNTRn_EL0(12), HDFGRTR, PMEVCNTRn_EL0, 1), 1782 SR_FGT(SYS_PMEVCNTRn_EL0(13), HDFGRTR, PMEVCNTRn_EL0, 1), 1783 SR_FGT(SYS_PMEVCNTRn_EL0(14), HDFGRTR, PMEVCNTRn_EL0, 1), 1784 SR_FGT(SYS_PMEVCNTRn_EL0(15), HDFGRTR, PMEVCNTRn_EL0, 1), 1785 SR_FGT(SYS_PMEVCNTRn_EL0(16), HDFGRTR, PMEVCNTRn_EL0, 1), 1786 SR_FGT(SYS_PMEVCNTRn_EL0(17), HDFGRTR, PMEVCNTRn_EL0, 1), 1787 SR_FGT(SYS_PMEVCNTRn_EL0(18), HDFGRTR, PMEVCNTRn_EL0, 1), 1788 SR_FGT(SYS_PMEVCNTRn_EL0(19), HDFGRTR, PMEVCNTRn_EL0, 1), 1789 SR_FGT(SYS_PMEVCNTRn_EL0(20), HDFGRTR, PMEVCNTRn_EL0, 1), 1790 SR_FGT(SYS_PMEVCNTRn_EL0(21), HDFGRTR, PMEVCNTRn_EL0, 1), 1791 SR_FGT(SYS_PMEVCNTRn_EL0(22), HDFGRTR, PMEVCNTRn_EL0, 1), 1792 SR_FGT(SYS_PMEVCNTRn_EL0(23), HDFGRTR, PMEVCNTRn_EL0, 1), 1793 SR_FGT(SYS_PMEVCNTRn_EL0(24), HDFGRTR, PMEVCNTRn_EL0, 1), 1794 SR_FGT(SYS_PMEVCNTRn_EL0(25), HDFGRTR, PMEVCNTRn_EL0, 1), 1795 SR_FGT(SYS_PMEVCNTRn_EL0(26), HDFGRTR, PMEVCNTRn_EL0, 1), 1796 SR_FGT(SYS_PMEVCNTRn_EL0(27), HDFGRTR, PMEVCNTRn_EL0, 1), 1797 SR_FGT(SYS_PMEVCNTRn_EL0(28), HDFGRTR, PMEVCNTRn_EL0, 1), 1798 SR_FGT(SYS_PMEVCNTRn_EL0(29), HDFGRTR, PMEVCNTRn_EL0, 1), 1799 SR_FGT(SYS_PMEVCNTRn_EL0(30), HDFGRTR, PMEVCNTRn_EL0, 1), 1800 SR_FGT(SYS_OSDLR_EL1, HDFGRTR, OSDLR_EL1, 1), 1801 SR_FGT(SYS_OSECCR_EL1, HDFGRTR, OSECCR_EL1, 1), 1802 SR_FGT(SYS_OSLSR_EL1, HDFGRTR, OSLSR_EL1, 1), 1803 SR_FGT(SYS_DBGPRCR_EL1, HDFGRTR, DBGPRCR_EL1, 1), 1804 SR_FGT(SYS_DBGAUTHSTATUS_EL1, HDFGRTR, DBGAUTHSTATUS_EL1, 1), 1805 SR_FGT(SYS_DBGCLAIMSET_EL1, HDFGRTR, DBGCLAIM, 1), 1806 SR_FGT(SYS_DBGCLAIMCLR_EL1, HDFGRTR, DBGCLAIM, 1), 1807 SR_FGT(SYS_MDSCR_EL1, HDFGRTR, MDSCR_EL1, 1), 1808 /* 1809 * The trap bits capture *64* debug registers per bit, but the 1810 * ARM ARM only describes the encoding for the first 16, and 1811 * we don't really support more than that anyway. 1812 */ 1813 SR_FGT(SYS_DBGWVRn_EL1(0), HDFGRTR, DBGWVRn_EL1, 1), 1814 SR_FGT(SYS_DBGWVRn_EL1(1), HDFGRTR, DBGWVRn_EL1, 1), 1815 SR_FGT(SYS_DBGWVRn_EL1(2), HDFGRTR, DBGWVRn_EL1, 1), 1816 SR_FGT(SYS_DBGWVRn_EL1(3), HDFGRTR, DBGWVRn_EL1, 1), 1817 SR_FGT(SYS_DBGWVRn_EL1(4), HDFGRTR, DBGWVRn_EL1, 1), 1818 SR_FGT(SYS_DBGWVRn_EL1(5), HDFGRTR, DBGWVRn_EL1, 1), 1819 SR_FGT(SYS_DBGWVRn_EL1(6), HDFGRTR, DBGWVRn_EL1, 1), 1820 SR_FGT(SYS_DBGWVRn_EL1(7), HDFGRTR, DBGWVRn_EL1, 1), 1821 SR_FGT(SYS_DBGWVRn_EL1(8), HDFGRTR, DBGWVRn_EL1, 1), 1822 SR_FGT(SYS_DBGWVRn_EL1(9), HDFGRTR, DBGWVRn_EL1, 1), 1823 SR_FGT(SYS_DBGWVRn_EL1(10), HDFGRTR, DBGWVRn_EL1, 1), 1824 SR_FGT(SYS_DBGWVRn_EL1(11), HDFGRTR, DBGWVRn_EL1, 1), 1825 SR_FGT(SYS_DBGWVRn_EL1(12), HDFGRTR, DBGWVRn_EL1, 1), 1826 SR_FGT(SYS_DBGWVRn_EL1(13), HDFGRTR, DBGWVRn_EL1, 1), 1827 SR_FGT(SYS_DBGWVRn_EL1(14), HDFGRTR, DBGWVRn_EL1, 1), 1828 SR_FGT(SYS_DBGWVRn_EL1(15), HDFGRTR, DBGWVRn_EL1, 1), 1829 SR_FGT(SYS_DBGWCRn_EL1(0), HDFGRTR, DBGWCRn_EL1, 1), 1830 SR_FGT(SYS_DBGWCRn_EL1(1), HDFGRTR, DBGWCRn_EL1, 1), 1831 SR_FGT(SYS_DBGWCRn_EL1(2), HDFGRTR, DBGWCRn_EL1, 1), 1832 SR_FGT(SYS_DBGWCRn_EL1(3), HDFGRTR, DBGWCRn_EL1, 1), 1833 SR_FGT(SYS_DBGWCRn_EL1(4), HDFGRTR, DBGWCRn_EL1, 1), 1834 SR_FGT(SYS_DBGWCRn_EL1(5), HDFGRTR, DBGWCRn_EL1, 1), 1835 SR_FGT(SYS_DBGWCRn_EL1(6), HDFGRTR, DBGWCRn_EL1, 1), 1836 SR_FGT(SYS_DBGWCRn_EL1(7), HDFGRTR, DBGWCRn_EL1, 1), 1837 SR_FGT(SYS_DBGWCRn_EL1(8), HDFGRTR, DBGWCRn_EL1, 1), 1838 SR_FGT(SYS_DBGWCRn_EL1(9), HDFGRTR, DBGWCRn_EL1, 1), 1839 SR_FGT(SYS_DBGWCRn_EL1(10), HDFGRTR, DBGWCRn_EL1, 1), 1840 SR_FGT(SYS_DBGWCRn_EL1(11), HDFGRTR, DBGWCRn_EL1, 1), 1841 SR_FGT(SYS_DBGWCRn_EL1(12), HDFGRTR, DBGWCRn_EL1, 1), 1842 SR_FGT(SYS_DBGWCRn_EL1(13), HDFGRTR, DBGWCRn_EL1, 1), 1843 SR_FGT(SYS_DBGWCRn_EL1(14), HDFGRTR, DBGWCRn_EL1, 1), 1844 SR_FGT(SYS_DBGWCRn_EL1(15), HDFGRTR, DBGWCRn_EL1, 1), 1845 SR_FGT(SYS_DBGBVRn_EL1(0), HDFGRTR, DBGBVRn_EL1, 1), 1846 SR_FGT(SYS_DBGBVRn_EL1(1), HDFGRTR, DBGBVRn_EL1, 1), 1847 SR_FGT(SYS_DBGBVRn_EL1(2), HDFGRTR, DBGBVRn_EL1, 1), 1848 SR_FGT(SYS_DBGBVRn_EL1(3), HDFGRTR, DBGBVRn_EL1, 1), 1849 SR_FGT(SYS_DBGBVRn_EL1(4), HDFGRTR, DBGBVRn_EL1, 1), 1850 SR_FGT(SYS_DBGBVRn_EL1(5), HDFGRTR, DBGBVRn_EL1, 1), 1851 SR_FGT(SYS_DBGBVRn_EL1(6), HDFGRTR, DBGBVRn_EL1, 1), 1852 SR_FGT(SYS_DBGBVRn_EL1(7), HDFGRTR, DBGBVRn_EL1, 1), 1853 SR_FGT(SYS_DBGBVRn_EL1(8), HDFGRTR, DBGBVRn_EL1, 1), 1854 SR_FGT(SYS_DBGBVRn_EL1(9), HDFGRTR, DBGBVRn_EL1, 1), 1855 SR_FGT(SYS_DBGBVRn_EL1(10), HDFGRTR, DBGBVRn_EL1, 1), 1856 SR_FGT(SYS_DBGBVRn_EL1(11), HDFGRTR, DBGBVRn_EL1, 1), 1857 SR_FGT(SYS_DBGBVRn_EL1(12), HDFGRTR, DBGBVRn_EL1, 1), 1858 SR_FGT(SYS_DBGBVRn_EL1(13), HDFGRTR, DBGBVRn_EL1, 1), 1859 SR_FGT(SYS_DBGBVRn_EL1(14), HDFGRTR, DBGBVRn_EL1, 1), 1860 SR_FGT(SYS_DBGBVRn_EL1(15), HDFGRTR, DBGBVRn_EL1, 1), 1861 SR_FGT(SYS_DBGBCRn_EL1(0), HDFGRTR, DBGBCRn_EL1, 1), 1862 SR_FGT(SYS_DBGBCRn_EL1(1), HDFGRTR, DBGBCRn_EL1, 1), 1863 SR_FGT(SYS_DBGBCRn_EL1(2), HDFGRTR, DBGBCRn_EL1, 1), 1864 SR_FGT(SYS_DBGBCRn_EL1(3), HDFGRTR, DBGBCRn_EL1, 1), 1865 SR_FGT(SYS_DBGBCRn_EL1(4), HDFGRTR, DBGBCRn_EL1, 1), 1866 SR_FGT(SYS_DBGBCRn_EL1(5), HDFGRTR, DBGBCRn_EL1, 1), 1867 SR_FGT(SYS_DBGBCRn_EL1(6), HDFGRTR, DBGBCRn_EL1, 1), 1868 SR_FGT(SYS_DBGBCRn_EL1(7), HDFGRTR, DBGBCRn_EL1, 1), 1869 SR_FGT(SYS_DBGBCRn_EL1(8), HDFGRTR, DBGBCRn_EL1, 1), 1870 SR_FGT(SYS_DBGBCRn_EL1(9), HDFGRTR, DBGBCRn_EL1, 1), 1871 SR_FGT(SYS_DBGBCRn_EL1(10), HDFGRTR, DBGBCRn_EL1, 1), 1872 SR_FGT(SYS_DBGBCRn_EL1(11), HDFGRTR, DBGBCRn_EL1, 1), 1873 SR_FGT(SYS_DBGBCRn_EL1(12), HDFGRTR, DBGBCRn_EL1, 1), 1874 SR_FGT(SYS_DBGBCRn_EL1(13), HDFGRTR, DBGBCRn_EL1, 1), 1875 SR_FGT(SYS_DBGBCRn_EL1(14), HDFGRTR, DBGBCRn_EL1, 1), 1876 SR_FGT(SYS_DBGBCRn_EL1(15), HDFGRTR, DBGBCRn_EL1, 1), 1877 /* 1878 * HDFGWTR_EL2 1879 * 1880 * Although HDFGRTR_EL2 and HDFGWTR_EL2 registers largely 1881 * overlap in their bit assignment, there are a number of bits 1882 * that are RES0 on one side, and an actual trap bit on the 1883 * other. The policy chosen here is to describe all the 1884 * read-side mappings, and only the write-side mappings that 1885 * differ from the read side, and the trap handler will pick 1886 * the correct shadow register based on the access type. 1887 */ 1888 SR_FGT(SYS_TRFCR_EL1, HDFGWTR, TRFCR_EL1, 1), 1889 SR_FGT(SYS_TRCOSLAR, HDFGWTR, TRCOSLAR, 1), 1890 SR_FGT(SYS_PMCR_EL0, HDFGWTR, PMCR_EL0, 1), 1891 SR_FGT(SYS_PMSWINC_EL0, HDFGWTR, PMSWINC_EL0, 1), 1892 SR_FGT(SYS_OSLAR_EL1, HDFGWTR, OSLAR_EL1, 1), 1893 /* 1894 * HAFGRTR_EL2 1895 */ 1896 SR_FGT(SYS_AMEVTYPER1_EL0(15), HAFGRTR, AMEVTYPER115_EL0, 1), 1897 SR_FGT(SYS_AMEVTYPER1_EL0(14), HAFGRTR, AMEVTYPER114_EL0, 1), 1898 SR_FGT(SYS_AMEVTYPER1_EL0(13), HAFGRTR, AMEVTYPER113_EL0, 1), 1899 SR_FGT(SYS_AMEVTYPER1_EL0(12), HAFGRTR, AMEVTYPER112_EL0, 1), 1900 SR_FGT(SYS_AMEVTYPER1_EL0(11), HAFGRTR, AMEVTYPER111_EL0, 1), 1901 SR_FGT(SYS_AMEVTYPER1_EL0(10), HAFGRTR, AMEVTYPER110_EL0, 1), 1902 SR_FGT(SYS_AMEVTYPER1_EL0(9), HAFGRTR, AMEVTYPER19_EL0, 1), 1903 SR_FGT(SYS_AMEVTYPER1_EL0(8), HAFGRTR, AMEVTYPER18_EL0, 1), 1904 SR_FGT(SYS_AMEVTYPER1_EL0(7), HAFGRTR, AMEVTYPER17_EL0, 1), 1905 SR_FGT(SYS_AMEVTYPER1_EL0(6), HAFGRTR, AMEVTYPER16_EL0, 1), 1906 SR_FGT(SYS_AMEVTYPER1_EL0(5), HAFGRTR, AMEVTYPER15_EL0, 1), 1907 SR_FGT(SYS_AMEVTYPER1_EL0(4), HAFGRTR, AMEVTYPER14_EL0, 1), 1908 SR_FGT(SYS_AMEVTYPER1_EL0(3), HAFGRTR, AMEVTYPER13_EL0, 1), 1909 SR_FGT(SYS_AMEVTYPER1_EL0(2), HAFGRTR, AMEVTYPER12_EL0, 1), 1910 SR_FGT(SYS_AMEVTYPER1_EL0(1), HAFGRTR, AMEVTYPER11_EL0, 1), 1911 SR_FGT(SYS_AMEVTYPER1_EL0(0), HAFGRTR, AMEVTYPER10_EL0, 1), 1912 SR_FGT(SYS_AMEVCNTR1_EL0(15), HAFGRTR, AMEVCNTR115_EL0, 1), 1913 SR_FGT(SYS_AMEVCNTR1_EL0(14), HAFGRTR, AMEVCNTR114_EL0, 1), 1914 SR_FGT(SYS_AMEVCNTR1_EL0(13), HAFGRTR, AMEVCNTR113_EL0, 1), 1915 SR_FGT(SYS_AMEVCNTR1_EL0(12), HAFGRTR, AMEVCNTR112_EL0, 1), 1916 SR_FGT(SYS_AMEVCNTR1_EL0(11), HAFGRTR, AMEVCNTR111_EL0, 1), 1917 SR_FGT(SYS_AMEVCNTR1_EL0(10), HAFGRTR, AMEVCNTR110_EL0, 1), 1918 SR_FGT(SYS_AMEVCNTR1_EL0(9), HAFGRTR, AMEVCNTR19_EL0, 1), 1919 SR_FGT(SYS_AMEVCNTR1_EL0(8), HAFGRTR, AMEVCNTR18_EL0, 1), 1920 SR_FGT(SYS_AMEVCNTR1_EL0(7), HAFGRTR, AMEVCNTR17_EL0, 1), 1921 SR_FGT(SYS_AMEVCNTR1_EL0(6), HAFGRTR, AMEVCNTR16_EL0, 1), 1922 SR_FGT(SYS_AMEVCNTR1_EL0(5), HAFGRTR, AMEVCNTR15_EL0, 1), 1923 SR_FGT(SYS_AMEVCNTR1_EL0(4), HAFGRTR, AMEVCNTR14_EL0, 1), 1924 SR_FGT(SYS_AMEVCNTR1_EL0(3), HAFGRTR, AMEVCNTR13_EL0, 1), 1925 SR_FGT(SYS_AMEVCNTR1_EL0(2), HAFGRTR, AMEVCNTR12_EL0, 1), 1926 SR_FGT(SYS_AMEVCNTR1_EL0(1), HAFGRTR, AMEVCNTR11_EL0, 1), 1927 SR_FGT(SYS_AMEVCNTR1_EL0(0), HAFGRTR, AMEVCNTR10_EL0, 1), 1928 SR_FGT(SYS_AMCNTENCLR1_EL0, HAFGRTR, AMCNTEN1, 1), 1929 SR_FGT(SYS_AMCNTENSET1_EL0, HAFGRTR, AMCNTEN1, 1), 1930 SR_FGT(SYS_AMCNTENCLR0_EL0, HAFGRTR, AMCNTEN0, 1), 1931 SR_FGT(SYS_AMCNTENSET0_EL0, HAFGRTR, AMCNTEN0, 1), 1932 SR_FGT(SYS_AMEVCNTR0_EL0(3), HAFGRTR, AMEVCNTR03_EL0, 1), 1933 SR_FGT(SYS_AMEVCNTR0_EL0(2), HAFGRTR, AMEVCNTR02_EL0, 1), 1934 SR_FGT(SYS_AMEVCNTR0_EL0(1), HAFGRTR, AMEVCNTR01_EL0, 1), 1935 SR_FGT(SYS_AMEVCNTR0_EL0(0), HAFGRTR, AMEVCNTR00_EL0, 1), 1936 }; 1937 1938 static union trap_config get_trap_config(u32 sysreg) 1939 { 1940 return (union trap_config) { 1941 .val = xa_to_value(xa_load(&sr_forward_xa, sysreg)), 1942 }; 1943 } 1944 1945 static __init void print_nv_trap_error(const struct encoding_to_trap_config *tc, 1946 const char *type, int err) 1947 { 1948 kvm_err("%s line %d encoding range " 1949 "(%d, %d, %d, %d, %d) - (%d, %d, %d, %d, %d) (err=%d)\n", 1950 type, tc->line, 1951 sys_reg_Op0(tc->encoding), sys_reg_Op1(tc->encoding), 1952 sys_reg_CRn(tc->encoding), sys_reg_CRm(tc->encoding), 1953 sys_reg_Op2(tc->encoding), 1954 sys_reg_Op0(tc->end), sys_reg_Op1(tc->end), 1955 sys_reg_CRn(tc->end), sys_reg_CRm(tc->end), 1956 sys_reg_Op2(tc->end), 1957 err); 1958 } 1959 1960 static u32 encoding_next(u32 encoding) 1961 { 1962 u8 op0, op1, crn, crm, op2; 1963 1964 op0 = sys_reg_Op0(encoding); 1965 op1 = sys_reg_Op1(encoding); 1966 crn = sys_reg_CRn(encoding); 1967 crm = sys_reg_CRm(encoding); 1968 op2 = sys_reg_Op2(encoding); 1969 1970 if (op2 < Op2_mask) 1971 return sys_reg(op0, op1, crn, crm, op2 + 1); 1972 if (crm < CRm_mask) 1973 return sys_reg(op0, op1, crn, crm + 1, 0); 1974 if (crn < CRn_mask) 1975 return sys_reg(op0, op1, crn + 1, 0, 0); 1976 if (op1 < Op1_mask) 1977 return sys_reg(op0, op1 + 1, 0, 0, 0); 1978 1979 return sys_reg(op0 + 1, 0, 0, 0, 0); 1980 } 1981 1982 int __init populate_nv_trap_config(void) 1983 { 1984 int ret = 0; 1985 1986 BUILD_BUG_ON(sizeof(union trap_config) != sizeof(void *)); 1987 BUILD_BUG_ON(__NR_CGT_GROUP_IDS__ > BIT(TC_CGT_BITS)); 1988 BUILD_BUG_ON(__NR_FGT_GROUP_IDS__ > BIT(TC_FGT_BITS)); 1989 BUILD_BUG_ON(__NR_FG_FILTER_IDS__ > BIT(TC_FGF_BITS)); 1990 1991 for (int i = 0; i < ARRAY_SIZE(encoding_to_cgt); i++) { 1992 const struct encoding_to_trap_config *cgt = &encoding_to_cgt[i]; 1993 void *prev; 1994 1995 if (cgt->tc.val & BIT(63)) { 1996 kvm_err("CGT[%d] has MBZ bit set\n", i); 1997 ret = -EINVAL; 1998 } 1999 2000 for (u32 enc = cgt->encoding; enc <= cgt->end; enc = encoding_next(enc)) { 2001 prev = xa_store(&sr_forward_xa, enc, 2002 xa_mk_value(cgt->tc.val), GFP_KERNEL); 2003 if (prev && !xa_is_err(prev)) { 2004 ret = -EINVAL; 2005 print_nv_trap_error(cgt, "Duplicate CGT", ret); 2006 } 2007 2008 if (xa_is_err(prev)) { 2009 ret = xa_err(prev); 2010 print_nv_trap_error(cgt, "Failed CGT insertion", ret); 2011 } 2012 } 2013 } 2014 2015 kvm_info("nv: %ld coarse grained trap handlers\n", 2016 ARRAY_SIZE(encoding_to_cgt)); 2017 2018 if (!cpus_have_final_cap(ARM64_HAS_FGT)) 2019 goto check_mcb; 2020 2021 for (int i = 0; i < ARRAY_SIZE(encoding_to_fgt); i++) { 2022 const struct encoding_to_trap_config *fgt = &encoding_to_fgt[i]; 2023 union trap_config tc; 2024 void *prev; 2025 2026 if (fgt->tc.fgt >= __NR_FGT_GROUP_IDS__) { 2027 ret = -EINVAL; 2028 print_nv_trap_error(fgt, "Invalid FGT", ret); 2029 } 2030 2031 tc = get_trap_config(fgt->encoding); 2032 2033 if (tc.fgt) { 2034 ret = -EINVAL; 2035 print_nv_trap_error(fgt, "Duplicate FGT", ret); 2036 } 2037 2038 tc.val |= fgt->tc.val; 2039 prev = xa_store(&sr_forward_xa, fgt->encoding, 2040 xa_mk_value(tc.val), GFP_KERNEL); 2041 2042 if (xa_is_err(prev)) { 2043 ret = xa_err(prev); 2044 print_nv_trap_error(fgt, "Failed FGT insertion", ret); 2045 } 2046 } 2047 2048 kvm_info("nv: %ld fine grained trap handlers\n", 2049 ARRAY_SIZE(encoding_to_fgt)); 2050 2051 check_mcb: 2052 for (int id = __MULTIPLE_CONTROL_BITS__; id < __COMPLEX_CONDITIONS__; id++) { 2053 const enum cgt_group_id *cgids; 2054 2055 cgids = coarse_control_combo[id - __MULTIPLE_CONTROL_BITS__]; 2056 2057 for (int i = 0; cgids[i] != __RESERVED__; i++) { 2058 if (cgids[i] >= __MULTIPLE_CONTROL_BITS__ && 2059 cgids[i] < __COMPLEX_CONDITIONS__) { 2060 kvm_err("Recursive MCB %d/%d\n", id, cgids[i]); 2061 ret = -EINVAL; 2062 } 2063 } 2064 } 2065 2066 if (ret) 2067 xa_destroy(&sr_forward_xa); 2068 2069 return ret; 2070 } 2071 2072 int __init populate_sysreg_config(const struct sys_reg_desc *sr, 2073 unsigned int idx) 2074 { 2075 union trap_config tc; 2076 u32 encoding; 2077 void *ret; 2078 2079 /* 2080 * 0 is a valid value for the index, but not for the storage. 2081 * We'll store (idx+1), so check against an offset'd limit. 2082 */ 2083 if (idx >= (BIT(TC_SRI_BITS) - 1)) { 2084 kvm_err("sysreg %s (%d) out of range\n", sr->name, idx); 2085 return -EINVAL; 2086 } 2087 2088 encoding = sys_reg(sr->Op0, sr->Op1, sr->CRn, sr->CRm, sr->Op2); 2089 tc = get_trap_config(encoding); 2090 2091 if (tc.sri) { 2092 kvm_err("sysreg %s (%d) duplicate entry (%d)\n", 2093 sr->name, idx - 1, tc.sri); 2094 return -EINVAL; 2095 } 2096 2097 tc.sri = idx + 1; 2098 ret = xa_store(&sr_forward_xa, encoding, 2099 xa_mk_value(tc.val), GFP_KERNEL); 2100 2101 return xa_err(ret); 2102 } 2103 2104 static enum trap_behaviour get_behaviour(struct kvm_vcpu *vcpu, 2105 const struct trap_bits *tb) 2106 { 2107 enum trap_behaviour b = BEHAVE_HANDLE_LOCALLY; 2108 u64 val; 2109 2110 val = __vcpu_sys_reg(vcpu, tb->index); 2111 if ((val & tb->mask) == tb->value) 2112 b |= tb->behaviour; 2113 2114 return b; 2115 } 2116 2117 static enum trap_behaviour __compute_trap_behaviour(struct kvm_vcpu *vcpu, 2118 const enum cgt_group_id id, 2119 enum trap_behaviour b) 2120 { 2121 switch (id) { 2122 const enum cgt_group_id *cgids; 2123 2124 case __RESERVED__ ... __MULTIPLE_CONTROL_BITS__ - 1: 2125 if (likely(id != __RESERVED__)) 2126 b |= get_behaviour(vcpu, &coarse_trap_bits[id]); 2127 break; 2128 case __MULTIPLE_CONTROL_BITS__ ... __COMPLEX_CONDITIONS__ - 1: 2129 /* Yes, this is recursive. Don't do anything stupid. */ 2130 cgids = coarse_control_combo[id - __MULTIPLE_CONTROL_BITS__]; 2131 for (int i = 0; cgids[i] != __RESERVED__; i++) 2132 b |= __compute_trap_behaviour(vcpu, cgids[i], b); 2133 break; 2134 default: 2135 if (ARRAY_SIZE(ccc)) 2136 b |= ccc[id - __COMPLEX_CONDITIONS__](vcpu); 2137 break; 2138 } 2139 2140 return b; 2141 } 2142 2143 static enum trap_behaviour compute_trap_behaviour(struct kvm_vcpu *vcpu, 2144 const union trap_config tc) 2145 { 2146 enum trap_behaviour b = BEHAVE_HANDLE_LOCALLY; 2147 2148 return __compute_trap_behaviour(vcpu, tc.cgt, b); 2149 } 2150 2151 static u64 kvm_get_sysreg_res0(struct kvm *kvm, enum vcpu_sysreg sr) 2152 { 2153 struct kvm_sysreg_masks *masks; 2154 2155 /* Only handle the VNCR-backed regs for now */ 2156 if (sr < __VNCR_START__) 2157 return 0; 2158 2159 masks = kvm->arch.sysreg_masks; 2160 2161 return masks->mask[sr - __VNCR_START__].res0; 2162 } 2163 2164 static bool check_fgt_bit(struct kvm_vcpu *vcpu, bool is_read, 2165 u64 val, const union trap_config tc) 2166 { 2167 struct kvm *kvm = vcpu->kvm; 2168 enum vcpu_sysreg sr; 2169 2170 /* 2171 * KVM doesn't know about any FGTs that apply to the host, and hopefully 2172 * that'll remain the case. 2173 */ 2174 if (is_hyp_ctxt(vcpu)) 2175 return false; 2176 2177 if (tc.pol) 2178 return (val & BIT(tc.bit)); 2179 2180 /* 2181 * FGTs with negative polarities are an absolute nightmare, as 2182 * we need to evaluate the bit in the light of the feature 2183 * that defines it. WTF were they thinking? 2184 * 2185 * So let's check if the bit has been earmarked as RES0, as 2186 * this indicates an unimplemented feature. 2187 */ 2188 if (val & BIT(tc.bit)) 2189 return false; 2190 2191 switch ((enum fgt_group_id)tc.fgt) { 2192 case HFGxTR_GROUP: 2193 sr = is_read ? HFGRTR_EL2 : HFGWTR_EL2; 2194 break; 2195 2196 case HDFGRTR_GROUP: 2197 sr = is_read ? HDFGRTR_EL2 : HDFGWTR_EL2; 2198 break; 2199 2200 case HAFGRTR_GROUP: 2201 sr = HAFGRTR_EL2; 2202 break; 2203 2204 case HFGITR_GROUP: 2205 sr = HFGITR_EL2; 2206 break; 2207 2208 default: 2209 WARN_ONCE(1, "Unhandled FGT group"); 2210 return false; 2211 } 2212 2213 return !(kvm_get_sysreg_res0(kvm, sr) & BIT(tc.bit)); 2214 } 2215 2216 bool triage_sysreg_trap(struct kvm_vcpu *vcpu, int *sr_index) 2217 { 2218 union trap_config tc; 2219 enum trap_behaviour b; 2220 bool is_read; 2221 u32 sysreg; 2222 u64 esr, val; 2223 2224 esr = kvm_vcpu_get_esr(vcpu); 2225 sysreg = esr_sys64_to_sysreg(esr); 2226 is_read = (esr & ESR_ELx_SYS64_ISS_DIR_MASK) == ESR_ELx_SYS64_ISS_DIR_READ; 2227 2228 tc = get_trap_config(sysreg); 2229 2230 /* 2231 * A value of 0 for the whole entry means that we know nothing 2232 * for this sysreg, and that it cannot be re-injected into the 2233 * nested hypervisor. In this situation, let's cut it short. 2234 */ 2235 if (!tc.val) 2236 goto local; 2237 2238 /* 2239 * If a sysreg can be trapped using a FGT, first check whether we 2240 * trap for the purpose of forbidding the feature. In that case, 2241 * inject an UNDEF. 2242 */ 2243 if (tc.fgt != __NO_FGT_GROUP__ && 2244 (vcpu->kvm->arch.fgu[tc.fgt] & BIT(tc.bit))) { 2245 kvm_inject_undefined(vcpu); 2246 return true; 2247 } 2248 2249 /* 2250 * If we're not nesting, immediately return to the caller, with the 2251 * sysreg index, should we have it. 2252 */ 2253 if (!vcpu_has_nv(vcpu)) 2254 goto local; 2255 2256 /* 2257 * There are a few traps that take effect InHost, but are constrained 2258 * to EL0. Don't bother with computing the trap behaviour if the vCPU 2259 * isn't in EL0. 2260 */ 2261 if (is_hyp_ctxt(vcpu) && !vcpu_is_host_el0(vcpu)) 2262 goto local; 2263 2264 switch ((enum fgt_group_id)tc.fgt) { 2265 case __NO_FGT_GROUP__: 2266 break; 2267 2268 case HFGxTR_GROUP: 2269 if (is_read) 2270 val = __vcpu_sys_reg(vcpu, HFGRTR_EL2); 2271 else 2272 val = __vcpu_sys_reg(vcpu, HFGWTR_EL2); 2273 break; 2274 2275 case HDFGRTR_GROUP: 2276 if (is_read) 2277 val = __vcpu_sys_reg(vcpu, HDFGRTR_EL2); 2278 else 2279 val = __vcpu_sys_reg(vcpu, HDFGWTR_EL2); 2280 break; 2281 2282 case HAFGRTR_GROUP: 2283 val = __vcpu_sys_reg(vcpu, HAFGRTR_EL2); 2284 break; 2285 2286 case HFGITR_GROUP: 2287 val = __vcpu_sys_reg(vcpu, HFGITR_EL2); 2288 switch (tc.fgf) { 2289 u64 tmp; 2290 2291 case __NO_FGF__: 2292 break; 2293 2294 case HCRX_FGTnXS: 2295 tmp = __vcpu_sys_reg(vcpu, HCRX_EL2); 2296 if (tmp & HCRX_EL2_FGTnXS) 2297 tc.fgt = __NO_FGT_GROUP__; 2298 } 2299 break; 2300 2301 case __NR_FGT_GROUP_IDS__: 2302 /* Something is really wrong, bail out */ 2303 WARN_ONCE(1, "__NR_FGT_GROUP_IDS__"); 2304 goto local; 2305 } 2306 2307 if (tc.fgt != __NO_FGT_GROUP__ && check_fgt_bit(vcpu, is_read, val, tc)) 2308 goto inject; 2309 2310 b = compute_trap_behaviour(vcpu, tc); 2311 2312 if (!(b & BEHAVE_FORWARD_IN_HOST_EL0) && vcpu_is_host_el0(vcpu)) 2313 goto local; 2314 2315 if (((b & BEHAVE_FORWARD_READ) && is_read) || 2316 ((b & BEHAVE_FORWARD_WRITE) && !is_read)) 2317 goto inject; 2318 2319 local: 2320 if (!tc.sri) { 2321 struct sys_reg_params params; 2322 2323 params = esr_sys64_to_params(esr); 2324 2325 /* 2326 * Check for the IMPDEF range, as per DDI0487 J.a, 2327 * D18.3.2 Reserved encodings for IMPLEMENTATION 2328 * DEFINED registers. 2329 */ 2330 if (!(params.Op0 == 3 && (params.CRn & 0b1011) == 0b1011)) 2331 print_sys_reg_msg(¶ms, 2332 "Unsupported guest access at: %lx\n", 2333 *vcpu_pc(vcpu)); 2334 kvm_inject_undefined(vcpu); 2335 return true; 2336 } 2337 2338 *sr_index = tc.sri - 1; 2339 return false; 2340 2341 inject: 2342 trace_kvm_forward_sysreg_trap(vcpu, sysreg, is_read); 2343 2344 kvm_inject_nested_sync(vcpu, kvm_vcpu_get_esr(vcpu)); 2345 return true; 2346 } 2347 2348 static bool forward_traps(struct kvm_vcpu *vcpu, u64 control_bit) 2349 { 2350 bool control_bit_set; 2351 2352 if (!vcpu_has_nv(vcpu)) 2353 return false; 2354 2355 control_bit_set = __vcpu_sys_reg(vcpu, HCR_EL2) & control_bit; 2356 if (!is_hyp_ctxt(vcpu) && control_bit_set) { 2357 kvm_inject_nested_sync(vcpu, kvm_vcpu_get_esr(vcpu)); 2358 return true; 2359 } 2360 return false; 2361 } 2362 2363 bool forward_smc_trap(struct kvm_vcpu *vcpu) 2364 { 2365 return forward_traps(vcpu, HCR_TSC); 2366 } 2367 2368 static u64 kvm_check_illegal_exception_return(struct kvm_vcpu *vcpu, u64 spsr) 2369 { 2370 u64 mode = spsr & PSR_MODE_MASK; 2371 2372 /* 2373 * Possible causes for an Illegal Exception Return from EL2: 2374 * - trying to return to EL3 2375 * - trying to return to an illegal M value 2376 * - trying to return to a 32bit EL 2377 * - trying to return to EL1 with HCR_EL2.TGE set 2378 */ 2379 if (mode == PSR_MODE_EL3t || mode == PSR_MODE_EL3h || 2380 mode == 0b00001 || (mode & BIT(1)) || 2381 (spsr & PSR_MODE32_BIT) || 2382 (vcpu_el2_tge_is_set(vcpu) && (mode == PSR_MODE_EL1t || 2383 mode == PSR_MODE_EL1h))) { 2384 /* 2385 * The guest is playing with our nerves. Preserve EL, SP, 2386 * masks, flags from the existing PSTATE, and set IL. 2387 * The HW will then generate an Illegal State Exception 2388 * immediately after ERET. 2389 */ 2390 spsr = *vcpu_cpsr(vcpu); 2391 2392 spsr &= (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT | 2393 PSR_N_BIT | PSR_Z_BIT | PSR_C_BIT | PSR_V_BIT | 2394 PSR_MODE_MASK | PSR_MODE32_BIT); 2395 spsr |= PSR_IL_BIT; 2396 } 2397 2398 return spsr; 2399 } 2400 2401 void kvm_emulate_nested_eret(struct kvm_vcpu *vcpu) 2402 { 2403 u64 spsr, elr, esr; 2404 2405 /* 2406 * Forward this trap to the virtual EL2 if the virtual 2407 * HCR_EL2.NV bit is set and this is coming from !EL2. 2408 */ 2409 if (forward_traps(vcpu, HCR_NV)) 2410 return; 2411 2412 spsr = vcpu_read_sys_reg(vcpu, SPSR_EL2); 2413 spsr = kvm_check_illegal_exception_return(vcpu, spsr); 2414 2415 /* Check for an ERETAx */ 2416 esr = kvm_vcpu_get_esr(vcpu); 2417 if (esr_iss_is_eretax(esr) && !kvm_auth_eretax(vcpu, &elr)) { 2418 /* 2419 * Oh no, ERETAx failed to authenticate. 2420 * 2421 * If we have FPACCOMBINE and we don't have a pending 2422 * Illegal Execution State exception (which has priority 2423 * over FPAC), deliver an exception right away. 2424 * 2425 * Otherwise, let the mangled ELR value trickle down the 2426 * ERET handling, and the guest will have a little surprise. 2427 */ 2428 if (kvm_has_pauth(vcpu->kvm, FPACCOMBINE) && !(spsr & PSR_IL_BIT)) { 2429 esr &= ESR_ELx_ERET_ISS_ERETA; 2430 esr |= FIELD_PREP(ESR_ELx_EC_MASK, ESR_ELx_EC_FPAC); 2431 kvm_inject_nested_sync(vcpu, esr); 2432 return; 2433 } 2434 } 2435 2436 preempt_disable(); 2437 kvm_arch_vcpu_put(vcpu); 2438 2439 if (!esr_iss_is_eretax(esr)) 2440 elr = __vcpu_sys_reg(vcpu, ELR_EL2); 2441 2442 trace_kvm_nested_eret(vcpu, elr, spsr); 2443 2444 *vcpu_pc(vcpu) = elr; 2445 *vcpu_cpsr(vcpu) = spsr; 2446 2447 kvm_arch_vcpu_load(vcpu, smp_processor_id()); 2448 preempt_enable(); 2449 2450 kvm_pmu_nested_transition(vcpu); 2451 } 2452 2453 static void kvm_inject_el2_exception(struct kvm_vcpu *vcpu, u64 esr_el2, 2454 enum exception_type type) 2455 { 2456 trace_kvm_inject_nested_exception(vcpu, esr_el2, type); 2457 2458 switch (type) { 2459 case except_type_sync: 2460 kvm_pend_exception(vcpu, EXCEPT_AA64_EL2_SYNC); 2461 vcpu_write_sys_reg(vcpu, esr_el2, ESR_EL2); 2462 break; 2463 case except_type_irq: 2464 kvm_pend_exception(vcpu, EXCEPT_AA64_EL2_IRQ); 2465 break; 2466 default: 2467 WARN_ONCE(1, "Unsupported EL2 exception injection %d\n", type); 2468 } 2469 } 2470 2471 /* 2472 * Emulate taking an exception to EL2. 2473 * See ARM ARM J8.1.2 AArch64.TakeException() 2474 */ 2475 static int kvm_inject_nested(struct kvm_vcpu *vcpu, u64 esr_el2, 2476 enum exception_type type) 2477 { 2478 u64 pstate, mode; 2479 bool direct_inject; 2480 2481 if (!vcpu_has_nv(vcpu)) { 2482 kvm_err("Unexpected call to %s for the non-nesting configuration\n", 2483 __func__); 2484 return -EINVAL; 2485 } 2486 2487 /* 2488 * As for ERET, we can avoid doing too much on the injection path by 2489 * checking that we either took the exception from a VHE host 2490 * userspace or from vEL2. In these cases, there is no change in 2491 * translation regime (or anything else), so let's do as little as 2492 * possible. 2493 */ 2494 pstate = *vcpu_cpsr(vcpu); 2495 mode = pstate & (PSR_MODE_MASK | PSR_MODE32_BIT); 2496 2497 direct_inject = (mode == PSR_MODE_EL0t && 2498 vcpu_el2_e2h_is_set(vcpu) && 2499 vcpu_el2_tge_is_set(vcpu)); 2500 direct_inject |= (mode == PSR_MODE_EL2h || mode == PSR_MODE_EL2t); 2501 2502 if (direct_inject) { 2503 kvm_inject_el2_exception(vcpu, esr_el2, type); 2504 return 1; 2505 } 2506 2507 preempt_disable(); 2508 2509 /* 2510 * We may have an exception or PC update in the EL0/EL1 context. 2511 * Commit it before entering EL2. 2512 */ 2513 __kvm_adjust_pc(vcpu); 2514 2515 kvm_arch_vcpu_put(vcpu); 2516 2517 kvm_inject_el2_exception(vcpu, esr_el2, type); 2518 2519 /* 2520 * A hard requirement is that a switch between EL1 and EL2 2521 * contexts has to happen between a put/load, so that we can 2522 * pick the correct timer and interrupt configuration, among 2523 * other things. 2524 * 2525 * Make sure the exception actually took place before we load 2526 * the new context. 2527 */ 2528 __kvm_adjust_pc(vcpu); 2529 2530 kvm_arch_vcpu_load(vcpu, smp_processor_id()); 2531 preempt_enable(); 2532 2533 kvm_pmu_nested_transition(vcpu); 2534 2535 return 1; 2536 } 2537 2538 int kvm_inject_nested_sync(struct kvm_vcpu *vcpu, u64 esr_el2) 2539 { 2540 return kvm_inject_nested(vcpu, esr_el2, except_type_sync); 2541 } 2542 2543 int kvm_inject_nested_irq(struct kvm_vcpu *vcpu) 2544 { 2545 /* 2546 * Do not inject an irq if the: 2547 * - Current exception level is EL2, and 2548 * - virtual HCR_EL2.TGE == 0 2549 * - virtual HCR_EL2.IMO == 0 2550 * 2551 * See Table D1-17 "Physical interrupt target and masking when EL3 is 2552 * not implemented and EL2 is implemented" in ARM DDI 0487C.a. 2553 */ 2554 2555 if (vcpu_is_el2(vcpu) && !vcpu_el2_tge_is_set(vcpu) && 2556 !(__vcpu_sys_reg(vcpu, HCR_EL2) & HCR_IMO)) 2557 return 1; 2558 2559 /* esr_el2 value doesn't matter for exits due to irqs. */ 2560 return kvm_inject_nested(vcpu, 0, except_type_irq); 2561 } 2562