1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2016 - Linaro and Columbia University 4 * Author: Jintack Lim <jintack.lim@linaro.org> 5 */ 6 7 #include <linux/kvm.h> 8 #include <linux/kvm_host.h> 9 10 #include <asm/kvm_emulate.h> 11 #include <asm/kvm_nested.h> 12 13 #include "hyp/include/hyp/adjust_pc.h" 14 15 #include "trace.h" 16 17 enum trap_behaviour { 18 BEHAVE_HANDLE_LOCALLY = 0, 19 BEHAVE_FORWARD_READ = BIT(0), 20 BEHAVE_FORWARD_WRITE = BIT(1), 21 BEHAVE_FORWARD_ANY = BEHAVE_FORWARD_READ | BEHAVE_FORWARD_WRITE, 22 }; 23 24 struct trap_bits { 25 const enum vcpu_sysreg index; 26 const enum trap_behaviour behaviour; 27 const u64 value; 28 const u64 mask; 29 }; 30 31 /* Coarse Grained Trap definitions */ 32 enum cgt_group_id { 33 /* Indicates no coarse trap control */ 34 __RESERVED__, 35 36 /* 37 * The first batch of IDs denote coarse trapping that are used 38 * on their own instead of being part of a combination of 39 * trap controls. 40 */ 41 CGT_HCR_TID1, 42 CGT_HCR_TID2, 43 CGT_HCR_TID3, 44 CGT_HCR_IMO, 45 CGT_HCR_FMO, 46 CGT_HCR_TIDCP, 47 CGT_HCR_TACR, 48 CGT_HCR_TSW, 49 CGT_HCR_TPC, 50 CGT_HCR_TPU, 51 CGT_HCR_TTLB, 52 CGT_HCR_TVM, 53 CGT_HCR_TDZ, 54 CGT_HCR_TRVM, 55 CGT_HCR_TLOR, 56 CGT_HCR_TERR, 57 CGT_HCR_APK, 58 CGT_HCR_NV, 59 CGT_HCR_NV_nNV2, 60 CGT_HCR_NV1_nNV2, 61 CGT_HCR_AT, 62 CGT_HCR_nFIEN, 63 CGT_HCR_TID4, 64 CGT_HCR_TICAB, 65 CGT_HCR_TOCU, 66 CGT_HCR_ENSCXT, 67 CGT_HCR_TTLBIS, 68 CGT_HCR_TTLBOS, 69 70 CGT_MDCR_TPMCR, 71 CGT_MDCR_TPM, 72 CGT_MDCR_TDE, 73 CGT_MDCR_TDA, 74 CGT_MDCR_TDOSA, 75 CGT_MDCR_TDRA, 76 CGT_MDCR_E2PB, 77 CGT_MDCR_TPMS, 78 CGT_MDCR_TTRF, 79 CGT_MDCR_E2TB, 80 CGT_MDCR_TDCC, 81 82 /* 83 * Anything after this point is a combination of coarse trap 84 * controls, which must all be evaluated to decide what to do. 85 */ 86 __MULTIPLE_CONTROL_BITS__, 87 CGT_HCR_IMO_FMO = __MULTIPLE_CONTROL_BITS__, 88 CGT_HCR_TID2_TID4, 89 CGT_HCR_TTLB_TTLBIS, 90 CGT_HCR_TTLB_TTLBOS, 91 CGT_HCR_TVM_TRVM, 92 CGT_HCR_TPU_TICAB, 93 CGT_HCR_TPU_TOCU, 94 CGT_HCR_NV1_nNV2_ENSCXT, 95 CGT_MDCR_TPM_TPMCR, 96 CGT_MDCR_TDE_TDA, 97 CGT_MDCR_TDE_TDOSA, 98 CGT_MDCR_TDE_TDRA, 99 CGT_MDCR_TDCC_TDE_TDA, 100 101 /* 102 * Anything after this point requires a callback evaluating a 103 * complex trap condition. Ugly stuff. 104 */ 105 __COMPLEX_CONDITIONS__, 106 CGT_CNTHCTL_EL1PCTEN = __COMPLEX_CONDITIONS__, 107 CGT_CNTHCTL_EL1PTEN, 108 109 /* Must be last */ 110 __NR_CGT_GROUP_IDS__ 111 }; 112 113 static const struct trap_bits coarse_trap_bits[] = { 114 [CGT_HCR_TID1] = { 115 .index = HCR_EL2, 116 .value = HCR_TID1, 117 .mask = HCR_TID1, 118 .behaviour = BEHAVE_FORWARD_READ, 119 }, 120 [CGT_HCR_TID2] = { 121 .index = HCR_EL2, 122 .value = HCR_TID2, 123 .mask = HCR_TID2, 124 .behaviour = BEHAVE_FORWARD_ANY, 125 }, 126 [CGT_HCR_TID3] = { 127 .index = HCR_EL2, 128 .value = HCR_TID3, 129 .mask = HCR_TID3, 130 .behaviour = BEHAVE_FORWARD_READ, 131 }, 132 [CGT_HCR_IMO] = { 133 .index = HCR_EL2, 134 .value = HCR_IMO, 135 .mask = HCR_IMO, 136 .behaviour = BEHAVE_FORWARD_WRITE, 137 }, 138 [CGT_HCR_FMO] = { 139 .index = HCR_EL2, 140 .value = HCR_FMO, 141 .mask = HCR_FMO, 142 .behaviour = BEHAVE_FORWARD_WRITE, 143 }, 144 [CGT_HCR_TIDCP] = { 145 .index = HCR_EL2, 146 .value = HCR_TIDCP, 147 .mask = HCR_TIDCP, 148 .behaviour = BEHAVE_FORWARD_ANY, 149 }, 150 [CGT_HCR_TACR] = { 151 .index = HCR_EL2, 152 .value = HCR_TACR, 153 .mask = HCR_TACR, 154 .behaviour = BEHAVE_FORWARD_ANY, 155 }, 156 [CGT_HCR_TSW] = { 157 .index = HCR_EL2, 158 .value = HCR_TSW, 159 .mask = HCR_TSW, 160 .behaviour = BEHAVE_FORWARD_ANY, 161 }, 162 [CGT_HCR_TPC] = { /* Also called TCPC when FEAT_DPB is implemented */ 163 .index = HCR_EL2, 164 .value = HCR_TPC, 165 .mask = HCR_TPC, 166 .behaviour = BEHAVE_FORWARD_ANY, 167 }, 168 [CGT_HCR_TPU] = { 169 .index = HCR_EL2, 170 .value = HCR_TPU, 171 .mask = HCR_TPU, 172 .behaviour = BEHAVE_FORWARD_ANY, 173 }, 174 [CGT_HCR_TTLB] = { 175 .index = HCR_EL2, 176 .value = HCR_TTLB, 177 .mask = HCR_TTLB, 178 .behaviour = BEHAVE_FORWARD_ANY, 179 }, 180 [CGT_HCR_TVM] = { 181 .index = HCR_EL2, 182 .value = HCR_TVM, 183 .mask = HCR_TVM, 184 .behaviour = BEHAVE_FORWARD_WRITE, 185 }, 186 [CGT_HCR_TDZ] = { 187 .index = HCR_EL2, 188 .value = HCR_TDZ, 189 .mask = HCR_TDZ, 190 .behaviour = BEHAVE_FORWARD_ANY, 191 }, 192 [CGT_HCR_TRVM] = { 193 .index = HCR_EL2, 194 .value = HCR_TRVM, 195 .mask = HCR_TRVM, 196 .behaviour = BEHAVE_FORWARD_READ, 197 }, 198 [CGT_HCR_TLOR] = { 199 .index = HCR_EL2, 200 .value = HCR_TLOR, 201 .mask = HCR_TLOR, 202 .behaviour = BEHAVE_FORWARD_ANY, 203 }, 204 [CGT_HCR_TERR] = { 205 .index = HCR_EL2, 206 .value = HCR_TERR, 207 .mask = HCR_TERR, 208 .behaviour = BEHAVE_FORWARD_ANY, 209 }, 210 [CGT_HCR_APK] = { 211 .index = HCR_EL2, 212 .value = 0, 213 .mask = HCR_APK, 214 .behaviour = BEHAVE_FORWARD_ANY, 215 }, 216 [CGT_HCR_NV] = { 217 .index = HCR_EL2, 218 .value = HCR_NV, 219 .mask = HCR_NV, 220 .behaviour = BEHAVE_FORWARD_ANY, 221 }, 222 [CGT_HCR_NV_nNV2] = { 223 .index = HCR_EL2, 224 .value = HCR_NV, 225 .mask = HCR_NV | HCR_NV2, 226 .behaviour = BEHAVE_FORWARD_ANY, 227 }, 228 [CGT_HCR_NV1_nNV2] = { 229 .index = HCR_EL2, 230 .value = HCR_NV | HCR_NV1, 231 .mask = HCR_NV | HCR_NV1 | HCR_NV2, 232 .behaviour = BEHAVE_FORWARD_ANY, 233 }, 234 [CGT_HCR_AT] = { 235 .index = HCR_EL2, 236 .value = HCR_AT, 237 .mask = HCR_AT, 238 .behaviour = BEHAVE_FORWARD_ANY, 239 }, 240 [CGT_HCR_nFIEN] = { 241 .index = HCR_EL2, 242 .value = 0, 243 .mask = HCR_FIEN, 244 .behaviour = BEHAVE_FORWARD_ANY, 245 }, 246 [CGT_HCR_TID4] = { 247 .index = HCR_EL2, 248 .value = HCR_TID4, 249 .mask = HCR_TID4, 250 .behaviour = BEHAVE_FORWARD_ANY, 251 }, 252 [CGT_HCR_TICAB] = { 253 .index = HCR_EL2, 254 .value = HCR_TICAB, 255 .mask = HCR_TICAB, 256 .behaviour = BEHAVE_FORWARD_ANY, 257 }, 258 [CGT_HCR_TOCU] = { 259 .index = HCR_EL2, 260 .value = HCR_TOCU, 261 .mask = HCR_TOCU, 262 .behaviour = BEHAVE_FORWARD_ANY, 263 }, 264 [CGT_HCR_ENSCXT] = { 265 .index = HCR_EL2, 266 .value = 0, 267 .mask = HCR_ENSCXT, 268 .behaviour = BEHAVE_FORWARD_ANY, 269 }, 270 [CGT_HCR_TTLBIS] = { 271 .index = HCR_EL2, 272 .value = HCR_TTLBIS, 273 .mask = HCR_TTLBIS, 274 .behaviour = BEHAVE_FORWARD_ANY, 275 }, 276 [CGT_HCR_TTLBOS] = { 277 .index = HCR_EL2, 278 .value = HCR_TTLBOS, 279 .mask = HCR_TTLBOS, 280 .behaviour = BEHAVE_FORWARD_ANY, 281 }, 282 [CGT_MDCR_TPMCR] = { 283 .index = MDCR_EL2, 284 .value = MDCR_EL2_TPMCR, 285 .mask = MDCR_EL2_TPMCR, 286 .behaviour = BEHAVE_FORWARD_ANY, 287 }, 288 [CGT_MDCR_TPM] = { 289 .index = MDCR_EL2, 290 .value = MDCR_EL2_TPM, 291 .mask = MDCR_EL2_TPM, 292 .behaviour = BEHAVE_FORWARD_ANY, 293 }, 294 [CGT_MDCR_TDE] = { 295 .index = MDCR_EL2, 296 .value = MDCR_EL2_TDE, 297 .mask = MDCR_EL2_TDE, 298 .behaviour = BEHAVE_FORWARD_ANY, 299 }, 300 [CGT_MDCR_TDA] = { 301 .index = MDCR_EL2, 302 .value = MDCR_EL2_TDA, 303 .mask = MDCR_EL2_TDA, 304 .behaviour = BEHAVE_FORWARD_ANY, 305 }, 306 [CGT_MDCR_TDOSA] = { 307 .index = MDCR_EL2, 308 .value = MDCR_EL2_TDOSA, 309 .mask = MDCR_EL2_TDOSA, 310 .behaviour = BEHAVE_FORWARD_ANY, 311 }, 312 [CGT_MDCR_TDRA] = { 313 .index = MDCR_EL2, 314 .value = MDCR_EL2_TDRA, 315 .mask = MDCR_EL2_TDRA, 316 .behaviour = BEHAVE_FORWARD_ANY, 317 }, 318 [CGT_MDCR_E2PB] = { 319 .index = MDCR_EL2, 320 .value = 0, 321 .mask = BIT(MDCR_EL2_E2PB_SHIFT), 322 .behaviour = BEHAVE_FORWARD_ANY, 323 }, 324 [CGT_MDCR_TPMS] = { 325 .index = MDCR_EL2, 326 .value = MDCR_EL2_TPMS, 327 .mask = MDCR_EL2_TPMS, 328 .behaviour = BEHAVE_FORWARD_ANY, 329 }, 330 [CGT_MDCR_TTRF] = { 331 .index = MDCR_EL2, 332 .value = MDCR_EL2_TTRF, 333 .mask = MDCR_EL2_TTRF, 334 .behaviour = BEHAVE_FORWARD_ANY, 335 }, 336 [CGT_MDCR_E2TB] = { 337 .index = MDCR_EL2, 338 .value = 0, 339 .mask = BIT(MDCR_EL2_E2TB_SHIFT), 340 .behaviour = BEHAVE_FORWARD_ANY, 341 }, 342 [CGT_MDCR_TDCC] = { 343 .index = MDCR_EL2, 344 .value = MDCR_EL2_TDCC, 345 .mask = MDCR_EL2_TDCC, 346 .behaviour = BEHAVE_FORWARD_ANY, 347 }, 348 }; 349 350 #define MCB(id, ...) \ 351 [id - __MULTIPLE_CONTROL_BITS__] = \ 352 (const enum cgt_group_id[]){ \ 353 __VA_ARGS__, __RESERVED__ \ 354 } 355 356 static const enum cgt_group_id *coarse_control_combo[] = { 357 MCB(CGT_HCR_IMO_FMO, CGT_HCR_IMO, CGT_HCR_FMO), 358 MCB(CGT_HCR_TID2_TID4, CGT_HCR_TID2, CGT_HCR_TID4), 359 MCB(CGT_HCR_TTLB_TTLBIS, CGT_HCR_TTLB, CGT_HCR_TTLBIS), 360 MCB(CGT_HCR_TTLB_TTLBOS, CGT_HCR_TTLB, CGT_HCR_TTLBOS), 361 MCB(CGT_HCR_TVM_TRVM, CGT_HCR_TVM, CGT_HCR_TRVM), 362 MCB(CGT_HCR_TPU_TICAB, CGT_HCR_TPU, CGT_HCR_TICAB), 363 MCB(CGT_HCR_TPU_TOCU, CGT_HCR_TPU, CGT_HCR_TOCU), 364 MCB(CGT_HCR_NV1_nNV2_ENSCXT, CGT_HCR_NV1_nNV2, CGT_HCR_ENSCXT), 365 MCB(CGT_MDCR_TPM_TPMCR, CGT_MDCR_TPM, CGT_MDCR_TPMCR), 366 MCB(CGT_MDCR_TDE_TDA, CGT_MDCR_TDE, CGT_MDCR_TDA), 367 MCB(CGT_MDCR_TDE_TDOSA, CGT_MDCR_TDE, CGT_MDCR_TDOSA), 368 MCB(CGT_MDCR_TDE_TDRA, CGT_MDCR_TDE, CGT_MDCR_TDRA), 369 MCB(CGT_MDCR_TDCC_TDE_TDA, CGT_MDCR_TDCC, CGT_MDCR_TDE, CGT_MDCR_TDA), 370 }; 371 372 typedef enum trap_behaviour (*complex_condition_check)(struct kvm_vcpu *); 373 374 /* 375 * Warning, maximum confusion ahead. 376 * 377 * When E2H=0, CNTHCTL_EL2[1:0] are defined as EL1PCEN:EL1PCTEN 378 * When E2H=1, CNTHCTL_EL2[11:10] are defined as EL1PTEN:EL1PCTEN 379 * 380 * Note the single letter difference? Yet, the bits have the same 381 * function despite a different layout and a different name. 382 * 383 * We don't try to reconcile this mess. We just use the E2H=0 bits 384 * to generate something that is in the E2H=1 format, and live with 385 * it. You're welcome. 386 */ 387 static u64 get_sanitized_cnthctl(struct kvm_vcpu *vcpu) 388 { 389 u64 val = __vcpu_sys_reg(vcpu, CNTHCTL_EL2); 390 391 if (!vcpu_el2_e2h_is_set(vcpu)) 392 val = (val & (CNTHCTL_EL1PCEN | CNTHCTL_EL1PCTEN)) << 10; 393 394 return val & ((CNTHCTL_EL1PCEN | CNTHCTL_EL1PCTEN) << 10); 395 } 396 397 static enum trap_behaviour check_cnthctl_el1pcten(struct kvm_vcpu *vcpu) 398 { 399 if (get_sanitized_cnthctl(vcpu) & (CNTHCTL_EL1PCTEN << 10)) 400 return BEHAVE_HANDLE_LOCALLY; 401 402 return BEHAVE_FORWARD_ANY; 403 } 404 405 static enum trap_behaviour check_cnthctl_el1pten(struct kvm_vcpu *vcpu) 406 { 407 if (get_sanitized_cnthctl(vcpu) & (CNTHCTL_EL1PCEN << 10)) 408 return BEHAVE_HANDLE_LOCALLY; 409 410 return BEHAVE_FORWARD_ANY; 411 } 412 413 #define CCC(id, fn) \ 414 [id - __COMPLEX_CONDITIONS__] = fn 415 416 static const complex_condition_check ccc[] = { 417 CCC(CGT_CNTHCTL_EL1PCTEN, check_cnthctl_el1pcten), 418 CCC(CGT_CNTHCTL_EL1PTEN, check_cnthctl_el1pten), 419 }; 420 421 /* 422 * Bit assignment for the trap controls. We use a 64bit word with the 423 * following layout for each trapped sysreg: 424 * 425 * [9:0] enum cgt_group_id (10 bits) 426 * [13:10] enum fgt_group_id (4 bits) 427 * [19:14] bit number in the FGT register (6 bits) 428 * [20] trap polarity (1 bit) 429 * [25:21] FG filter (5 bits) 430 * [35:26] Main SysReg table index (10 bits) 431 * [62:36] Unused (27 bits) 432 * [63] RES0 - Must be zero, as lost on insertion in the xarray 433 */ 434 #define TC_CGT_BITS 10 435 #define TC_FGT_BITS 4 436 #define TC_FGF_BITS 5 437 #define TC_SRI_BITS 10 438 439 union trap_config { 440 u64 val; 441 struct { 442 unsigned long cgt:TC_CGT_BITS; /* Coarse Grained Trap id */ 443 unsigned long fgt:TC_FGT_BITS; /* Fine Grained Trap id */ 444 unsigned long bit:6; /* Bit number */ 445 unsigned long pol:1; /* Polarity */ 446 unsigned long fgf:TC_FGF_BITS; /* Fine Grained Filter */ 447 unsigned long sri:TC_SRI_BITS; /* SysReg Index */ 448 unsigned long unused:27; /* Unused, should be zero */ 449 unsigned long mbz:1; /* Must Be Zero */ 450 }; 451 }; 452 453 struct encoding_to_trap_config { 454 const u32 encoding; 455 const u32 end; 456 const union trap_config tc; 457 const unsigned int line; 458 }; 459 460 #define SR_RANGE_TRAP(sr_start, sr_end, trap_id) \ 461 { \ 462 .encoding = sr_start, \ 463 .end = sr_end, \ 464 .tc = { \ 465 .cgt = trap_id, \ 466 }, \ 467 .line = __LINE__, \ 468 } 469 470 #define SR_TRAP(sr, trap_id) SR_RANGE_TRAP(sr, sr, trap_id) 471 472 /* 473 * Map encoding to trap bits for exception reported with EC=0x18. 474 * These must only be evaluated when running a nested hypervisor, but 475 * that the current context is not a hypervisor context. When the 476 * trapped access matches one of the trap controls, the exception is 477 * re-injected in the nested hypervisor. 478 */ 479 static const struct encoding_to_trap_config encoding_to_cgt[] __initconst = { 480 SR_TRAP(SYS_REVIDR_EL1, CGT_HCR_TID1), 481 SR_TRAP(SYS_AIDR_EL1, CGT_HCR_TID1), 482 SR_TRAP(SYS_SMIDR_EL1, CGT_HCR_TID1), 483 SR_TRAP(SYS_CTR_EL0, CGT_HCR_TID2), 484 SR_TRAP(SYS_CCSIDR_EL1, CGT_HCR_TID2_TID4), 485 SR_TRAP(SYS_CCSIDR2_EL1, CGT_HCR_TID2_TID4), 486 SR_TRAP(SYS_CLIDR_EL1, CGT_HCR_TID2_TID4), 487 SR_TRAP(SYS_CSSELR_EL1, CGT_HCR_TID2_TID4), 488 SR_RANGE_TRAP(SYS_ID_PFR0_EL1, 489 sys_reg(3, 0, 0, 7, 7), CGT_HCR_TID3), 490 SR_TRAP(SYS_ICC_SGI0R_EL1, CGT_HCR_IMO_FMO), 491 SR_TRAP(SYS_ICC_ASGI1R_EL1, CGT_HCR_IMO_FMO), 492 SR_TRAP(SYS_ICC_SGI1R_EL1, CGT_HCR_IMO_FMO), 493 SR_RANGE_TRAP(sys_reg(3, 0, 11, 0, 0), 494 sys_reg(3, 0, 11, 15, 7), CGT_HCR_TIDCP), 495 SR_RANGE_TRAP(sys_reg(3, 1, 11, 0, 0), 496 sys_reg(3, 1, 11, 15, 7), CGT_HCR_TIDCP), 497 SR_RANGE_TRAP(sys_reg(3, 2, 11, 0, 0), 498 sys_reg(3, 2, 11, 15, 7), CGT_HCR_TIDCP), 499 SR_RANGE_TRAP(sys_reg(3, 3, 11, 0, 0), 500 sys_reg(3, 3, 11, 15, 7), CGT_HCR_TIDCP), 501 SR_RANGE_TRAP(sys_reg(3, 4, 11, 0, 0), 502 sys_reg(3, 4, 11, 15, 7), CGT_HCR_TIDCP), 503 SR_RANGE_TRAP(sys_reg(3, 5, 11, 0, 0), 504 sys_reg(3, 5, 11, 15, 7), CGT_HCR_TIDCP), 505 SR_RANGE_TRAP(sys_reg(3, 6, 11, 0, 0), 506 sys_reg(3, 6, 11, 15, 7), CGT_HCR_TIDCP), 507 SR_RANGE_TRAP(sys_reg(3, 7, 11, 0, 0), 508 sys_reg(3, 7, 11, 15, 7), CGT_HCR_TIDCP), 509 SR_RANGE_TRAP(sys_reg(3, 0, 15, 0, 0), 510 sys_reg(3, 0, 15, 15, 7), CGT_HCR_TIDCP), 511 SR_RANGE_TRAP(sys_reg(3, 1, 15, 0, 0), 512 sys_reg(3, 1, 15, 15, 7), CGT_HCR_TIDCP), 513 SR_RANGE_TRAP(sys_reg(3, 2, 15, 0, 0), 514 sys_reg(3, 2, 15, 15, 7), CGT_HCR_TIDCP), 515 SR_RANGE_TRAP(sys_reg(3, 3, 15, 0, 0), 516 sys_reg(3, 3, 15, 15, 7), CGT_HCR_TIDCP), 517 SR_RANGE_TRAP(sys_reg(3, 4, 15, 0, 0), 518 sys_reg(3, 4, 15, 15, 7), CGT_HCR_TIDCP), 519 SR_RANGE_TRAP(sys_reg(3, 5, 15, 0, 0), 520 sys_reg(3, 5, 15, 15, 7), CGT_HCR_TIDCP), 521 SR_RANGE_TRAP(sys_reg(3, 6, 15, 0, 0), 522 sys_reg(3, 6, 15, 15, 7), CGT_HCR_TIDCP), 523 SR_RANGE_TRAP(sys_reg(3, 7, 15, 0, 0), 524 sys_reg(3, 7, 15, 15, 7), CGT_HCR_TIDCP), 525 SR_TRAP(SYS_ACTLR_EL1, CGT_HCR_TACR), 526 SR_TRAP(SYS_DC_ISW, CGT_HCR_TSW), 527 SR_TRAP(SYS_DC_CSW, CGT_HCR_TSW), 528 SR_TRAP(SYS_DC_CISW, CGT_HCR_TSW), 529 SR_TRAP(SYS_DC_IGSW, CGT_HCR_TSW), 530 SR_TRAP(SYS_DC_IGDSW, CGT_HCR_TSW), 531 SR_TRAP(SYS_DC_CGSW, CGT_HCR_TSW), 532 SR_TRAP(SYS_DC_CGDSW, CGT_HCR_TSW), 533 SR_TRAP(SYS_DC_CIGSW, CGT_HCR_TSW), 534 SR_TRAP(SYS_DC_CIGDSW, CGT_HCR_TSW), 535 SR_TRAP(SYS_DC_CIVAC, CGT_HCR_TPC), 536 SR_TRAP(SYS_DC_CVAC, CGT_HCR_TPC), 537 SR_TRAP(SYS_DC_CVAP, CGT_HCR_TPC), 538 SR_TRAP(SYS_DC_CVADP, CGT_HCR_TPC), 539 SR_TRAP(SYS_DC_IVAC, CGT_HCR_TPC), 540 SR_TRAP(SYS_DC_CIGVAC, CGT_HCR_TPC), 541 SR_TRAP(SYS_DC_CIGDVAC, CGT_HCR_TPC), 542 SR_TRAP(SYS_DC_IGVAC, CGT_HCR_TPC), 543 SR_TRAP(SYS_DC_IGDVAC, CGT_HCR_TPC), 544 SR_TRAP(SYS_DC_CGVAC, CGT_HCR_TPC), 545 SR_TRAP(SYS_DC_CGDVAC, CGT_HCR_TPC), 546 SR_TRAP(SYS_DC_CGVAP, CGT_HCR_TPC), 547 SR_TRAP(SYS_DC_CGDVAP, CGT_HCR_TPC), 548 SR_TRAP(SYS_DC_CGVADP, CGT_HCR_TPC), 549 SR_TRAP(SYS_DC_CGDVADP, CGT_HCR_TPC), 550 SR_TRAP(SYS_IC_IVAU, CGT_HCR_TPU_TOCU), 551 SR_TRAP(SYS_IC_IALLU, CGT_HCR_TPU_TOCU), 552 SR_TRAP(SYS_IC_IALLUIS, CGT_HCR_TPU_TICAB), 553 SR_TRAP(SYS_DC_CVAU, CGT_HCR_TPU_TOCU), 554 SR_TRAP(OP_TLBI_RVAE1, CGT_HCR_TTLB), 555 SR_TRAP(OP_TLBI_RVAAE1, CGT_HCR_TTLB), 556 SR_TRAP(OP_TLBI_RVALE1, CGT_HCR_TTLB), 557 SR_TRAP(OP_TLBI_RVAALE1, CGT_HCR_TTLB), 558 SR_TRAP(OP_TLBI_VMALLE1, CGT_HCR_TTLB), 559 SR_TRAP(OP_TLBI_VAE1, CGT_HCR_TTLB), 560 SR_TRAP(OP_TLBI_ASIDE1, CGT_HCR_TTLB), 561 SR_TRAP(OP_TLBI_VAAE1, CGT_HCR_TTLB), 562 SR_TRAP(OP_TLBI_VALE1, CGT_HCR_TTLB), 563 SR_TRAP(OP_TLBI_VAALE1, CGT_HCR_TTLB), 564 SR_TRAP(OP_TLBI_RVAE1NXS, CGT_HCR_TTLB), 565 SR_TRAP(OP_TLBI_RVAAE1NXS, CGT_HCR_TTLB), 566 SR_TRAP(OP_TLBI_RVALE1NXS, CGT_HCR_TTLB), 567 SR_TRAP(OP_TLBI_RVAALE1NXS, CGT_HCR_TTLB), 568 SR_TRAP(OP_TLBI_VMALLE1NXS, CGT_HCR_TTLB), 569 SR_TRAP(OP_TLBI_VAE1NXS, CGT_HCR_TTLB), 570 SR_TRAP(OP_TLBI_ASIDE1NXS, CGT_HCR_TTLB), 571 SR_TRAP(OP_TLBI_VAAE1NXS, CGT_HCR_TTLB), 572 SR_TRAP(OP_TLBI_VALE1NXS, CGT_HCR_TTLB), 573 SR_TRAP(OP_TLBI_VAALE1NXS, CGT_HCR_TTLB), 574 SR_TRAP(OP_TLBI_RVAE1IS, CGT_HCR_TTLB_TTLBIS), 575 SR_TRAP(OP_TLBI_RVAAE1IS, CGT_HCR_TTLB_TTLBIS), 576 SR_TRAP(OP_TLBI_RVALE1IS, CGT_HCR_TTLB_TTLBIS), 577 SR_TRAP(OP_TLBI_RVAALE1IS, CGT_HCR_TTLB_TTLBIS), 578 SR_TRAP(OP_TLBI_VMALLE1IS, CGT_HCR_TTLB_TTLBIS), 579 SR_TRAP(OP_TLBI_VAE1IS, CGT_HCR_TTLB_TTLBIS), 580 SR_TRAP(OP_TLBI_ASIDE1IS, CGT_HCR_TTLB_TTLBIS), 581 SR_TRAP(OP_TLBI_VAAE1IS, CGT_HCR_TTLB_TTLBIS), 582 SR_TRAP(OP_TLBI_VALE1IS, CGT_HCR_TTLB_TTLBIS), 583 SR_TRAP(OP_TLBI_VAALE1IS, CGT_HCR_TTLB_TTLBIS), 584 SR_TRAP(OP_TLBI_RVAE1ISNXS, CGT_HCR_TTLB_TTLBIS), 585 SR_TRAP(OP_TLBI_RVAAE1ISNXS, CGT_HCR_TTLB_TTLBIS), 586 SR_TRAP(OP_TLBI_RVALE1ISNXS, CGT_HCR_TTLB_TTLBIS), 587 SR_TRAP(OP_TLBI_RVAALE1ISNXS, CGT_HCR_TTLB_TTLBIS), 588 SR_TRAP(OP_TLBI_VMALLE1ISNXS, CGT_HCR_TTLB_TTLBIS), 589 SR_TRAP(OP_TLBI_VAE1ISNXS, CGT_HCR_TTLB_TTLBIS), 590 SR_TRAP(OP_TLBI_ASIDE1ISNXS, CGT_HCR_TTLB_TTLBIS), 591 SR_TRAP(OP_TLBI_VAAE1ISNXS, CGT_HCR_TTLB_TTLBIS), 592 SR_TRAP(OP_TLBI_VALE1ISNXS, CGT_HCR_TTLB_TTLBIS), 593 SR_TRAP(OP_TLBI_VAALE1ISNXS, CGT_HCR_TTLB_TTLBIS), 594 SR_TRAP(OP_TLBI_VMALLE1OS, CGT_HCR_TTLB_TTLBOS), 595 SR_TRAP(OP_TLBI_VAE1OS, CGT_HCR_TTLB_TTLBOS), 596 SR_TRAP(OP_TLBI_ASIDE1OS, CGT_HCR_TTLB_TTLBOS), 597 SR_TRAP(OP_TLBI_VAAE1OS, CGT_HCR_TTLB_TTLBOS), 598 SR_TRAP(OP_TLBI_VALE1OS, CGT_HCR_TTLB_TTLBOS), 599 SR_TRAP(OP_TLBI_VAALE1OS, CGT_HCR_TTLB_TTLBOS), 600 SR_TRAP(OP_TLBI_RVAE1OS, CGT_HCR_TTLB_TTLBOS), 601 SR_TRAP(OP_TLBI_RVAAE1OS, CGT_HCR_TTLB_TTLBOS), 602 SR_TRAP(OP_TLBI_RVALE1OS, CGT_HCR_TTLB_TTLBOS), 603 SR_TRAP(OP_TLBI_RVAALE1OS, CGT_HCR_TTLB_TTLBOS), 604 SR_TRAP(OP_TLBI_VMALLE1OSNXS, CGT_HCR_TTLB_TTLBOS), 605 SR_TRAP(OP_TLBI_VAE1OSNXS, CGT_HCR_TTLB_TTLBOS), 606 SR_TRAP(OP_TLBI_ASIDE1OSNXS, CGT_HCR_TTLB_TTLBOS), 607 SR_TRAP(OP_TLBI_VAAE1OSNXS, CGT_HCR_TTLB_TTLBOS), 608 SR_TRAP(OP_TLBI_VALE1OSNXS, CGT_HCR_TTLB_TTLBOS), 609 SR_TRAP(OP_TLBI_VAALE1OSNXS, CGT_HCR_TTLB_TTLBOS), 610 SR_TRAP(OP_TLBI_RVAE1OSNXS, CGT_HCR_TTLB_TTLBOS), 611 SR_TRAP(OP_TLBI_RVAAE1OSNXS, CGT_HCR_TTLB_TTLBOS), 612 SR_TRAP(OP_TLBI_RVALE1OSNXS, CGT_HCR_TTLB_TTLBOS), 613 SR_TRAP(OP_TLBI_RVAALE1OSNXS, CGT_HCR_TTLB_TTLBOS), 614 SR_TRAP(SYS_SCTLR_EL1, CGT_HCR_TVM_TRVM), 615 SR_TRAP(SYS_TTBR0_EL1, CGT_HCR_TVM_TRVM), 616 SR_TRAP(SYS_TTBR1_EL1, CGT_HCR_TVM_TRVM), 617 SR_TRAP(SYS_TCR_EL1, CGT_HCR_TVM_TRVM), 618 SR_TRAP(SYS_ESR_EL1, CGT_HCR_TVM_TRVM), 619 SR_TRAP(SYS_FAR_EL1, CGT_HCR_TVM_TRVM), 620 SR_TRAP(SYS_AFSR0_EL1, CGT_HCR_TVM_TRVM), 621 SR_TRAP(SYS_AFSR1_EL1, CGT_HCR_TVM_TRVM), 622 SR_TRAP(SYS_MAIR_EL1, CGT_HCR_TVM_TRVM), 623 SR_TRAP(SYS_AMAIR_EL1, CGT_HCR_TVM_TRVM), 624 SR_TRAP(SYS_CONTEXTIDR_EL1, CGT_HCR_TVM_TRVM), 625 SR_TRAP(SYS_DC_ZVA, CGT_HCR_TDZ), 626 SR_TRAP(SYS_DC_GVA, CGT_HCR_TDZ), 627 SR_TRAP(SYS_DC_GZVA, CGT_HCR_TDZ), 628 SR_TRAP(SYS_LORSA_EL1, CGT_HCR_TLOR), 629 SR_TRAP(SYS_LOREA_EL1, CGT_HCR_TLOR), 630 SR_TRAP(SYS_LORN_EL1, CGT_HCR_TLOR), 631 SR_TRAP(SYS_LORC_EL1, CGT_HCR_TLOR), 632 SR_TRAP(SYS_LORID_EL1, CGT_HCR_TLOR), 633 SR_TRAP(SYS_ERRIDR_EL1, CGT_HCR_TERR), 634 SR_TRAP(SYS_ERRSELR_EL1, CGT_HCR_TERR), 635 SR_TRAP(SYS_ERXADDR_EL1, CGT_HCR_TERR), 636 SR_TRAP(SYS_ERXCTLR_EL1, CGT_HCR_TERR), 637 SR_TRAP(SYS_ERXFR_EL1, CGT_HCR_TERR), 638 SR_TRAP(SYS_ERXMISC0_EL1, CGT_HCR_TERR), 639 SR_TRAP(SYS_ERXMISC1_EL1, CGT_HCR_TERR), 640 SR_TRAP(SYS_ERXMISC2_EL1, CGT_HCR_TERR), 641 SR_TRAP(SYS_ERXMISC3_EL1, CGT_HCR_TERR), 642 SR_TRAP(SYS_ERXSTATUS_EL1, CGT_HCR_TERR), 643 SR_TRAP(SYS_APIAKEYLO_EL1, CGT_HCR_APK), 644 SR_TRAP(SYS_APIAKEYHI_EL1, CGT_HCR_APK), 645 SR_TRAP(SYS_APIBKEYLO_EL1, CGT_HCR_APK), 646 SR_TRAP(SYS_APIBKEYHI_EL1, CGT_HCR_APK), 647 SR_TRAP(SYS_APDAKEYLO_EL1, CGT_HCR_APK), 648 SR_TRAP(SYS_APDAKEYHI_EL1, CGT_HCR_APK), 649 SR_TRAP(SYS_APDBKEYLO_EL1, CGT_HCR_APK), 650 SR_TRAP(SYS_APDBKEYHI_EL1, CGT_HCR_APK), 651 SR_TRAP(SYS_APGAKEYLO_EL1, CGT_HCR_APK), 652 SR_TRAP(SYS_APGAKEYHI_EL1, CGT_HCR_APK), 653 /* All _EL2 registers */ 654 SR_TRAP(SYS_BRBCR_EL2, CGT_HCR_NV), 655 SR_TRAP(SYS_VPIDR_EL2, CGT_HCR_NV), 656 SR_TRAP(SYS_VMPIDR_EL2, CGT_HCR_NV), 657 SR_TRAP(SYS_SCTLR_EL2, CGT_HCR_NV), 658 SR_TRAP(SYS_ACTLR_EL2, CGT_HCR_NV), 659 SR_TRAP(SYS_SCTLR2_EL2, CGT_HCR_NV), 660 SR_RANGE_TRAP(SYS_HCR_EL2, 661 SYS_HCRX_EL2, CGT_HCR_NV), 662 SR_TRAP(SYS_SMPRIMAP_EL2, CGT_HCR_NV), 663 SR_TRAP(SYS_SMCR_EL2, CGT_HCR_NV), 664 SR_RANGE_TRAP(SYS_TTBR0_EL2, 665 SYS_TCR2_EL2, CGT_HCR_NV), 666 SR_TRAP(SYS_VTTBR_EL2, CGT_HCR_NV), 667 SR_TRAP(SYS_VTCR_EL2, CGT_HCR_NV), 668 SR_TRAP(SYS_VNCR_EL2, CGT_HCR_NV), 669 SR_RANGE_TRAP(SYS_HDFGRTR_EL2, 670 SYS_HAFGRTR_EL2, CGT_HCR_NV), 671 /* Skip the SP_EL1 encoding... */ 672 SR_TRAP(SYS_SPSR_EL2, CGT_HCR_NV), 673 SR_TRAP(SYS_ELR_EL2, CGT_HCR_NV), 674 /* Skip SPSR_irq, SPSR_abt, SPSR_und, SPSR_fiq */ 675 SR_TRAP(SYS_AFSR0_EL2, CGT_HCR_NV), 676 SR_TRAP(SYS_AFSR1_EL2, CGT_HCR_NV), 677 SR_TRAP(SYS_ESR_EL2, CGT_HCR_NV), 678 SR_TRAP(SYS_VSESR_EL2, CGT_HCR_NV), 679 SR_TRAP(SYS_TFSR_EL2, CGT_HCR_NV), 680 SR_TRAP(SYS_FAR_EL2, CGT_HCR_NV), 681 SR_TRAP(SYS_HPFAR_EL2, CGT_HCR_NV), 682 SR_TRAP(SYS_PMSCR_EL2, CGT_HCR_NV), 683 SR_TRAP(SYS_MAIR_EL2, CGT_HCR_NV), 684 SR_TRAP(SYS_AMAIR_EL2, CGT_HCR_NV), 685 SR_TRAP(SYS_MPAMHCR_EL2, CGT_HCR_NV), 686 SR_TRAP(SYS_MPAMVPMV_EL2, CGT_HCR_NV), 687 SR_TRAP(SYS_MPAM2_EL2, CGT_HCR_NV), 688 SR_RANGE_TRAP(SYS_MPAMVPM0_EL2, 689 SYS_MPAMVPM7_EL2, CGT_HCR_NV), 690 /* 691 * Note that the spec. describes a group of MEC registers 692 * whose access should not trap, therefore skip the following: 693 * MECID_A0_EL2, MECID_A1_EL2, MECID_P0_EL2, 694 * MECID_P1_EL2, MECIDR_EL2, VMECID_A_EL2, 695 * VMECID_P_EL2. 696 */ 697 SR_RANGE_TRAP(SYS_VBAR_EL2, 698 SYS_RMR_EL2, CGT_HCR_NV), 699 SR_TRAP(SYS_VDISR_EL2, CGT_HCR_NV), 700 /* ICH_AP0R<m>_EL2 */ 701 SR_RANGE_TRAP(SYS_ICH_AP0R0_EL2, 702 SYS_ICH_AP0R3_EL2, CGT_HCR_NV), 703 /* ICH_AP1R<m>_EL2 */ 704 SR_RANGE_TRAP(SYS_ICH_AP1R0_EL2, 705 SYS_ICH_AP1R3_EL2, CGT_HCR_NV), 706 SR_TRAP(SYS_ICC_SRE_EL2, CGT_HCR_NV), 707 SR_RANGE_TRAP(SYS_ICH_HCR_EL2, 708 SYS_ICH_EISR_EL2, CGT_HCR_NV), 709 SR_TRAP(SYS_ICH_ELRSR_EL2, CGT_HCR_NV), 710 SR_TRAP(SYS_ICH_VMCR_EL2, CGT_HCR_NV), 711 /* ICH_LR<m>_EL2 */ 712 SR_RANGE_TRAP(SYS_ICH_LR0_EL2, 713 SYS_ICH_LR15_EL2, CGT_HCR_NV), 714 SR_TRAP(SYS_CONTEXTIDR_EL2, CGT_HCR_NV), 715 SR_TRAP(SYS_TPIDR_EL2, CGT_HCR_NV), 716 SR_TRAP(SYS_SCXTNUM_EL2, CGT_HCR_NV), 717 /* AMEVCNTVOFF0<n>_EL2, AMEVCNTVOFF1<n>_EL2 */ 718 SR_RANGE_TRAP(SYS_AMEVCNTVOFF0n_EL2(0), 719 SYS_AMEVCNTVOFF1n_EL2(15), CGT_HCR_NV), 720 /* CNT*_EL2 */ 721 SR_TRAP(SYS_CNTVOFF_EL2, CGT_HCR_NV), 722 SR_TRAP(SYS_CNTPOFF_EL2, CGT_HCR_NV), 723 SR_TRAP(SYS_CNTHCTL_EL2, CGT_HCR_NV), 724 SR_RANGE_TRAP(SYS_CNTHP_TVAL_EL2, 725 SYS_CNTHP_CVAL_EL2, CGT_HCR_NV), 726 SR_RANGE_TRAP(SYS_CNTHV_TVAL_EL2, 727 SYS_CNTHV_CVAL_EL2, CGT_HCR_NV), 728 /* All _EL02, _EL12 registers */ 729 SR_RANGE_TRAP(sys_reg(3, 5, 0, 0, 0), 730 sys_reg(3, 5, 10, 15, 7), CGT_HCR_NV), 731 SR_RANGE_TRAP(sys_reg(3, 5, 12, 0, 0), 732 sys_reg(3, 5, 14, 15, 7), CGT_HCR_NV), 733 SR_TRAP(OP_AT_S1E2R, CGT_HCR_NV), 734 SR_TRAP(OP_AT_S1E2W, CGT_HCR_NV), 735 SR_TRAP(OP_AT_S12E1R, CGT_HCR_NV), 736 SR_TRAP(OP_AT_S12E1W, CGT_HCR_NV), 737 SR_TRAP(OP_AT_S12E0R, CGT_HCR_NV), 738 SR_TRAP(OP_AT_S12E0W, CGT_HCR_NV), 739 SR_TRAP(OP_TLBI_IPAS2E1, CGT_HCR_NV), 740 SR_TRAP(OP_TLBI_RIPAS2E1, CGT_HCR_NV), 741 SR_TRAP(OP_TLBI_IPAS2LE1, CGT_HCR_NV), 742 SR_TRAP(OP_TLBI_RIPAS2LE1, CGT_HCR_NV), 743 SR_TRAP(OP_TLBI_RVAE2, CGT_HCR_NV), 744 SR_TRAP(OP_TLBI_RVALE2, CGT_HCR_NV), 745 SR_TRAP(OP_TLBI_ALLE2, CGT_HCR_NV), 746 SR_TRAP(OP_TLBI_VAE2, CGT_HCR_NV), 747 SR_TRAP(OP_TLBI_ALLE1, CGT_HCR_NV), 748 SR_TRAP(OP_TLBI_VALE2, CGT_HCR_NV), 749 SR_TRAP(OP_TLBI_VMALLS12E1, CGT_HCR_NV), 750 SR_TRAP(OP_TLBI_IPAS2E1NXS, CGT_HCR_NV), 751 SR_TRAP(OP_TLBI_RIPAS2E1NXS, CGT_HCR_NV), 752 SR_TRAP(OP_TLBI_IPAS2LE1NXS, CGT_HCR_NV), 753 SR_TRAP(OP_TLBI_RIPAS2LE1NXS, CGT_HCR_NV), 754 SR_TRAP(OP_TLBI_RVAE2NXS, CGT_HCR_NV), 755 SR_TRAP(OP_TLBI_RVALE2NXS, CGT_HCR_NV), 756 SR_TRAP(OP_TLBI_ALLE2NXS, CGT_HCR_NV), 757 SR_TRAP(OP_TLBI_VAE2NXS, CGT_HCR_NV), 758 SR_TRAP(OP_TLBI_ALLE1NXS, CGT_HCR_NV), 759 SR_TRAP(OP_TLBI_VALE2NXS, CGT_HCR_NV), 760 SR_TRAP(OP_TLBI_VMALLS12E1NXS, CGT_HCR_NV), 761 SR_TRAP(OP_TLBI_IPAS2E1IS, CGT_HCR_NV), 762 SR_TRAP(OP_TLBI_RIPAS2E1IS, CGT_HCR_NV), 763 SR_TRAP(OP_TLBI_IPAS2LE1IS, CGT_HCR_NV), 764 SR_TRAP(OP_TLBI_RIPAS2LE1IS, CGT_HCR_NV), 765 SR_TRAP(OP_TLBI_RVAE2IS, CGT_HCR_NV), 766 SR_TRAP(OP_TLBI_RVALE2IS, CGT_HCR_NV), 767 SR_TRAP(OP_TLBI_ALLE2IS, CGT_HCR_NV), 768 SR_TRAP(OP_TLBI_VAE2IS, CGT_HCR_NV), 769 SR_TRAP(OP_TLBI_ALLE1IS, CGT_HCR_NV), 770 SR_TRAP(OP_TLBI_VALE2IS, CGT_HCR_NV), 771 SR_TRAP(OP_TLBI_VMALLS12E1IS, CGT_HCR_NV), 772 SR_TRAP(OP_TLBI_IPAS2E1ISNXS, CGT_HCR_NV), 773 SR_TRAP(OP_TLBI_RIPAS2E1ISNXS, CGT_HCR_NV), 774 SR_TRAP(OP_TLBI_IPAS2LE1ISNXS, CGT_HCR_NV), 775 SR_TRAP(OP_TLBI_RIPAS2LE1ISNXS, CGT_HCR_NV), 776 SR_TRAP(OP_TLBI_RVAE2ISNXS, CGT_HCR_NV), 777 SR_TRAP(OP_TLBI_RVALE2ISNXS, CGT_HCR_NV), 778 SR_TRAP(OP_TLBI_ALLE2ISNXS, CGT_HCR_NV), 779 SR_TRAP(OP_TLBI_VAE2ISNXS, CGT_HCR_NV), 780 SR_TRAP(OP_TLBI_ALLE1ISNXS, CGT_HCR_NV), 781 SR_TRAP(OP_TLBI_VALE2ISNXS, CGT_HCR_NV), 782 SR_TRAP(OP_TLBI_VMALLS12E1ISNXS,CGT_HCR_NV), 783 SR_TRAP(OP_TLBI_ALLE2OS, CGT_HCR_NV), 784 SR_TRAP(OP_TLBI_VAE2OS, CGT_HCR_NV), 785 SR_TRAP(OP_TLBI_ALLE1OS, CGT_HCR_NV), 786 SR_TRAP(OP_TLBI_VALE2OS, CGT_HCR_NV), 787 SR_TRAP(OP_TLBI_VMALLS12E1OS, CGT_HCR_NV), 788 SR_TRAP(OP_TLBI_IPAS2E1OS, CGT_HCR_NV), 789 SR_TRAP(OP_TLBI_RIPAS2E1OS, CGT_HCR_NV), 790 SR_TRAP(OP_TLBI_IPAS2LE1OS, CGT_HCR_NV), 791 SR_TRAP(OP_TLBI_RIPAS2LE1OS, CGT_HCR_NV), 792 SR_TRAP(OP_TLBI_RVAE2OS, CGT_HCR_NV), 793 SR_TRAP(OP_TLBI_RVALE2OS, CGT_HCR_NV), 794 SR_TRAP(OP_TLBI_ALLE2OSNXS, CGT_HCR_NV), 795 SR_TRAP(OP_TLBI_VAE2OSNXS, CGT_HCR_NV), 796 SR_TRAP(OP_TLBI_ALLE1OSNXS, CGT_HCR_NV), 797 SR_TRAP(OP_TLBI_VALE2OSNXS, CGT_HCR_NV), 798 SR_TRAP(OP_TLBI_VMALLS12E1OSNXS,CGT_HCR_NV), 799 SR_TRAP(OP_TLBI_IPAS2E1OSNXS, CGT_HCR_NV), 800 SR_TRAP(OP_TLBI_RIPAS2E1OSNXS, CGT_HCR_NV), 801 SR_TRAP(OP_TLBI_IPAS2LE1OSNXS, CGT_HCR_NV), 802 SR_TRAP(OP_TLBI_RIPAS2LE1OSNXS, CGT_HCR_NV), 803 SR_TRAP(OP_TLBI_RVAE2OSNXS, CGT_HCR_NV), 804 SR_TRAP(OP_TLBI_RVALE2OSNXS, CGT_HCR_NV), 805 SR_TRAP(OP_CPP_RCTX, CGT_HCR_NV), 806 SR_TRAP(OP_DVP_RCTX, CGT_HCR_NV), 807 SR_TRAP(OP_CFP_RCTX, CGT_HCR_NV), 808 SR_TRAP(SYS_SP_EL1, CGT_HCR_NV_nNV2), 809 SR_TRAP(SYS_VBAR_EL1, CGT_HCR_NV1_nNV2), 810 SR_TRAP(SYS_ELR_EL1, CGT_HCR_NV1_nNV2), 811 SR_TRAP(SYS_SPSR_EL1, CGT_HCR_NV1_nNV2), 812 SR_TRAP(SYS_SCXTNUM_EL1, CGT_HCR_NV1_nNV2_ENSCXT), 813 SR_TRAP(SYS_SCXTNUM_EL0, CGT_HCR_ENSCXT), 814 SR_TRAP(OP_AT_S1E1R, CGT_HCR_AT), 815 SR_TRAP(OP_AT_S1E1W, CGT_HCR_AT), 816 SR_TRAP(OP_AT_S1E0R, CGT_HCR_AT), 817 SR_TRAP(OP_AT_S1E0W, CGT_HCR_AT), 818 SR_TRAP(OP_AT_S1E1RP, CGT_HCR_AT), 819 SR_TRAP(OP_AT_S1E1WP, CGT_HCR_AT), 820 SR_TRAP(SYS_ERXPFGF_EL1, CGT_HCR_nFIEN), 821 SR_TRAP(SYS_ERXPFGCTL_EL1, CGT_HCR_nFIEN), 822 SR_TRAP(SYS_ERXPFGCDN_EL1, CGT_HCR_nFIEN), 823 SR_TRAP(SYS_PMCR_EL0, CGT_MDCR_TPM_TPMCR), 824 SR_TRAP(SYS_PMCNTENSET_EL0, CGT_MDCR_TPM), 825 SR_TRAP(SYS_PMCNTENCLR_EL0, CGT_MDCR_TPM), 826 SR_TRAP(SYS_PMOVSSET_EL0, CGT_MDCR_TPM), 827 SR_TRAP(SYS_PMOVSCLR_EL0, CGT_MDCR_TPM), 828 SR_TRAP(SYS_PMCEID0_EL0, CGT_MDCR_TPM), 829 SR_TRAP(SYS_PMCEID1_EL0, CGT_MDCR_TPM), 830 SR_TRAP(SYS_PMXEVTYPER_EL0, CGT_MDCR_TPM), 831 SR_TRAP(SYS_PMSWINC_EL0, CGT_MDCR_TPM), 832 SR_TRAP(SYS_PMSELR_EL0, CGT_MDCR_TPM), 833 SR_TRAP(SYS_PMXEVCNTR_EL0, CGT_MDCR_TPM), 834 SR_TRAP(SYS_PMCCNTR_EL0, CGT_MDCR_TPM), 835 SR_TRAP(SYS_PMUSERENR_EL0, CGT_MDCR_TPM), 836 SR_TRAP(SYS_PMINTENSET_EL1, CGT_MDCR_TPM), 837 SR_TRAP(SYS_PMINTENCLR_EL1, CGT_MDCR_TPM), 838 SR_TRAP(SYS_PMMIR_EL1, CGT_MDCR_TPM), 839 SR_TRAP(SYS_PMEVCNTRn_EL0(0), CGT_MDCR_TPM), 840 SR_TRAP(SYS_PMEVCNTRn_EL0(1), CGT_MDCR_TPM), 841 SR_TRAP(SYS_PMEVCNTRn_EL0(2), CGT_MDCR_TPM), 842 SR_TRAP(SYS_PMEVCNTRn_EL0(3), CGT_MDCR_TPM), 843 SR_TRAP(SYS_PMEVCNTRn_EL0(4), CGT_MDCR_TPM), 844 SR_TRAP(SYS_PMEVCNTRn_EL0(5), CGT_MDCR_TPM), 845 SR_TRAP(SYS_PMEVCNTRn_EL0(6), CGT_MDCR_TPM), 846 SR_TRAP(SYS_PMEVCNTRn_EL0(7), CGT_MDCR_TPM), 847 SR_TRAP(SYS_PMEVCNTRn_EL0(8), CGT_MDCR_TPM), 848 SR_TRAP(SYS_PMEVCNTRn_EL0(9), CGT_MDCR_TPM), 849 SR_TRAP(SYS_PMEVCNTRn_EL0(10), CGT_MDCR_TPM), 850 SR_TRAP(SYS_PMEVCNTRn_EL0(11), CGT_MDCR_TPM), 851 SR_TRAP(SYS_PMEVCNTRn_EL0(12), CGT_MDCR_TPM), 852 SR_TRAP(SYS_PMEVCNTRn_EL0(13), CGT_MDCR_TPM), 853 SR_TRAP(SYS_PMEVCNTRn_EL0(14), CGT_MDCR_TPM), 854 SR_TRAP(SYS_PMEVCNTRn_EL0(15), CGT_MDCR_TPM), 855 SR_TRAP(SYS_PMEVCNTRn_EL0(16), CGT_MDCR_TPM), 856 SR_TRAP(SYS_PMEVCNTRn_EL0(17), CGT_MDCR_TPM), 857 SR_TRAP(SYS_PMEVCNTRn_EL0(18), CGT_MDCR_TPM), 858 SR_TRAP(SYS_PMEVCNTRn_EL0(19), CGT_MDCR_TPM), 859 SR_TRAP(SYS_PMEVCNTRn_EL0(20), CGT_MDCR_TPM), 860 SR_TRAP(SYS_PMEVCNTRn_EL0(21), CGT_MDCR_TPM), 861 SR_TRAP(SYS_PMEVCNTRn_EL0(22), CGT_MDCR_TPM), 862 SR_TRAP(SYS_PMEVCNTRn_EL0(23), CGT_MDCR_TPM), 863 SR_TRAP(SYS_PMEVCNTRn_EL0(24), CGT_MDCR_TPM), 864 SR_TRAP(SYS_PMEVCNTRn_EL0(25), CGT_MDCR_TPM), 865 SR_TRAP(SYS_PMEVCNTRn_EL0(26), CGT_MDCR_TPM), 866 SR_TRAP(SYS_PMEVCNTRn_EL0(27), CGT_MDCR_TPM), 867 SR_TRAP(SYS_PMEVCNTRn_EL0(28), CGT_MDCR_TPM), 868 SR_TRAP(SYS_PMEVCNTRn_EL0(29), CGT_MDCR_TPM), 869 SR_TRAP(SYS_PMEVCNTRn_EL0(30), CGT_MDCR_TPM), 870 SR_TRAP(SYS_PMEVTYPERn_EL0(0), CGT_MDCR_TPM), 871 SR_TRAP(SYS_PMEVTYPERn_EL0(1), CGT_MDCR_TPM), 872 SR_TRAP(SYS_PMEVTYPERn_EL0(2), CGT_MDCR_TPM), 873 SR_TRAP(SYS_PMEVTYPERn_EL0(3), CGT_MDCR_TPM), 874 SR_TRAP(SYS_PMEVTYPERn_EL0(4), CGT_MDCR_TPM), 875 SR_TRAP(SYS_PMEVTYPERn_EL0(5), CGT_MDCR_TPM), 876 SR_TRAP(SYS_PMEVTYPERn_EL0(6), CGT_MDCR_TPM), 877 SR_TRAP(SYS_PMEVTYPERn_EL0(7), CGT_MDCR_TPM), 878 SR_TRAP(SYS_PMEVTYPERn_EL0(8), CGT_MDCR_TPM), 879 SR_TRAP(SYS_PMEVTYPERn_EL0(9), CGT_MDCR_TPM), 880 SR_TRAP(SYS_PMEVTYPERn_EL0(10), CGT_MDCR_TPM), 881 SR_TRAP(SYS_PMEVTYPERn_EL0(11), CGT_MDCR_TPM), 882 SR_TRAP(SYS_PMEVTYPERn_EL0(12), CGT_MDCR_TPM), 883 SR_TRAP(SYS_PMEVTYPERn_EL0(13), CGT_MDCR_TPM), 884 SR_TRAP(SYS_PMEVTYPERn_EL0(14), CGT_MDCR_TPM), 885 SR_TRAP(SYS_PMEVTYPERn_EL0(15), CGT_MDCR_TPM), 886 SR_TRAP(SYS_PMEVTYPERn_EL0(16), CGT_MDCR_TPM), 887 SR_TRAP(SYS_PMEVTYPERn_EL0(17), CGT_MDCR_TPM), 888 SR_TRAP(SYS_PMEVTYPERn_EL0(18), CGT_MDCR_TPM), 889 SR_TRAP(SYS_PMEVTYPERn_EL0(19), CGT_MDCR_TPM), 890 SR_TRAP(SYS_PMEVTYPERn_EL0(20), CGT_MDCR_TPM), 891 SR_TRAP(SYS_PMEVTYPERn_EL0(21), CGT_MDCR_TPM), 892 SR_TRAP(SYS_PMEVTYPERn_EL0(22), CGT_MDCR_TPM), 893 SR_TRAP(SYS_PMEVTYPERn_EL0(23), CGT_MDCR_TPM), 894 SR_TRAP(SYS_PMEVTYPERn_EL0(24), CGT_MDCR_TPM), 895 SR_TRAP(SYS_PMEVTYPERn_EL0(25), CGT_MDCR_TPM), 896 SR_TRAP(SYS_PMEVTYPERn_EL0(26), CGT_MDCR_TPM), 897 SR_TRAP(SYS_PMEVTYPERn_EL0(27), CGT_MDCR_TPM), 898 SR_TRAP(SYS_PMEVTYPERn_EL0(28), CGT_MDCR_TPM), 899 SR_TRAP(SYS_PMEVTYPERn_EL0(29), CGT_MDCR_TPM), 900 SR_TRAP(SYS_PMEVTYPERn_EL0(30), CGT_MDCR_TPM), 901 SR_TRAP(SYS_PMCCFILTR_EL0, CGT_MDCR_TPM), 902 SR_TRAP(SYS_MDCCSR_EL0, CGT_MDCR_TDCC_TDE_TDA), 903 SR_TRAP(SYS_MDCCINT_EL1, CGT_MDCR_TDCC_TDE_TDA), 904 SR_TRAP(SYS_OSDTRRX_EL1, CGT_MDCR_TDCC_TDE_TDA), 905 SR_TRAP(SYS_OSDTRTX_EL1, CGT_MDCR_TDCC_TDE_TDA), 906 SR_TRAP(SYS_DBGDTR_EL0, CGT_MDCR_TDCC_TDE_TDA), 907 /* 908 * Also covers DBGDTRRX_EL0, which has the same encoding as 909 * SYS_DBGDTRTX_EL0... 910 */ 911 SR_TRAP(SYS_DBGDTRTX_EL0, CGT_MDCR_TDCC_TDE_TDA), 912 SR_TRAP(SYS_MDSCR_EL1, CGT_MDCR_TDE_TDA), 913 SR_TRAP(SYS_OSECCR_EL1, CGT_MDCR_TDE_TDA), 914 SR_TRAP(SYS_DBGBVRn_EL1(0), CGT_MDCR_TDE_TDA), 915 SR_TRAP(SYS_DBGBVRn_EL1(1), CGT_MDCR_TDE_TDA), 916 SR_TRAP(SYS_DBGBVRn_EL1(2), CGT_MDCR_TDE_TDA), 917 SR_TRAP(SYS_DBGBVRn_EL1(3), CGT_MDCR_TDE_TDA), 918 SR_TRAP(SYS_DBGBVRn_EL1(4), CGT_MDCR_TDE_TDA), 919 SR_TRAP(SYS_DBGBVRn_EL1(5), CGT_MDCR_TDE_TDA), 920 SR_TRAP(SYS_DBGBVRn_EL1(6), CGT_MDCR_TDE_TDA), 921 SR_TRAP(SYS_DBGBVRn_EL1(7), CGT_MDCR_TDE_TDA), 922 SR_TRAP(SYS_DBGBVRn_EL1(8), CGT_MDCR_TDE_TDA), 923 SR_TRAP(SYS_DBGBVRn_EL1(9), CGT_MDCR_TDE_TDA), 924 SR_TRAP(SYS_DBGBVRn_EL1(10), CGT_MDCR_TDE_TDA), 925 SR_TRAP(SYS_DBGBVRn_EL1(11), CGT_MDCR_TDE_TDA), 926 SR_TRAP(SYS_DBGBVRn_EL1(12), CGT_MDCR_TDE_TDA), 927 SR_TRAP(SYS_DBGBVRn_EL1(13), CGT_MDCR_TDE_TDA), 928 SR_TRAP(SYS_DBGBVRn_EL1(14), CGT_MDCR_TDE_TDA), 929 SR_TRAP(SYS_DBGBVRn_EL1(15), CGT_MDCR_TDE_TDA), 930 SR_TRAP(SYS_DBGBCRn_EL1(0), CGT_MDCR_TDE_TDA), 931 SR_TRAP(SYS_DBGBCRn_EL1(1), CGT_MDCR_TDE_TDA), 932 SR_TRAP(SYS_DBGBCRn_EL1(2), CGT_MDCR_TDE_TDA), 933 SR_TRAP(SYS_DBGBCRn_EL1(3), CGT_MDCR_TDE_TDA), 934 SR_TRAP(SYS_DBGBCRn_EL1(4), CGT_MDCR_TDE_TDA), 935 SR_TRAP(SYS_DBGBCRn_EL1(5), CGT_MDCR_TDE_TDA), 936 SR_TRAP(SYS_DBGBCRn_EL1(6), CGT_MDCR_TDE_TDA), 937 SR_TRAP(SYS_DBGBCRn_EL1(7), CGT_MDCR_TDE_TDA), 938 SR_TRAP(SYS_DBGBCRn_EL1(8), CGT_MDCR_TDE_TDA), 939 SR_TRAP(SYS_DBGBCRn_EL1(9), CGT_MDCR_TDE_TDA), 940 SR_TRAP(SYS_DBGBCRn_EL1(10), CGT_MDCR_TDE_TDA), 941 SR_TRAP(SYS_DBGBCRn_EL1(11), CGT_MDCR_TDE_TDA), 942 SR_TRAP(SYS_DBGBCRn_EL1(12), CGT_MDCR_TDE_TDA), 943 SR_TRAP(SYS_DBGBCRn_EL1(13), CGT_MDCR_TDE_TDA), 944 SR_TRAP(SYS_DBGBCRn_EL1(14), CGT_MDCR_TDE_TDA), 945 SR_TRAP(SYS_DBGBCRn_EL1(15), CGT_MDCR_TDE_TDA), 946 SR_TRAP(SYS_DBGWVRn_EL1(0), CGT_MDCR_TDE_TDA), 947 SR_TRAP(SYS_DBGWVRn_EL1(1), CGT_MDCR_TDE_TDA), 948 SR_TRAP(SYS_DBGWVRn_EL1(2), CGT_MDCR_TDE_TDA), 949 SR_TRAP(SYS_DBGWVRn_EL1(3), CGT_MDCR_TDE_TDA), 950 SR_TRAP(SYS_DBGWVRn_EL1(4), CGT_MDCR_TDE_TDA), 951 SR_TRAP(SYS_DBGWVRn_EL1(5), CGT_MDCR_TDE_TDA), 952 SR_TRAP(SYS_DBGWVRn_EL1(6), CGT_MDCR_TDE_TDA), 953 SR_TRAP(SYS_DBGWVRn_EL1(7), CGT_MDCR_TDE_TDA), 954 SR_TRAP(SYS_DBGWVRn_EL1(8), CGT_MDCR_TDE_TDA), 955 SR_TRAP(SYS_DBGWVRn_EL1(9), CGT_MDCR_TDE_TDA), 956 SR_TRAP(SYS_DBGWVRn_EL1(10), CGT_MDCR_TDE_TDA), 957 SR_TRAP(SYS_DBGWVRn_EL1(11), CGT_MDCR_TDE_TDA), 958 SR_TRAP(SYS_DBGWVRn_EL1(12), CGT_MDCR_TDE_TDA), 959 SR_TRAP(SYS_DBGWVRn_EL1(13), CGT_MDCR_TDE_TDA), 960 SR_TRAP(SYS_DBGWVRn_EL1(14), CGT_MDCR_TDE_TDA), 961 SR_TRAP(SYS_DBGWVRn_EL1(15), CGT_MDCR_TDE_TDA), 962 SR_TRAP(SYS_DBGWCRn_EL1(0), CGT_MDCR_TDE_TDA), 963 SR_TRAP(SYS_DBGWCRn_EL1(1), CGT_MDCR_TDE_TDA), 964 SR_TRAP(SYS_DBGWCRn_EL1(2), CGT_MDCR_TDE_TDA), 965 SR_TRAP(SYS_DBGWCRn_EL1(3), CGT_MDCR_TDE_TDA), 966 SR_TRAP(SYS_DBGWCRn_EL1(4), CGT_MDCR_TDE_TDA), 967 SR_TRAP(SYS_DBGWCRn_EL1(5), CGT_MDCR_TDE_TDA), 968 SR_TRAP(SYS_DBGWCRn_EL1(6), CGT_MDCR_TDE_TDA), 969 SR_TRAP(SYS_DBGWCRn_EL1(7), CGT_MDCR_TDE_TDA), 970 SR_TRAP(SYS_DBGWCRn_EL1(8), CGT_MDCR_TDE_TDA), 971 SR_TRAP(SYS_DBGWCRn_EL1(9), CGT_MDCR_TDE_TDA), 972 SR_TRAP(SYS_DBGWCRn_EL1(10), CGT_MDCR_TDE_TDA), 973 SR_TRAP(SYS_DBGWCRn_EL1(11), CGT_MDCR_TDE_TDA), 974 SR_TRAP(SYS_DBGWCRn_EL1(12), CGT_MDCR_TDE_TDA), 975 SR_TRAP(SYS_DBGWCRn_EL1(13), CGT_MDCR_TDE_TDA), 976 SR_TRAP(SYS_DBGWCRn_EL1(14), CGT_MDCR_TDE_TDA), 977 SR_TRAP(SYS_DBGCLAIMSET_EL1, CGT_MDCR_TDE_TDA), 978 SR_TRAP(SYS_DBGCLAIMCLR_EL1, CGT_MDCR_TDE_TDA), 979 SR_TRAP(SYS_DBGAUTHSTATUS_EL1, CGT_MDCR_TDE_TDA), 980 SR_TRAP(SYS_OSLAR_EL1, CGT_MDCR_TDE_TDOSA), 981 SR_TRAP(SYS_OSLSR_EL1, CGT_MDCR_TDE_TDOSA), 982 SR_TRAP(SYS_OSDLR_EL1, CGT_MDCR_TDE_TDOSA), 983 SR_TRAP(SYS_DBGPRCR_EL1, CGT_MDCR_TDE_TDOSA), 984 SR_TRAP(SYS_MDRAR_EL1, CGT_MDCR_TDE_TDRA), 985 SR_TRAP(SYS_PMBLIMITR_EL1, CGT_MDCR_E2PB), 986 SR_TRAP(SYS_PMBPTR_EL1, CGT_MDCR_E2PB), 987 SR_TRAP(SYS_PMBSR_EL1, CGT_MDCR_E2PB), 988 SR_TRAP(SYS_PMSCR_EL1, CGT_MDCR_TPMS), 989 SR_TRAP(SYS_PMSEVFR_EL1, CGT_MDCR_TPMS), 990 SR_TRAP(SYS_PMSFCR_EL1, CGT_MDCR_TPMS), 991 SR_TRAP(SYS_PMSICR_EL1, CGT_MDCR_TPMS), 992 SR_TRAP(SYS_PMSIDR_EL1, CGT_MDCR_TPMS), 993 SR_TRAP(SYS_PMSIRR_EL1, CGT_MDCR_TPMS), 994 SR_TRAP(SYS_PMSLATFR_EL1, CGT_MDCR_TPMS), 995 SR_TRAP(SYS_PMSNEVFR_EL1, CGT_MDCR_TPMS), 996 SR_TRAP(SYS_TRFCR_EL1, CGT_MDCR_TTRF), 997 SR_TRAP(SYS_TRBBASER_EL1, CGT_MDCR_E2TB), 998 SR_TRAP(SYS_TRBLIMITR_EL1, CGT_MDCR_E2TB), 999 SR_TRAP(SYS_TRBMAR_EL1, CGT_MDCR_E2TB), 1000 SR_TRAP(SYS_TRBPTR_EL1, CGT_MDCR_E2TB), 1001 SR_TRAP(SYS_TRBSR_EL1, CGT_MDCR_E2TB), 1002 SR_TRAP(SYS_TRBTRG_EL1, CGT_MDCR_E2TB), 1003 SR_TRAP(SYS_CNTP_TVAL_EL0, CGT_CNTHCTL_EL1PTEN), 1004 SR_TRAP(SYS_CNTP_CVAL_EL0, CGT_CNTHCTL_EL1PTEN), 1005 SR_TRAP(SYS_CNTP_CTL_EL0, CGT_CNTHCTL_EL1PTEN), 1006 SR_TRAP(SYS_CNTPCT_EL0, CGT_CNTHCTL_EL1PCTEN), 1007 SR_TRAP(SYS_CNTPCTSS_EL0, CGT_CNTHCTL_EL1PCTEN), 1008 }; 1009 1010 static DEFINE_XARRAY(sr_forward_xa); 1011 1012 enum fg_filter_id { 1013 __NO_FGF__, 1014 HCRX_FGTnXS, 1015 1016 /* Must be last */ 1017 __NR_FG_FILTER_IDS__ 1018 }; 1019 1020 #define SR_FGF(sr, g, b, p, f) \ 1021 { \ 1022 .encoding = sr, \ 1023 .end = sr, \ 1024 .tc = { \ 1025 .fgt = g ## _GROUP, \ 1026 .bit = g ## _EL2_ ## b ## _SHIFT, \ 1027 .pol = p, \ 1028 .fgf = f, \ 1029 }, \ 1030 .line = __LINE__, \ 1031 } 1032 1033 #define SR_FGT(sr, g, b, p) SR_FGF(sr, g, b, p, __NO_FGF__) 1034 1035 static const struct encoding_to_trap_config encoding_to_fgt[] __initconst = { 1036 /* HFGRTR_EL2, HFGWTR_EL2 */ 1037 SR_FGT(SYS_AMAIR2_EL1, HFGxTR, nAMAIR2_EL1, 0), 1038 SR_FGT(SYS_MAIR2_EL1, HFGxTR, nMAIR2_EL1, 0), 1039 SR_FGT(SYS_S2POR_EL1, HFGxTR, nS2POR_EL1, 0), 1040 SR_FGT(SYS_POR_EL1, HFGxTR, nPOR_EL1, 0), 1041 SR_FGT(SYS_POR_EL0, HFGxTR, nPOR_EL0, 0), 1042 SR_FGT(SYS_PIR_EL1, HFGxTR, nPIR_EL1, 0), 1043 SR_FGT(SYS_PIRE0_EL1, HFGxTR, nPIRE0_EL1, 0), 1044 SR_FGT(SYS_RCWMASK_EL1, HFGxTR, nRCWMASK_EL1, 0), 1045 SR_FGT(SYS_TPIDR2_EL0, HFGxTR, nTPIDR2_EL0, 0), 1046 SR_FGT(SYS_SMPRI_EL1, HFGxTR, nSMPRI_EL1, 0), 1047 SR_FGT(SYS_GCSCR_EL1, HFGxTR, nGCS_EL1, 0), 1048 SR_FGT(SYS_GCSPR_EL1, HFGxTR, nGCS_EL1, 0), 1049 SR_FGT(SYS_GCSCRE0_EL1, HFGxTR, nGCS_EL0, 0), 1050 SR_FGT(SYS_GCSPR_EL0, HFGxTR, nGCS_EL0, 0), 1051 SR_FGT(SYS_ACCDATA_EL1, HFGxTR, nACCDATA_EL1, 0), 1052 SR_FGT(SYS_ERXADDR_EL1, HFGxTR, ERXADDR_EL1, 1), 1053 SR_FGT(SYS_ERXPFGCDN_EL1, HFGxTR, ERXPFGCDN_EL1, 1), 1054 SR_FGT(SYS_ERXPFGCTL_EL1, HFGxTR, ERXPFGCTL_EL1, 1), 1055 SR_FGT(SYS_ERXPFGF_EL1, HFGxTR, ERXPFGF_EL1, 1), 1056 SR_FGT(SYS_ERXMISC0_EL1, HFGxTR, ERXMISCn_EL1, 1), 1057 SR_FGT(SYS_ERXMISC1_EL1, HFGxTR, ERXMISCn_EL1, 1), 1058 SR_FGT(SYS_ERXMISC2_EL1, HFGxTR, ERXMISCn_EL1, 1), 1059 SR_FGT(SYS_ERXMISC3_EL1, HFGxTR, ERXMISCn_EL1, 1), 1060 SR_FGT(SYS_ERXSTATUS_EL1, HFGxTR, ERXSTATUS_EL1, 1), 1061 SR_FGT(SYS_ERXCTLR_EL1, HFGxTR, ERXCTLR_EL1, 1), 1062 SR_FGT(SYS_ERXFR_EL1, HFGxTR, ERXFR_EL1, 1), 1063 SR_FGT(SYS_ERRSELR_EL1, HFGxTR, ERRSELR_EL1, 1), 1064 SR_FGT(SYS_ERRIDR_EL1, HFGxTR, ERRIDR_EL1, 1), 1065 SR_FGT(SYS_ICC_IGRPEN0_EL1, HFGxTR, ICC_IGRPENn_EL1, 1), 1066 SR_FGT(SYS_ICC_IGRPEN1_EL1, HFGxTR, ICC_IGRPENn_EL1, 1), 1067 SR_FGT(SYS_VBAR_EL1, HFGxTR, VBAR_EL1, 1), 1068 SR_FGT(SYS_TTBR1_EL1, HFGxTR, TTBR1_EL1, 1), 1069 SR_FGT(SYS_TTBR0_EL1, HFGxTR, TTBR0_EL1, 1), 1070 SR_FGT(SYS_TPIDR_EL0, HFGxTR, TPIDR_EL0, 1), 1071 SR_FGT(SYS_TPIDRRO_EL0, HFGxTR, TPIDRRO_EL0, 1), 1072 SR_FGT(SYS_TPIDR_EL1, HFGxTR, TPIDR_EL1, 1), 1073 SR_FGT(SYS_TCR_EL1, HFGxTR, TCR_EL1, 1), 1074 SR_FGT(SYS_SCXTNUM_EL0, HFGxTR, SCXTNUM_EL0, 1), 1075 SR_FGT(SYS_SCXTNUM_EL1, HFGxTR, SCXTNUM_EL1, 1), 1076 SR_FGT(SYS_SCTLR_EL1, HFGxTR, SCTLR_EL1, 1), 1077 SR_FGT(SYS_REVIDR_EL1, HFGxTR, REVIDR_EL1, 1), 1078 SR_FGT(SYS_PAR_EL1, HFGxTR, PAR_EL1, 1), 1079 SR_FGT(SYS_MPIDR_EL1, HFGxTR, MPIDR_EL1, 1), 1080 SR_FGT(SYS_MIDR_EL1, HFGxTR, MIDR_EL1, 1), 1081 SR_FGT(SYS_MAIR_EL1, HFGxTR, MAIR_EL1, 1), 1082 SR_FGT(SYS_LORSA_EL1, HFGxTR, LORSA_EL1, 1), 1083 SR_FGT(SYS_LORN_EL1, HFGxTR, LORN_EL1, 1), 1084 SR_FGT(SYS_LORID_EL1, HFGxTR, LORID_EL1, 1), 1085 SR_FGT(SYS_LOREA_EL1, HFGxTR, LOREA_EL1, 1), 1086 SR_FGT(SYS_LORC_EL1, HFGxTR, LORC_EL1, 1), 1087 SR_FGT(SYS_ISR_EL1, HFGxTR, ISR_EL1, 1), 1088 SR_FGT(SYS_FAR_EL1, HFGxTR, FAR_EL1, 1), 1089 SR_FGT(SYS_ESR_EL1, HFGxTR, ESR_EL1, 1), 1090 SR_FGT(SYS_DCZID_EL0, HFGxTR, DCZID_EL0, 1), 1091 SR_FGT(SYS_CTR_EL0, HFGxTR, CTR_EL0, 1), 1092 SR_FGT(SYS_CSSELR_EL1, HFGxTR, CSSELR_EL1, 1), 1093 SR_FGT(SYS_CPACR_EL1, HFGxTR, CPACR_EL1, 1), 1094 SR_FGT(SYS_CONTEXTIDR_EL1, HFGxTR, CONTEXTIDR_EL1, 1), 1095 SR_FGT(SYS_CLIDR_EL1, HFGxTR, CLIDR_EL1, 1), 1096 SR_FGT(SYS_CCSIDR_EL1, HFGxTR, CCSIDR_EL1, 1), 1097 SR_FGT(SYS_APIBKEYLO_EL1, HFGxTR, APIBKey, 1), 1098 SR_FGT(SYS_APIBKEYHI_EL1, HFGxTR, APIBKey, 1), 1099 SR_FGT(SYS_APIAKEYLO_EL1, HFGxTR, APIAKey, 1), 1100 SR_FGT(SYS_APIAKEYHI_EL1, HFGxTR, APIAKey, 1), 1101 SR_FGT(SYS_APGAKEYLO_EL1, HFGxTR, APGAKey, 1), 1102 SR_FGT(SYS_APGAKEYHI_EL1, HFGxTR, APGAKey, 1), 1103 SR_FGT(SYS_APDBKEYLO_EL1, HFGxTR, APDBKey, 1), 1104 SR_FGT(SYS_APDBKEYHI_EL1, HFGxTR, APDBKey, 1), 1105 SR_FGT(SYS_APDAKEYLO_EL1, HFGxTR, APDAKey, 1), 1106 SR_FGT(SYS_APDAKEYHI_EL1, HFGxTR, APDAKey, 1), 1107 SR_FGT(SYS_AMAIR_EL1, HFGxTR, AMAIR_EL1, 1), 1108 SR_FGT(SYS_AIDR_EL1, HFGxTR, AIDR_EL1, 1), 1109 SR_FGT(SYS_AFSR1_EL1, HFGxTR, AFSR1_EL1, 1), 1110 SR_FGT(SYS_AFSR0_EL1, HFGxTR, AFSR0_EL1, 1), 1111 /* HFGITR_EL2 */ 1112 SR_FGT(OP_AT_S1E1A, HFGITR, ATS1E1A, 1), 1113 SR_FGT(OP_COSP_RCTX, HFGITR, COSPRCTX, 1), 1114 SR_FGT(OP_GCSPUSHX, HFGITR, nGCSEPP, 0), 1115 SR_FGT(OP_GCSPOPX, HFGITR, nGCSEPP, 0), 1116 SR_FGT(OP_GCSPUSHM, HFGITR, nGCSPUSHM_EL1, 0), 1117 SR_FGT(OP_BRB_IALL, HFGITR, nBRBIALL, 0), 1118 SR_FGT(OP_BRB_INJ, HFGITR, nBRBINJ, 0), 1119 SR_FGT(SYS_DC_CVAC, HFGITR, DCCVAC, 1), 1120 SR_FGT(SYS_DC_CGVAC, HFGITR, DCCVAC, 1), 1121 SR_FGT(SYS_DC_CGDVAC, HFGITR, DCCVAC, 1), 1122 SR_FGT(OP_CPP_RCTX, HFGITR, CPPRCTX, 1), 1123 SR_FGT(OP_DVP_RCTX, HFGITR, DVPRCTX, 1), 1124 SR_FGT(OP_CFP_RCTX, HFGITR, CFPRCTX, 1), 1125 SR_FGT(OP_TLBI_VAALE1, HFGITR, TLBIVAALE1, 1), 1126 SR_FGT(OP_TLBI_VALE1, HFGITR, TLBIVALE1, 1), 1127 SR_FGT(OP_TLBI_VAAE1, HFGITR, TLBIVAAE1, 1), 1128 SR_FGT(OP_TLBI_ASIDE1, HFGITR, TLBIASIDE1, 1), 1129 SR_FGT(OP_TLBI_VAE1, HFGITR, TLBIVAE1, 1), 1130 SR_FGT(OP_TLBI_VMALLE1, HFGITR, TLBIVMALLE1, 1), 1131 SR_FGT(OP_TLBI_RVAALE1, HFGITR, TLBIRVAALE1, 1), 1132 SR_FGT(OP_TLBI_RVALE1, HFGITR, TLBIRVALE1, 1), 1133 SR_FGT(OP_TLBI_RVAAE1, HFGITR, TLBIRVAAE1, 1), 1134 SR_FGT(OP_TLBI_RVAE1, HFGITR, TLBIRVAE1, 1), 1135 SR_FGT(OP_TLBI_RVAALE1IS, HFGITR, TLBIRVAALE1IS, 1), 1136 SR_FGT(OP_TLBI_RVALE1IS, HFGITR, TLBIRVALE1IS, 1), 1137 SR_FGT(OP_TLBI_RVAAE1IS, HFGITR, TLBIRVAAE1IS, 1), 1138 SR_FGT(OP_TLBI_RVAE1IS, HFGITR, TLBIRVAE1IS, 1), 1139 SR_FGT(OP_TLBI_VAALE1IS, HFGITR, TLBIVAALE1IS, 1), 1140 SR_FGT(OP_TLBI_VALE1IS, HFGITR, TLBIVALE1IS, 1), 1141 SR_FGT(OP_TLBI_VAAE1IS, HFGITR, TLBIVAAE1IS, 1), 1142 SR_FGT(OP_TLBI_ASIDE1IS, HFGITR, TLBIASIDE1IS, 1), 1143 SR_FGT(OP_TLBI_VAE1IS, HFGITR, TLBIVAE1IS, 1), 1144 SR_FGT(OP_TLBI_VMALLE1IS, HFGITR, TLBIVMALLE1IS, 1), 1145 SR_FGT(OP_TLBI_RVAALE1OS, HFGITR, TLBIRVAALE1OS, 1), 1146 SR_FGT(OP_TLBI_RVALE1OS, HFGITR, TLBIRVALE1OS, 1), 1147 SR_FGT(OP_TLBI_RVAAE1OS, HFGITR, TLBIRVAAE1OS, 1), 1148 SR_FGT(OP_TLBI_RVAE1OS, HFGITR, TLBIRVAE1OS, 1), 1149 SR_FGT(OP_TLBI_VAALE1OS, HFGITR, TLBIVAALE1OS, 1), 1150 SR_FGT(OP_TLBI_VALE1OS, HFGITR, TLBIVALE1OS, 1), 1151 SR_FGT(OP_TLBI_VAAE1OS, HFGITR, TLBIVAAE1OS, 1), 1152 SR_FGT(OP_TLBI_ASIDE1OS, HFGITR, TLBIASIDE1OS, 1), 1153 SR_FGT(OP_TLBI_VAE1OS, HFGITR, TLBIVAE1OS, 1), 1154 SR_FGT(OP_TLBI_VMALLE1OS, HFGITR, TLBIVMALLE1OS, 1), 1155 /* nXS variants must be checked against HCRX_EL2.FGTnXS */ 1156 SR_FGF(OP_TLBI_VAALE1NXS, HFGITR, TLBIVAALE1, 1, HCRX_FGTnXS), 1157 SR_FGF(OP_TLBI_VALE1NXS, HFGITR, TLBIVALE1, 1, HCRX_FGTnXS), 1158 SR_FGF(OP_TLBI_VAAE1NXS, HFGITR, TLBIVAAE1, 1, HCRX_FGTnXS), 1159 SR_FGF(OP_TLBI_ASIDE1NXS, HFGITR, TLBIASIDE1, 1, HCRX_FGTnXS), 1160 SR_FGF(OP_TLBI_VAE1NXS, HFGITR, TLBIVAE1, 1, HCRX_FGTnXS), 1161 SR_FGF(OP_TLBI_VMALLE1NXS, HFGITR, TLBIVMALLE1, 1, HCRX_FGTnXS), 1162 SR_FGF(OP_TLBI_RVAALE1NXS, HFGITR, TLBIRVAALE1, 1, HCRX_FGTnXS), 1163 SR_FGF(OP_TLBI_RVALE1NXS, HFGITR, TLBIRVALE1, 1, HCRX_FGTnXS), 1164 SR_FGF(OP_TLBI_RVAAE1NXS, HFGITR, TLBIRVAAE1, 1, HCRX_FGTnXS), 1165 SR_FGF(OP_TLBI_RVAE1NXS, HFGITR, TLBIRVAE1, 1, HCRX_FGTnXS), 1166 SR_FGF(OP_TLBI_RVAALE1ISNXS, HFGITR, TLBIRVAALE1IS, 1, HCRX_FGTnXS), 1167 SR_FGF(OP_TLBI_RVALE1ISNXS, HFGITR, TLBIRVALE1IS, 1, HCRX_FGTnXS), 1168 SR_FGF(OP_TLBI_RVAAE1ISNXS, HFGITR, TLBIRVAAE1IS, 1, HCRX_FGTnXS), 1169 SR_FGF(OP_TLBI_RVAE1ISNXS, HFGITR, TLBIRVAE1IS, 1, HCRX_FGTnXS), 1170 SR_FGF(OP_TLBI_VAALE1ISNXS, HFGITR, TLBIVAALE1IS, 1, HCRX_FGTnXS), 1171 SR_FGF(OP_TLBI_VALE1ISNXS, HFGITR, TLBIVALE1IS, 1, HCRX_FGTnXS), 1172 SR_FGF(OP_TLBI_VAAE1ISNXS, HFGITR, TLBIVAAE1IS, 1, HCRX_FGTnXS), 1173 SR_FGF(OP_TLBI_ASIDE1ISNXS, HFGITR, TLBIASIDE1IS, 1, HCRX_FGTnXS), 1174 SR_FGF(OP_TLBI_VAE1ISNXS, HFGITR, TLBIVAE1IS, 1, HCRX_FGTnXS), 1175 SR_FGF(OP_TLBI_VMALLE1ISNXS, HFGITR, TLBIVMALLE1IS, 1, HCRX_FGTnXS), 1176 SR_FGF(OP_TLBI_RVAALE1OSNXS, HFGITR, TLBIRVAALE1OS, 1, HCRX_FGTnXS), 1177 SR_FGF(OP_TLBI_RVALE1OSNXS, HFGITR, TLBIRVALE1OS, 1, HCRX_FGTnXS), 1178 SR_FGF(OP_TLBI_RVAAE1OSNXS, HFGITR, TLBIRVAAE1OS, 1, HCRX_FGTnXS), 1179 SR_FGF(OP_TLBI_RVAE1OSNXS, HFGITR, TLBIRVAE1OS, 1, HCRX_FGTnXS), 1180 SR_FGF(OP_TLBI_VAALE1OSNXS, HFGITR, TLBIVAALE1OS, 1, HCRX_FGTnXS), 1181 SR_FGF(OP_TLBI_VALE1OSNXS, HFGITR, TLBIVALE1OS, 1, HCRX_FGTnXS), 1182 SR_FGF(OP_TLBI_VAAE1OSNXS, HFGITR, TLBIVAAE1OS, 1, HCRX_FGTnXS), 1183 SR_FGF(OP_TLBI_ASIDE1OSNXS, HFGITR, TLBIASIDE1OS, 1, HCRX_FGTnXS), 1184 SR_FGF(OP_TLBI_VAE1OSNXS, HFGITR, TLBIVAE1OS, 1, HCRX_FGTnXS), 1185 SR_FGF(OP_TLBI_VMALLE1OSNXS, HFGITR, TLBIVMALLE1OS, 1, HCRX_FGTnXS), 1186 SR_FGT(OP_AT_S1E1WP, HFGITR, ATS1E1WP, 1), 1187 SR_FGT(OP_AT_S1E1RP, HFGITR, ATS1E1RP, 1), 1188 SR_FGT(OP_AT_S1E0W, HFGITR, ATS1E0W, 1), 1189 SR_FGT(OP_AT_S1E0R, HFGITR, ATS1E0R, 1), 1190 SR_FGT(OP_AT_S1E1W, HFGITR, ATS1E1W, 1), 1191 SR_FGT(OP_AT_S1E1R, HFGITR, ATS1E1R, 1), 1192 SR_FGT(SYS_DC_ZVA, HFGITR, DCZVA, 1), 1193 SR_FGT(SYS_DC_GVA, HFGITR, DCZVA, 1), 1194 SR_FGT(SYS_DC_GZVA, HFGITR, DCZVA, 1), 1195 SR_FGT(SYS_DC_CIVAC, HFGITR, DCCIVAC, 1), 1196 SR_FGT(SYS_DC_CIGVAC, HFGITR, DCCIVAC, 1), 1197 SR_FGT(SYS_DC_CIGDVAC, HFGITR, DCCIVAC, 1), 1198 SR_FGT(SYS_DC_CVADP, HFGITR, DCCVADP, 1), 1199 SR_FGT(SYS_DC_CGVADP, HFGITR, DCCVADP, 1), 1200 SR_FGT(SYS_DC_CGDVADP, HFGITR, DCCVADP, 1), 1201 SR_FGT(SYS_DC_CVAP, HFGITR, DCCVAP, 1), 1202 SR_FGT(SYS_DC_CGVAP, HFGITR, DCCVAP, 1), 1203 SR_FGT(SYS_DC_CGDVAP, HFGITR, DCCVAP, 1), 1204 SR_FGT(SYS_DC_CVAU, HFGITR, DCCVAU, 1), 1205 SR_FGT(SYS_DC_CISW, HFGITR, DCCISW, 1), 1206 SR_FGT(SYS_DC_CIGSW, HFGITR, DCCISW, 1), 1207 SR_FGT(SYS_DC_CIGDSW, HFGITR, DCCISW, 1), 1208 SR_FGT(SYS_DC_CSW, HFGITR, DCCSW, 1), 1209 SR_FGT(SYS_DC_CGSW, HFGITR, DCCSW, 1), 1210 SR_FGT(SYS_DC_CGDSW, HFGITR, DCCSW, 1), 1211 SR_FGT(SYS_DC_ISW, HFGITR, DCISW, 1), 1212 SR_FGT(SYS_DC_IGSW, HFGITR, DCISW, 1), 1213 SR_FGT(SYS_DC_IGDSW, HFGITR, DCISW, 1), 1214 SR_FGT(SYS_DC_IVAC, HFGITR, DCIVAC, 1), 1215 SR_FGT(SYS_DC_IGVAC, HFGITR, DCIVAC, 1), 1216 SR_FGT(SYS_DC_IGDVAC, HFGITR, DCIVAC, 1), 1217 SR_FGT(SYS_IC_IVAU, HFGITR, ICIVAU, 1), 1218 SR_FGT(SYS_IC_IALLU, HFGITR, ICIALLU, 1), 1219 SR_FGT(SYS_IC_IALLUIS, HFGITR, ICIALLUIS, 1), 1220 /* HDFGRTR_EL2 */ 1221 SR_FGT(SYS_PMBIDR_EL1, HDFGRTR, PMBIDR_EL1, 1), 1222 SR_FGT(SYS_PMSNEVFR_EL1, HDFGRTR, nPMSNEVFR_EL1, 0), 1223 SR_FGT(SYS_BRBINF_EL1(0), HDFGRTR, nBRBDATA, 0), 1224 SR_FGT(SYS_BRBINF_EL1(1), HDFGRTR, nBRBDATA, 0), 1225 SR_FGT(SYS_BRBINF_EL1(2), HDFGRTR, nBRBDATA, 0), 1226 SR_FGT(SYS_BRBINF_EL1(3), HDFGRTR, nBRBDATA, 0), 1227 SR_FGT(SYS_BRBINF_EL1(4), HDFGRTR, nBRBDATA, 0), 1228 SR_FGT(SYS_BRBINF_EL1(5), HDFGRTR, nBRBDATA, 0), 1229 SR_FGT(SYS_BRBINF_EL1(6), HDFGRTR, nBRBDATA, 0), 1230 SR_FGT(SYS_BRBINF_EL1(7), HDFGRTR, nBRBDATA, 0), 1231 SR_FGT(SYS_BRBINF_EL1(8), HDFGRTR, nBRBDATA, 0), 1232 SR_FGT(SYS_BRBINF_EL1(9), HDFGRTR, nBRBDATA, 0), 1233 SR_FGT(SYS_BRBINF_EL1(10), HDFGRTR, nBRBDATA, 0), 1234 SR_FGT(SYS_BRBINF_EL1(11), HDFGRTR, nBRBDATA, 0), 1235 SR_FGT(SYS_BRBINF_EL1(12), HDFGRTR, nBRBDATA, 0), 1236 SR_FGT(SYS_BRBINF_EL1(13), HDFGRTR, nBRBDATA, 0), 1237 SR_FGT(SYS_BRBINF_EL1(14), HDFGRTR, nBRBDATA, 0), 1238 SR_FGT(SYS_BRBINF_EL1(15), HDFGRTR, nBRBDATA, 0), 1239 SR_FGT(SYS_BRBINF_EL1(16), HDFGRTR, nBRBDATA, 0), 1240 SR_FGT(SYS_BRBINF_EL1(17), HDFGRTR, nBRBDATA, 0), 1241 SR_FGT(SYS_BRBINF_EL1(18), HDFGRTR, nBRBDATA, 0), 1242 SR_FGT(SYS_BRBINF_EL1(19), HDFGRTR, nBRBDATA, 0), 1243 SR_FGT(SYS_BRBINF_EL1(20), HDFGRTR, nBRBDATA, 0), 1244 SR_FGT(SYS_BRBINF_EL1(21), HDFGRTR, nBRBDATA, 0), 1245 SR_FGT(SYS_BRBINF_EL1(22), HDFGRTR, nBRBDATA, 0), 1246 SR_FGT(SYS_BRBINF_EL1(23), HDFGRTR, nBRBDATA, 0), 1247 SR_FGT(SYS_BRBINF_EL1(24), HDFGRTR, nBRBDATA, 0), 1248 SR_FGT(SYS_BRBINF_EL1(25), HDFGRTR, nBRBDATA, 0), 1249 SR_FGT(SYS_BRBINF_EL1(26), HDFGRTR, nBRBDATA, 0), 1250 SR_FGT(SYS_BRBINF_EL1(27), HDFGRTR, nBRBDATA, 0), 1251 SR_FGT(SYS_BRBINF_EL1(28), HDFGRTR, nBRBDATA, 0), 1252 SR_FGT(SYS_BRBINF_EL1(29), HDFGRTR, nBRBDATA, 0), 1253 SR_FGT(SYS_BRBINF_EL1(30), HDFGRTR, nBRBDATA, 0), 1254 SR_FGT(SYS_BRBINF_EL1(31), HDFGRTR, nBRBDATA, 0), 1255 SR_FGT(SYS_BRBINFINJ_EL1, HDFGRTR, nBRBDATA, 0), 1256 SR_FGT(SYS_BRBSRC_EL1(0), HDFGRTR, nBRBDATA, 0), 1257 SR_FGT(SYS_BRBSRC_EL1(1), HDFGRTR, nBRBDATA, 0), 1258 SR_FGT(SYS_BRBSRC_EL1(2), HDFGRTR, nBRBDATA, 0), 1259 SR_FGT(SYS_BRBSRC_EL1(3), HDFGRTR, nBRBDATA, 0), 1260 SR_FGT(SYS_BRBSRC_EL1(4), HDFGRTR, nBRBDATA, 0), 1261 SR_FGT(SYS_BRBSRC_EL1(5), HDFGRTR, nBRBDATA, 0), 1262 SR_FGT(SYS_BRBSRC_EL1(6), HDFGRTR, nBRBDATA, 0), 1263 SR_FGT(SYS_BRBSRC_EL1(7), HDFGRTR, nBRBDATA, 0), 1264 SR_FGT(SYS_BRBSRC_EL1(8), HDFGRTR, nBRBDATA, 0), 1265 SR_FGT(SYS_BRBSRC_EL1(9), HDFGRTR, nBRBDATA, 0), 1266 SR_FGT(SYS_BRBSRC_EL1(10), HDFGRTR, nBRBDATA, 0), 1267 SR_FGT(SYS_BRBSRC_EL1(11), HDFGRTR, nBRBDATA, 0), 1268 SR_FGT(SYS_BRBSRC_EL1(12), HDFGRTR, nBRBDATA, 0), 1269 SR_FGT(SYS_BRBSRC_EL1(13), HDFGRTR, nBRBDATA, 0), 1270 SR_FGT(SYS_BRBSRC_EL1(14), HDFGRTR, nBRBDATA, 0), 1271 SR_FGT(SYS_BRBSRC_EL1(15), HDFGRTR, nBRBDATA, 0), 1272 SR_FGT(SYS_BRBSRC_EL1(16), HDFGRTR, nBRBDATA, 0), 1273 SR_FGT(SYS_BRBSRC_EL1(17), HDFGRTR, nBRBDATA, 0), 1274 SR_FGT(SYS_BRBSRC_EL1(18), HDFGRTR, nBRBDATA, 0), 1275 SR_FGT(SYS_BRBSRC_EL1(19), HDFGRTR, nBRBDATA, 0), 1276 SR_FGT(SYS_BRBSRC_EL1(20), HDFGRTR, nBRBDATA, 0), 1277 SR_FGT(SYS_BRBSRC_EL1(21), HDFGRTR, nBRBDATA, 0), 1278 SR_FGT(SYS_BRBSRC_EL1(22), HDFGRTR, nBRBDATA, 0), 1279 SR_FGT(SYS_BRBSRC_EL1(23), HDFGRTR, nBRBDATA, 0), 1280 SR_FGT(SYS_BRBSRC_EL1(24), HDFGRTR, nBRBDATA, 0), 1281 SR_FGT(SYS_BRBSRC_EL1(25), HDFGRTR, nBRBDATA, 0), 1282 SR_FGT(SYS_BRBSRC_EL1(26), HDFGRTR, nBRBDATA, 0), 1283 SR_FGT(SYS_BRBSRC_EL1(27), HDFGRTR, nBRBDATA, 0), 1284 SR_FGT(SYS_BRBSRC_EL1(28), HDFGRTR, nBRBDATA, 0), 1285 SR_FGT(SYS_BRBSRC_EL1(29), HDFGRTR, nBRBDATA, 0), 1286 SR_FGT(SYS_BRBSRC_EL1(30), HDFGRTR, nBRBDATA, 0), 1287 SR_FGT(SYS_BRBSRC_EL1(31), HDFGRTR, nBRBDATA, 0), 1288 SR_FGT(SYS_BRBSRCINJ_EL1, HDFGRTR, nBRBDATA, 0), 1289 SR_FGT(SYS_BRBTGT_EL1(0), HDFGRTR, nBRBDATA, 0), 1290 SR_FGT(SYS_BRBTGT_EL1(1), HDFGRTR, nBRBDATA, 0), 1291 SR_FGT(SYS_BRBTGT_EL1(2), HDFGRTR, nBRBDATA, 0), 1292 SR_FGT(SYS_BRBTGT_EL1(3), HDFGRTR, nBRBDATA, 0), 1293 SR_FGT(SYS_BRBTGT_EL1(4), HDFGRTR, nBRBDATA, 0), 1294 SR_FGT(SYS_BRBTGT_EL1(5), HDFGRTR, nBRBDATA, 0), 1295 SR_FGT(SYS_BRBTGT_EL1(6), HDFGRTR, nBRBDATA, 0), 1296 SR_FGT(SYS_BRBTGT_EL1(7), HDFGRTR, nBRBDATA, 0), 1297 SR_FGT(SYS_BRBTGT_EL1(8), HDFGRTR, nBRBDATA, 0), 1298 SR_FGT(SYS_BRBTGT_EL1(9), HDFGRTR, nBRBDATA, 0), 1299 SR_FGT(SYS_BRBTGT_EL1(10), HDFGRTR, nBRBDATA, 0), 1300 SR_FGT(SYS_BRBTGT_EL1(11), HDFGRTR, nBRBDATA, 0), 1301 SR_FGT(SYS_BRBTGT_EL1(12), HDFGRTR, nBRBDATA, 0), 1302 SR_FGT(SYS_BRBTGT_EL1(13), HDFGRTR, nBRBDATA, 0), 1303 SR_FGT(SYS_BRBTGT_EL1(14), HDFGRTR, nBRBDATA, 0), 1304 SR_FGT(SYS_BRBTGT_EL1(15), HDFGRTR, nBRBDATA, 0), 1305 SR_FGT(SYS_BRBTGT_EL1(16), HDFGRTR, nBRBDATA, 0), 1306 SR_FGT(SYS_BRBTGT_EL1(17), HDFGRTR, nBRBDATA, 0), 1307 SR_FGT(SYS_BRBTGT_EL1(18), HDFGRTR, nBRBDATA, 0), 1308 SR_FGT(SYS_BRBTGT_EL1(19), HDFGRTR, nBRBDATA, 0), 1309 SR_FGT(SYS_BRBTGT_EL1(20), HDFGRTR, nBRBDATA, 0), 1310 SR_FGT(SYS_BRBTGT_EL1(21), HDFGRTR, nBRBDATA, 0), 1311 SR_FGT(SYS_BRBTGT_EL1(22), HDFGRTR, nBRBDATA, 0), 1312 SR_FGT(SYS_BRBTGT_EL1(23), HDFGRTR, nBRBDATA, 0), 1313 SR_FGT(SYS_BRBTGT_EL1(24), HDFGRTR, nBRBDATA, 0), 1314 SR_FGT(SYS_BRBTGT_EL1(25), HDFGRTR, nBRBDATA, 0), 1315 SR_FGT(SYS_BRBTGT_EL1(26), HDFGRTR, nBRBDATA, 0), 1316 SR_FGT(SYS_BRBTGT_EL1(27), HDFGRTR, nBRBDATA, 0), 1317 SR_FGT(SYS_BRBTGT_EL1(28), HDFGRTR, nBRBDATA, 0), 1318 SR_FGT(SYS_BRBTGT_EL1(29), HDFGRTR, nBRBDATA, 0), 1319 SR_FGT(SYS_BRBTGT_EL1(30), HDFGRTR, nBRBDATA, 0), 1320 SR_FGT(SYS_BRBTGT_EL1(31), HDFGRTR, nBRBDATA, 0), 1321 SR_FGT(SYS_BRBTGTINJ_EL1, HDFGRTR, nBRBDATA, 0), 1322 SR_FGT(SYS_BRBTS_EL1, HDFGRTR, nBRBDATA, 0), 1323 SR_FGT(SYS_BRBCR_EL1, HDFGRTR, nBRBCTL, 0), 1324 SR_FGT(SYS_BRBFCR_EL1, HDFGRTR, nBRBCTL, 0), 1325 SR_FGT(SYS_BRBIDR0_EL1, HDFGRTR, nBRBIDR, 0), 1326 SR_FGT(SYS_PMCEID0_EL0, HDFGRTR, PMCEIDn_EL0, 1), 1327 SR_FGT(SYS_PMCEID1_EL0, HDFGRTR, PMCEIDn_EL0, 1), 1328 SR_FGT(SYS_PMUSERENR_EL0, HDFGRTR, PMUSERENR_EL0, 1), 1329 SR_FGT(SYS_TRBTRG_EL1, HDFGRTR, TRBTRG_EL1, 1), 1330 SR_FGT(SYS_TRBSR_EL1, HDFGRTR, TRBSR_EL1, 1), 1331 SR_FGT(SYS_TRBPTR_EL1, HDFGRTR, TRBPTR_EL1, 1), 1332 SR_FGT(SYS_TRBMAR_EL1, HDFGRTR, TRBMAR_EL1, 1), 1333 SR_FGT(SYS_TRBLIMITR_EL1, HDFGRTR, TRBLIMITR_EL1, 1), 1334 SR_FGT(SYS_TRBIDR_EL1, HDFGRTR, TRBIDR_EL1, 1), 1335 SR_FGT(SYS_TRBBASER_EL1, HDFGRTR, TRBBASER_EL1, 1), 1336 SR_FGT(SYS_TRCVICTLR, HDFGRTR, TRCVICTLR, 1), 1337 SR_FGT(SYS_TRCSTATR, HDFGRTR, TRCSTATR, 1), 1338 SR_FGT(SYS_TRCSSCSR(0), HDFGRTR, TRCSSCSRn, 1), 1339 SR_FGT(SYS_TRCSSCSR(1), HDFGRTR, TRCSSCSRn, 1), 1340 SR_FGT(SYS_TRCSSCSR(2), HDFGRTR, TRCSSCSRn, 1), 1341 SR_FGT(SYS_TRCSSCSR(3), HDFGRTR, TRCSSCSRn, 1), 1342 SR_FGT(SYS_TRCSSCSR(4), HDFGRTR, TRCSSCSRn, 1), 1343 SR_FGT(SYS_TRCSSCSR(5), HDFGRTR, TRCSSCSRn, 1), 1344 SR_FGT(SYS_TRCSSCSR(6), HDFGRTR, TRCSSCSRn, 1), 1345 SR_FGT(SYS_TRCSSCSR(7), HDFGRTR, TRCSSCSRn, 1), 1346 SR_FGT(SYS_TRCSEQSTR, HDFGRTR, TRCSEQSTR, 1), 1347 SR_FGT(SYS_TRCPRGCTLR, HDFGRTR, TRCPRGCTLR, 1), 1348 SR_FGT(SYS_TRCOSLSR, HDFGRTR, TRCOSLSR, 1), 1349 SR_FGT(SYS_TRCIMSPEC(0), HDFGRTR, TRCIMSPECn, 1), 1350 SR_FGT(SYS_TRCIMSPEC(1), HDFGRTR, TRCIMSPECn, 1), 1351 SR_FGT(SYS_TRCIMSPEC(2), HDFGRTR, TRCIMSPECn, 1), 1352 SR_FGT(SYS_TRCIMSPEC(3), HDFGRTR, TRCIMSPECn, 1), 1353 SR_FGT(SYS_TRCIMSPEC(4), HDFGRTR, TRCIMSPECn, 1), 1354 SR_FGT(SYS_TRCIMSPEC(5), HDFGRTR, TRCIMSPECn, 1), 1355 SR_FGT(SYS_TRCIMSPEC(6), HDFGRTR, TRCIMSPECn, 1), 1356 SR_FGT(SYS_TRCIMSPEC(7), HDFGRTR, TRCIMSPECn, 1), 1357 SR_FGT(SYS_TRCDEVARCH, HDFGRTR, TRCID, 1), 1358 SR_FGT(SYS_TRCDEVID, HDFGRTR, TRCID, 1), 1359 SR_FGT(SYS_TRCIDR0, HDFGRTR, TRCID, 1), 1360 SR_FGT(SYS_TRCIDR1, HDFGRTR, TRCID, 1), 1361 SR_FGT(SYS_TRCIDR2, HDFGRTR, TRCID, 1), 1362 SR_FGT(SYS_TRCIDR3, HDFGRTR, TRCID, 1), 1363 SR_FGT(SYS_TRCIDR4, HDFGRTR, TRCID, 1), 1364 SR_FGT(SYS_TRCIDR5, HDFGRTR, TRCID, 1), 1365 SR_FGT(SYS_TRCIDR6, HDFGRTR, TRCID, 1), 1366 SR_FGT(SYS_TRCIDR7, HDFGRTR, TRCID, 1), 1367 SR_FGT(SYS_TRCIDR8, HDFGRTR, TRCID, 1), 1368 SR_FGT(SYS_TRCIDR9, HDFGRTR, TRCID, 1), 1369 SR_FGT(SYS_TRCIDR10, HDFGRTR, TRCID, 1), 1370 SR_FGT(SYS_TRCIDR11, HDFGRTR, TRCID, 1), 1371 SR_FGT(SYS_TRCIDR12, HDFGRTR, TRCID, 1), 1372 SR_FGT(SYS_TRCIDR13, HDFGRTR, TRCID, 1), 1373 SR_FGT(SYS_TRCCNTVR(0), HDFGRTR, TRCCNTVRn, 1), 1374 SR_FGT(SYS_TRCCNTVR(1), HDFGRTR, TRCCNTVRn, 1), 1375 SR_FGT(SYS_TRCCNTVR(2), HDFGRTR, TRCCNTVRn, 1), 1376 SR_FGT(SYS_TRCCNTVR(3), HDFGRTR, TRCCNTVRn, 1), 1377 SR_FGT(SYS_TRCCLAIMCLR, HDFGRTR, TRCCLAIM, 1), 1378 SR_FGT(SYS_TRCCLAIMSET, HDFGRTR, TRCCLAIM, 1), 1379 SR_FGT(SYS_TRCAUXCTLR, HDFGRTR, TRCAUXCTLR, 1), 1380 SR_FGT(SYS_TRCAUTHSTATUS, HDFGRTR, TRCAUTHSTATUS, 1), 1381 SR_FGT(SYS_TRCACATR(0), HDFGRTR, TRC, 1), 1382 SR_FGT(SYS_TRCACATR(1), HDFGRTR, TRC, 1), 1383 SR_FGT(SYS_TRCACATR(2), HDFGRTR, TRC, 1), 1384 SR_FGT(SYS_TRCACATR(3), HDFGRTR, TRC, 1), 1385 SR_FGT(SYS_TRCACATR(4), HDFGRTR, TRC, 1), 1386 SR_FGT(SYS_TRCACATR(5), HDFGRTR, TRC, 1), 1387 SR_FGT(SYS_TRCACATR(6), HDFGRTR, TRC, 1), 1388 SR_FGT(SYS_TRCACATR(7), HDFGRTR, TRC, 1), 1389 SR_FGT(SYS_TRCACATR(8), HDFGRTR, TRC, 1), 1390 SR_FGT(SYS_TRCACATR(9), HDFGRTR, TRC, 1), 1391 SR_FGT(SYS_TRCACATR(10), HDFGRTR, TRC, 1), 1392 SR_FGT(SYS_TRCACATR(11), HDFGRTR, TRC, 1), 1393 SR_FGT(SYS_TRCACATR(12), HDFGRTR, TRC, 1), 1394 SR_FGT(SYS_TRCACATR(13), HDFGRTR, TRC, 1), 1395 SR_FGT(SYS_TRCACATR(14), HDFGRTR, TRC, 1), 1396 SR_FGT(SYS_TRCACATR(15), HDFGRTR, TRC, 1), 1397 SR_FGT(SYS_TRCACVR(0), HDFGRTR, TRC, 1), 1398 SR_FGT(SYS_TRCACVR(1), HDFGRTR, TRC, 1), 1399 SR_FGT(SYS_TRCACVR(2), HDFGRTR, TRC, 1), 1400 SR_FGT(SYS_TRCACVR(3), HDFGRTR, TRC, 1), 1401 SR_FGT(SYS_TRCACVR(4), HDFGRTR, TRC, 1), 1402 SR_FGT(SYS_TRCACVR(5), HDFGRTR, TRC, 1), 1403 SR_FGT(SYS_TRCACVR(6), HDFGRTR, TRC, 1), 1404 SR_FGT(SYS_TRCACVR(7), HDFGRTR, TRC, 1), 1405 SR_FGT(SYS_TRCACVR(8), HDFGRTR, TRC, 1), 1406 SR_FGT(SYS_TRCACVR(9), HDFGRTR, TRC, 1), 1407 SR_FGT(SYS_TRCACVR(10), HDFGRTR, TRC, 1), 1408 SR_FGT(SYS_TRCACVR(11), HDFGRTR, TRC, 1), 1409 SR_FGT(SYS_TRCACVR(12), HDFGRTR, TRC, 1), 1410 SR_FGT(SYS_TRCACVR(13), HDFGRTR, TRC, 1), 1411 SR_FGT(SYS_TRCACVR(14), HDFGRTR, TRC, 1), 1412 SR_FGT(SYS_TRCACVR(15), HDFGRTR, TRC, 1), 1413 SR_FGT(SYS_TRCBBCTLR, HDFGRTR, TRC, 1), 1414 SR_FGT(SYS_TRCCCCTLR, HDFGRTR, TRC, 1), 1415 SR_FGT(SYS_TRCCIDCCTLR0, HDFGRTR, TRC, 1), 1416 SR_FGT(SYS_TRCCIDCCTLR1, HDFGRTR, TRC, 1), 1417 SR_FGT(SYS_TRCCIDCVR(0), HDFGRTR, TRC, 1), 1418 SR_FGT(SYS_TRCCIDCVR(1), HDFGRTR, TRC, 1), 1419 SR_FGT(SYS_TRCCIDCVR(2), HDFGRTR, TRC, 1), 1420 SR_FGT(SYS_TRCCIDCVR(3), HDFGRTR, TRC, 1), 1421 SR_FGT(SYS_TRCCIDCVR(4), HDFGRTR, TRC, 1), 1422 SR_FGT(SYS_TRCCIDCVR(5), HDFGRTR, TRC, 1), 1423 SR_FGT(SYS_TRCCIDCVR(6), HDFGRTR, TRC, 1), 1424 SR_FGT(SYS_TRCCIDCVR(7), HDFGRTR, TRC, 1), 1425 SR_FGT(SYS_TRCCNTCTLR(0), HDFGRTR, TRC, 1), 1426 SR_FGT(SYS_TRCCNTCTLR(1), HDFGRTR, TRC, 1), 1427 SR_FGT(SYS_TRCCNTCTLR(2), HDFGRTR, TRC, 1), 1428 SR_FGT(SYS_TRCCNTCTLR(3), HDFGRTR, TRC, 1), 1429 SR_FGT(SYS_TRCCNTRLDVR(0), HDFGRTR, TRC, 1), 1430 SR_FGT(SYS_TRCCNTRLDVR(1), HDFGRTR, TRC, 1), 1431 SR_FGT(SYS_TRCCNTRLDVR(2), HDFGRTR, TRC, 1), 1432 SR_FGT(SYS_TRCCNTRLDVR(3), HDFGRTR, TRC, 1), 1433 SR_FGT(SYS_TRCCONFIGR, HDFGRTR, TRC, 1), 1434 SR_FGT(SYS_TRCEVENTCTL0R, HDFGRTR, TRC, 1), 1435 SR_FGT(SYS_TRCEVENTCTL1R, HDFGRTR, TRC, 1), 1436 SR_FGT(SYS_TRCEXTINSELR(0), HDFGRTR, TRC, 1), 1437 SR_FGT(SYS_TRCEXTINSELR(1), HDFGRTR, TRC, 1), 1438 SR_FGT(SYS_TRCEXTINSELR(2), HDFGRTR, TRC, 1), 1439 SR_FGT(SYS_TRCEXTINSELR(3), HDFGRTR, TRC, 1), 1440 SR_FGT(SYS_TRCQCTLR, HDFGRTR, TRC, 1), 1441 SR_FGT(SYS_TRCRSCTLR(2), HDFGRTR, TRC, 1), 1442 SR_FGT(SYS_TRCRSCTLR(3), HDFGRTR, TRC, 1), 1443 SR_FGT(SYS_TRCRSCTLR(4), HDFGRTR, TRC, 1), 1444 SR_FGT(SYS_TRCRSCTLR(5), HDFGRTR, TRC, 1), 1445 SR_FGT(SYS_TRCRSCTLR(6), HDFGRTR, TRC, 1), 1446 SR_FGT(SYS_TRCRSCTLR(7), HDFGRTR, TRC, 1), 1447 SR_FGT(SYS_TRCRSCTLR(8), HDFGRTR, TRC, 1), 1448 SR_FGT(SYS_TRCRSCTLR(9), HDFGRTR, TRC, 1), 1449 SR_FGT(SYS_TRCRSCTLR(10), HDFGRTR, TRC, 1), 1450 SR_FGT(SYS_TRCRSCTLR(11), HDFGRTR, TRC, 1), 1451 SR_FGT(SYS_TRCRSCTLR(12), HDFGRTR, TRC, 1), 1452 SR_FGT(SYS_TRCRSCTLR(13), HDFGRTR, TRC, 1), 1453 SR_FGT(SYS_TRCRSCTLR(14), HDFGRTR, TRC, 1), 1454 SR_FGT(SYS_TRCRSCTLR(15), HDFGRTR, TRC, 1), 1455 SR_FGT(SYS_TRCRSCTLR(16), HDFGRTR, TRC, 1), 1456 SR_FGT(SYS_TRCRSCTLR(17), HDFGRTR, TRC, 1), 1457 SR_FGT(SYS_TRCRSCTLR(18), HDFGRTR, TRC, 1), 1458 SR_FGT(SYS_TRCRSCTLR(19), HDFGRTR, TRC, 1), 1459 SR_FGT(SYS_TRCRSCTLR(20), HDFGRTR, TRC, 1), 1460 SR_FGT(SYS_TRCRSCTLR(21), HDFGRTR, TRC, 1), 1461 SR_FGT(SYS_TRCRSCTLR(22), HDFGRTR, TRC, 1), 1462 SR_FGT(SYS_TRCRSCTLR(23), HDFGRTR, TRC, 1), 1463 SR_FGT(SYS_TRCRSCTLR(24), HDFGRTR, TRC, 1), 1464 SR_FGT(SYS_TRCRSCTLR(25), HDFGRTR, TRC, 1), 1465 SR_FGT(SYS_TRCRSCTLR(26), HDFGRTR, TRC, 1), 1466 SR_FGT(SYS_TRCRSCTLR(27), HDFGRTR, TRC, 1), 1467 SR_FGT(SYS_TRCRSCTLR(28), HDFGRTR, TRC, 1), 1468 SR_FGT(SYS_TRCRSCTLR(29), HDFGRTR, TRC, 1), 1469 SR_FGT(SYS_TRCRSCTLR(30), HDFGRTR, TRC, 1), 1470 SR_FGT(SYS_TRCRSCTLR(31), HDFGRTR, TRC, 1), 1471 SR_FGT(SYS_TRCRSR, HDFGRTR, TRC, 1), 1472 SR_FGT(SYS_TRCSEQEVR(0), HDFGRTR, TRC, 1), 1473 SR_FGT(SYS_TRCSEQEVR(1), HDFGRTR, TRC, 1), 1474 SR_FGT(SYS_TRCSEQEVR(2), HDFGRTR, TRC, 1), 1475 SR_FGT(SYS_TRCSEQRSTEVR, HDFGRTR, TRC, 1), 1476 SR_FGT(SYS_TRCSSCCR(0), HDFGRTR, TRC, 1), 1477 SR_FGT(SYS_TRCSSCCR(1), HDFGRTR, TRC, 1), 1478 SR_FGT(SYS_TRCSSCCR(2), HDFGRTR, TRC, 1), 1479 SR_FGT(SYS_TRCSSCCR(3), HDFGRTR, TRC, 1), 1480 SR_FGT(SYS_TRCSSCCR(4), HDFGRTR, TRC, 1), 1481 SR_FGT(SYS_TRCSSCCR(5), HDFGRTR, TRC, 1), 1482 SR_FGT(SYS_TRCSSCCR(6), HDFGRTR, TRC, 1), 1483 SR_FGT(SYS_TRCSSCCR(7), HDFGRTR, TRC, 1), 1484 SR_FGT(SYS_TRCSSPCICR(0), HDFGRTR, TRC, 1), 1485 SR_FGT(SYS_TRCSSPCICR(1), HDFGRTR, TRC, 1), 1486 SR_FGT(SYS_TRCSSPCICR(2), HDFGRTR, TRC, 1), 1487 SR_FGT(SYS_TRCSSPCICR(3), HDFGRTR, TRC, 1), 1488 SR_FGT(SYS_TRCSSPCICR(4), HDFGRTR, TRC, 1), 1489 SR_FGT(SYS_TRCSSPCICR(5), HDFGRTR, TRC, 1), 1490 SR_FGT(SYS_TRCSSPCICR(6), HDFGRTR, TRC, 1), 1491 SR_FGT(SYS_TRCSSPCICR(7), HDFGRTR, TRC, 1), 1492 SR_FGT(SYS_TRCSTALLCTLR, HDFGRTR, TRC, 1), 1493 SR_FGT(SYS_TRCSYNCPR, HDFGRTR, TRC, 1), 1494 SR_FGT(SYS_TRCTRACEIDR, HDFGRTR, TRC, 1), 1495 SR_FGT(SYS_TRCTSCTLR, HDFGRTR, TRC, 1), 1496 SR_FGT(SYS_TRCVIIECTLR, HDFGRTR, TRC, 1), 1497 SR_FGT(SYS_TRCVIPCSSCTLR, HDFGRTR, TRC, 1), 1498 SR_FGT(SYS_TRCVISSCTLR, HDFGRTR, TRC, 1), 1499 SR_FGT(SYS_TRCVMIDCCTLR0, HDFGRTR, TRC, 1), 1500 SR_FGT(SYS_TRCVMIDCCTLR1, HDFGRTR, TRC, 1), 1501 SR_FGT(SYS_TRCVMIDCVR(0), HDFGRTR, TRC, 1), 1502 SR_FGT(SYS_TRCVMIDCVR(1), HDFGRTR, TRC, 1), 1503 SR_FGT(SYS_TRCVMIDCVR(2), HDFGRTR, TRC, 1), 1504 SR_FGT(SYS_TRCVMIDCVR(3), HDFGRTR, TRC, 1), 1505 SR_FGT(SYS_TRCVMIDCVR(4), HDFGRTR, TRC, 1), 1506 SR_FGT(SYS_TRCVMIDCVR(5), HDFGRTR, TRC, 1), 1507 SR_FGT(SYS_TRCVMIDCVR(6), HDFGRTR, TRC, 1), 1508 SR_FGT(SYS_TRCVMIDCVR(7), HDFGRTR, TRC, 1), 1509 SR_FGT(SYS_PMSLATFR_EL1, HDFGRTR, PMSLATFR_EL1, 1), 1510 SR_FGT(SYS_PMSIRR_EL1, HDFGRTR, PMSIRR_EL1, 1), 1511 SR_FGT(SYS_PMSIDR_EL1, HDFGRTR, PMSIDR_EL1, 1), 1512 SR_FGT(SYS_PMSICR_EL1, HDFGRTR, PMSICR_EL1, 1), 1513 SR_FGT(SYS_PMSFCR_EL1, HDFGRTR, PMSFCR_EL1, 1), 1514 SR_FGT(SYS_PMSEVFR_EL1, HDFGRTR, PMSEVFR_EL1, 1), 1515 SR_FGT(SYS_PMSCR_EL1, HDFGRTR, PMSCR_EL1, 1), 1516 SR_FGT(SYS_PMBSR_EL1, HDFGRTR, PMBSR_EL1, 1), 1517 SR_FGT(SYS_PMBPTR_EL1, HDFGRTR, PMBPTR_EL1, 1), 1518 SR_FGT(SYS_PMBLIMITR_EL1, HDFGRTR, PMBLIMITR_EL1, 1), 1519 SR_FGT(SYS_PMMIR_EL1, HDFGRTR, PMMIR_EL1, 1), 1520 SR_FGT(SYS_PMSELR_EL0, HDFGRTR, PMSELR_EL0, 1), 1521 SR_FGT(SYS_PMOVSCLR_EL0, HDFGRTR, PMOVS, 1), 1522 SR_FGT(SYS_PMOVSSET_EL0, HDFGRTR, PMOVS, 1), 1523 SR_FGT(SYS_PMINTENCLR_EL1, HDFGRTR, PMINTEN, 1), 1524 SR_FGT(SYS_PMINTENSET_EL1, HDFGRTR, PMINTEN, 1), 1525 SR_FGT(SYS_PMCNTENCLR_EL0, HDFGRTR, PMCNTEN, 1), 1526 SR_FGT(SYS_PMCNTENSET_EL0, HDFGRTR, PMCNTEN, 1), 1527 SR_FGT(SYS_PMCCNTR_EL0, HDFGRTR, PMCCNTR_EL0, 1), 1528 SR_FGT(SYS_PMCCFILTR_EL0, HDFGRTR, PMCCFILTR_EL0, 1), 1529 SR_FGT(SYS_PMEVTYPERn_EL0(0), HDFGRTR, PMEVTYPERn_EL0, 1), 1530 SR_FGT(SYS_PMEVTYPERn_EL0(1), HDFGRTR, PMEVTYPERn_EL0, 1), 1531 SR_FGT(SYS_PMEVTYPERn_EL0(2), HDFGRTR, PMEVTYPERn_EL0, 1), 1532 SR_FGT(SYS_PMEVTYPERn_EL0(3), HDFGRTR, PMEVTYPERn_EL0, 1), 1533 SR_FGT(SYS_PMEVTYPERn_EL0(4), HDFGRTR, PMEVTYPERn_EL0, 1), 1534 SR_FGT(SYS_PMEVTYPERn_EL0(5), HDFGRTR, PMEVTYPERn_EL0, 1), 1535 SR_FGT(SYS_PMEVTYPERn_EL0(6), HDFGRTR, PMEVTYPERn_EL0, 1), 1536 SR_FGT(SYS_PMEVTYPERn_EL0(7), HDFGRTR, PMEVTYPERn_EL0, 1), 1537 SR_FGT(SYS_PMEVTYPERn_EL0(8), HDFGRTR, PMEVTYPERn_EL0, 1), 1538 SR_FGT(SYS_PMEVTYPERn_EL0(9), HDFGRTR, PMEVTYPERn_EL0, 1), 1539 SR_FGT(SYS_PMEVTYPERn_EL0(10), HDFGRTR, PMEVTYPERn_EL0, 1), 1540 SR_FGT(SYS_PMEVTYPERn_EL0(11), HDFGRTR, PMEVTYPERn_EL0, 1), 1541 SR_FGT(SYS_PMEVTYPERn_EL0(12), HDFGRTR, PMEVTYPERn_EL0, 1), 1542 SR_FGT(SYS_PMEVTYPERn_EL0(13), HDFGRTR, PMEVTYPERn_EL0, 1), 1543 SR_FGT(SYS_PMEVTYPERn_EL0(14), HDFGRTR, PMEVTYPERn_EL0, 1), 1544 SR_FGT(SYS_PMEVTYPERn_EL0(15), HDFGRTR, PMEVTYPERn_EL0, 1), 1545 SR_FGT(SYS_PMEVTYPERn_EL0(16), HDFGRTR, PMEVTYPERn_EL0, 1), 1546 SR_FGT(SYS_PMEVTYPERn_EL0(17), HDFGRTR, PMEVTYPERn_EL0, 1), 1547 SR_FGT(SYS_PMEVTYPERn_EL0(18), HDFGRTR, PMEVTYPERn_EL0, 1), 1548 SR_FGT(SYS_PMEVTYPERn_EL0(19), HDFGRTR, PMEVTYPERn_EL0, 1), 1549 SR_FGT(SYS_PMEVTYPERn_EL0(20), HDFGRTR, PMEVTYPERn_EL0, 1), 1550 SR_FGT(SYS_PMEVTYPERn_EL0(21), HDFGRTR, PMEVTYPERn_EL0, 1), 1551 SR_FGT(SYS_PMEVTYPERn_EL0(22), HDFGRTR, PMEVTYPERn_EL0, 1), 1552 SR_FGT(SYS_PMEVTYPERn_EL0(23), HDFGRTR, PMEVTYPERn_EL0, 1), 1553 SR_FGT(SYS_PMEVTYPERn_EL0(24), HDFGRTR, PMEVTYPERn_EL0, 1), 1554 SR_FGT(SYS_PMEVTYPERn_EL0(25), HDFGRTR, PMEVTYPERn_EL0, 1), 1555 SR_FGT(SYS_PMEVTYPERn_EL0(26), HDFGRTR, PMEVTYPERn_EL0, 1), 1556 SR_FGT(SYS_PMEVTYPERn_EL0(27), HDFGRTR, PMEVTYPERn_EL0, 1), 1557 SR_FGT(SYS_PMEVTYPERn_EL0(28), HDFGRTR, PMEVTYPERn_EL0, 1), 1558 SR_FGT(SYS_PMEVTYPERn_EL0(29), HDFGRTR, PMEVTYPERn_EL0, 1), 1559 SR_FGT(SYS_PMEVTYPERn_EL0(30), HDFGRTR, PMEVTYPERn_EL0, 1), 1560 SR_FGT(SYS_PMEVCNTRn_EL0(0), HDFGRTR, PMEVCNTRn_EL0, 1), 1561 SR_FGT(SYS_PMEVCNTRn_EL0(1), HDFGRTR, PMEVCNTRn_EL0, 1), 1562 SR_FGT(SYS_PMEVCNTRn_EL0(2), HDFGRTR, PMEVCNTRn_EL0, 1), 1563 SR_FGT(SYS_PMEVCNTRn_EL0(3), HDFGRTR, PMEVCNTRn_EL0, 1), 1564 SR_FGT(SYS_PMEVCNTRn_EL0(4), HDFGRTR, PMEVCNTRn_EL0, 1), 1565 SR_FGT(SYS_PMEVCNTRn_EL0(5), HDFGRTR, PMEVCNTRn_EL0, 1), 1566 SR_FGT(SYS_PMEVCNTRn_EL0(6), HDFGRTR, PMEVCNTRn_EL0, 1), 1567 SR_FGT(SYS_PMEVCNTRn_EL0(7), HDFGRTR, PMEVCNTRn_EL0, 1), 1568 SR_FGT(SYS_PMEVCNTRn_EL0(8), HDFGRTR, PMEVCNTRn_EL0, 1), 1569 SR_FGT(SYS_PMEVCNTRn_EL0(9), HDFGRTR, PMEVCNTRn_EL0, 1), 1570 SR_FGT(SYS_PMEVCNTRn_EL0(10), HDFGRTR, PMEVCNTRn_EL0, 1), 1571 SR_FGT(SYS_PMEVCNTRn_EL0(11), HDFGRTR, PMEVCNTRn_EL0, 1), 1572 SR_FGT(SYS_PMEVCNTRn_EL0(12), HDFGRTR, PMEVCNTRn_EL0, 1), 1573 SR_FGT(SYS_PMEVCNTRn_EL0(13), HDFGRTR, PMEVCNTRn_EL0, 1), 1574 SR_FGT(SYS_PMEVCNTRn_EL0(14), HDFGRTR, PMEVCNTRn_EL0, 1), 1575 SR_FGT(SYS_PMEVCNTRn_EL0(15), HDFGRTR, PMEVCNTRn_EL0, 1), 1576 SR_FGT(SYS_PMEVCNTRn_EL0(16), HDFGRTR, PMEVCNTRn_EL0, 1), 1577 SR_FGT(SYS_PMEVCNTRn_EL0(17), HDFGRTR, PMEVCNTRn_EL0, 1), 1578 SR_FGT(SYS_PMEVCNTRn_EL0(18), HDFGRTR, PMEVCNTRn_EL0, 1), 1579 SR_FGT(SYS_PMEVCNTRn_EL0(19), HDFGRTR, PMEVCNTRn_EL0, 1), 1580 SR_FGT(SYS_PMEVCNTRn_EL0(20), HDFGRTR, PMEVCNTRn_EL0, 1), 1581 SR_FGT(SYS_PMEVCNTRn_EL0(21), HDFGRTR, PMEVCNTRn_EL0, 1), 1582 SR_FGT(SYS_PMEVCNTRn_EL0(22), HDFGRTR, PMEVCNTRn_EL0, 1), 1583 SR_FGT(SYS_PMEVCNTRn_EL0(23), HDFGRTR, PMEVCNTRn_EL0, 1), 1584 SR_FGT(SYS_PMEVCNTRn_EL0(24), HDFGRTR, PMEVCNTRn_EL0, 1), 1585 SR_FGT(SYS_PMEVCNTRn_EL0(25), HDFGRTR, PMEVCNTRn_EL0, 1), 1586 SR_FGT(SYS_PMEVCNTRn_EL0(26), HDFGRTR, PMEVCNTRn_EL0, 1), 1587 SR_FGT(SYS_PMEVCNTRn_EL0(27), HDFGRTR, PMEVCNTRn_EL0, 1), 1588 SR_FGT(SYS_PMEVCNTRn_EL0(28), HDFGRTR, PMEVCNTRn_EL0, 1), 1589 SR_FGT(SYS_PMEVCNTRn_EL0(29), HDFGRTR, PMEVCNTRn_EL0, 1), 1590 SR_FGT(SYS_PMEVCNTRn_EL0(30), HDFGRTR, PMEVCNTRn_EL0, 1), 1591 SR_FGT(SYS_OSDLR_EL1, HDFGRTR, OSDLR_EL1, 1), 1592 SR_FGT(SYS_OSECCR_EL1, HDFGRTR, OSECCR_EL1, 1), 1593 SR_FGT(SYS_OSLSR_EL1, HDFGRTR, OSLSR_EL1, 1), 1594 SR_FGT(SYS_DBGPRCR_EL1, HDFGRTR, DBGPRCR_EL1, 1), 1595 SR_FGT(SYS_DBGAUTHSTATUS_EL1, HDFGRTR, DBGAUTHSTATUS_EL1, 1), 1596 SR_FGT(SYS_DBGCLAIMSET_EL1, HDFGRTR, DBGCLAIM, 1), 1597 SR_FGT(SYS_DBGCLAIMCLR_EL1, HDFGRTR, DBGCLAIM, 1), 1598 SR_FGT(SYS_MDSCR_EL1, HDFGRTR, MDSCR_EL1, 1), 1599 /* 1600 * The trap bits capture *64* debug registers per bit, but the 1601 * ARM ARM only describes the encoding for the first 16, and 1602 * we don't really support more than that anyway. 1603 */ 1604 SR_FGT(SYS_DBGWVRn_EL1(0), HDFGRTR, DBGWVRn_EL1, 1), 1605 SR_FGT(SYS_DBGWVRn_EL1(1), HDFGRTR, DBGWVRn_EL1, 1), 1606 SR_FGT(SYS_DBGWVRn_EL1(2), HDFGRTR, DBGWVRn_EL1, 1), 1607 SR_FGT(SYS_DBGWVRn_EL1(3), HDFGRTR, DBGWVRn_EL1, 1), 1608 SR_FGT(SYS_DBGWVRn_EL1(4), HDFGRTR, DBGWVRn_EL1, 1), 1609 SR_FGT(SYS_DBGWVRn_EL1(5), HDFGRTR, DBGWVRn_EL1, 1), 1610 SR_FGT(SYS_DBGWVRn_EL1(6), HDFGRTR, DBGWVRn_EL1, 1), 1611 SR_FGT(SYS_DBGWVRn_EL1(7), HDFGRTR, DBGWVRn_EL1, 1), 1612 SR_FGT(SYS_DBGWVRn_EL1(8), HDFGRTR, DBGWVRn_EL1, 1), 1613 SR_FGT(SYS_DBGWVRn_EL1(9), HDFGRTR, DBGWVRn_EL1, 1), 1614 SR_FGT(SYS_DBGWVRn_EL1(10), HDFGRTR, DBGWVRn_EL1, 1), 1615 SR_FGT(SYS_DBGWVRn_EL1(11), HDFGRTR, DBGWVRn_EL1, 1), 1616 SR_FGT(SYS_DBGWVRn_EL1(12), HDFGRTR, DBGWVRn_EL1, 1), 1617 SR_FGT(SYS_DBGWVRn_EL1(13), HDFGRTR, DBGWVRn_EL1, 1), 1618 SR_FGT(SYS_DBGWVRn_EL1(14), HDFGRTR, DBGWVRn_EL1, 1), 1619 SR_FGT(SYS_DBGWVRn_EL1(15), HDFGRTR, DBGWVRn_EL1, 1), 1620 SR_FGT(SYS_DBGWCRn_EL1(0), HDFGRTR, DBGWCRn_EL1, 1), 1621 SR_FGT(SYS_DBGWCRn_EL1(1), HDFGRTR, DBGWCRn_EL1, 1), 1622 SR_FGT(SYS_DBGWCRn_EL1(2), HDFGRTR, DBGWCRn_EL1, 1), 1623 SR_FGT(SYS_DBGWCRn_EL1(3), HDFGRTR, DBGWCRn_EL1, 1), 1624 SR_FGT(SYS_DBGWCRn_EL1(4), HDFGRTR, DBGWCRn_EL1, 1), 1625 SR_FGT(SYS_DBGWCRn_EL1(5), HDFGRTR, DBGWCRn_EL1, 1), 1626 SR_FGT(SYS_DBGWCRn_EL1(6), HDFGRTR, DBGWCRn_EL1, 1), 1627 SR_FGT(SYS_DBGWCRn_EL1(7), HDFGRTR, DBGWCRn_EL1, 1), 1628 SR_FGT(SYS_DBGWCRn_EL1(8), HDFGRTR, DBGWCRn_EL1, 1), 1629 SR_FGT(SYS_DBGWCRn_EL1(9), HDFGRTR, DBGWCRn_EL1, 1), 1630 SR_FGT(SYS_DBGWCRn_EL1(10), HDFGRTR, DBGWCRn_EL1, 1), 1631 SR_FGT(SYS_DBGWCRn_EL1(11), HDFGRTR, DBGWCRn_EL1, 1), 1632 SR_FGT(SYS_DBGWCRn_EL1(12), HDFGRTR, DBGWCRn_EL1, 1), 1633 SR_FGT(SYS_DBGWCRn_EL1(13), HDFGRTR, DBGWCRn_EL1, 1), 1634 SR_FGT(SYS_DBGWCRn_EL1(14), HDFGRTR, DBGWCRn_EL1, 1), 1635 SR_FGT(SYS_DBGWCRn_EL1(15), HDFGRTR, DBGWCRn_EL1, 1), 1636 SR_FGT(SYS_DBGBVRn_EL1(0), HDFGRTR, DBGBVRn_EL1, 1), 1637 SR_FGT(SYS_DBGBVRn_EL1(1), HDFGRTR, DBGBVRn_EL1, 1), 1638 SR_FGT(SYS_DBGBVRn_EL1(2), HDFGRTR, DBGBVRn_EL1, 1), 1639 SR_FGT(SYS_DBGBVRn_EL1(3), HDFGRTR, DBGBVRn_EL1, 1), 1640 SR_FGT(SYS_DBGBVRn_EL1(4), HDFGRTR, DBGBVRn_EL1, 1), 1641 SR_FGT(SYS_DBGBVRn_EL1(5), HDFGRTR, DBGBVRn_EL1, 1), 1642 SR_FGT(SYS_DBGBVRn_EL1(6), HDFGRTR, DBGBVRn_EL1, 1), 1643 SR_FGT(SYS_DBGBVRn_EL1(7), HDFGRTR, DBGBVRn_EL1, 1), 1644 SR_FGT(SYS_DBGBVRn_EL1(8), HDFGRTR, DBGBVRn_EL1, 1), 1645 SR_FGT(SYS_DBGBVRn_EL1(9), HDFGRTR, DBGBVRn_EL1, 1), 1646 SR_FGT(SYS_DBGBVRn_EL1(10), HDFGRTR, DBGBVRn_EL1, 1), 1647 SR_FGT(SYS_DBGBVRn_EL1(11), HDFGRTR, DBGBVRn_EL1, 1), 1648 SR_FGT(SYS_DBGBVRn_EL1(12), HDFGRTR, DBGBVRn_EL1, 1), 1649 SR_FGT(SYS_DBGBVRn_EL1(13), HDFGRTR, DBGBVRn_EL1, 1), 1650 SR_FGT(SYS_DBGBVRn_EL1(14), HDFGRTR, DBGBVRn_EL1, 1), 1651 SR_FGT(SYS_DBGBVRn_EL1(15), HDFGRTR, DBGBVRn_EL1, 1), 1652 SR_FGT(SYS_DBGBCRn_EL1(0), HDFGRTR, DBGBCRn_EL1, 1), 1653 SR_FGT(SYS_DBGBCRn_EL1(1), HDFGRTR, DBGBCRn_EL1, 1), 1654 SR_FGT(SYS_DBGBCRn_EL1(2), HDFGRTR, DBGBCRn_EL1, 1), 1655 SR_FGT(SYS_DBGBCRn_EL1(3), HDFGRTR, DBGBCRn_EL1, 1), 1656 SR_FGT(SYS_DBGBCRn_EL1(4), HDFGRTR, DBGBCRn_EL1, 1), 1657 SR_FGT(SYS_DBGBCRn_EL1(5), HDFGRTR, DBGBCRn_EL1, 1), 1658 SR_FGT(SYS_DBGBCRn_EL1(6), HDFGRTR, DBGBCRn_EL1, 1), 1659 SR_FGT(SYS_DBGBCRn_EL1(7), HDFGRTR, DBGBCRn_EL1, 1), 1660 SR_FGT(SYS_DBGBCRn_EL1(8), HDFGRTR, DBGBCRn_EL1, 1), 1661 SR_FGT(SYS_DBGBCRn_EL1(9), HDFGRTR, DBGBCRn_EL1, 1), 1662 SR_FGT(SYS_DBGBCRn_EL1(10), HDFGRTR, DBGBCRn_EL1, 1), 1663 SR_FGT(SYS_DBGBCRn_EL1(11), HDFGRTR, DBGBCRn_EL1, 1), 1664 SR_FGT(SYS_DBGBCRn_EL1(12), HDFGRTR, DBGBCRn_EL1, 1), 1665 SR_FGT(SYS_DBGBCRn_EL1(13), HDFGRTR, DBGBCRn_EL1, 1), 1666 SR_FGT(SYS_DBGBCRn_EL1(14), HDFGRTR, DBGBCRn_EL1, 1), 1667 SR_FGT(SYS_DBGBCRn_EL1(15), HDFGRTR, DBGBCRn_EL1, 1), 1668 /* 1669 * HDFGWTR_EL2 1670 * 1671 * Although HDFGRTR_EL2 and HDFGWTR_EL2 registers largely 1672 * overlap in their bit assignment, there are a number of bits 1673 * that are RES0 on one side, and an actual trap bit on the 1674 * other. The policy chosen here is to describe all the 1675 * read-side mappings, and only the write-side mappings that 1676 * differ from the read side, and the trap handler will pick 1677 * the correct shadow register based on the access type. 1678 */ 1679 SR_FGT(SYS_TRFCR_EL1, HDFGWTR, TRFCR_EL1, 1), 1680 SR_FGT(SYS_TRCOSLAR, HDFGWTR, TRCOSLAR, 1), 1681 SR_FGT(SYS_PMCR_EL0, HDFGWTR, PMCR_EL0, 1), 1682 SR_FGT(SYS_PMSWINC_EL0, HDFGWTR, PMSWINC_EL0, 1), 1683 SR_FGT(SYS_OSLAR_EL1, HDFGWTR, OSLAR_EL1, 1), 1684 /* 1685 * HAFGRTR_EL2 1686 */ 1687 SR_FGT(SYS_AMEVTYPER1_EL0(15), HAFGRTR, AMEVTYPER115_EL0, 1), 1688 SR_FGT(SYS_AMEVTYPER1_EL0(14), HAFGRTR, AMEVTYPER114_EL0, 1), 1689 SR_FGT(SYS_AMEVTYPER1_EL0(13), HAFGRTR, AMEVTYPER113_EL0, 1), 1690 SR_FGT(SYS_AMEVTYPER1_EL0(12), HAFGRTR, AMEVTYPER112_EL0, 1), 1691 SR_FGT(SYS_AMEVTYPER1_EL0(11), HAFGRTR, AMEVTYPER111_EL0, 1), 1692 SR_FGT(SYS_AMEVTYPER1_EL0(10), HAFGRTR, AMEVTYPER110_EL0, 1), 1693 SR_FGT(SYS_AMEVTYPER1_EL0(9), HAFGRTR, AMEVTYPER19_EL0, 1), 1694 SR_FGT(SYS_AMEVTYPER1_EL0(8), HAFGRTR, AMEVTYPER18_EL0, 1), 1695 SR_FGT(SYS_AMEVTYPER1_EL0(7), HAFGRTR, AMEVTYPER17_EL0, 1), 1696 SR_FGT(SYS_AMEVTYPER1_EL0(6), HAFGRTR, AMEVTYPER16_EL0, 1), 1697 SR_FGT(SYS_AMEVTYPER1_EL0(5), HAFGRTR, AMEVTYPER15_EL0, 1), 1698 SR_FGT(SYS_AMEVTYPER1_EL0(4), HAFGRTR, AMEVTYPER14_EL0, 1), 1699 SR_FGT(SYS_AMEVTYPER1_EL0(3), HAFGRTR, AMEVTYPER13_EL0, 1), 1700 SR_FGT(SYS_AMEVTYPER1_EL0(2), HAFGRTR, AMEVTYPER12_EL0, 1), 1701 SR_FGT(SYS_AMEVTYPER1_EL0(1), HAFGRTR, AMEVTYPER11_EL0, 1), 1702 SR_FGT(SYS_AMEVTYPER1_EL0(0), HAFGRTR, AMEVTYPER10_EL0, 1), 1703 SR_FGT(SYS_AMEVCNTR1_EL0(15), HAFGRTR, AMEVCNTR115_EL0, 1), 1704 SR_FGT(SYS_AMEVCNTR1_EL0(14), HAFGRTR, AMEVCNTR114_EL0, 1), 1705 SR_FGT(SYS_AMEVCNTR1_EL0(13), HAFGRTR, AMEVCNTR113_EL0, 1), 1706 SR_FGT(SYS_AMEVCNTR1_EL0(12), HAFGRTR, AMEVCNTR112_EL0, 1), 1707 SR_FGT(SYS_AMEVCNTR1_EL0(11), HAFGRTR, AMEVCNTR111_EL0, 1), 1708 SR_FGT(SYS_AMEVCNTR1_EL0(10), HAFGRTR, AMEVCNTR110_EL0, 1), 1709 SR_FGT(SYS_AMEVCNTR1_EL0(9), HAFGRTR, AMEVCNTR19_EL0, 1), 1710 SR_FGT(SYS_AMEVCNTR1_EL0(8), HAFGRTR, AMEVCNTR18_EL0, 1), 1711 SR_FGT(SYS_AMEVCNTR1_EL0(7), HAFGRTR, AMEVCNTR17_EL0, 1), 1712 SR_FGT(SYS_AMEVCNTR1_EL0(6), HAFGRTR, AMEVCNTR16_EL0, 1), 1713 SR_FGT(SYS_AMEVCNTR1_EL0(5), HAFGRTR, AMEVCNTR15_EL0, 1), 1714 SR_FGT(SYS_AMEVCNTR1_EL0(4), HAFGRTR, AMEVCNTR14_EL0, 1), 1715 SR_FGT(SYS_AMEVCNTR1_EL0(3), HAFGRTR, AMEVCNTR13_EL0, 1), 1716 SR_FGT(SYS_AMEVCNTR1_EL0(2), HAFGRTR, AMEVCNTR12_EL0, 1), 1717 SR_FGT(SYS_AMEVCNTR1_EL0(1), HAFGRTR, AMEVCNTR11_EL0, 1), 1718 SR_FGT(SYS_AMEVCNTR1_EL0(0), HAFGRTR, AMEVCNTR10_EL0, 1), 1719 SR_FGT(SYS_AMCNTENCLR1_EL0, HAFGRTR, AMCNTEN1, 1), 1720 SR_FGT(SYS_AMCNTENSET1_EL0, HAFGRTR, AMCNTEN1, 1), 1721 SR_FGT(SYS_AMCNTENCLR0_EL0, HAFGRTR, AMCNTEN0, 1), 1722 SR_FGT(SYS_AMCNTENSET0_EL0, HAFGRTR, AMCNTEN0, 1), 1723 SR_FGT(SYS_AMEVCNTR0_EL0(3), HAFGRTR, AMEVCNTR03_EL0, 1), 1724 SR_FGT(SYS_AMEVCNTR0_EL0(2), HAFGRTR, AMEVCNTR02_EL0, 1), 1725 SR_FGT(SYS_AMEVCNTR0_EL0(1), HAFGRTR, AMEVCNTR01_EL0, 1), 1726 SR_FGT(SYS_AMEVCNTR0_EL0(0), HAFGRTR, AMEVCNTR00_EL0, 1), 1727 }; 1728 1729 static union trap_config get_trap_config(u32 sysreg) 1730 { 1731 return (union trap_config) { 1732 .val = xa_to_value(xa_load(&sr_forward_xa, sysreg)), 1733 }; 1734 } 1735 1736 static __init void print_nv_trap_error(const struct encoding_to_trap_config *tc, 1737 const char *type, int err) 1738 { 1739 kvm_err("%s line %d encoding range " 1740 "(%d, %d, %d, %d, %d) - (%d, %d, %d, %d, %d) (err=%d)\n", 1741 type, tc->line, 1742 sys_reg_Op0(tc->encoding), sys_reg_Op1(tc->encoding), 1743 sys_reg_CRn(tc->encoding), sys_reg_CRm(tc->encoding), 1744 sys_reg_Op2(tc->encoding), 1745 sys_reg_Op0(tc->end), sys_reg_Op1(tc->end), 1746 sys_reg_CRn(tc->end), sys_reg_CRm(tc->end), 1747 sys_reg_Op2(tc->end), 1748 err); 1749 } 1750 1751 static u32 encoding_next(u32 encoding) 1752 { 1753 u8 op0, op1, crn, crm, op2; 1754 1755 op0 = sys_reg_Op0(encoding); 1756 op1 = sys_reg_Op1(encoding); 1757 crn = sys_reg_CRn(encoding); 1758 crm = sys_reg_CRm(encoding); 1759 op2 = sys_reg_Op2(encoding); 1760 1761 if (op2 < Op2_mask) 1762 return sys_reg(op0, op1, crn, crm, op2 + 1); 1763 if (crm < CRm_mask) 1764 return sys_reg(op0, op1, crn, crm + 1, 0); 1765 if (crn < CRn_mask) 1766 return sys_reg(op0, op1, crn + 1, 0, 0); 1767 if (op1 < Op1_mask) 1768 return sys_reg(op0, op1 + 1, 0, 0, 0); 1769 1770 return sys_reg(op0 + 1, 0, 0, 0, 0); 1771 } 1772 1773 int __init populate_nv_trap_config(void) 1774 { 1775 int ret = 0; 1776 1777 BUILD_BUG_ON(sizeof(union trap_config) != sizeof(void *)); 1778 BUILD_BUG_ON(__NR_CGT_GROUP_IDS__ > BIT(TC_CGT_BITS)); 1779 BUILD_BUG_ON(__NR_FGT_GROUP_IDS__ > BIT(TC_FGT_BITS)); 1780 BUILD_BUG_ON(__NR_FG_FILTER_IDS__ > BIT(TC_FGF_BITS)); 1781 1782 for (int i = 0; i < ARRAY_SIZE(encoding_to_cgt); i++) { 1783 const struct encoding_to_trap_config *cgt = &encoding_to_cgt[i]; 1784 void *prev; 1785 1786 if (cgt->tc.val & BIT(63)) { 1787 kvm_err("CGT[%d] has MBZ bit set\n", i); 1788 ret = -EINVAL; 1789 } 1790 1791 for (u32 enc = cgt->encoding; enc <= cgt->end; enc = encoding_next(enc)) { 1792 prev = xa_store(&sr_forward_xa, enc, 1793 xa_mk_value(cgt->tc.val), GFP_KERNEL); 1794 if (prev && !xa_is_err(prev)) { 1795 ret = -EINVAL; 1796 print_nv_trap_error(cgt, "Duplicate CGT", ret); 1797 } 1798 1799 if (xa_is_err(prev)) { 1800 ret = xa_err(prev); 1801 print_nv_trap_error(cgt, "Failed CGT insertion", ret); 1802 } 1803 } 1804 } 1805 1806 kvm_info("nv: %ld coarse grained trap handlers\n", 1807 ARRAY_SIZE(encoding_to_cgt)); 1808 1809 if (!cpus_have_final_cap(ARM64_HAS_FGT)) 1810 goto check_mcb; 1811 1812 for (int i = 0; i < ARRAY_SIZE(encoding_to_fgt); i++) { 1813 const struct encoding_to_trap_config *fgt = &encoding_to_fgt[i]; 1814 union trap_config tc; 1815 void *prev; 1816 1817 if (fgt->tc.fgt >= __NR_FGT_GROUP_IDS__) { 1818 ret = -EINVAL; 1819 print_nv_trap_error(fgt, "Invalid FGT", ret); 1820 } 1821 1822 tc = get_trap_config(fgt->encoding); 1823 1824 if (tc.fgt) { 1825 ret = -EINVAL; 1826 print_nv_trap_error(fgt, "Duplicate FGT", ret); 1827 } 1828 1829 tc.val |= fgt->tc.val; 1830 prev = xa_store(&sr_forward_xa, fgt->encoding, 1831 xa_mk_value(tc.val), GFP_KERNEL); 1832 1833 if (xa_is_err(prev)) { 1834 ret = xa_err(prev); 1835 print_nv_trap_error(fgt, "Failed FGT insertion", ret); 1836 } 1837 } 1838 1839 kvm_info("nv: %ld fine grained trap handlers\n", 1840 ARRAY_SIZE(encoding_to_fgt)); 1841 1842 check_mcb: 1843 for (int id = __MULTIPLE_CONTROL_BITS__; id < __COMPLEX_CONDITIONS__; id++) { 1844 const enum cgt_group_id *cgids; 1845 1846 cgids = coarse_control_combo[id - __MULTIPLE_CONTROL_BITS__]; 1847 1848 for (int i = 0; cgids[i] != __RESERVED__; i++) { 1849 if (cgids[i] >= __MULTIPLE_CONTROL_BITS__) { 1850 kvm_err("Recursive MCB %d/%d\n", id, cgids[i]); 1851 ret = -EINVAL; 1852 } 1853 } 1854 } 1855 1856 if (ret) 1857 xa_destroy(&sr_forward_xa); 1858 1859 return ret; 1860 } 1861 1862 int __init populate_sysreg_config(const struct sys_reg_desc *sr, 1863 unsigned int idx) 1864 { 1865 union trap_config tc; 1866 u32 encoding; 1867 void *ret; 1868 1869 /* 1870 * 0 is a valid value for the index, but not for the storage. 1871 * We'll store (idx+1), so check against an offset'd limit. 1872 */ 1873 if (idx >= (BIT(TC_SRI_BITS) - 1)) { 1874 kvm_err("sysreg %s (%d) out of range\n", sr->name, idx); 1875 return -EINVAL; 1876 } 1877 1878 encoding = sys_reg(sr->Op0, sr->Op1, sr->CRn, sr->CRm, sr->Op2); 1879 tc = get_trap_config(encoding); 1880 1881 if (tc.sri) { 1882 kvm_err("sysreg %s (%d) duplicate entry (%d)\n", 1883 sr->name, idx - 1, tc.sri); 1884 return -EINVAL; 1885 } 1886 1887 tc.sri = idx + 1; 1888 ret = xa_store(&sr_forward_xa, encoding, 1889 xa_mk_value(tc.val), GFP_KERNEL); 1890 1891 return xa_err(ret); 1892 } 1893 1894 static enum trap_behaviour get_behaviour(struct kvm_vcpu *vcpu, 1895 const struct trap_bits *tb) 1896 { 1897 enum trap_behaviour b = BEHAVE_HANDLE_LOCALLY; 1898 u64 val; 1899 1900 val = __vcpu_sys_reg(vcpu, tb->index); 1901 if ((val & tb->mask) == tb->value) 1902 b |= tb->behaviour; 1903 1904 return b; 1905 } 1906 1907 static enum trap_behaviour __compute_trap_behaviour(struct kvm_vcpu *vcpu, 1908 const enum cgt_group_id id, 1909 enum trap_behaviour b) 1910 { 1911 switch (id) { 1912 const enum cgt_group_id *cgids; 1913 1914 case __RESERVED__ ... __MULTIPLE_CONTROL_BITS__ - 1: 1915 if (likely(id != __RESERVED__)) 1916 b |= get_behaviour(vcpu, &coarse_trap_bits[id]); 1917 break; 1918 case __MULTIPLE_CONTROL_BITS__ ... __COMPLEX_CONDITIONS__ - 1: 1919 /* Yes, this is recursive. Don't do anything stupid. */ 1920 cgids = coarse_control_combo[id - __MULTIPLE_CONTROL_BITS__]; 1921 for (int i = 0; cgids[i] != __RESERVED__; i++) 1922 b |= __compute_trap_behaviour(vcpu, cgids[i], b); 1923 break; 1924 default: 1925 if (ARRAY_SIZE(ccc)) 1926 b |= ccc[id - __COMPLEX_CONDITIONS__](vcpu); 1927 break; 1928 } 1929 1930 return b; 1931 } 1932 1933 static enum trap_behaviour compute_trap_behaviour(struct kvm_vcpu *vcpu, 1934 const union trap_config tc) 1935 { 1936 enum trap_behaviour b = BEHAVE_HANDLE_LOCALLY; 1937 1938 return __compute_trap_behaviour(vcpu, tc.cgt, b); 1939 } 1940 1941 static u64 kvm_get_sysreg_res0(struct kvm *kvm, enum vcpu_sysreg sr) 1942 { 1943 struct kvm_sysreg_masks *masks; 1944 1945 /* Only handle the VNCR-backed regs for now */ 1946 if (sr < __VNCR_START__) 1947 return 0; 1948 1949 masks = kvm->arch.sysreg_masks; 1950 1951 return masks->mask[sr - __VNCR_START__].res0; 1952 } 1953 1954 static bool check_fgt_bit(struct kvm *kvm, bool is_read, 1955 u64 val, const union trap_config tc) 1956 { 1957 enum vcpu_sysreg sr; 1958 1959 if (tc.pol) 1960 return (val & BIT(tc.bit)); 1961 1962 /* 1963 * FGTs with negative polarities are an absolute nightmare, as 1964 * we need to evaluate the bit in the light of the feature 1965 * that defines it. WTF were they thinking? 1966 * 1967 * So let's check if the bit has been earmarked as RES0, as 1968 * this indicates an unimplemented feature. 1969 */ 1970 if (val & BIT(tc.bit)) 1971 return false; 1972 1973 switch ((enum fgt_group_id)tc.fgt) { 1974 case HFGxTR_GROUP: 1975 sr = is_read ? HFGRTR_EL2 : HFGWTR_EL2; 1976 break; 1977 1978 case HDFGRTR_GROUP: 1979 sr = is_read ? HDFGRTR_EL2 : HDFGWTR_EL2; 1980 break; 1981 1982 case HAFGRTR_GROUP: 1983 sr = HAFGRTR_EL2; 1984 break; 1985 1986 case HFGITR_GROUP: 1987 sr = HFGITR_EL2; 1988 break; 1989 1990 default: 1991 WARN_ONCE(1, "Unhandled FGT group"); 1992 return false; 1993 } 1994 1995 return !(kvm_get_sysreg_res0(kvm, sr) & BIT(tc.bit)); 1996 } 1997 1998 bool triage_sysreg_trap(struct kvm_vcpu *vcpu, int *sr_index) 1999 { 2000 union trap_config tc; 2001 enum trap_behaviour b; 2002 bool is_read; 2003 u32 sysreg; 2004 u64 esr, val; 2005 2006 esr = kvm_vcpu_get_esr(vcpu); 2007 sysreg = esr_sys64_to_sysreg(esr); 2008 is_read = (esr & ESR_ELx_SYS64_ISS_DIR_MASK) == ESR_ELx_SYS64_ISS_DIR_READ; 2009 2010 tc = get_trap_config(sysreg); 2011 2012 /* 2013 * A value of 0 for the whole entry means that we know nothing 2014 * for this sysreg, and that it cannot be re-injected into the 2015 * nested hypervisor. In this situation, let's cut it short. 2016 */ 2017 if (!tc.val) 2018 goto local; 2019 2020 /* 2021 * If a sysreg can be trapped using a FGT, first check whether we 2022 * trap for the purpose of forbidding the feature. In that case, 2023 * inject an UNDEF. 2024 */ 2025 if (tc.fgt != __NO_FGT_GROUP__ && 2026 (vcpu->kvm->arch.fgu[tc.fgt] & BIT(tc.bit))) { 2027 kvm_inject_undefined(vcpu); 2028 return true; 2029 } 2030 2031 /* 2032 * If we're not nesting, immediately return to the caller, with the 2033 * sysreg index, should we have it. 2034 */ 2035 if (!vcpu_has_nv(vcpu) || is_hyp_ctxt(vcpu)) 2036 goto local; 2037 2038 switch ((enum fgt_group_id)tc.fgt) { 2039 case __NO_FGT_GROUP__: 2040 break; 2041 2042 case HFGxTR_GROUP: 2043 if (is_read) 2044 val = __vcpu_sys_reg(vcpu, HFGRTR_EL2); 2045 else 2046 val = __vcpu_sys_reg(vcpu, HFGWTR_EL2); 2047 break; 2048 2049 case HDFGRTR_GROUP: 2050 if (is_read) 2051 val = __vcpu_sys_reg(vcpu, HDFGRTR_EL2); 2052 else 2053 val = __vcpu_sys_reg(vcpu, HDFGWTR_EL2); 2054 break; 2055 2056 case HAFGRTR_GROUP: 2057 val = __vcpu_sys_reg(vcpu, HAFGRTR_EL2); 2058 break; 2059 2060 case HFGITR_GROUP: 2061 val = __vcpu_sys_reg(vcpu, HFGITR_EL2); 2062 switch (tc.fgf) { 2063 u64 tmp; 2064 2065 case __NO_FGF__: 2066 break; 2067 2068 case HCRX_FGTnXS: 2069 tmp = __vcpu_sys_reg(vcpu, HCRX_EL2); 2070 if (tmp & HCRX_EL2_FGTnXS) 2071 tc.fgt = __NO_FGT_GROUP__; 2072 } 2073 break; 2074 2075 case __NR_FGT_GROUP_IDS__: 2076 /* Something is really wrong, bail out */ 2077 WARN_ONCE(1, "__NR_FGT_GROUP_IDS__"); 2078 goto local; 2079 } 2080 2081 if (tc.fgt != __NO_FGT_GROUP__ && check_fgt_bit(vcpu->kvm, is_read, 2082 val, tc)) 2083 goto inject; 2084 2085 b = compute_trap_behaviour(vcpu, tc); 2086 2087 if (((b & BEHAVE_FORWARD_READ) && is_read) || 2088 ((b & BEHAVE_FORWARD_WRITE) && !is_read)) 2089 goto inject; 2090 2091 local: 2092 if (!tc.sri) { 2093 struct sys_reg_params params; 2094 2095 params = esr_sys64_to_params(esr); 2096 2097 /* 2098 * Check for the IMPDEF range, as per DDI0487 J.a, 2099 * D18.3.2 Reserved encodings for IMPLEMENTATION 2100 * DEFINED registers. 2101 */ 2102 if (!(params.Op0 == 3 && (params.CRn & 0b1011) == 0b1011)) 2103 print_sys_reg_msg(¶ms, 2104 "Unsupported guest access at: %lx\n", 2105 *vcpu_pc(vcpu)); 2106 kvm_inject_undefined(vcpu); 2107 return true; 2108 } 2109 2110 *sr_index = tc.sri - 1; 2111 return false; 2112 2113 inject: 2114 trace_kvm_forward_sysreg_trap(vcpu, sysreg, is_read); 2115 2116 kvm_inject_nested_sync(vcpu, kvm_vcpu_get_esr(vcpu)); 2117 return true; 2118 } 2119 2120 static u64 kvm_check_illegal_exception_return(struct kvm_vcpu *vcpu, u64 spsr) 2121 { 2122 u64 mode = spsr & PSR_MODE_MASK; 2123 2124 /* 2125 * Possible causes for an Illegal Exception Return from EL2: 2126 * - trying to return to EL3 2127 * - trying to return to an illegal M value 2128 * - trying to return to a 32bit EL 2129 * - trying to return to EL1 with HCR_EL2.TGE set 2130 */ 2131 if (mode == PSR_MODE_EL3t || mode == PSR_MODE_EL3h || 2132 mode == 0b00001 || (mode & BIT(1)) || 2133 (spsr & PSR_MODE32_BIT) || 2134 (vcpu_el2_tge_is_set(vcpu) && (mode == PSR_MODE_EL1t || 2135 mode == PSR_MODE_EL1h))) { 2136 /* 2137 * The guest is playing with our nerves. Preserve EL, SP, 2138 * masks, flags from the existing PSTATE, and set IL. 2139 * The HW will then generate an Illegal State Exception 2140 * immediately after ERET. 2141 */ 2142 spsr = *vcpu_cpsr(vcpu); 2143 2144 spsr &= (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT | 2145 PSR_N_BIT | PSR_Z_BIT | PSR_C_BIT | PSR_V_BIT | 2146 PSR_MODE_MASK | PSR_MODE32_BIT); 2147 spsr |= PSR_IL_BIT; 2148 } 2149 2150 return spsr; 2151 } 2152 2153 void kvm_emulate_nested_eret(struct kvm_vcpu *vcpu) 2154 { 2155 u64 spsr, elr, mode; 2156 bool direct_eret; 2157 2158 /* 2159 * Going through the whole put/load motions is a waste of time 2160 * if this is a VHE guest hypervisor returning to its own 2161 * userspace, or the hypervisor performing a local exception 2162 * return. No need to save/restore registers, no need to 2163 * switch S2 MMU. Just do the canonical ERET. 2164 */ 2165 spsr = vcpu_read_sys_reg(vcpu, SPSR_EL2); 2166 spsr = kvm_check_illegal_exception_return(vcpu, spsr); 2167 2168 mode = spsr & (PSR_MODE_MASK | PSR_MODE32_BIT); 2169 2170 direct_eret = (mode == PSR_MODE_EL0t && 2171 vcpu_el2_e2h_is_set(vcpu) && 2172 vcpu_el2_tge_is_set(vcpu)); 2173 direct_eret |= (mode == PSR_MODE_EL2h || mode == PSR_MODE_EL2t); 2174 2175 if (direct_eret) { 2176 *vcpu_pc(vcpu) = vcpu_read_sys_reg(vcpu, ELR_EL2); 2177 *vcpu_cpsr(vcpu) = spsr; 2178 trace_kvm_nested_eret(vcpu, *vcpu_pc(vcpu), spsr); 2179 return; 2180 } 2181 2182 preempt_disable(); 2183 kvm_arch_vcpu_put(vcpu); 2184 2185 elr = __vcpu_sys_reg(vcpu, ELR_EL2); 2186 2187 trace_kvm_nested_eret(vcpu, elr, spsr); 2188 2189 /* 2190 * Note that the current exception level is always the virtual EL2, 2191 * since we set HCR_EL2.NV bit only when entering the virtual EL2. 2192 */ 2193 *vcpu_pc(vcpu) = elr; 2194 *vcpu_cpsr(vcpu) = spsr; 2195 2196 kvm_arch_vcpu_load(vcpu, smp_processor_id()); 2197 preempt_enable(); 2198 } 2199 2200 static void kvm_inject_el2_exception(struct kvm_vcpu *vcpu, u64 esr_el2, 2201 enum exception_type type) 2202 { 2203 trace_kvm_inject_nested_exception(vcpu, esr_el2, type); 2204 2205 switch (type) { 2206 case except_type_sync: 2207 kvm_pend_exception(vcpu, EXCEPT_AA64_EL2_SYNC); 2208 vcpu_write_sys_reg(vcpu, esr_el2, ESR_EL2); 2209 break; 2210 case except_type_irq: 2211 kvm_pend_exception(vcpu, EXCEPT_AA64_EL2_IRQ); 2212 break; 2213 default: 2214 WARN_ONCE(1, "Unsupported EL2 exception injection %d\n", type); 2215 } 2216 } 2217 2218 /* 2219 * Emulate taking an exception to EL2. 2220 * See ARM ARM J8.1.2 AArch64.TakeException() 2221 */ 2222 static int kvm_inject_nested(struct kvm_vcpu *vcpu, u64 esr_el2, 2223 enum exception_type type) 2224 { 2225 u64 pstate, mode; 2226 bool direct_inject; 2227 2228 if (!vcpu_has_nv(vcpu)) { 2229 kvm_err("Unexpected call to %s for the non-nesting configuration\n", 2230 __func__); 2231 return -EINVAL; 2232 } 2233 2234 /* 2235 * As for ERET, we can avoid doing too much on the injection path by 2236 * checking that we either took the exception from a VHE host 2237 * userspace or from vEL2. In these cases, there is no change in 2238 * translation regime (or anything else), so let's do as little as 2239 * possible. 2240 */ 2241 pstate = *vcpu_cpsr(vcpu); 2242 mode = pstate & (PSR_MODE_MASK | PSR_MODE32_BIT); 2243 2244 direct_inject = (mode == PSR_MODE_EL0t && 2245 vcpu_el2_e2h_is_set(vcpu) && 2246 vcpu_el2_tge_is_set(vcpu)); 2247 direct_inject |= (mode == PSR_MODE_EL2h || mode == PSR_MODE_EL2t); 2248 2249 if (direct_inject) { 2250 kvm_inject_el2_exception(vcpu, esr_el2, type); 2251 return 1; 2252 } 2253 2254 preempt_disable(); 2255 2256 /* 2257 * We may have an exception or PC update in the EL0/EL1 context. 2258 * Commit it before entering EL2. 2259 */ 2260 __kvm_adjust_pc(vcpu); 2261 2262 kvm_arch_vcpu_put(vcpu); 2263 2264 kvm_inject_el2_exception(vcpu, esr_el2, type); 2265 2266 /* 2267 * A hard requirement is that a switch between EL1 and EL2 2268 * contexts has to happen between a put/load, so that we can 2269 * pick the correct timer and interrupt configuration, among 2270 * other things. 2271 * 2272 * Make sure the exception actually took place before we load 2273 * the new context. 2274 */ 2275 __kvm_adjust_pc(vcpu); 2276 2277 kvm_arch_vcpu_load(vcpu, smp_processor_id()); 2278 preempt_enable(); 2279 2280 return 1; 2281 } 2282 2283 int kvm_inject_nested_sync(struct kvm_vcpu *vcpu, u64 esr_el2) 2284 { 2285 return kvm_inject_nested(vcpu, esr_el2, except_type_sync); 2286 } 2287 2288 int kvm_inject_nested_irq(struct kvm_vcpu *vcpu) 2289 { 2290 /* 2291 * Do not inject an irq if the: 2292 * - Current exception level is EL2, and 2293 * - virtual HCR_EL2.TGE == 0 2294 * - virtual HCR_EL2.IMO == 0 2295 * 2296 * See Table D1-17 "Physical interrupt target and masking when EL3 is 2297 * not implemented and EL2 is implemented" in ARM DDI 0487C.a. 2298 */ 2299 2300 if (vcpu_is_el2(vcpu) && !vcpu_el2_tge_is_set(vcpu) && 2301 !(__vcpu_sys_reg(vcpu, HCR_EL2) & HCR_IMO)) 2302 return 1; 2303 2304 /* esr_el2 value doesn't matter for exits due to irqs. */ 2305 return kvm_inject_nested(vcpu, 0, except_type_irq); 2306 } 2307