1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2016 - Linaro and Columbia University 4 * Author: Jintack Lim <jintack.lim@linaro.org> 5 */ 6 7 #include <linux/kvm.h> 8 #include <linux/kvm_host.h> 9 10 #include <asm/kvm_emulate.h> 11 #include <asm/kvm_nested.h> 12 13 #include "hyp/include/hyp/adjust_pc.h" 14 15 #include "trace.h" 16 17 enum trap_behaviour { 18 BEHAVE_HANDLE_LOCALLY = 0, 19 20 BEHAVE_FORWARD_READ = BIT(0), 21 BEHAVE_FORWARD_WRITE = BIT(1), 22 BEHAVE_FORWARD_RW = BEHAVE_FORWARD_READ | BEHAVE_FORWARD_WRITE, 23 24 /* Traps that take effect in Host EL0, this is rare! */ 25 BEHAVE_FORWARD_IN_HOST_EL0 = BIT(2), 26 }; 27 28 struct trap_bits { 29 const enum vcpu_sysreg index; 30 const enum trap_behaviour behaviour; 31 const u64 value; 32 const u64 mask; 33 }; 34 35 /* Coarse Grained Trap definitions */ 36 enum cgt_group_id { 37 /* Indicates no coarse trap control */ 38 __RESERVED__, 39 40 /* 41 * The first batch of IDs denote coarse trapping that are used 42 * on their own instead of being part of a combination of 43 * trap controls. 44 */ 45 CGT_HCR_TID1, 46 CGT_HCR_TID2, 47 CGT_HCR_TID3, 48 CGT_HCR_IMO, 49 CGT_HCR_FMO, 50 CGT_HCR_TIDCP, 51 CGT_HCR_TACR, 52 CGT_HCR_TSW, 53 CGT_HCR_TPC, 54 CGT_HCR_TPU, 55 CGT_HCR_TTLB, 56 CGT_HCR_TVM, 57 CGT_HCR_TDZ, 58 CGT_HCR_TRVM, 59 CGT_HCR_TLOR, 60 CGT_HCR_TERR, 61 CGT_HCR_APK, 62 CGT_HCR_NV, 63 CGT_HCR_NV_nNV2, 64 CGT_HCR_NV1_nNV2, 65 CGT_HCR_AT, 66 CGT_HCR_nFIEN, 67 CGT_HCR_TID4, 68 CGT_HCR_TICAB, 69 CGT_HCR_TOCU, 70 CGT_HCR_ENSCXT, 71 CGT_HCR_TTLBIS, 72 CGT_HCR_TTLBOS, 73 CGT_HCR_TID5, 74 75 CGT_MDCR_TPMCR, 76 CGT_MDCR_TPM, 77 CGT_MDCR_TDE, 78 CGT_MDCR_TDA, 79 CGT_MDCR_TDOSA, 80 CGT_MDCR_TDRA, 81 CGT_MDCR_E2PB, 82 CGT_MDCR_TPMS, 83 CGT_MDCR_TTRF, 84 CGT_MDCR_E2TB, 85 CGT_MDCR_TDCC, 86 87 CGT_CPTR_TAM, 88 CGT_CPTR_TCPAC, 89 90 CGT_HCRX_EnFPM, 91 CGT_HCRX_TCR2En, 92 CGT_HCRX_SCTLR2En, 93 94 CGT_CNTHCTL_EL1TVT, 95 CGT_CNTHCTL_EL1TVCT, 96 97 CGT_ICH_HCR_TC, 98 CGT_ICH_HCR_TALL0, 99 CGT_ICH_HCR_TALL1, 100 CGT_ICH_HCR_TDIR, 101 102 /* 103 * Anything after this point is a combination of coarse trap 104 * controls, which must all be evaluated to decide what to do. 105 */ 106 __MULTIPLE_CONTROL_BITS__, 107 CGT_HCR_IMO_FMO_ICH_HCR_TC = __MULTIPLE_CONTROL_BITS__, 108 CGT_HCR_TID2_TID4, 109 CGT_HCR_TTLB_TTLBIS, 110 CGT_HCR_TTLB_TTLBOS, 111 CGT_HCR_TVM_TRVM, 112 CGT_HCR_TVM_TRVM_HCRX_TCR2En, 113 CGT_HCR_TVM_TRVM_HCRX_SCTLR2En, 114 CGT_HCR_TPU_TICAB, 115 CGT_HCR_TPU_TOCU, 116 CGT_HCR_NV1_nNV2_ENSCXT, 117 CGT_MDCR_TPM_TPMCR, 118 CGT_MDCR_TPM_HPMN, 119 CGT_MDCR_TDE_TDA, 120 CGT_MDCR_TDE_TDOSA, 121 CGT_MDCR_TDE_TDRA, 122 CGT_MDCR_TDCC_TDE_TDA, 123 124 CGT_ICH_HCR_TC_TDIR, 125 126 /* 127 * Anything after this point requires a callback evaluating a 128 * complex trap condition. Ugly stuff. 129 */ 130 __COMPLEX_CONDITIONS__, 131 CGT_CNTHCTL_EL1PCTEN = __COMPLEX_CONDITIONS__, 132 CGT_CNTHCTL_EL1PTEN, 133 CGT_CNTHCTL_EL1NVPCT, 134 CGT_CNTHCTL_EL1NVVCT, 135 136 CGT_CPTR_TTA, 137 CGT_MDCR_HPMN, 138 139 CGT_HCR_NV_HCRX_nNVTGE, 140 141 /* Must be last */ 142 __NR_CGT_GROUP_IDS__ 143 }; 144 145 static const struct trap_bits coarse_trap_bits[] = { 146 [CGT_HCR_TID1] = { 147 .index = HCR_EL2, 148 .value = HCR_TID1, 149 .mask = HCR_TID1, 150 .behaviour = BEHAVE_FORWARD_READ, 151 }, 152 [CGT_HCR_TID2] = { 153 .index = HCR_EL2, 154 .value = HCR_TID2, 155 .mask = HCR_TID2, 156 .behaviour = BEHAVE_FORWARD_RW, 157 }, 158 [CGT_HCR_TID3] = { 159 .index = HCR_EL2, 160 .value = HCR_TID3, 161 .mask = HCR_TID3, 162 .behaviour = BEHAVE_FORWARD_READ, 163 }, 164 [CGT_HCR_IMO] = { 165 .index = HCR_EL2, 166 .value = HCR_IMO, 167 .mask = HCR_IMO, 168 .behaviour = BEHAVE_FORWARD_WRITE, 169 }, 170 [CGT_HCR_FMO] = { 171 .index = HCR_EL2, 172 .value = HCR_FMO, 173 .mask = HCR_FMO, 174 .behaviour = BEHAVE_FORWARD_WRITE, 175 }, 176 [CGT_HCR_TIDCP] = { 177 .index = HCR_EL2, 178 .value = HCR_TIDCP, 179 .mask = HCR_TIDCP, 180 .behaviour = BEHAVE_FORWARD_RW, 181 }, 182 [CGT_HCR_TACR] = { 183 .index = HCR_EL2, 184 .value = HCR_TACR, 185 .mask = HCR_TACR, 186 .behaviour = BEHAVE_FORWARD_RW, 187 }, 188 [CGT_HCR_TSW] = { 189 .index = HCR_EL2, 190 .value = HCR_TSW, 191 .mask = HCR_TSW, 192 .behaviour = BEHAVE_FORWARD_RW, 193 }, 194 [CGT_HCR_TPC] = { /* Also called TCPC when FEAT_DPB is implemented */ 195 .index = HCR_EL2, 196 .value = HCR_TPC, 197 .mask = HCR_TPC, 198 .behaviour = BEHAVE_FORWARD_RW, 199 }, 200 [CGT_HCR_TPU] = { 201 .index = HCR_EL2, 202 .value = HCR_TPU, 203 .mask = HCR_TPU, 204 .behaviour = BEHAVE_FORWARD_RW, 205 }, 206 [CGT_HCR_TTLB] = { 207 .index = HCR_EL2, 208 .value = HCR_TTLB, 209 .mask = HCR_TTLB, 210 .behaviour = BEHAVE_FORWARD_RW, 211 }, 212 [CGT_HCR_TVM] = { 213 .index = HCR_EL2, 214 .value = HCR_TVM, 215 .mask = HCR_TVM, 216 .behaviour = BEHAVE_FORWARD_WRITE, 217 }, 218 [CGT_HCR_TDZ] = { 219 .index = HCR_EL2, 220 .value = HCR_TDZ, 221 .mask = HCR_TDZ, 222 .behaviour = BEHAVE_FORWARD_RW, 223 }, 224 [CGT_HCR_TRVM] = { 225 .index = HCR_EL2, 226 .value = HCR_TRVM, 227 .mask = HCR_TRVM, 228 .behaviour = BEHAVE_FORWARD_READ, 229 }, 230 [CGT_HCR_TLOR] = { 231 .index = HCR_EL2, 232 .value = HCR_TLOR, 233 .mask = HCR_TLOR, 234 .behaviour = BEHAVE_FORWARD_RW, 235 }, 236 [CGT_HCR_TERR] = { 237 .index = HCR_EL2, 238 .value = HCR_TERR, 239 .mask = HCR_TERR, 240 .behaviour = BEHAVE_FORWARD_RW, 241 }, 242 [CGT_HCR_APK] = { 243 .index = HCR_EL2, 244 .value = 0, 245 .mask = HCR_APK, 246 .behaviour = BEHAVE_FORWARD_RW, 247 }, 248 [CGT_HCR_NV] = { 249 .index = HCR_EL2, 250 .value = HCR_NV, 251 .mask = HCR_NV, 252 .behaviour = BEHAVE_FORWARD_RW, 253 }, 254 [CGT_HCR_NV_nNV2] = { 255 .index = HCR_EL2, 256 .value = HCR_NV, 257 .mask = HCR_NV | HCR_NV2, 258 .behaviour = BEHAVE_FORWARD_RW, 259 }, 260 [CGT_HCR_NV1_nNV2] = { 261 .index = HCR_EL2, 262 .value = HCR_NV | HCR_NV1, 263 .mask = HCR_NV | HCR_NV1 | HCR_NV2, 264 .behaviour = BEHAVE_FORWARD_RW, 265 }, 266 [CGT_HCR_AT] = { 267 .index = HCR_EL2, 268 .value = HCR_AT, 269 .mask = HCR_AT, 270 .behaviour = BEHAVE_FORWARD_RW, 271 }, 272 [CGT_HCR_nFIEN] = { 273 .index = HCR_EL2, 274 .value = 0, 275 .mask = HCR_FIEN, 276 .behaviour = BEHAVE_FORWARD_RW, 277 }, 278 [CGT_HCR_TID4] = { 279 .index = HCR_EL2, 280 .value = HCR_TID4, 281 .mask = HCR_TID4, 282 .behaviour = BEHAVE_FORWARD_RW, 283 }, 284 [CGT_HCR_TICAB] = { 285 .index = HCR_EL2, 286 .value = HCR_TICAB, 287 .mask = HCR_TICAB, 288 .behaviour = BEHAVE_FORWARD_RW, 289 }, 290 [CGT_HCR_TOCU] = { 291 .index = HCR_EL2, 292 .value = HCR_TOCU, 293 .mask = HCR_TOCU, 294 .behaviour = BEHAVE_FORWARD_RW, 295 }, 296 [CGT_HCR_ENSCXT] = { 297 .index = HCR_EL2, 298 .value = 0, 299 .mask = HCR_ENSCXT, 300 .behaviour = BEHAVE_FORWARD_RW, 301 }, 302 [CGT_HCR_TTLBIS] = { 303 .index = HCR_EL2, 304 .value = HCR_TTLBIS, 305 .mask = HCR_TTLBIS, 306 .behaviour = BEHAVE_FORWARD_RW, 307 }, 308 [CGT_HCR_TTLBOS] = { 309 .index = HCR_EL2, 310 .value = HCR_TTLBOS, 311 .mask = HCR_TTLBOS, 312 .behaviour = BEHAVE_FORWARD_RW, 313 }, 314 [CGT_HCR_TID5] = { 315 .index = HCR_EL2, 316 .value = HCR_TID5, 317 .mask = HCR_TID5, 318 .behaviour = BEHAVE_FORWARD_RW, 319 }, 320 [CGT_MDCR_TPMCR] = { 321 .index = MDCR_EL2, 322 .value = MDCR_EL2_TPMCR, 323 .mask = MDCR_EL2_TPMCR, 324 .behaviour = BEHAVE_FORWARD_RW | 325 BEHAVE_FORWARD_IN_HOST_EL0, 326 }, 327 [CGT_MDCR_TPM] = { 328 .index = MDCR_EL2, 329 .value = MDCR_EL2_TPM, 330 .mask = MDCR_EL2_TPM, 331 .behaviour = BEHAVE_FORWARD_RW | 332 BEHAVE_FORWARD_IN_HOST_EL0, 333 }, 334 [CGT_MDCR_TDE] = { 335 .index = MDCR_EL2, 336 .value = MDCR_EL2_TDE, 337 .mask = MDCR_EL2_TDE, 338 .behaviour = BEHAVE_FORWARD_RW, 339 }, 340 [CGT_MDCR_TDA] = { 341 .index = MDCR_EL2, 342 .value = MDCR_EL2_TDA, 343 .mask = MDCR_EL2_TDA, 344 .behaviour = BEHAVE_FORWARD_RW, 345 }, 346 [CGT_MDCR_TDOSA] = { 347 .index = MDCR_EL2, 348 .value = MDCR_EL2_TDOSA, 349 .mask = MDCR_EL2_TDOSA, 350 .behaviour = BEHAVE_FORWARD_RW, 351 }, 352 [CGT_MDCR_TDRA] = { 353 .index = MDCR_EL2, 354 .value = MDCR_EL2_TDRA, 355 .mask = MDCR_EL2_TDRA, 356 .behaviour = BEHAVE_FORWARD_RW, 357 }, 358 [CGT_MDCR_E2PB] = { 359 .index = MDCR_EL2, 360 .value = 0, 361 .mask = BIT(MDCR_EL2_E2PB_SHIFT), 362 .behaviour = BEHAVE_FORWARD_RW, 363 }, 364 [CGT_MDCR_TPMS] = { 365 .index = MDCR_EL2, 366 .value = MDCR_EL2_TPMS, 367 .mask = MDCR_EL2_TPMS, 368 .behaviour = BEHAVE_FORWARD_RW, 369 }, 370 [CGT_MDCR_TTRF] = { 371 .index = MDCR_EL2, 372 .value = MDCR_EL2_TTRF, 373 .mask = MDCR_EL2_TTRF, 374 .behaviour = BEHAVE_FORWARD_RW, 375 }, 376 [CGT_MDCR_E2TB] = { 377 .index = MDCR_EL2, 378 .value = 0, 379 .mask = BIT(MDCR_EL2_E2TB_SHIFT), 380 .behaviour = BEHAVE_FORWARD_RW, 381 }, 382 [CGT_MDCR_TDCC] = { 383 .index = MDCR_EL2, 384 .value = MDCR_EL2_TDCC, 385 .mask = MDCR_EL2_TDCC, 386 .behaviour = BEHAVE_FORWARD_RW, 387 }, 388 [CGT_CPTR_TAM] = { 389 .index = CPTR_EL2, 390 .value = CPTR_EL2_TAM, 391 .mask = CPTR_EL2_TAM, 392 .behaviour = BEHAVE_FORWARD_RW, 393 }, 394 [CGT_CPTR_TCPAC] = { 395 .index = CPTR_EL2, 396 .value = CPTR_EL2_TCPAC, 397 .mask = CPTR_EL2_TCPAC, 398 .behaviour = BEHAVE_FORWARD_RW, 399 }, 400 [CGT_HCRX_EnFPM] = { 401 .index = HCRX_EL2, 402 .value = 0, 403 .mask = HCRX_EL2_EnFPM, 404 .behaviour = BEHAVE_FORWARD_RW, 405 }, 406 [CGT_HCRX_TCR2En] = { 407 .index = HCRX_EL2, 408 .value = 0, 409 .mask = HCRX_EL2_TCR2En, 410 .behaviour = BEHAVE_FORWARD_RW, 411 }, 412 [CGT_HCRX_SCTLR2En] = { 413 .index = HCRX_EL2, 414 .value = 0, 415 .mask = HCRX_EL2_SCTLR2En, 416 .behaviour = BEHAVE_FORWARD_RW, 417 }, 418 [CGT_CNTHCTL_EL1TVT] = { 419 .index = CNTHCTL_EL2, 420 .value = CNTHCTL_EL1TVT, 421 .mask = CNTHCTL_EL1TVT, 422 .behaviour = BEHAVE_FORWARD_RW, 423 }, 424 [CGT_CNTHCTL_EL1TVCT] = { 425 .index = CNTHCTL_EL2, 426 .value = CNTHCTL_EL1TVCT, 427 .mask = CNTHCTL_EL1TVCT, 428 .behaviour = BEHAVE_FORWARD_READ, 429 }, 430 [CGT_ICH_HCR_TC] = { 431 .index = ICH_HCR_EL2, 432 .value = ICH_HCR_EL2_TC, 433 .mask = ICH_HCR_EL2_TC, 434 .behaviour = BEHAVE_FORWARD_RW, 435 }, 436 [CGT_ICH_HCR_TALL0] = { 437 .index = ICH_HCR_EL2, 438 .value = ICH_HCR_EL2_TALL0, 439 .mask = ICH_HCR_EL2_TALL0, 440 .behaviour = BEHAVE_FORWARD_RW, 441 }, 442 [CGT_ICH_HCR_TALL1] = { 443 .index = ICH_HCR_EL2, 444 .value = ICH_HCR_EL2_TALL1, 445 .mask = ICH_HCR_EL2_TALL1, 446 .behaviour = BEHAVE_FORWARD_RW, 447 }, 448 [CGT_ICH_HCR_TDIR] = { 449 .index = ICH_HCR_EL2, 450 .value = ICH_HCR_EL2_TDIR, 451 .mask = ICH_HCR_EL2_TDIR, 452 .behaviour = BEHAVE_FORWARD_RW, 453 }, 454 }; 455 456 #define MCB(id, ...) \ 457 [id - __MULTIPLE_CONTROL_BITS__] = \ 458 (const enum cgt_group_id[]){ \ 459 __VA_ARGS__, __RESERVED__ \ 460 } 461 462 static const enum cgt_group_id *coarse_control_combo[] = { 463 MCB(CGT_HCR_TID2_TID4, CGT_HCR_TID2, CGT_HCR_TID4), 464 MCB(CGT_HCR_TTLB_TTLBIS, CGT_HCR_TTLB, CGT_HCR_TTLBIS), 465 MCB(CGT_HCR_TTLB_TTLBOS, CGT_HCR_TTLB, CGT_HCR_TTLBOS), 466 MCB(CGT_HCR_TVM_TRVM, CGT_HCR_TVM, CGT_HCR_TRVM), 467 MCB(CGT_HCR_TVM_TRVM_HCRX_TCR2En, 468 CGT_HCR_TVM, CGT_HCR_TRVM, CGT_HCRX_TCR2En), 469 MCB(CGT_HCR_TVM_TRVM_HCRX_SCTLR2En, 470 CGT_HCR_TVM, CGT_HCR_TRVM, CGT_HCRX_SCTLR2En), 471 MCB(CGT_HCR_TPU_TICAB, CGT_HCR_TPU, CGT_HCR_TICAB), 472 MCB(CGT_HCR_TPU_TOCU, CGT_HCR_TPU, CGT_HCR_TOCU), 473 MCB(CGT_HCR_NV1_nNV2_ENSCXT, CGT_HCR_NV1_nNV2, CGT_HCR_ENSCXT), 474 MCB(CGT_MDCR_TPM_TPMCR, CGT_MDCR_TPM, CGT_MDCR_TPMCR), 475 MCB(CGT_MDCR_TPM_HPMN, CGT_MDCR_TPM, CGT_MDCR_HPMN), 476 MCB(CGT_MDCR_TDE_TDA, CGT_MDCR_TDE, CGT_MDCR_TDA), 477 MCB(CGT_MDCR_TDE_TDOSA, CGT_MDCR_TDE, CGT_MDCR_TDOSA), 478 MCB(CGT_MDCR_TDE_TDRA, CGT_MDCR_TDE, CGT_MDCR_TDRA), 479 MCB(CGT_MDCR_TDCC_TDE_TDA, CGT_MDCR_TDCC, CGT_MDCR_TDE, CGT_MDCR_TDA), 480 481 MCB(CGT_HCR_IMO_FMO_ICH_HCR_TC, CGT_HCR_IMO, CGT_HCR_FMO, CGT_ICH_HCR_TC), 482 MCB(CGT_ICH_HCR_TC_TDIR, CGT_ICH_HCR_TC, CGT_ICH_HCR_TDIR), 483 }; 484 485 typedef enum trap_behaviour (*complex_condition_check)(struct kvm_vcpu *); 486 487 /* 488 * Warning, maximum confusion ahead. 489 * 490 * When E2H=0, CNTHCTL_EL2[1:0] are defined as EL1PCEN:EL1PCTEN 491 * When E2H=1, CNTHCTL_EL2[11:10] are defined as EL1PTEN:EL1PCTEN 492 * 493 * Note the single letter difference? Yet, the bits have the same 494 * function despite a different layout and a different name. 495 * 496 * We don't try to reconcile this mess. We just use the E2H=0 bits 497 * to generate something that is in the E2H=1 format, and live with 498 * it. You're welcome. 499 */ 500 static u64 get_sanitized_cnthctl(struct kvm_vcpu *vcpu) 501 { 502 u64 val = __vcpu_sys_reg(vcpu, CNTHCTL_EL2); 503 504 if (!vcpu_el2_e2h_is_set(vcpu)) 505 val = (val & (CNTHCTL_EL1PCEN | CNTHCTL_EL1PCTEN)) << 10; 506 507 return val & ((CNTHCTL_EL1PCEN | CNTHCTL_EL1PCTEN) << 10); 508 } 509 510 static enum trap_behaviour check_cnthctl_el1pcten(struct kvm_vcpu *vcpu) 511 { 512 if (get_sanitized_cnthctl(vcpu) & (CNTHCTL_EL1PCTEN << 10)) 513 return BEHAVE_HANDLE_LOCALLY; 514 515 return BEHAVE_FORWARD_RW; 516 } 517 518 static enum trap_behaviour check_cnthctl_el1pten(struct kvm_vcpu *vcpu) 519 { 520 if (get_sanitized_cnthctl(vcpu) & (CNTHCTL_EL1PCEN << 10)) 521 return BEHAVE_HANDLE_LOCALLY; 522 523 return BEHAVE_FORWARD_RW; 524 } 525 526 static bool is_nested_nv2_guest(struct kvm_vcpu *vcpu) 527 { 528 u64 val; 529 530 val = __vcpu_sys_reg(vcpu, HCR_EL2); 531 return ((val & (HCR_E2H | HCR_TGE | HCR_NV2 | HCR_NV1 | HCR_NV)) == (HCR_E2H | HCR_NV2 | HCR_NV)); 532 } 533 534 static enum trap_behaviour check_cnthctl_el1nvpct(struct kvm_vcpu *vcpu) 535 { 536 if (!is_nested_nv2_guest(vcpu) || 537 !(__vcpu_sys_reg(vcpu, CNTHCTL_EL2) & CNTHCTL_EL1NVPCT)) 538 return BEHAVE_HANDLE_LOCALLY; 539 540 return BEHAVE_FORWARD_RW; 541 } 542 543 static enum trap_behaviour check_cnthctl_el1nvvct(struct kvm_vcpu *vcpu) 544 { 545 if (!is_nested_nv2_guest(vcpu) || 546 !(__vcpu_sys_reg(vcpu, CNTHCTL_EL2) & CNTHCTL_EL1NVVCT)) 547 return BEHAVE_HANDLE_LOCALLY; 548 549 return BEHAVE_FORWARD_RW; 550 } 551 552 static enum trap_behaviour check_cptr_tta(struct kvm_vcpu *vcpu) 553 { 554 u64 val = __vcpu_sys_reg(vcpu, CPTR_EL2); 555 556 if (!vcpu_el2_e2h_is_set(vcpu)) 557 val = translate_cptr_el2_to_cpacr_el1(val); 558 559 if (val & CPACR_EL1_TTA) 560 return BEHAVE_FORWARD_RW; 561 562 return BEHAVE_HANDLE_LOCALLY; 563 } 564 565 static enum trap_behaviour check_mdcr_hpmn(struct kvm_vcpu *vcpu) 566 { 567 u32 sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu)); 568 unsigned int idx; 569 570 571 switch (sysreg) { 572 case SYS_PMEVTYPERn_EL0(0) ... SYS_PMEVTYPERn_EL0(30): 573 case SYS_PMEVCNTRn_EL0(0) ... SYS_PMEVCNTRn_EL0(30): 574 idx = (sys_reg_CRm(sysreg) & 0x3) << 3 | sys_reg_Op2(sysreg); 575 break; 576 case SYS_PMXEVTYPER_EL0: 577 case SYS_PMXEVCNTR_EL0: 578 idx = SYS_FIELD_GET(PMSELR_EL0, SEL, 579 __vcpu_sys_reg(vcpu, PMSELR_EL0)); 580 break; 581 default: 582 /* Someone used this trap helper for something else... */ 583 KVM_BUG_ON(1, vcpu->kvm); 584 return BEHAVE_HANDLE_LOCALLY; 585 } 586 587 if (kvm_pmu_counter_is_hyp(vcpu, idx)) 588 return BEHAVE_FORWARD_RW | BEHAVE_FORWARD_IN_HOST_EL0; 589 590 return BEHAVE_HANDLE_LOCALLY; 591 } 592 593 static enum trap_behaviour check_hcr_nv_hcrx_nnvtge(struct kvm_vcpu *vcpu) 594 { 595 if ((__vcpu_sys_reg(vcpu, HCR_EL2) & HCR_EL2_NV) && 596 !(__vcpu_sys_reg(vcpu, HCRX_EL2) & HCRX_EL2_NVTGE)) 597 return BEHAVE_FORWARD_RW; 598 599 return BEHAVE_HANDLE_LOCALLY; 600 } 601 602 #define CCC(id, fn) \ 603 [id - __COMPLEX_CONDITIONS__] = fn 604 605 static const complex_condition_check ccc[] = { 606 CCC(CGT_CNTHCTL_EL1PCTEN, check_cnthctl_el1pcten), 607 CCC(CGT_CNTHCTL_EL1PTEN, check_cnthctl_el1pten), 608 CCC(CGT_CNTHCTL_EL1NVPCT, check_cnthctl_el1nvpct), 609 CCC(CGT_CNTHCTL_EL1NVVCT, check_cnthctl_el1nvvct), 610 CCC(CGT_CPTR_TTA, check_cptr_tta), 611 CCC(CGT_MDCR_HPMN, check_mdcr_hpmn), 612 CCC(CGT_HCR_NV_HCRX_nNVTGE, check_hcr_nv_hcrx_nnvtge), 613 }; 614 615 /* 616 * Bit assignment for the trap controls. We use a 64bit word with the 617 * following layout for each trapped sysreg: 618 * 619 * [9:0] enum cgt_group_id (10 bits) 620 * [13:10] enum fgt_group_id (4 bits) 621 * [19:14] bit number in the FGT register (6 bits) 622 * [20] trap polarity (1 bit) 623 * [25:21] FG filter (5 bits) 624 * [35:26] Main SysReg table index (10 bits) 625 * [62:36] Unused (27 bits) 626 * [63] RES0 - Must be zero, as lost on insertion in the xarray 627 */ 628 #define TC_CGT_BITS 10 629 #define TC_FGT_BITS 4 630 #define TC_FGF_BITS 5 631 #define TC_SRI_BITS 10 632 633 union trap_config { 634 u64 val; 635 struct { 636 unsigned long cgt:TC_CGT_BITS; /* Coarse Grained Trap id */ 637 unsigned long fgt:TC_FGT_BITS; /* Fine Grained Trap id */ 638 unsigned long bit:6; /* Bit number */ 639 unsigned long pol:1; /* Polarity */ 640 unsigned long fgf:TC_FGF_BITS; /* Fine Grained Filter */ 641 unsigned long sri:TC_SRI_BITS; /* SysReg Index */ 642 unsigned long unused:27; /* Unused, should be zero */ 643 unsigned long mbz:1; /* Must Be Zero */ 644 }; 645 }; 646 647 struct encoding_to_trap_config { 648 const u32 encoding; 649 const u32 end; 650 const union trap_config tc; 651 const unsigned int line; 652 }; 653 654 /* 655 * WARNING: using ranges is a treacherous endeavour, as sysregs that 656 * are part of an architectural range are not necessarily contiguous 657 * in the [Op0,Op1,CRn,CRm,Ops] space. Tread carefully. 658 */ 659 #define SR_RANGE_TRAP(sr_start, sr_end, trap_id) \ 660 { \ 661 .encoding = sr_start, \ 662 .end = sr_end, \ 663 .tc = { \ 664 .cgt = trap_id, \ 665 }, \ 666 .line = __LINE__, \ 667 } 668 669 #define SR_TRAP(sr, trap_id) SR_RANGE_TRAP(sr, sr, trap_id) 670 671 /* 672 * Map encoding to trap bits for exception reported with EC=0x18. 673 * These must only be evaluated when running a nested hypervisor, but 674 * that the current context is not a hypervisor context. When the 675 * trapped access matches one of the trap controls, the exception is 676 * re-injected in the nested hypervisor. 677 */ 678 static const struct encoding_to_trap_config encoding_to_cgt[] __initconst = { 679 SR_TRAP(SYS_REVIDR_EL1, CGT_HCR_TID1), 680 SR_TRAP(SYS_AIDR_EL1, CGT_HCR_TID1), 681 SR_TRAP(SYS_SMIDR_EL1, CGT_HCR_TID1), 682 SR_TRAP(SYS_CTR_EL0, CGT_HCR_TID2), 683 SR_TRAP(SYS_CCSIDR_EL1, CGT_HCR_TID2_TID4), 684 SR_TRAP(SYS_CCSIDR2_EL1, CGT_HCR_TID2_TID4), 685 SR_TRAP(SYS_CLIDR_EL1, CGT_HCR_TID2_TID4), 686 SR_TRAP(SYS_CSSELR_EL1, CGT_HCR_TID2_TID4), 687 SR_TRAP(SYS_GMID_EL1, CGT_HCR_TID5), 688 SR_RANGE_TRAP(SYS_ID_PFR0_EL1, 689 sys_reg(3, 0, 0, 7, 7), CGT_HCR_TID3), 690 SR_TRAP(SYS_ICC_SGI0R_EL1, CGT_HCR_IMO_FMO_ICH_HCR_TC), 691 SR_TRAP(SYS_ICC_ASGI1R_EL1, CGT_HCR_IMO_FMO_ICH_HCR_TC), 692 SR_TRAP(SYS_ICC_SGI1R_EL1, CGT_HCR_IMO_FMO_ICH_HCR_TC), 693 SR_RANGE_TRAP(sys_reg(3, 0, 11, 0, 0), 694 sys_reg(3, 0, 11, 15, 7), CGT_HCR_TIDCP), 695 SR_RANGE_TRAP(sys_reg(3, 1, 11, 0, 0), 696 sys_reg(3, 1, 11, 15, 7), CGT_HCR_TIDCP), 697 SR_RANGE_TRAP(sys_reg(3, 2, 11, 0, 0), 698 sys_reg(3, 2, 11, 15, 7), CGT_HCR_TIDCP), 699 SR_RANGE_TRAP(sys_reg(3, 3, 11, 0, 0), 700 sys_reg(3, 3, 11, 15, 7), CGT_HCR_TIDCP), 701 SR_RANGE_TRAP(sys_reg(3, 4, 11, 0, 0), 702 sys_reg(3, 4, 11, 15, 7), CGT_HCR_TIDCP), 703 SR_RANGE_TRAP(sys_reg(3, 5, 11, 0, 0), 704 sys_reg(3, 5, 11, 15, 7), CGT_HCR_TIDCP), 705 SR_RANGE_TRAP(sys_reg(3, 6, 11, 0, 0), 706 sys_reg(3, 6, 11, 15, 7), CGT_HCR_TIDCP), 707 SR_RANGE_TRAP(sys_reg(3, 7, 11, 0, 0), 708 sys_reg(3, 7, 11, 15, 7), CGT_HCR_TIDCP), 709 SR_RANGE_TRAP(sys_reg(3, 0, 15, 0, 0), 710 sys_reg(3, 0, 15, 15, 7), CGT_HCR_TIDCP), 711 SR_RANGE_TRAP(sys_reg(3, 1, 15, 0, 0), 712 sys_reg(3, 1, 15, 15, 7), CGT_HCR_TIDCP), 713 SR_RANGE_TRAP(sys_reg(3, 2, 15, 0, 0), 714 sys_reg(3, 2, 15, 15, 7), CGT_HCR_TIDCP), 715 SR_RANGE_TRAP(sys_reg(3, 3, 15, 0, 0), 716 sys_reg(3, 3, 15, 15, 7), CGT_HCR_TIDCP), 717 SR_RANGE_TRAP(sys_reg(3, 4, 15, 0, 0), 718 sys_reg(3, 4, 15, 15, 7), CGT_HCR_TIDCP), 719 SR_RANGE_TRAP(sys_reg(3, 5, 15, 0, 0), 720 sys_reg(3, 5, 15, 15, 7), CGT_HCR_TIDCP), 721 SR_RANGE_TRAP(sys_reg(3, 6, 15, 0, 0), 722 sys_reg(3, 6, 15, 15, 7), CGT_HCR_TIDCP), 723 SR_RANGE_TRAP(sys_reg(3, 7, 15, 0, 0), 724 sys_reg(3, 7, 15, 15, 7), CGT_HCR_TIDCP), 725 SR_TRAP(SYS_ACTLR_EL1, CGT_HCR_TACR), 726 SR_TRAP(SYS_DC_ISW, CGT_HCR_TSW), 727 SR_TRAP(SYS_DC_CSW, CGT_HCR_TSW), 728 SR_TRAP(SYS_DC_CISW, CGT_HCR_TSW), 729 SR_TRAP(SYS_DC_IGSW, CGT_HCR_TSW), 730 SR_TRAP(SYS_DC_IGDSW, CGT_HCR_TSW), 731 SR_TRAP(SYS_DC_CGSW, CGT_HCR_TSW), 732 SR_TRAP(SYS_DC_CGDSW, CGT_HCR_TSW), 733 SR_TRAP(SYS_DC_CIGSW, CGT_HCR_TSW), 734 SR_TRAP(SYS_DC_CIGDSW, CGT_HCR_TSW), 735 SR_TRAP(SYS_DC_CIVAC, CGT_HCR_TPC), 736 SR_TRAP(SYS_DC_CVAC, CGT_HCR_TPC), 737 SR_TRAP(SYS_DC_CVAP, CGT_HCR_TPC), 738 SR_TRAP(SYS_DC_CVADP, CGT_HCR_TPC), 739 SR_TRAP(SYS_DC_IVAC, CGT_HCR_TPC), 740 SR_TRAP(SYS_DC_CIGVAC, CGT_HCR_TPC), 741 SR_TRAP(SYS_DC_CIGDVAC, CGT_HCR_TPC), 742 SR_TRAP(SYS_DC_IGVAC, CGT_HCR_TPC), 743 SR_TRAP(SYS_DC_IGDVAC, CGT_HCR_TPC), 744 SR_TRAP(SYS_DC_CGVAC, CGT_HCR_TPC), 745 SR_TRAP(SYS_DC_CGDVAC, CGT_HCR_TPC), 746 SR_TRAP(SYS_DC_CGVAP, CGT_HCR_TPC), 747 SR_TRAP(SYS_DC_CGDVAP, CGT_HCR_TPC), 748 SR_TRAP(SYS_DC_CGVADP, CGT_HCR_TPC), 749 SR_TRAP(SYS_DC_CGDVADP, CGT_HCR_TPC), 750 SR_TRAP(SYS_IC_IVAU, CGT_HCR_TPU_TOCU), 751 SR_TRAP(SYS_IC_IALLU, CGT_HCR_TPU_TOCU), 752 SR_TRAP(SYS_IC_IALLUIS, CGT_HCR_TPU_TICAB), 753 SR_TRAP(SYS_DC_CVAU, CGT_HCR_TPU_TOCU), 754 SR_TRAP(OP_TLBI_RVAE1, CGT_HCR_TTLB), 755 SR_TRAP(OP_TLBI_RVAAE1, CGT_HCR_TTLB), 756 SR_TRAP(OP_TLBI_RVALE1, CGT_HCR_TTLB), 757 SR_TRAP(OP_TLBI_RVAALE1, CGT_HCR_TTLB), 758 SR_TRAP(OP_TLBI_VMALLE1, CGT_HCR_TTLB), 759 SR_TRAP(OP_TLBI_VAE1, CGT_HCR_TTLB), 760 SR_TRAP(OP_TLBI_ASIDE1, CGT_HCR_TTLB), 761 SR_TRAP(OP_TLBI_VAAE1, CGT_HCR_TTLB), 762 SR_TRAP(OP_TLBI_VALE1, CGT_HCR_TTLB), 763 SR_TRAP(OP_TLBI_VAALE1, CGT_HCR_TTLB), 764 SR_TRAP(OP_TLBI_RVAE1NXS, CGT_HCR_TTLB), 765 SR_TRAP(OP_TLBI_RVAAE1NXS, CGT_HCR_TTLB), 766 SR_TRAP(OP_TLBI_RVALE1NXS, CGT_HCR_TTLB), 767 SR_TRAP(OP_TLBI_RVAALE1NXS, CGT_HCR_TTLB), 768 SR_TRAP(OP_TLBI_VMALLE1NXS, CGT_HCR_TTLB), 769 SR_TRAP(OP_TLBI_VAE1NXS, CGT_HCR_TTLB), 770 SR_TRAP(OP_TLBI_ASIDE1NXS, CGT_HCR_TTLB), 771 SR_TRAP(OP_TLBI_VAAE1NXS, CGT_HCR_TTLB), 772 SR_TRAP(OP_TLBI_VALE1NXS, CGT_HCR_TTLB), 773 SR_TRAP(OP_TLBI_VAALE1NXS, CGT_HCR_TTLB), 774 SR_TRAP(OP_TLBI_RVAE1IS, CGT_HCR_TTLB_TTLBIS), 775 SR_TRAP(OP_TLBI_RVAAE1IS, CGT_HCR_TTLB_TTLBIS), 776 SR_TRAP(OP_TLBI_RVALE1IS, CGT_HCR_TTLB_TTLBIS), 777 SR_TRAP(OP_TLBI_RVAALE1IS, CGT_HCR_TTLB_TTLBIS), 778 SR_TRAP(OP_TLBI_VMALLE1IS, CGT_HCR_TTLB_TTLBIS), 779 SR_TRAP(OP_TLBI_VAE1IS, CGT_HCR_TTLB_TTLBIS), 780 SR_TRAP(OP_TLBI_ASIDE1IS, CGT_HCR_TTLB_TTLBIS), 781 SR_TRAP(OP_TLBI_VAAE1IS, CGT_HCR_TTLB_TTLBIS), 782 SR_TRAP(OP_TLBI_VALE1IS, CGT_HCR_TTLB_TTLBIS), 783 SR_TRAP(OP_TLBI_VAALE1IS, CGT_HCR_TTLB_TTLBIS), 784 SR_TRAP(OP_TLBI_RVAE1ISNXS, CGT_HCR_TTLB_TTLBIS), 785 SR_TRAP(OP_TLBI_RVAAE1ISNXS, CGT_HCR_TTLB_TTLBIS), 786 SR_TRAP(OP_TLBI_RVALE1ISNXS, CGT_HCR_TTLB_TTLBIS), 787 SR_TRAP(OP_TLBI_RVAALE1ISNXS, CGT_HCR_TTLB_TTLBIS), 788 SR_TRAP(OP_TLBI_VMALLE1ISNXS, CGT_HCR_TTLB_TTLBIS), 789 SR_TRAP(OP_TLBI_VAE1ISNXS, CGT_HCR_TTLB_TTLBIS), 790 SR_TRAP(OP_TLBI_ASIDE1ISNXS, CGT_HCR_TTLB_TTLBIS), 791 SR_TRAP(OP_TLBI_VAAE1ISNXS, CGT_HCR_TTLB_TTLBIS), 792 SR_TRAP(OP_TLBI_VALE1ISNXS, CGT_HCR_TTLB_TTLBIS), 793 SR_TRAP(OP_TLBI_VAALE1ISNXS, CGT_HCR_TTLB_TTLBIS), 794 SR_TRAP(OP_TLBI_VMALLE1OS, CGT_HCR_TTLB_TTLBOS), 795 SR_TRAP(OP_TLBI_VAE1OS, CGT_HCR_TTLB_TTLBOS), 796 SR_TRAP(OP_TLBI_ASIDE1OS, CGT_HCR_TTLB_TTLBOS), 797 SR_TRAP(OP_TLBI_VAAE1OS, CGT_HCR_TTLB_TTLBOS), 798 SR_TRAP(OP_TLBI_VALE1OS, CGT_HCR_TTLB_TTLBOS), 799 SR_TRAP(OP_TLBI_VAALE1OS, CGT_HCR_TTLB_TTLBOS), 800 SR_TRAP(OP_TLBI_RVAE1OS, CGT_HCR_TTLB_TTLBOS), 801 SR_TRAP(OP_TLBI_RVAAE1OS, CGT_HCR_TTLB_TTLBOS), 802 SR_TRAP(OP_TLBI_RVALE1OS, CGT_HCR_TTLB_TTLBOS), 803 SR_TRAP(OP_TLBI_RVAALE1OS, CGT_HCR_TTLB_TTLBOS), 804 SR_TRAP(OP_TLBI_VMALLE1OSNXS, CGT_HCR_TTLB_TTLBOS), 805 SR_TRAP(OP_TLBI_VAE1OSNXS, CGT_HCR_TTLB_TTLBOS), 806 SR_TRAP(OP_TLBI_ASIDE1OSNXS, CGT_HCR_TTLB_TTLBOS), 807 SR_TRAP(OP_TLBI_VAAE1OSNXS, CGT_HCR_TTLB_TTLBOS), 808 SR_TRAP(OP_TLBI_VALE1OSNXS, CGT_HCR_TTLB_TTLBOS), 809 SR_TRAP(OP_TLBI_VAALE1OSNXS, CGT_HCR_TTLB_TTLBOS), 810 SR_TRAP(OP_TLBI_RVAE1OSNXS, CGT_HCR_TTLB_TTLBOS), 811 SR_TRAP(OP_TLBI_RVAAE1OSNXS, CGT_HCR_TTLB_TTLBOS), 812 SR_TRAP(OP_TLBI_RVALE1OSNXS, CGT_HCR_TTLB_TTLBOS), 813 SR_TRAP(OP_TLBI_RVAALE1OSNXS, CGT_HCR_TTLB_TTLBOS), 814 SR_TRAP(SYS_SCTLR_EL1, CGT_HCR_TVM_TRVM), 815 SR_TRAP(SYS_SCTLR2_EL1, CGT_HCR_TVM_TRVM_HCRX_SCTLR2En), 816 SR_TRAP(SYS_TTBR0_EL1, CGT_HCR_TVM_TRVM), 817 SR_TRAP(SYS_TTBR1_EL1, CGT_HCR_TVM_TRVM), 818 SR_TRAP(SYS_TCR_EL1, CGT_HCR_TVM_TRVM), 819 SR_TRAP(SYS_ESR_EL1, CGT_HCR_TVM_TRVM), 820 SR_TRAP(SYS_FAR_EL1, CGT_HCR_TVM_TRVM), 821 SR_TRAP(SYS_AFSR0_EL1, CGT_HCR_TVM_TRVM), 822 SR_TRAP(SYS_AFSR1_EL1, CGT_HCR_TVM_TRVM), 823 SR_TRAP(SYS_MAIR_EL1, CGT_HCR_TVM_TRVM), 824 SR_TRAP(SYS_AMAIR_EL1, CGT_HCR_TVM_TRVM), 825 SR_TRAP(SYS_CONTEXTIDR_EL1, CGT_HCR_TVM_TRVM), 826 SR_TRAP(SYS_PIR_EL1, CGT_HCR_TVM_TRVM), 827 SR_TRAP(SYS_PIRE0_EL1, CGT_HCR_TVM_TRVM), 828 SR_TRAP(SYS_POR_EL0, CGT_HCR_TVM_TRVM), 829 SR_TRAP(SYS_POR_EL1, CGT_HCR_TVM_TRVM), 830 SR_TRAP(SYS_TCR2_EL1, CGT_HCR_TVM_TRVM_HCRX_TCR2En), 831 SR_TRAP(SYS_DC_ZVA, CGT_HCR_TDZ), 832 SR_TRAP(SYS_DC_GVA, CGT_HCR_TDZ), 833 SR_TRAP(SYS_DC_GZVA, CGT_HCR_TDZ), 834 SR_TRAP(SYS_LORSA_EL1, CGT_HCR_TLOR), 835 SR_TRAP(SYS_LOREA_EL1, CGT_HCR_TLOR), 836 SR_TRAP(SYS_LORN_EL1, CGT_HCR_TLOR), 837 SR_TRAP(SYS_LORC_EL1, CGT_HCR_TLOR), 838 SR_TRAP(SYS_LORID_EL1, CGT_HCR_TLOR), 839 SR_TRAP(SYS_ERRIDR_EL1, CGT_HCR_TERR), 840 SR_TRAP(SYS_ERRSELR_EL1, CGT_HCR_TERR), 841 SR_TRAP(SYS_ERXADDR_EL1, CGT_HCR_TERR), 842 SR_TRAP(SYS_ERXCTLR_EL1, CGT_HCR_TERR), 843 SR_TRAP(SYS_ERXFR_EL1, CGT_HCR_TERR), 844 SR_TRAP(SYS_ERXMISC0_EL1, CGT_HCR_TERR), 845 SR_TRAP(SYS_ERXMISC1_EL1, CGT_HCR_TERR), 846 SR_TRAP(SYS_ERXMISC2_EL1, CGT_HCR_TERR), 847 SR_TRAP(SYS_ERXMISC3_EL1, CGT_HCR_TERR), 848 SR_TRAP(SYS_ERXSTATUS_EL1, CGT_HCR_TERR), 849 SR_TRAP(SYS_APIAKEYLO_EL1, CGT_HCR_APK), 850 SR_TRAP(SYS_APIAKEYHI_EL1, CGT_HCR_APK), 851 SR_TRAP(SYS_APIBKEYLO_EL1, CGT_HCR_APK), 852 SR_TRAP(SYS_APIBKEYHI_EL1, CGT_HCR_APK), 853 SR_TRAP(SYS_APDAKEYLO_EL1, CGT_HCR_APK), 854 SR_TRAP(SYS_APDAKEYHI_EL1, CGT_HCR_APK), 855 SR_TRAP(SYS_APDBKEYLO_EL1, CGT_HCR_APK), 856 SR_TRAP(SYS_APDBKEYHI_EL1, CGT_HCR_APK), 857 SR_TRAP(SYS_APGAKEYLO_EL1, CGT_HCR_APK), 858 SR_TRAP(SYS_APGAKEYHI_EL1, CGT_HCR_APK), 859 /* All _EL2 registers */ 860 SR_TRAP(SYS_BRBCR_EL2, CGT_HCR_NV), 861 SR_TRAP(SYS_VPIDR_EL2, CGT_HCR_NV), 862 SR_TRAP(SYS_VMPIDR_EL2, CGT_HCR_NV), 863 SR_TRAP(SYS_SCTLR_EL2, CGT_HCR_NV), 864 SR_TRAP(SYS_ACTLR_EL2, CGT_HCR_NV), 865 SR_TRAP(SYS_SCTLR2_EL2, CGT_HCR_NV), 866 SR_RANGE_TRAP(SYS_HCR_EL2, 867 SYS_HCRX_EL2, CGT_HCR_NV), 868 SR_TRAP(SYS_NVHCR_EL2, CGT_HCR_NV_HCRX_nNVTGE), 869 SR_TRAP(SYS_SMPRIMAP_EL2, CGT_HCR_NV), 870 SR_TRAP(SYS_SMCR_EL2, CGT_HCR_NV), 871 SR_RANGE_TRAP(SYS_TTBR0_EL2, 872 SYS_TCR2_EL2, CGT_HCR_NV), 873 SR_TRAP(SYS_VTTBR_EL2, CGT_HCR_NV), 874 SR_TRAP(SYS_VTCR_EL2, CGT_HCR_NV), 875 SR_TRAP(SYS_VNCR_EL2, CGT_HCR_NV), 876 SR_RANGE_TRAP(SYS_HDFGRTR_EL2, 877 SYS_HAFGRTR_EL2, CGT_HCR_NV), 878 /* Skip the SP_EL1 encoding... */ 879 SR_TRAP(SYS_SPSR_EL2, CGT_HCR_NV), 880 SR_TRAP(SYS_ELR_EL2, CGT_HCR_NV), 881 /* Skip SPSR_irq, SPSR_abt, SPSR_und, SPSR_fiq */ 882 SR_TRAP(SYS_AFSR0_EL2, CGT_HCR_NV), 883 SR_TRAP(SYS_AFSR1_EL2, CGT_HCR_NV), 884 SR_TRAP(SYS_ESR_EL2, CGT_HCR_NV), 885 SR_TRAP(SYS_VSESR_EL2, CGT_HCR_NV), 886 SR_TRAP(SYS_TFSR_EL2, CGT_HCR_NV), 887 SR_TRAP(SYS_FAR_EL2, CGT_HCR_NV), 888 SR_TRAP(SYS_HPFAR_EL2, CGT_HCR_NV), 889 SR_TRAP(SYS_PMSCR_EL2, CGT_HCR_NV), 890 SR_TRAP(SYS_MAIR_EL2, CGT_HCR_NV), 891 SR_TRAP(SYS_AMAIR_EL2, CGT_HCR_NV), 892 SR_TRAP(SYS_MPAMHCR_EL2, CGT_HCR_NV), 893 SR_TRAP(SYS_MPAMVPMV_EL2, CGT_HCR_NV), 894 SR_TRAP(SYS_MPAM2_EL2, CGT_HCR_NV), 895 SR_RANGE_TRAP(SYS_MPAMVPM0_EL2, 896 SYS_MPAMVPM7_EL2, CGT_HCR_NV), 897 /* 898 * Note that the spec. describes a group of MEC registers 899 * whose access should not trap, therefore skip the following: 900 * MECID_A0_EL2, MECID_A1_EL2, MECID_P0_EL2, 901 * MECID_P1_EL2, MECIDR_EL2, VMECID_A_EL2, 902 * VMECID_P_EL2. 903 */ 904 SR_RANGE_TRAP(SYS_VBAR_EL2, 905 SYS_RMR_EL2, CGT_HCR_NV), 906 SR_TRAP(SYS_VDISR_EL2, CGT_HCR_NV), 907 /* ICH_AP0R<m>_EL2 */ 908 SR_RANGE_TRAP(SYS_ICH_AP0R0_EL2, 909 SYS_ICH_AP0R3_EL2, CGT_HCR_NV), 910 /* ICH_AP1R<m>_EL2 */ 911 SR_RANGE_TRAP(SYS_ICH_AP1R0_EL2, 912 SYS_ICH_AP1R3_EL2, CGT_HCR_NV), 913 SR_TRAP(SYS_ICC_SRE_EL2, CGT_HCR_NV), 914 SR_RANGE_TRAP(SYS_ICH_HCR_EL2, 915 SYS_ICH_EISR_EL2, CGT_HCR_NV), 916 SR_TRAP(SYS_ICH_ELRSR_EL2, CGT_HCR_NV), 917 SR_TRAP(SYS_ICH_VMCR_EL2, CGT_HCR_NV), 918 /* ICH_LR<m>_EL2 */ 919 SR_RANGE_TRAP(SYS_ICH_LR0_EL2, 920 SYS_ICH_LR15_EL2, CGT_HCR_NV), 921 SR_TRAP(SYS_CONTEXTIDR_EL2, CGT_HCR_NV), 922 SR_TRAP(SYS_TPIDR_EL2, CGT_HCR_NV), 923 SR_TRAP(SYS_SCXTNUM_EL2, CGT_HCR_NV), 924 /* AMEVCNTVOFF0<n>_EL2, AMEVCNTVOFF1<n>_EL2 */ 925 SR_RANGE_TRAP(SYS_AMEVCNTVOFF0n_EL2(0), 926 SYS_AMEVCNTVOFF1n_EL2(15), CGT_HCR_NV), 927 /* CNT*_EL2 */ 928 SR_TRAP(SYS_CNTVOFF_EL2, CGT_HCR_NV), 929 SR_TRAP(SYS_CNTPOFF_EL2, CGT_HCR_NV), 930 SR_TRAP(SYS_CNTHCTL_EL2, CGT_HCR_NV), 931 SR_RANGE_TRAP(SYS_CNTHP_TVAL_EL2, 932 SYS_CNTHP_CVAL_EL2, CGT_HCR_NV), 933 SR_RANGE_TRAP(SYS_CNTHV_TVAL_EL2, 934 SYS_CNTHV_CVAL_EL2, CGT_HCR_NV), 935 /* All _EL02, _EL12 registers up to CNTKCTL_EL12*/ 936 SR_RANGE_TRAP(sys_reg(3, 5, 0, 0, 0), 937 sys_reg(3, 5, 10, 15, 7), CGT_HCR_NV), 938 SR_RANGE_TRAP(sys_reg(3, 5, 12, 0, 0), 939 sys_reg(3, 5, 14, 1, 0), CGT_HCR_NV), 940 SR_TRAP(SYS_CNTP_CTL_EL02, CGT_CNTHCTL_EL1NVPCT), 941 SR_TRAP(SYS_CNTP_CVAL_EL02, CGT_CNTHCTL_EL1NVPCT), 942 SR_TRAP(SYS_CNTV_CTL_EL02, CGT_CNTHCTL_EL1NVVCT), 943 SR_TRAP(SYS_CNTV_CVAL_EL02, CGT_CNTHCTL_EL1NVVCT), 944 SR_TRAP(OP_AT_S1E2R, CGT_HCR_NV), 945 SR_TRAP(OP_AT_S1E2W, CGT_HCR_NV), 946 SR_TRAP(OP_AT_S12E1R, CGT_HCR_NV), 947 SR_TRAP(OP_AT_S12E1W, CGT_HCR_NV), 948 SR_TRAP(OP_AT_S12E0R, CGT_HCR_NV), 949 SR_TRAP(OP_AT_S12E0W, CGT_HCR_NV), 950 SR_TRAP(OP_AT_S1E2A, CGT_HCR_NV), 951 SR_TRAP(OP_TLBI_IPAS2E1, CGT_HCR_NV), 952 SR_TRAP(OP_TLBI_RIPAS2E1, CGT_HCR_NV), 953 SR_TRAP(OP_TLBI_IPAS2LE1, CGT_HCR_NV), 954 SR_TRAP(OP_TLBI_RIPAS2LE1, CGT_HCR_NV), 955 SR_TRAP(OP_TLBI_RVAE2, CGT_HCR_NV), 956 SR_TRAP(OP_TLBI_RVALE2, CGT_HCR_NV), 957 SR_TRAP(OP_TLBI_ALLE2, CGT_HCR_NV), 958 SR_TRAP(OP_TLBI_VAE2, CGT_HCR_NV), 959 SR_TRAP(OP_TLBI_ALLE1, CGT_HCR_NV), 960 SR_TRAP(OP_TLBI_VALE2, CGT_HCR_NV), 961 SR_TRAP(OP_TLBI_VMALLS12E1, CGT_HCR_NV), 962 SR_TRAP(OP_TLBI_IPAS2E1NXS, CGT_HCR_NV), 963 SR_TRAP(OP_TLBI_RIPAS2E1NXS, CGT_HCR_NV), 964 SR_TRAP(OP_TLBI_IPAS2LE1NXS, CGT_HCR_NV), 965 SR_TRAP(OP_TLBI_RIPAS2LE1NXS, CGT_HCR_NV), 966 SR_TRAP(OP_TLBI_RVAE2NXS, CGT_HCR_NV), 967 SR_TRAP(OP_TLBI_RVALE2NXS, CGT_HCR_NV), 968 SR_TRAP(OP_TLBI_ALLE2NXS, CGT_HCR_NV), 969 SR_TRAP(OP_TLBI_VAE2NXS, CGT_HCR_NV), 970 SR_TRAP(OP_TLBI_ALLE1NXS, CGT_HCR_NV), 971 SR_TRAP(OP_TLBI_VALE2NXS, CGT_HCR_NV), 972 SR_TRAP(OP_TLBI_VMALLS12E1NXS, CGT_HCR_NV), 973 SR_TRAP(OP_TLBI_IPAS2E1IS, CGT_HCR_NV), 974 SR_TRAP(OP_TLBI_RIPAS2E1IS, CGT_HCR_NV), 975 SR_TRAP(OP_TLBI_IPAS2LE1IS, CGT_HCR_NV), 976 SR_TRAP(OP_TLBI_RIPAS2LE1IS, CGT_HCR_NV), 977 SR_TRAP(OP_TLBI_RVAE2IS, CGT_HCR_NV), 978 SR_TRAP(OP_TLBI_RVALE2IS, CGT_HCR_NV), 979 SR_TRAP(OP_TLBI_ALLE2IS, CGT_HCR_NV), 980 SR_TRAP(OP_TLBI_VAE2IS, CGT_HCR_NV), 981 SR_TRAP(OP_TLBI_ALLE1IS, CGT_HCR_NV), 982 SR_TRAP(OP_TLBI_VALE2IS, CGT_HCR_NV), 983 SR_TRAP(OP_TLBI_VMALLS12E1IS, CGT_HCR_NV), 984 SR_TRAP(OP_TLBI_IPAS2E1ISNXS, CGT_HCR_NV), 985 SR_TRAP(OP_TLBI_RIPAS2E1ISNXS, CGT_HCR_NV), 986 SR_TRAP(OP_TLBI_IPAS2LE1ISNXS, CGT_HCR_NV), 987 SR_TRAP(OP_TLBI_RIPAS2LE1ISNXS, CGT_HCR_NV), 988 SR_TRAP(OP_TLBI_RVAE2ISNXS, CGT_HCR_NV), 989 SR_TRAP(OP_TLBI_RVALE2ISNXS, CGT_HCR_NV), 990 SR_TRAP(OP_TLBI_ALLE2ISNXS, CGT_HCR_NV), 991 SR_TRAP(OP_TLBI_VAE2ISNXS, CGT_HCR_NV), 992 SR_TRAP(OP_TLBI_ALLE1ISNXS, CGT_HCR_NV), 993 SR_TRAP(OP_TLBI_VALE2ISNXS, CGT_HCR_NV), 994 SR_TRAP(OP_TLBI_VMALLS12E1ISNXS,CGT_HCR_NV), 995 SR_TRAP(OP_TLBI_ALLE2OS, CGT_HCR_NV), 996 SR_TRAP(OP_TLBI_VAE2OS, CGT_HCR_NV), 997 SR_TRAP(OP_TLBI_ALLE1OS, CGT_HCR_NV), 998 SR_TRAP(OP_TLBI_VALE2OS, CGT_HCR_NV), 999 SR_TRAP(OP_TLBI_VMALLS12E1OS, CGT_HCR_NV), 1000 SR_TRAP(OP_TLBI_IPAS2E1OS, CGT_HCR_NV), 1001 SR_TRAP(OP_TLBI_RIPAS2E1OS, CGT_HCR_NV), 1002 SR_TRAP(OP_TLBI_IPAS2LE1OS, CGT_HCR_NV), 1003 SR_TRAP(OP_TLBI_RIPAS2LE1OS, CGT_HCR_NV), 1004 SR_TRAP(OP_TLBI_RVAE2OS, CGT_HCR_NV), 1005 SR_TRAP(OP_TLBI_RVALE2OS, CGT_HCR_NV), 1006 SR_TRAP(OP_TLBI_ALLE2OSNXS, CGT_HCR_NV), 1007 SR_TRAP(OP_TLBI_VAE2OSNXS, CGT_HCR_NV), 1008 SR_TRAP(OP_TLBI_ALLE1OSNXS, CGT_HCR_NV), 1009 SR_TRAP(OP_TLBI_VALE2OSNXS, CGT_HCR_NV), 1010 SR_TRAP(OP_TLBI_VMALLS12E1OSNXS,CGT_HCR_NV), 1011 SR_TRAP(OP_TLBI_IPAS2E1OSNXS, CGT_HCR_NV), 1012 SR_TRAP(OP_TLBI_RIPAS2E1OSNXS, CGT_HCR_NV), 1013 SR_TRAP(OP_TLBI_IPAS2LE1OSNXS, CGT_HCR_NV), 1014 SR_TRAP(OP_TLBI_RIPAS2LE1OSNXS, CGT_HCR_NV), 1015 SR_TRAP(OP_TLBI_RVAE2OSNXS, CGT_HCR_NV), 1016 SR_TRAP(OP_TLBI_RVALE2OSNXS, CGT_HCR_NV), 1017 SR_TRAP(OP_CPP_RCTX, CGT_HCR_NV), 1018 SR_TRAP(OP_DVP_RCTX, CGT_HCR_NV), 1019 SR_TRAP(OP_CFP_RCTX, CGT_HCR_NV), 1020 SR_TRAP(SYS_SP_EL1, CGT_HCR_NV_nNV2), 1021 SR_TRAP(SYS_VBAR_EL1, CGT_HCR_NV1_nNV2), 1022 SR_TRAP(SYS_ELR_EL1, CGT_HCR_NV1_nNV2), 1023 SR_TRAP(SYS_SPSR_EL1, CGT_HCR_NV1_nNV2), 1024 SR_TRAP(SYS_SCXTNUM_EL1, CGT_HCR_NV1_nNV2_ENSCXT), 1025 SR_TRAP(SYS_SCXTNUM_EL0, CGT_HCR_ENSCXT), 1026 SR_TRAP(OP_AT_S1E1R, CGT_HCR_AT), 1027 SR_TRAP(OP_AT_S1E1W, CGT_HCR_AT), 1028 SR_TRAP(OP_AT_S1E0R, CGT_HCR_AT), 1029 SR_TRAP(OP_AT_S1E0W, CGT_HCR_AT), 1030 SR_TRAP(OP_AT_S1E1RP, CGT_HCR_AT), 1031 SR_TRAP(OP_AT_S1E1WP, CGT_HCR_AT), 1032 SR_TRAP(OP_AT_S1E1A, CGT_HCR_AT), 1033 SR_TRAP(SYS_ERXPFGF_EL1, CGT_HCR_nFIEN), 1034 SR_TRAP(SYS_ERXPFGCTL_EL1, CGT_HCR_nFIEN), 1035 SR_TRAP(SYS_ERXPFGCDN_EL1, CGT_HCR_nFIEN), 1036 SR_TRAP(SYS_PMCR_EL0, CGT_MDCR_TPM_TPMCR), 1037 SR_TRAP(SYS_PMCNTENSET_EL0, CGT_MDCR_TPM), 1038 SR_TRAP(SYS_PMCNTENCLR_EL0, CGT_MDCR_TPM), 1039 SR_TRAP(SYS_PMOVSSET_EL0, CGT_MDCR_TPM), 1040 SR_TRAP(SYS_PMOVSCLR_EL0, CGT_MDCR_TPM), 1041 SR_TRAP(SYS_PMCEID0_EL0, CGT_MDCR_TPM), 1042 SR_TRAP(SYS_PMCEID1_EL0, CGT_MDCR_TPM), 1043 SR_TRAP(SYS_PMXEVTYPER_EL0, CGT_MDCR_TPM_HPMN), 1044 SR_TRAP(SYS_PMSWINC_EL0, CGT_MDCR_TPM), 1045 SR_TRAP(SYS_PMSELR_EL0, CGT_MDCR_TPM), 1046 SR_TRAP(SYS_PMXEVCNTR_EL0, CGT_MDCR_TPM_HPMN), 1047 SR_TRAP(SYS_PMCCNTR_EL0, CGT_MDCR_TPM), 1048 SR_TRAP(SYS_PMUSERENR_EL0, CGT_MDCR_TPM), 1049 SR_TRAP(SYS_PMINTENSET_EL1, CGT_MDCR_TPM), 1050 SR_TRAP(SYS_PMINTENCLR_EL1, CGT_MDCR_TPM), 1051 SR_TRAP(SYS_PMMIR_EL1, CGT_MDCR_TPM), 1052 SR_TRAP(SYS_PMEVCNTRn_EL0(0), CGT_MDCR_TPM_HPMN), 1053 SR_TRAP(SYS_PMEVCNTRn_EL0(1), CGT_MDCR_TPM_HPMN), 1054 SR_TRAP(SYS_PMEVCNTRn_EL0(2), CGT_MDCR_TPM_HPMN), 1055 SR_TRAP(SYS_PMEVCNTRn_EL0(3), CGT_MDCR_TPM_HPMN), 1056 SR_TRAP(SYS_PMEVCNTRn_EL0(4), CGT_MDCR_TPM_HPMN), 1057 SR_TRAP(SYS_PMEVCNTRn_EL0(5), CGT_MDCR_TPM_HPMN), 1058 SR_TRAP(SYS_PMEVCNTRn_EL0(6), CGT_MDCR_TPM_HPMN), 1059 SR_TRAP(SYS_PMEVCNTRn_EL0(7), CGT_MDCR_TPM_HPMN), 1060 SR_TRAP(SYS_PMEVCNTRn_EL0(8), CGT_MDCR_TPM_HPMN), 1061 SR_TRAP(SYS_PMEVCNTRn_EL0(9), CGT_MDCR_TPM_HPMN), 1062 SR_TRAP(SYS_PMEVCNTRn_EL0(10), CGT_MDCR_TPM_HPMN), 1063 SR_TRAP(SYS_PMEVCNTRn_EL0(11), CGT_MDCR_TPM_HPMN), 1064 SR_TRAP(SYS_PMEVCNTRn_EL0(12), CGT_MDCR_TPM_HPMN), 1065 SR_TRAP(SYS_PMEVCNTRn_EL0(13), CGT_MDCR_TPM_HPMN), 1066 SR_TRAP(SYS_PMEVCNTRn_EL0(14), CGT_MDCR_TPM_HPMN), 1067 SR_TRAP(SYS_PMEVCNTRn_EL0(15), CGT_MDCR_TPM_HPMN), 1068 SR_TRAP(SYS_PMEVCNTRn_EL0(16), CGT_MDCR_TPM_HPMN), 1069 SR_TRAP(SYS_PMEVCNTRn_EL0(17), CGT_MDCR_TPM_HPMN), 1070 SR_TRAP(SYS_PMEVCNTRn_EL0(18), CGT_MDCR_TPM_HPMN), 1071 SR_TRAP(SYS_PMEVCNTRn_EL0(19), CGT_MDCR_TPM_HPMN), 1072 SR_TRAP(SYS_PMEVCNTRn_EL0(20), CGT_MDCR_TPM_HPMN), 1073 SR_TRAP(SYS_PMEVCNTRn_EL0(21), CGT_MDCR_TPM_HPMN), 1074 SR_TRAP(SYS_PMEVCNTRn_EL0(22), CGT_MDCR_TPM_HPMN), 1075 SR_TRAP(SYS_PMEVCNTRn_EL0(23), CGT_MDCR_TPM_HPMN), 1076 SR_TRAP(SYS_PMEVCNTRn_EL0(24), CGT_MDCR_TPM_HPMN), 1077 SR_TRAP(SYS_PMEVCNTRn_EL0(25), CGT_MDCR_TPM_HPMN), 1078 SR_TRAP(SYS_PMEVCNTRn_EL0(26), CGT_MDCR_TPM_HPMN), 1079 SR_TRAP(SYS_PMEVCNTRn_EL0(27), CGT_MDCR_TPM_HPMN), 1080 SR_TRAP(SYS_PMEVCNTRn_EL0(28), CGT_MDCR_TPM_HPMN), 1081 SR_TRAP(SYS_PMEVCNTRn_EL0(29), CGT_MDCR_TPM_HPMN), 1082 SR_TRAP(SYS_PMEVCNTRn_EL0(30), CGT_MDCR_TPM_HPMN), 1083 SR_TRAP(SYS_PMEVTYPERn_EL0(0), CGT_MDCR_TPM_HPMN), 1084 SR_TRAP(SYS_PMEVTYPERn_EL0(1), CGT_MDCR_TPM_HPMN), 1085 SR_TRAP(SYS_PMEVTYPERn_EL0(2), CGT_MDCR_TPM_HPMN), 1086 SR_TRAP(SYS_PMEVTYPERn_EL0(3), CGT_MDCR_TPM_HPMN), 1087 SR_TRAP(SYS_PMEVTYPERn_EL0(4), CGT_MDCR_TPM_HPMN), 1088 SR_TRAP(SYS_PMEVTYPERn_EL0(5), CGT_MDCR_TPM_HPMN), 1089 SR_TRAP(SYS_PMEVTYPERn_EL0(6), CGT_MDCR_TPM_HPMN), 1090 SR_TRAP(SYS_PMEVTYPERn_EL0(7), CGT_MDCR_TPM_HPMN), 1091 SR_TRAP(SYS_PMEVTYPERn_EL0(8), CGT_MDCR_TPM_HPMN), 1092 SR_TRAP(SYS_PMEVTYPERn_EL0(9), CGT_MDCR_TPM_HPMN), 1093 SR_TRAP(SYS_PMEVTYPERn_EL0(10), CGT_MDCR_TPM_HPMN), 1094 SR_TRAP(SYS_PMEVTYPERn_EL0(11), CGT_MDCR_TPM_HPMN), 1095 SR_TRAP(SYS_PMEVTYPERn_EL0(12), CGT_MDCR_TPM_HPMN), 1096 SR_TRAP(SYS_PMEVTYPERn_EL0(13), CGT_MDCR_TPM_HPMN), 1097 SR_TRAP(SYS_PMEVTYPERn_EL0(14), CGT_MDCR_TPM_HPMN), 1098 SR_TRAP(SYS_PMEVTYPERn_EL0(15), CGT_MDCR_TPM_HPMN), 1099 SR_TRAP(SYS_PMEVTYPERn_EL0(16), CGT_MDCR_TPM_HPMN), 1100 SR_TRAP(SYS_PMEVTYPERn_EL0(17), CGT_MDCR_TPM_HPMN), 1101 SR_TRAP(SYS_PMEVTYPERn_EL0(18), CGT_MDCR_TPM_HPMN), 1102 SR_TRAP(SYS_PMEVTYPERn_EL0(19), CGT_MDCR_TPM_HPMN), 1103 SR_TRAP(SYS_PMEVTYPERn_EL0(20), CGT_MDCR_TPM_HPMN), 1104 SR_TRAP(SYS_PMEVTYPERn_EL0(21), CGT_MDCR_TPM_HPMN), 1105 SR_TRAP(SYS_PMEVTYPERn_EL0(22), CGT_MDCR_TPM_HPMN), 1106 SR_TRAP(SYS_PMEVTYPERn_EL0(23), CGT_MDCR_TPM_HPMN), 1107 SR_TRAP(SYS_PMEVTYPERn_EL0(24), CGT_MDCR_TPM_HPMN), 1108 SR_TRAP(SYS_PMEVTYPERn_EL0(25), CGT_MDCR_TPM_HPMN), 1109 SR_TRAP(SYS_PMEVTYPERn_EL0(26), CGT_MDCR_TPM_HPMN), 1110 SR_TRAP(SYS_PMEVTYPERn_EL0(27), CGT_MDCR_TPM_HPMN), 1111 SR_TRAP(SYS_PMEVTYPERn_EL0(28), CGT_MDCR_TPM_HPMN), 1112 SR_TRAP(SYS_PMEVTYPERn_EL0(29), CGT_MDCR_TPM_HPMN), 1113 SR_TRAP(SYS_PMEVTYPERn_EL0(30), CGT_MDCR_TPM_HPMN), 1114 SR_TRAP(SYS_PMCCFILTR_EL0, CGT_MDCR_TPM), 1115 SR_TRAP(SYS_MDCCSR_EL0, CGT_MDCR_TDCC_TDE_TDA), 1116 SR_TRAP(SYS_MDCCINT_EL1, CGT_MDCR_TDCC_TDE_TDA), 1117 SR_TRAP(SYS_OSDTRRX_EL1, CGT_MDCR_TDCC_TDE_TDA), 1118 SR_TRAP(SYS_OSDTRTX_EL1, CGT_MDCR_TDCC_TDE_TDA), 1119 SR_TRAP(SYS_DBGDTR_EL0, CGT_MDCR_TDCC_TDE_TDA), 1120 /* 1121 * Also covers DBGDTRRX_EL0, which has the same encoding as 1122 * SYS_DBGDTRTX_EL0... 1123 */ 1124 SR_TRAP(SYS_DBGDTRTX_EL0, CGT_MDCR_TDCC_TDE_TDA), 1125 SR_TRAP(SYS_MDSCR_EL1, CGT_MDCR_TDE_TDA), 1126 SR_TRAP(SYS_OSECCR_EL1, CGT_MDCR_TDE_TDA), 1127 SR_TRAP(SYS_DBGBVRn_EL1(0), CGT_MDCR_TDE_TDA), 1128 SR_TRAP(SYS_DBGBVRn_EL1(1), CGT_MDCR_TDE_TDA), 1129 SR_TRAP(SYS_DBGBVRn_EL1(2), CGT_MDCR_TDE_TDA), 1130 SR_TRAP(SYS_DBGBVRn_EL1(3), CGT_MDCR_TDE_TDA), 1131 SR_TRAP(SYS_DBGBVRn_EL1(4), CGT_MDCR_TDE_TDA), 1132 SR_TRAP(SYS_DBGBVRn_EL1(5), CGT_MDCR_TDE_TDA), 1133 SR_TRAP(SYS_DBGBVRn_EL1(6), CGT_MDCR_TDE_TDA), 1134 SR_TRAP(SYS_DBGBVRn_EL1(7), CGT_MDCR_TDE_TDA), 1135 SR_TRAP(SYS_DBGBVRn_EL1(8), CGT_MDCR_TDE_TDA), 1136 SR_TRAP(SYS_DBGBVRn_EL1(9), CGT_MDCR_TDE_TDA), 1137 SR_TRAP(SYS_DBGBVRn_EL1(10), CGT_MDCR_TDE_TDA), 1138 SR_TRAP(SYS_DBGBVRn_EL1(11), CGT_MDCR_TDE_TDA), 1139 SR_TRAP(SYS_DBGBVRn_EL1(12), CGT_MDCR_TDE_TDA), 1140 SR_TRAP(SYS_DBGBVRn_EL1(13), CGT_MDCR_TDE_TDA), 1141 SR_TRAP(SYS_DBGBVRn_EL1(14), CGT_MDCR_TDE_TDA), 1142 SR_TRAP(SYS_DBGBVRn_EL1(15), CGT_MDCR_TDE_TDA), 1143 SR_TRAP(SYS_DBGBCRn_EL1(0), CGT_MDCR_TDE_TDA), 1144 SR_TRAP(SYS_DBGBCRn_EL1(1), CGT_MDCR_TDE_TDA), 1145 SR_TRAP(SYS_DBGBCRn_EL1(2), CGT_MDCR_TDE_TDA), 1146 SR_TRAP(SYS_DBGBCRn_EL1(3), CGT_MDCR_TDE_TDA), 1147 SR_TRAP(SYS_DBGBCRn_EL1(4), CGT_MDCR_TDE_TDA), 1148 SR_TRAP(SYS_DBGBCRn_EL1(5), CGT_MDCR_TDE_TDA), 1149 SR_TRAP(SYS_DBGBCRn_EL1(6), CGT_MDCR_TDE_TDA), 1150 SR_TRAP(SYS_DBGBCRn_EL1(7), CGT_MDCR_TDE_TDA), 1151 SR_TRAP(SYS_DBGBCRn_EL1(8), CGT_MDCR_TDE_TDA), 1152 SR_TRAP(SYS_DBGBCRn_EL1(9), CGT_MDCR_TDE_TDA), 1153 SR_TRAP(SYS_DBGBCRn_EL1(10), CGT_MDCR_TDE_TDA), 1154 SR_TRAP(SYS_DBGBCRn_EL1(11), CGT_MDCR_TDE_TDA), 1155 SR_TRAP(SYS_DBGBCRn_EL1(12), CGT_MDCR_TDE_TDA), 1156 SR_TRAP(SYS_DBGBCRn_EL1(13), CGT_MDCR_TDE_TDA), 1157 SR_TRAP(SYS_DBGBCRn_EL1(14), CGT_MDCR_TDE_TDA), 1158 SR_TRAP(SYS_DBGBCRn_EL1(15), CGT_MDCR_TDE_TDA), 1159 SR_TRAP(SYS_DBGWVRn_EL1(0), CGT_MDCR_TDE_TDA), 1160 SR_TRAP(SYS_DBGWVRn_EL1(1), CGT_MDCR_TDE_TDA), 1161 SR_TRAP(SYS_DBGWVRn_EL1(2), CGT_MDCR_TDE_TDA), 1162 SR_TRAP(SYS_DBGWVRn_EL1(3), CGT_MDCR_TDE_TDA), 1163 SR_TRAP(SYS_DBGWVRn_EL1(4), CGT_MDCR_TDE_TDA), 1164 SR_TRAP(SYS_DBGWVRn_EL1(5), CGT_MDCR_TDE_TDA), 1165 SR_TRAP(SYS_DBGWVRn_EL1(6), CGT_MDCR_TDE_TDA), 1166 SR_TRAP(SYS_DBGWVRn_EL1(7), CGT_MDCR_TDE_TDA), 1167 SR_TRAP(SYS_DBGWVRn_EL1(8), CGT_MDCR_TDE_TDA), 1168 SR_TRAP(SYS_DBGWVRn_EL1(9), CGT_MDCR_TDE_TDA), 1169 SR_TRAP(SYS_DBGWVRn_EL1(10), CGT_MDCR_TDE_TDA), 1170 SR_TRAP(SYS_DBGWVRn_EL1(11), CGT_MDCR_TDE_TDA), 1171 SR_TRAP(SYS_DBGWVRn_EL1(12), CGT_MDCR_TDE_TDA), 1172 SR_TRAP(SYS_DBGWVRn_EL1(13), CGT_MDCR_TDE_TDA), 1173 SR_TRAP(SYS_DBGWVRn_EL1(14), CGT_MDCR_TDE_TDA), 1174 SR_TRAP(SYS_DBGWVRn_EL1(15), CGT_MDCR_TDE_TDA), 1175 SR_TRAP(SYS_DBGWCRn_EL1(0), CGT_MDCR_TDE_TDA), 1176 SR_TRAP(SYS_DBGWCRn_EL1(1), CGT_MDCR_TDE_TDA), 1177 SR_TRAP(SYS_DBGWCRn_EL1(2), CGT_MDCR_TDE_TDA), 1178 SR_TRAP(SYS_DBGWCRn_EL1(3), CGT_MDCR_TDE_TDA), 1179 SR_TRAP(SYS_DBGWCRn_EL1(4), CGT_MDCR_TDE_TDA), 1180 SR_TRAP(SYS_DBGWCRn_EL1(5), CGT_MDCR_TDE_TDA), 1181 SR_TRAP(SYS_DBGWCRn_EL1(6), CGT_MDCR_TDE_TDA), 1182 SR_TRAP(SYS_DBGWCRn_EL1(7), CGT_MDCR_TDE_TDA), 1183 SR_TRAP(SYS_DBGWCRn_EL1(8), CGT_MDCR_TDE_TDA), 1184 SR_TRAP(SYS_DBGWCRn_EL1(9), CGT_MDCR_TDE_TDA), 1185 SR_TRAP(SYS_DBGWCRn_EL1(10), CGT_MDCR_TDE_TDA), 1186 SR_TRAP(SYS_DBGWCRn_EL1(11), CGT_MDCR_TDE_TDA), 1187 SR_TRAP(SYS_DBGWCRn_EL1(12), CGT_MDCR_TDE_TDA), 1188 SR_TRAP(SYS_DBGWCRn_EL1(13), CGT_MDCR_TDE_TDA), 1189 SR_TRAP(SYS_DBGWCRn_EL1(14), CGT_MDCR_TDE_TDA), 1190 SR_TRAP(SYS_DBGWCRn_EL1(15), CGT_MDCR_TDE_TDA), 1191 SR_TRAP(SYS_DBGCLAIMSET_EL1, CGT_MDCR_TDE_TDA), 1192 SR_TRAP(SYS_DBGCLAIMCLR_EL1, CGT_MDCR_TDE_TDA), 1193 SR_TRAP(SYS_DBGAUTHSTATUS_EL1, CGT_MDCR_TDE_TDA), 1194 SR_TRAP(SYS_OSLAR_EL1, CGT_MDCR_TDE_TDOSA), 1195 SR_TRAP(SYS_OSLSR_EL1, CGT_MDCR_TDE_TDOSA), 1196 SR_TRAP(SYS_OSDLR_EL1, CGT_MDCR_TDE_TDOSA), 1197 SR_TRAP(SYS_DBGPRCR_EL1, CGT_MDCR_TDE_TDOSA), 1198 SR_TRAP(SYS_MDRAR_EL1, CGT_MDCR_TDE_TDRA), 1199 SR_TRAP(SYS_PMBLIMITR_EL1, CGT_MDCR_E2PB), 1200 SR_TRAP(SYS_PMBPTR_EL1, CGT_MDCR_E2PB), 1201 SR_TRAP(SYS_PMBSR_EL1, CGT_MDCR_E2PB), 1202 SR_TRAP(SYS_PMSCR_EL1, CGT_MDCR_TPMS), 1203 SR_TRAP(SYS_PMSEVFR_EL1, CGT_MDCR_TPMS), 1204 SR_TRAP(SYS_PMSFCR_EL1, CGT_MDCR_TPMS), 1205 SR_TRAP(SYS_PMSICR_EL1, CGT_MDCR_TPMS), 1206 SR_TRAP(SYS_PMSIDR_EL1, CGT_MDCR_TPMS), 1207 SR_TRAP(SYS_PMSIRR_EL1, CGT_MDCR_TPMS), 1208 SR_TRAP(SYS_PMSLATFR_EL1, CGT_MDCR_TPMS), 1209 SR_TRAP(SYS_PMSNEVFR_EL1, CGT_MDCR_TPMS), 1210 SR_TRAP(SYS_PMSDSFR_EL1, CGT_MDCR_TPMS), 1211 SR_TRAP(SYS_TRFCR_EL1, CGT_MDCR_TTRF), 1212 SR_TRAP(SYS_TRBBASER_EL1, CGT_MDCR_E2TB), 1213 SR_TRAP(SYS_TRBLIMITR_EL1, CGT_MDCR_E2TB), 1214 SR_TRAP(SYS_TRBMAR_EL1, CGT_MDCR_E2TB), 1215 SR_TRAP(SYS_TRBPTR_EL1, CGT_MDCR_E2TB), 1216 SR_TRAP(SYS_TRBSR_EL1, CGT_MDCR_E2TB), 1217 SR_TRAP(SYS_TRBTRG_EL1, CGT_MDCR_E2TB), 1218 SR_TRAP(SYS_CPACR_EL1, CGT_CPTR_TCPAC), 1219 SR_TRAP(SYS_AMUSERENR_EL0, CGT_CPTR_TAM), 1220 SR_TRAP(SYS_AMCFGR_EL0, CGT_CPTR_TAM), 1221 SR_TRAP(SYS_AMCGCR_EL0, CGT_CPTR_TAM), 1222 SR_TRAP(SYS_AMCNTENCLR0_EL0, CGT_CPTR_TAM), 1223 SR_TRAP(SYS_AMCNTENCLR1_EL0, CGT_CPTR_TAM), 1224 SR_TRAP(SYS_AMCNTENSET0_EL0, CGT_CPTR_TAM), 1225 SR_TRAP(SYS_AMCNTENSET1_EL0, CGT_CPTR_TAM), 1226 SR_TRAP(SYS_AMCR_EL0, CGT_CPTR_TAM), 1227 SR_TRAP(SYS_AMEVCNTR0_EL0(0), CGT_CPTR_TAM), 1228 SR_TRAP(SYS_AMEVCNTR0_EL0(1), CGT_CPTR_TAM), 1229 SR_TRAP(SYS_AMEVCNTR0_EL0(2), CGT_CPTR_TAM), 1230 SR_TRAP(SYS_AMEVCNTR0_EL0(3), CGT_CPTR_TAM), 1231 SR_TRAP(SYS_AMEVCNTR1_EL0(0), CGT_CPTR_TAM), 1232 SR_TRAP(SYS_AMEVCNTR1_EL0(1), CGT_CPTR_TAM), 1233 SR_TRAP(SYS_AMEVCNTR1_EL0(2), CGT_CPTR_TAM), 1234 SR_TRAP(SYS_AMEVCNTR1_EL0(3), CGT_CPTR_TAM), 1235 SR_TRAP(SYS_AMEVCNTR1_EL0(4), CGT_CPTR_TAM), 1236 SR_TRAP(SYS_AMEVCNTR1_EL0(5), CGT_CPTR_TAM), 1237 SR_TRAP(SYS_AMEVCNTR1_EL0(6), CGT_CPTR_TAM), 1238 SR_TRAP(SYS_AMEVCNTR1_EL0(7), CGT_CPTR_TAM), 1239 SR_TRAP(SYS_AMEVCNTR1_EL0(8), CGT_CPTR_TAM), 1240 SR_TRAP(SYS_AMEVCNTR1_EL0(9), CGT_CPTR_TAM), 1241 SR_TRAP(SYS_AMEVCNTR1_EL0(10), CGT_CPTR_TAM), 1242 SR_TRAP(SYS_AMEVCNTR1_EL0(11), CGT_CPTR_TAM), 1243 SR_TRAP(SYS_AMEVCNTR1_EL0(12), CGT_CPTR_TAM), 1244 SR_TRAP(SYS_AMEVCNTR1_EL0(13), CGT_CPTR_TAM), 1245 SR_TRAP(SYS_AMEVCNTR1_EL0(14), CGT_CPTR_TAM), 1246 SR_TRAP(SYS_AMEVCNTR1_EL0(15), CGT_CPTR_TAM), 1247 SR_TRAP(SYS_AMEVTYPER0_EL0(0), CGT_CPTR_TAM), 1248 SR_TRAP(SYS_AMEVTYPER0_EL0(1), CGT_CPTR_TAM), 1249 SR_TRAP(SYS_AMEVTYPER0_EL0(2), CGT_CPTR_TAM), 1250 SR_TRAP(SYS_AMEVTYPER0_EL0(3), CGT_CPTR_TAM), 1251 SR_TRAP(SYS_AMEVTYPER1_EL0(0), CGT_CPTR_TAM), 1252 SR_TRAP(SYS_AMEVTYPER1_EL0(1), CGT_CPTR_TAM), 1253 SR_TRAP(SYS_AMEVTYPER1_EL0(2), CGT_CPTR_TAM), 1254 SR_TRAP(SYS_AMEVTYPER1_EL0(3), CGT_CPTR_TAM), 1255 SR_TRAP(SYS_AMEVTYPER1_EL0(4), CGT_CPTR_TAM), 1256 SR_TRAP(SYS_AMEVTYPER1_EL0(5), CGT_CPTR_TAM), 1257 SR_TRAP(SYS_AMEVTYPER1_EL0(6), CGT_CPTR_TAM), 1258 SR_TRAP(SYS_AMEVTYPER1_EL0(7), CGT_CPTR_TAM), 1259 SR_TRAP(SYS_AMEVTYPER1_EL0(8), CGT_CPTR_TAM), 1260 SR_TRAP(SYS_AMEVTYPER1_EL0(9), CGT_CPTR_TAM), 1261 SR_TRAP(SYS_AMEVTYPER1_EL0(10), CGT_CPTR_TAM), 1262 SR_TRAP(SYS_AMEVTYPER1_EL0(11), CGT_CPTR_TAM), 1263 SR_TRAP(SYS_AMEVTYPER1_EL0(12), CGT_CPTR_TAM), 1264 SR_TRAP(SYS_AMEVTYPER1_EL0(13), CGT_CPTR_TAM), 1265 SR_TRAP(SYS_AMEVTYPER1_EL0(14), CGT_CPTR_TAM), 1266 SR_TRAP(SYS_AMEVTYPER1_EL0(15), CGT_CPTR_TAM), 1267 /* op0=2, op1=1, and CRn<0b1000 */ 1268 SR_RANGE_TRAP(sys_reg(2, 1, 0, 0, 0), 1269 sys_reg(2, 1, 7, 15, 7), CGT_CPTR_TTA), 1270 SR_TRAP(SYS_CNTP_TVAL_EL0, CGT_CNTHCTL_EL1PTEN), 1271 SR_TRAP(SYS_CNTP_CVAL_EL0, CGT_CNTHCTL_EL1PTEN), 1272 SR_TRAP(SYS_CNTP_CTL_EL0, CGT_CNTHCTL_EL1PTEN), 1273 SR_TRAP(SYS_CNTPCT_EL0, CGT_CNTHCTL_EL1PCTEN), 1274 SR_TRAP(SYS_CNTPCTSS_EL0, CGT_CNTHCTL_EL1PCTEN), 1275 SR_TRAP(SYS_CNTV_TVAL_EL0, CGT_CNTHCTL_EL1TVT), 1276 SR_TRAP(SYS_CNTV_CVAL_EL0, CGT_CNTHCTL_EL1TVT), 1277 SR_TRAP(SYS_CNTV_CTL_EL0, CGT_CNTHCTL_EL1TVT), 1278 SR_TRAP(SYS_CNTVCT_EL0, CGT_CNTHCTL_EL1TVCT), 1279 SR_TRAP(SYS_CNTVCTSS_EL0, CGT_CNTHCTL_EL1TVCT), 1280 SR_TRAP(SYS_FPMR, CGT_HCRX_EnFPM), 1281 /* 1282 * IMPDEF choice: 1283 * We treat ICC_SRE_EL2.{SRE,Enable) and ICV_SRE_EL1.SRE as 1284 * RAO/WI. We therefore never consider ICC_SRE_EL2.Enable for 1285 * ICC_SRE_EL1 access, and always handle it locally. 1286 */ 1287 SR_TRAP(SYS_ICC_AP0R0_EL1, CGT_ICH_HCR_TALL0), 1288 SR_TRAP(SYS_ICC_AP0R1_EL1, CGT_ICH_HCR_TALL0), 1289 SR_TRAP(SYS_ICC_AP0R2_EL1, CGT_ICH_HCR_TALL0), 1290 SR_TRAP(SYS_ICC_AP0R3_EL1, CGT_ICH_HCR_TALL0), 1291 SR_TRAP(SYS_ICC_AP1R0_EL1, CGT_ICH_HCR_TALL1), 1292 SR_TRAP(SYS_ICC_AP1R1_EL1, CGT_ICH_HCR_TALL1), 1293 SR_TRAP(SYS_ICC_AP1R2_EL1, CGT_ICH_HCR_TALL1), 1294 SR_TRAP(SYS_ICC_AP1R3_EL1, CGT_ICH_HCR_TALL1), 1295 SR_TRAP(SYS_ICC_BPR0_EL1, CGT_ICH_HCR_TALL0), 1296 SR_TRAP(SYS_ICC_BPR1_EL1, CGT_ICH_HCR_TALL1), 1297 SR_TRAP(SYS_ICC_CTLR_EL1, CGT_ICH_HCR_TC), 1298 SR_TRAP(SYS_ICC_DIR_EL1, CGT_ICH_HCR_TC_TDIR), 1299 SR_TRAP(SYS_ICC_EOIR0_EL1, CGT_ICH_HCR_TALL0), 1300 SR_TRAP(SYS_ICC_EOIR1_EL1, CGT_ICH_HCR_TALL1), 1301 SR_TRAP(SYS_ICC_HPPIR0_EL1, CGT_ICH_HCR_TALL0), 1302 SR_TRAP(SYS_ICC_HPPIR1_EL1, CGT_ICH_HCR_TALL1), 1303 SR_TRAP(SYS_ICC_IAR0_EL1, CGT_ICH_HCR_TALL0), 1304 SR_TRAP(SYS_ICC_IAR1_EL1, CGT_ICH_HCR_TALL1), 1305 SR_TRAP(SYS_ICC_IGRPEN0_EL1, CGT_ICH_HCR_TALL0), 1306 SR_TRAP(SYS_ICC_IGRPEN1_EL1, CGT_ICH_HCR_TALL1), 1307 SR_TRAP(SYS_ICC_PMR_EL1, CGT_ICH_HCR_TC), 1308 SR_TRAP(SYS_ICC_RPR_EL1, CGT_ICH_HCR_TC), 1309 }; 1310 1311 static DEFINE_XARRAY(sr_forward_xa); 1312 1313 enum fg_filter_id { 1314 __NO_FGF__, 1315 HCRX_FGTnXS, 1316 1317 /* Must be last */ 1318 __NR_FG_FILTER_IDS__ 1319 }; 1320 1321 #define __FGT(g, b, p, f) \ 1322 { \ 1323 .fgt = g ## _GROUP, \ 1324 .bit = g ## _EL2_ ## b ## _SHIFT, \ 1325 .pol = p, \ 1326 .fgf = f, \ 1327 } 1328 1329 #define FGT(g, b, p) __FGT(g, b, p, __NO_FGF__) 1330 1331 /* 1332 * See the warning next to SR_RANGE_TRAP(), and apply the same 1333 * level of caution. 1334 */ 1335 #define SR_FGF_RANGE(sr, e, g, b, p, f) \ 1336 { \ 1337 .encoding = sr, \ 1338 .end = e, \ 1339 .tc = __FGT(g, b, p, f), \ 1340 .line = __LINE__, \ 1341 } 1342 1343 #define SR_FGF(sr, g, b, p, f) SR_FGF_RANGE(sr, sr, g, b, p, f) 1344 #define SR_FGT(sr, g, b, p) SR_FGF_RANGE(sr, sr, g, b, p, __NO_FGF__) 1345 #define SR_FGT_RANGE(sr, end, g, b, p) \ 1346 SR_FGF_RANGE(sr, end, g, b, p, __NO_FGF__) 1347 1348 static const struct encoding_to_trap_config encoding_to_fgt[] __initconst = { 1349 /* HFGRTR_EL2, HFGWTR_EL2 */ 1350 SR_FGT(SYS_AMAIR2_EL1, HFGRTR, nAMAIR2_EL1, 0), 1351 SR_FGT(SYS_MAIR2_EL1, HFGRTR, nMAIR2_EL1, 0), 1352 SR_FGT(SYS_S2POR_EL1, HFGRTR, nS2POR_EL1, 0), 1353 SR_FGT(SYS_POR_EL1, HFGRTR, nPOR_EL1, 0), 1354 SR_FGT(SYS_POR_EL0, HFGRTR, nPOR_EL0, 0), 1355 SR_FGT(SYS_PIR_EL1, HFGRTR, nPIR_EL1, 0), 1356 SR_FGT(SYS_PIRE0_EL1, HFGRTR, nPIRE0_EL1, 0), 1357 SR_FGT(SYS_RCWMASK_EL1, HFGRTR, nRCWMASK_EL1, 0), 1358 SR_FGT(SYS_TPIDR2_EL0, HFGRTR, nTPIDR2_EL0, 0), 1359 SR_FGT(SYS_SMPRI_EL1, HFGRTR, nSMPRI_EL1, 0), 1360 SR_FGT(SYS_GCSCR_EL1, HFGRTR, nGCS_EL1, 0), 1361 SR_FGT(SYS_GCSPR_EL1, HFGRTR, nGCS_EL1, 0), 1362 SR_FGT(SYS_GCSCRE0_EL1, HFGRTR, nGCS_EL0, 0), 1363 SR_FGT(SYS_GCSPR_EL0, HFGRTR, nGCS_EL0, 0), 1364 SR_FGT(SYS_ACCDATA_EL1, HFGRTR, nACCDATA_EL1, 0), 1365 SR_FGT(SYS_ERXADDR_EL1, HFGRTR, ERXADDR_EL1, 1), 1366 SR_FGT(SYS_ERXPFGCDN_EL1, HFGRTR, ERXPFGCDN_EL1, 1), 1367 SR_FGT(SYS_ERXPFGCTL_EL1, HFGRTR, ERXPFGCTL_EL1, 1), 1368 SR_FGT(SYS_ERXPFGF_EL1, HFGRTR, ERXPFGF_EL1, 1), 1369 SR_FGT(SYS_ERXMISC0_EL1, HFGRTR, ERXMISCn_EL1, 1), 1370 SR_FGT(SYS_ERXMISC1_EL1, HFGRTR, ERXMISCn_EL1, 1), 1371 SR_FGT(SYS_ERXMISC2_EL1, HFGRTR, ERXMISCn_EL1, 1), 1372 SR_FGT(SYS_ERXMISC3_EL1, HFGRTR, ERXMISCn_EL1, 1), 1373 SR_FGT(SYS_ERXSTATUS_EL1, HFGRTR, ERXSTATUS_EL1, 1), 1374 SR_FGT(SYS_ERXCTLR_EL1, HFGRTR, ERXCTLR_EL1, 1), 1375 SR_FGT(SYS_ERXFR_EL1, HFGRTR, ERXFR_EL1, 1), 1376 SR_FGT(SYS_ERRSELR_EL1, HFGRTR, ERRSELR_EL1, 1), 1377 SR_FGT(SYS_ERRIDR_EL1, HFGRTR, ERRIDR_EL1, 1), 1378 SR_FGT(SYS_ICC_IGRPEN0_EL1, HFGRTR, ICC_IGRPENn_EL1, 1), 1379 SR_FGT(SYS_ICC_IGRPEN1_EL1, HFGRTR, ICC_IGRPENn_EL1, 1), 1380 SR_FGT(SYS_VBAR_EL1, HFGRTR, VBAR_EL1, 1), 1381 SR_FGT(SYS_TTBR1_EL1, HFGRTR, TTBR1_EL1, 1), 1382 SR_FGT(SYS_TTBR0_EL1, HFGRTR, TTBR0_EL1, 1), 1383 SR_FGT(SYS_TPIDR_EL0, HFGRTR, TPIDR_EL0, 1), 1384 SR_FGT(SYS_TPIDRRO_EL0, HFGRTR, TPIDRRO_EL0, 1), 1385 SR_FGT(SYS_TPIDR_EL1, HFGRTR, TPIDR_EL1, 1), 1386 SR_FGT(SYS_TCR_EL1, HFGRTR, TCR_EL1, 1), 1387 SR_FGT(SYS_TCR2_EL1, HFGRTR, TCR_EL1, 1), 1388 SR_FGT(SYS_SCXTNUM_EL0, HFGRTR, SCXTNUM_EL0, 1), 1389 SR_FGT(SYS_SCXTNUM_EL1, HFGRTR, SCXTNUM_EL1, 1), 1390 SR_FGT(SYS_SCTLR_EL1, HFGRTR, SCTLR_EL1, 1), 1391 SR_FGT(SYS_SCTLR2_EL1, HFGRTR, SCTLR_EL1, 1), 1392 SR_FGT(SYS_REVIDR_EL1, HFGRTR, REVIDR_EL1, 1), 1393 SR_FGT(SYS_PAR_EL1, HFGRTR, PAR_EL1, 1), 1394 SR_FGT(SYS_MPIDR_EL1, HFGRTR, MPIDR_EL1, 1), 1395 SR_FGT(SYS_MIDR_EL1, HFGRTR, MIDR_EL1, 1), 1396 SR_FGT(SYS_MAIR_EL1, HFGRTR, MAIR_EL1, 1), 1397 SR_FGT(SYS_LORSA_EL1, HFGRTR, LORSA_EL1, 1), 1398 SR_FGT(SYS_LORN_EL1, HFGRTR, LORN_EL1, 1), 1399 SR_FGT(SYS_LORID_EL1, HFGRTR, LORID_EL1, 1), 1400 SR_FGT(SYS_LOREA_EL1, HFGRTR, LOREA_EL1, 1), 1401 SR_FGT(SYS_LORC_EL1, HFGRTR, LORC_EL1, 1), 1402 SR_FGT(SYS_ISR_EL1, HFGRTR, ISR_EL1, 1), 1403 SR_FGT(SYS_FAR_EL1, HFGRTR, FAR_EL1, 1), 1404 SR_FGT(SYS_ESR_EL1, HFGRTR, ESR_EL1, 1), 1405 SR_FGT(SYS_DCZID_EL0, HFGRTR, DCZID_EL0, 1), 1406 SR_FGT(SYS_CTR_EL0, HFGRTR, CTR_EL0, 1), 1407 SR_FGT(SYS_CSSELR_EL1, HFGRTR, CSSELR_EL1, 1), 1408 SR_FGT(SYS_CPACR_EL1, HFGRTR, CPACR_EL1, 1), 1409 SR_FGT(SYS_CONTEXTIDR_EL1, HFGRTR, CONTEXTIDR_EL1, 1), 1410 SR_FGT(SYS_CLIDR_EL1, HFGRTR, CLIDR_EL1, 1), 1411 SR_FGT(SYS_CCSIDR_EL1, HFGRTR, CCSIDR_EL1, 1), 1412 SR_FGT(SYS_APIBKEYLO_EL1, HFGRTR, APIBKey, 1), 1413 SR_FGT(SYS_APIBKEYHI_EL1, HFGRTR, APIBKey, 1), 1414 SR_FGT(SYS_APIAKEYLO_EL1, HFGRTR, APIAKey, 1), 1415 SR_FGT(SYS_APIAKEYHI_EL1, HFGRTR, APIAKey, 1), 1416 SR_FGT(SYS_APGAKEYLO_EL1, HFGRTR, APGAKey, 1), 1417 SR_FGT(SYS_APGAKEYHI_EL1, HFGRTR, APGAKey, 1), 1418 SR_FGT(SYS_APDBKEYLO_EL1, HFGRTR, APDBKey, 1), 1419 SR_FGT(SYS_APDBKEYHI_EL1, HFGRTR, APDBKey, 1), 1420 SR_FGT(SYS_APDAKEYLO_EL1, HFGRTR, APDAKey, 1), 1421 SR_FGT(SYS_APDAKEYHI_EL1, HFGRTR, APDAKey, 1), 1422 SR_FGT(SYS_AMAIR_EL1, HFGRTR, AMAIR_EL1, 1), 1423 SR_FGT(SYS_AIDR_EL1, HFGRTR, AIDR_EL1, 1), 1424 SR_FGT(SYS_AFSR1_EL1, HFGRTR, AFSR1_EL1, 1), 1425 SR_FGT(SYS_AFSR0_EL1, HFGRTR, AFSR0_EL1, 1), 1426 1427 /* HFGRTR2_EL2, HFGWTR2_EL2 */ 1428 SR_FGT(SYS_ACTLRALIAS_EL1, HFGRTR2, nACTLRALIAS_EL1, 0), 1429 SR_FGT(SYS_ACTLRMASK_EL1, HFGRTR2, nACTLRMASK_EL1, 0), 1430 SR_FGT(SYS_CPACRALIAS_EL1, HFGRTR2, nCPACRALIAS_EL1, 0), 1431 SR_FGT(SYS_CPACRMASK_EL1, HFGRTR2, nCPACRMASK_EL1, 0), 1432 SR_FGT(SYS_PFAR_EL1, HFGRTR2, nPFAR_EL1, 0), 1433 SR_FGT(SYS_RCWSMASK_EL1, HFGRTR2, nRCWSMASK_EL1, 0), 1434 SR_FGT(SYS_SCTLR2ALIAS_EL1, HFGRTR2, nSCTLRALIAS2_EL1, 0), 1435 SR_FGT(SYS_SCTLR2MASK_EL1, HFGRTR2, nSCTLR2MASK_EL1, 0), 1436 SR_FGT(SYS_SCTLRALIAS_EL1, HFGRTR2, nSCTLRALIAS_EL1, 0), 1437 SR_FGT(SYS_SCTLRMASK_EL1, HFGRTR2, nSCTLRMASK_EL1, 0), 1438 SR_FGT(SYS_TCR2ALIAS_EL1, HFGRTR2, nTCR2ALIAS_EL1, 0), 1439 SR_FGT(SYS_TCR2MASK_EL1, HFGRTR2, nTCR2MASK_EL1, 0), 1440 SR_FGT(SYS_TCRALIAS_EL1, HFGRTR2, nTCRALIAS_EL1, 0), 1441 SR_FGT(SYS_TCRMASK_EL1, HFGRTR2, nTCRMASK_EL1, 0), 1442 SR_FGT(SYS_ERXGSR_EL1, HFGRTR2, nERXGSR_EL1, 0), 1443 1444 /* HFGITR_EL2 */ 1445 SR_FGT(OP_AT_S1E1A, HFGITR, ATS1E1A, 1), 1446 SR_FGT(OP_COSP_RCTX, HFGITR, COSPRCTX, 1), 1447 SR_FGT(OP_GCSPUSHX, HFGITR, nGCSEPP, 0), 1448 SR_FGT(OP_GCSPOPX, HFGITR, nGCSEPP, 0), 1449 SR_FGT(OP_GCSPUSHM, HFGITR, nGCSPUSHM_EL1, 0), 1450 SR_FGT(OP_BRB_IALL, HFGITR, nBRBIALL, 0), 1451 SR_FGT(OP_BRB_INJ, HFGITR, nBRBINJ, 0), 1452 SR_FGT(SYS_DC_CVAC, HFGITR, DCCVAC, 1), 1453 SR_FGT(SYS_DC_CGVAC, HFGITR, DCCVAC, 1), 1454 SR_FGT(SYS_DC_CGDVAC, HFGITR, DCCVAC, 1), 1455 SR_FGT(OP_CPP_RCTX, HFGITR, CPPRCTX, 1), 1456 SR_FGT(OP_DVP_RCTX, HFGITR, DVPRCTX, 1), 1457 SR_FGT(OP_CFP_RCTX, HFGITR, CFPRCTX, 1), 1458 SR_FGT(OP_TLBI_VAALE1, HFGITR, TLBIVAALE1, 1), 1459 SR_FGT(OP_TLBI_VALE1, HFGITR, TLBIVALE1, 1), 1460 SR_FGT(OP_TLBI_VAAE1, HFGITR, TLBIVAAE1, 1), 1461 SR_FGT(OP_TLBI_ASIDE1, HFGITR, TLBIASIDE1, 1), 1462 SR_FGT(OP_TLBI_VAE1, HFGITR, TLBIVAE1, 1), 1463 SR_FGT(OP_TLBI_VMALLE1, HFGITR, TLBIVMALLE1, 1), 1464 SR_FGT(OP_TLBI_RVAALE1, HFGITR, TLBIRVAALE1, 1), 1465 SR_FGT(OP_TLBI_RVALE1, HFGITR, TLBIRVALE1, 1), 1466 SR_FGT(OP_TLBI_RVAAE1, HFGITR, TLBIRVAAE1, 1), 1467 SR_FGT(OP_TLBI_RVAE1, HFGITR, TLBIRVAE1, 1), 1468 SR_FGT(OP_TLBI_RVAALE1IS, HFGITR, TLBIRVAALE1IS, 1), 1469 SR_FGT(OP_TLBI_RVALE1IS, HFGITR, TLBIRVALE1IS, 1), 1470 SR_FGT(OP_TLBI_RVAAE1IS, HFGITR, TLBIRVAAE1IS, 1), 1471 SR_FGT(OP_TLBI_RVAE1IS, HFGITR, TLBIRVAE1IS, 1), 1472 SR_FGT(OP_TLBI_VAALE1IS, HFGITR, TLBIVAALE1IS, 1), 1473 SR_FGT(OP_TLBI_VALE1IS, HFGITR, TLBIVALE1IS, 1), 1474 SR_FGT(OP_TLBI_VAAE1IS, HFGITR, TLBIVAAE1IS, 1), 1475 SR_FGT(OP_TLBI_ASIDE1IS, HFGITR, TLBIASIDE1IS, 1), 1476 SR_FGT(OP_TLBI_VAE1IS, HFGITR, TLBIVAE1IS, 1), 1477 SR_FGT(OP_TLBI_VMALLE1IS, HFGITR, TLBIVMALLE1IS, 1), 1478 SR_FGT(OP_TLBI_RVAALE1OS, HFGITR, TLBIRVAALE1OS, 1), 1479 SR_FGT(OP_TLBI_RVALE1OS, HFGITR, TLBIRVALE1OS, 1), 1480 SR_FGT(OP_TLBI_RVAAE1OS, HFGITR, TLBIRVAAE1OS, 1), 1481 SR_FGT(OP_TLBI_RVAE1OS, HFGITR, TLBIRVAE1OS, 1), 1482 SR_FGT(OP_TLBI_VAALE1OS, HFGITR, TLBIVAALE1OS, 1), 1483 SR_FGT(OP_TLBI_VALE1OS, HFGITR, TLBIVALE1OS, 1), 1484 SR_FGT(OP_TLBI_VAAE1OS, HFGITR, TLBIVAAE1OS, 1), 1485 SR_FGT(OP_TLBI_ASIDE1OS, HFGITR, TLBIASIDE1OS, 1), 1486 SR_FGT(OP_TLBI_VAE1OS, HFGITR, TLBIVAE1OS, 1), 1487 SR_FGT(OP_TLBI_VMALLE1OS, HFGITR, TLBIVMALLE1OS, 1), 1488 /* nXS variants must be checked against HCRX_EL2.FGTnXS */ 1489 SR_FGF(OP_TLBI_VAALE1NXS, HFGITR, TLBIVAALE1, 1, HCRX_FGTnXS), 1490 SR_FGF(OP_TLBI_VALE1NXS, HFGITR, TLBIVALE1, 1, HCRX_FGTnXS), 1491 SR_FGF(OP_TLBI_VAAE1NXS, HFGITR, TLBIVAAE1, 1, HCRX_FGTnXS), 1492 SR_FGF(OP_TLBI_ASIDE1NXS, HFGITR, TLBIASIDE1, 1, HCRX_FGTnXS), 1493 SR_FGF(OP_TLBI_VAE1NXS, HFGITR, TLBIVAE1, 1, HCRX_FGTnXS), 1494 SR_FGF(OP_TLBI_VMALLE1NXS, HFGITR, TLBIVMALLE1, 1, HCRX_FGTnXS), 1495 SR_FGF(OP_TLBI_RVAALE1NXS, HFGITR, TLBIRVAALE1, 1, HCRX_FGTnXS), 1496 SR_FGF(OP_TLBI_RVALE1NXS, HFGITR, TLBIRVALE1, 1, HCRX_FGTnXS), 1497 SR_FGF(OP_TLBI_RVAAE1NXS, HFGITR, TLBIRVAAE1, 1, HCRX_FGTnXS), 1498 SR_FGF(OP_TLBI_RVAE1NXS, HFGITR, TLBIRVAE1, 1, HCRX_FGTnXS), 1499 SR_FGF(OP_TLBI_RVAALE1ISNXS, HFGITR, TLBIRVAALE1IS, 1, HCRX_FGTnXS), 1500 SR_FGF(OP_TLBI_RVALE1ISNXS, HFGITR, TLBIRVALE1IS, 1, HCRX_FGTnXS), 1501 SR_FGF(OP_TLBI_RVAAE1ISNXS, HFGITR, TLBIRVAAE1IS, 1, HCRX_FGTnXS), 1502 SR_FGF(OP_TLBI_RVAE1ISNXS, HFGITR, TLBIRVAE1IS, 1, HCRX_FGTnXS), 1503 SR_FGF(OP_TLBI_VAALE1ISNXS, HFGITR, TLBIVAALE1IS, 1, HCRX_FGTnXS), 1504 SR_FGF(OP_TLBI_VALE1ISNXS, HFGITR, TLBIVALE1IS, 1, HCRX_FGTnXS), 1505 SR_FGF(OP_TLBI_VAAE1ISNXS, HFGITR, TLBIVAAE1IS, 1, HCRX_FGTnXS), 1506 SR_FGF(OP_TLBI_ASIDE1ISNXS, HFGITR, TLBIASIDE1IS, 1, HCRX_FGTnXS), 1507 SR_FGF(OP_TLBI_VAE1ISNXS, HFGITR, TLBIVAE1IS, 1, HCRX_FGTnXS), 1508 SR_FGF(OP_TLBI_VMALLE1ISNXS, HFGITR, TLBIVMALLE1IS, 1, HCRX_FGTnXS), 1509 SR_FGF(OP_TLBI_RVAALE1OSNXS, HFGITR, TLBIRVAALE1OS, 1, HCRX_FGTnXS), 1510 SR_FGF(OP_TLBI_RVALE1OSNXS, HFGITR, TLBIRVALE1OS, 1, HCRX_FGTnXS), 1511 SR_FGF(OP_TLBI_RVAAE1OSNXS, HFGITR, TLBIRVAAE1OS, 1, HCRX_FGTnXS), 1512 SR_FGF(OP_TLBI_RVAE1OSNXS, HFGITR, TLBIRVAE1OS, 1, HCRX_FGTnXS), 1513 SR_FGF(OP_TLBI_VAALE1OSNXS, HFGITR, TLBIVAALE1OS, 1, HCRX_FGTnXS), 1514 SR_FGF(OP_TLBI_VALE1OSNXS, HFGITR, TLBIVALE1OS, 1, HCRX_FGTnXS), 1515 SR_FGF(OP_TLBI_VAAE1OSNXS, HFGITR, TLBIVAAE1OS, 1, HCRX_FGTnXS), 1516 SR_FGF(OP_TLBI_ASIDE1OSNXS, HFGITR, TLBIASIDE1OS, 1, HCRX_FGTnXS), 1517 SR_FGF(OP_TLBI_VAE1OSNXS, HFGITR, TLBIVAE1OS, 1, HCRX_FGTnXS), 1518 SR_FGF(OP_TLBI_VMALLE1OSNXS, HFGITR, TLBIVMALLE1OS, 1, HCRX_FGTnXS), 1519 SR_FGT(OP_AT_S1E1WP, HFGITR, ATS1E1WP, 1), 1520 SR_FGT(OP_AT_S1E1RP, HFGITR, ATS1E1RP, 1), 1521 SR_FGT(OP_AT_S1E0W, HFGITR, ATS1E0W, 1), 1522 SR_FGT(OP_AT_S1E0R, HFGITR, ATS1E0R, 1), 1523 SR_FGT(OP_AT_S1E1W, HFGITR, ATS1E1W, 1), 1524 SR_FGT(OP_AT_S1E1R, HFGITR, ATS1E1R, 1), 1525 SR_FGT(SYS_DC_ZVA, HFGITR, DCZVA, 1), 1526 SR_FGT(SYS_DC_GVA, HFGITR, DCZVA, 1), 1527 SR_FGT(SYS_DC_GZVA, HFGITR, DCZVA, 1), 1528 SR_FGT(SYS_DC_CIVAC, HFGITR, DCCIVAC, 1), 1529 SR_FGT(SYS_DC_CIGVAC, HFGITR, DCCIVAC, 1), 1530 SR_FGT(SYS_DC_CIGDVAC, HFGITR, DCCIVAC, 1), 1531 SR_FGT(SYS_DC_CVADP, HFGITR, DCCVADP, 1), 1532 SR_FGT(SYS_DC_CGVADP, HFGITR, DCCVADP, 1), 1533 SR_FGT(SYS_DC_CGDVADP, HFGITR, DCCVADP, 1), 1534 SR_FGT(SYS_DC_CVAP, HFGITR, DCCVAP, 1), 1535 SR_FGT(SYS_DC_CGVAP, HFGITR, DCCVAP, 1), 1536 SR_FGT(SYS_DC_CGDVAP, HFGITR, DCCVAP, 1), 1537 SR_FGT(SYS_DC_CVAU, HFGITR, DCCVAU, 1), 1538 SR_FGT(SYS_DC_CISW, HFGITR, DCCISW, 1), 1539 SR_FGT(SYS_DC_CIGSW, HFGITR, DCCISW, 1), 1540 SR_FGT(SYS_DC_CIGDSW, HFGITR, DCCISW, 1), 1541 SR_FGT(SYS_DC_CSW, HFGITR, DCCSW, 1), 1542 SR_FGT(SYS_DC_CGSW, HFGITR, DCCSW, 1), 1543 SR_FGT(SYS_DC_CGDSW, HFGITR, DCCSW, 1), 1544 SR_FGT(SYS_DC_ISW, HFGITR, DCISW, 1), 1545 SR_FGT(SYS_DC_IGSW, HFGITR, DCISW, 1), 1546 SR_FGT(SYS_DC_IGDSW, HFGITR, DCISW, 1), 1547 SR_FGT(SYS_DC_IVAC, HFGITR, DCIVAC, 1), 1548 SR_FGT(SYS_DC_IGVAC, HFGITR, DCIVAC, 1), 1549 SR_FGT(SYS_DC_IGDVAC, HFGITR, DCIVAC, 1), 1550 SR_FGT(SYS_IC_IVAU, HFGITR, ICIVAU, 1), 1551 SR_FGT(SYS_IC_IALLU, HFGITR, ICIALLU, 1), 1552 SR_FGT(SYS_IC_IALLUIS, HFGITR, ICIALLUIS, 1), 1553 1554 /* HFGITR2_EL2 */ 1555 SR_FGT(SYS_DC_CIGDVAPS, HFGITR2, nDCCIVAPS, 0), 1556 SR_FGT(SYS_DC_CIVAPS, HFGITR2, nDCCIVAPS, 0), 1557 1558 /* HDFGRTR_EL2 */ 1559 SR_FGT(SYS_PMBIDR_EL1, HDFGRTR, PMBIDR_EL1, 1), 1560 SR_FGT(SYS_PMSNEVFR_EL1, HDFGRTR, nPMSNEVFR_EL1, 0), 1561 SR_FGT(SYS_BRBINF_EL1(0), HDFGRTR, nBRBDATA, 0), 1562 SR_FGT(SYS_BRBINF_EL1(1), HDFGRTR, nBRBDATA, 0), 1563 SR_FGT(SYS_BRBINF_EL1(2), HDFGRTR, nBRBDATA, 0), 1564 SR_FGT(SYS_BRBINF_EL1(3), HDFGRTR, nBRBDATA, 0), 1565 SR_FGT(SYS_BRBINF_EL1(4), HDFGRTR, nBRBDATA, 0), 1566 SR_FGT(SYS_BRBINF_EL1(5), HDFGRTR, nBRBDATA, 0), 1567 SR_FGT(SYS_BRBINF_EL1(6), HDFGRTR, nBRBDATA, 0), 1568 SR_FGT(SYS_BRBINF_EL1(7), HDFGRTR, nBRBDATA, 0), 1569 SR_FGT(SYS_BRBINF_EL1(8), HDFGRTR, nBRBDATA, 0), 1570 SR_FGT(SYS_BRBINF_EL1(9), HDFGRTR, nBRBDATA, 0), 1571 SR_FGT(SYS_BRBINF_EL1(10), HDFGRTR, nBRBDATA, 0), 1572 SR_FGT(SYS_BRBINF_EL1(11), HDFGRTR, nBRBDATA, 0), 1573 SR_FGT(SYS_BRBINF_EL1(12), HDFGRTR, nBRBDATA, 0), 1574 SR_FGT(SYS_BRBINF_EL1(13), HDFGRTR, nBRBDATA, 0), 1575 SR_FGT(SYS_BRBINF_EL1(14), HDFGRTR, nBRBDATA, 0), 1576 SR_FGT(SYS_BRBINF_EL1(15), HDFGRTR, nBRBDATA, 0), 1577 SR_FGT(SYS_BRBINF_EL1(16), HDFGRTR, nBRBDATA, 0), 1578 SR_FGT(SYS_BRBINF_EL1(17), HDFGRTR, nBRBDATA, 0), 1579 SR_FGT(SYS_BRBINF_EL1(18), HDFGRTR, nBRBDATA, 0), 1580 SR_FGT(SYS_BRBINF_EL1(19), HDFGRTR, nBRBDATA, 0), 1581 SR_FGT(SYS_BRBINF_EL1(20), HDFGRTR, nBRBDATA, 0), 1582 SR_FGT(SYS_BRBINF_EL1(21), HDFGRTR, nBRBDATA, 0), 1583 SR_FGT(SYS_BRBINF_EL1(22), HDFGRTR, nBRBDATA, 0), 1584 SR_FGT(SYS_BRBINF_EL1(23), HDFGRTR, nBRBDATA, 0), 1585 SR_FGT(SYS_BRBINF_EL1(24), HDFGRTR, nBRBDATA, 0), 1586 SR_FGT(SYS_BRBINF_EL1(25), HDFGRTR, nBRBDATA, 0), 1587 SR_FGT(SYS_BRBINF_EL1(26), HDFGRTR, nBRBDATA, 0), 1588 SR_FGT(SYS_BRBINF_EL1(27), HDFGRTR, nBRBDATA, 0), 1589 SR_FGT(SYS_BRBINF_EL1(28), HDFGRTR, nBRBDATA, 0), 1590 SR_FGT(SYS_BRBINF_EL1(29), HDFGRTR, nBRBDATA, 0), 1591 SR_FGT(SYS_BRBINF_EL1(30), HDFGRTR, nBRBDATA, 0), 1592 SR_FGT(SYS_BRBINF_EL1(31), HDFGRTR, nBRBDATA, 0), 1593 SR_FGT(SYS_BRBINFINJ_EL1, HDFGRTR, nBRBDATA, 0), 1594 SR_FGT(SYS_BRBSRC_EL1(0), HDFGRTR, nBRBDATA, 0), 1595 SR_FGT(SYS_BRBSRC_EL1(1), HDFGRTR, nBRBDATA, 0), 1596 SR_FGT(SYS_BRBSRC_EL1(2), HDFGRTR, nBRBDATA, 0), 1597 SR_FGT(SYS_BRBSRC_EL1(3), HDFGRTR, nBRBDATA, 0), 1598 SR_FGT(SYS_BRBSRC_EL1(4), HDFGRTR, nBRBDATA, 0), 1599 SR_FGT(SYS_BRBSRC_EL1(5), HDFGRTR, nBRBDATA, 0), 1600 SR_FGT(SYS_BRBSRC_EL1(6), HDFGRTR, nBRBDATA, 0), 1601 SR_FGT(SYS_BRBSRC_EL1(7), HDFGRTR, nBRBDATA, 0), 1602 SR_FGT(SYS_BRBSRC_EL1(8), HDFGRTR, nBRBDATA, 0), 1603 SR_FGT(SYS_BRBSRC_EL1(9), HDFGRTR, nBRBDATA, 0), 1604 SR_FGT(SYS_BRBSRC_EL1(10), HDFGRTR, nBRBDATA, 0), 1605 SR_FGT(SYS_BRBSRC_EL1(11), HDFGRTR, nBRBDATA, 0), 1606 SR_FGT(SYS_BRBSRC_EL1(12), HDFGRTR, nBRBDATA, 0), 1607 SR_FGT(SYS_BRBSRC_EL1(13), HDFGRTR, nBRBDATA, 0), 1608 SR_FGT(SYS_BRBSRC_EL1(14), HDFGRTR, nBRBDATA, 0), 1609 SR_FGT(SYS_BRBSRC_EL1(15), HDFGRTR, nBRBDATA, 0), 1610 SR_FGT(SYS_BRBSRC_EL1(16), HDFGRTR, nBRBDATA, 0), 1611 SR_FGT(SYS_BRBSRC_EL1(17), HDFGRTR, nBRBDATA, 0), 1612 SR_FGT(SYS_BRBSRC_EL1(18), HDFGRTR, nBRBDATA, 0), 1613 SR_FGT(SYS_BRBSRC_EL1(19), HDFGRTR, nBRBDATA, 0), 1614 SR_FGT(SYS_BRBSRC_EL1(20), HDFGRTR, nBRBDATA, 0), 1615 SR_FGT(SYS_BRBSRC_EL1(21), HDFGRTR, nBRBDATA, 0), 1616 SR_FGT(SYS_BRBSRC_EL1(22), HDFGRTR, nBRBDATA, 0), 1617 SR_FGT(SYS_BRBSRC_EL1(23), HDFGRTR, nBRBDATA, 0), 1618 SR_FGT(SYS_BRBSRC_EL1(24), HDFGRTR, nBRBDATA, 0), 1619 SR_FGT(SYS_BRBSRC_EL1(25), HDFGRTR, nBRBDATA, 0), 1620 SR_FGT(SYS_BRBSRC_EL1(26), HDFGRTR, nBRBDATA, 0), 1621 SR_FGT(SYS_BRBSRC_EL1(27), HDFGRTR, nBRBDATA, 0), 1622 SR_FGT(SYS_BRBSRC_EL1(28), HDFGRTR, nBRBDATA, 0), 1623 SR_FGT(SYS_BRBSRC_EL1(29), HDFGRTR, nBRBDATA, 0), 1624 SR_FGT(SYS_BRBSRC_EL1(30), HDFGRTR, nBRBDATA, 0), 1625 SR_FGT(SYS_BRBSRC_EL1(31), HDFGRTR, nBRBDATA, 0), 1626 SR_FGT(SYS_BRBSRCINJ_EL1, HDFGRTR, nBRBDATA, 0), 1627 SR_FGT(SYS_BRBTGT_EL1(0), HDFGRTR, nBRBDATA, 0), 1628 SR_FGT(SYS_BRBTGT_EL1(1), HDFGRTR, nBRBDATA, 0), 1629 SR_FGT(SYS_BRBTGT_EL1(2), HDFGRTR, nBRBDATA, 0), 1630 SR_FGT(SYS_BRBTGT_EL1(3), HDFGRTR, nBRBDATA, 0), 1631 SR_FGT(SYS_BRBTGT_EL1(4), HDFGRTR, nBRBDATA, 0), 1632 SR_FGT(SYS_BRBTGT_EL1(5), HDFGRTR, nBRBDATA, 0), 1633 SR_FGT(SYS_BRBTGT_EL1(6), HDFGRTR, nBRBDATA, 0), 1634 SR_FGT(SYS_BRBTGT_EL1(7), HDFGRTR, nBRBDATA, 0), 1635 SR_FGT(SYS_BRBTGT_EL1(8), HDFGRTR, nBRBDATA, 0), 1636 SR_FGT(SYS_BRBTGT_EL1(9), HDFGRTR, nBRBDATA, 0), 1637 SR_FGT(SYS_BRBTGT_EL1(10), HDFGRTR, nBRBDATA, 0), 1638 SR_FGT(SYS_BRBTGT_EL1(11), HDFGRTR, nBRBDATA, 0), 1639 SR_FGT(SYS_BRBTGT_EL1(12), HDFGRTR, nBRBDATA, 0), 1640 SR_FGT(SYS_BRBTGT_EL1(13), HDFGRTR, nBRBDATA, 0), 1641 SR_FGT(SYS_BRBTGT_EL1(14), HDFGRTR, nBRBDATA, 0), 1642 SR_FGT(SYS_BRBTGT_EL1(15), HDFGRTR, nBRBDATA, 0), 1643 SR_FGT(SYS_BRBTGT_EL1(16), HDFGRTR, nBRBDATA, 0), 1644 SR_FGT(SYS_BRBTGT_EL1(17), HDFGRTR, nBRBDATA, 0), 1645 SR_FGT(SYS_BRBTGT_EL1(18), HDFGRTR, nBRBDATA, 0), 1646 SR_FGT(SYS_BRBTGT_EL1(19), HDFGRTR, nBRBDATA, 0), 1647 SR_FGT(SYS_BRBTGT_EL1(20), HDFGRTR, nBRBDATA, 0), 1648 SR_FGT(SYS_BRBTGT_EL1(21), HDFGRTR, nBRBDATA, 0), 1649 SR_FGT(SYS_BRBTGT_EL1(22), HDFGRTR, nBRBDATA, 0), 1650 SR_FGT(SYS_BRBTGT_EL1(23), HDFGRTR, nBRBDATA, 0), 1651 SR_FGT(SYS_BRBTGT_EL1(24), HDFGRTR, nBRBDATA, 0), 1652 SR_FGT(SYS_BRBTGT_EL1(25), HDFGRTR, nBRBDATA, 0), 1653 SR_FGT(SYS_BRBTGT_EL1(26), HDFGRTR, nBRBDATA, 0), 1654 SR_FGT(SYS_BRBTGT_EL1(27), HDFGRTR, nBRBDATA, 0), 1655 SR_FGT(SYS_BRBTGT_EL1(28), HDFGRTR, nBRBDATA, 0), 1656 SR_FGT(SYS_BRBTGT_EL1(29), HDFGRTR, nBRBDATA, 0), 1657 SR_FGT(SYS_BRBTGT_EL1(30), HDFGRTR, nBRBDATA, 0), 1658 SR_FGT(SYS_BRBTGT_EL1(31), HDFGRTR, nBRBDATA, 0), 1659 SR_FGT(SYS_BRBTGTINJ_EL1, HDFGRTR, nBRBDATA, 0), 1660 SR_FGT(SYS_BRBTS_EL1, HDFGRTR, nBRBDATA, 0), 1661 SR_FGT(SYS_BRBCR_EL1, HDFGRTR, nBRBCTL, 0), 1662 SR_FGT(SYS_BRBFCR_EL1, HDFGRTR, nBRBCTL, 0), 1663 SR_FGT(SYS_BRBIDR0_EL1, HDFGRTR, nBRBIDR, 0), 1664 SR_FGT(SYS_PMCEID0_EL0, HDFGRTR, PMCEIDn_EL0, 1), 1665 SR_FGT(SYS_PMCEID1_EL0, HDFGRTR, PMCEIDn_EL0, 1), 1666 SR_FGT(SYS_PMUSERENR_EL0, HDFGRTR, PMUSERENR_EL0, 1), 1667 SR_FGT(SYS_TRBTRG_EL1, HDFGRTR, TRBTRG_EL1, 1), 1668 SR_FGT(SYS_TRBSR_EL1, HDFGRTR, TRBSR_EL1, 1), 1669 SR_FGT(SYS_TRBPTR_EL1, HDFGRTR, TRBPTR_EL1, 1), 1670 SR_FGT(SYS_TRBMAR_EL1, HDFGRTR, TRBMAR_EL1, 1), 1671 SR_FGT(SYS_TRBLIMITR_EL1, HDFGRTR, TRBLIMITR_EL1, 1), 1672 SR_FGT(SYS_TRBIDR_EL1, HDFGRTR, TRBIDR_EL1, 1), 1673 SR_FGT(SYS_TRBBASER_EL1, HDFGRTR, TRBBASER_EL1, 1), 1674 SR_FGT(SYS_TRCVICTLR, HDFGRTR, TRCVICTLR, 1), 1675 SR_FGT(SYS_TRCSTATR, HDFGRTR, TRCSTATR, 1), 1676 SR_FGT(SYS_TRCSSCSR(0), HDFGRTR, TRCSSCSRn, 1), 1677 SR_FGT(SYS_TRCSSCSR(1), HDFGRTR, TRCSSCSRn, 1), 1678 SR_FGT(SYS_TRCSSCSR(2), HDFGRTR, TRCSSCSRn, 1), 1679 SR_FGT(SYS_TRCSSCSR(3), HDFGRTR, TRCSSCSRn, 1), 1680 SR_FGT(SYS_TRCSSCSR(4), HDFGRTR, TRCSSCSRn, 1), 1681 SR_FGT(SYS_TRCSSCSR(5), HDFGRTR, TRCSSCSRn, 1), 1682 SR_FGT(SYS_TRCSSCSR(6), HDFGRTR, TRCSSCSRn, 1), 1683 SR_FGT(SYS_TRCSSCSR(7), HDFGRTR, TRCSSCSRn, 1), 1684 SR_FGT(SYS_TRCSEQSTR, HDFGRTR, TRCSEQSTR, 1), 1685 SR_FGT(SYS_TRCPRGCTLR, HDFGRTR, TRCPRGCTLR, 1), 1686 SR_FGT(SYS_TRCOSLSR, HDFGRTR, TRCOSLSR, 1), 1687 SR_FGT(SYS_TRCIMSPEC(0), HDFGRTR, TRCIMSPECn, 1), 1688 SR_FGT(SYS_TRCIMSPEC(1), HDFGRTR, TRCIMSPECn, 1), 1689 SR_FGT(SYS_TRCIMSPEC(2), HDFGRTR, TRCIMSPECn, 1), 1690 SR_FGT(SYS_TRCIMSPEC(3), HDFGRTR, TRCIMSPECn, 1), 1691 SR_FGT(SYS_TRCIMSPEC(4), HDFGRTR, TRCIMSPECn, 1), 1692 SR_FGT(SYS_TRCIMSPEC(5), HDFGRTR, TRCIMSPECn, 1), 1693 SR_FGT(SYS_TRCIMSPEC(6), HDFGRTR, TRCIMSPECn, 1), 1694 SR_FGT(SYS_TRCIMSPEC(7), HDFGRTR, TRCIMSPECn, 1), 1695 SR_FGT(SYS_TRCDEVARCH, HDFGRTR, TRCID, 1), 1696 SR_FGT(SYS_TRCDEVID, HDFGRTR, TRCID, 1), 1697 SR_FGT(SYS_TRCIDR0, HDFGRTR, TRCID, 1), 1698 SR_FGT(SYS_TRCIDR1, HDFGRTR, TRCID, 1), 1699 SR_FGT(SYS_TRCIDR2, HDFGRTR, TRCID, 1), 1700 SR_FGT(SYS_TRCIDR3, HDFGRTR, TRCID, 1), 1701 SR_FGT(SYS_TRCIDR4, HDFGRTR, TRCID, 1), 1702 SR_FGT(SYS_TRCIDR5, HDFGRTR, TRCID, 1), 1703 SR_FGT(SYS_TRCIDR6, HDFGRTR, TRCID, 1), 1704 SR_FGT(SYS_TRCIDR7, HDFGRTR, TRCID, 1), 1705 SR_FGT(SYS_TRCIDR8, HDFGRTR, TRCID, 1), 1706 SR_FGT(SYS_TRCIDR9, HDFGRTR, TRCID, 1), 1707 SR_FGT(SYS_TRCIDR10, HDFGRTR, TRCID, 1), 1708 SR_FGT(SYS_TRCIDR11, HDFGRTR, TRCID, 1), 1709 SR_FGT(SYS_TRCIDR12, HDFGRTR, TRCID, 1), 1710 SR_FGT(SYS_TRCIDR13, HDFGRTR, TRCID, 1), 1711 SR_FGT(SYS_TRCCNTVR(0), HDFGRTR, TRCCNTVRn, 1), 1712 SR_FGT(SYS_TRCCNTVR(1), HDFGRTR, TRCCNTVRn, 1), 1713 SR_FGT(SYS_TRCCNTVR(2), HDFGRTR, TRCCNTVRn, 1), 1714 SR_FGT(SYS_TRCCNTVR(3), HDFGRTR, TRCCNTVRn, 1), 1715 SR_FGT(SYS_TRCCLAIMCLR, HDFGRTR, TRCCLAIM, 1), 1716 SR_FGT(SYS_TRCCLAIMSET, HDFGRTR, TRCCLAIM, 1), 1717 SR_FGT(SYS_TRCAUXCTLR, HDFGRTR, TRCAUXCTLR, 1), 1718 SR_FGT(SYS_TRCAUTHSTATUS, HDFGRTR, TRCAUTHSTATUS, 1), 1719 SR_FGT(SYS_TRCACATR(0), HDFGRTR, TRC, 1), 1720 SR_FGT(SYS_TRCACATR(1), HDFGRTR, TRC, 1), 1721 SR_FGT(SYS_TRCACATR(2), HDFGRTR, TRC, 1), 1722 SR_FGT(SYS_TRCACATR(3), HDFGRTR, TRC, 1), 1723 SR_FGT(SYS_TRCACATR(4), HDFGRTR, TRC, 1), 1724 SR_FGT(SYS_TRCACATR(5), HDFGRTR, TRC, 1), 1725 SR_FGT(SYS_TRCACATR(6), HDFGRTR, TRC, 1), 1726 SR_FGT(SYS_TRCACATR(7), HDFGRTR, TRC, 1), 1727 SR_FGT(SYS_TRCACATR(8), HDFGRTR, TRC, 1), 1728 SR_FGT(SYS_TRCACATR(9), HDFGRTR, TRC, 1), 1729 SR_FGT(SYS_TRCACATR(10), HDFGRTR, TRC, 1), 1730 SR_FGT(SYS_TRCACATR(11), HDFGRTR, TRC, 1), 1731 SR_FGT(SYS_TRCACATR(12), HDFGRTR, TRC, 1), 1732 SR_FGT(SYS_TRCACATR(13), HDFGRTR, TRC, 1), 1733 SR_FGT(SYS_TRCACATR(14), HDFGRTR, TRC, 1), 1734 SR_FGT(SYS_TRCACATR(15), HDFGRTR, TRC, 1), 1735 SR_FGT(SYS_TRCACVR(0), HDFGRTR, TRC, 1), 1736 SR_FGT(SYS_TRCACVR(1), HDFGRTR, TRC, 1), 1737 SR_FGT(SYS_TRCACVR(2), HDFGRTR, TRC, 1), 1738 SR_FGT(SYS_TRCACVR(3), HDFGRTR, TRC, 1), 1739 SR_FGT(SYS_TRCACVR(4), HDFGRTR, TRC, 1), 1740 SR_FGT(SYS_TRCACVR(5), HDFGRTR, TRC, 1), 1741 SR_FGT(SYS_TRCACVR(6), HDFGRTR, TRC, 1), 1742 SR_FGT(SYS_TRCACVR(7), HDFGRTR, TRC, 1), 1743 SR_FGT(SYS_TRCACVR(8), HDFGRTR, TRC, 1), 1744 SR_FGT(SYS_TRCACVR(9), HDFGRTR, TRC, 1), 1745 SR_FGT(SYS_TRCACVR(10), HDFGRTR, TRC, 1), 1746 SR_FGT(SYS_TRCACVR(11), HDFGRTR, TRC, 1), 1747 SR_FGT(SYS_TRCACVR(12), HDFGRTR, TRC, 1), 1748 SR_FGT(SYS_TRCACVR(13), HDFGRTR, TRC, 1), 1749 SR_FGT(SYS_TRCACVR(14), HDFGRTR, TRC, 1), 1750 SR_FGT(SYS_TRCACVR(15), HDFGRTR, TRC, 1), 1751 SR_FGT(SYS_TRCBBCTLR, HDFGRTR, TRC, 1), 1752 SR_FGT(SYS_TRCCCCTLR, HDFGRTR, TRC, 1), 1753 SR_FGT(SYS_TRCCIDCCTLR0, HDFGRTR, TRC, 1), 1754 SR_FGT(SYS_TRCCIDCCTLR1, HDFGRTR, TRC, 1), 1755 SR_FGT(SYS_TRCCIDCVR(0), HDFGRTR, TRC, 1), 1756 SR_FGT(SYS_TRCCIDCVR(1), HDFGRTR, TRC, 1), 1757 SR_FGT(SYS_TRCCIDCVR(2), HDFGRTR, TRC, 1), 1758 SR_FGT(SYS_TRCCIDCVR(3), HDFGRTR, TRC, 1), 1759 SR_FGT(SYS_TRCCIDCVR(4), HDFGRTR, TRC, 1), 1760 SR_FGT(SYS_TRCCIDCVR(5), HDFGRTR, TRC, 1), 1761 SR_FGT(SYS_TRCCIDCVR(6), HDFGRTR, TRC, 1), 1762 SR_FGT(SYS_TRCCIDCVR(7), HDFGRTR, TRC, 1), 1763 SR_FGT(SYS_TRCCNTCTLR(0), HDFGRTR, TRC, 1), 1764 SR_FGT(SYS_TRCCNTCTLR(1), HDFGRTR, TRC, 1), 1765 SR_FGT(SYS_TRCCNTCTLR(2), HDFGRTR, TRC, 1), 1766 SR_FGT(SYS_TRCCNTCTLR(3), HDFGRTR, TRC, 1), 1767 SR_FGT(SYS_TRCCNTRLDVR(0), HDFGRTR, TRC, 1), 1768 SR_FGT(SYS_TRCCNTRLDVR(1), HDFGRTR, TRC, 1), 1769 SR_FGT(SYS_TRCCNTRLDVR(2), HDFGRTR, TRC, 1), 1770 SR_FGT(SYS_TRCCNTRLDVR(3), HDFGRTR, TRC, 1), 1771 SR_FGT(SYS_TRCCONFIGR, HDFGRTR, TRC, 1), 1772 SR_FGT(SYS_TRCEVENTCTL0R, HDFGRTR, TRC, 1), 1773 SR_FGT(SYS_TRCEVENTCTL1R, HDFGRTR, TRC, 1), 1774 SR_FGT(SYS_TRCEXTINSELR(0), HDFGRTR, TRC, 1), 1775 SR_FGT(SYS_TRCEXTINSELR(1), HDFGRTR, TRC, 1), 1776 SR_FGT(SYS_TRCEXTINSELR(2), HDFGRTR, TRC, 1), 1777 SR_FGT(SYS_TRCEXTINSELR(3), HDFGRTR, TRC, 1), 1778 SR_FGT(SYS_TRCQCTLR, HDFGRTR, TRC, 1), 1779 SR_FGT(SYS_TRCRSCTLR(2), HDFGRTR, TRC, 1), 1780 SR_FGT(SYS_TRCRSCTLR(3), HDFGRTR, TRC, 1), 1781 SR_FGT(SYS_TRCRSCTLR(4), HDFGRTR, TRC, 1), 1782 SR_FGT(SYS_TRCRSCTLR(5), HDFGRTR, TRC, 1), 1783 SR_FGT(SYS_TRCRSCTLR(6), HDFGRTR, TRC, 1), 1784 SR_FGT(SYS_TRCRSCTLR(7), HDFGRTR, TRC, 1), 1785 SR_FGT(SYS_TRCRSCTLR(8), HDFGRTR, TRC, 1), 1786 SR_FGT(SYS_TRCRSCTLR(9), HDFGRTR, TRC, 1), 1787 SR_FGT(SYS_TRCRSCTLR(10), HDFGRTR, TRC, 1), 1788 SR_FGT(SYS_TRCRSCTLR(11), HDFGRTR, TRC, 1), 1789 SR_FGT(SYS_TRCRSCTLR(12), HDFGRTR, TRC, 1), 1790 SR_FGT(SYS_TRCRSCTLR(13), HDFGRTR, TRC, 1), 1791 SR_FGT(SYS_TRCRSCTLR(14), HDFGRTR, TRC, 1), 1792 SR_FGT(SYS_TRCRSCTLR(15), HDFGRTR, TRC, 1), 1793 SR_FGT(SYS_TRCRSCTLR(16), HDFGRTR, TRC, 1), 1794 SR_FGT(SYS_TRCRSCTLR(17), HDFGRTR, TRC, 1), 1795 SR_FGT(SYS_TRCRSCTLR(18), HDFGRTR, TRC, 1), 1796 SR_FGT(SYS_TRCRSCTLR(19), HDFGRTR, TRC, 1), 1797 SR_FGT(SYS_TRCRSCTLR(20), HDFGRTR, TRC, 1), 1798 SR_FGT(SYS_TRCRSCTLR(21), HDFGRTR, TRC, 1), 1799 SR_FGT(SYS_TRCRSCTLR(22), HDFGRTR, TRC, 1), 1800 SR_FGT(SYS_TRCRSCTLR(23), HDFGRTR, TRC, 1), 1801 SR_FGT(SYS_TRCRSCTLR(24), HDFGRTR, TRC, 1), 1802 SR_FGT(SYS_TRCRSCTLR(25), HDFGRTR, TRC, 1), 1803 SR_FGT(SYS_TRCRSCTLR(26), HDFGRTR, TRC, 1), 1804 SR_FGT(SYS_TRCRSCTLR(27), HDFGRTR, TRC, 1), 1805 SR_FGT(SYS_TRCRSCTLR(28), HDFGRTR, TRC, 1), 1806 SR_FGT(SYS_TRCRSCTLR(29), HDFGRTR, TRC, 1), 1807 SR_FGT(SYS_TRCRSCTLR(30), HDFGRTR, TRC, 1), 1808 SR_FGT(SYS_TRCRSCTLR(31), HDFGRTR, TRC, 1), 1809 SR_FGT(SYS_TRCRSR, HDFGRTR, TRC, 1), 1810 SR_FGT(SYS_TRCSEQEVR(0), HDFGRTR, TRC, 1), 1811 SR_FGT(SYS_TRCSEQEVR(1), HDFGRTR, TRC, 1), 1812 SR_FGT(SYS_TRCSEQEVR(2), HDFGRTR, TRC, 1), 1813 SR_FGT(SYS_TRCSEQRSTEVR, HDFGRTR, TRC, 1), 1814 SR_FGT(SYS_TRCSSCCR(0), HDFGRTR, TRC, 1), 1815 SR_FGT(SYS_TRCSSCCR(1), HDFGRTR, TRC, 1), 1816 SR_FGT(SYS_TRCSSCCR(2), HDFGRTR, TRC, 1), 1817 SR_FGT(SYS_TRCSSCCR(3), HDFGRTR, TRC, 1), 1818 SR_FGT(SYS_TRCSSCCR(4), HDFGRTR, TRC, 1), 1819 SR_FGT(SYS_TRCSSCCR(5), HDFGRTR, TRC, 1), 1820 SR_FGT(SYS_TRCSSCCR(6), HDFGRTR, TRC, 1), 1821 SR_FGT(SYS_TRCSSCCR(7), HDFGRTR, TRC, 1), 1822 SR_FGT(SYS_TRCSSPCICR(0), HDFGRTR, TRC, 1), 1823 SR_FGT(SYS_TRCSSPCICR(1), HDFGRTR, TRC, 1), 1824 SR_FGT(SYS_TRCSSPCICR(2), HDFGRTR, TRC, 1), 1825 SR_FGT(SYS_TRCSSPCICR(3), HDFGRTR, TRC, 1), 1826 SR_FGT(SYS_TRCSSPCICR(4), HDFGRTR, TRC, 1), 1827 SR_FGT(SYS_TRCSSPCICR(5), HDFGRTR, TRC, 1), 1828 SR_FGT(SYS_TRCSSPCICR(6), HDFGRTR, TRC, 1), 1829 SR_FGT(SYS_TRCSSPCICR(7), HDFGRTR, TRC, 1), 1830 SR_FGT(SYS_TRCSTALLCTLR, HDFGRTR, TRC, 1), 1831 SR_FGT(SYS_TRCSYNCPR, HDFGRTR, TRC, 1), 1832 SR_FGT(SYS_TRCTRACEIDR, HDFGRTR, TRC, 1), 1833 SR_FGT(SYS_TRCTSCTLR, HDFGRTR, TRC, 1), 1834 SR_FGT(SYS_TRCVIIECTLR, HDFGRTR, TRC, 1), 1835 SR_FGT(SYS_TRCVIPCSSCTLR, HDFGRTR, TRC, 1), 1836 SR_FGT(SYS_TRCVISSCTLR, HDFGRTR, TRC, 1), 1837 SR_FGT(SYS_TRCVMIDCCTLR0, HDFGRTR, TRC, 1), 1838 SR_FGT(SYS_TRCVMIDCCTLR1, HDFGRTR, TRC, 1), 1839 SR_FGT(SYS_TRCVMIDCVR(0), HDFGRTR, TRC, 1), 1840 SR_FGT(SYS_TRCVMIDCVR(1), HDFGRTR, TRC, 1), 1841 SR_FGT(SYS_TRCVMIDCVR(2), HDFGRTR, TRC, 1), 1842 SR_FGT(SYS_TRCVMIDCVR(3), HDFGRTR, TRC, 1), 1843 SR_FGT(SYS_TRCVMIDCVR(4), HDFGRTR, TRC, 1), 1844 SR_FGT(SYS_TRCVMIDCVR(5), HDFGRTR, TRC, 1), 1845 SR_FGT(SYS_TRCVMIDCVR(6), HDFGRTR, TRC, 1), 1846 SR_FGT(SYS_TRCVMIDCVR(7), HDFGRTR, TRC, 1), 1847 SR_FGT(SYS_PMSLATFR_EL1, HDFGRTR, PMSLATFR_EL1, 1), 1848 SR_FGT(SYS_PMSIRR_EL1, HDFGRTR, PMSIRR_EL1, 1), 1849 SR_FGT(SYS_PMSIDR_EL1, HDFGRTR, PMSIDR_EL1, 1), 1850 SR_FGT(SYS_PMSICR_EL1, HDFGRTR, PMSICR_EL1, 1), 1851 SR_FGT(SYS_PMSFCR_EL1, HDFGRTR, PMSFCR_EL1, 1), 1852 SR_FGT(SYS_PMSEVFR_EL1, HDFGRTR, PMSEVFR_EL1, 1), 1853 SR_FGT(SYS_PMSCR_EL1, HDFGRTR, PMSCR_EL1, 1), 1854 SR_FGT(SYS_PMBSR_EL1, HDFGRTR, PMBSR_EL1, 1), 1855 SR_FGT(SYS_PMBPTR_EL1, HDFGRTR, PMBPTR_EL1, 1), 1856 SR_FGT(SYS_PMBLIMITR_EL1, HDFGRTR, PMBLIMITR_EL1, 1), 1857 SR_FGT(SYS_PMMIR_EL1, HDFGRTR, PMMIR_EL1, 1), 1858 SR_FGT(SYS_PMSELR_EL0, HDFGRTR, PMSELR_EL0, 1), 1859 SR_FGT(SYS_PMOVSCLR_EL0, HDFGRTR, PMOVS, 1), 1860 SR_FGT(SYS_PMOVSSET_EL0, HDFGRTR, PMOVS, 1), 1861 SR_FGT(SYS_PMINTENCLR_EL1, HDFGRTR, PMINTEN, 1), 1862 SR_FGT(SYS_PMINTENSET_EL1, HDFGRTR, PMINTEN, 1), 1863 SR_FGT(SYS_PMCNTENCLR_EL0, HDFGRTR, PMCNTEN, 1), 1864 SR_FGT(SYS_PMCNTENSET_EL0, HDFGRTR, PMCNTEN, 1), 1865 SR_FGT(SYS_PMCCNTR_EL0, HDFGRTR, PMCCNTR_EL0, 1), 1866 SR_FGT(SYS_PMCCFILTR_EL0, HDFGRTR, PMCCFILTR_EL0, 1), 1867 SR_FGT_RANGE(SYS_PMEVTYPERn_EL0(0), 1868 SYS_PMEVTYPERn_EL0(30), 1869 HDFGRTR, PMEVTYPERn_EL0, 1), 1870 SR_FGT_RANGE(SYS_PMEVCNTRn_EL0(0), 1871 SYS_PMEVCNTRn_EL0(30), 1872 HDFGRTR, PMEVCNTRn_EL0, 1), 1873 SR_FGT(SYS_OSDLR_EL1, HDFGRTR, OSDLR_EL1, 1), 1874 SR_FGT(SYS_OSECCR_EL1, HDFGRTR, OSECCR_EL1, 1), 1875 SR_FGT(SYS_OSLSR_EL1, HDFGRTR, OSLSR_EL1, 1), 1876 SR_FGT(SYS_DBGPRCR_EL1, HDFGRTR, DBGPRCR_EL1, 1), 1877 SR_FGT(SYS_DBGAUTHSTATUS_EL1, HDFGRTR, DBGAUTHSTATUS_EL1, 1), 1878 SR_FGT(SYS_DBGCLAIMSET_EL1, HDFGRTR, DBGCLAIM, 1), 1879 SR_FGT(SYS_DBGCLAIMCLR_EL1, HDFGRTR, DBGCLAIM, 1), 1880 SR_FGT(SYS_MDSCR_EL1, HDFGRTR, MDSCR_EL1, 1), 1881 /* 1882 * The trap bits capture *64* debug registers per bit, but the 1883 * ARM ARM only describes the encoding for the first 16, and 1884 * we don't really support more than that anyway. 1885 */ 1886 SR_FGT(SYS_DBGWVRn_EL1(0), HDFGRTR, DBGWVRn_EL1, 1), 1887 SR_FGT(SYS_DBGWVRn_EL1(1), HDFGRTR, DBGWVRn_EL1, 1), 1888 SR_FGT(SYS_DBGWVRn_EL1(2), HDFGRTR, DBGWVRn_EL1, 1), 1889 SR_FGT(SYS_DBGWVRn_EL1(3), HDFGRTR, DBGWVRn_EL1, 1), 1890 SR_FGT(SYS_DBGWVRn_EL1(4), HDFGRTR, DBGWVRn_EL1, 1), 1891 SR_FGT(SYS_DBGWVRn_EL1(5), HDFGRTR, DBGWVRn_EL1, 1), 1892 SR_FGT(SYS_DBGWVRn_EL1(6), HDFGRTR, DBGWVRn_EL1, 1), 1893 SR_FGT(SYS_DBGWVRn_EL1(7), HDFGRTR, DBGWVRn_EL1, 1), 1894 SR_FGT(SYS_DBGWVRn_EL1(8), HDFGRTR, DBGWVRn_EL1, 1), 1895 SR_FGT(SYS_DBGWVRn_EL1(9), HDFGRTR, DBGWVRn_EL1, 1), 1896 SR_FGT(SYS_DBGWVRn_EL1(10), HDFGRTR, DBGWVRn_EL1, 1), 1897 SR_FGT(SYS_DBGWVRn_EL1(11), HDFGRTR, DBGWVRn_EL1, 1), 1898 SR_FGT(SYS_DBGWVRn_EL1(12), HDFGRTR, DBGWVRn_EL1, 1), 1899 SR_FGT(SYS_DBGWVRn_EL1(13), HDFGRTR, DBGWVRn_EL1, 1), 1900 SR_FGT(SYS_DBGWVRn_EL1(14), HDFGRTR, DBGWVRn_EL1, 1), 1901 SR_FGT(SYS_DBGWVRn_EL1(15), HDFGRTR, DBGWVRn_EL1, 1), 1902 SR_FGT(SYS_DBGWCRn_EL1(0), HDFGRTR, DBGWCRn_EL1, 1), 1903 SR_FGT(SYS_DBGWCRn_EL1(1), HDFGRTR, DBGWCRn_EL1, 1), 1904 SR_FGT(SYS_DBGWCRn_EL1(2), HDFGRTR, DBGWCRn_EL1, 1), 1905 SR_FGT(SYS_DBGWCRn_EL1(3), HDFGRTR, DBGWCRn_EL1, 1), 1906 SR_FGT(SYS_DBGWCRn_EL1(4), HDFGRTR, DBGWCRn_EL1, 1), 1907 SR_FGT(SYS_DBGWCRn_EL1(5), HDFGRTR, DBGWCRn_EL1, 1), 1908 SR_FGT(SYS_DBGWCRn_EL1(6), HDFGRTR, DBGWCRn_EL1, 1), 1909 SR_FGT(SYS_DBGWCRn_EL1(7), HDFGRTR, DBGWCRn_EL1, 1), 1910 SR_FGT(SYS_DBGWCRn_EL1(8), HDFGRTR, DBGWCRn_EL1, 1), 1911 SR_FGT(SYS_DBGWCRn_EL1(9), HDFGRTR, DBGWCRn_EL1, 1), 1912 SR_FGT(SYS_DBGWCRn_EL1(10), HDFGRTR, DBGWCRn_EL1, 1), 1913 SR_FGT(SYS_DBGWCRn_EL1(11), HDFGRTR, DBGWCRn_EL1, 1), 1914 SR_FGT(SYS_DBGWCRn_EL1(12), HDFGRTR, DBGWCRn_EL1, 1), 1915 SR_FGT(SYS_DBGWCRn_EL1(13), HDFGRTR, DBGWCRn_EL1, 1), 1916 SR_FGT(SYS_DBGWCRn_EL1(14), HDFGRTR, DBGWCRn_EL1, 1), 1917 SR_FGT(SYS_DBGWCRn_EL1(15), HDFGRTR, DBGWCRn_EL1, 1), 1918 SR_FGT(SYS_DBGBVRn_EL1(0), HDFGRTR, DBGBVRn_EL1, 1), 1919 SR_FGT(SYS_DBGBVRn_EL1(1), HDFGRTR, DBGBVRn_EL1, 1), 1920 SR_FGT(SYS_DBGBVRn_EL1(2), HDFGRTR, DBGBVRn_EL1, 1), 1921 SR_FGT(SYS_DBGBVRn_EL1(3), HDFGRTR, DBGBVRn_EL1, 1), 1922 SR_FGT(SYS_DBGBVRn_EL1(4), HDFGRTR, DBGBVRn_EL1, 1), 1923 SR_FGT(SYS_DBGBVRn_EL1(5), HDFGRTR, DBGBVRn_EL1, 1), 1924 SR_FGT(SYS_DBGBVRn_EL1(6), HDFGRTR, DBGBVRn_EL1, 1), 1925 SR_FGT(SYS_DBGBVRn_EL1(7), HDFGRTR, DBGBVRn_EL1, 1), 1926 SR_FGT(SYS_DBGBVRn_EL1(8), HDFGRTR, DBGBVRn_EL1, 1), 1927 SR_FGT(SYS_DBGBVRn_EL1(9), HDFGRTR, DBGBVRn_EL1, 1), 1928 SR_FGT(SYS_DBGBVRn_EL1(10), HDFGRTR, DBGBVRn_EL1, 1), 1929 SR_FGT(SYS_DBGBVRn_EL1(11), HDFGRTR, DBGBVRn_EL1, 1), 1930 SR_FGT(SYS_DBGBVRn_EL1(12), HDFGRTR, DBGBVRn_EL1, 1), 1931 SR_FGT(SYS_DBGBVRn_EL1(13), HDFGRTR, DBGBVRn_EL1, 1), 1932 SR_FGT(SYS_DBGBVRn_EL1(14), HDFGRTR, DBGBVRn_EL1, 1), 1933 SR_FGT(SYS_DBGBVRn_EL1(15), HDFGRTR, DBGBVRn_EL1, 1), 1934 SR_FGT(SYS_DBGBCRn_EL1(0), HDFGRTR, DBGBCRn_EL1, 1), 1935 SR_FGT(SYS_DBGBCRn_EL1(1), HDFGRTR, DBGBCRn_EL1, 1), 1936 SR_FGT(SYS_DBGBCRn_EL1(2), HDFGRTR, DBGBCRn_EL1, 1), 1937 SR_FGT(SYS_DBGBCRn_EL1(3), HDFGRTR, DBGBCRn_EL1, 1), 1938 SR_FGT(SYS_DBGBCRn_EL1(4), HDFGRTR, DBGBCRn_EL1, 1), 1939 SR_FGT(SYS_DBGBCRn_EL1(5), HDFGRTR, DBGBCRn_EL1, 1), 1940 SR_FGT(SYS_DBGBCRn_EL1(6), HDFGRTR, DBGBCRn_EL1, 1), 1941 SR_FGT(SYS_DBGBCRn_EL1(7), HDFGRTR, DBGBCRn_EL1, 1), 1942 SR_FGT(SYS_DBGBCRn_EL1(8), HDFGRTR, DBGBCRn_EL1, 1), 1943 SR_FGT(SYS_DBGBCRn_EL1(9), HDFGRTR, DBGBCRn_EL1, 1), 1944 SR_FGT(SYS_DBGBCRn_EL1(10), HDFGRTR, DBGBCRn_EL1, 1), 1945 SR_FGT(SYS_DBGBCRn_EL1(11), HDFGRTR, DBGBCRn_EL1, 1), 1946 SR_FGT(SYS_DBGBCRn_EL1(12), HDFGRTR, DBGBCRn_EL1, 1), 1947 SR_FGT(SYS_DBGBCRn_EL1(13), HDFGRTR, DBGBCRn_EL1, 1), 1948 SR_FGT(SYS_DBGBCRn_EL1(14), HDFGRTR, DBGBCRn_EL1, 1), 1949 SR_FGT(SYS_DBGBCRn_EL1(15), HDFGRTR, DBGBCRn_EL1, 1), 1950 1951 /* HDFGRTR2_EL2 */ 1952 SR_FGT(SYS_MDSELR_EL1, HDFGRTR2, nMDSELR_EL1, 0), 1953 SR_FGT(SYS_MDSTEPOP_EL1, HDFGRTR2, nMDSTEPOP_EL1, 0), 1954 SR_FGT(SYS_PMCCNTSVR_EL1, HDFGRTR2, nPMSSDATA, 0), 1955 SR_FGT_RANGE(SYS_PMEVCNTSVRn_EL1(0), 1956 SYS_PMEVCNTSVRn_EL1(30), 1957 HDFGRTR2, nPMSSDATA, 0), 1958 SR_FGT(SYS_PMICNTSVR_EL1, HDFGRTR2, nPMSSDATA, 0), 1959 SR_FGT(SYS_PMECR_EL1, HDFGRTR2, nPMECR_EL1, 0), 1960 SR_FGT(SYS_PMIAR_EL1, HDFGRTR2, nPMIAR_EL1, 0), 1961 SR_FGT(SYS_PMICFILTR_EL0, HDFGRTR2, nPMICFILTR_EL0, 0), 1962 SR_FGT(SYS_PMICNTR_EL0, HDFGRTR2, nPMICNTR_EL0, 0), 1963 SR_FGT(SYS_PMSSCR_EL1, HDFGRTR2, nPMSSCR_EL1, 0), 1964 SR_FGT(SYS_PMUACR_EL1, HDFGRTR2, nPMUACR_EL1, 0), 1965 SR_FGT(SYS_SPMACCESSR_EL1, HDFGRTR2, nSPMACCESSR_EL1, 0), 1966 SR_FGT(SYS_SPMCFGR_EL1, HDFGRTR2, nSPMID, 0), 1967 SR_FGT(SYS_SPMDEVARCH_EL1, HDFGRTR2, nSPMID, 0), 1968 SR_FGT(SYS_SPMCGCRn_EL1(0), HDFGRTR2, nSPMID, 0), 1969 SR_FGT(SYS_SPMCGCRn_EL1(1), HDFGRTR2, nSPMID, 0), 1970 SR_FGT(SYS_SPMIIDR_EL1, HDFGRTR2, nSPMID, 0), 1971 SR_FGT(SYS_SPMCNTENCLR_EL0, HDFGRTR2, nSPMCNTEN, 0), 1972 SR_FGT(SYS_SPMCNTENSET_EL0, HDFGRTR2, nSPMCNTEN, 0), 1973 SR_FGT(SYS_SPMCR_EL0, HDFGRTR2, nSPMCR_EL0, 0), 1974 SR_FGT(SYS_SPMDEVAFF_EL1, HDFGRTR2, nSPMDEVAFF_EL1, 0), 1975 /* 1976 * We have up to 64 of these registers in ranges of 16, banked via 1977 * SPMSELR_EL0.BANK. We're only concerned with the accessors here, 1978 * not the architectural registers. 1979 */ 1980 SR_FGT_RANGE(SYS_SPMEVCNTRn_EL0(0), 1981 SYS_SPMEVCNTRn_EL0(15), 1982 HDFGRTR2, nSPMEVCNTRn_EL0, 0), 1983 SR_FGT_RANGE(SYS_SPMEVFILT2Rn_EL0(0), 1984 SYS_SPMEVFILT2Rn_EL0(15), 1985 HDFGRTR2, nSPMEVTYPERn_EL0, 0), 1986 SR_FGT_RANGE(SYS_SPMEVFILTRn_EL0(0), 1987 SYS_SPMEVFILTRn_EL0(15), 1988 HDFGRTR2, nSPMEVTYPERn_EL0, 0), 1989 SR_FGT_RANGE(SYS_SPMEVTYPERn_EL0(0), 1990 SYS_SPMEVTYPERn_EL0(15), 1991 HDFGRTR2, nSPMEVTYPERn_EL0, 0), 1992 SR_FGT(SYS_SPMINTENCLR_EL1, HDFGRTR2, nSPMINTEN, 0), 1993 SR_FGT(SYS_SPMINTENSET_EL1, HDFGRTR2, nSPMINTEN, 0), 1994 SR_FGT(SYS_SPMOVSCLR_EL0, HDFGRTR2, nSPMOVS, 0), 1995 SR_FGT(SYS_SPMOVSSET_EL0, HDFGRTR2, nSPMOVS, 0), 1996 SR_FGT(SYS_SPMSCR_EL1, HDFGRTR2, nSPMSCR_EL1, 0), 1997 SR_FGT(SYS_SPMSELR_EL0, HDFGRTR2, nSPMSELR_EL0, 0), 1998 SR_FGT(SYS_TRCITECR_EL1, HDFGRTR2, nTRCITECR_EL1, 0), 1999 SR_FGT(SYS_PMBMAR_EL1, HDFGRTR2, nPMBMAR_EL1, 0), 2000 SR_FGT(SYS_PMSDSFR_EL1, HDFGRTR2, nPMSDSFR_EL1, 0), 2001 SR_FGT(SYS_TRBMPAM_EL1, HDFGRTR2, nTRBMPAM_EL1, 0), 2002 2003 /* 2004 * HDFGWTR_EL2 2005 * 2006 * Although HDFGRTR_EL2 and HDFGWTR_EL2 registers largely 2007 * overlap in their bit assignment, there are a number of bits 2008 * that are RES0 on one side, and an actual trap bit on the 2009 * other. The policy chosen here is to describe all the 2010 * read-side mappings, and only the write-side mappings that 2011 * differ from the read side, and the trap handler will pick 2012 * the correct shadow register based on the access type. 2013 * 2014 * Same model applies to the FEAT_FGT2 registers. 2015 */ 2016 SR_FGT(SYS_TRFCR_EL1, HDFGWTR, TRFCR_EL1, 1), 2017 SR_FGT(SYS_TRCOSLAR, HDFGWTR, TRCOSLAR, 1), 2018 SR_FGT(SYS_PMCR_EL0, HDFGWTR, PMCR_EL0, 1), 2019 SR_FGT(SYS_PMSWINC_EL0, HDFGWTR, PMSWINC_EL0, 1), 2020 SR_FGT(SYS_OSLAR_EL1, HDFGWTR, OSLAR_EL1, 1), 2021 2022 /* HDFGWTR2_EL2 */ 2023 SR_FGT(SYS_PMZR_EL0, HDFGWTR2, nPMZR_EL0, 0), 2024 SR_FGT(SYS_SPMZR_EL0, HDFGWTR2, nSPMEVCNTRn_EL0, 0), 2025 2026 /* 2027 * HAFGRTR_EL2 2028 */ 2029 SR_FGT(SYS_AMEVTYPER1_EL0(15), HAFGRTR, AMEVTYPER115_EL0, 1), 2030 SR_FGT(SYS_AMEVTYPER1_EL0(14), HAFGRTR, AMEVTYPER114_EL0, 1), 2031 SR_FGT(SYS_AMEVTYPER1_EL0(13), HAFGRTR, AMEVTYPER113_EL0, 1), 2032 SR_FGT(SYS_AMEVTYPER1_EL0(12), HAFGRTR, AMEVTYPER112_EL0, 1), 2033 SR_FGT(SYS_AMEVTYPER1_EL0(11), HAFGRTR, AMEVTYPER111_EL0, 1), 2034 SR_FGT(SYS_AMEVTYPER1_EL0(10), HAFGRTR, AMEVTYPER110_EL0, 1), 2035 SR_FGT(SYS_AMEVTYPER1_EL0(9), HAFGRTR, AMEVTYPER19_EL0, 1), 2036 SR_FGT(SYS_AMEVTYPER1_EL0(8), HAFGRTR, AMEVTYPER18_EL0, 1), 2037 SR_FGT(SYS_AMEVTYPER1_EL0(7), HAFGRTR, AMEVTYPER17_EL0, 1), 2038 SR_FGT(SYS_AMEVTYPER1_EL0(6), HAFGRTR, AMEVTYPER16_EL0, 1), 2039 SR_FGT(SYS_AMEVTYPER1_EL0(5), HAFGRTR, AMEVTYPER15_EL0, 1), 2040 SR_FGT(SYS_AMEVTYPER1_EL0(4), HAFGRTR, AMEVTYPER14_EL0, 1), 2041 SR_FGT(SYS_AMEVTYPER1_EL0(3), HAFGRTR, AMEVTYPER13_EL0, 1), 2042 SR_FGT(SYS_AMEVTYPER1_EL0(2), HAFGRTR, AMEVTYPER12_EL0, 1), 2043 SR_FGT(SYS_AMEVTYPER1_EL0(1), HAFGRTR, AMEVTYPER11_EL0, 1), 2044 SR_FGT(SYS_AMEVTYPER1_EL0(0), HAFGRTR, AMEVTYPER10_EL0, 1), 2045 SR_FGT(SYS_AMEVCNTR1_EL0(15), HAFGRTR, AMEVCNTR115_EL0, 1), 2046 SR_FGT(SYS_AMEVCNTR1_EL0(14), HAFGRTR, AMEVCNTR114_EL0, 1), 2047 SR_FGT(SYS_AMEVCNTR1_EL0(13), HAFGRTR, AMEVCNTR113_EL0, 1), 2048 SR_FGT(SYS_AMEVCNTR1_EL0(12), HAFGRTR, AMEVCNTR112_EL0, 1), 2049 SR_FGT(SYS_AMEVCNTR1_EL0(11), HAFGRTR, AMEVCNTR111_EL0, 1), 2050 SR_FGT(SYS_AMEVCNTR1_EL0(10), HAFGRTR, AMEVCNTR110_EL0, 1), 2051 SR_FGT(SYS_AMEVCNTR1_EL0(9), HAFGRTR, AMEVCNTR19_EL0, 1), 2052 SR_FGT(SYS_AMEVCNTR1_EL0(8), HAFGRTR, AMEVCNTR18_EL0, 1), 2053 SR_FGT(SYS_AMEVCNTR1_EL0(7), HAFGRTR, AMEVCNTR17_EL0, 1), 2054 SR_FGT(SYS_AMEVCNTR1_EL0(6), HAFGRTR, AMEVCNTR16_EL0, 1), 2055 SR_FGT(SYS_AMEVCNTR1_EL0(5), HAFGRTR, AMEVCNTR15_EL0, 1), 2056 SR_FGT(SYS_AMEVCNTR1_EL0(4), HAFGRTR, AMEVCNTR14_EL0, 1), 2057 SR_FGT(SYS_AMEVCNTR1_EL0(3), HAFGRTR, AMEVCNTR13_EL0, 1), 2058 SR_FGT(SYS_AMEVCNTR1_EL0(2), HAFGRTR, AMEVCNTR12_EL0, 1), 2059 SR_FGT(SYS_AMEVCNTR1_EL0(1), HAFGRTR, AMEVCNTR11_EL0, 1), 2060 SR_FGT(SYS_AMEVCNTR1_EL0(0), HAFGRTR, AMEVCNTR10_EL0, 1), 2061 SR_FGT(SYS_AMCNTENCLR1_EL0, HAFGRTR, AMCNTEN1, 1), 2062 SR_FGT(SYS_AMCNTENSET1_EL0, HAFGRTR, AMCNTEN1, 1), 2063 SR_FGT(SYS_AMCNTENCLR0_EL0, HAFGRTR, AMCNTEN0, 1), 2064 SR_FGT(SYS_AMCNTENSET0_EL0, HAFGRTR, AMCNTEN0, 1), 2065 SR_FGT(SYS_AMEVCNTR0_EL0(3), HAFGRTR, AMEVCNTR03_EL0, 1), 2066 SR_FGT(SYS_AMEVCNTR0_EL0(2), HAFGRTR, AMEVCNTR02_EL0, 1), 2067 SR_FGT(SYS_AMEVCNTR0_EL0(1), HAFGRTR, AMEVCNTR01_EL0, 1), 2068 SR_FGT(SYS_AMEVCNTR0_EL0(0), HAFGRTR, AMEVCNTR00_EL0, 1), 2069 2070 /* 2071 * ICH_HFGRTR_EL2 & ICH_HFGWTR_EL2 2072 */ 2073 SR_FGT(SYS_ICC_APR_EL1, ICH_HFGRTR, ICC_APR_EL1, 0), 2074 SR_FGT(SYS_ICC_IDR0_EL1, ICH_HFGRTR, ICC_IDRn_EL1, 0), 2075 SR_FGT(SYS_ICC_CR0_EL1, ICH_HFGRTR, ICC_CR0_EL1, 0), 2076 SR_FGT(SYS_ICC_HPPIR_EL1, ICH_HFGRTR, ICC_HPPIR_EL1, 0), 2077 SR_FGT(SYS_ICC_PCR_EL1, ICH_HFGRTR, ICC_PCR_EL1, 0), 2078 SR_FGT(SYS_ICC_ICSR_EL1, ICH_HFGRTR, ICC_ICSR_EL1, 0), 2079 SR_FGT(SYS_ICC_IAFFIDR_EL1, ICH_HFGRTR, ICC_IAFFIDR_EL1, 0), 2080 SR_FGT(SYS_ICC_PPI_HMR0_EL1, ICH_HFGRTR, ICC_PPI_HMRn_EL1, 0), 2081 SR_FGT(SYS_ICC_PPI_HMR1_EL1, ICH_HFGRTR, ICC_PPI_HMRn_EL1, 0), 2082 SR_FGT(SYS_ICC_PPI_ENABLER0_EL1, ICH_HFGRTR, ICC_PPI_ENABLERn_EL1, 0), 2083 SR_FGT(SYS_ICC_PPI_ENABLER1_EL1, ICH_HFGRTR, ICC_PPI_ENABLERn_EL1, 0), 2084 SR_FGT(SYS_ICC_PPI_CPENDR0_EL1, ICH_HFGRTR, ICC_PPI_PENDRn_EL1, 0), 2085 SR_FGT(SYS_ICC_PPI_CPENDR1_EL1, ICH_HFGRTR, ICC_PPI_PENDRn_EL1, 0), 2086 SR_FGT(SYS_ICC_PPI_SPENDR0_EL1, ICH_HFGRTR, ICC_PPI_PENDRn_EL1, 0), 2087 SR_FGT(SYS_ICC_PPI_SPENDR1_EL1, ICH_HFGRTR, ICC_PPI_PENDRn_EL1, 0), 2088 SR_FGT(SYS_ICC_PPI_PRIORITYR0_EL1, ICH_HFGRTR, ICC_PPI_PRIORITYRn_EL1, 0), 2089 SR_FGT(SYS_ICC_PPI_PRIORITYR1_EL1, ICH_HFGRTR, ICC_PPI_PRIORITYRn_EL1, 0), 2090 SR_FGT(SYS_ICC_PPI_PRIORITYR2_EL1, ICH_HFGRTR, ICC_PPI_PRIORITYRn_EL1, 0), 2091 SR_FGT(SYS_ICC_PPI_PRIORITYR3_EL1, ICH_HFGRTR, ICC_PPI_PRIORITYRn_EL1, 0), 2092 SR_FGT(SYS_ICC_PPI_PRIORITYR4_EL1, ICH_HFGRTR, ICC_PPI_PRIORITYRn_EL1, 0), 2093 SR_FGT(SYS_ICC_PPI_PRIORITYR5_EL1, ICH_HFGRTR, ICC_PPI_PRIORITYRn_EL1, 0), 2094 SR_FGT(SYS_ICC_PPI_PRIORITYR6_EL1, ICH_HFGRTR, ICC_PPI_PRIORITYRn_EL1, 0), 2095 SR_FGT(SYS_ICC_PPI_PRIORITYR7_EL1, ICH_HFGRTR, ICC_PPI_PRIORITYRn_EL1, 0), 2096 SR_FGT(SYS_ICC_PPI_PRIORITYR8_EL1, ICH_HFGRTR, ICC_PPI_PRIORITYRn_EL1, 0), 2097 SR_FGT(SYS_ICC_PPI_PRIORITYR9_EL1, ICH_HFGRTR, ICC_PPI_PRIORITYRn_EL1, 0), 2098 SR_FGT(SYS_ICC_PPI_PRIORITYR10_EL1, ICH_HFGRTR, ICC_PPI_PRIORITYRn_EL1, 0), 2099 SR_FGT(SYS_ICC_PPI_PRIORITYR11_EL1, ICH_HFGRTR, ICC_PPI_PRIORITYRn_EL1, 0), 2100 SR_FGT(SYS_ICC_PPI_PRIORITYR12_EL1, ICH_HFGRTR, ICC_PPI_PRIORITYRn_EL1, 0), 2101 SR_FGT(SYS_ICC_PPI_PRIORITYR13_EL1, ICH_HFGRTR, ICC_PPI_PRIORITYRn_EL1, 0), 2102 SR_FGT(SYS_ICC_PPI_PRIORITYR14_EL1, ICH_HFGRTR, ICC_PPI_PRIORITYRn_EL1, 0), 2103 SR_FGT(SYS_ICC_PPI_PRIORITYR15_EL1, ICH_HFGRTR, ICC_PPI_PRIORITYRn_EL1, 0), 2104 SR_FGT(SYS_ICC_PPI_CACTIVER0_EL1, ICH_HFGRTR, ICC_PPI_ACTIVERn_EL1, 0), 2105 SR_FGT(SYS_ICC_PPI_CACTIVER1_EL1, ICH_HFGRTR, ICC_PPI_ACTIVERn_EL1, 0), 2106 SR_FGT(SYS_ICC_PPI_SACTIVER0_EL1, ICH_HFGRTR, ICC_PPI_ACTIVERn_EL1, 0), 2107 SR_FGT(SYS_ICC_PPI_SACTIVER1_EL1, ICH_HFGRTR, ICC_PPI_ACTIVERn_EL1, 0), 2108 2109 /* 2110 * ICH_HFGITR_EL2 2111 */ 2112 SR_FGT(GICV5_OP_GIC_CDEN, ICH_HFGITR, GICCDEN, 0), 2113 SR_FGT(GICV5_OP_GIC_CDDIS, ICH_HFGITR, GICCDDIS, 0), 2114 SR_FGT(GICV5_OP_GIC_CDPRI, ICH_HFGITR, GICCDPRI, 0), 2115 SR_FGT(GICV5_OP_GIC_CDAFF, ICH_HFGITR, GICCDAFF, 0), 2116 SR_FGT(GICV5_OP_GIC_CDPEND, ICH_HFGITR, GICCDPEND, 0), 2117 SR_FGT(GICV5_OP_GIC_CDRCFG, ICH_HFGITR, GICCDRCFG, 0), 2118 SR_FGT(GICV5_OP_GIC_CDHM, ICH_HFGITR, GICCDHM, 0), 2119 SR_FGT(GICV5_OP_GIC_CDEOI, ICH_HFGITR, GICCDEOI, 0), 2120 SR_FGT(GICV5_OP_GIC_CDDI, ICH_HFGITR, GICCDDI, 0), 2121 SR_FGT(GICV5_OP_GICR_CDIA, ICH_HFGITR, GICRCDIA, 0), 2122 SR_FGT(GICV5_OP_GICR_CDNMIA, ICH_HFGITR, GICRCDNMIA, 0), 2123 }; 2124 2125 /* 2126 * Additional FGTs that do not fire with ESR_EL2.EC==0x18. This table 2127 * isn't used for exception routing, but only as a promise that the 2128 * trap is handled somewhere else. 2129 */ 2130 static const union trap_config non_0x18_fgt[] __initconst = { 2131 FGT(HFGITR, PSBCSYNC, 1), 2132 FGT(HFGITR, nGCSSTR_EL1, 0), 2133 FGT(HFGITR, SVC_EL1, 1), 2134 FGT(HFGITR, SVC_EL0, 1), 2135 FGT(HFGITR, ERET, 1), 2136 FGT(HFGITR2, TSBCSYNC, 1), 2137 }; 2138 2139 static union trap_config get_trap_config(u32 sysreg) 2140 { 2141 return (union trap_config) { 2142 .val = xa_to_value(xa_load(&sr_forward_xa, sysreg)), 2143 }; 2144 } 2145 2146 static __init void print_nv_trap_error(const struct encoding_to_trap_config *tc, 2147 const char *type, int err) 2148 { 2149 kvm_err("%s line %d encoding range " 2150 "(%d, %d, %d, %d, %d) - (%d, %d, %d, %d, %d) (err=%d)\n", 2151 type, tc->line, 2152 sys_reg_Op0(tc->encoding), sys_reg_Op1(tc->encoding), 2153 sys_reg_CRn(tc->encoding), sys_reg_CRm(tc->encoding), 2154 sys_reg_Op2(tc->encoding), 2155 sys_reg_Op0(tc->end), sys_reg_Op1(tc->end), 2156 sys_reg_CRn(tc->end), sys_reg_CRm(tc->end), 2157 sys_reg_Op2(tc->end), 2158 err); 2159 } 2160 2161 static u32 encoding_next(u32 encoding) 2162 { 2163 u8 op0, op1, crn, crm, op2; 2164 2165 op0 = sys_reg_Op0(encoding); 2166 op1 = sys_reg_Op1(encoding); 2167 crn = sys_reg_CRn(encoding); 2168 crm = sys_reg_CRm(encoding); 2169 op2 = sys_reg_Op2(encoding); 2170 2171 if (op2 < Op2_mask) 2172 return sys_reg(op0, op1, crn, crm, op2 + 1); 2173 if (crm < CRm_mask) 2174 return sys_reg(op0, op1, crn, crm + 1, 0); 2175 if (crn < CRn_mask) 2176 return sys_reg(op0, op1, crn + 1, 0, 0); 2177 if (op1 < Op1_mask) 2178 return sys_reg(op0, op1 + 1, 0, 0, 0); 2179 2180 return sys_reg(op0 + 1, 0, 0, 0, 0); 2181 } 2182 2183 #define FGT_MASKS(__n, __m) \ 2184 struct fgt_masks __n = { .str = #__m, .res0 = __m ## _RES0, .res1 = __m ## _RES1 } 2185 2186 FGT_MASKS(hfgrtr_masks, HFGRTR_EL2); 2187 FGT_MASKS(hfgwtr_masks, HFGWTR_EL2); 2188 FGT_MASKS(hfgitr_masks, HFGITR_EL2); 2189 FGT_MASKS(hdfgrtr_masks, HDFGRTR_EL2); 2190 FGT_MASKS(hdfgwtr_masks, HDFGWTR_EL2); 2191 FGT_MASKS(hafgrtr_masks, HAFGRTR_EL2); 2192 FGT_MASKS(hfgrtr2_masks, HFGRTR2_EL2); 2193 FGT_MASKS(hfgwtr2_masks, HFGWTR2_EL2); 2194 FGT_MASKS(hfgitr2_masks, HFGITR2_EL2); 2195 FGT_MASKS(hdfgrtr2_masks, HDFGRTR2_EL2); 2196 FGT_MASKS(hdfgwtr2_masks, HDFGWTR2_EL2); 2197 FGT_MASKS(ich_hfgrtr_masks, ICH_HFGRTR_EL2); 2198 FGT_MASKS(ich_hfgwtr_masks, ICH_HFGWTR_EL2); 2199 FGT_MASKS(ich_hfgitr_masks, ICH_HFGITR_EL2); 2200 2201 static __init bool aggregate_fgt(union trap_config tc) 2202 { 2203 struct fgt_masks *rmasks, *wmasks; 2204 u64 rresx, wresx; 2205 2206 switch (tc.fgt) { 2207 case HFGRTR_GROUP: 2208 rmasks = &hfgrtr_masks; 2209 wmasks = &hfgwtr_masks; 2210 break; 2211 case HDFGRTR_GROUP: 2212 rmasks = &hdfgrtr_masks; 2213 wmasks = &hdfgwtr_masks; 2214 break; 2215 case HAFGRTR_GROUP: 2216 rmasks = &hafgrtr_masks; 2217 wmasks = NULL; 2218 break; 2219 case HFGITR_GROUP: 2220 rmasks = &hfgitr_masks; 2221 wmasks = NULL; 2222 break; 2223 case HFGRTR2_GROUP: 2224 rmasks = &hfgrtr2_masks; 2225 wmasks = &hfgwtr2_masks; 2226 break; 2227 case HDFGRTR2_GROUP: 2228 rmasks = &hdfgrtr2_masks; 2229 wmasks = &hdfgwtr2_masks; 2230 break; 2231 case HFGITR2_GROUP: 2232 rmasks = &hfgitr2_masks; 2233 wmasks = NULL; 2234 break; 2235 case ICH_HFGRTR_GROUP: 2236 rmasks = &ich_hfgrtr_masks; 2237 wmasks = &ich_hfgwtr_masks; 2238 break; 2239 case ICH_HFGITR_GROUP: 2240 rmasks = &ich_hfgitr_masks; 2241 wmasks = NULL; 2242 break; 2243 } 2244 2245 rresx = rmasks->res0 | rmasks->res1; 2246 if (wmasks) 2247 wresx = wmasks->res0 | wmasks->res1; 2248 2249 /* 2250 * A bit can be reserved in either the R or W register, but 2251 * not both. 2252 */ 2253 if ((BIT(tc.bit) & rresx) && (!wmasks || (BIT(tc.bit) & wresx))) 2254 return false; 2255 2256 if (tc.pol) 2257 rmasks->mask |= BIT(tc.bit) & ~rresx; 2258 else 2259 rmasks->nmask |= BIT(tc.bit) & ~rresx; 2260 2261 if (wmasks) { 2262 if (tc.pol) 2263 wmasks->mask |= BIT(tc.bit) & ~wresx; 2264 else 2265 wmasks->nmask |= BIT(tc.bit) & ~wresx; 2266 } 2267 2268 return true; 2269 } 2270 2271 static __init int check_fgt_masks(struct fgt_masks *masks) 2272 { 2273 unsigned long duplicate = masks->mask & masks->nmask; 2274 int ret = 0; 2275 2276 if (duplicate) { 2277 int i; 2278 2279 for_each_set_bit(i, &duplicate, 64) { 2280 kvm_err("%s[%d] bit has both polarities\n", 2281 masks->str, i); 2282 } 2283 2284 ret = -EINVAL; 2285 } 2286 2287 if ((masks->res0 | masks->res1 | masks->mask | masks->nmask) != GENMASK(63, 0) || 2288 (masks->res0 & masks->res1) || (masks->res0 & masks->mask) || 2289 (masks->res0 & masks->nmask) || (masks->res1 & masks->mask) || 2290 (masks->res1 & masks->nmask) || (masks->mask & masks->nmask)) { 2291 kvm_info("Inconsistent masks for %s (%016llx, %016llx, %016llx, %016llx)\n", 2292 masks->str, masks->res0, masks->res1, masks->mask, masks->nmask); 2293 masks->res0 = ~(masks->res1 | masks->mask | masks->nmask); 2294 } 2295 2296 return ret; 2297 } 2298 2299 static __init int check_all_fgt_masks(int ret) 2300 { 2301 static struct fgt_masks * const masks[] __initconst = { 2302 &hfgrtr_masks, 2303 &hfgwtr_masks, 2304 &hfgitr_masks, 2305 &hdfgrtr_masks, 2306 &hdfgwtr_masks, 2307 &hafgrtr_masks, 2308 &hfgrtr2_masks, 2309 &hfgwtr2_masks, 2310 &hfgitr2_masks, 2311 &hdfgrtr2_masks, 2312 &hdfgwtr2_masks, 2313 &ich_hfgrtr_masks, 2314 &ich_hfgwtr_masks, 2315 &ich_hfgitr_masks, 2316 }; 2317 int err = 0; 2318 2319 for (int i = 0; i < ARRAY_SIZE(masks); i++) 2320 err |= check_fgt_masks(masks[i]); 2321 2322 return ret ?: err; 2323 } 2324 2325 #define for_each_encoding_in(__x, __s, __e) \ 2326 for (u32 __x = __s; __x <= __e; __x = encoding_next(__x)) 2327 2328 int __init populate_nv_trap_config(void) 2329 { 2330 int ret = 0; 2331 2332 BUILD_BUG_ON(sizeof(union trap_config) != sizeof(void *)); 2333 BUILD_BUG_ON(__NR_CGT_GROUP_IDS__ > BIT(TC_CGT_BITS)); 2334 BUILD_BUG_ON(__NR_FGT_GROUP_IDS__ > BIT(TC_FGT_BITS)); 2335 BUILD_BUG_ON(__NR_FG_FILTER_IDS__ > BIT(TC_FGF_BITS)); 2336 2337 for (int i = 0; i < ARRAY_SIZE(encoding_to_cgt); i++) { 2338 const struct encoding_to_trap_config *cgt = &encoding_to_cgt[i]; 2339 void *prev; 2340 2341 if (cgt->tc.val & BIT(63)) { 2342 kvm_err("CGT[%d] has MBZ bit set\n", i); 2343 ret = -EINVAL; 2344 } 2345 2346 for_each_encoding_in(enc, cgt->encoding, cgt->end) { 2347 prev = xa_store(&sr_forward_xa, enc, 2348 xa_mk_value(cgt->tc.val), GFP_KERNEL); 2349 if (prev && !xa_is_err(prev)) { 2350 ret = -EINVAL; 2351 print_nv_trap_error(cgt, "Duplicate CGT", ret); 2352 } 2353 2354 if (xa_is_err(prev)) { 2355 ret = xa_err(prev); 2356 print_nv_trap_error(cgt, "Failed CGT insertion", ret); 2357 } 2358 } 2359 } 2360 2361 kvm_info("nv: %ld coarse grained trap handlers\n", 2362 ARRAY_SIZE(encoding_to_cgt)); 2363 2364 for (int i = 0; i < ARRAY_SIZE(encoding_to_fgt); i++) { 2365 const struct encoding_to_trap_config *fgt = &encoding_to_fgt[i]; 2366 union trap_config tc; 2367 void *prev; 2368 2369 if (fgt->tc.fgt >= __NR_FGT_GROUP_IDS__) { 2370 ret = -EINVAL; 2371 print_nv_trap_error(fgt, "Invalid FGT", ret); 2372 } 2373 2374 for_each_encoding_in(enc, fgt->encoding, fgt->end) { 2375 tc = get_trap_config(enc); 2376 2377 if (tc.fgt) { 2378 ret = -EINVAL; 2379 print_nv_trap_error(fgt, "Duplicate FGT", ret); 2380 } 2381 2382 tc.val |= fgt->tc.val; 2383 2384 if (!aggregate_fgt(tc)) { 2385 ret = -EINVAL; 2386 print_nv_trap_error(fgt, "FGT bit is reserved", ret); 2387 } 2388 2389 if (!cpus_have_final_cap(ARM64_HAS_FGT)) 2390 continue; 2391 2392 prev = xa_store(&sr_forward_xa, enc, 2393 xa_mk_value(tc.val), GFP_KERNEL); 2394 2395 if (xa_is_err(prev)) { 2396 ret = xa_err(prev); 2397 print_nv_trap_error(fgt, "Failed FGT insertion", ret); 2398 } 2399 } 2400 } 2401 2402 for (int i = 0; i < ARRAY_SIZE(non_0x18_fgt); i++) { 2403 if (!aggregate_fgt(non_0x18_fgt[i])) { 2404 ret = -EINVAL; 2405 kvm_err("non_0x18_fgt[%d] is reserved\n", i); 2406 } 2407 } 2408 2409 ret = check_all_fgt_masks(ret); 2410 2411 kvm_info("nv: %ld fine grained trap handlers\n", 2412 ARRAY_SIZE(encoding_to_fgt)); 2413 2414 for (int id = __MULTIPLE_CONTROL_BITS__; id < __COMPLEX_CONDITIONS__; id++) { 2415 const enum cgt_group_id *cgids; 2416 2417 cgids = coarse_control_combo[id - __MULTIPLE_CONTROL_BITS__]; 2418 2419 for (int i = 0; cgids[i] != __RESERVED__; i++) { 2420 if (cgids[i] >= __MULTIPLE_CONTROL_BITS__ && 2421 cgids[i] < __COMPLEX_CONDITIONS__) { 2422 kvm_err("Recursive MCB %d/%d\n", id, cgids[i]); 2423 ret = -EINVAL; 2424 } 2425 } 2426 } 2427 2428 if (ret) 2429 xa_destroy(&sr_forward_xa); 2430 2431 return ret; 2432 } 2433 2434 int __init populate_sysreg_config(const struct sys_reg_desc *sr, 2435 unsigned int idx) 2436 { 2437 union trap_config tc; 2438 u32 encoding; 2439 void *ret; 2440 2441 /* 2442 * 0 is a valid value for the index, but not for the storage. 2443 * We'll store (idx+1), so check against an offset'd limit. 2444 */ 2445 if (idx >= (BIT(TC_SRI_BITS) - 1)) { 2446 kvm_err("sysreg %s (%d) out of range\n", sr->name, idx); 2447 return -EINVAL; 2448 } 2449 2450 encoding = sys_reg(sr->Op0, sr->Op1, sr->CRn, sr->CRm, sr->Op2); 2451 tc = get_trap_config(encoding); 2452 2453 if (tc.sri) { 2454 kvm_err("sysreg %s (%d) duplicate entry (%d)\n", 2455 sr->name, idx - 1, tc.sri); 2456 return -EINVAL; 2457 } 2458 2459 tc.sri = idx + 1; 2460 ret = xa_store(&sr_forward_xa, encoding, 2461 xa_mk_value(tc.val), GFP_KERNEL); 2462 2463 return xa_err(ret); 2464 } 2465 2466 static enum trap_behaviour get_behaviour(struct kvm_vcpu *vcpu, 2467 const struct trap_bits *tb) 2468 { 2469 enum trap_behaviour b = BEHAVE_HANDLE_LOCALLY; 2470 u64 val; 2471 2472 val = __vcpu_sys_reg(vcpu, tb->index); 2473 if ((val & tb->mask) == tb->value) 2474 b |= tb->behaviour; 2475 2476 return b; 2477 } 2478 2479 static enum trap_behaviour __compute_trap_behaviour(struct kvm_vcpu *vcpu, 2480 const enum cgt_group_id id, 2481 enum trap_behaviour b) 2482 { 2483 switch (id) { 2484 const enum cgt_group_id *cgids; 2485 2486 case __RESERVED__ ... __MULTIPLE_CONTROL_BITS__ - 1: 2487 if (likely(id != __RESERVED__)) 2488 b |= get_behaviour(vcpu, &coarse_trap_bits[id]); 2489 break; 2490 case __MULTIPLE_CONTROL_BITS__ ... __COMPLEX_CONDITIONS__ - 1: 2491 /* Yes, this is recursive. Don't do anything stupid. */ 2492 cgids = coarse_control_combo[id - __MULTIPLE_CONTROL_BITS__]; 2493 for (int i = 0; cgids[i] != __RESERVED__; i++) 2494 b |= __compute_trap_behaviour(vcpu, cgids[i], b); 2495 break; 2496 default: 2497 if (ARRAY_SIZE(ccc)) 2498 b |= ccc[id - __COMPLEX_CONDITIONS__](vcpu); 2499 break; 2500 } 2501 2502 return b; 2503 } 2504 2505 static enum trap_behaviour compute_trap_behaviour(struct kvm_vcpu *vcpu, 2506 const union trap_config tc) 2507 { 2508 enum trap_behaviour b = BEHAVE_HANDLE_LOCALLY; 2509 2510 return __compute_trap_behaviour(vcpu, tc.cgt, b); 2511 } 2512 2513 static u64 kvm_get_sysreg_res0(struct kvm *kvm, enum vcpu_sysreg sr) 2514 { 2515 return kvm_get_sysreg_resx(kvm, sr).res0; 2516 } 2517 2518 static bool check_fgt_bit(struct kvm_vcpu *vcpu, enum vcpu_sysreg sr, 2519 const union trap_config tc) 2520 { 2521 struct kvm *kvm = vcpu->kvm; 2522 u64 val; 2523 2524 /* 2525 * KVM doesn't know about any FGTs that apply to the host, and hopefully 2526 * that'll remain the case. 2527 */ 2528 if (is_hyp_ctxt(vcpu)) 2529 return false; 2530 2531 val = __vcpu_sys_reg(vcpu, sr); 2532 2533 if (tc.pol) 2534 return (val & BIT(tc.bit)); 2535 2536 /* 2537 * FGTs with negative polarities are an absolute nightmare, as 2538 * we need to evaluate the bit in the light of the feature 2539 * that defines it. WTF were they thinking? 2540 * 2541 * So let's check if the bit has been earmarked as RES0, as 2542 * this indicates an unimplemented feature. 2543 */ 2544 if (val & BIT(tc.bit)) 2545 return false; 2546 2547 return !(kvm_get_sysreg_res0(kvm, sr) & BIT(tc.bit)); 2548 } 2549 2550 bool triage_sysreg_trap(struct kvm_vcpu *vcpu, int *sr_index) 2551 { 2552 enum vcpu_sysreg fgtreg; 2553 union trap_config tc; 2554 enum trap_behaviour b; 2555 bool is_read; 2556 u32 sysreg; 2557 u64 esr; 2558 2559 esr = kvm_vcpu_get_esr(vcpu); 2560 sysreg = esr_sys64_to_sysreg(esr); 2561 is_read = (esr & ESR_ELx_SYS64_ISS_DIR_MASK) == ESR_ELx_SYS64_ISS_DIR_READ; 2562 2563 tc = get_trap_config(sysreg); 2564 2565 /* 2566 * A value of 0 for the whole entry means that we know nothing 2567 * for this sysreg, and that it cannot be re-injected into the 2568 * nested hypervisor. In this situation, let's cut it short. 2569 */ 2570 if (!tc.val) 2571 goto local; 2572 2573 /* 2574 * If a sysreg can be trapped using a FGT, first check whether we 2575 * trap for the purpose of forbidding the feature. In that case, 2576 * inject an UNDEF. 2577 */ 2578 if (tc.fgt != __NO_FGT_GROUP__ && 2579 (vcpu->kvm->arch.fgu[tc.fgt] & BIT(tc.bit))) { 2580 kvm_inject_undefined(vcpu); 2581 return true; 2582 } 2583 2584 /* 2585 * If we're not nesting, immediately return to the caller, with the 2586 * sysreg index, should we have it. 2587 */ 2588 if (!vcpu_has_nv(vcpu)) 2589 goto local; 2590 2591 /* 2592 * There are a few traps that take effect InHost, but are constrained 2593 * to EL0. Don't bother with computing the trap behaviour if the vCPU 2594 * isn't in EL0. 2595 */ 2596 if (is_hyp_ctxt(vcpu) && !vcpu_is_host_el0(vcpu)) 2597 goto local; 2598 2599 switch ((enum fgt_group_id)tc.fgt) { 2600 case __NO_FGT_GROUP__: 2601 break; 2602 2603 case HFGRTR_GROUP: 2604 fgtreg = is_read ? HFGRTR_EL2 : HFGWTR_EL2; 2605 break; 2606 2607 case HDFGRTR_GROUP: 2608 fgtreg = is_read ? HDFGRTR_EL2 : HDFGWTR_EL2; 2609 break; 2610 2611 case HAFGRTR_GROUP: 2612 fgtreg = HAFGRTR_EL2; 2613 break; 2614 2615 case HFGITR_GROUP: 2616 fgtreg = HFGITR_EL2; 2617 switch (tc.fgf) { 2618 u64 tmp; 2619 2620 case __NO_FGF__: 2621 break; 2622 2623 case HCRX_FGTnXS: 2624 tmp = __vcpu_sys_reg(vcpu, HCRX_EL2); 2625 if (tmp & HCRX_EL2_FGTnXS) 2626 tc.fgt = __NO_FGT_GROUP__; 2627 } 2628 break; 2629 2630 case HFGRTR2_GROUP: 2631 fgtreg = is_read ? HFGRTR2_EL2 : HFGWTR2_EL2; 2632 break; 2633 2634 case HDFGRTR2_GROUP: 2635 fgtreg = is_read ? HDFGRTR2_EL2 : HDFGWTR2_EL2; 2636 break; 2637 2638 case HFGITR2_GROUP: 2639 fgtreg = HFGITR2_EL2; 2640 break; 2641 2642 case ICH_HFGRTR_GROUP: 2643 fgtreg = is_read ? ICH_HFGRTR_EL2 : ICH_HFGWTR_EL2; 2644 break; 2645 2646 case ICH_HFGITR_GROUP: 2647 fgtreg = ICH_HFGITR_EL2; 2648 break; 2649 2650 default: 2651 /* Something is really wrong, bail out */ 2652 WARN_ONCE(1, "Bad FGT group (encoding %08x, config %016llx)\n", 2653 sysreg, tc.val); 2654 goto local; 2655 } 2656 2657 if (tc.fgt != __NO_FGT_GROUP__ && check_fgt_bit(vcpu, fgtreg, tc)) 2658 goto inject; 2659 2660 b = compute_trap_behaviour(vcpu, tc); 2661 2662 if (!(b & BEHAVE_FORWARD_IN_HOST_EL0) && vcpu_is_host_el0(vcpu)) 2663 goto local; 2664 2665 if (((b & BEHAVE_FORWARD_READ) && is_read) || 2666 ((b & BEHAVE_FORWARD_WRITE) && !is_read)) 2667 goto inject; 2668 2669 local: 2670 if (!tc.sri) { 2671 struct sys_reg_params params; 2672 2673 params = esr_sys64_to_params(esr); 2674 2675 /* 2676 * This implements the pseudocode UnimplementedIDRegister() 2677 * helper for the purpose of dealing with FEAT_IDST. 2678 */ 2679 if (in_feat_id_space(¶ms)) { 2680 if (kvm_has_feat(vcpu->kvm, ID_AA64MMFR2_EL1, IDS, IMP)) 2681 kvm_inject_sync(vcpu, kvm_vcpu_get_esr(vcpu)); 2682 else 2683 kvm_inject_undefined(vcpu); 2684 2685 return true; 2686 } 2687 2688 /* 2689 * Check for the IMPDEF range, as per DDI0487 J.a, 2690 * D18.3.2 Reserved encodings for IMPLEMENTATION 2691 * DEFINED registers. 2692 */ 2693 if (!(params.Op0 == 3 && (params.CRn & 0b1011) == 0b1011)) 2694 print_sys_reg_msg(¶ms, 2695 "Unsupported guest access at: %lx\n", 2696 *vcpu_pc(vcpu)); 2697 kvm_inject_undefined(vcpu); 2698 return true; 2699 } 2700 2701 *sr_index = tc.sri - 1; 2702 return false; 2703 2704 inject: 2705 trace_kvm_forward_sysreg_trap(vcpu, sysreg, is_read); 2706 2707 kvm_inject_nested_sync(vcpu, kvm_vcpu_get_esr(vcpu)); 2708 return true; 2709 } 2710 2711 static bool __forward_traps(struct kvm_vcpu *vcpu, unsigned int reg, u64 control_bit) 2712 { 2713 if (is_nested_ctxt(vcpu) && 2714 (__vcpu_sys_reg(vcpu, reg) & control_bit)) { 2715 kvm_inject_nested_sync(vcpu, kvm_vcpu_get_esr(vcpu)); 2716 return true; 2717 } 2718 return false; 2719 } 2720 2721 static bool forward_hcr_traps(struct kvm_vcpu *vcpu, u64 control_bit) 2722 { 2723 return __forward_traps(vcpu, HCR_EL2, control_bit); 2724 } 2725 2726 bool forward_smc_trap(struct kvm_vcpu *vcpu) 2727 { 2728 return forward_hcr_traps(vcpu, HCR_TSC); 2729 } 2730 2731 static bool forward_mdcr_traps(struct kvm_vcpu *vcpu, u64 control_bit) 2732 { 2733 return __forward_traps(vcpu, MDCR_EL2, control_bit); 2734 } 2735 2736 bool forward_debug_exception(struct kvm_vcpu *vcpu) 2737 { 2738 return forward_mdcr_traps(vcpu, MDCR_EL2_TDE); 2739 } 2740 2741 static u64 kvm_check_illegal_exception_return(struct kvm_vcpu *vcpu, u64 spsr) 2742 { 2743 u64 mode = spsr & PSR_MODE_MASK; 2744 2745 /* 2746 * Possible causes for an Illegal Exception Return from EL2: 2747 * - trying to return to EL3 2748 * - trying to return to an illegal M value 2749 * - trying to return to a 32bit EL 2750 * - trying to return to EL1 with HCR_EL2.TGE set 2751 */ 2752 if (mode == PSR_MODE_EL3t || mode == PSR_MODE_EL3h || 2753 mode == 0b00001 || (mode & BIT(1)) || 2754 (spsr & PSR_MODE32_BIT) || 2755 (vcpu_el2_tge_is_set(vcpu) && (mode == PSR_MODE_EL1t || 2756 mode == PSR_MODE_EL1h))) { 2757 u64 mask; 2758 2759 /* 2760 * On an illegal exception return, the flags and masks are 2761 * taken from the SPSR while PSTATE.{EL,SP,nRW} and, if 2762 * FEAT_GCS, PSTATE.EXLOCK are unchanged (R_VWJHB). Set IL 2763 * so the HW generates an Illegal State Exception right 2764 * after ERET. 2765 */ 2766 mask = PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT | 2767 PSR_N_BIT | PSR_Z_BIT | PSR_C_BIT | PSR_V_BIT; 2768 2769 if (kvm_has_feat(vcpu->kvm, ID_AA64MMFR1_EL1, PAN, IMP)) 2770 mask |= PSR_PAN_BIT; 2771 if (kvm_has_feat(vcpu->kvm, ID_AA64PFR1_EL1, NMI, IMP)) 2772 mask |= ALLINT_ALLINT; 2773 /* FEAT_SPE_EXC and FEAT_TRBE_EXC also gate PSTATE.PM one day... */ 2774 if (kvm_has_feat(vcpu->kvm, ID_AA64DFR1_EL1, EBEP, IMP)) 2775 mask |= BIT_ULL(32); /* SPSR_ELx.PM */ 2776 2777 spsr &= mask; 2778 2779 mask = PSR_MODE_MASK | PSR_MODE32_BIT; 2780 if (kvm_has_feat(vcpu->kvm, ID_AA64PFR1_EL1, GCS, IMP)) 2781 mask |= BIT_ULL(34); /* PSTATE.EXLOCK */ 2782 2783 spsr |= *vcpu_cpsr(vcpu) & mask; 2784 spsr |= PSR_IL_BIT; 2785 } 2786 2787 return spsr; 2788 } 2789 2790 void kvm_emulate_nested_eret(struct kvm_vcpu *vcpu) 2791 { 2792 u64 spsr, elr, esr; 2793 2794 spsr = vcpu_read_sys_reg(vcpu, SPSR_EL2); 2795 spsr = kvm_check_illegal_exception_return(vcpu, spsr); 2796 2797 /* Check for an ERETAx */ 2798 esr = kvm_vcpu_get_esr(vcpu); 2799 if (esr_iss_is_eretax(esr) && !kvm_auth_eretax(vcpu, &elr)) { 2800 /* 2801 * Oh no, ERETAx failed to authenticate. 2802 * 2803 * If we have FPACCOMBINE and we don't have a pending 2804 * Illegal Execution State exception (which has priority 2805 * over FPAC), deliver an exception right away. 2806 * 2807 * Otherwise, let the mangled ELR value trickle down the 2808 * ERET handling, and the guest will have a little surprise. 2809 */ 2810 if (kvm_has_pauth(vcpu->kvm, FPACCOMBINE) && !(spsr & PSR_IL_BIT)) { 2811 esr &= (ESR_ELx_ERET_ISS_ERETA | ESR_ELx_IL); 2812 esr |= FIELD_PREP(ESR_ELx_EC_MASK, ESR_ELx_EC_FPAC); 2813 kvm_inject_nested_sync(vcpu, esr); 2814 return; 2815 } 2816 } 2817 2818 preempt_disable(); 2819 vcpu_set_flag(vcpu, IN_NESTED_ERET); 2820 kvm_arch_vcpu_put(vcpu); 2821 2822 if (!esr_iss_is_eretax(esr)) 2823 elr = __vcpu_sys_reg(vcpu, ELR_EL2); 2824 2825 trace_kvm_nested_eret(vcpu, elr, spsr); 2826 2827 *vcpu_pc(vcpu) = elr; 2828 *vcpu_cpsr(vcpu) = spsr; 2829 2830 kvm_arch_vcpu_load(vcpu, smp_processor_id()); 2831 vcpu_clear_flag(vcpu, IN_NESTED_ERET); 2832 preempt_enable(); 2833 2834 if (kvm_vcpu_has_pmu(vcpu)) 2835 kvm_pmu_nested_transition(vcpu); 2836 } 2837 2838 static void kvm_inject_el2_exception(struct kvm_vcpu *vcpu, u64 esr_el2, 2839 enum exception_type type) 2840 { 2841 trace_kvm_inject_nested_exception(vcpu, esr_el2, type); 2842 2843 switch (type) { 2844 case except_type_sync: 2845 kvm_pend_exception(vcpu, EXCEPT_AA64_EL2_SYNC); 2846 vcpu_write_sys_reg(vcpu, esr_el2, ESR_EL2); 2847 break; 2848 case except_type_irq: 2849 kvm_pend_exception(vcpu, EXCEPT_AA64_EL2_IRQ); 2850 break; 2851 case except_type_serror: 2852 kvm_pend_exception(vcpu, EXCEPT_AA64_EL2_SERR); 2853 vcpu_write_sys_reg(vcpu, esr_el2, ESR_EL2); 2854 break; 2855 default: 2856 WARN_ONCE(1, "Unsupported EL2 exception injection %d\n", type); 2857 } 2858 } 2859 2860 /* 2861 * Emulate taking an exception to EL2. 2862 * See ARM ARM J8.1.2 AArch64.TakeException() 2863 */ 2864 static int kvm_inject_nested(struct kvm_vcpu *vcpu, u64 esr_el2, 2865 enum exception_type type) 2866 { 2867 u64 pstate, mode; 2868 bool direct_inject; 2869 2870 if (!vcpu_has_nv(vcpu)) { 2871 kvm_err("Unexpected call to %s for the non-nesting configuration\n", 2872 __func__); 2873 return -EINVAL; 2874 } 2875 2876 /* 2877 * As for ERET, we can avoid doing too much on the injection path by 2878 * checking that we either took the exception from a VHE host 2879 * userspace or from vEL2. In these cases, there is no change in 2880 * translation regime (or anything else), so let's do as little as 2881 * possible. 2882 */ 2883 pstate = *vcpu_cpsr(vcpu); 2884 mode = pstate & (PSR_MODE_MASK | PSR_MODE32_BIT); 2885 2886 direct_inject = (mode == PSR_MODE_EL0t && 2887 vcpu_el2_e2h_is_set(vcpu) && 2888 vcpu_el2_tge_is_set(vcpu)); 2889 direct_inject |= (mode == PSR_MODE_EL2h || mode == PSR_MODE_EL2t); 2890 2891 if (direct_inject) { 2892 kvm_inject_el2_exception(vcpu, esr_el2, type); 2893 return 1; 2894 } 2895 2896 preempt_disable(); 2897 2898 vcpu_set_flag(vcpu, IN_NESTED_EXCEPTION); 2899 2900 /* 2901 * We may have an exception or PC update in the EL0/EL1 context. 2902 * Commit it before entering EL2. 2903 */ 2904 __kvm_adjust_pc(vcpu); 2905 2906 kvm_arch_vcpu_put(vcpu); 2907 2908 kvm_inject_el2_exception(vcpu, esr_el2, type); 2909 2910 /* 2911 * A hard requirement is that a switch between EL1 and EL2 2912 * contexts has to happen between a put/load, so that we can 2913 * pick the correct timer and interrupt configuration, among 2914 * other things. 2915 * 2916 * Make sure the exception actually took place before we load 2917 * the new context. 2918 */ 2919 __kvm_adjust_pc(vcpu); 2920 2921 kvm_arch_vcpu_load(vcpu, smp_processor_id()); 2922 vcpu_clear_flag(vcpu, IN_NESTED_EXCEPTION); 2923 2924 preempt_enable(); 2925 2926 if (kvm_vcpu_has_pmu(vcpu)) 2927 kvm_pmu_nested_transition(vcpu); 2928 2929 return 1; 2930 } 2931 2932 int kvm_inject_nested_sync(struct kvm_vcpu *vcpu, u64 esr_el2) 2933 { 2934 return kvm_inject_nested(vcpu, esr_el2, except_type_sync); 2935 } 2936 2937 int kvm_inject_nested_irq(struct kvm_vcpu *vcpu) 2938 { 2939 /* 2940 * Do not inject an irq if the: 2941 * - Current exception level is EL2, and 2942 * - virtual HCR_EL2.TGE == 0 2943 * - virtual HCR_EL2.IMO == 0 2944 * 2945 * See Table D1-17 "Physical interrupt target and masking when EL3 is 2946 * not implemented and EL2 is implemented" in ARM DDI 0487C.a. 2947 */ 2948 2949 if (vcpu_is_el2(vcpu) && !vcpu_el2_tge_is_set(vcpu) && 2950 !(__vcpu_sys_reg(vcpu, HCR_EL2) & HCR_IMO)) 2951 return 1; 2952 2953 /* esr_el2 value doesn't matter for exits due to irqs. */ 2954 return kvm_inject_nested(vcpu, 0, except_type_irq); 2955 } 2956 2957 int kvm_inject_nested_sea(struct kvm_vcpu *vcpu, bool iabt, u64 addr) 2958 { 2959 u64 esr = FIELD_PREP(ESR_ELx_EC_MASK, 2960 iabt ? ESR_ELx_EC_IABT_LOW : ESR_ELx_EC_DABT_LOW); 2961 esr |= ESR_ELx_FSC_EXTABT | ESR_ELx_IL; 2962 2963 vcpu_write_sys_reg(vcpu, addr, FAR_EL2); 2964 2965 if (__vcpu_sys_reg(vcpu, SCTLR2_EL2) & SCTLR2_EL1_EASE) 2966 return kvm_inject_nested(vcpu, esr, except_type_serror); 2967 2968 return kvm_inject_nested_sync(vcpu, esr); 2969 } 2970 2971 int kvm_inject_nested_serror(struct kvm_vcpu *vcpu, u64 esr) 2972 { 2973 /* 2974 * Hardware sets up the EC field when propagating ESR as a result of 2975 * vSError injection. Manually populate EC for an emulated SError 2976 * exception. 2977 */ 2978 esr |= FIELD_PREP(ESR_ELx_EC_MASK, ESR_ELx_EC_SERROR) | ESR_ELx_IL; 2979 return kvm_inject_nested(vcpu, esr, except_type_serror); 2980 } 2981