1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2025 Google LLC 4 * Author: Marc Zyngier <maz@kernel.org> 5 */ 6 7 #include <linux/kvm_host.h> 8 #include <asm/sysreg.h> 9 10 struct reg_bits_to_feat_map { 11 u64 bits; 12 13 #define NEVER_FGU BIT(0) /* Can trap, but never UNDEF */ 14 #define CALL_FUNC BIT(1) /* Needs to evaluate tons of crap */ 15 #define FIXED_VALUE BIT(2) /* RAZ/WI or RAO/WI in KVM */ 16 unsigned long flags; 17 18 union { 19 struct { 20 u8 regidx; 21 u8 shift; 22 u8 width; 23 bool sign; 24 s8 lo_lim; 25 }; 26 bool (*match)(struct kvm *); 27 bool (*fval)(struct kvm *, u64 *); 28 }; 29 }; 30 31 #define __NEEDS_FEAT_3(m, f, id, fld, lim) \ 32 { \ 33 .bits = (m), \ 34 .flags = (f), \ 35 .regidx = IDREG_IDX(SYS_ ## id), \ 36 .shift = id ##_## fld ## _SHIFT, \ 37 .width = id ##_## fld ## _WIDTH, \ 38 .sign = id ##_## fld ## _SIGNED, \ 39 .lo_lim = id ##_## fld ##_## lim \ 40 } 41 42 #define __NEEDS_FEAT_2(m, f, fun, dummy) \ 43 { \ 44 .bits = (m), \ 45 .flags = (f) | CALL_FUNC, \ 46 .fval = (fun), \ 47 } 48 49 #define __NEEDS_FEAT_1(m, f, fun) \ 50 { \ 51 .bits = (m), \ 52 .flags = (f) | CALL_FUNC, \ 53 .match = (fun), \ 54 } 55 56 #define NEEDS_FEAT_FLAG(m, f, ...) \ 57 CONCATENATE(__NEEDS_FEAT_, COUNT_ARGS(__VA_ARGS__))(m, f, __VA_ARGS__) 58 59 #define NEEDS_FEAT_FIXED(m, ...) \ 60 NEEDS_FEAT_FLAG(m, FIXED_VALUE, __VA_ARGS__, 0) 61 62 #define NEEDS_FEAT(m, ...) NEEDS_FEAT_FLAG(m, 0, __VA_ARGS__) 63 64 #define FEAT_SPE ID_AA64DFR0_EL1, PMSVer, IMP 65 #define FEAT_SPE_FnE ID_AA64DFR0_EL1, PMSVer, V1P2 66 #define FEAT_BRBE ID_AA64DFR0_EL1, BRBE, IMP 67 #define FEAT_TRC_SR ID_AA64DFR0_EL1, TraceVer, IMP 68 #define FEAT_PMUv3 ID_AA64DFR0_EL1, PMUVer, IMP 69 #define FEAT_TRBE ID_AA64DFR0_EL1, TraceBuffer, IMP 70 #define FEAT_TRBEv1p1 ID_AA64DFR0_EL1, TraceBuffer, TRBE_V1P1 71 #define FEAT_DoubleLock ID_AA64DFR0_EL1, DoubleLock, IMP 72 #define FEAT_TRF ID_AA64DFR0_EL1, TraceFilt, IMP 73 #define FEAT_AA32EL0 ID_AA64PFR0_EL1, EL0, AARCH32 74 #define FEAT_AA32EL1 ID_AA64PFR0_EL1, EL1, AARCH32 75 #define FEAT_AA64EL1 ID_AA64PFR0_EL1, EL1, IMP 76 #define FEAT_AA64EL3 ID_AA64PFR0_EL1, EL3, IMP 77 #define FEAT_AIE ID_AA64MMFR3_EL1, AIE, IMP 78 #define FEAT_S2POE ID_AA64MMFR3_EL1, S2POE, IMP 79 #define FEAT_S1POE ID_AA64MMFR3_EL1, S1POE, IMP 80 #define FEAT_S1PIE ID_AA64MMFR3_EL1, S1PIE, IMP 81 #define FEAT_THE ID_AA64PFR1_EL1, THE, IMP 82 #define FEAT_SME ID_AA64PFR1_EL1, SME, IMP 83 #define FEAT_GCS ID_AA64PFR1_EL1, GCS, IMP 84 #define FEAT_LS64 ID_AA64ISAR1_EL1, LS64, LS64 85 #define FEAT_LS64_V ID_AA64ISAR1_EL1, LS64, LS64_V 86 #define FEAT_LS64_ACCDATA ID_AA64ISAR1_EL1, LS64, LS64_ACCDATA 87 #define FEAT_RAS ID_AA64PFR0_EL1, RAS, IMP 88 #define FEAT_RASv2 ID_AA64PFR0_EL1, RAS, V2 89 #define FEAT_GICv3 ID_AA64PFR0_EL1, GIC, IMP 90 #define FEAT_LOR ID_AA64MMFR1_EL1, LO, IMP 91 #define FEAT_SPEv1p2 ID_AA64DFR0_EL1, PMSVer, V1P2 92 #define FEAT_SPEv1p4 ID_AA64DFR0_EL1, PMSVer, V1P4 93 #define FEAT_SPEv1p5 ID_AA64DFR0_EL1, PMSVer, V1P5 94 #define FEAT_ATS1A ID_AA64ISAR2_EL1, ATS1A, IMP 95 #define FEAT_SPECRES2 ID_AA64ISAR1_EL1, SPECRES, COSP_RCTX 96 #define FEAT_SPECRES ID_AA64ISAR1_EL1, SPECRES, IMP 97 #define FEAT_TLBIRANGE ID_AA64ISAR0_EL1, TLB, RANGE 98 #define FEAT_TLBIOS ID_AA64ISAR0_EL1, TLB, OS 99 #define FEAT_PAN2 ID_AA64MMFR1_EL1, PAN, PAN2 100 #define FEAT_DPB2 ID_AA64ISAR1_EL1, DPB, DPB2 101 #define FEAT_AMUv1 ID_AA64PFR0_EL1, AMU, IMP 102 #define FEAT_AMUv1p1 ID_AA64PFR0_EL1, AMU, V1P1 103 #define FEAT_CMOW ID_AA64MMFR1_EL1, CMOW, IMP 104 #define FEAT_D128 ID_AA64MMFR3_EL1, D128, IMP 105 #define FEAT_DoubleFault2 ID_AA64PFR1_EL1, DF2, IMP 106 #define FEAT_FPMR ID_AA64PFR2_EL1, FPMR, IMP 107 #define FEAT_MOPS ID_AA64ISAR2_EL1, MOPS, IMP 108 #define FEAT_NMI ID_AA64PFR1_EL1, NMI, IMP 109 #define FEAT_SCTLR2 ID_AA64MMFR3_EL1, SCTLRX, IMP 110 #define FEAT_SYSREG128 ID_AA64ISAR2_EL1, SYSREG_128, IMP 111 #define FEAT_TCR2 ID_AA64MMFR3_EL1, TCRX, IMP 112 #define FEAT_XS ID_AA64ISAR1_EL1, XS, IMP 113 #define FEAT_EVT ID_AA64MMFR2_EL1, EVT, IMP 114 #define FEAT_EVT_TTLBxS ID_AA64MMFR2_EL1, EVT, TTLBxS 115 #define FEAT_MTE2 ID_AA64PFR1_EL1, MTE, MTE2 116 #define FEAT_RME ID_AA64PFR0_EL1, RME, IMP 117 #define FEAT_MPAM ID_AA64PFR0_EL1, MPAM, 1 118 #define FEAT_S2FWB ID_AA64MMFR2_EL1, FWB, IMP 119 #define FEAT_TME ID_AA64ISAR0_EL1, TME, IMP 120 #define FEAT_TWED ID_AA64MMFR1_EL1, TWED, IMP 121 #define FEAT_E2H0 ID_AA64MMFR4_EL1, E2H0, IMP 122 #define FEAT_SRMASK ID_AA64MMFR4_EL1, SRMASK, IMP 123 #define FEAT_PoPS ID_AA64MMFR4_EL1, PoPS, IMP 124 #define FEAT_PFAR ID_AA64PFR1_EL1, PFAR, IMP 125 #define FEAT_Debugv8p9 ID_AA64DFR0_EL1, PMUVer, V3P9 126 #define FEAT_PMUv3_SS ID_AA64DFR0_EL1, PMSS, IMP 127 #define FEAT_SEBEP ID_AA64DFR0_EL1, SEBEP, IMP 128 #define FEAT_EBEP ID_AA64DFR1_EL1, EBEP, IMP 129 #define FEAT_ITE ID_AA64DFR1_EL1, ITE, IMP 130 #define FEAT_PMUv3_ICNTR ID_AA64DFR1_EL1, PMICNTR, IMP 131 #define FEAT_SPMU ID_AA64DFR1_EL1, SPMU, IMP 132 #define FEAT_SPE_nVM ID_AA64DFR2_EL1, SPE_nVM, IMP 133 #define FEAT_STEP2 ID_AA64DFR2_EL1, STEP, IMP 134 #define FEAT_SYSREG128 ID_AA64ISAR2_EL1, SYSREG_128, IMP 135 #define FEAT_CPA2 ID_AA64ISAR3_EL1, CPA, CPA2 136 #define FEAT_ASID2 ID_AA64MMFR4_EL1, ASID2, IMP 137 #define FEAT_MEC ID_AA64MMFR3_EL1, MEC, IMP 138 #define FEAT_HAFT ID_AA64MMFR1_EL1, HAFDBS, HAFT 139 #define FEAT_BTI ID_AA64PFR1_EL1, BT, IMP 140 #define FEAT_ExS ID_AA64MMFR0_EL1, EXS, IMP 141 #define FEAT_IESB ID_AA64MMFR2_EL1, IESB, IMP 142 #define FEAT_LSE2 ID_AA64MMFR2_EL1, AT, IMP 143 #define FEAT_LSMAOC ID_AA64MMFR2_EL1, LSM, IMP 144 #define FEAT_MixedEnd ID_AA64MMFR0_EL1, BIGEND, IMP 145 #define FEAT_MixedEndEL0 ID_AA64MMFR0_EL1, BIGENDEL0, IMP 146 #define FEAT_MTE2 ID_AA64PFR1_EL1, MTE, MTE2 147 #define FEAT_MTE_ASYNC ID_AA64PFR1_EL1, MTE_frac, ASYNC 148 #define FEAT_MTE_STORE_ONLY ID_AA64PFR2_EL1, MTESTOREONLY, IMP 149 #define FEAT_PAN ID_AA64MMFR1_EL1, PAN, IMP 150 #define FEAT_PAN3 ID_AA64MMFR1_EL1, PAN, PAN3 151 #define FEAT_SSBS ID_AA64PFR1_EL1, SSBS, IMP 152 #define FEAT_TIDCP1 ID_AA64MMFR1_EL1, TIDCP1, IMP 153 #define FEAT_FGT ID_AA64MMFR0_EL1, FGT, IMP 154 #define FEAT_MTPMU ID_AA64DFR0_EL1, MTPMU, IMP 155 156 static bool not_feat_aa64el3(struct kvm *kvm) 157 { 158 return !kvm_has_feat(kvm, FEAT_AA64EL3); 159 } 160 161 static bool feat_nv2(struct kvm *kvm) 162 { 163 return ((kvm_has_feat(kvm, ID_AA64MMFR4_EL1, NV_frac, NV2_ONLY) && 164 kvm_has_feat_enum(kvm, ID_AA64MMFR2_EL1, NV, NI)) || 165 kvm_has_feat(kvm, ID_AA64MMFR2_EL1, NV, NV2)); 166 } 167 168 static bool feat_nv2_e2h0_ni(struct kvm *kvm) 169 { 170 return feat_nv2(kvm) && !kvm_has_feat(kvm, FEAT_E2H0); 171 } 172 173 static bool feat_rasv1p1(struct kvm *kvm) 174 { 175 return (kvm_has_feat(kvm, ID_AA64PFR0_EL1, RAS, V1P1) || 176 (kvm_has_feat_enum(kvm, ID_AA64PFR0_EL1, RAS, IMP) && 177 kvm_has_feat(kvm, ID_AA64PFR1_EL1, RAS_frac, RASv1p1))); 178 } 179 180 static bool feat_csv2_2_csv2_1p2(struct kvm *kvm) 181 { 182 return (kvm_has_feat(kvm, ID_AA64PFR0_EL1, CSV2, CSV2_2) || 183 (kvm_has_feat(kvm, ID_AA64PFR1_EL1, CSV2_frac, CSV2_1p2) && 184 kvm_has_feat_enum(kvm, ID_AA64PFR0_EL1, CSV2, IMP))); 185 } 186 187 static bool feat_pauth(struct kvm *kvm) 188 { 189 return kvm_has_pauth(kvm, PAuth); 190 } 191 192 static bool feat_pauth_lr(struct kvm *kvm) 193 { 194 return kvm_has_pauth(kvm, PAuth_LR); 195 } 196 197 static bool feat_aderr(struct kvm *kvm) 198 { 199 return (kvm_has_feat(kvm, ID_AA64MMFR3_EL1, ADERR, FEAT_ADERR) && 200 kvm_has_feat(kvm, ID_AA64MMFR3_EL1, SDERR, FEAT_ADERR)); 201 } 202 203 static bool feat_anerr(struct kvm *kvm) 204 { 205 return (kvm_has_feat(kvm, ID_AA64MMFR3_EL1, ANERR, FEAT_ANERR) && 206 kvm_has_feat(kvm, ID_AA64MMFR3_EL1, SNERR, FEAT_ANERR)); 207 } 208 209 static bool feat_sme_smps(struct kvm *kvm) 210 { 211 /* 212 * Revists this if KVM ever supports SME -- this really should 213 * look at the guest's view of SMIDR_EL1. Funnily enough, this 214 * is not captured in the JSON file, but only as a note in the 215 * ARM ARM. 216 */ 217 return (kvm_has_feat(kvm, FEAT_SME) && 218 (read_sysreg_s(SYS_SMIDR_EL1) & SMIDR_EL1_SMPS)); 219 } 220 221 static bool feat_spe_fds(struct kvm *kvm) 222 { 223 /* 224 * Revists this if KVM ever supports SPE -- this really should 225 * look at the guest's view of PMSIDR_EL1. 226 */ 227 return (kvm_has_feat(kvm, FEAT_SPEv1p4) && 228 (read_sysreg_s(SYS_PMSIDR_EL1) & PMSIDR_EL1_FDS)); 229 } 230 231 static bool feat_trbe_mpam(struct kvm *kvm) 232 { 233 /* 234 * Revists this if KVM ever supports both MPAM and TRBE -- 235 * this really should look at the guest's view of TRBIDR_EL1. 236 */ 237 return (kvm_has_feat(kvm, FEAT_TRBE) && 238 kvm_has_feat(kvm, FEAT_MPAM) && 239 (read_sysreg_s(SYS_TRBIDR_EL1) & TRBIDR_EL1_MPAM)); 240 } 241 242 static bool feat_asid2_e2h1(struct kvm *kvm) 243 { 244 return kvm_has_feat(kvm, FEAT_ASID2) && !kvm_has_feat(kvm, FEAT_E2H0); 245 } 246 247 static bool feat_d128_e2h1(struct kvm *kvm) 248 { 249 return kvm_has_feat(kvm, FEAT_D128) && !kvm_has_feat(kvm, FEAT_E2H0); 250 } 251 252 static bool feat_mec_e2h1(struct kvm *kvm) 253 { 254 return kvm_has_feat(kvm, FEAT_MEC) && !kvm_has_feat(kvm, FEAT_E2H0); 255 } 256 257 static bool feat_ebep_pmuv3_ss(struct kvm *kvm) 258 { 259 return kvm_has_feat(kvm, FEAT_EBEP) || kvm_has_feat(kvm, FEAT_PMUv3_SS); 260 } 261 262 static bool feat_mixedendel0(struct kvm *kvm) 263 { 264 return kvm_has_feat(kvm, FEAT_MixedEnd) || kvm_has_feat(kvm, FEAT_MixedEndEL0); 265 } 266 267 static bool feat_mte_async(struct kvm *kvm) 268 { 269 return kvm_has_feat(kvm, FEAT_MTE2) && kvm_has_feat_enum(kvm, FEAT_MTE_ASYNC); 270 } 271 272 #define check_pmu_revision(k, r) \ 273 ({ \ 274 (kvm_has_feat((k), ID_AA64DFR0_EL1, PMUVer, r) && \ 275 !kvm_has_feat((k), ID_AA64DFR0_EL1, PMUVer, IMP_DEF)); \ 276 }) 277 278 static bool feat_pmuv3p1(struct kvm *kvm) 279 { 280 return check_pmu_revision(kvm, V3P1); 281 } 282 283 static bool feat_pmuv3p5(struct kvm *kvm) 284 { 285 return check_pmu_revision(kvm, V3P5); 286 } 287 288 static bool feat_pmuv3p7(struct kvm *kvm) 289 { 290 return check_pmu_revision(kvm, V3P7); 291 } 292 293 static bool feat_pmuv3p9(struct kvm *kvm) 294 { 295 return check_pmu_revision(kvm, V3P9); 296 } 297 298 static bool compute_hcr_rw(struct kvm *kvm, u64 *bits) 299 { 300 /* This is purely academic: AArch32 and NV are mutually exclusive */ 301 if (bits) { 302 if (kvm_has_feat(kvm, FEAT_AA32EL1)) 303 *bits &= ~HCR_EL2_RW; 304 else 305 *bits |= HCR_EL2_RW; 306 } 307 308 return true; 309 } 310 311 static bool compute_hcr_e2h(struct kvm *kvm, u64 *bits) 312 { 313 if (bits) { 314 if (kvm_has_feat(kvm, FEAT_E2H0)) 315 *bits &= ~HCR_EL2_E2H; 316 else 317 *bits |= HCR_EL2_E2H; 318 } 319 320 return true; 321 } 322 323 static const struct reg_bits_to_feat_map hfgrtr_feat_map[] = { 324 NEEDS_FEAT(HFGRTR_EL2_nAMAIR2_EL1 | 325 HFGRTR_EL2_nMAIR2_EL1, 326 FEAT_AIE), 327 NEEDS_FEAT(HFGRTR_EL2_nS2POR_EL1, FEAT_S2POE), 328 NEEDS_FEAT(HFGRTR_EL2_nPOR_EL1 | 329 HFGRTR_EL2_nPOR_EL0, 330 FEAT_S1POE), 331 NEEDS_FEAT(HFGRTR_EL2_nPIR_EL1 | 332 HFGRTR_EL2_nPIRE0_EL1, 333 FEAT_S1PIE), 334 NEEDS_FEAT(HFGRTR_EL2_nRCWMASK_EL1, FEAT_THE), 335 NEEDS_FEAT(HFGRTR_EL2_nTPIDR2_EL0 | 336 HFGRTR_EL2_nSMPRI_EL1, 337 FEAT_SME), 338 NEEDS_FEAT(HFGRTR_EL2_nGCS_EL1 | 339 HFGRTR_EL2_nGCS_EL0, 340 FEAT_GCS), 341 NEEDS_FEAT(HFGRTR_EL2_nACCDATA_EL1, FEAT_LS64_ACCDATA), 342 NEEDS_FEAT(HFGRTR_EL2_ERXADDR_EL1 | 343 HFGRTR_EL2_ERXMISCn_EL1 | 344 HFGRTR_EL2_ERXSTATUS_EL1 | 345 HFGRTR_EL2_ERXCTLR_EL1 | 346 HFGRTR_EL2_ERXFR_EL1 | 347 HFGRTR_EL2_ERRSELR_EL1 | 348 HFGRTR_EL2_ERRIDR_EL1, 349 FEAT_RAS), 350 NEEDS_FEAT(HFGRTR_EL2_ERXPFGCDN_EL1 | 351 HFGRTR_EL2_ERXPFGCTL_EL1 | 352 HFGRTR_EL2_ERXPFGF_EL1, 353 feat_rasv1p1), 354 NEEDS_FEAT(HFGRTR_EL2_ICC_IGRPENn_EL1, FEAT_GICv3), 355 NEEDS_FEAT(HFGRTR_EL2_SCXTNUM_EL0 | 356 HFGRTR_EL2_SCXTNUM_EL1, 357 feat_csv2_2_csv2_1p2), 358 NEEDS_FEAT(HFGRTR_EL2_LORSA_EL1 | 359 HFGRTR_EL2_LORN_EL1 | 360 HFGRTR_EL2_LORID_EL1 | 361 HFGRTR_EL2_LOREA_EL1 | 362 HFGRTR_EL2_LORC_EL1, 363 FEAT_LOR), 364 NEEDS_FEAT(HFGRTR_EL2_APIBKey | 365 HFGRTR_EL2_APIAKey | 366 HFGRTR_EL2_APGAKey | 367 HFGRTR_EL2_APDBKey | 368 HFGRTR_EL2_APDAKey, 369 feat_pauth), 370 NEEDS_FEAT_FLAG(HFGRTR_EL2_VBAR_EL1 | 371 HFGRTR_EL2_TTBR1_EL1 | 372 HFGRTR_EL2_TTBR0_EL1 | 373 HFGRTR_EL2_TPIDR_EL0 | 374 HFGRTR_EL2_TPIDRRO_EL0 | 375 HFGRTR_EL2_TPIDR_EL1 | 376 HFGRTR_EL2_TCR_EL1 | 377 HFGRTR_EL2_SCTLR_EL1 | 378 HFGRTR_EL2_REVIDR_EL1 | 379 HFGRTR_EL2_PAR_EL1 | 380 HFGRTR_EL2_MPIDR_EL1 | 381 HFGRTR_EL2_MIDR_EL1 | 382 HFGRTR_EL2_MAIR_EL1 | 383 HFGRTR_EL2_ISR_EL1 | 384 HFGRTR_EL2_FAR_EL1 | 385 HFGRTR_EL2_ESR_EL1 | 386 HFGRTR_EL2_DCZID_EL0 | 387 HFGRTR_EL2_CTR_EL0 | 388 HFGRTR_EL2_CSSELR_EL1 | 389 HFGRTR_EL2_CPACR_EL1 | 390 HFGRTR_EL2_CONTEXTIDR_EL1| 391 HFGRTR_EL2_CLIDR_EL1 | 392 HFGRTR_EL2_CCSIDR_EL1 | 393 HFGRTR_EL2_AMAIR_EL1 | 394 HFGRTR_EL2_AIDR_EL1 | 395 HFGRTR_EL2_AFSR1_EL1 | 396 HFGRTR_EL2_AFSR0_EL1, 397 NEVER_FGU, FEAT_AA64EL1), 398 }; 399 400 static const struct reg_bits_to_feat_map hfgwtr_feat_map[] = { 401 NEEDS_FEAT(HFGWTR_EL2_nAMAIR2_EL1 | 402 HFGWTR_EL2_nMAIR2_EL1, 403 FEAT_AIE), 404 NEEDS_FEAT(HFGWTR_EL2_nS2POR_EL1, FEAT_S2POE), 405 NEEDS_FEAT(HFGWTR_EL2_nPOR_EL1 | 406 HFGWTR_EL2_nPOR_EL0, 407 FEAT_S1POE), 408 NEEDS_FEAT(HFGWTR_EL2_nPIR_EL1 | 409 HFGWTR_EL2_nPIRE0_EL1, 410 FEAT_S1PIE), 411 NEEDS_FEAT(HFGWTR_EL2_nRCWMASK_EL1, FEAT_THE), 412 NEEDS_FEAT(HFGWTR_EL2_nTPIDR2_EL0 | 413 HFGWTR_EL2_nSMPRI_EL1, 414 FEAT_SME), 415 NEEDS_FEAT(HFGWTR_EL2_nGCS_EL1 | 416 HFGWTR_EL2_nGCS_EL0, 417 FEAT_GCS), 418 NEEDS_FEAT(HFGWTR_EL2_nACCDATA_EL1, FEAT_LS64_ACCDATA), 419 NEEDS_FEAT(HFGWTR_EL2_ERXADDR_EL1 | 420 HFGWTR_EL2_ERXMISCn_EL1 | 421 HFGWTR_EL2_ERXSTATUS_EL1 | 422 HFGWTR_EL2_ERXCTLR_EL1 | 423 HFGWTR_EL2_ERRSELR_EL1, 424 FEAT_RAS), 425 NEEDS_FEAT(HFGWTR_EL2_ERXPFGCDN_EL1 | 426 HFGWTR_EL2_ERXPFGCTL_EL1, 427 feat_rasv1p1), 428 NEEDS_FEAT(HFGWTR_EL2_ICC_IGRPENn_EL1, FEAT_GICv3), 429 NEEDS_FEAT(HFGWTR_EL2_SCXTNUM_EL0 | 430 HFGWTR_EL2_SCXTNUM_EL1, 431 feat_csv2_2_csv2_1p2), 432 NEEDS_FEAT(HFGWTR_EL2_LORSA_EL1 | 433 HFGWTR_EL2_LORN_EL1 | 434 HFGWTR_EL2_LOREA_EL1 | 435 HFGWTR_EL2_LORC_EL1, 436 FEAT_LOR), 437 NEEDS_FEAT(HFGWTR_EL2_APIBKey | 438 HFGWTR_EL2_APIAKey | 439 HFGWTR_EL2_APGAKey | 440 HFGWTR_EL2_APDBKey | 441 HFGWTR_EL2_APDAKey, 442 feat_pauth), 443 NEEDS_FEAT_FLAG(HFGWTR_EL2_VBAR_EL1 | 444 HFGWTR_EL2_TTBR1_EL1 | 445 HFGWTR_EL2_TTBR0_EL1 | 446 HFGWTR_EL2_TPIDR_EL0 | 447 HFGWTR_EL2_TPIDRRO_EL0 | 448 HFGWTR_EL2_TPIDR_EL1 | 449 HFGWTR_EL2_TCR_EL1 | 450 HFGWTR_EL2_SCTLR_EL1 | 451 HFGWTR_EL2_PAR_EL1 | 452 HFGWTR_EL2_MAIR_EL1 | 453 HFGWTR_EL2_FAR_EL1 | 454 HFGWTR_EL2_ESR_EL1 | 455 HFGWTR_EL2_CSSELR_EL1 | 456 HFGWTR_EL2_CPACR_EL1 | 457 HFGWTR_EL2_CONTEXTIDR_EL1| 458 HFGWTR_EL2_AMAIR_EL1 | 459 HFGWTR_EL2_AFSR1_EL1 | 460 HFGWTR_EL2_AFSR0_EL1, 461 NEVER_FGU, FEAT_AA64EL1), 462 }; 463 464 static const struct reg_bits_to_feat_map hdfgrtr_feat_map[] = { 465 NEEDS_FEAT(HDFGRTR_EL2_PMBIDR_EL1 | 466 HDFGRTR_EL2_PMSLATFR_EL1 | 467 HDFGRTR_EL2_PMSIRR_EL1 | 468 HDFGRTR_EL2_PMSIDR_EL1 | 469 HDFGRTR_EL2_PMSICR_EL1 | 470 HDFGRTR_EL2_PMSFCR_EL1 | 471 HDFGRTR_EL2_PMSEVFR_EL1 | 472 HDFGRTR_EL2_PMSCR_EL1 | 473 HDFGRTR_EL2_PMBSR_EL1 | 474 HDFGRTR_EL2_PMBPTR_EL1 | 475 HDFGRTR_EL2_PMBLIMITR_EL1, 476 FEAT_SPE), 477 NEEDS_FEAT(HDFGRTR_EL2_nPMSNEVFR_EL1, FEAT_SPE_FnE), 478 NEEDS_FEAT(HDFGRTR_EL2_nBRBDATA | 479 HDFGRTR_EL2_nBRBCTL | 480 HDFGRTR_EL2_nBRBIDR, 481 FEAT_BRBE), 482 NEEDS_FEAT(HDFGRTR_EL2_TRCVICTLR | 483 HDFGRTR_EL2_TRCSTATR | 484 HDFGRTR_EL2_TRCSSCSRn | 485 HDFGRTR_EL2_TRCSEQSTR | 486 HDFGRTR_EL2_TRCPRGCTLR | 487 HDFGRTR_EL2_TRCOSLSR | 488 HDFGRTR_EL2_TRCIMSPECn | 489 HDFGRTR_EL2_TRCID | 490 HDFGRTR_EL2_TRCCNTVRn | 491 HDFGRTR_EL2_TRCCLAIM | 492 HDFGRTR_EL2_TRCAUXCTLR | 493 HDFGRTR_EL2_TRCAUTHSTATUS | 494 HDFGRTR_EL2_TRC, 495 FEAT_TRC_SR), 496 NEEDS_FEAT(HDFGRTR_EL2_PMCEIDn_EL0 | 497 HDFGRTR_EL2_PMUSERENR_EL0 | 498 HDFGRTR_EL2_PMMIR_EL1 | 499 HDFGRTR_EL2_PMSELR_EL0 | 500 HDFGRTR_EL2_PMOVS | 501 HDFGRTR_EL2_PMINTEN | 502 HDFGRTR_EL2_PMCNTEN | 503 HDFGRTR_EL2_PMCCNTR_EL0 | 504 HDFGRTR_EL2_PMCCFILTR_EL0 | 505 HDFGRTR_EL2_PMEVTYPERn_EL0 | 506 HDFGRTR_EL2_PMEVCNTRn_EL0, 507 FEAT_PMUv3), 508 NEEDS_FEAT(HDFGRTR_EL2_TRBTRG_EL1 | 509 HDFGRTR_EL2_TRBSR_EL1 | 510 HDFGRTR_EL2_TRBPTR_EL1 | 511 HDFGRTR_EL2_TRBMAR_EL1 | 512 HDFGRTR_EL2_TRBLIMITR_EL1 | 513 HDFGRTR_EL2_TRBIDR_EL1 | 514 HDFGRTR_EL2_TRBBASER_EL1, 515 FEAT_TRBE), 516 NEEDS_FEAT_FLAG(HDFGRTR_EL2_OSDLR_EL1, NEVER_FGU, 517 FEAT_DoubleLock), 518 NEEDS_FEAT_FLAG(HDFGRTR_EL2_OSECCR_EL1 | 519 HDFGRTR_EL2_OSLSR_EL1 | 520 HDFGRTR_EL2_DBGPRCR_EL1 | 521 HDFGRTR_EL2_DBGAUTHSTATUS_EL1| 522 HDFGRTR_EL2_DBGCLAIM | 523 HDFGRTR_EL2_MDSCR_EL1 | 524 HDFGRTR_EL2_DBGWVRn_EL1 | 525 HDFGRTR_EL2_DBGWCRn_EL1 | 526 HDFGRTR_EL2_DBGBVRn_EL1 | 527 HDFGRTR_EL2_DBGBCRn_EL1, 528 NEVER_FGU, FEAT_AA64EL1) 529 }; 530 531 static const struct reg_bits_to_feat_map hdfgwtr_feat_map[] = { 532 NEEDS_FEAT(HDFGWTR_EL2_PMSLATFR_EL1 | 533 HDFGWTR_EL2_PMSIRR_EL1 | 534 HDFGWTR_EL2_PMSICR_EL1 | 535 HDFGWTR_EL2_PMSFCR_EL1 | 536 HDFGWTR_EL2_PMSEVFR_EL1 | 537 HDFGWTR_EL2_PMSCR_EL1 | 538 HDFGWTR_EL2_PMBSR_EL1 | 539 HDFGWTR_EL2_PMBPTR_EL1 | 540 HDFGWTR_EL2_PMBLIMITR_EL1, 541 FEAT_SPE), 542 NEEDS_FEAT(HDFGWTR_EL2_nPMSNEVFR_EL1, FEAT_SPE_FnE), 543 NEEDS_FEAT(HDFGWTR_EL2_nBRBDATA | 544 HDFGWTR_EL2_nBRBCTL, 545 FEAT_BRBE), 546 NEEDS_FEAT(HDFGWTR_EL2_TRCVICTLR | 547 HDFGWTR_EL2_TRCSSCSRn | 548 HDFGWTR_EL2_TRCSEQSTR | 549 HDFGWTR_EL2_TRCPRGCTLR | 550 HDFGWTR_EL2_TRCOSLAR | 551 HDFGWTR_EL2_TRCIMSPECn | 552 HDFGWTR_EL2_TRCCNTVRn | 553 HDFGWTR_EL2_TRCCLAIM | 554 HDFGWTR_EL2_TRCAUXCTLR | 555 HDFGWTR_EL2_TRC, 556 FEAT_TRC_SR), 557 NEEDS_FEAT(HDFGWTR_EL2_PMUSERENR_EL0 | 558 HDFGWTR_EL2_PMCR_EL0 | 559 HDFGWTR_EL2_PMSWINC_EL0 | 560 HDFGWTR_EL2_PMSELR_EL0 | 561 HDFGWTR_EL2_PMOVS | 562 HDFGWTR_EL2_PMINTEN | 563 HDFGWTR_EL2_PMCNTEN | 564 HDFGWTR_EL2_PMCCNTR_EL0 | 565 HDFGWTR_EL2_PMCCFILTR_EL0 | 566 HDFGWTR_EL2_PMEVTYPERn_EL0 | 567 HDFGWTR_EL2_PMEVCNTRn_EL0, 568 FEAT_PMUv3), 569 NEEDS_FEAT(HDFGWTR_EL2_TRBTRG_EL1 | 570 HDFGWTR_EL2_TRBSR_EL1 | 571 HDFGWTR_EL2_TRBPTR_EL1 | 572 HDFGWTR_EL2_TRBMAR_EL1 | 573 HDFGWTR_EL2_TRBLIMITR_EL1 | 574 HDFGWTR_EL2_TRBBASER_EL1, 575 FEAT_TRBE), 576 NEEDS_FEAT_FLAG(HDFGWTR_EL2_OSDLR_EL1, 577 NEVER_FGU, FEAT_DoubleLock), 578 NEEDS_FEAT_FLAG(HDFGWTR_EL2_OSECCR_EL1 | 579 HDFGWTR_EL2_OSLAR_EL1 | 580 HDFGWTR_EL2_DBGPRCR_EL1 | 581 HDFGWTR_EL2_DBGCLAIM | 582 HDFGWTR_EL2_MDSCR_EL1 | 583 HDFGWTR_EL2_DBGWVRn_EL1 | 584 HDFGWTR_EL2_DBGWCRn_EL1 | 585 HDFGWTR_EL2_DBGBVRn_EL1 | 586 HDFGWTR_EL2_DBGBCRn_EL1, 587 NEVER_FGU, FEAT_AA64EL1), 588 NEEDS_FEAT(HDFGWTR_EL2_TRFCR_EL1, FEAT_TRF), 589 }; 590 591 592 static const struct reg_bits_to_feat_map hfgitr_feat_map[] = { 593 NEEDS_FEAT(HFGITR_EL2_PSBCSYNC, FEAT_SPEv1p5), 594 NEEDS_FEAT(HFGITR_EL2_ATS1E1A, FEAT_ATS1A), 595 NEEDS_FEAT(HFGITR_EL2_COSPRCTX, FEAT_SPECRES2), 596 NEEDS_FEAT(HFGITR_EL2_nGCSEPP | 597 HFGITR_EL2_nGCSSTR_EL1 | 598 HFGITR_EL2_nGCSPUSHM_EL1, 599 FEAT_GCS), 600 NEEDS_FEAT(HFGITR_EL2_nBRBIALL | 601 HFGITR_EL2_nBRBINJ, 602 FEAT_BRBE), 603 NEEDS_FEAT(HFGITR_EL2_CPPRCTX | 604 HFGITR_EL2_DVPRCTX | 605 HFGITR_EL2_CFPRCTX, 606 FEAT_SPECRES), 607 NEEDS_FEAT(HFGITR_EL2_TLBIRVAALE1 | 608 HFGITR_EL2_TLBIRVALE1 | 609 HFGITR_EL2_TLBIRVAAE1 | 610 HFGITR_EL2_TLBIRVAE1 | 611 HFGITR_EL2_TLBIRVAALE1IS | 612 HFGITR_EL2_TLBIRVALE1IS | 613 HFGITR_EL2_TLBIRVAAE1IS | 614 HFGITR_EL2_TLBIRVAE1IS | 615 HFGITR_EL2_TLBIRVAALE1OS | 616 HFGITR_EL2_TLBIRVALE1OS | 617 HFGITR_EL2_TLBIRVAAE1OS | 618 HFGITR_EL2_TLBIRVAE1OS, 619 FEAT_TLBIRANGE), 620 NEEDS_FEAT(HFGITR_EL2_TLBIVAALE1OS | 621 HFGITR_EL2_TLBIVALE1OS | 622 HFGITR_EL2_TLBIVAAE1OS | 623 HFGITR_EL2_TLBIASIDE1OS | 624 HFGITR_EL2_TLBIVAE1OS | 625 HFGITR_EL2_TLBIVMALLE1OS, 626 FEAT_TLBIOS), 627 NEEDS_FEAT(HFGITR_EL2_ATS1E1WP | 628 HFGITR_EL2_ATS1E1RP, 629 FEAT_PAN2), 630 NEEDS_FEAT(HFGITR_EL2_DCCVADP, FEAT_DPB2), 631 NEEDS_FEAT_FLAG(HFGITR_EL2_DCCVAC | 632 HFGITR_EL2_SVC_EL1 | 633 HFGITR_EL2_SVC_EL0 | 634 HFGITR_EL2_ERET | 635 HFGITR_EL2_TLBIVAALE1 | 636 HFGITR_EL2_TLBIVALE1 | 637 HFGITR_EL2_TLBIVAAE1 | 638 HFGITR_EL2_TLBIASIDE1 | 639 HFGITR_EL2_TLBIVAE1 | 640 HFGITR_EL2_TLBIVMALLE1 | 641 HFGITR_EL2_TLBIVAALE1IS | 642 HFGITR_EL2_TLBIVALE1IS | 643 HFGITR_EL2_TLBIVAAE1IS | 644 HFGITR_EL2_TLBIASIDE1IS | 645 HFGITR_EL2_TLBIVAE1IS | 646 HFGITR_EL2_TLBIVMALLE1IS| 647 HFGITR_EL2_ATS1E0W | 648 HFGITR_EL2_ATS1E0R | 649 HFGITR_EL2_ATS1E1W | 650 HFGITR_EL2_ATS1E1R | 651 HFGITR_EL2_DCZVA | 652 HFGITR_EL2_DCCIVAC | 653 HFGITR_EL2_DCCVAP | 654 HFGITR_EL2_DCCVAU | 655 HFGITR_EL2_DCCISW | 656 HFGITR_EL2_DCCSW | 657 HFGITR_EL2_DCISW | 658 HFGITR_EL2_DCIVAC | 659 HFGITR_EL2_ICIVAU | 660 HFGITR_EL2_ICIALLU | 661 HFGITR_EL2_ICIALLUIS, 662 NEVER_FGU, FEAT_AA64EL1), 663 }; 664 665 static const struct reg_bits_to_feat_map hafgrtr_feat_map[] = { 666 NEEDS_FEAT(HAFGRTR_EL2_AMEVTYPER115_EL0 | 667 HAFGRTR_EL2_AMEVTYPER114_EL0 | 668 HAFGRTR_EL2_AMEVTYPER113_EL0 | 669 HAFGRTR_EL2_AMEVTYPER112_EL0 | 670 HAFGRTR_EL2_AMEVTYPER111_EL0 | 671 HAFGRTR_EL2_AMEVTYPER110_EL0 | 672 HAFGRTR_EL2_AMEVTYPER19_EL0 | 673 HAFGRTR_EL2_AMEVTYPER18_EL0 | 674 HAFGRTR_EL2_AMEVTYPER17_EL0 | 675 HAFGRTR_EL2_AMEVTYPER16_EL0 | 676 HAFGRTR_EL2_AMEVTYPER15_EL0 | 677 HAFGRTR_EL2_AMEVTYPER14_EL0 | 678 HAFGRTR_EL2_AMEVTYPER13_EL0 | 679 HAFGRTR_EL2_AMEVTYPER12_EL0 | 680 HAFGRTR_EL2_AMEVTYPER11_EL0 | 681 HAFGRTR_EL2_AMEVTYPER10_EL0 | 682 HAFGRTR_EL2_AMEVCNTR115_EL0 | 683 HAFGRTR_EL2_AMEVCNTR114_EL0 | 684 HAFGRTR_EL2_AMEVCNTR113_EL0 | 685 HAFGRTR_EL2_AMEVCNTR112_EL0 | 686 HAFGRTR_EL2_AMEVCNTR111_EL0 | 687 HAFGRTR_EL2_AMEVCNTR110_EL0 | 688 HAFGRTR_EL2_AMEVCNTR19_EL0 | 689 HAFGRTR_EL2_AMEVCNTR18_EL0 | 690 HAFGRTR_EL2_AMEVCNTR17_EL0 | 691 HAFGRTR_EL2_AMEVCNTR16_EL0 | 692 HAFGRTR_EL2_AMEVCNTR15_EL0 | 693 HAFGRTR_EL2_AMEVCNTR14_EL0 | 694 HAFGRTR_EL2_AMEVCNTR13_EL0 | 695 HAFGRTR_EL2_AMEVCNTR12_EL0 | 696 HAFGRTR_EL2_AMEVCNTR11_EL0 | 697 HAFGRTR_EL2_AMEVCNTR10_EL0 | 698 HAFGRTR_EL2_AMCNTEN1 | 699 HAFGRTR_EL2_AMCNTEN0 | 700 HAFGRTR_EL2_AMEVCNTR03_EL0 | 701 HAFGRTR_EL2_AMEVCNTR02_EL0 | 702 HAFGRTR_EL2_AMEVCNTR01_EL0 | 703 HAFGRTR_EL2_AMEVCNTR00_EL0, 704 FEAT_AMUv1), 705 }; 706 707 static const struct reg_bits_to_feat_map hfgitr2_feat_map[] = { 708 NEEDS_FEAT(HFGITR2_EL2_nDCCIVAPS, FEAT_PoPS), 709 NEEDS_FEAT(HFGITR2_EL2_TSBCSYNC, FEAT_TRBEv1p1) 710 }; 711 712 static const struct reg_bits_to_feat_map hfgrtr2_feat_map[] = { 713 NEEDS_FEAT(HFGRTR2_EL2_nPFAR_EL1, FEAT_PFAR), 714 NEEDS_FEAT(HFGRTR2_EL2_nERXGSR_EL1, FEAT_RASv2), 715 NEEDS_FEAT(HFGRTR2_EL2_nACTLRALIAS_EL1 | 716 HFGRTR2_EL2_nACTLRMASK_EL1 | 717 HFGRTR2_EL2_nCPACRALIAS_EL1 | 718 HFGRTR2_EL2_nCPACRMASK_EL1 | 719 HFGRTR2_EL2_nSCTLR2MASK_EL1 | 720 HFGRTR2_EL2_nSCTLRALIAS2_EL1 | 721 HFGRTR2_EL2_nSCTLRALIAS_EL1 | 722 HFGRTR2_EL2_nSCTLRMASK_EL1 | 723 HFGRTR2_EL2_nTCR2ALIAS_EL1 | 724 HFGRTR2_EL2_nTCR2MASK_EL1 | 725 HFGRTR2_EL2_nTCRALIAS_EL1 | 726 HFGRTR2_EL2_nTCRMASK_EL1, 727 FEAT_SRMASK), 728 NEEDS_FEAT(HFGRTR2_EL2_nRCWSMASK_EL1, FEAT_THE), 729 }; 730 731 static const struct reg_bits_to_feat_map hfgwtr2_feat_map[] = { 732 NEEDS_FEAT(HFGWTR2_EL2_nPFAR_EL1, FEAT_PFAR), 733 NEEDS_FEAT(HFGWTR2_EL2_nACTLRALIAS_EL1 | 734 HFGWTR2_EL2_nACTLRMASK_EL1 | 735 HFGWTR2_EL2_nCPACRALIAS_EL1 | 736 HFGWTR2_EL2_nCPACRMASK_EL1 | 737 HFGWTR2_EL2_nSCTLR2MASK_EL1 | 738 HFGWTR2_EL2_nSCTLRALIAS2_EL1 | 739 HFGWTR2_EL2_nSCTLRALIAS_EL1 | 740 HFGWTR2_EL2_nSCTLRMASK_EL1 | 741 HFGWTR2_EL2_nTCR2ALIAS_EL1 | 742 HFGWTR2_EL2_nTCR2MASK_EL1 | 743 HFGWTR2_EL2_nTCRALIAS_EL1 | 744 HFGWTR2_EL2_nTCRMASK_EL1, 745 FEAT_SRMASK), 746 NEEDS_FEAT(HFGWTR2_EL2_nRCWSMASK_EL1, FEAT_THE), 747 }; 748 749 static const struct reg_bits_to_feat_map hdfgrtr2_feat_map[] = { 750 NEEDS_FEAT(HDFGRTR2_EL2_nMDSELR_EL1, FEAT_Debugv8p9), 751 NEEDS_FEAT(HDFGRTR2_EL2_nPMECR_EL1, feat_ebep_pmuv3_ss), 752 NEEDS_FEAT(HDFGRTR2_EL2_nTRCITECR_EL1, FEAT_ITE), 753 NEEDS_FEAT(HDFGRTR2_EL2_nPMICFILTR_EL0 | 754 HDFGRTR2_EL2_nPMICNTR_EL0, 755 FEAT_PMUv3_ICNTR), 756 NEEDS_FEAT(HDFGRTR2_EL2_nPMUACR_EL1, feat_pmuv3p9), 757 NEEDS_FEAT(HDFGRTR2_EL2_nPMSSCR_EL1 | 758 HDFGRTR2_EL2_nPMSSDATA, 759 FEAT_PMUv3_SS), 760 NEEDS_FEAT(HDFGRTR2_EL2_nPMIAR_EL1, FEAT_SEBEP), 761 NEEDS_FEAT(HDFGRTR2_EL2_nPMSDSFR_EL1, feat_spe_fds), 762 NEEDS_FEAT(HDFGRTR2_EL2_nPMBMAR_EL1, FEAT_SPE_nVM), 763 NEEDS_FEAT(HDFGRTR2_EL2_nSPMACCESSR_EL1 | 764 HDFGRTR2_EL2_nSPMCNTEN | 765 HDFGRTR2_EL2_nSPMCR_EL0 | 766 HDFGRTR2_EL2_nSPMDEVAFF_EL1 | 767 HDFGRTR2_EL2_nSPMEVCNTRn_EL0 | 768 HDFGRTR2_EL2_nSPMEVTYPERn_EL0| 769 HDFGRTR2_EL2_nSPMID | 770 HDFGRTR2_EL2_nSPMINTEN | 771 HDFGRTR2_EL2_nSPMOVS | 772 HDFGRTR2_EL2_nSPMSCR_EL1 | 773 HDFGRTR2_EL2_nSPMSELR_EL0, 774 FEAT_SPMU), 775 NEEDS_FEAT(HDFGRTR2_EL2_nMDSTEPOP_EL1, FEAT_STEP2), 776 NEEDS_FEAT(HDFGRTR2_EL2_nTRBMPAM_EL1, feat_trbe_mpam), 777 }; 778 779 static const struct reg_bits_to_feat_map hdfgwtr2_feat_map[] = { 780 NEEDS_FEAT(HDFGWTR2_EL2_nMDSELR_EL1, FEAT_Debugv8p9), 781 NEEDS_FEAT(HDFGWTR2_EL2_nPMECR_EL1, feat_ebep_pmuv3_ss), 782 NEEDS_FEAT(HDFGWTR2_EL2_nTRCITECR_EL1, FEAT_ITE), 783 NEEDS_FEAT(HDFGWTR2_EL2_nPMICFILTR_EL0 | 784 HDFGWTR2_EL2_nPMICNTR_EL0, 785 FEAT_PMUv3_ICNTR), 786 NEEDS_FEAT(HDFGWTR2_EL2_nPMUACR_EL1 | 787 HDFGWTR2_EL2_nPMZR_EL0, 788 feat_pmuv3p9), 789 NEEDS_FEAT(HDFGWTR2_EL2_nPMSSCR_EL1, FEAT_PMUv3_SS), 790 NEEDS_FEAT(HDFGWTR2_EL2_nPMIAR_EL1, FEAT_SEBEP), 791 NEEDS_FEAT(HDFGWTR2_EL2_nPMSDSFR_EL1, feat_spe_fds), 792 NEEDS_FEAT(HDFGWTR2_EL2_nPMBMAR_EL1, FEAT_SPE_nVM), 793 NEEDS_FEAT(HDFGWTR2_EL2_nSPMACCESSR_EL1 | 794 HDFGWTR2_EL2_nSPMCNTEN | 795 HDFGWTR2_EL2_nSPMCR_EL0 | 796 HDFGWTR2_EL2_nSPMEVCNTRn_EL0 | 797 HDFGWTR2_EL2_nSPMEVTYPERn_EL0| 798 HDFGWTR2_EL2_nSPMINTEN | 799 HDFGWTR2_EL2_nSPMOVS | 800 HDFGWTR2_EL2_nSPMSCR_EL1 | 801 HDFGWTR2_EL2_nSPMSELR_EL0, 802 FEAT_SPMU), 803 NEEDS_FEAT(HDFGWTR2_EL2_nMDSTEPOP_EL1, FEAT_STEP2), 804 NEEDS_FEAT(HDFGWTR2_EL2_nTRBMPAM_EL1, feat_trbe_mpam), 805 }; 806 807 static const struct reg_bits_to_feat_map hcrx_feat_map[] = { 808 NEEDS_FEAT(HCRX_EL2_PACMEn, feat_pauth_lr), 809 NEEDS_FEAT(HCRX_EL2_EnFPM, FEAT_FPMR), 810 NEEDS_FEAT(HCRX_EL2_GCSEn, FEAT_GCS), 811 NEEDS_FEAT(HCRX_EL2_EnIDCP128, FEAT_SYSREG128), 812 NEEDS_FEAT(HCRX_EL2_EnSDERR, feat_aderr), 813 NEEDS_FEAT(HCRX_EL2_TMEA, FEAT_DoubleFault2), 814 NEEDS_FEAT(HCRX_EL2_EnSNERR, feat_anerr), 815 NEEDS_FEAT(HCRX_EL2_D128En, FEAT_D128), 816 NEEDS_FEAT(HCRX_EL2_PTTWI, FEAT_THE), 817 NEEDS_FEAT(HCRX_EL2_SCTLR2En, FEAT_SCTLR2), 818 NEEDS_FEAT(HCRX_EL2_TCR2En, FEAT_TCR2), 819 NEEDS_FEAT(HCRX_EL2_MSCEn | 820 HCRX_EL2_MCE2, 821 FEAT_MOPS), 822 NEEDS_FEAT(HCRX_EL2_CMOW, FEAT_CMOW), 823 NEEDS_FEAT(HCRX_EL2_VFNMI | 824 HCRX_EL2_VINMI | 825 HCRX_EL2_TALLINT, 826 FEAT_NMI), 827 NEEDS_FEAT(HCRX_EL2_SMPME, feat_sme_smps), 828 NEEDS_FEAT(HCRX_EL2_FGTnXS | 829 HCRX_EL2_FnXS, 830 FEAT_XS), 831 NEEDS_FEAT(HCRX_EL2_EnASR, FEAT_LS64_V), 832 NEEDS_FEAT(HCRX_EL2_EnALS, FEAT_LS64), 833 NEEDS_FEAT(HCRX_EL2_EnAS0, FEAT_LS64_ACCDATA), 834 }; 835 836 static const struct reg_bits_to_feat_map hcr_feat_map[] = { 837 NEEDS_FEAT(HCR_EL2_TID0, FEAT_AA32EL0), 838 NEEDS_FEAT_FIXED(HCR_EL2_RW, compute_hcr_rw), 839 NEEDS_FEAT(HCR_EL2_HCD, not_feat_aa64el3), 840 NEEDS_FEAT(HCR_EL2_AMO | 841 HCR_EL2_BSU | 842 HCR_EL2_CD | 843 HCR_EL2_DC | 844 HCR_EL2_FB | 845 HCR_EL2_FMO | 846 HCR_EL2_ID | 847 HCR_EL2_IMO | 848 HCR_EL2_MIOCNCE | 849 HCR_EL2_PTW | 850 HCR_EL2_SWIO | 851 HCR_EL2_TACR | 852 HCR_EL2_TDZ | 853 HCR_EL2_TGE | 854 HCR_EL2_TID1 | 855 HCR_EL2_TID2 | 856 HCR_EL2_TID3 | 857 HCR_EL2_TIDCP | 858 HCR_EL2_TPCP | 859 HCR_EL2_TPU | 860 HCR_EL2_TRVM | 861 HCR_EL2_TSC | 862 HCR_EL2_TSW | 863 HCR_EL2_TTLB | 864 HCR_EL2_TVM | 865 HCR_EL2_TWE | 866 HCR_EL2_TWI | 867 HCR_EL2_VF | 868 HCR_EL2_VI | 869 HCR_EL2_VM | 870 HCR_EL2_VSE, 871 FEAT_AA64EL1), 872 NEEDS_FEAT(HCR_EL2_AMVOFFEN, FEAT_AMUv1p1), 873 NEEDS_FEAT(HCR_EL2_EnSCXT, feat_csv2_2_csv2_1p2), 874 NEEDS_FEAT(HCR_EL2_TICAB | 875 HCR_EL2_TID4 | 876 HCR_EL2_TOCU, 877 FEAT_EVT), 878 NEEDS_FEAT(HCR_EL2_TTLBIS | 879 HCR_EL2_TTLBOS, 880 FEAT_EVT_TTLBxS), 881 NEEDS_FEAT(HCR_EL2_TLOR, FEAT_LOR), 882 NEEDS_FEAT(HCR_EL2_ATA | 883 HCR_EL2_DCT | 884 HCR_EL2_TID5, 885 FEAT_MTE2), 886 NEEDS_FEAT(HCR_EL2_AT | /* Ignore the original FEAT_NV */ 887 HCR_EL2_NV2 | 888 HCR_EL2_NV, 889 feat_nv2), 890 NEEDS_FEAT(HCR_EL2_NV1, feat_nv2_e2h0_ni), /* Missing from JSON */ 891 NEEDS_FEAT(HCR_EL2_API | 892 HCR_EL2_APK, 893 feat_pauth), 894 NEEDS_FEAT(HCR_EL2_TEA | 895 HCR_EL2_TERR, 896 FEAT_RAS), 897 NEEDS_FEAT(HCR_EL2_FIEN, feat_rasv1p1), 898 NEEDS_FEAT(HCR_EL2_GPF, FEAT_RME), 899 NEEDS_FEAT(HCR_EL2_FWB, FEAT_S2FWB), 900 NEEDS_FEAT(HCR_EL2_TME, FEAT_TME), 901 NEEDS_FEAT(HCR_EL2_TWEDEL | 902 HCR_EL2_TWEDEn, 903 FEAT_TWED), 904 NEEDS_FEAT_FIXED(HCR_EL2_E2H, compute_hcr_e2h), 905 }; 906 907 static const struct reg_bits_to_feat_map sctlr2_feat_map[] = { 908 NEEDS_FEAT(SCTLR2_EL1_NMEA | 909 SCTLR2_EL1_EASE, 910 FEAT_DoubleFault2), 911 NEEDS_FEAT(SCTLR2_EL1_EnADERR, feat_aderr), 912 NEEDS_FEAT(SCTLR2_EL1_EnANERR, feat_anerr), 913 NEEDS_FEAT(SCTLR2_EL1_EnIDCP128, FEAT_SYSREG128), 914 NEEDS_FEAT(SCTLR2_EL1_EnPACM | 915 SCTLR2_EL1_EnPACM0, 916 feat_pauth_lr), 917 NEEDS_FEAT(SCTLR2_EL1_CPTA | 918 SCTLR2_EL1_CPTA0 | 919 SCTLR2_EL1_CPTM | 920 SCTLR2_EL1_CPTM0, 921 FEAT_CPA2), 922 }; 923 924 static const struct reg_bits_to_feat_map tcr2_el2_feat_map[] = { 925 NEEDS_FEAT(TCR2_EL2_FNG1 | 926 TCR2_EL2_FNG0 | 927 TCR2_EL2_A2, 928 feat_asid2_e2h1), 929 NEEDS_FEAT(TCR2_EL2_DisCH1 | 930 TCR2_EL2_DisCH0 | 931 TCR2_EL2_D128, 932 feat_d128_e2h1), 933 NEEDS_FEAT(TCR2_EL2_AMEC1, feat_mec_e2h1), 934 NEEDS_FEAT(TCR2_EL2_AMEC0, FEAT_MEC), 935 NEEDS_FEAT(TCR2_EL2_HAFT, FEAT_HAFT), 936 NEEDS_FEAT(TCR2_EL2_PTTWI | 937 TCR2_EL2_PnCH, 938 FEAT_THE), 939 NEEDS_FEAT(TCR2_EL2_AIE, FEAT_AIE), 940 NEEDS_FEAT(TCR2_EL2_POE | 941 TCR2_EL2_E0POE, 942 FEAT_S1POE), 943 NEEDS_FEAT(TCR2_EL2_PIE, FEAT_S1PIE), 944 }; 945 946 static const struct reg_bits_to_feat_map sctlr_el1_feat_map[] = { 947 NEEDS_FEAT(SCTLR_EL1_CP15BEN | 948 SCTLR_EL1_ITD | 949 SCTLR_EL1_SED, 950 FEAT_AA32EL0), 951 NEEDS_FEAT(SCTLR_EL1_BT0 | 952 SCTLR_EL1_BT1, 953 FEAT_BTI), 954 NEEDS_FEAT(SCTLR_EL1_CMOW, FEAT_CMOW), 955 NEEDS_FEAT(SCTLR_EL1_TSCXT, feat_csv2_2_csv2_1p2), 956 NEEDS_FEAT(SCTLR_EL1_EIS | 957 SCTLR_EL1_EOS, 958 FEAT_ExS), 959 NEEDS_FEAT(SCTLR_EL1_EnFPM, FEAT_FPMR), 960 NEEDS_FEAT(SCTLR_EL1_IESB, FEAT_IESB), 961 NEEDS_FEAT(SCTLR_EL1_EnALS, FEAT_LS64), 962 NEEDS_FEAT(SCTLR_EL1_EnAS0, FEAT_LS64_ACCDATA), 963 NEEDS_FEAT(SCTLR_EL1_EnASR, FEAT_LS64_V), 964 NEEDS_FEAT(SCTLR_EL1_nAA, FEAT_LSE2), 965 NEEDS_FEAT(SCTLR_EL1_LSMAOE | 966 SCTLR_EL1_nTLSMD, 967 FEAT_LSMAOC), 968 NEEDS_FEAT(SCTLR_EL1_EE, FEAT_MixedEnd), 969 NEEDS_FEAT(SCTLR_EL1_E0E, feat_mixedendel0), 970 NEEDS_FEAT(SCTLR_EL1_MSCEn, FEAT_MOPS), 971 NEEDS_FEAT(SCTLR_EL1_ATA0 | 972 SCTLR_EL1_ATA | 973 SCTLR_EL1_TCF0 | 974 SCTLR_EL1_TCF, 975 FEAT_MTE2), 976 NEEDS_FEAT(SCTLR_EL1_ITFSB, feat_mte_async), 977 NEEDS_FEAT(SCTLR_EL1_TCSO0 | 978 SCTLR_EL1_TCSO, 979 FEAT_MTE_STORE_ONLY), 980 NEEDS_FEAT(SCTLR_EL1_NMI | 981 SCTLR_EL1_SPINTMASK, 982 FEAT_NMI), 983 NEEDS_FEAT(SCTLR_EL1_SPAN, FEAT_PAN), 984 NEEDS_FEAT(SCTLR_EL1_EPAN, FEAT_PAN3), 985 NEEDS_FEAT(SCTLR_EL1_EnDA | 986 SCTLR_EL1_EnDB | 987 SCTLR_EL1_EnIA | 988 SCTLR_EL1_EnIB, 989 feat_pauth), 990 NEEDS_FEAT(SCTLR_EL1_EnTP2, FEAT_SME), 991 NEEDS_FEAT(SCTLR_EL1_EnRCTX, FEAT_SPECRES), 992 NEEDS_FEAT(SCTLR_EL1_DSSBS, FEAT_SSBS), 993 NEEDS_FEAT(SCTLR_EL1_TIDCP, FEAT_TIDCP1), 994 NEEDS_FEAT(SCTLR_EL1_TME0 | 995 SCTLR_EL1_TME | 996 SCTLR_EL1_TMT0 | 997 SCTLR_EL1_TMT, 998 FEAT_TME), 999 NEEDS_FEAT(SCTLR_EL1_TWEDEL | 1000 SCTLR_EL1_TWEDEn, 1001 FEAT_TWED), 1002 NEEDS_FEAT(SCTLR_EL1_UCI | 1003 SCTLR_EL1_EE | 1004 SCTLR_EL1_E0E | 1005 SCTLR_EL1_WXN | 1006 SCTLR_EL1_nTWE | 1007 SCTLR_EL1_nTWI | 1008 SCTLR_EL1_UCT | 1009 SCTLR_EL1_DZE | 1010 SCTLR_EL1_I | 1011 SCTLR_EL1_UMA | 1012 SCTLR_EL1_SA0 | 1013 SCTLR_EL1_SA | 1014 SCTLR_EL1_C | 1015 SCTLR_EL1_A | 1016 SCTLR_EL1_M, 1017 FEAT_AA64EL1), 1018 }; 1019 1020 static const struct reg_bits_to_feat_map mdcr_el2_feat_map[] = { 1021 NEEDS_FEAT(MDCR_EL2_EBWE, FEAT_Debugv8p9), 1022 NEEDS_FEAT(MDCR_EL2_TDOSA, FEAT_DoubleLock), 1023 NEEDS_FEAT(MDCR_EL2_PMEE, FEAT_EBEP), 1024 NEEDS_FEAT(MDCR_EL2_TDCC, FEAT_FGT), 1025 NEEDS_FEAT(MDCR_EL2_MTPME, FEAT_MTPMU), 1026 NEEDS_FEAT(MDCR_EL2_HPME | 1027 MDCR_EL2_HPMN | 1028 MDCR_EL2_TPMCR | 1029 MDCR_EL2_TPM, 1030 FEAT_PMUv3), 1031 NEEDS_FEAT(MDCR_EL2_HPMD, feat_pmuv3p1), 1032 NEEDS_FEAT(MDCR_EL2_HCCD | 1033 MDCR_EL2_HLP, 1034 feat_pmuv3p5), 1035 NEEDS_FEAT(MDCR_EL2_HPMFZO, feat_pmuv3p7), 1036 NEEDS_FEAT(MDCR_EL2_PMSSE, FEAT_PMUv3_SS), 1037 NEEDS_FEAT(MDCR_EL2_E2PB | 1038 MDCR_EL2_TPMS, 1039 FEAT_SPE), 1040 NEEDS_FEAT(MDCR_EL2_HPMFZS, FEAT_SPEv1p2), 1041 NEEDS_FEAT(MDCR_EL2_EnSPM, FEAT_SPMU), 1042 NEEDS_FEAT(MDCR_EL2_EnSTEPOP, FEAT_STEP2), 1043 NEEDS_FEAT(MDCR_EL2_E2TB, FEAT_TRBE), 1044 NEEDS_FEAT(MDCR_EL2_TTRF, FEAT_TRF), 1045 NEEDS_FEAT(MDCR_EL2_TDA | 1046 MDCR_EL2_TDE | 1047 MDCR_EL2_TDRA, 1048 FEAT_AA64EL1), 1049 }; 1050 1051 static void __init check_feat_map(const struct reg_bits_to_feat_map *map, 1052 int map_size, u64 res0, const char *str) 1053 { 1054 u64 mask = 0; 1055 1056 for (int i = 0; i < map_size; i++) 1057 mask |= map[i].bits; 1058 1059 if (mask != ~res0) 1060 kvm_err("Undefined %s behaviour, bits %016llx\n", 1061 str, mask ^ ~res0); 1062 } 1063 1064 void __init check_feature_map(void) 1065 { 1066 check_feat_map(hfgrtr_feat_map, ARRAY_SIZE(hfgrtr_feat_map), 1067 hfgrtr_masks.res0, hfgrtr_masks.str); 1068 check_feat_map(hfgwtr_feat_map, ARRAY_SIZE(hfgwtr_feat_map), 1069 hfgwtr_masks.res0, hfgwtr_masks.str); 1070 check_feat_map(hfgitr_feat_map, ARRAY_SIZE(hfgitr_feat_map), 1071 hfgitr_masks.res0, hfgitr_masks.str); 1072 check_feat_map(hdfgrtr_feat_map, ARRAY_SIZE(hdfgrtr_feat_map), 1073 hdfgrtr_masks.res0, hdfgrtr_masks.str); 1074 check_feat_map(hdfgwtr_feat_map, ARRAY_SIZE(hdfgwtr_feat_map), 1075 hdfgwtr_masks.res0, hdfgwtr_masks.str); 1076 check_feat_map(hafgrtr_feat_map, ARRAY_SIZE(hafgrtr_feat_map), 1077 hafgrtr_masks.res0, hafgrtr_masks.str); 1078 check_feat_map(hcrx_feat_map, ARRAY_SIZE(hcrx_feat_map), 1079 __HCRX_EL2_RES0, "HCRX_EL2"); 1080 check_feat_map(hcr_feat_map, ARRAY_SIZE(hcr_feat_map), 1081 HCR_EL2_RES0, "HCR_EL2"); 1082 check_feat_map(sctlr2_feat_map, ARRAY_SIZE(sctlr2_feat_map), 1083 SCTLR2_EL1_RES0, "SCTLR2_EL1"); 1084 check_feat_map(tcr2_el2_feat_map, ARRAY_SIZE(tcr2_el2_feat_map), 1085 TCR2_EL2_RES0, "TCR2_EL2"); 1086 check_feat_map(sctlr_el1_feat_map, ARRAY_SIZE(sctlr_el1_feat_map), 1087 SCTLR_EL1_RES0, "SCTLR_EL1"); 1088 check_feat_map(mdcr_el2_feat_map, ARRAY_SIZE(mdcr_el2_feat_map), 1089 MDCR_EL2_RES0, "MDCR_EL2"); 1090 } 1091 1092 static bool idreg_feat_match(struct kvm *kvm, const struct reg_bits_to_feat_map *map) 1093 { 1094 u64 regval = kvm->arch.id_regs[map->regidx]; 1095 u64 regfld = (regval >> map->shift) & GENMASK(map->width - 1, 0); 1096 1097 if (map->sign) { 1098 s64 sfld = sign_extend64(regfld, map->width - 1); 1099 s64 slim = sign_extend64(map->lo_lim, map->width - 1); 1100 return sfld >= slim; 1101 } else { 1102 return regfld >= map->lo_lim; 1103 } 1104 } 1105 1106 static u64 __compute_fixed_bits(struct kvm *kvm, 1107 const struct reg_bits_to_feat_map *map, 1108 int map_size, 1109 u64 *fixed_bits, 1110 unsigned long require, 1111 unsigned long exclude) 1112 { 1113 u64 val = 0; 1114 1115 for (int i = 0; i < map_size; i++) { 1116 bool match; 1117 1118 if ((map[i].flags & require) != require) 1119 continue; 1120 1121 if (map[i].flags & exclude) 1122 continue; 1123 1124 if (map[i].flags & CALL_FUNC) 1125 match = (map[i].flags & FIXED_VALUE) ? 1126 map[i].fval(kvm, fixed_bits) : 1127 map[i].match(kvm); 1128 else 1129 match = idreg_feat_match(kvm, &map[i]); 1130 1131 if (!match || (map[i].flags & FIXED_VALUE)) 1132 val |= map[i].bits; 1133 } 1134 1135 return val; 1136 } 1137 1138 static u64 compute_res0_bits(struct kvm *kvm, 1139 const struct reg_bits_to_feat_map *map, 1140 int map_size, 1141 unsigned long require, 1142 unsigned long exclude) 1143 { 1144 return __compute_fixed_bits(kvm, map, map_size, NULL, 1145 require, exclude | FIXED_VALUE); 1146 } 1147 1148 static u64 compute_fixed_bits(struct kvm *kvm, 1149 const struct reg_bits_to_feat_map *map, 1150 int map_size, 1151 u64 *fixed_bits, 1152 unsigned long require, 1153 unsigned long exclude) 1154 { 1155 return __compute_fixed_bits(kvm, map, map_size, fixed_bits, 1156 require | FIXED_VALUE, exclude); 1157 } 1158 1159 void compute_fgu(struct kvm *kvm, enum fgt_group_id fgt) 1160 { 1161 u64 val = 0; 1162 1163 switch (fgt) { 1164 case HFGRTR_GROUP: 1165 val |= compute_res0_bits(kvm, hfgrtr_feat_map, 1166 ARRAY_SIZE(hfgrtr_feat_map), 1167 0, NEVER_FGU); 1168 val |= compute_res0_bits(kvm, hfgwtr_feat_map, 1169 ARRAY_SIZE(hfgwtr_feat_map), 1170 0, NEVER_FGU); 1171 break; 1172 case HFGITR_GROUP: 1173 val |= compute_res0_bits(kvm, hfgitr_feat_map, 1174 ARRAY_SIZE(hfgitr_feat_map), 1175 0, NEVER_FGU); 1176 break; 1177 case HDFGRTR_GROUP: 1178 val |= compute_res0_bits(kvm, hdfgrtr_feat_map, 1179 ARRAY_SIZE(hdfgrtr_feat_map), 1180 0, NEVER_FGU); 1181 val |= compute_res0_bits(kvm, hdfgwtr_feat_map, 1182 ARRAY_SIZE(hdfgwtr_feat_map), 1183 0, NEVER_FGU); 1184 break; 1185 case HAFGRTR_GROUP: 1186 val |= compute_res0_bits(kvm, hafgrtr_feat_map, 1187 ARRAY_SIZE(hafgrtr_feat_map), 1188 0, NEVER_FGU); 1189 break; 1190 case HFGRTR2_GROUP: 1191 val |= compute_res0_bits(kvm, hfgrtr2_feat_map, 1192 ARRAY_SIZE(hfgrtr2_feat_map), 1193 0, NEVER_FGU); 1194 val |= compute_res0_bits(kvm, hfgwtr2_feat_map, 1195 ARRAY_SIZE(hfgwtr2_feat_map), 1196 0, NEVER_FGU); 1197 break; 1198 case HFGITR2_GROUP: 1199 val |= compute_res0_bits(kvm, hfgitr2_feat_map, 1200 ARRAY_SIZE(hfgitr2_feat_map), 1201 0, NEVER_FGU); 1202 break; 1203 case HDFGRTR2_GROUP: 1204 val |= compute_res0_bits(kvm, hdfgrtr2_feat_map, 1205 ARRAY_SIZE(hdfgrtr2_feat_map), 1206 0, NEVER_FGU); 1207 val |= compute_res0_bits(kvm, hdfgwtr2_feat_map, 1208 ARRAY_SIZE(hdfgwtr2_feat_map), 1209 0, NEVER_FGU); 1210 break; 1211 default: 1212 BUG(); 1213 } 1214 1215 kvm->arch.fgu[fgt] = val; 1216 } 1217 1218 void get_reg_fixed_bits(struct kvm *kvm, enum vcpu_sysreg reg, u64 *res0, u64 *res1) 1219 { 1220 u64 fixed = 0, mask; 1221 1222 switch (reg) { 1223 case HFGRTR_EL2: 1224 *res0 = compute_res0_bits(kvm, hfgrtr_feat_map, 1225 ARRAY_SIZE(hfgrtr_feat_map), 0, 0); 1226 *res0 |= hfgrtr_masks.res0; 1227 *res1 = HFGRTR_EL2_RES1; 1228 break; 1229 case HFGWTR_EL2: 1230 *res0 = compute_res0_bits(kvm, hfgwtr_feat_map, 1231 ARRAY_SIZE(hfgwtr_feat_map), 0, 0); 1232 *res0 |= hfgwtr_masks.res0; 1233 *res1 = HFGWTR_EL2_RES1; 1234 break; 1235 case HFGITR_EL2: 1236 *res0 = compute_res0_bits(kvm, hfgitr_feat_map, 1237 ARRAY_SIZE(hfgitr_feat_map), 0, 0); 1238 *res0 |= hfgitr_masks.res0; 1239 *res1 = HFGITR_EL2_RES1; 1240 break; 1241 case HDFGRTR_EL2: 1242 *res0 = compute_res0_bits(kvm, hdfgrtr_feat_map, 1243 ARRAY_SIZE(hdfgrtr_feat_map), 0, 0); 1244 *res0 |= hdfgrtr_masks.res0; 1245 *res1 = HDFGRTR_EL2_RES1; 1246 break; 1247 case HDFGWTR_EL2: 1248 *res0 = compute_res0_bits(kvm, hdfgwtr_feat_map, 1249 ARRAY_SIZE(hdfgwtr_feat_map), 0, 0); 1250 *res0 |= hdfgwtr_masks.res0; 1251 *res1 = HDFGWTR_EL2_RES1; 1252 break; 1253 case HAFGRTR_EL2: 1254 *res0 = compute_res0_bits(kvm, hafgrtr_feat_map, 1255 ARRAY_SIZE(hafgrtr_feat_map), 0, 0); 1256 *res0 |= hafgrtr_masks.res0; 1257 *res1 = HAFGRTR_EL2_RES1; 1258 break; 1259 case HFGRTR2_EL2: 1260 *res0 = compute_res0_bits(kvm, hfgrtr2_feat_map, 1261 ARRAY_SIZE(hfgrtr2_feat_map), 0, 0); 1262 *res0 |= hfgrtr2_masks.res0; 1263 *res1 = HFGRTR2_EL2_RES1; 1264 break; 1265 case HFGWTR2_EL2: 1266 *res0 = compute_res0_bits(kvm, hfgwtr2_feat_map, 1267 ARRAY_SIZE(hfgwtr2_feat_map), 0, 0); 1268 *res0 |= hfgwtr2_masks.res0; 1269 *res1 = HFGWTR2_EL2_RES1; 1270 break; 1271 case HFGITR2_EL2: 1272 *res0 = compute_res0_bits(kvm, hfgitr2_feat_map, 1273 ARRAY_SIZE(hfgitr2_feat_map), 0, 0); 1274 *res0 |= hfgitr2_masks.res0; 1275 *res1 = HFGITR2_EL2_RES1; 1276 break; 1277 case HDFGRTR2_EL2: 1278 *res0 = compute_res0_bits(kvm, hdfgrtr2_feat_map, 1279 ARRAY_SIZE(hdfgrtr2_feat_map), 0, 0); 1280 *res0 |= hdfgrtr2_masks.res0; 1281 *res1 = HDFGRTR2_EL2_RES1; 1282 break; 1283 case HDFGWTR2_EL2: 1284 *res0 = compute_res0_bits(kvm, hdfgwtr2_feat_map, 1285 ARRAY_SIZE(hdfgwtr2_feat_map), 0, 0); 1286 *res0 |= hdfgwtr2_masks.res0; 1287 *res1 = HDFGWTR2_EL2_RES1; 1288 break; 1289 case HCRX_EL2: 1290 *res0 = compute_res0_bits(kvm, hcrx_feat_map, 1291 ARRAY_SIZE(hcrx_feat_map), 0, 0); 1292 *res0 |= __HCRX_EL2_RES0; 1293 *res1 = __HCRX_EL2_RES1; 1294 break; 1295 case HCR_EL2: 1296 mask = compute_fixed_bits(kvm, hcr_feat_map, 1297 ARRAY_SIZE(hcr_feat_map), &fixed, 1298 0, 0); 1299 *res0 = compute_res0_bits(kvm, hcr_feat_map, 1300 ARRAY_SIZE(hcr_feat_map), 0, 0); 1301 *res0 |= HCR_EL2_RES0 | (mask & ~fixed); 1302 *res1 = HCR_EL2_RES1 | (mask & fixed); 1303 break; 1304 case SCTLR2_EL1: 1305 case SCTLR2_EL2: 1306 *res0 = compute_res0_bits(kvm, sctlr2_feat_map, 1307 ARRAY_SIZE(sctlr2_feat_map), 0, 0); 1308 *res0 |= SCTLR2_EL1_RES0; 1309 *res1 = SCTLR2_EL1_RES1; 1310 break; 1311 case TCR2_EL2: 1312 *res0 = compute_res0_bits(kvm, tcr2_el2_feat_map, 1313 ARRAY_SIZE(tcr2_el2_feat_map), 0, 0); 1314 *res0 |= TCR2_EL2_RES0; 1315 *res1 = TCR2_EL2_RES1; 1316 break; 1317 case SCTLR_EL1: 1318 *res0 = compute_res0_bits(kvm, sctlr_el1_feat_map, 1319 ARRAY_SIZE(sctlr_el1_feat_map), 0, 0); 1320 *res0 |= SCTLR_EL1_RES0; 1321 *res1 = SCTLR_EL1_RES1; 1322 break; 1323 case MDCR_EL2: 1324 *res0 = compute_res0_bits(kvm, mdcr_el2_feat_map, 1325 ARRAY_SIZE(mdcr_el2_feat_map), 0, 0); 1326 *res0 |= MDCR_EL2_RES0; 1327 *res1 = MDCR_EL2_RES1; 1328 break; 1329 default: 1330 WARN_ON_ONCE(1); 1331 *res0 = *res1 = 0; 1332 break; 1333 } 1334 } 1335