1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Based on arch/arm/kernel/setup.c 4 * 5 * Copyright (C) 1995-2001 Russell King 6 * Copyright (C) 2012 ARM Ltd. 7 */ 8 9 #include <linux/acpi.h> 10 #include <linux/export.h> 11 #include <linux/kernel.h> 12 #include <linux/stddef.h> 13 #include <linux/ioport.h> 14 #include <linux/delay.h> 15 #include <linux/initrd.h> 16 #include <linux/console.h> 17 #include <linux/cache.h> 18 #include <linux/screen_info.h> 19 #include <linux/init.h> 20 #include <linux/kexec.h> 21 #include <linux/root_dev.h> 22 #include <linux/cpu.h> 23 #include <linux/interrupt.h> 24 #include <linux/smp.h> 25 #include <linux/fs.h> 26 #include <linux/panic_notifier.h> 27 #include <linux/proc_fs.h> 28 #include <linux/memblock.h> 29 #include <linux/of_fdt.h> 30 #include <linux/efi.h> 31 #include <linux/psci.h> 32 #include <linux/sched/task.h> 33 #include <linux/mm.h> 34 35 #include <asm/acpi.h> 36 #include <asm/fixmap.h> 37 #include <asm/cpu.h> 38 #include <asm/cputype.h> 39 #include <asm/daifflags.h> 40 #include <asm/elf.h> 41 #include <asm/cpufeature.h> 42 #include <asm/cpu_ops.h> 43 #include <asm/kasan.h> 44 #include <asm/numa.h> 45 #include <asm/sections.h> 46 #include <asm/setup.h> 47 #include <asm/smp_plat.h> 48 #include <asm/cacheflush.h> 49 #include <asm/tlbflush.h> 50 #include <asm/traps.h> 51 #include <asm/efi.h> 52 #include <asm/xen/hypervisor.h> 53 #include <asm/mmu_context.h> 54 55 static int num_standard_resources; 56 static struct resource *standard_resources; 57 58 phys_addr_t __fdt_pointer __initdata; 59 60 /* 61 * Standard memory resources 62 */ 63 static struct resource mem_res[] = { 64 { 65 .name = "Kernel code", 66 .start = 0, 67 .end = 0, 68 .flags = IORESOURCE_SYSTEM_RAM 69 }, 70 { 71 .name = "Kernel data", 72 .start = 0, 73 .end = 0, 74 .flags = IORESOURCE_SYSTEM_RAM 75 } 76 }; 77 78 #define kernel_code mem_res[0] 79 #define kernel_data mem_res[1] 80 81 /* 82 * The recorded values of x0 .. x3 upon kernel entry. 83 */ 84 u64 __cacheline_aligned boot_args[4]; 85 86 void __init smp_setup_processor_id(void) 87 { 88 u64 mpidr = read_cpuid_mpidr() & MPIDR_HWID_BITMASK; 89 set_cpu_logical_map(0, mpidr); 90 91 pr_info("Booting Linux on physical CPU 0x%010lx [0x%08x]\n", 92 (unsigned long)mpidr, read_cpuid_id()); 93 } 94 95 bool arch_match_cpu_phys_id(int cpu, u64 phys_id) 96 { 97 return phys_id == cpu_logical_map(cpu); 98 } 99 100 struct mpidr_hash mpidr_hash; 101 /** 102 * smp_build_mpidr_hash - Pre-compute shifts required at each affinity 103 * level in order to build a linear index from an 104 * MPIDR value. Resulting algorithm is a collision 105 * free hash carried out through shifting and ORing 106 */ 107 static void __init smp_build_mpidr_hash(void) 108 { 109 u32 i, affinity, fs[4], bits[4], ls; 110 u64 mask = 0; 111 /* 112 * Pre-scan the list of MPIDRS and filter out bits that do 113 * not contribute to affinity levels, ie they never toggle. 114 */ 115 for_each_possible_cpu(i) 116 mask |= (cpu_logical_map(i) ^ cpu_logical_map(0)); 117 pr_debug("mask of set bits %#llx\n", mask); 118 /* 119 * Find and stash the last and first bit set at all affinity levels to 120 * check how many bits are required to represent them. 121 */ 122 for (i = 0; i < 4; i++) { 123 affinity = MPIDR_AFFINITY_LEVEL(mask, i); 124 /* 125 * Find the MSB bit and LSB bits position 126 * to determine how many bits are required 127 * to express the affinity level. 128 */ 129 ls = fls(affinity); 130 fs[i] = affinity ? ffs(affinity) - 1 : 0; 131 bits[i] = ls - fs[i]; 132 } 133 /* 134 * An index can be created from the MPIDR_EL1 by isolating the 135 * significant bits at each affinity level and by shifting 136 * them in order to compress the 32 bits values space to a 137 * compressed set of values. This is equivalent to hashing 138 * the MPIDR_EL1 through shifting and ORing. It is a collision free 139 * hash though not minimal since some levels might contain a number 140 * of CPUs that is not an exact power of 2 and their bit 141 * representation might contain holes, eg MPIDR_EL1[7:0] = {0x2, 0x80}. 142 */ 143 mpidr_hash.shift_aff[0] = MPIDR_LEVEL_SHIFT(0) + fs[0]; 144 mpidr_hash.shift_aff[1] = MPIDR_LEVEL_SHIFT(1) + fs[1] - bits[0]; 145 mpidr_hash.shift_aff[2] = MPIDR_LEVEL_SHIFT(2) + fs[2] - 146 (bits[1] + bits[0]); 147 mpidr_hash.shift_aff[3] = MPIDR_LEVEL_SHIFT(3) + 148 fs[3] - (bits[2] + bits[1] + bits[0]); 149 mpidr_hash.mask = mask; 150 mpidr_hash.bits = bits[3] + bits[2] + bits[1] + bits[0]; 151 pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] aff3[%u] mask[%#llx] bits[%u]\n", 152 mpidr_hash.shift_aff[0], 153 mpidr_hash.shift_aff[1], 154 mpidr_hash.shift_aff[2], 155 mpidr_hash.shift_aff[3], 156 mpidr_hash.mask, 157 mpidr_hash.bits); 158 /* 159 * 4x is an arbitrary value used to warn on a hash table much bigger 160 * than expected on most systems. 161 */ 162 if (mpidr_hash_size() > 4 * num_possible_cpus()) 163 pr_warn("Large number of MPIDR hash buckets detected\n"); 164 } 165 166 static void __init setup_machine_fdt(phys_addr_t dt_phys) 167 { 168 int size; 169 void *dt_virt = fixmap_remap_fdt(dt_phys, &size, PAGE_KERNEL); 170 const char *name; 171 172 if (dt_virt) 173 memblock_reserve(dt_phys, size); 174 175 if (!dt_virt || !early_init_dt_scan(dt_virt)) { 176 pr_crit("\n" 177 "Error: invalid device tree blob at physical address %pa (virtual address 0x%px)\n" 178 "The dtb must be 8-byte aligned and must not exceed 2 MB in size\n" 179 "\nPlease check your bootloader.", 180 &dt_phys, dt_virt); 181 182 /* 183 * Note that in this _really_ early stage we cannot even BUG() 184 * or oops, so the least terrible thing to do is cpu_relax(), 185 * or else we could end-up printing non-initialized data, etc. 186 */ 187 while (true) 188 cpu_relax(); 189 } 190 191 /* Early fixups are done, map the FDT as read-only now */ 192 fixmap_remap_fdt(dt_phys, &size, PAGE_KERNEL_RO); 193 194 name = of_flat_dt_get_machine_name(); 195 if (!name) 196 return; 197 198 pr_info("Machine model: %s\n", name); 199 dump_stack_set_arch_desc("%s (DT)", name); 200 } 201 202 static void __init request_standard_resources(void) 203 { 204 struct memblock_region *region; 205 struct resource *res; 206 unsigned long i = 0; 207 size_t res_size; 208 209 kernel_code.start = __pa_symbol(_stext); 210 kernel_code.end = __pa_symbol(__init_begin - 1); 211 kernel_data.start = __pa_symbol(_sdata); 212 kernel_data.end = __pa_symbol(_end - 1); 213 insert_resource(&iomem_resource, &kernel_code); 214 insert_resource(&iomem_resource, &kernel_data); 215 216 num_standard_resources = memblock.memory.cnt; 217 res_size = num_standard_resources * sizeof(*standard_resources); 218 standard_resources = memblock_alloc(res_size, SMP_CACHE_BYTES); 219 if (!standard_resources) 220 panic("%s: Failed to allocate %zu bytes\n", __func__, res_size); 221 222 for_each_mem_region(region) { 223 res = &standard_resources[i++]; 224 if (memblock_is_nomap(region)) { 225 res->name = "reserved"; 226 res->flags = IORESOURCE_MEM; 227 res->start = __pfn_to_phys(memblock_region_reserved_base_pfn(region)); 228 res->end = __pfn_to_phys(memblock_region_reserved_end_pfn(region)) - 1; 229 } else { 230 res->name = "System RAM"; 231 res->flags = IORESOURCE_SYSTEM_RAM | IORESOURCE_BUSY; 232 res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region)); 233 res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1; 234 } 235 236 insert_resource(&iomem_resource, res); 237 } 238 } 239 240 static int __init reserve_memblock_reserved_regions(void) 241 { 242 u64 i, j; 243 244 for (i = 0; i < num_standard_resources; ++i) { 245 struct resource *mem = &standard_resources[i]; 246 phys_addr_t r_start, r_end, mem_size = resource_size(mem); 247 248 if (!memblock_is_region_reserved(mem->start, mem_size)) 249 continue; 250 251 for_each_reserved_mem_range(j, &r_start, &r_end) { 252 resource_size_t start, end; 253 254 start = max(PFN_PHYS(PFN_DOWN(r_start)), mem->start); 255 end = min(PFN_PHYS(PFN_UP(r_end)) - 1, mem->end); 256 257 if (start > mem->end || end < mem->start) 258 continue; 259 260 reserve_region_with_split(mem, start, end, "reserved"); 261 } 262 } 263 264 return 0; 265 } 266 arch_initcall(reserve_memblock_reserved_regions); 267 268 u64 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_HWID }; 269 270 u64 cpu_logical_map(unsigned int cpu) 271 { 272 return __cpu_logical_map[cpu]; 273 } 274 275 void __init __no_sanitize_address setup_arch(char **cmdline_p) 276 { 277 setup_initial_init_mm(_stext, _etext, _edata, _end); 278 279 *cmdline_p = boot_command_line; 280 281 /* 282 * If know now we are going to need KPTI then use non-global 283 * mappings from the start, avoiding the cost of rewriting 284 * everything later. 285 */ 286 arm64_use_ng_mappings = kaslr_requires_kpti(); 287 288 early_fixmap_init(); 289 early_ioremap_init(); 290 291 setup_machine_fdt(__fdt_pointer); 292 293 /* 294 * Initialise the static keys early as they may be enabled by the 295 * cpufeature code and early parameters. 296 */ 297 jump_label_init(); 298 parse_early_param(); 299 300 /* 301 * Unmask asynchronous aborts and fiq after bringing up possible 302 * earlycon. (Report possible System Errors once we can report this 303 * occurred). 304 */ 305 local_daif_restore(DAIF_PROCCTX_NOIRQ); 306 307 /* 308 * TTBR0 is only used for the identity mapping at this stage. Make it 309 * point to zero page to avoid speculatively fetching new entries. 310 */ 311 cpu_uninstall_idmap(); 312 313 xen_early_init(); 314 efi_init(); 315 316 if (!efi_enabled(EFI_BOOT) && ((u64)_text % MIN_KIMG_ALIGN) != 0) 317 pr_warn(FW_BUG "Kernel image misaligned at boot, please fix your bootloader!"); 318 319 arm64_memblock_init(); 320 321 paging_init(); 322 323 acpi_table_upgrade(); 324 325 /* Parse the ACPI tables for possible boot-time configuration */ 326 acpi_boot_table_init(); 327 328 if (acpi_disabled) 329 unflatten_device_tree(); 330 331 bootmem_init(); 332 333 kasan_init(); 334 335 request_standard_resources(); 336 337 early_ioremap_reset(); 338 339 if (acpi_disabled) 340 psci_dt_init(); 341 else 342 psci_acpi_init(); 343 344 init_bootcpu_ops(); 345 smp_init_cpus(); 346 smp_build_mpidr_hash(); 347 348 /* Init percpu seeds for random tags after cpus are set up. */ 349 kasan_init_sw_tags(); 350 351 #ifdef CONFIG_ARM64_SW_TTBR0_PAN 352 /* 353 * Make sure init_thread_info.ttbr0 always generates translation 354 * faults in case uaccess_enable() is inadvertently called by the init 355 * thread. 356 */ 357 init_task.thread_info.ttbr0 = phys_to_ttbr(__pa_symbol(reserved_pg_dir)); 358 #endif 359 360 if (boot_args[1] || boot_args[2] || boot_args[3]) { 361 pr_err("WARNING: x1-x3 nonzero in violation of boot protocol:\n" 362 "\tx1: %016llx\n\tx2: %016llx\n\tx3: %016llx\n" 363 "This indicates a broken bootloader or old kernel\n", 364 boot_args[1], boot_args[2], boot_args[3]); 365 } 366 } 367 368 static inline bool cpu_can_disable(unsigned int cpu) 369 { 370 #ifdef CONFIG_HOTPLUG_CPU 371 const struct cpu_operations *ops = get_cpu_ops(cpu); 372 373 if (ops && ops->cpu_can_disable) 374 return ops->cpu_can_disable(cpu); 375 #endif 376 return false; 377 } 378 379 static int __init topology_init(void) 380 { 381 int i; 382 383 for_each_possible_cpu(i) { 384 struct cpu *cpu = &per_cpu(cpu_data.cpu, i); 385 cpu->hotpluggable = cpu_can_disable(i); 386 register_cpu(cpu, i); 387 } 388 389 return 0; 390 } 391 subsys_initcall(topology_init); 392 393 static void dump_kernel_offset(void) 394 { 395 const unsigned long offset = kaslr_offset(); 396 397 if (IS_ENABLED(CONFIG_RANDOMIZE_BASE) && offset > 0) { 398 pr_emerg("Kernel Offset: 0x%lx from 0x%lx\n", 399 offset, KIMAGE_VADDR); 400 pr_emerg("PHYS_OFFSET: 0x%llx\n", PHYS_OFFSET); 401 } else { 402 pr_emerg("Kernel Offset: disabled\n"); 403 } 404 } 405 406 static int arm64_panic_block_dump(struct notifier_block *self, 407 unsigned long v, void *p) 408 { 409 dump_kernel_offset(); 410 dump_cpu_features(); 411 dump_mem_limit(); 412 return 0; 413 } 414 415 static struct notifier_block arm64_panic_block = { 416 .notifier_call = arm64_panic_block_dump 417 }; 418 419 static int __init register_arm64_panic_block(void) 420 { 421 atomic_notifier_chain_register(&panic_notifier_list, 422 &arm64_panic_block); 423 return 0; 424 } 425 device_initcall(register_arm64_panic_block); 426