1 /* 2 * Based on arch/arm/kernel/setup.c 3 * 4 * Copyright (C) 1995-2001 Russell King 5 * Copyright (C) 2012 ARM Ltd. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include <linux/acpi.h> 21 #include <linux/export.h> 22 #include <linux/kernel.h> 23 #include <linux/stddef.h> 24 #include <linux/ioport.h> 25 #include <linux/delay.h> 26 #include <linux/utsname.h> 27 #include <linux/initrd.h> 28 #include <linux/console.h> 29 #include <linux/cache.h> 30 #include <linux/bootmem.h> 31 #include <linux/seq_file.h> 32 #include <linux/screen_info.h> 33 #include <linux/init.h> 34 #include <linux/kexec.h> 35 #include <linux/crash_dump.h> 36 #include <linux/root_dev.h> 37 #include <linux/cpu.h> 38 #include <linux/interrupt.h> 39 #include <linux/smp.h> 40 #include <linux/fs.h> 41 #include <linux/proc_fs.h> 42 #include <linux/memblock.h> 43 #include <linux/of_iommu.h> 44 #include <linux/of_fdt.h> 45 #include <linux/of_platform.h> 46 #include <linux/efi.h> 47 #include <linux/personality.h> 48 #include <linux/psci.h> 49 50 #include <asm/acpi.h> 51 #include <asm/fixmap.h> 52 #include <asm/cpu.h> 53 #include <asm/cputype.h> 54 #include <asm/elf.h> 55 #include <asm/cpufeature.h> 56 #include <asm/cpu_ops.h> 57 #include <asm/kasan.h> 58 #include <asm/sections.h> 59 #include <asm/setup.h> 60 #include <asm/smp_plat.h> 61 #include <asm/cacheflush.h> 62 #include <asm/tlbflush.h> 63 #include <asm/traps.h> 64 #include <asm/memblock.h> 65 #include <asm/efi.h> 66 #include <asm/xen/hypervisor.h> 67 68 unsigned long elf_hwcap __read_mostly; 69 EXPORT_SYMBOL_GPL(elf_hwcap); 70 71 #ifdef CONFIG_COMPAT 72 #define COMPAT_ELF_HWCAP_DEFAULT \ 73 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 74 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 75 COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\ 76 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\ 77 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\ 78 COMPAT_HWCAP_LPAE) 79 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 80 unsigned int compat_elf_hwcap2 __read_mostly; 81 #endif 82 83 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS); 84 85 phys_addr_t __fdt_pointer __initdata; 86 87 /* 88 * Standard memory resources 89 */ 90 static struct resource mem_res[] = { 91 { 92 .name = "Kernel code", 93 .start = 0, 94 .end = 0, 95 .flags = IORESOURCE_MEM 96 }, 97 { 98 .name = "Kernel data", 99 .start = 0, 100 .end = 0, 101 .flags = IORESOURCE_MEM 102 } 103 }; 104 105 #define kernel_code mem_res[0] 106 #define kernel_data mem_res[1] 107 108 /* 109 * The recorded values of x0 .. x3 upon kernel entry. 110 */ 111 u64 __cacheline_aligned boot_args[4]; 112 113 void __init smp_setup_processor_id(void) 114 { 115 u64 mpidr = read_cpuid_mpidr() & MPIDR_HWID_BITMASK; 116 cpu_logical_map(0) = mpidr; 117 118 /* 119 * clear __my_cpu_offset on boot CPU to avoid hang caused by 120 * using percpu variable early, for example, lockdep will 121 * access percpu variable inside lock_release 122 */ 123 set_my_cpu_offset(0); 124 pr_info("Booting Linux on physical CPU 0x%lx\n", (unsigned long)mpidr); 125 } 126 127 bool arch_match_cpu_phys_id(int cpu, u64 phys_id) 128 { 129 return phys_id == cpu_logical_map(cpu); 130 } 131 132 struct mpidr_hash mpidr_hash; 133 /** 134 * smp_build_mpidr_hash - Pre-compute shifts required at each affinity 135 * level in order to build a linear index from an 136 * MPIDR value. Resulting algorithm is a collision 137 * free hash carried out through shifting and ORing 138 */ 139 static void __init smp_build_mpidr_hash(void) 140 { 141 u32 i, affinity, fs[4], bits[4], ls; 142 u64 mask = 0; 143 /* 144 * Pre-scan the list of MPIDRS and filter out bits that do 145 * not contribute to affinity levels, ie they never toggle. 146 */ 147 for_each_possible_cpu(i) 148 mask |= (cpu_logical_map(i) ^ cpu_logical_map(0)); 149 pr_debug("mask of set bits %#llx\n", mask); 150 /* 151 * Find and stash the last and first bit set at all affinity levels to 152 * check how many bits are required to represent them. 153 */ 154 for (i = 0; i < 4; i++) { 155 affinity = MPIDR_AFFINITY_LEVEL(mask, i); 156 /* 157 * Find the MSB bit and LSB bits position 158 * to determine how many bits are required 159 * to express the affinity level. 160 */ 161 ls = fls(affinity); 162 fs[i] = affinity ? ffs(affinity) - 1 : 0; 163 bits[i] = ls - fs[i]; 164 } 165 /* 166 * An index can be created from the MPIDR_EL1 by isolating the 167 * significant bits at each affinity level and by shifting 168 * them in order to compress the 32 bits values space to a 169 * compressed set of values. This is equivalent to hashing 170 * the MPIDR_EL1 through shifting and ORing. It is a collision free 171 * hash though not minimal since some levels might contain a number 172 * of CPUs that is not an exact power of 2 and their bit 173 * representation might contain holes, eg MPIDR_EL1[7:0] = {0x2, 0x80}. 174 */ 175 mpidr_hash.shift_aff[0] = MPIDR_LEVEL_SHIFT(0) + fs[0]; 176 mpidr_hash.shift_aff[1] = MPIDR_LEVEL_SHIFT(1) + fs[1] - bits[0]; 177 mpidr_hash.shift_aff[2] = MPIDR_LEVEL_SHIFT(2) + fs[2] - 178 (bits[1] + bits[0]); 179 mpidr_hash.shift_aff[3] = MPIDR_LEVEL_SHIFT(3) + 180 fs[3] - (bits[2] + bits[1] + bits[0]); 181 mpidr_hash.mask = mask; 182 mpidr_hash.bits = bits[3] + bits[2] + bits[1] + bits[0]; 183 pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] aff3[%u] mask[%#llx] bits[%u]\n", 184 mpidr_hash.shift_aff[0], 185 mpidr_hash.shift_aff[1], 186 mpidr_hash.shift_aff[2], 187 mpidr_hash.shift_aff[3], 188 mpidr_hash.mask, 189 mpidr_hash.bits); 190 /* 191 * 4x is an arbitrary value used to warn on a hash table much bigger 192 * than expected on most systems. 193 */ 194 if (mpidr_hash_size() > 4 * num_possible_cpus()) 195 pr_warn("Large number of MPIDR hash buckets detected\n"); 196 __flush_dcache_area(&mpidr_hash, sizeof(struct mpidr_hash)); 197 } 198 199 static void __init setup_processor(void) 200 { 201 u64 features; 202 s64 block; 203 u32 cwg; 204 int cls; 205 206 printk("CPU: AArch64 Processor [%08x] revision %d\n", 207 read_cpuid_id(), read_cpuid_id() & 15); 208 209 sprintf(init_utsname()->machine, ELF_PLATFORM); 210 elf_hwcap = 0; 211 212 cpuinfo_store_boot_cpu(); 213 214 /* 215 * Check for sane CTR_EL0.CWG value. 216 */ 217 cwg = cache_type_cwg(); 218 cls = cache_line_size(); 219 if (!cwg) 220 pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n", 221 cls); 222 if (L1_CACHE_BYTES < cls) 223 pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n", 224 L1_CACHE_BYTES, cls); 225 226 /* 227 * ID_AA64ISAR0_EL1 contains 4-bit wide signed feature blocks. 228 * The blocks we test below represent incremental functionality 229 * for non-negative values. Negative values are reserved. 230 */ 231 features = read_cpuid(ID_AA64ISAR0_EL1); 232 block = cpuid_feature_extract_field(features, 4); 233 if (block > 0) { 234 switch (block) { 235 default: 236 case 2: 237 elf_hwcap |= HWCAP_PMULL; 238 case 1: 239 elf_hwcap |= HWCAP_AES; 240 case 0: 241 break; 242 } 243 } 244 245 if (cpuid_feature_extract_field(features, 8) > 0) 246 elf_hwcap |= HWCAP_SHA1; 247 248 if (cpuid_feature_extract_field(features, 12) > 0) 249 elf_hwcap |= HWCAP_SHA2; 250 251 if (cpuid_feature_extract_field(features, 16) > 0) 252 elf_hwcap |= HWCAP_CRC32; 253 254 block = cpuid_feature_extract_field(features, 20); 255 if (block > 0) { 256 switch (block) { 257 default: 258 case 2: 259 elf_hwcap |= HWCAP_ATOMICS; 260 case 1: 261 /* RESERVED */ 262 case 0: 263 break; 264 } 265 } 266 267 #ifdef CONFIG_COMPAT 268 /* 269 * ID_ISAR5_EL1 carries similar information as above, but pertaining to 270 * the AArch32 32-bit execution state. 271 */ 272 features = read_cpuid(ID_ISAR5_EL1); 273 block = cpuid_feature_extract_field(features, 4); 274 if (block > 0) { 275 switch (block) { 276 default: 277 case 2: 278 compat_elf_hwcap2 |= COMPAT_HWCAP2_PMULL; 279 case 1: 280 compat_elf_hwcap2 |= COMPAT_HWCAP2_AES; 281 case 0: 282 break; 283 } 284 } 285 286 if (cpuid_feature_extract_field(features, 8) > 0) 287 compat_elf_hwcap2 |= COMPAT_HWCAP2_SHA1; 288 289 if (cpuid_feature_extract_field(features, 12) > 0) 290 compat_elf_hwcap2 |= COMPAT_HWCAP2_SHA2; 291 292 if (cpuid_feature_extract_field(features, 16) > 0) 293 compat_elf_hwcap2 |= COMPAT_HWCAP2_CRC32; 294 #endif 295 } 296 297 static void __init setup_machine_fdt(phys_addr_t dt_phys) 298 { 299 void *dt_virt = fixmap_remap_fdt(dt_phys); 300 301 if (!dt_virt || !early_init_dt_scan(dt_virt)) { 302 pr_crit("\n" 303 "Error: invalid device tree blob at physical address %pa (virtual address 0x%p)\n" 304 "The dtb must be 8-byte aligned and must not exceed 2 MB in size\n" 305 "\nPlease check your bootloader.", 306 &dt_phys, dt_virt); 307 308 while (true) 309 cpu_relax(); 310 } 311 312 dump_stack_set_arch_desc("%s (DT)", of_flat_dt_get_machine_name()); 313 } 314 315 static void __init request_standard_resources(void) 316 { 317 struct memblock_region *region; 318 struct resource *res; 319 320 kernel_code.start = virt_to_phys(_text); 321 kernel_code.end = virt_to_phys(_etext - 1); 322 kernel_data.start = virt_to_phys(_sdata); 323 kernel_data.end = virt_to_phys(_end - 1); 324 325 for_each_memblock(memory, region) { 326 res = alloc_bootmem_low(sizeof(*res)); 327 res->name = "System RAM"; 328 res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region)); 329 res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1; 330 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY; 331 332 request_resource(&iomem_resource, res); 333 334 if (kernel_code.start >= res->start && 335 kernel_code.end <= res->end) 336 request_resource(res, &kernel_code); 337 if (kernel_data.start >= res->start && 338 kernel_data.end <= res->end) 339 request_resource(res, &kernel_data); 340 } 341 } 342 343 #ifdef CONFIG_BLK_DEV_INITRD 344 /* 345 * Relocate initrd if it is not completely within the linear mapping. 346 * This would be the case if mem= cuts out all or part of it. 347 */ 348 static void __init relocate_initrd(void) 349 { 350 phys_addr_t orig_start = __virt_to_phys(initrd_start); 351 phys_addr_t orig_end = __virt_to_phys(initrd_end); 352 phys_addr_t ram_end = memblock_end_of_DRAM(); 353 phys_addr_t new_start; 354 unsigned long size, to_free = 0; 355 void *dest; 356 357 if (orig_end <= ram_end) 358 return; 359 360 /* 361 * Any of the original initrd which overlaps the linear map should 362 * be freed after relocating. 363 */ 364 if (orig_start < ram_end) 365 to_free = ram_end - orig_start; 366 367 size = orig_end - orig_start; 368 369 /* initrd needs to be relocated completely inside linear mapping */ 370 new_start = memblock_find_in_range(0, PFN_PHYS(max_pfn), 371 size, PAGE_SIZE); 372 if (!new_start) 373 panic("Cannot relocate initrd of size %ld\n", size); 374 memblock_reserve(new_start, size); 375 376 initrd_start = __phys_to_virt(new_start); 377 initrd_end = initrd_start + size; 378 379 pr_info("Moving initrd from [%llx-%llx] to [%llx-%llx]\n", 380 orig_start, orig_start + size - 1, 381 new_start, new_start + size - 1); 382 383 dest = (void *)initrd_start; 384 385 if (to_free) { 386 memcpy(dest, (void *)__phys_to_virt(orig_start), to_free); 387 dest += to_free; 388 } 389 390 copy_from_early_mem(dest, orig_start + to_free, size - to_free); 391 392 if (to_free) { 393 pr_info("Freeing original RAMDISK from [%llx-%llx]\n", 394 orig_start, orig_start + to_free - 1); 395 memblock_free(orig_start, to_free); 396 } 397 } 398 #else 399 static inline void __init relocate_initrd(void) 400 { 401 } 402 #endif 403 404 u64 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_HWID }; 405 406 void __init setup_arch(char **cmdline_p) 407 { 408 setup_processor(); 409 410 init_mm.start_code = (unsigned long) _text; 411 init_mm.end_code = (unsigned long) _etext; 412 init_mm.end_data = (unsigned long) _edata; 413 init_mm.brk = (unsigned long) _end; 414 415 *cmdline_p = boot_command_line; 416 417 early_fixmap_init(); 418 early_ioremap_init(); 419 420 setup_machine_fdt(__fdt_pointer); 421 422 parse_early_param(); 423 424 /* 425 * Unmask asynchronous aborts after bringing up possible earlycon. 426 * (Report possible System Errors once we can report this occurred) 427 */ 428 local_async_enable(); 429 430 efi_init(); 431 arm64_memblock_init(); 432 433 /* Parse the ACPI tables for possible boot-time configuration */ 434 acpi_boot_table_init(); 435 436 paging_init(); 437 relocate_initrd(); 438 439 kasan_init(); 440 441 request_standard_resources(); 442 443 early_ioremap_reset(); 444 445 if (acpi_disabled) { 446 unflatten_device_tree(); 447 psci_dt_init(); 448 } else { 449 psci_acpi_init(); 450 } 451 xen_early_init(); 452 453 cpu_read_bootcpu_ops(); 454 smp_init_cpus(); 455 smp_build_mpidr_hash(); 456 457 #ifdef CONFIG_VT 458 #if defined(CONFIG_VGA_CONSOLE) 459 conswitchp = &vga_con; 460 #elif defined(CONFIG_DUMMY_CONSOLE) 461 conswitchp = &dummy_con; 462 #endif 463 #endif 464 if (boot_args[1] || boot_args[2] || boot_args[3]) { 465 pr_err("WARNING: x1-x3 nonzero in violation of boot protocol:\n" 466 "\tx1: %016llx\n\tx2: %016llx\n\tx3: %016llx\n" 467 "This indicates a broken bootloader or old kernel\n", 468 boot_args[1], boot_args[2], boot_args[3]); 469 } 470 } 471 472 static int __init arm64_device_init(void) 473 { 474 if (of_have_populated_dt()) { 475 of_iommu_init(); 476 of_platform_populate(NULL, of_default_bus_match_table, 477 NULL, NULL); 478 } else if (acpi_disabled) { 479 pr_crit("Device tree not populated\n"); 480 } 481 return 0; 482 } 483 arch_initcall_sync(arm64_device_init); 484 485 static int __init topology_init(void) 486 { 487 int i; 488 489 for_each_possible_cpu(i) { 490 struct cpu *cpu = &per_cpu(cpu_data.cpu, i); 491 cpu->hotpluggable = 1; 492 register_cpu(cpu, i); 493 } 494 495 return 0; 496 } 497 subsys_initcall(topology_init); 498 499 static const char *hwcap_str[] = { 500 "fp", 501 "asimd", 502 "evtstrm", 503 "aes", 504 "pmull", 505 "sha1", 506 "sha2", 507 "crc32", 508 "atomics", 509 NULL 510 }; 511 512 #ifdef CONFIG_COMPAT 513 static const char *compat_hwcap_str[] = { 514 "swp", 515 "half", 516 "thumb", 517 "26bit", 518 "fastmult", 519 "fpa", 520 "vfp", 521 "edsp", 522 "java", 523 "iwmmxt", 524 "crunch", 525 "thumbee", 526 "neon", 527 "vfpv3", 528 "vfpv3d16", 529 "tls", 530 "vfpv4", 531 "idiva", 532 "idivt", 533 "vfpd32", 534 "lpae", 535 "evtstrm" 536 }; 537 538 static const char *compat_hwcap2_str[] = { 539 "aes", 540 "pmull", 541 "sha1", 542 "sha2", 543 "crc32", 544 NULL 545 }; 546 #endif /* CONFIG_COMPAT */ 547 548 static int c_show(struct seq_file *m, void *v) 549 { 550 int i, j; 551 552 for_each_online_cpu(i) { 553 struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i); 554 u32 midr = cpuinfo->reg_midr; 555 556 /* 557 * glibc reads /proc/cpuinfo to determine the number of 558 * online processors, looking for lines beginning with 559 * "processor". Give glibc what it expects. 560 */ 561 seq_printf(m, "processor\t: %d\n", i); 562 563 /* 564 * Dump out the common processor features in a single line. 565 * Userspace should read the hwcaps with getauxval(AT_HWCAP) 566 * rather than attempting to parse this, but there's a body of 567 * software which does already (at least for 32-bit). 568 */ 569 seq_puts(m, "Features\t:"); 570 if (personality(current->personality) == PER_LINUX32) { 571 #ifdef CONFIG_COMPAT 572 for (j = 0; compat_hwcap_str[j]; j++) 573 if (compat_elf_hwcap & (1 << j)) 574 seq_printf(m, " %s", compat_hwcap_str[j]); 575 576 for (j = 0; compat_hwcap2_str[j]; j++) 577 if (compat_elf_hwcap2 & (1 << j)) 578 seq_printf(m, " %s", compat_hwcap2_str[j]); 579 #endif /* CONFIG_COMPAT */ 580 } else { 581 for (j = 0; hwcap_str[j]; j++) 582 if (elf_hwcap & (1 << j)) 583 seq_printf(m, " %s", hwcap_str[j]); 584 } 585 seq_puts(m, "\n"); 586 587 seq_printf(m, "CPU implementer\t: 0x%02x\n", 588 MIDR_IMPLEMENTOR(midr)); 589 seq_printf(m, "CPU architecture: 8\n"); 590 seq_printf(m, "CPU variant\t: 0x%x\n", MIDR_VARIANT(midr)); 591 seq_printf(m, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr)); 592 seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr)); 593 } 594 595 return 0; 596 } 597 598 static void *c_start(struct seq_file *m, loff_t *pos) 599 { 600 return *pos < 1 ? (void *)1 : NULL; 601 } 602 603 static void *c_next(struct seq_file *m, void *v, loff_t *pos) 604 { 605 ++*pos; 606 return NULL; 607 } 608 609 static void c_stop(struct seq_file *m, void *v) 610 { 611 } 612 613 const struct seq_operations cpuinfo_op = { 614 .start = c_start, 615 .next = c_next, 616 .stop = c_stop, 617 .show = c_show 618 }; 619