1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Based on arch/arm/kernel/ptrace.c 4 * 5 * By Ross Biro 1/23/92 6 * edited by Linus Torvalds 7 * ARM modifications Copyright (C) 2000 Russell King 8 * Copyright (C) 2012 ARM Ltd. 9 */ 10 11 #include <linux/audit.h> 12 #include <linux/compat.h> 13 #include <linux/kernel.h> 14 #include <linux/sched/signal.h> 15 #include <linux/sched/task_stack.h> 16 #include <linux/mm.h> 17 #include <linux/nospec.h> 18 #include <linux/smp.h> 19 #include <linux/ptrace.h> 20 #include <linux/user.h> 21 #include <linux/seccomp.h> 22 #include <linux/security.h> 23 #include <linux/init.h> 24 #include <linux/signal.h> 25 #include <linux/string.h> 26 #include <linux/uaccess.h> 27 #include <linux/perf_event.h> 28 #include <linux/hw_breakpoint.h> 29 #include <linux/regset.h> 30 #include <linux/elf.h> 31 32 #include <asm/compat.h> 33 #include <asm/cpufeature.h> 34 #include <asm/debug-monitors.h> 35 #include <asm/fpsimd.h> 36 #include <asm/mte.h> 37 #include <asm/pointer_auth.h> 38 #include <asm/stacktrace.h> 39 #include <asm/syscall.h> 40 #include <asm/traps.h> 41 #include <asm/system_misc.h> 42 43 #define CREATE_TRACE_POINTS 44 #include <trace/events/syscalls.h> 45 46 struct pt_regs_offset { 47 const char *name; 48 int offset; 49 }; 50 51 #define REG_OFFSET_NAME(r) {.name = #r, .offset = offsetof(struct pt_regs, r)} 52 #define REG_OFFSET_END {.name = NULL, .offset = 0} 53 #define GPR_OFFSET_NAME(r) \ 54 {.name = "x" #r, .offset = offsetof(struct pt_regs, regs[r])} 55 56 static const struct pt_regs_offset regoffset_table[] = { 57 GPR_OFFSET_NAME(0), 58 GPR_OFFSET_NAME(1), 59 GPR_OFFSET_NAME(2), 60 GPR_OFFSET_NAME(3), 61 GPR_OFFSET_NAME(4), 62 GPR_OFFSET_NAME(5), 63 GPR_OFFSET_NAME(6), 64 GPR_OFFSET_NAME(7), 65 GPR_OFFSET_NAME(8), 66 GPR_OFFSET_NAME(9), 67 GPR_OFFSET_NAME(10), 68 GPR_OFFSET_NAME(11), 69 GPR_OFFSET_NAME(12), 70 GPR_OFFSET_NAME(13), 71 GPR_OFFSET_NAME(14), 72 GPR_OFFSET_NAME(15), 73 GPR_OFFSET_NAME(16), 74 GPR_OFFSET_NAME(17), 75 GPR_OFFSET_NAME(18), 76 GPR_OFFSET_NAME(19), 77 GPR_OFFSET_NAME(20), 78 GPR_OFFSET_NAME(21), 79 GPR_OFFSET_NAME(22), 80 GPR_OFFSET_NAME(23), 81 GPR_OFFSET_NAME(24), 82 GPR_OFFSET_NAME(25), 83 GPR_OFFSET_NAME(26), 84 GPR_OFFSET_NAME(27), 85 GPR_OFFSET_NAME(28), 86 GPR_OFFSET_NAME(29), 87 GPR_OFFSET_NAME(30), 88 {.name = "lr", .offset = offsetof(struct pt_regs, regs[30])}, 89 REG_OFFSET_NAME(sp), 90 REG_OFFSET_NAME(pc), 91 REG_OFFSET_NAME(pstate), 92 REG_OFFSET_END, 93 }; 94 95 /** 96 * regs_query_register_offset() - query register offset from its name 97 * @name: the name of a register 98 * 99 * regs_query_register_offset() returns the offset of a register in struct 100 * pt_regs from its name. If the name is invalid, this returns -EINVAL; 101 */ 102 int regs_query_register_offset(const char *name) 103 { 104 const struct pt_regs_offset *roff; 105 106 for (roff = regoffset_table; roff->name != NULL; roff++) 107 if (!strcmp(roff->name, name)) 108 return roff->offset; 109 return -EINVAL; 110 } 111 112 /** 113 * regs_within_kernel_stack() - check the address in the stack 114 * @regs: pt_regs which contains kernel stack pointer. 115 * @addr: address which is checked. 116 * 117 * regs_within_kernel_stack() checks @addr is within the kernel stack page(s). 118 * If @addr is within the kernel stack, it returns true. If not, returns false. 119 */ 120 static bool regs_within_kernel_stack(struct pt_regs *regs, unsigned long addr) 121 { 122 return ((addr & ~(THREAD_SIZE - 1)) == 123 (kernel_stack_pointer(regs) & ~(THREAD_SIZE - 1))) || 124 on_irq_stack(addr, sizeof(unsigned long)); 125 } 126 127 /** 128 * regs_get_kernel_stack_nth() - get Nth entry of the stack 129 * @regs: pt_regs which contains kernel stack pointer. 130 * @n: stack entry number. 131 * 132 * regs_get_kernel_stack_nth() returns @n th entry of the kernel stack which 133 * is specified by @regs. If the @n th entry is NOT in the kernel stack, 134 * this returns 0. 135 */ 136 unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, unsigned int n) 137 { 138 unsigned long *addr = (unsigned long *)kernel_stack_pointer(regs); 139 140 addr += n; 141 if (regs_within_kernel_stack(regs, (unsigned long)addr)) 142 return *addr; 143 else 144 return 0; 145 } 146 147 /* 148 * TODO: does not yet catch signals sent when the child dies. 149 * in exit.c or in signal.c. 150 */ 151 152 /* 153 * Called by kernel/ptrace.c when detaching.. 154 */ 155 void ptrace_disable(struct task_struct *child) 156 { 157 /* 158 * This would be better off in core code, but PTRACE_DETACH has 159 * grown its fair share of arch-specific worts and changing it 160 * is likely to cause regressions on obscure architectures. 161 */ 162 user_disable_single_step(child); 163 } 164 165 #ifdef CONFIG_HAVE_HW_BREAKPOINT 166 /* 167 * Handle hitting a HW-breakpoint. 168 */ 169 static void ptrace_hbptriggered(struct perf_event *bp, 170 struct perf_sample_data *data, 171 struct pt_regs *regs) 172 { 173 struct arch_hw_breakpoint *bkpt = counter_arch_bp(bp); 174 const char *desc = "Hardware breakpoint trap (ptrace)"; 175 176 #ifdef CONFIG_COMPAT 177 if (is_compat_task()) { 178 int si_errno = 0; 179 int i; 180 181 for (i = 0; i < ARM_MAX_BRP; ++i) { 182 if (current->thread.debug.hbp_break[i] == bp) { 183 si_errno = (i << 1) + 1; 184 break; 185 } 186 } 187 188 for (i = 0; i < ARM_MAX_WRP; ++i) { 189 if (current->thread.debug.hbp_watch[i] == bp) { 190 si_errno = -((i << 1) + 1); 191 break; 192 } 193 } 194 arm64_force_sig_ptrace_errno_trap(si_errno, bkpt->trigger, 195 desc); 196 return; 197 } 198 #endif 199 arm64_force_sig_fault(SIGTRAP, TRAP_HWBKPT, bkpt->trigger, desc); 200 } 201 202 /* 203 * Unregister breakpoints from this task and reset the pointers in 204 * the thread_struct. 205 */ 206 void flush_ptrace_hw_breakpoint(struct task_struct *tsk) 207 { 208 int i; 209 struct thread_struct *t = &tsk->thread; 210 211 for (i = 0; i < ARM_MAX_BRP; i++) { 212 if (t->debug.hbp_break[i]) { 213 unregister_hw_breakpoint(t->debug.hbp_break[i]); 214 t->debug.hbp_break[i] = NULL; 215 } 216 } 217 218 for (i = 0; i < ARM_MAX_WRP; i++) { 219 if (t->debug.hbp_watch[i]) { 220 unregister_hw_breakpoint(t->debug.hbp_watch[i]); 221 t->debug.hbp_watch[i] = NULL; 222 } 223 } 224 } 225 226 void ptrace_hw_copy_thread(struct task_struct *tsk) 227 { 228 memset(&tsk->thread.debug, 0, sizeof(struct debug_info)); 229 } 230 231 static struct perf_event *ptrace_hbp_get_event(unsigned int note_type, 232 struct task_struct *tsk, 233 unsigned long idx) 234 { 235 struct perf_event *bp = ERR_PTR(-EINVAL); 236 237 switch (note_type) { 238 case NT_ARM_HW_BREAK: 239 if (idx >= ARM_MAX_BRP) 240 goto out; 241 idx = array_index_nospec(idx, ARM_MAX_BRP); 242 bp = tsk->thread.debug.hbp_break[idx]; 243 break; 244 case NT_ARM_HW_WATCH: 245 if (idx >= ARM_MAX_WRP) 246 goto out; 247 idx = array_index_nospec(idx, ARM_MAX_WRP); 248 bp = tsk->thread.debug.hbp_watch[idx]; 249 break; 250 } 251 252 out: 253 return bp; 254 } 255 256 static int ptrace_hbp_set_event(unsigned int note_type, 257 struct task_struct *tsk, 258 unsigned long idx, 259 struct perf_event *bp) 260 { 261 int err = -EINVAL; 262 263 switch (note_type) { 264 case NT_ARM_HW_BREAK: 265 if (idx >= ARM_MAX_BRP) 266 goto out; 267 idx = array_index_nospec(idx, ARM_MAX_BRP); 268 tsk->thread.debug.hbp_break[idx] = bp; 269 err = 0; 270 break; 271 case NT_ARM_HW_WATCH: 272 if (idx >= ARM_MAX_WRP) 273 goto out; 274 idx = array_index_nospec(idx, ARM_MAX_WRP); 275 tsk->thread.debug.hbp_watch[idx] = bp; 276 err = 0; 277 break; 278 } 279 280 out: 281 return err; 282 } 283 284 static struct perf_event *ptrace_hbp_create(unsigned int note_type, 285 struct task_struct *tsk, 286 unsigned long idx) 287 { 288 struct perf_event *bp; 289 struct perf_event_attr attr; 290 int err, type; 291 292 switch (note_type) { 293 case NT_ARM_HW_BREAK: 294 type = HW_BREAKPOINT_X; 295 break; 296 case NT_ARM_HW_WATCH: 297 type = HW_BREAKPOINT_RW; 298 break; 299 default: 300 return ERR_PTR(-EINVAL); 301 } 302 303 ptrace_breakpoint_init(&attr); 304 305 /* 306 * Initialise fields to sane defaults 307 * (i.e. values that will pass validation). 308 */ 309 attr.bp_addr = 0; 310 attr.bp_len = HW_BREAKPOINT_LEN_4; 311 attr.bp_type = type; 312 attr.disabled = 1; 313 314 bp = register_user_hw_breakpoint(&attr, ptrace_hbptriggered, NULL, tsk); 315 if (IS_ERR(bp)) 316 return bp; 317 318 err = ptrace_hbp_set_event(note_type, tsk, idx, bp); 319 if (err) 320 return ERR_PTR(err); 321 322 return bp; 323 } 324 325 static int ptrace_hbp_fill_attr_ctrl(unsigned int note_type, 326 struct arch_hw_breakpoint_ctrl ctrl, 327 struct perf_event_attr *attr) 328 { 329 int err, len, type, offset, disabled = !ctrl.enabled; 330 331 attr->disabled = disabled; 332 if (disabled) 333 return 0; 334 335 err = arch_bp_generic_fields(ctrl, &len, &type, &offset); 336 if (err) 337 return err; 338 339 switch (note_type) { 340 case NT_ARM_HW_BREAK: 341 if ((type & HW_BREAKPOINT_X) != type) 342 return -EINVAL; 343 break; 344 case NT_ARM_HW_WATCH: 345 if ((type & HW_BREAKPOINT_RW) != type) 346 return -EINVAL; 347 break; 348 default: 349 return -EINVAL; 350 } 351 352 attr->bp_len = len; 353 attr->bp_type = type; 354 attr->bp_addr += offset; 355 356 return 0; 357 } 358 359 static int ptrace_hbp_get_resource_info(unsigned int note_type, u32 *info) 360 { 361 u8 num; 362 u32 reg = 0; 363 364 switch (note_type) { 365 case NT_ARM_HW_BREAK: 366 num = hw_breakpoint_slots(TYPE_INST); 367 break; 368 case NT_ARM_HW_WATCH: 369 num = hw_breakpoint_slots(TYPE_DATA); 370 break; 371 default: 372 return -EINVAL; 373 } 374 375 reg |= debug_monitors_arch(); 376 reg <<= 8; 377 reg |= num; 378 379 *info = reg; 380 return 0; 381 } 382 383 static int ptrace_hbp_get_ctrl(unsigned int note_type, 384 struct task_struct *tsk, 385 unsigned long idx, 386 u32 *ctrl) 387 { 388 struct perf_event *bp = ptrace_hbp_get_event(note_type, tsk, idx); 389 390 if (IS_ERR(bp)) 391 return PTR_ERR(bp); 392 393 *ctrl = bp ? encode_ctrl_reg(counter_arch_bp(bp)->ctrl) : 0; 394 return 0; 395 } 396 397 static int ptrace_hbp_get_addr(unsigned int note_type, 398 struct task_struct *tsk, 399 unsigned long idx, 400 u64 *addr) 401 { 402 struct perf_event *bp = ptrace_hbp_get_event(note_type, tsk, idx); 403 404 if (IS_ERR(bp)) 405 return PTR_ERR(bp); 406 407 *addr = bp ? counter_arch_bp(bp)->address : 0; 408 return 0; 409 } 410 411 static struct perf_event *ptrace_hbp_get_initialised_bp(unsigned int note_type, 412 struct task_struct *tsk, 413 unsigned long idx) 414 { 415 struct perf_event *bp = ptrace_hbp_get_event(note_type, tsk, idx); 416 417 if (!bp) 418 bp = ptrace_hbp_create(note_type, tsk, idx); 419 420 return bp; 421 } 422 423 static int ptrace_hbp_set_ctrl(unsigned int note_type, 424 struct task_struct *tsk, 425 unsigned long idx, 426 u32 uctrl) 427 { 428 int err; 429 struct perf_event *bp; 430 struct perf_event_attr attr; 431 struct arch_hw_breakpoint_ctrl ctrl; 432 433 bp = ptrace_hbp_get_initialised_bp(note_type, tsk, idx); 434 if (IS_ERR(bp)) { 435 err = PTR_ERR(bp); 436 return err; 437 } 438 439 attr = bp->attr; 440 decode_ctrl_reg(uctrl, &ctrl); 441 err = ptrace_hbp_fill_attr_ctrl(note_type, ctrl, &attr); 442 if (err) 443 return err; 444 445 return modify_user_hw_breakpoint(bp, &attr); 446 } 447 448 static int ptrace_hbp_set_addr(unsigned int note_type, 449 struct task_struct *tsk, 450 unsigned long idx, 451 u64 addr) 452 { 453 int err; 454 struct perf_event *bp; 455 struct perf_event_attr attr; 456 457 bp = ptrace_hbp_get_initialised_bp(note_type, tsk, idx); 458 if (IS_ERR(bp)) { 459 err = PTR_ERR(bp); 460 return err; 461 } 462 463 attr = bp->attr; 464 attr.bp_addr = addr; 465 err = modify_user_hw_breakpoint(bp, &attr); 466 return err; 467 } 468 469 #define PTRACE_HBP_ADDR_SZ sizeof(u64) 470 #define PTRACE_HBP_CTRL_SZ sizeof(u32) 471 #define PTRACE_HBP_PAD_SZ sizeof(u32) 472 473 static int hw_break_get(struct task_struct *target, 474 const struct user_regset *regset, 475 struct membuf to) 476 { 477 unsigned int note_type = regset->core_note_type; 478 int ret, idx = 0; 479 u32 info, ctrl; 480 u64 addr; 481 482 /* Resource info */ 483 ret = ptrace_hbp_get_resource_info(note_type, &info); 484 if (ret) 485 return ret; 486 487 membuf_write(&to, &info, sizeof(info)); 488 membuf_zero(&to, sizeof(u32)); 489 /* (address, ctrl) registers */ 490 while (to.left) { 491 ret = ptrace_hbp_get_addr(note_type, target, idx, &addr); 492 if (ret) 493 return ret; 494 ret = ptrace_hbp_get_ctrl(note_type, target, idx, &ctrl); 495 if (ret) 496 return ret; 497 membuf_store(&to, addr); 498 membuf_store(&to, ctrl); 499 membuf_zero(&to, sizeof(u32)); 500 idx++; 501 } 502 return 0; 503 } 504 505 static int hw_break_set(struct task_struct *target, 506 const struct user_regset *regset, 507 unsigned int pos, unsigned int count, 508 const void *kbuf, const void __user *ubuf) 509 { 510 unsigned int note_type = regset->core_note_type; 511 int ret, idx = 0, offset, limit; 512 u32 ctrl; 513 u64 addr; 514 515 /* Resource info and pad */ 516 offset = offsetof(struct user_hwdebug_state, dbg_regs); 517 user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf, 0, offset); 518 519 /* (address, ctrl) registers */ 520 limit = regset->n * regset->size; 521 while (count && offset < limit) { 522 if (count < PTRACE_HBP_ADDR_SZ) 523 return -EINVAL; 524 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &addr, 525 offset, offset + PTRACE_HBP_ADDR_SZ); 526 if (ret) 527 return ret; 528 ret = ptrace_hbp_set_addr(note_type, target, idx, addr); 529 if (ret) 530 return ret; 531 offset += PTRACE_HBP_ADDR_SZ; 532 533 if (!count) 534 break; 535 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &ctrl, 536 offset, offset + PTRACE_HBP_CTRL_SZ); 537 if (ret) 538 return ret; 539 ret = ptrace_hbp_set_ctrl(note_type, target, idx, ctrl); 540 if (ret) 541 return ret; 542 offset += PTRACE_HBP_CTRL_SZ; 543 544 user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf, 545 offset, offset + PTRACE_HBP_PAD_SZ); 546 offset += PTRACE_HBP_PAD_SZ; 547 idx++; 548 } 549 550 return 0; 551 } 552 #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 553 554 static int gpr_get(struct task_struct *target, 555 const struct user_regset *regset, 556 struct membuf to) 557 { 558 struct user_pt_regs *uregs = &task_pt_regs(target)->user_regs; 559 return membuf_write(&to, uregs, sizeof(*uregs)); 560 } 561 562 static int gpr_set(struct task_struct *target, const struct user_regset *regset, 563 unsigned int pos, unsigned int count, 564 const void *kbuf, const void __user *ubuf) 565 { 566 int ret; 567 struct user_pt_regs newregs = task_pt_regs(target)->user_regs; 568 569 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &newregs, 0, -1); 570 if (ret) 571 return ret; 572 573 if (!valid_user_regs(&newregs, target)) 574 return -EINVAL; 575 576 task_pt_regs(target)->user_regs = newregs; 577 return 0; 578 } 579 580 static int fpr_active(struct task_struct *target, const struct user_regset *regset) 581 { 582 if (!system_supports_fpsimd()) 583 return -ENODEV; 584 return regset->n; 585 } 586 587 /* 588 * TODO: update fp accessors for lazy context switching (sync/flush hwstate) 589 */ 590 static int __fpr_get(struct task_struct *target, 591 const struct user_regset *regset, 592 struct membuf to) 593 { 594 struct user_fpsimd_state *uregs; 595 596 sve_sync_to_fpsimd(target); 597 598 uregs = &target->thread.uw.fpsimd_state; 599 600 return membuf_write(&to, uregs, sizeof(*uregs)); 601 } 602 603 static int fpr_get(struct task_struct *target, const struct user_regset *regset, 604 struct membuf to) 605 { 606 if (!system_supports_fpsimd()) 607 return -EINVAL; 608 609 if (target == current) 610 fpsimd_preserve_current_state(); 611 612 return __fpr_get(target, regset, to); 613 } 614 615 static int __fpr_set(struct task_struct *target, 616 const struct user_regset *regset, 617 unsigned int pos, unsigned int count, 618 const void *kbuf, const void __user *ubuf, 619 unsigned int start_pos) 620 { 621 int ret; 622 struct user_fpsimd_state newstate; 623 624 /* 625 * Ensure target->thread.uw.fpsimd_state is up to date, so that a 626 * short copyin can't resurrect stale data. 627 */ 628 sve_sync_to_fpsimd(target); 629 630 newstate = target->thread.uw.fpsimd_state; 631 632 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &newstate, 633 start_pos, start_pos + sizeof(newstate)); 634 if (ret) 635 return ret; 636 637 target->thread.uw.fpsimd_state = newstate; 638 639 return ret; 640 } 641 642 static int fpr_set(struct task_struct *target, const struct user_regset *regset, 643 unsigned int pos, unsigned int count, 644 const void *kbuf, const void __user *ubuf) 645 { 646 int ret; 647 648 if (!system_supports_fpsimd()) 649 return -EINVAL; 650 651 ret = __fpr_set(target, regset, pos, count, kbuf, ubuf, 0); 652 if (ret) 653 return ret; 654 655 sve_sync_from_fpsimd_zeropad(target); 656 fpsimd_flush_task_state(target); 657 658 return ret; 659 } 660 661 static int tls_get(struct task_struct *target, const struct user_regset *regset, 662 struct membuf to) 663 { 664 int ret; 665 666 if (target == current) 667 tls_preserve_current_state(); 668 669 ret = membuf_store(&to, target->thread.uw.tp_value); 670 if (system_supports_tpidr2()) 671 ret = membuf_store(&to, target->thread.tpidr2_el0); 672 else 673 ret = membuf_zero(&to, sizeof(u64)); 674 675 return ret; 676 } 677 678 static int tls_set(struct task_struct *target, const struct user_regset *regset, 679 unsigned int pos, unsigned int count, 680 const void *kbuf, const void __user *ubuf) 681 { 682 int ret; 683 unsigned long tls[2]; 684 685 tls[0] = target->thread.uw.tp_value; 686 if (system_supports_sme()) 687 tls[1] = target->thread.tpidr2_el0; 688 689 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, tls, 0, count); 690 if (ret) 691 return ret; 692 693 target->thread.uw.tp_value = tls[0]; 694 if (system_supports_sme()) 695 target->thread.tpidr2_el0 = tls[1]; 696 697 return ret; 698 } 699 700 static int system_call_get(struct task_struct *target, 701 const struct user_regset *regset, 702 struct membuf to) 703 { 704 return membuf_store(&to, task_pt_regs(target)->syscallno); 705 } 706 707 static int system_call_set(struct task_struct *target, 708 const struct user_regset *regset, 709 unsigned int pos, unsigned int count, 710 const void *kbuf, const void __user *ubuf) 711 { 712 int syscallno = task_pt_regs(target)->syscallno; 713 int ret; 714 715 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &syscallno, 0, -1); 716 if (ret) 717 return ret; 718 719 task_pt_regs(target)->syscallno = syscallno; 720 return ret; 721 } 722 723 #ifdef CONFIG_ARM64_SVE 724 725 static void sve_init_header_from_task(struct user_sve_header *header, 726 struct task_struct *target, 727 enum vec_type type) 728 { 729 unsigned int vq; 730 bool active; 731 bool fpsimd_only; 732 enum vec_type task_type; 733 734 memset(header, 0, sizeof(*header)); 735 736 /* Check if the requested registers are active for the task */ 737 if (thread_sm_enabled(&target->thread)) 738 task_type = ARM64_VEC_SME; 739 else 740 task_type = ARM64_VEC_SVE; 741 active = (task_type == type); 742 743 switch (type) { 744 case ARM64_VEC_SVE: 745 if (test_tsk_thread_flag(target, TIF_SVE_VL_INHERIT)) 746 header->flags |= SVE_PT_VL_INHERIT; 747 fpsimd_only = !test_tsk_thread_flag(target, TIF_SVE); 748 break; 749 case ARM64_VEC_SME: 750 if (test_tsk_thread_flag(target, TIF_SME_VL_INHERIT)) 751 header->flags |= SVE_PT_VL_INHERIT; 752 fpsimd_only = false; 753 break; 754 default: 755 WARN_ON_ONCE(1); 756 return; 757 } 758 759 if (active) { 760 if (fpsimd_only) { 761 header->flags |= SVE_PT_REGS_FPSIMD; 762 } else { 763 header->flags |= SVE_PT_REGS_SVE; 764 } 765 } 766 767 header->vl = task_get_vl(target, type); 768 vq = sve_vq_from_vl(header->vl); 769 770 header->max_vl = vec_max_vl(type); 771 header->size = SVE_PT_SIZE(vq, header->flags); 772 header->max_size = SVE_PT_SIZE(sve_vq_from_vl(header->max_vl), 773 SVE_PT_REGS_SVE); 774 } 775 776 static unsigned int sve_size_from_header(struct user_sve_header const *header) 777 { 778 return ALIGN(header->size, SVE_VQ_BYTES); 779 } 780 781 static int sve_get_common(struct task_struct *target, 782 const struct user_regset *regset, 783 struct membuf to, 784 enum vec_type type) 785 { 786 struct user_sve_header header; 787 unsigned int vq; 788 unsigned long start, end; 789 790 /* Header */ 791 sve_init_header_from_task(&header, target, type); 792 vq = sve_vq_from_vl(header.vl); 793 794 membuf_write(&to, &header, sizeof(header)); 795 796 if (target == current) 797 fpsimd_preserve_current_state(); 798 799 BUILD_BUG_ON(SVE_PT_FPSIMD_OFFSET != sizeof(header)); 800 BUILD_BUG_ON(SVE_PT_SVE_OFFSET != sizeof(header)); 801 802 switch ((header.flags & SVE_PT_REGS_MASK)) { 803 case SVE_PT_REGS_FPSIMD: 804 return __fpr_get(target, regset, to); 805 806 case SVE_PT_REGS_SVE: 807 start = SVE_PT_SVE_OFFSET; 808 end = SVE_PT_SVE_FFR_OFFSET(vq) + SVE_PT_SVE_FFR_SIZE(vq); 809 membuf_write(&to, target->thread.sve_state, end - start); 810 811 start = end; 812 end = SVE_PT_SVE_FPSR_OFFSET(vq); 813 membuf_zero(&to, end - start); 814 815 /* 816 * Copy fpsr, and fpcr which must follow contiguously in 817 * struct fpsimd_state: 818 */ 819 start = end; 820 end = SVE_PT_SVE_FPCR_OFFSET(vq) + SVE_PT_SVE_FPCR_SIZE; 821 membuf_write(&to, &target->thread.uw.fpsimd_state.fpsr, 822 end - start); 823 824 start = end; 825 end = sve_size_from_header(&header); 826 return membuf_zero(&to, end - start); 827 828 default: 829 return 0; 830 } 831 } 832 833 static int sve_get(struct task_struct *target, 834 const struct user_regset *regset, 835 struct membuf to) 836 { 837 if (!system_supports_sve()) 838 return -EINVAL; 839 840 return sve_get_common(target, regset, to, ARM64_VEC_SVE); 841 } 842 843 static int sve_set_common(struct task_struct *target, 844 const struct user_regset *regset, 845 unsigned int pos, unsigned int count, 846 const void *kbuf, const void __user *ubuf, 847 enum vec_type type) 848 { 849 int ret; 850 struct user_sve_header header; 851 unsigned int vq; 852 unsigned long start, end; 853 854 /* Header */ 855 if (count < sizeof(header)) 856 return -EINVAL; 857 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &header, 858 0, sizeof(header)); 859 if (ret) 860 goto out; 861 862 /* 863 * Apart from SVE_PT_REGS_MASK, all SVE_PT_* flags are consumed by 864 * vec_set_vector_length(), which will also validate them for us: 865 */ 866 ret = vec_set_vector_length(target, type, header.vl, 867 ((unsigned long)header.flags & ~SVE_PT_REGS_MASK) << 16); 868 if (ret) 869 goto out; 870 871 /* Actual VL set may be less than the user asked for: */ 872 vq = sve_vq_from_vl(task_get_vl(target, type)); 873 874 /* Enter/exit streaming mode */ 875 if (system_supports_sme()) { 876 u64 old_svcr = target->thread.svcr; 877 878 switch (type) { 879 case ARM64_VEC_SVE: 880 target->thread.svcr &= ~SVCR_SM_MASK; 881 break; 882 case ARM64_VEC_SME: 883 target->thread.svcr |= SVCR_SM_MASK; 884 break; 885 default: 886 WARN_ON_ONCE(1); 887 return -EINVAL; 888 } 889 890 /* 891 * If we switched then invalidate any existing SVE 892 * state and ensure there's storage. 893 */ 894 if (target->thread.svcr != old_svcr) 895 sve_alloc(target, true); 896 } 897 898 /* Registers: FPSIMD-only case */ 899 900 BUILD_BUG_ON(SVE_PT_FPSIMD_OFFSET != sizeof(header)); 901 if ((header.flags & SVE_PT_REGS_MASK) == SVE_PT_REGS_FPSIMD) { 902 ret = __fpr_set(target, regset, pos, count, kbuf, ubuf, 903 SVE_PT_FPSIMD_OFFSET); 904 clear_tsk_thread_flag(target, TIF_SVE); 905 if (type == ARM64_VEC_SME) 906 fpsimd_force_sync_to_sve(target); 907 goto out; 908 } 909 910 /* 911 * Otherwise: no registers or full SVE case. For backwards 912 * compatibility reasons we treat empty flags as SVE registers. 913 */ 914 915 /* 916 * If setting a different VL from the requested VL and there is 917 * register data, the data layout will be wrong: don't even 918 * try to set the registers in this case. 919 */ 920 if (count && vq != sve_vq_from_vl(header.vl)) { 921 ret = -EIO; 922 goto out; 923 } 924 925 sve_alloc(target, true); 926 if (!target->thread.sve_state) { 927 ret = -ENOMEM; 928 clear_tsk_thread_flag(target, TIF_SVE); 929 goto out; 930 } 931 932 /* 933 * Ensure target->thread.sve_state is up to date with target's 934 * FPSIMD regs, so that a short copyin leaves trailing 935 * registers unmodified. Always enable SVE even if going into 936 * streaming mode. 937 */ 938 fpsimd_sync_to_sve(target); 939 set_tsk_thread_flag(target, TIF_SVE); 940 941 BUILD_BUG_ON(SVE_PT_SVE_OFFSET != sizeof(header)); 942 start = SVE_PT_SVE_OFFSET; 943 end = SVE_PT_SVE_FFR_OFFSET(vq) + SVE_PT_SVE_FFR_SIZE(vq); 944 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, 945 target->thread.sve_state, 946 start, end); 947 if (ret) 948 goto out; 949 950 start = end; 951 end = SVE_PT_SVE_FPSR_OFFSET(vq); 952 user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf, start, end); 953 954 /* 955 * Copy fpsr, and fpcr which must follow contiguously in 956 * struct fpsimd_state: 957 */ 958 start = end; 959 end = SVE_PT_SVE_FPCR_OFFSET(vq) + SVE_PT_SVE_FPCR_SIZE; 960 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, 961 &target->thread.uw.fpsimd_state.fpsr, 962 start, end); 963 964 out: 965 fpsimd_flush_task_state(target); 966 return ret; 967 } 968 969 static int sve_set(struct task_struct *target, 970 const struct user_regset *regset, 971 unsigned int pos, unsigned int count, 972 const void *kbuf, const void __user *ubuf) 973 { 974 if (!system_supports_sve()) 975 return -EINVAL; 976 977 return sve_set_common(target, regset, pos, count, kbuf, ubuf, 978 ARM64_VEC_SVE); 979 } 980 981 #endif /* CONFIG_ARM64_SVE */ 982 983 #ifdef CONFIG_ARM64_SME 984 985 static int ssve_get(struct task_struct *target, 986 const struct user_regset *regset, 987 struct membuf to) 988 { 989 if (!system_supports_sme()) 990 return -EINVAL; 991 992 return sve_get_common(target, regset, to, ARM64_VEC_SME); 993 } 994 995 static int ssve_set(struct task_struct *target, 996 const struct user_regset *regset, 997 unsigned int pos, unsigned int count, 998 const void *kbuf, const void __user *ubuf) 999 { 1000 if (!system_supports_sme()) 1001 return -EINVAL; 1002 1003 return sve_set_common(target, regset, pos, count, kbuf, ubuf, 1004 ARM64_VEC_SME); 1005 } 1006 1007 static int za_get(struct task_struct *target, 1008 const struct user_regset *regset, 1009 struct membuf to) 1010 { 1011 struct user_za_header header; 1012 unsigned int vq; 1013 unsigned long start, end; 1014 1015 if (!system_supports_sme()) 1016 return -EINVAL; 1017 1018 /* Header */ 1019 memset(&header, 0, sizeof(header)); 1020 1021 if (test_tsk_thread_flag(target, TIF_SME_VL_INHERIT)) 1022 header.flags |= ZA_PT_VL_INHERIT; 1023 1024 header.vl = task_get_sme_vl(target); 1025 vq = sve_vq_from_vl(header.vl); 1026 header.max_vl = sme_max_vl(); 1027 header.max_size = ZA_PT_SIZE(vq); 1028 1029 /* If ZA is not active there is only the header */ 1030 if (thread_za_enabled(&target->thread)) 1031 header.size = ZA_PT_SIZE(vq); 1032 else 1033 header.size = ZA_PT_ZA_OFFSET; 1034 1035 membuf_write(&to, &header, sizeof(header)); 1036 1037 BUILD_BUG_ON(ZA_PT_ZA_OFFSET != sizeof(header)); 1038 end = ZA_PT_ZA_OFFSET; 1039 1040 if (target == current) 1041 fpsimd_preserve_current_state(); 1042 1043 /* Any register data to include? */ 1044 if (thread_za_enabled(&target->thread)) { 1045 start = end; 1046 end = ZA_PT_SIZE(vq); 1047 membuf_write(&to, target->thread.za_state, end - start); 1048 } 1049 1050 /* Zero any trailing padding */ 1051 start = end; 1052 end = ALIGN(header.size, SVE_VQ_BYTES); 1053 return membuf_zero(&to, end - start); 1054 } 1055 1056 static int za_set(struct task_struct *target, 1057 const struct user_regset *regset, 1058 unsigned int pos, unsigned int count, 1059 const void *kbuf, const void __user *ubuf) 1060 { 1061 int ret; 1062 struct user_za_header header; 1063 unsigned int vq; 1064 unsigned long start, end; 1065 1066 if (!system_supports_sme()) 1067 return -EINVAL; 1068 1069 /* Header */ 1070 if (count < sizeof(header)) 1071 return -EINVAL; 1072 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &header, 1073 0, sizeof(header)); 1074 if (ret) 1075 goto out; 1076 1077 /* 1078 * All current ZA_PT_* flags are consumed by 1079 * vec_set_vector_length(), which will also validate them for 1080 * us: 1081 */ 1082 ret = vec_set_vector_length(target, ARM64_VEC_SME, header.vl, 1083 ((unsigned long)header.flags) << 16); 1084 if (ret) 1085 goto out; 1086 1087 /* Actual VL set may be less than the user asked for: */ 1088 vq = sve_vq_from_vl(task_get_sme_vl(target)); 1089 1090 /* Ensure there is some SVE storage for streaming mode */ 1091 if (!target->thread.sve_state) { 1092 sve_alloc(target, false); 1093 if (!target->thread.sve_state) { 1094 ret = -ENOMEM; 1095 goto out; 1096 } 1097 } 1098 1099 /* Allocate/reinit ZA storage */ 1100 sme_alloc(target); 1101 if (!target->thread.za_state) { 1102 ret = -ENOMEM; 1103 goto out; 1104 } 1105 1106 /* If there is no data then disable ZA */ 1107 if (!count) { 1108 target->thread.svcr &= ~SVCR_ZA_MASK; 1109 goto out; 1110 } 1111 1112 /* 1113 * If setting a different VL from the requested VL and there is 1114 * register data, the data layout will be wrong: don't even 1115 * try to set the registers in this case. 1116 */ 1117 if (vq != sve_vq_from_vl(header.vl)) { 1118 ret = -EIO; 1119 goto out; 1120 } 1121 1122 BUILD_BUG_ON(ZA_PT_ZA_OFFSET != sizeof(header)); 1123 start = ZA_PT_ZA_OFFSET; 1124 end = ZA_PT_SIZE(vq); 1125 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, 1126 target->thread.za_state, 1127 start, end); 1128 if (ret) 1129 goto out; 1130 1131 /* Mark ZA as active and let userspace use it */ 1132 set_tsk_thread_flag(target, TIF_SME); 1133 target->thread.svcr |= SVCR_ZA_MASK; 1134 1135 out: 1136 fpsimd_flush_task_state(target); 1137 return ret; 1138 } 1139 1140 #endif /* CONFIG_ARM64_SME */ 1141 1142 #ifdef CONFIG_ARM64_PTR_AUTH 1143 static int pac_mask_get(struct task_struct *target, 1144 const struct user_regset *regset, 1145 struct membuf to) 1146 { 1147 /* 1148 * The PAC bits can differ across data and instruction pointers 1149 * depending on TCR_EL1.TBID*, which we may make use of in future, so 1150 * we expose separate masks. 1151 */ 1152 unsigned long mask = ptrauth_user_pac_mask(); 1153 struct user_pac_mask uregs = { 1154 .data_mask = mask, 1155 .insn_mask = mask, 1156 }; 1157 1158 if (!system_supports_address_auth()) 1159 return -EINVAL; 1160 1161 return membuf_write(&to, &uregs, sizeof(uregs)); 1162 } 1163 1164 static int pac_enabled_keys_get(struct task_struct *target, 1165 const struct user_regset *regset, 1166 struct membuf to) 1167 { 1168 long enabled_keys = ptrauth_get_enabled_keys(target); 1169 1170 if (IS_ERR_VALUE(enabled_keys)) 1171 return enabled_keys; 1172 1173 return membuf_write(&to, &enabled_keys, sizeof(enabled_keys)); 1174 } 1175 1176 static int pac_enabled_keys_set(struct task_struct *target, 1177 const struct user_regset *regset, 1178 unsigned int pos, unsigned int count, 1179 const void *kbuf, const void __user *ubuf) 1180 { 1181 int ret; 1182 long enabled_keys = ptrauth_get_enabled_keys(target); 1183 1184 if (IS_ERR_VALUE(enabled_keys)) 1185 return enabled_keys; 1186 1187 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &enabled_keys, 0, 1188 sizeof(long)); 1189 if (ret) 1190 return ret; 1191 1192 return ptrauth_set_enabled_keys(target, PR_PAC_ENABLED_KEYS_MASK, 1193 enabled_keys); 1194 } 1195 1196 #ifdef CONFIG_CHECKPOINT_RESTORE 1197 static __uint128_t pac_key_to_user(const struct ptrauth_key *key) 1198 { 1199 return (__uint128_t)key->hi << 64 | key->lo; 1200 } 1201 1202 static struct ptrauth_key pac_key_from_user(__uint128_t ukey) 1203 { 1204 struct ptrauth_key key = { 1205 .lo = (unsigned long)ukey, 1206 .hi = (unsigned long)(ukey >> 64), 1207 }; 1208 1209 return key; 1210 } 1211 1212 static void pac_address_keys_to_user(struct user_pac_address_keys *ukeys, 1213 const struct ptrauth_keys_user *keys) 1214 { 1215 ukeys->apiakey = pac_key_to_user(&keys->apia); 1216 ukeys->apibkey = pac_key_to_user(&keys->apib); 1217 ukeys->apdakey = pac_key_to_user(&keys->apda); 1218 ukeys->apdbkey = pac_key_to_user(&keys->apdb); 1219 } 1220 1221 static void pac_address_keys_from_user(struct ptrauth_keys_user *keys, 1222 const struct user_pac_address_keys *ukeys) 1223 { 1224 keys->apia = pac_key_from_user(ukeys->apiakey); 1225 keys->apib = pac_key_from_user(ukeys->apibkey); 1226 keys->apda = pac_key_from_user(ukeys->apdakey); 1227 keys->apdb = pac_key_from_user(ukeys->apdbkey); 1228 } 1229 1230 static int pac_address_keys_get(struct task_struct *target, 1231 const struct user_regset *regset, 1232 struct membuf to) 1233 { 1234 struct ptrauth_keys_user *keys = &target->thread.keys_user; 1235 struct user_pac_address_keys user_keys; 1236 1237 if (!system_supports_address_auth()) 1238 return -EINVAL; 1239 1240 pac_address_keys_to_user(&user_keys, keys); 1241 1242 return membuf_write(&to, &user_keys, sizeof(user_keys)); 1243 } 1244 1245 static int pac_address_keys_set(struct task_struct *target, 1246 const struct user_regset *regset, 1247 unsigned int pos, unsigned int count, 1248 const void *kbuf, const void __user *ubuf) 1249 { 1250 struct ptrauth_keys_user *keys = &target->thread.keys_user; 1251 struct user_pac_address_keys user_keys; 1252 int ret; 1253 1254 if (!system_supports_address_auth()) 1255 return -EINVAL; 1256 1257 pac_address_keys_to_user(&user_keys, keys); 1258 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, 1259 &user_keys, 0, -1); 1260 if (ret) 1261 return ret; 1262 pac_address_keys_from_user(keys, &user_keys); 1263 1264 return 0; 1265 } 1266 1267 static void pac_generic_keys_to_user(struct user_pac_generic_keys *ukeys, 1268 const struct ptrauth_keys_user *keys) 1269 { 1270 ukeys->apgakey = pac_key_to_user(&keys->apga); 1271 } 1272 1273 static void pac_generic_keys_from_user(struct ptrauth_keys_user *keys, 1274 const struct user_pac_generic_keys *ukeys) 1275 { 1276 keys->apga = pac_key_from_user(ukeys->apgakey); 1277 } 1278 1279 static int pac_generic_keys_get(struct task_struct *target, 1280 const struct user_regset *regset, 1281 struct membuf to) 1282 { 1283 struct ptrauth_keys_user *keys = &target->thread.keys_user; 1284 struct user_pac_generic_keys user_keys; 1285 1286 if (!system_supports_generic_auth()) 1287 return -EINVAL; 1288 1289 pac_generic_keys_to_user(&user_keys, keys); 1290 1291 return membuf_write(&to, &user_keys, sizeof(user_keys)); 1292 } 1293 1294 static int pac_generic_keys_set(struct task_struct *target, 1295 const struct user_regset *regset, 1296 unsigned int pos, unsigned int count, 1297 const void *kbuf, const void __user *ubuf) 1298 { 1299 struct ptrauth_keys_user *keys = &target->thread.keys_user; 1300 struct user_pac_generic_keys user_keys; 1301 int ret; 1302 1303 if (!system_supports_generic_auth()) 1304 return -EINVAL; 1305 1306 pac_generic_keys_to_user(&user_keys, keys); 1307 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, 1308 &user_keys, 0, -1); 1309 if (ret) 1310 return ret; 1311 pac_generic_keys_from_user(keys, &user_keys); 1312 1313 return 0; 1314 } 1315 #endif /* CONFIG_CHECKPOINT_RESTORE */ 1316 #endif /* CONFIG_ARM64_PTR_AUTH */ 1317 1318 #ifdef CONFIG_ARM64_TAGGED_ADDR_ABI 1319 static int tagged_addr_ctrl_get(struct task_struct *target, 1320 const struct user_regset *regset, 1321 struct membuf to) 1322 { 1323 long ctrl = get_tagged_addr_ctrl(target); 1324 1325 if (IS_ERR_VALUE(ctrl)) 1326 return ctrl; 1327 1328 return membuf_write(&to, &ctrl, sizeof(ctrl)); 1329 } 1330 1331 static int tagged_addr_ctrl_set(struct task_struct *target, const struct 1332 user_regset *regset, unsigned int pos, 1333 unsigned int count, const void *kbuf, const 1334 void __user *ubuf) 1335 { 1336 int ret; 1337 long ctrl; 1338 1339 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &ctrl, 0, -1); 1340 if (ret) 1341 return ret; 1342 1343 return set_tagged_addr_ctrl(target, ctrl); 1344 } 1345 #endif 1346 1347 enum aarch64_regset { 1348 REGSET_GPR, 1349 REGSET_FPR, 1350 REGSET_TLS, 1351 #ifdef CONFIG_HAVE_HW_BREAKPOINT 1352 REGSET_HW_BREAK, 1353 REGSET_HW_WATCH, 1354 #endif 1355 REGSET_SYSTEM_CALL, 1356 #ifdef CONFIG_ARM64_SVE 1357 REGSET_SVE, 1358 #endif 1359 #ifdef CONFIG_ARM64_SVE 1360 REGSET_SSVE, 1361 REGSET_ZA, 1362 #endif 1363 #ifdef CONFIG_ARM64_PTR_AUTH 1364 REGSET_PAC_MASK, 1365 REGSET_PAC_ENABLED_KEYS, 1366 #ifdef CONFIG_CHECKPOINT_RESTORE 1367 REGSET_PACA_KEYS, 1368 REGSET_PACG_KEYS, 1369 #endif 1370 #endif 1371 #ifdef CONFIG_ARM64_TAGGED_ADDR_ABI 1372 REGSET_TAGGED_ADDR_CTRL, 1373 #endif 1374 }; 1375 1376 static const struct user_regset aarch64_regsets[] = { 1377 [REGSET_GPR] = { 1378 .core_note_type = NT_PRSTATUS, 1379 .n = sizeof(struct user_pt_regs) / sizeof(u64), 1380 .size = sizeof(u64), 1381 .align = sizeof(u64), 1382 .regset_get = gpr_get, 1383 .set = gpr_set 1384 }, 1385 [REGSET_FPR] = { 1386 .core_note_type = NT_PRFPREG, 1387 .n = sizeof(struct user_fpsimd_state) / sizeof(u32), 1388 /* 1389 * We pretend we have 32-bit registers because the fpsr and 1390 * fpcr are 32-bits wide. 1391 */ 1392 .size = sizeof(u32), 1393 .align = sizeof(u32), 1394 .active = fpr_active, 1395 .regset_get = fpr_get, 1396 .set = fpr_set 1397 }, 1398 [REGSET_TLS] = { 1399 .core_note_type = NT_ARM_TLS, 1400 .n = 2, 1401 .size = sizeof(void *), 1402 .align = sizeof(void *), 1403 .regset_get = tls_get, 1404 .set = tls_set, 1405 }, 1406 #ifdef CONFIG_HAVE_HW_BREAKPOINT 1407 [REGSET_HW_BREAK] = { 1408 .core_note_type = NT_ARM_HW_BREAK, 1409 .n = sizeof(struct user_hwdebug_state) / sizeof(u32), 1410 .size = sizeof(u32), 1411 .align = sizeof(u32), 1412 .regset_get = hw_break_get, 1413 .set = hw_break_set, 1414 }, 1415 [REGSET_HW_WATCH] = { 1416 .core_note_type = NT_ARM_HW_WATCH, 1417 .n = sizeof(struct user_hwdebug_state) / sizeof(u32), 1418 .size = sizeof(u32), 1419 .align = sizeof(u32), 1420 .regset_get = hw_break_get, 1421 .set = hw_break_set, 1422 }, 1423 #endif 1424 [REGSET_SYSTEM_CALL] = { 1425 .core_note_type = NT_ARM_SYSTEM_CALL, 1426 .n = 1, 1427 .size = sizeof(int), 1428 .align = sizeof(int), 1429 .regset_get = system_call_get, 1430 .set = system_call_set, 1431 }, 1432 #ifdef CONFIG_ARM64_SVE 1433 [REGSET_SVE] = { /* Scalable Vector Extension */ 1434 .core_note_type = NT_ARM_SVE, 1435 .n = DIV_ROUND_UP(SVE_PT_SIZE(SVE_VQ_MAX, SVE_PT_REGS_SVE), 1436 SVE_VQ_BYTES), 1437 .size = SVE_VQ_BYTES, 1438 .align = SVE_VQ_BYTES, 1439 .regset_get = sve_get, 1440 .set = sve_set, 1441 }, 1442 #endif 1443 #ifdef CONFIG_ARM64_SME 1444 [REGSET_SSVE] = { /* Streaming mode SVE */ 1445 .core_note_type = NT_ARM_SSVE, 1446 .n = DIV_ROUND_UP(SVE_PT_SIZE(SME_VQ_MAX, SVE_PT_REGS_SVE), 1447 SVE_VQ_BYTES), 1448 .size = SVE_VQ_BYTES, 1449 .align = SVE_VQ_BYTES, 1450 .regset_get = ssve_get, 1451 .set = ssve_set, 1452 }, 1453 [REGSET_ZA] = { /* SME ZA */ 1454 .core_note_type = NT_ARM_ZA, 1455 /* 1456 * ZA is a single register but it's variably sized and 1457 * the ptrace core requires that the size of any data 1458 * be an exact multiple of the configured register 1459 * size so report as though we had SVE_VQ_BYTES 1460 * registers. These values aren't exposed to 1461 * userspace. 1462 */ 1463 .n = DIV_ROUND_UP(ZA_PT_SIZE(SME_VQ_MAX), SVE_VQ_BYTES), 1464 .size = SVE_VQ_BYTES, 1465 .align = SVE_VQ_BYTES, 1466 .regset_get = za_get, 1467 .set = za_set, 1468 }, 1469 #endif 1470 #ifdef CONFIG_ARM64_PTR_AUTH 1471 [REGSET_PAC_MASK] = { 1472 .core_note_type = NT_ARM_PAC_MASK, 1473 .n = sizeof(struct user_pac_mask) / sizeof(u64), 1474 .size = sizeof(u64), 1475 .align = sizeof(u64), 1476 .regset_get = pac_mask_get, 1477 /* this cannot be set dynamically */ 1478 }, 1479 [REGSET_PAC_ENABLED_KEYS] = { 1480 .core_note_type = NT_ARM_PAC_ENABLED_KEYS, 1481 .n = 1, 1482 .size = sizeof(long), 1483 .align = sizeof(long), 1484 .regset_get = pac_enabled_keys_get, 1485 .set = pac_enabled_keys_set, 1486 }, 1487 #ifdef CONFIG_CHECKPOINT_RESTORE 1488 [REGSET_PACA_KEYS] = { 1489 .core_note_type = NT_ARM_PACA_KEYS, 1490 .n = sizeof(struct user_pac_address_keys) / sizeof(__uint128_t), 1491 .size = sizeof(__uint128_t), 1492 .align = sizeof(__uint128_t), 1493 .regset_get = pac_address_keys_get, 1494 .set = pac_address_keys_set, 1495 }, 1496 [REGSET_PACG_KEYS] = { 1497 .core_note_type = NT_ARM_PACG_KEYS, 1498 .n = sizeof(struct user_pac_generic_keys) / sizeof(__uint128_t), 1499 .size = sizeof(__uint128_t), 1500 .align = sizeof(__uint128_t), 1501 .regset_get = pac_generic_keys_get, 1502 .set = pac_generic_keys_set, 1503 }, 1504 #endif 1505 #endif 1506 #ifdef CONFIG_ARM64_TAGGED_ADDR_ABI 1507 [REGSET_TAGGED_ADDR_CTRL] = { 1508 .core_note_type = NT_ARM_TAGGED_ADDR_CTRL, 1509 .n = 1, 1510 .size = sizeof(long), 1511 .align = sizeof(long), 1512 .regset_get = tagged_addr_ctrl_get, 1513 .set = tagged_addr_ctrl_set, 1514 }, 1515 #endif 1516 }; 1517 1518 static const struct user_regset_view user_aarch64_view = { 1519 .name = "aarch64", .e_machine = EM_AARCH64, 1520 .regsets = aarch64_regsets, .n = ARRAY_SIZE(aarch64_regsets) 1521 }; 1522 1523 #ifdef CONFIG_COMPAT 1524 enum compat_regset { 1525 REGSET_COMPAT_GPR, 1526 REGSET_COMPAT_VFP, 1527 }; 1528 1529 static inline compat_ulong_t compat_get_user_reg(struct task_struct *task, int idx) 1530 { 1531 struct pt_regs *regs = task_pt_regs(task); 1532 1533 switch (idx) { 1534 case 15: 1535 return regs->pc; 1536 case 16: 1537 return pstate_to_compat_psr(regs->pstate); 1538 case 17: 1539 return regs->orig_x0; 1540 default: 1541 return regs->regs[idx]; 1542 } 1543 } 1544 1545 static int compat_gpr_get(struct task_struct *target, 1546 const struct user_regset *regset, 1547 struct membuf to) 1548 { 1549 int i = 0; 1550 1551 while (to.left) 1552 membuf_store(&to, compat_get_user_reg(target, i++)); 1553 return 0; 1554 } 1555 1556 static int compat_gpr_set(struct task_struct *target, 1557 const struct user_regset *regset, 1558 unsigned int pos, unsigned int count, 1559 const void *kbuf, const void __user *ubuf) 1560 { 1561 struct pt_regs newregs; 1562 int ret = 0; 1563 unsigned int i, start, num_regs; 1564 1565 /* Calculate the number of AArch32 registers contained in count */ 1566 num_regs = count / regset->size; 1567 1568 /* Convert pos into an register number */ 1569 start = pos / regset->size; 1570 1571 if (start + num_regs > regset->n) 1572 return -EIO; 1573 1574 newregs = *task_pt_regs(target); 1575 1576 for (i = 0; i < num_regs; ++i) { 1577 unsigned int idx = start + i; 1578 compat_ulong_t reg; 1579 1580 if (kbuf) { 1581 memcpy(®, kbuf, sizeof(reg)); 1582 kbuf += sizeof(reg); 1583 } else { 1584 ret = copy_from_user(®, ubuf, sizeof(reg)); 1585 if (ret) { 1586 ret = -EFAULT; 1587 break; 1588 } 1589 1590 ubuf += sizeof(reg); 1591 } 1592 1593 switch (idx) { 1594 case 15: 1595 newregs.pc = reg; 1596 break; 1597 case 16: 1598 reg = compat_psr_to_pstate(reg); 1599 newregs.pstate = reg; 1600 break; 1601 case 17: 1602 newregs.orig_x0 = reg; 1603 break; 1604 default: 1605 newregs.regs[idx] = reg; 1606 } 1607 1608 } 1609 1610 if (valid_user_regs(&newregs.user_regs, target)) 1611 *task_pt_regs(target) = newregs; 1612 else 1613 ret = -EINVAL; 1614 1615 return ret; 1616 } 1617 1618 static int compat_vfp_get(struct task_struct *target, 1619 const struct user_regset *regset, 1620 struct membuf to) 1621 { 1622 struct user_fpsimd_state *uregs; 1623 compat_ulong_t fpscr; 1624 1625 if (!system_supports_fpsimd()) 1626 return -EINVAL; 1627 1628 uregs = &target->thread.uw.fpsimd_state; 1629 1630 if (target == current) 1631 fpsimd_preserve_current_state(); 1632 1633 /* 1634 * The VFP registers are packed into the fpsimd_state, so they all sit 1635 * nicely together for us. We just need to create the fpscr separately. 1636 */ 1637 membuf_write(&to, uregs, VFP_STATE_SIZE - sizeof(compat_ulong_t)); 1638 fpscr = (uregs->fpsr & VFP_FPSCR_STAT_MASK) | 1639 (uregs->fpcr & VFP_FPSCR_CTRL_MASK); 1640 return membuf_store(&to, fpscr); 1641 } 1642 1643 static int compat_vfp_set(struct task_struct *target, 1644 const struct user_regset *regset, 1645 unsigned int pos, unsigned int count, 1646 const void *kbuf, const void __user *ubuf) 1647 { 1648 struct user_fpsimd_state *uregs; 1649 compat_ulong_t fpscr; 1650 int ret, vregs_end_pos; 1651 1652 if (!system_supports_fpsimd()) 1653 return -EINVAL; 1654 1655 uregs = &target->thread.uw.fpsimd_state; 1656 1657 vregs_end_pos = VFP_STATE_SIZE - sizeof(compat_ulong_t); 1658 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, uregs, 0, 1659 vregs_end_pos); 1660 1661 if (count && !ret) { 1662 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &fpscr, 1663 vregs_end_pos, VFP_STATE_SIZE); 1664 if (!ret) { 1665 uregs->fpsr = fpscr & VFP_FPSCR_STAT_MASK; 1666 uregs->fpcr = fpscr & VFP_FPSCR_CTRL_MASK; 1667 } 1668 } 1669 1670 fpsimd_flush_task_state(target); 1671 return ret; 1672 } 1673 1674 static int compat_tls_get(struct task_struct *target, 1675 const struct user_regset *regset, 1676 struct membuf to) 1677 { 1678 return membuf_store(&to, (compat_ulong_t)target->thread.uw.tp_value); 1679 } 1680 1681 static int compat_tls_set(struct task_struct *target, 1682 const struct user_regset *regset, unsigned int pos, 1683 unsigned int count, const void *kbuf, 1684 const void __user *ubuf) 1685 { 1686 int ret; 1687 compat_ulong_t tls = target->thread.uw.tp_value; 1688 1689 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &tls, 0, -1); 1690 if (ret) 1691 return ret; 1692 1693 target->thread.uw.tp_value = tls; 1694 return ret; 1695 } 1696 1697 static const struct user_regset aarch32_regsets[] = { 1698 [REGSET_COMPAT_GPR] = { 1699 .core_note_type = NT_PRSTATUS, 1700 .n = COMPAT_ELF_NGREG, 1701 .size = sizeof(compat_elf_greg_t), 1702 .align = sizeof(compat_elf_greg_t), 1703 .regset_get = compat_gpr_get, 1704 .set = compat_gpr_set 1705 }, 1706 [REGSET_COMPAT_VFP] = { 1707 .core_note_type = NT_ARM_VFP, 1708 .n = VFP_STATE_SIZE / sizeof(compat_ulong_t), 1709 .size = sizeof(compat_ulong_t), 1710 .align = sizeof(compat_ulong_t), 1711 .active = fpr_active, 1712 .regset_get = compat_vfp_get, 1713 .set = compat_vfp_set 1714 }, 1715 }; 1716 1717 static const struct user_regset_view user_aarch32_view = { 1718 .name = "aarch32", .e_machine = EM_ARM, 1719 .regsets = aarch32_regsets, .n = ARRAY_SIZE(aarch32_regsets) 1720 }; 1721 1722 static const struct user_regset aarch32_ptrace_regsets[] = { 1723 [REGSET_GPR] = { 1724 .core_note_type = NT_PRSTATUS, 1725 .n = COMPAT_ELF_NGREG, 1726 .size = sizeof(compat_elf_greg_t), 1727 .align = sizeof(compat_elf_greg_t), 1728 .regset_get = compat_gpr_get, 1729 .set = compat_gpr_set 1730 }, 1731 [REGSET_FPR] = { 1732 .core_note_type = NT_ARM_VFP, 1733 .n = VFP_STATE_SIZE / sizeof(compat_ulong_t), 1734 .size = sizeof(compat_ulong_t), 1735 .align = sizeof(compat_ulong_t), 1736 .regset_get = compat_vfp_get, 1737 .set = compat_vfp_set 1738 }, 1739 [REGSET_TLS] = { 1740 .core_note_type = NT_ARM_TLS, 1741 .n = 1, 1742 .size = sizeof(compat_ulong_t), 1743 .align = sizeof(compat_ulong_t), 1744 .regset_get = compat_tls_get, 1745 .set = compat_tls_set, 1746 }, 1747 #ifdef CONFIG_HAVE_HW_BREAKPOINT 1748 [REGSET_HW_BREAK] = { 1749 .core_note_type = NT_ARM_HW_BREAK, 1750 .n = sizeof(struct user_hwdebug_state) / sizeof(u32), 1751 .size = sizeof(u32), 1752 .align = sizeof(u32), 1753 .regset_get = hw_break_get, 1754 .set = hw_break_set, 1755 }, 1756 [REGSET_HW_WATCH] = { 1757 .core_note_type = NT_ARM_HW_WATCH, 1758 .n = sizeof(struct user_hwdebug_state) / sizeof(u32), 1759 .size = sizeof(u32), 1760 .align = sizeof(u32), 1761 .regset_get = hw_break_get, 1762 .set = hw_break_set, 1763 }, 1764 #endif 1765 [REGSET_SYSTEM_CALL] = { 1766 .core_note_type = NT_ARM_SYSTEM_CALL, 1767 .n = 1, 1768 .size = sizeof(int), 1769 .align = sizeof(int), 1770 .regset_get = system_call_get, 1771 .set = system_call_set, 1772 }, 1773 }; 1774 1775 static const struct user_regset_view user_aarch32_ptrace_view = { 1776 .name = "aarch32", .e_machine = EM_ARM, 1777 .regsets = aarch32_ptrace_regsets, .n = ARRAY_SIZE(aarch32_ptrace_regsets) 1778 }; 1779 1780 static int compat_ptrace_read_user(struct task_struct *tsk, compat_ulong_t off, 1781 compat_ulong_t __user *ret) 1782 { 1783 compat_ulong_t tmp; 1784 1785 if (off & 3) 1786 return -EIO; 1787 1788 if (off == COMPAT_PT_TEXT_ADDR) 1789 tmp = tsk->mm->start_code; 1790 else if (off == COMPAT_PT_DATA_ADDR) 1791 tmp = tsk->mm->start_data; 1792 else if (off == COMPAT_PT_TEXT_END_ADDR) 1793 tmp = tsk->mm->end_code; 1794 else if (off < sizeof(compat_elf_gregset_t)) 1795 tmp = compat_get_user_reg(tsk, off >> 2); 1796 else if (off >= COMPAT_USER_SZ) 1797 return -EIO; 1798 else 1799 tmp = 0; 1800 1801 return put_user(tmp, ret); 1802 } 1803 1804 static int compat_ptrace_write_user(struct task_struct *tsk, compat_ulong_t off, 1805 compat_ulong_t val) 1806 { 1807 struct pt_regs newregs = *task_pt_regs(tsk); 1808 unsigned int idx = off / 4; 1809 1810 if (off & 3 || off >= COMPAT_USER_SZ) 1811 return -EIO; 1812 1813 if (off >= sizeof(compat_elf_gregset_t)) 1814 return 0; 1815 1816 switch (idx) { 1817 case 15: 1818 newregs.pc = val; 1819 break; 1820 case 16: 1821 newregs.pstate = compat_psr_to_pstate(val); 1822 break; 1823 case 17: 1824 newregs.orig_x0 = val; 1825 break; 1826 default: 1827 newregs.regs[idx] = val; 1828 } 1829 1830 if (!valid_user_regs(&newregs.user_regs, tsk)) 1831 return -EINVAL; 1832 1833 *task_pt_regs(tsk) = newregs; 1834 return 0; 1835 } 1836 1837 #ifdef CONFIG_HAVE_HW_BREAKPOINT 1838 1839 /* 1840 * Convert a virtual register number into an index for a thread_info 1841 * breakpoint array. Breakpoints are identified using positive numbers 1842 * whilst watchpoints are negative. The registers are laid out as pairs 1843 * of (address, control), each pair mapping to a unique hw_breakpoint struct. 1844 * Register 0 is reserved for describing resource information. 1845 */ 1846 static int compat_ptrace_hbp_num_to_idx(compat_long_t num) 1847 { 1848 return (abs(num) - 1) >> 1; 1849 } 1850 1851 static int compat_ptrace_hbp_get_resource_info(u32 *kdata) 1852 { 1853 u8 num_brps, num_wrps, debug_arch, wp_len; 1854 u32 reg = 0; 1855 1856 num_brps = hw_breakpoint_slots(TYPE_INST); 1857 num_wrps = hw_breakpoint_slots(TYPE_DATA); 1858 1859 debug_arch = debug_monitors_arch(); 1860 wp_len = 8; 1861 reg |= debug_arch; 1862 reg <<= 8; 1863 reg |= wp_len; 1864 reg <<= 8; 1865 reg |= num_wrps; 1866 reg <<= 8; 1867 reg |= num_brps; 1868 1869 *kdata = reg; 1870 return 0; 1871 } 1872 1873 static int compat_ptrace_hbp_get(unsigned int note_type, 1874 struct task_struct *tsk, 1875 compat_long_t num, 1876 u32 *kdata) 1877 { 1878 u64 addr = 0; 1879 u32 ctrl = 0; 1880 1881 int err, idx = compat_ptrace_hbp_num_to_idx(num); 1882 1883 if (num & 1) { 1884 err = ptrace_hbp_get_addr(note_type, tsk, idx, &addr); 1885 *kdata = (u32)addr; 1886 } else { 1887 err = ptrace_hbp_get_ctrl(note_type, tsk, idx, &ctrl); 1888 *kdata = ctrl; 1889 } 1890 1891 return err; 1892 } 1893 1894 static int compat_ptrace_hbp_set(unsigned int note_type, 1895 struct task_struct *tsk, 1896 compat_long_t num, 1897 u32 *kdata) 1898 { 1899 u64 addr; 1900 u32 ctrl; 1901 1902 int err, idx = compat_ptrace_hbp_num_to_idx(num); 1903 1904 if (num & 1) { 1905 addr = *kdata; 1906 err = ptrace_hbp_set_addr(note_type, tsk, idx, addr); 1907 } else { 1908 ctrl = *kdata; 1909 err = ptrace_hbp_set_ctrl(note_type, tsk, idx, ctrl); 1910 } 1911 1912 return err; 1913 } 1914 1915 static int compat_ptrace_gethbpregs(struct task_struct *tsk, compat_long_t num, 1916 compat_ulong_t __user *data) 1917 { 1918 int ret; 1919 u32 kdata; 1920 1921 /* Watchpoint */ 1922 if (num < 0) { 1923 ret = compat_ptrace_hbp_get(NT_ARM_HW_WATCH, tsk, num, &kdata); 1924 /* Resource info */ 1925 } else if (num == 0) { 1926 ret = compat_ptrace_hbp_get_resource_info(&kdata); 1927 /* Breakpoint */ 1928 } else { 1929 ret = compat_ptrace_hbp_get(NT_ARM_HW_BREAK, tsk, num, &kdata); 1930 } 1931 1932 if (!ret) 1933 ret = put_user(kdata, data); 1934 1935 return ret; 1936 } 1937 1938 static int compat_ptrace_sethbpregs(struct task_struct *tsk, compat_long_t num, 1939 compat_ulong_t __user *data) 1940 { 1941 int ret; 1942 u32 kdata = 0; 1943 1944 if (num == 0) 1945 return 0; 1946 1947 ret = get_user(kdata, data); 1948 if (ret) 1949 return ret; 1950 1951 if (num < 0) 1952 ret = compat_ptrace_hbp_set(NT_ARM_HW_WATCH, tsk, num, &kdata); 1953 else 1954 ret = compat_ptrace_hbp_set(NT_ARM_HW_BREAK, tsk, num, &kdata); 1955 1956 return ret; 1957 } 1958 #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 1959 1960 long compat_arch_ptrace(struct task_struct *child, compat_long_t request, 1961 compat_ulong_t caddr, compat_ulong_t cdata) 1962 { 1963 unsigned long addr = caddr; 1964 unsigned long data = cdata; 1965 void __user *datap = compat_ptr(data); 1966 int ret; 1967 1968 switch (request) { 1969 case PTRACE_PEEKUSR: 1970 ret = compat_ptrace_read_user(child, addr, datap); 1971 break; 1972 1973 case PTRACE_POKEUSR: 1974 ret = compat_ptrace_write_user(child, addr, data); 1975 break; 1976 1977 case COMPAT_PTRACE_GETREGS: 1978 ret = copy_regset_to_user(child, 1979 &user_aarch32_view, 1980 REGSET_COMPAT_GPR, 1981 0, sizeof(compat_elf_gregset_t), 1982 datap); 1983 break; 1984 1985 case COMPAT_PTRACE_SETREGS: 1986 ret = copy_regset_from_user(child, 1987 &user_aarch32_view, 1988 REGSET_COMPAT_GPR, 1989 0, sizeof(compat_elf_gregset_t), 1990 datap); 1991 break; 1992 1993 case COMPAT_PTRACE_GET_THREAD_AREA: 1994 ret = put_user((compat_ulong_t)child->thread.uw.tp_value, 1995 (compat_ulong_t __user *)datap); 1996 break; 1997 1998 case COMPAT_PTRACE_SET_SYSCALL: 1999 task_pt_regs(child)->syscallno = data; 2000 ret = 0; 2001 break; 2002 2003 case COMPAT_PTRACE_GETVFPREGS: 2004 ret = copy_regset_to_user(child, 2005 &user_aarch32_view, 2006 REGSET_COMPAT_VFP, 2007 0, VFP_STATE_SIZE, 2008 datap); 2009 break; 2010 2011 case COMPAT_PTRACE_SETVFPREGS: 2012 ret = copy_regset_from_user(child, 2013 &user_aarch32_view, 2014 REGSET_COMPAT_VFP, 2015 0, VFP_STATE_SIZE, 2016 datap); 2017 break; 2018 2019 #ifdef CONFIG_HAVE_HW_BREAKPOINT 2020 case COMPAT_PTRACE_GETHBPREGS: 2021 ret = compat_ptrace_gethbpregs(child, addr, datap); 2022 break; 2023 2024 case COMPAT_PTRACE_SETHBPREGS: 2025 ret = compat_ptrace_sethbpregs(child, addr, datap); 2026 break; 2027 #endif 2028 2029 default: 2030 ret = compat_ptrace_request(child, request, addr, 2031 data); 2032 break; 2033 } 2034 2035 return ret; 2036 } 2037 #endif /* CONFIG_COMPAT */ 2038 2039 const struct user_regset_view *task_user_regset_view(struct task_struct *task) 2040 { 2041 #ifdef CONFIG_COMPAT 2042 /* 2043 * Core dumping of 32-bit tasks or compat ptrace requests must use the 2044 * user_aarch32_view compatible with arm32. Native ptrace requests on 2045 * 32-bit children use an extended user_aarch32_ptrace_view to allow 2046 * access to the TLS register. 2047 */ 2048 if (is_compat_task()) 2049 return &user_aarch32_view; 2050 else if (is_compat_thread(task_thread_info(task))) 2051 return &user_aarch32_ptrace_view; 2052 #endif 2053 return &user_aarch64_view; 2054 } 2055 2056 long arch_ptrace(struct task_struct *child, long request, 2057 unsigned long addr, unsigned long data) 2058 { 2059 switch (request) { 2060 case PTRACE_PEEKMTETAGS: 2061 case PTRACE_POKEMTETAGS: 2062 return mte_ptrace_copy_tags(child, request, addr, data); 2063 } 2064 2065 return ptrace_request(child, request, addr, data); 2066 } 2067 2068 enum ptrace_syscall_dir { 2069 PTRACE_SYSCALL_ENTER = 0, 2070 PTRACE_SYSCALL_EXIT, 2071 }; 2072 2073 static void report_syscall(struct pt_regs *regs, enum ptrace_syscall_dir dir) 2074 { 2075 int regno; 2076 unsigned long saved_reg; 2077 2078 /* 2079 * We have some ABI weirdness here in the way that we handle syscall 2080 * exit stops because we indicate whether or not the stop has been 2081 * signalled from syscall entry or syscall exit by clobbering a general 2082 * purpose register (ip/r12 for AArch32, x7 for AArch64) in the tracee 2083 * and restoring its old value after the stop. This means that: 2084 * 2085 * - Any writes by the tracer to this register during the stop are 2086 * ignored/discarded. 2087 * 2088 * - The actual value of the register is not available during the stop, 2089 * so the tracer cannot save it and restore it later. 2090 * 2091 * - Syscall stops behave differently to seccomp and pseudo-step traps 2092 * (the latter do not nobble any registers). 2093 */ 2094 regno = (is_compat_task() ? 12 : 7); 2095 saved_reg = regs->regs[regno]; 2096 regs->regs[regno] = dir; 2097 2098 if (dir == PTRACE_SYSCALL_ENTER) { 2099 if (ptrace_report_syscall_entry(regs)) 2100 forget_syscall(regs); 2101 regs->regs[regno] = saved_reg; 2102 } else if (!test_thread_flag(TIF_SINGLESTEP)) { 2103 ptrace_report_syscall_exit(regs, 0); 2104 regs->regs[regno] = saved_reg; 2105 } else { 2106 regs->regs[regno] = saved_reg; 2107 2108 /* 2109 * Signal a pseudo-step exception since we are stepping but 2110 * tracer modifications to the registers may have rewound the 2111 * state machine. 2112 */ 2113 ptrace_report_syscall_exit(regs, 1); 2114 } 2115 } 2116 2117 int syscall_trace_enter(struct pt_regs *regs) 2118 { 2119 unsigned long flags = read_thread_flags(); 2120 2121 if (flags & (_TIF_SYSCALL_EMU | _TIF_SYSCALL_TRACE)) { 2122 report_syscall(regs, PTRACE_SYSCALL_ENTER); 2123 if (flags & _TIF_SYSCALL_EMU) 2124 return NO_SYSCALL; 2125 } 2126 2127 /* Do the secure computing after ptrace; failures should be fast. */ 2128 if (secure_computing() == -1) 2129 return NO_SYSCALL; 2130 2131 if (test_thread_flag(TIF_SYSCALL_TRACEPOINT)) 2132 trace_sys_enter(regs, regs->syscallno); 2133 2134 audit_syscall_entry(regs->syscallno, regs->orig_x0, regs->regs[1], 2135 regs->regs[2], regs->regs[3]); 2136 2137 return regs->syscallno; 2138 } 2139 2140 void syscall_trace_exit(struct pt_regs *regs) 2141 { 2142 unsigned long flags = read_thread_flags(); 2143 2144 audit_syscall_exit(regs); 2145 2146 if (flags & _TIF_SYSCALL_TRACEPOINT) 2147 trace_sys_exit(regs, syscall_get_return_value(current, regs)); 2148 2149 if (flags & (_TIF_SYSCALL_TRACE | _TIF_SINGLESTEP)) 2150 report_syscall(regs, PTRACE_SYSCALL_EXIT); 2151 2152 rseq_syscall(regs); 2153 } 2154 2155 /* 2156 * SPSR_ELx bits which are always architecturally RES0 per ARM DDI 0487D.a. 2157 * We permit userspace to set SSBS (AArch64 bit 12, AArch32 bit 23) which is 2158 * not described in ARM DDI 0487D.a. 2159 * We treat PAN and UAO as RES0 bits, as they are meaningless at EL0, and may 2160 * be allocated an EL0 meaning in future. 2161 * Userspace cannot use these until they have an architectural meaning. 2162 * Note that this follows the SPSR_ELx format, not the AArch32 PSR format. 2163 * We also reserve IL for the kernel; SS is handled dynamically. 2164 */ 2165 #define SPSR_EL1_AARCH64_RES0_BITS \ 2166 (GENMASK_ULL(63, 32) | GENMASK_ULL(27, 26) | GENMASK_ULL(23, 22) | \ 2167 GENMASK_ULL(20, 13) | GENMASK_ULL(5, 5)) 2168 #define SPSR_EL1_AARCH32_RES0_BITS \ 2169 (GENMASK_ULL(63, 32) | GENMASK_ULL(22, 22) | GENMASK_ULL(20, 20)) 2170 2171 static int valid_compat_regs(struct user_pt_regs *regs) 2172 { 2173 regs->pstate &= ~SPSR_EL1_AARCH32_RES0_BITS; 2174 2175 if (!system_supports_mixed_endian_el0()) { 2176 if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 2177 regs->pstate |= PSR_AA32_E_BIT; 2178 else 2179 regs->pstate &= ~PSR_AA32_E_BIT; 2180 } 2181 2182 if (user_mode(regs) && (regs->pstate & PSR_MODE32_BIT) && 2183 (regs->pstate & PSR_AA32_A_BIT) == 0 && 2184 (regs->pstate & PSR_AA32_I_BIT) == 0 && 2185 (regs->pstate & PSR_AA32_F_BIT) == 0) { 2186 return 1; 2187 } 2188 2189 /* 2190 * Force PSR to a valid 32-bit EL0t, preserving the same bits as 2191 * arch/arm. 2192 */ 2193 regs->pstate &= PSR_AA32_N_BIT | PSR_AA32_Z_BIT | 2194 PSR_AA32_C_BIT | PSR_AA32_V_BIT | 2195 PSR_AA32_Q_BIT | PSR_AA32_IT_MASK | 2196 PSR_AA32_GE_MASK | PSR_AA32_E_BIT | 2197 PSR_AA32_T_BIT; 2198 regs->pstate |= PSR_MODE32_BIT; 2199 2200 return 0; 2201 } 2202 2203 static int valid_native_regs(struct user_pt_regs *regs) 2204 { 2205 regs->pstate &= ~SPSR_EL1_AARCH64_RES0_BITS; 2206 2207 if (user_mode(regs) && !(regs->pstate & PSR_MODE32_BIT) && 2208 (regs->pstate & PSR_D_BIT) == 0 && 2209 (regs->pstate & PSR_A_BIT) == 0 && 2210 (regs->pstate & PSR_I_BIT) == 0 && 2211 (regs->pstate & PSR_F_BIT) == 0) { 2212 return 1; 2213 } 2214 2215 /* Force PSR to a valid 64-bit EL0t */ 2216 regs->pstate &= PSR_N_BIT | PSR_Z_BIT | PSR_C_BIT | PSR_V_BIT; 2217 2218 return 0; 2219 } 2220 2221 /* 2222 * Are the current registers suitable for user mode? (used to maintain 2223 * security in signal handlers) 2224 */ 2225 int valid_user_regs(struct user_pt_regs *regs, struct task_struct *task) 2226 { 2227 /* https://lore.kernel.org/lkml/20191118131525.GA4180@willie-the-truck */ 2228 user_regs_reset_single_step(regs, task); 2229 2230 if (is_compat_thread(task_thread_info(task))) 2231 return valid_compat_regs(regs); 2232 else 2233 return valid_native_regs(regs); 2234 } 2235