xref: /linux/arch/arm64/kernel/process.c (revision db4b0710fae90a4407bfa77b23db396e580b9e23)
1b3901d54SCatalin Marinas /*
2b3901d54SCatalin Marinas  * Based on arch/arm/kernel/process.c
3b3901d54SCatalin Marinas  *
4b3901d54SCatalin Marinas  * Original Copyright (C) 1995  Linus Torvalds
5b3901d54SCatalin Marinas  * Copyright (C) 1996-2000 Russell King - Converted to ARM.
6b3901d54SCatalin Marinas  * Copyright (C) 2012 ARM Ltd.
7b3901d54SCatalin Marinas  *
8b3901d54SCatalin Marinas  * This program is free software; you can redistribute it and/or modify
9b3901d54SCatalin Marinas  * it under the terms of the GNU General Public License version 2 as
10b3901d54SCatalin Marinas  * published by the Free Software Foundation.
11b3901d54SCatalin Marinas  *
12b3901d54SCatalin Marinas  * This program is distributed in the hope that it will be useful,
13b3901d54SCatalin Marinas  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14b3901d54SCatalin Marinas  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15b3901d54SCatalin Marinas  * GNU General Public License for more details.
16b3901d54SCatalin Marinas  *
17b3901d54SCatalin Marinas  * You should have received a copy of the GNU General Public License
18b3901d54SCatalin Marinas  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
19b3901d54SCatalin Marinas  */
20b3901d54SCatalin Marinas 
21b3901d54SCatalin Marinas #include <stdarg.h>
22b3901d54SCatalin Marinas 
23fd92d4a5SAKASHI Takahiro #include <linux/compat.h>
2460c0d45aSArd Biesheuvel #include <linux/efi.h>
25b3901d54SCatalin Marinas #include <linux/export.h>
26b3901d54SCatalin Marinas #include <linux/sched.h>
27b3901d54SCatalin Marinas #include <linux/kernel.h>
28b3901d54SCatalin Marinas #include <linux/mm.h>
29b3901d54SCatalin Marinas #include <linux/stddef.h>
30b3901d54SCatalin Marinas #include <linux/unistd.h>
31b3901d54SCatalin Marinas #include <linux/user.h>
32b3901d54SCatalin Marinas #include <linux/delay.h>
33b3901d54SCatalin Marinas #include <linux/reboot.h>
34b3901d54SCatalin Marinas #include <linux/interrupt.h>
35b3901d54SCatalin Marinas #include <linux/kallsyms.h>
36b3901d54SCatalin Marinas #include <linux/init.h>
37b3901d54SCatalin Marinas #include <linux/cpu.h>
38b3901d54SCatalin Marinas #include <linux/elfcore.h>
39b3901d54SCatalin Marinas #include <linux/pm.h>
40b3901d54SCatalin Marinas #include <linux/tick.h>
41b3901d54SCatalin Marinas #include <linux/utsname.h>
42b3901d54SCatalin Marinas #include <linux/uaccess.h>
43b3901d54SCatalin Marinas #include <linux/random.h>
44b3901d54SCatalin Marinas #include <linux/hw_breakpoint.h>
45b3901d54SCatalin Marinas #include <linux/personality.h>
46b3901d54SCatalin Marinas #include <linux/notifier.h>
47096b3224SJisheng Zhang #include <trace/events/power.h>
48b3901d54SCatalin Marinas 
4957f4959bSJames Morse #include <asm/alternative.h>
50b3901d54SCatalin Marinas #include <asm/compat.h>
51b3901d54SCatalin Marinas #include <asm/cacheflush.h>
52d0854412SJames Morse #include <asm/exec.h>
53ec45d1cfSWill Deacon #include <asm/fpsimd.h>
54ec45d1cfSWill Deacon #include <asm/mmu_context.h>
55b3901d54SCatalin Marinas #include <asm/processor.h>
56b3901d54SCatalin Marinas #include <asm/stacktrace.h>
57b3901d54SCatalin Marinas 
58c0c264aeSLaura Abbott #ifdef CONFIG_CC_STACKPROTECTOR
59c0c264aeSLaura Abbott #include <linux/stackprotector.h>
60c0c264aeSLaura Abbott unsigned long __stack_chk_guard __read_mostly;
61c0c264aeSLaura Abbott EXPORT_SYMBOL(__stack_chk_guard);
62c0c264aeSLaura Abbott #endif
63c0c264aeSLaura Abbott 
64b3901d54SCatalin Marinas /*
65b3901d54SCatalin Marinas  * Function pointers to optional machine specific functions
66b3901d54SCatalin Marinas  */
67b3901d54SCatalin Marinas void (*pm_power_off)(void);
68b3901d54SCatalin Marinas EXPORT_SYMBOL_GPL(pm_power_off);
69b3901d54SCatalin Marinas 
70b0946fc8SCatalin Marinas void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd);
71b3901d54SCatalin Marinas 
72b3901d54SCatalin Marinas /*
73b3901d54SCatalin Marinas  * This is our default idle handler.
74b3901d54SCatalin Marinas  */
750087298fSThomas Gleixner void arch_cpu_idle(void)
76b3901d54SCatalin Marinas {
77b3901d54SCatalin Marinas 	/*
78b3901d54SCatalin Marinas 	 * This should do all the clock switching and wait for interrupt
79b3901d54SCatalin Marinas 	 * tricks
80b3901d54SCatalin Marinas 	 */
81096b3224SJisheng Zhang 	trace_cpu_idle_rcuidle(1, smp_processor_id());
82b3901d54SCatalin Marinas 	cpu_do_idle();
83b3901d54SCatalin Marinas 	local_irq_enable();
84096b3224SJisheng Zhang 	trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
85b3901d54SCatalin Marinas }
86b3901d54SCatalin Marinas 
879327e2c6SMark Rutland #ifdef CONFIG_HOTPLUG_CPU
889327e2c6SMark Rutland void arch_cpu_idle_dead(void)
899327e2c6SMark Rutland {
909327e2c6SMark Rutland        cpu_die();
919327e2c6SMark Rutland }
929327e2c6SMark Rutland #endif
939327e2c6SMark Rutland 
9490f51a09SArun KS /*
9590f51a09SArun KS  * Called by kexec, immediately prior to machine_kexec().
9690f51a09SArun KS  *
9790f51a09SArun KS  * This must completely disable all secondary CPUs; simply causing those CPUs
9890f51a09SArun KS  * to execute e.g. a RAM-based pin loop is not sufficient. This allows the
9990f51a09SArun KS  * kexec'd kernel to use any and all RAM as it sees fit, without having to
10090f51a09SArun KS  * avoid any code or data used by any SW CPU pin loop. The CPU hotplug
10190f51a09SArun KS  * functionality embodied in disable_nonboot_cpus() to achieve this.
10290f51a09SArun KS  */
103b3901d54SCatalin Marinas void machine_shutdown(void)
104b3901d54SCatalin Marinas {
10590f51a09SArun KS 	disable_nonboot_cpus();
106b3901d54SCatalin Marinas }
107b3901d54SCatalin Marinas 
10890f51a09SArun KS /*
10990f51a09SArun KS  * Halting simply requires that the secondary CPUs stop performing any
11090f51a09SArun KS  * activity (executing tasks, handling interrupts). smp_send_stop()
11190f51a09SArun KS  * achieves this.
11290f51a09SArun KS  */
113b3901d54SCatalin Marinas void machine_halt(void)
114b3901d54SCatalin Marinas {
115b9acc49eSArun KS 	local_irq_disable();
11690f51a09SArun KS 	smp_send_stop();
117b3901d54SCatalin Marinas 	while (1);
118b3901d54SCatalin Marinas }
119b3901d54SCatalin Marinas 
12090f51a09SArun KS /*
12190f51a09SArun KS  * Power-off simply requires that the secondary CPUs stop performing any
12290f51a09SArun KS  * activity (executing tasks, handling interrupts). smp_send_stop()
12390f51a09SArun KS  * achieves this. When the system power is turned off, it will take all CPUs
12490f51a09SArun KS  * with it.
12590f51a09SArun KS  */
126b3901d54SCatalin Marinas void machine_power_off(void)
127b3901d54SCatalin Marinas {
128b9acc49eSArun KS 	local_irq_disable();
12990f51a09SArun KS 	smp_send_stop();
130b3901d54SCatalin Marinas 	if (pm_power_off)
131b3901d54SCatalin Marinas 		pm_power_off();
132b3901d54SCatalin Marinas }
133b3901d54SCatalin Marinas 
13490f51a09SArun KS /*
13590f51a09SArun KS  * Restart requires that the secondary CPUs stop performing any activity
13668234df4SMark Rutland  * while the primary CPU resets the system. Systems with multiple CPUs must
13790f51a09SArun KS  * provide a HW restart implementation, to ensure that all CPUs reset at once.
13890f51a09SArun KS  * This is required so that any code running after reset on the primary CPU
13990f51a09SArun KS  * doesn't have to co-ordinate with other CPUs to ensure they aren't still
14090f51a09SArun KS  * executing pre-reset code, and using RAM that the primary CPU's code wishes
14190f51a09SArun KS  * to use. Implementing such co-ordination would be essentially impossible.
14290f51a09SArun KS  */
143b3901d54SCatalin Marinas void machine_restart(char *cmd)
144b3901d54SCatalin Marinas {
145b3901d54SCatalin Marinas 	/* Disable interrupts first */
146b3901d54SCatalin Marinas 	local_irq_disable();
147b9acc49eSArun KS 	smp_send_stop();
148b3901d54SCatalin Marinas 
14960c0d45aSArd Biesheuvel 	/*
15060c0d45aSArd Biesheuvel 	 * UpdateCapsule() depends on the system being reset via
15160c0d45aSArd Biesheuvel 	 * ResetSystem().
15260c0d45aSArd Biesheuvel 	 */
15360c0d45aSArd Biesheuvel 	if (efi_enabled(EFI_RUNTIME_SERVICES))
15460c0d45aSArd Biesheuvel 		efi_reboot(reboot_mode, NULL);
15560c0d45aSArd Biesheuvel 
156b3901d54SCatalin Marinas 	/* Now call the architecture specific reboot code. */
157aa1e8ec1SCatalin Marinas 	if (arm_pm_restart)
158ff701306SMarc Zyngier 		arm_pm_restart(reboot_mode, cmd);
1591c7ffc32SGuenter Roeck 	else
1601c7ffc32SGuenter Roeck 		do_kernel_restart(cmd);
161b3901d54SCatalin Marinas 
162b3901d54SCatalin Marinas 	/*
163b3901d54SCatalin Marinas 	 * Whoops - the architecture was unable to reboot.
164b3901d54SCatalin Marinas 	 */
165b3901d54SCatalin Marinas 	printk("Reboot failed -- System halted\n");
166b3901d54SCatalin Marinas 	while (1);
167b3901d54SCatalin Marinas }
168b3901d54SCatalin Marinas 
169b3901d54SCatalin Marinas void __show_regs(struct pt_regs *regs)
170b3901d54SCatalin Marinas {
1716ca68e80SCatalin Marinas 	int i, top_reg;
1726ca68e80SCatalin Marinas 	u64 lr, sp;
1736ca68e80SCatalin Marinas 
1746ca68e80SCatalin Marinas 	if (compat_user_mode(regs)) {
1756ca68e80SCatalin Marinas 		lr = regs->compat_lr;
1766ca68e80SCatalin Marinas 		sp = regs->compat_sp;
1776ca68e80SCatalin Marinas 		top_reg = 12;
1786ca68e80SCatalin Marinas 	} else {
1796ca68e80SCatalin Marinas 		lr = regs->regs[30];
1806ca68e80SCatalin Marinas 		sp = regs->sp;
1816ca68e80SCatalin Marinas 		top_reg = 29;
1826ca68e80SCatalin Marinas 	}
183b3901d54SCatalin Marinas 
184a43cb95dSTejun Heo 	show_regs_print_info(KERN_DEFAULT);
185b3901d54SCatalin Marinas 	print_symbol("PC is at %s\n", instruction_pointer(regs));
1866ca68e80SCatalin Marinas 	print_symbol("LR is at %s\n", lr);
187b3901d54SCatalin Marinas 	printk("pc : [<%016llx>] lr : [<%016llx>] pstate: %08llx\n",
1886ca68e80SCatalin Marinas 	       regs->pc, lr, regs->pstate);
1896ca68e80SCatalin Marinas 	printk("sp : %016llx\n", sp);
190*db4b0710SMark Rutland 
191*db4b0710SMark Rutland 	i = top_reg;
192*db4b0710SMark Rutland 
193*db4b0710SMark Rutland 	while (i >= 0) {
194b3901d54SCatalin Marinas 		printk("x%-2d: %016llx ", i, regs->regs[i]);
195*db4b0710SMark Rutland 		i--;
196*db4b0710SMark Rutland 
197*db4b0710SMark Rutland 		if (i % 2 == 0) {
198*db4b0710SMark Rutland 			pr_cont("x%-2d: %016llx ", i, regs->regs[i]);
199*db4b0710SMark Rutland 			i--;
200*db4b0710SMark Rutland 		}
201*db4b0710SMark Rutland 
202*db4b0710SMark Rutland 		pr_cont("\n");
203b3901d54SCatalin Marinas 	}
204b3901d54SCatalin Marinas 	printk("\n");
205b3901d54SCatalin Marinas }
206b3901d54SCatalin Marinas 
207b3901d54SCatalin Marinas void show_regs(struct pt_regs * regs)
208b3901d54SCatalin Marinas {
209b3901d54SCatalin Marinas 	printk("\n");
210b3901d54SCatalin Marinas 	__show_regs(regs);
211b3901d54SCatalin Marinas }
212b3901d54SCatalin Marinas 
213eb35bdd7SWill Deacon static void tls_thread_flush(void)
214eb35bdd7SWill Deacon {
215adf75899SMark Rutland 	write_sysreg(0, tpidr_el0);
216eb35bdd7SWill Deacon 
217eb35bdd7SWill Deacon 	if (is_compat_task()) {
218eb35bdd7SWill Deacon 		current->thread.tp_value = 0;
219eb35bdd7SWill Deacon 
220eb35bdd7SWill Deacon 		/*
221eb35bdd7SWill Deacon 		 * We need to ensure ordering between the shadow state and the
222eb35bdd7SWill Deacon 		 * hardware state, so that we don't corrupt the hardware state
223eb35bdd7SWill Deacon 		 * with a stale shadow state during context switch.
224eb35bdd7SWill Deacon 		 */
225eb35bdd7SWill Deacon 		barrier();
226adf75899SMark Rutland 		write_sysreg(0, tpidrro_el0);
227eb35bdd7SWill Deacon 	}
228eb35bdd7SWill Deacon }
229eb35bdd7SWill Deacon 
230b3901d54SCatalin Marinas void flush_thread(void)
231b3901d54SCatalin Marinas {
232b3901d54SCatalin Marinas 	fpsimd_flush_thread();
233eb35bdd7SWill Deacon 	tls_thread_flush();
234b3901d54SCatalin Marinas 	flush_ptrace_hw_breakpoint(current);
235b3901d54SCatalin Marinas }
236b3901d54SCatalin Marinas 
237b3901d54SCatalin Marinas void release_thread(struct task_struct *dead_task)
238b3901d54SCatalin Marinas {
239b3901d54SCatalin Marinas }
240b3901d54SCatalin Marinas 
241b3901d54SCatalin Marinas int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
242b3901d54SCatalin Marinas {
2436eb6c801SJanet Liu 	if (current->mm)
244c51f9269SArd Biesheuvel 		fpsimd_preserve_current_state();
245b3901d54SCatalin Marinas 	*dst = *src;
246b3901d54SCatalin Marinas 	return 0;
247b3901d54SCatalin Marinas }
248b3901d54SCatalin Marinas 
249b3901d54SCatalin Marinas asmlinkage void ret_from_fork(void) asm("ret_from_fork");
250b3901d54SCatalin Marinas 
251b3901d54SCatalin Marinas int copy_thread(unsigned long clone_flags, unsigned long stack_start,
252afa86fc4SAl Viro 		unsigned long stk_sz, struct task_struct *p)
253b3901d54SCatalin Marinas {
254b3901d54SCatalin Marinas 	struct pt_regs *childregs = task_pt_regs(p);
255b3901d54SCatalin Marinas 
256c34501d2SCatalin Marinas 	memset(&p->thread.cpu_context, 0, sizeof(struct cpu_context));
257c34501d2SCatalin Marinas 
2589ac08002SAl Viro 	if (likely(!(p->flags & PF_KTHREAD))) {
2599ac08002SAl Viro 		*childregs = *current_pt_regs();
260b3901d54SCatalin Marinas 		childregs->regs[0] = 0;
261d00a3810SWill Deacon 
262b3901d54SCatalin Marinas 		/*
263b3901d54SCatalin Marinas 		 * Read the current TLS pointer from tpidr_el0 as it may be
264b3901d54SCatalin Marinas 		 * out-of-sync with the saved value.
265b3901d54SCatalin Marinas 		 */
266adf75899SMark Rutland 		*task_user_tls(p) = read_sysreg(tpidr_el0);
267d00a3810SWill Deacon 
268e0fd18ceSAl Viro 		if (stack_start) {
269d00a3810SWill Deacon 			if (is_compat_thread(task_thread_info(p)))
270d00a3810SWill Deacon 				childregs->compat_sp = stack_start;
271d00a3810SWill Deacon 			else
272b3901d54SCatalin Marinas 				childregs->sp = stack_start;
273b3901d54SCatalin Marinas 		}
274d00a3810SWill Deacon 
275c34501d2SCatalin Marinas 		/*
276c34501d2SCatalin Marinas 		 * If a TLS pointer was passed to clone (4th argument), use it
277c34501d2SCatalin Marinas 		 * for the new thread.
278c34501d2SCatalin Marinas 		 */
279b3901d54SCatalin Marinas 		if (clone_flags & CLONE_SETTLS)
280d00a3810SWill Deacon 			p->thread.tp_value = childregs->regs[3];
281c34501d2SCatalin Marinas 	} else {
282c34501d2SCatalin Marinas 		memset(childregs, 0, sizeof(struct pt_regs));
283c34501d2SCatalin Marinas 		childregs->pstate = PSR_MODE_EL1h;
28457f4959bSJames Morse 		if (IS_ENABLED(CONFIG_ARM64_UAO) &&
28557f4959bSJames Morse 		    cpus_have_cap(ARM64_HAS_UAO))
28657f4959bSJames Morse 			childregs->pstate |= PSR_UAO_BIT;
287c34501d2SCatalin Marinas 		p->thread.cpu_context.x19 = stack_start;
288c34501d2SCatalin Marinas 		p->thread.cpu_context.x20 = stk_sz;
289c34501d2SCatalin Marinas 	}
290c34501d2SCatalin Marinas 	p->thread.cpu_context.pc = (unsigned long)ret_from_fork;
291c34501d2SCatalin Marinas 	p->thread.cpu_context.sp = (unsigned long)childregs;
292b3901d54SCatalin Marinas 
293b3901d54SCatalin Marinas 	ptrace_hw_copy_thread(p);
294b3901d54SCatalin Marinas 
295b3901d54SCatalin Marinas 	return 0;
296b3901d54SCatalin Marinas }
297b3901d54SCatalin Marinas 
298b3901d54SCatalin Marinas static void tls_thread_switch(struct task_struct *next)
299b3901d54SCatalin Marinas {
300b3901d54SCatalin Marinas 	unsigned long tpidr, tpidrro;
301b3901d54SCatalin Marinas 
302adf75899SMark Rutland 	tpidr = read_sysreg(tpidr_el0);
303d00a3810SWill Deacon 	*task_user_tls(current) = tpidr;
304b3901d54SCatalin Marinas 
305d00a3810SWill Deacon 	tpidr = *task_user_tls(next);
306d00a3810SWill Deacon 	tpidrro = is_compat_thread(task_thread_info(next)) ?
307d00a3810SWill Deacon 		  next->thread.tp_value : 0;
308b3901d54SCatalin Marinas 
309adf75899SMark Rutland 	write_sysreg(tpidr, tpidr_el0);
310adf75899SMark Rutland 	write_sysreg(tpidrro, tpidrro_el0);
311b3901d54SCatalin Marinas }
312b3901d54SCatalin Marinas 
31357f4959bSJames Morse /* Restore the UAO state depending on next's addr_limit */
314d0854412SJames Morse void uao_thread_switch(struct task_struct *next)
31557f4959bSJames Morse {
316e950631eSCatalin Marinas 	if (IS_ENABLED(CONFIG_ARM64_UAO)) {
317e950631eSCatalin Marinas 		if (task_thread_info(next)->addr_limit == KERNEL_DS)
318e950631eSCatalin Marinas 			asm(ALTERNATIVE("nop", SET_PSTATE_UAO(1), ARM64_HAS_UAO));
31957f4959bSJames Morse 		else
320e950631eSCatalin Marinas 			asm(ALTERNATIVE("nop", SET_PSTATE_UAO(0), ARM64_HAS_UAO));
321e950631eSCatalin Marinas 	}
32257f4959bSJames Morse }
32357f4959bSJames Morse 
324b3901d54SCatalin Marinas /*
325b3901d54SCatalin Marinas  * Thread switching.
326b3901d54SCatalin Marinas  */
327b3901d54SCatalin Marinas struct task_struct *__switch_to(struct task_struct *prev,
328b3901d54SCatalin Marinas 				struct task_struct *next)
329b3901d54SCatalin Marinas {
330b3901d54SCatalin Marinas 	struct task_struct *last;
331b3901d54SCatalin Marinas 
332b3901d54SCatalin Marinas 	fpsimd_thread_switch(next);
333b3901d54SCatalin Marinas 	tls_thread_switch(next);
334b3901d54SCatalin Marinas 	hw_breakpoint_thread_switch(next);
3353325732fSChristopher Covington 	contextidr_thread_switch(next);
33657f4959bSJames Morse 	uao_thread_switch(next);
337b3901d54SCatalin Marinas 
3385108c67cSCatalin Marinas 	/*
3395108c67cSCatalin Marinas 	 * Complete any pending TLB or cache maintenance on this CPU in case
3405108c67cSCatalin Marinas 	 * the thread migrates to a different CPU.
3415108c67cSCatalin Marinas 	 */
34298f7685eSWill Deacon 	dsb(ish);
343b3901d54SCatalin Marinas 
344b3901d54SCatalin Marinas 	/* the actual thread switch */
345b3901d54SCatalin Marinas 	last = cpu_switch_to(prev, next);
346b3901d54SCatalin Marinas 
347b3901d54SCatalin Marinas 	return last;
348b3901d54SCatalin Marinas }
349b3901d54SCatalin Marinas 
350b3901d54SCatalin Marinas unsigned long get_wchan(struct task_struct *p)
351b3901d54SCatalin Marinas {
352b3901d54SCatalin Marinas 	struct stackframe frame;
353408c3658SKonstantin Khlebnikov 	unsigned long stack_page;
354b3901d54SCatalin Marinas 	int count = 0;
355b3901d54SCatalin Marinas 	if (!p || p == current || p->state == TASK_RUNNING)
356b3901d54SCatalin Marinas 		return 0;
357b3901d54SCatalin Marinas 
358b3901d54SCatalin Marinas 	frame.fp = thread_saved_fp(p);
359b3901d54SCatalin Marinas 	frame.sp = thread_saved_sp(p);
360b3901d54SCatalin Marinas 	frame.pc = thread_saved_pc(p);
36120380bb3SAKASHI Takahiro #ifdef CONFIG_FUNCTION_GRAPH_TRACER
36220380bb3SAKASHI Takahiro 	frame.graph = p->curr_ret_stack;
36320380bb3SAKASHI Takahiro #endif
364408c3658SKonstantin Khlebnikov 	stack_page = (unsigned long)task_stack_page(p);
365b3901d54SCatalin Marinas 	do {
366408c3658SKonstantin Khlebnikov 		if (frame.sp < stack_page ||
367408c3658SKonstantin Khlebnikov 		    frame.sp >= stack_page + THREAD_SIZE ||
368fe13f95bSAKASHI Takahiro 		    unwind_frame(p, &frame))
369b3901d54SCatalin Marinas 			return 0;
370b3901d54SCatalin Marinas 		if (!in_sched_functions(frame.pc))
371b3901d54SCatalin Marinas 			return frame.pc;
372b3901d54SCatalin Marinas 	} while (count ++ < 16);
373b3901d54SCatalin Marinas 	return 0;
374b3901d54SCatalin Marinas }
375b3901d54SCatalin Marinas 
376b3901d54SCatalin Marinas unsigned long arch_align_stack(unsigned long sp)
377b3901d54SCatalin Marinas {
378b3901d54SCatalin Marinas 	if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
379b3901d54SCatalin Marinas 		sp -= get_random_int() & ~PAGE_MASK;
380b3901d54SCatalin Marinas 	return sp & ~0xf;
381b3901d54SCatalin Marinas }
382b3901d54SCatalin Marinas 
383b3901d54SCatalin Marinas unsigned long arch_randomize_brk(struct mm_struct *mm)
384b3901d54SCatalin Marinas {
38561462c8aSKees Cook 	if (is_compat_task())
386fa5114c7SJason Cooper 		return randomize_page(mm->brk, 0x02000000);
38761462c8aSKees Cook 	else
388fa5114c7SJason Cooper 		return randomize_page(mm->brk, 0x40000000);
389b3901d54SCatalin Marinas }
390