1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Early cpufeature override framework 4 * 5 * Copyright (C) 2020 Google LLC 6 * Author: Marc Zyngier <maz@kernel.org> 7 */ 8 9 #include <linux/ctype.h> 10 #include <linux/kernel.h> 11 #include <linux/libfdt.h> 12 13 #include <asm/cacheflush.h> 14 #include <asm/cpufeature.h> 15 #include <asm/setup.h> 16 17 #include "pi.h" 18 19 #define FTR_DESC_NAME_LEN 20 20 #define FTR_DESC_FIELD_LEN 10 21 #define FTR_ALIAS_NAME_LEN 30 22 #define FTR_ALIAS_OPTION_LEN 116 23 24 static u64 __boot_status __initdata; 25 26 typedef bool filter_t(u64 val); 27 28 struct ftr_set_desc { 29 char name[FTR_DESC_NAME_LEN]; 30 PREL64(struct arm64_ftr_override, override); 31 struct { 32 char name[FTR_DESC_FIELD_LEN]; 33 u8 shift; 34 u8 width; 35 PREL64(filter_t, filter); 36 } fields[]; 37 }; 38 39 #define FIELD(n, s, f) { .name = n, .shift = s, .width = 4, .filter = f } 40 41 static const struct ftr_set_desc mmfr0 __prel64_initconst = { 42 .name = "id_aa64mmfr0", 43 .override = &id_aa64mmfr0_override, 44 .fields = { 45 FIELD("ecv", ID_AA64MMFR0_EL1_ECV_SHIFT, NULL), 46 {} 47 }, 48 }; 49 50 static bool __init mmfr1_vh_filter(u64 val) 51 { 52 /* 53 * If we ever reach this point while running VHE, we're 54 * guaranteed to be on one of these funky, VHE-stuck CPUs. If 55 * the user was trying to force nVHE on us, proceed with 56 * attitude adjustment. 57 */ 58 return !(__boot_status == (BOOT_CPU_FLAG_E2H | BOOT_CPU_MODE_EL2) && 59 val == 0); 60 } 61 62 static const struct ftr_set_desc mmfr1 __prel64_initconst = { 63 .name = "id_aa64mmfr1", 64 .override = &id_aa64mmfr1_override, 65 .fields = { 66 FIELD("vh", ID_AA64MMFR1_EL1_VH_SHIFT, mmfr1_vh_filter), 67 FIELD("hafdbs", ID_AA64MMFR1_EL1_HAFDBS_SHIFT, NULL), 68 {} 69 }, 70 }; 71 72 73 static bool __init mmfr2_varange_filter(u64 val) 74 { 75 int __maybe_unused feat; 76 77 if (val) 78 return false; 79 80 #ifdef CONFIG_ARM64_LPA2 81 feat = cpuid_feature_extract_signed_field(read_sysreg(id_aa64mmfr0_el1), 82 ID_AA64MMFR0_EL1_TGRAN_SHIFT); 83 if (feat >= ID_AA64MMFR0_EL1_TGRAN_LPA2) { 84 id_aa64mmfr0_override.val |= 85 (ID_AA64MMFR0_EL1_TGRAN_LPA2 - 1) << ID_AA64MMFR0_EL1_TGRAN_SHIFT; 86 id_aa64mmfr0_override.mask |= 0xfU << ID_AA64MMFR0_EL1_TGRAN_SHIFT; 87 88 /* 89 * Override PARange to 48 bits - the override will just be 90 * ignored if the actual PARange is smaller, but this is 91 * unlikely to be the case for LPA2 capable silicon. 92 */ 93 id_aa64mmfr0_override.val |= 94 ID_AA64MMFR0_EL1_PARANGE_48 << ID_AA64MMFR0_EL1_PARANGE_SHIFT; 95 id_aa64mmfr0_override.mask |= 0xfU << ID_AA64MMFR0_EL1_PARANGE_SHIFT; 96 } 97 #endif 98 return true; 99 } 100 101 static const struct ftr_set_desc mmfr2 __prel64_initconst = { 102 .name = "id_aa64mmfr2", 103 .override = &id_aa64mmfr2_override, 104 .fields = { 105 FIELD("varange", ID_AA64MMFR2_EL1_VARange_SHIFT, mmfr2_varange_filter), 106 {} 107 }, 108 }; 109 110 static bool __init pfr0_sve_filter(u64 val) 111 { 112 /* 113 * Disabling SVE also means disabling all the features that 114 * are associated with it. The easiest way to do it is just to 115 * override id_aa64zfr0_el1 to be 0. 116 */ 117 if (!val) { 118 id_aa64zfr0_override.val = 0; 119 id_aa64zfr0_override.mask = GENMASK(63, 0); 120 } 121 122 return true; 123 } 124 125 static const struct ftr_set_desc pfr0 __prel64_initconst = { 126 .name = "id_aa64pfr0", 127 .override = &id_aa64pfr0_override, 128 .fields = { 129 FIELD("sve", ID_AA64PFR0_EL1_SVE_SHIFT, pfr0_sve_filter), 130 FIELD("el0", ID_AA64PFR0_EL1_EL0_SHIFT, NULL), 131 FIELD("mpam", ID_AA64PFR0_EL1_MPAM_SHIFT, NULL), 132 {} 133 }, 134 }; 135 136 static bool __init pfr1_sme_filter(u64 val) 137 { 138 /* 139 * Similarly to SVE, disabling SME also means disabling all 140 * the features that are associated with it. Just set 141 * id_aa64smfr0_el1 to 0 and don't look back. 142 */ 143 if (!val) { 144 id_aa64smfr0_override.val = 0; 145 id_aa64smfr0_override.mask = GENMASK(63, 0); 146 } 147 148 return true; 149 } 150 151 static const struct ftr_set_desc pfr1 __prel64_initconst = { 152 .name = "id_aa64pfr1", 153 .override = &id_aa64pfr1_override, 154 .fields = { 155 FIELD("bt", ID_AA64PFR1_EL1_BT_SHIFT, NULL ), 156 FIELD("gcs", ID_AA64PFR1_EL1_GCS_SHIFT, NULL), 157 FIELD("mte", ID_AA64PFR1_EL1_MTE_SHIFT, NULL), 158 FIELD("sme", ID_AA64PFR1_EL1_SME_SHIFT, pfr1_sme_filter), 159 FIELD("mpam_frac", ID_AA64PFR1_EL1_MPAM_frac_SHIFT, NULL), 160 {} 161 }, 162 }; 163 164 static const struct ftr_set_desc isar1 __prel64_initconst = { 165 .name = "id_aa64isar1", 166 .override = &id_aa64isar1_override, 167 .fields = { 168 FIELD("gpi", ID_AA64ISAR1_EL1_GPI_SHIFT, NULL), 169 FIELD("gpa", ID_AA64ISAR1_EL1_GPA_SHIFT, NULL), 170 FIELD("api", ID_AA64ISAR1_EL1_API_SHIFT, NULL), 171 FIELD("apa", ID_AA64ISAR1_EL1_APA_SHIFT, NULL), 172 {} 173 }, 174 }; 175 176 static const struct ftr_set_desc isar2 __prel64_initconst = { 177 .name = "id_aa64isar2", 178 .override = &id_aa64isar2_override, 179 .fields = { 180 FIELD("gpa3", ID_AA64ISAR2_EL1_GPA3_SHIFT, NULL), 181 FIELD("apa3", ID_AA64ISAR2_EL1_APA3_SHIFT, NULL), 182 FIELD("mops", ID_AA64ISAR2_EL1_MOPS_SHIFT, NULL), 183 {} 184 }, 185 }; 186 187 static const struct ftr_set_desc smfr0 __prel64_initconst = { 188 .name = "id_aa64smfr0", 189 .override = &id_aa64smfr0_override, 190 .fields = { 191 FIELD("smever", ID_AA64SMFR0_EL1_SMEver_SHIFT, NULL), 192 /* FA64 is a one bit field... :-/ */ 193 { "fa64", ID_AA64SMFR0_EL1_FA64_SHIFT, 1, }, 194 {} 195 }, 196 }; 197 198 static bool __init hvhe_filter(u64 val) 199 { 200 u64 mmfr1 = read_sysreg(id_aa64mmfr1_el1); 201 202 return (val == 1 && 203 lower_32_bits(__boot_status) == BOOT_CPU_MODE_EL2 && 204 cpuid_feature_extract_unsigned_field(mmfr1, 205 ID_AA64MMFR1_EL1_VH_SHIFT)); 206 } 207 208 static const struct ftr_set_desc sw_features __prel64_initconst = { 209 .name = "arm64_sw", 210 .override = &arm64_sw_feature_override, 211 .fields = { 212 FIELD("nokaslr", ARM64_SW_FEATURE_OVERRIDE_NOKASLR, NULL), 213 FIELD("hvhe", ARM64_SW_FEATURE_OVERRIDE_HVHE, hvhe_filter), 214 FIELD("rodataoff", ARM64_SW_FEATURE_OVERRIDE_RODATA_OFF, NULL), 215 {} 216 }, 217 }; 218 219 static const 220 PREL64(const struct ftr_set_desc, reg) regs[] __prel64_initconst = { 221 { &mmfr0 }, 222 { &mmfr1 }, 223 { &mmfr2 }, 224 { &pfr0 }, 225 { &pfr1 }, 226 { &isar1 }, 227 { &isar2 }, 228 { &smfr0 }, 229 { &sw_features }, 230 }; 231 232 static const struct { 233 char alias[FTR_ALIAS_NAME_LEN]; 234 char feature[FTR_ALIAS_OPTION_LEN]; 235 } aliases[] __initconst = { 236 { "kvm_arm.mode=nvhe", "arm64_sw.hvhe=0 id_aa64mmfr1.vh=0" }, 237 { "kvm_arm.mode=protected", "arm64_sw.hvhe=1" }, 238 { "arm64.nosve", "id_aa64pfr0.sve=0" }, 239 { "arm64.nosme", "id_aa64pfr1.sme=0" }, 240 { "arm64.nobti", "id_aa64pfr1.bt=0" }, 241 { "arm64.nogcs", "id_aa64pfr1.gcs=0" }, 242 { "arm64.nopauth", 243 "id_aa64isar1.gpi=0 id_aa64isar1.gpa=0 " 244 "id_aa64isar1.api=0 id_aa64isar1.apa=0 " 245 "id_aa64isar2.gpa3=0 id_aa64isar2.apa3=0" }, 246 { "arm64.nomops", "id_aa64isar2.mops=0" }, 247 { "arm64.nomte", "id_aa64pfr1.mte=0" }, 248 { "nokaslr", "arm64_sw.nokaslr=1" }, 249 { "rodata=off", "arm64_sw.rodataoff=1" }, 250 { "arm64.nohaft", "id_aa64mmfr1.hafdbs=2" }, 251 { "arm64.nolva", "id_aa64mmfr2.varange=0" }, 252 { "arm64.no32bit_el0", "id_aa64pfr0.el0=1" }, 253 { "arm64.nompam", "id_aa64pfr0.mpam=0 id_aa64pfr1.mpam_frac=0" }, 254 }; 255 256 static int __init parse_hexdigit(const char *p, u64 *v) 257 { 258 // skip "0x" if it comes next 259 if (p[0] == '0' && tolower(p[1]) == 'x') 260 p += 2; 261 262 // check whether the RHS is a single hex digit 263 if (!isxdigit(p[0]) || (p[1] && !isspace(p[1]))) 264 return -EINVAL; 265 266 *v = tolower(*p) - (isdigit(*p) ? '0' : 'a' - 10); 267 return 0; 268 } 269 270 static int __init find_field(const char *cmdline, char *opt, int len, 271 const struct ftr_set_desc *reg, int f, u64 *v) 272 { 273 int flen = strlen(reg->fields[f].name); 274 275 // append '<fieldname>=' to obtain '<name>.<fieldname>=' 276 memcpy(opt + len, reg->fields[f].name, flen); 277 len += flen; 278 opt[len++] = '='; 279 280 if (memcmp(cmdline, opt, len)) 281 return -1; 282 283 return parse_hexdigit(cmdline + len, v); 284 } 285 286 static void __init match_options(const char *cmdline) 287 { 288 char opt[FTR_DESC_NAME_LEN + FTR_DESC_FIELD_LEN + 2]; 289 int i; 290 291 for (i = 0; i < ARRAY_SIZE(regs); i++) { 292 const struct ftr_set_desc *reg = prel64_pointer(regs[i].reg); 293 struct arm64_ftr_override *override; 294 int len = strlen(reg->name); 295 int f; 296 297 override = prel64_pointer(reg->override); 298 299 // set opt[] to '<name>.' 300 memcpy(opt, reg->name, len); 301 opt[len++] = '.'; 302 303 for (f = 0; reg->fields[f].name[0] != '\0'; f++) { 304 u64 shift = reg->fields[f].shift; 305 u64 width = reg->fields[f].width ?: 4; 306 u64 mask = GENMASK_ULL(shift + width - 1, shift); 307 bool (*filter)(u64 val); 308 u64 v; 309 310 if (find_field(cmdline, opt, len, reg, f, &v)) 311 continue; 312 313 /* 314 * If an override gets filtered out, advertise 315 * it by setting the value to the all-ones while 316 * clearing the mask... Yes, this is fragile. 317 */ 318 filter = prel64_pointer(reg->fields[f].filter); 319 if (filter && !filter(v)) { 320 override->val |= mask; 321 override->mask &= ~mask; 322 continue; 323 } 324 325 override->val &= ~mask; 326 override->val |= (v << shift) & mask; 327 override->mask |= mask; 328 329 return; 330 } 331 } 332 } 333 334 static __init void __parse_cmdline(const char *cmdline, bool parse_aliases) 335 { 336 do { 337 char buf[256]; 338 size_t len; 339 int i; 340 341 cmdline = skip_spaces(cmdline); 342 343 /* terminate on "--" appearing on the command line by itself */ 344 if (cmdline[0] == '-' && cmdline[1] == '-' && isspace(cmdline[2])) 345 return; 346 347 for (len = 0; cmdline[len] && !isspace(cmdline[len]); len++) { 348 if (len >= sizeof(buf) - 1) 349 break; 350 if (cmdline[len] == '-') 351 buf[len] = '_'; 352 else 353 buf[len] = cmdline[len]; 354 } 355 if (!len) 356 return; 357 358 buf[len] = 0; 359 360 cmdline += len; 361 362 match_options(buf); 363 364 for (i = 0; parse_aliases && i < ARRAY_SIZE(aliases); i++) 365 if (!memcmp(buf, aliases[i].alias, len + 1)) 366 __parse_cmdline(aliases[i].feature, false); 367 } while (1); 368 } 369 370 static __init const u8 *get_bootargs_cmdline(const void *fdt, int node) 371 { 372 static char const bootargs[] __initconst = "bootargs"; 373 const u8 *prop; 374 375 if (node < 0) 376 return NULL; 377 378 prop = fdt_getprop(fdt, node, bootargs, NULL); 379 if (!prop) 380 return NULL; 381 382 return strlen(prop) ? prop : NULL; 383 } 384 385 static __init void parse_cmdline(const void *fdt, int chosen) 386 { 387 static char const cmdline[] __initconst = CONFIG_CMDLINE; 388 const u8 *prop = get_bootargs_cmdline(fdt, chosen); 389 390 if (IS_ENABLED(CONFIG_CMDLINE_FORCE) || !prop) 391 __parse_cmdline(cmdline, true); 392 393 if (!IS_ENABLED(CONFIG_CMDLINE_FORCE) && prop) 394 __parse_cmdline(prop, true); 395 } 396 397 void __init init_feature_override(u64 boot_status, const void *fdt, 398 int chosen) 399 { 400 struct arm64_ftr_override *override; 401 const struct ftr_set_desc *reg; 402 int i; 403 404 for (i = 0; i < ARRAY_SIZE(regs); i++) { 405 reg = prel64_pointer(regs[i].reg); 406 override = prel64_pointer(reg->override); 407 408 override->val = 0; 409 override->mask = 0; 410 } 411 412 __boot_status = boot_status; 413 414 parse_cmdline(fdt, chosen); 415 416 for (i = 0; i < ARRAY_SIZE(regs); i++) { 417 reg = prel64_pointer(regs[i].reg); 418 override = prel64_pointer(reg->override); 419 dcache_clean_inval_poc((unsigned long)override, 420 (unsigned long)(override + 1)); 421 } 422 } 423 424 char * __init skip_spaces(const char *str) 425 { 426 while (isspace(*str)) 427 ++str; 428 return (char *)str; 429 } 430