1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Early cpufeature override framework 4 * 5 * Copyright (C) 2020 Google LLC 6 * Author: Marc Zyngier <maz@kernel.org> 7 */ 8 9 #include <linux/ctype.h> 10 #include <linux/kernel.h> 11 #include <linux/libfdt.h> 12 13 #include <asm/cacheflush.h> 14 #include <asm/cpufeature.h> 15 #include <asm/setup.h> 16 17 #include "pi.h" 18 19 #define FTR_DESC_NAME_LEN 20 20 #define FTR_DESC_FIELD_LEN 10 21 #define FTR_ALIAS_NAME_LEN 30 22 #define FTR_ALIAS_OPTION_LEN 116 23 24 static u64 __boot_status __initdata; 25 26 typedef bool filter_t(u64 val); 27 28 struct ftr_set_desc { 29 char name[FTR_DESC_NAME_LEN]; 30 PREL64(struct arm64_ftr_override, override); 31 struct { 32 char name[FTR_DESC_FIELD_LEN]; 33 u8 shift; 34 u8 width; 35 PREL64(filter_t, filter); 36 } fields[]; 37 }; 38 39 #define FIELD(n, s, f) { .name = n, .shift = s, .width = 4, .filter = f } 40 41 static const struct ftr_set_desc mmfr0 __prel64_initconst = { 42 .name = "id_aa64mmfr0", 43 .override = &id_aa64mmfr0_override, 44 .fields = { 45 FIELD("ecv", ID_AA64MMFR0_EL1_ECV_SHIFT, NULL), 46 {} 47 }, 48 }; 49 50 static bool __init mmfr1_vh_filter(u64 val) 51 { 52 /* 53 * If we ever reach this point while running VHE, we're 54 * guaranteed to be on one of these funky, VHE-stuck CPUs. If 55 * the user was trying to force nVHE on us, proceed with 56 * attitude adjustment. 57 */ 58 return !(__boot_status == (BOOT_CPU_FLAG_E2H | BOOT_CPU_MODE_EL2) && 59 val == 0); 60 } 61 62 static const struct ftr_set_desc mmfr1 __prel64_initconst = { 63 .name = "id_aa64mmfr1", 64 .override = &id_aa64mmfr1_override, 65 .fields = { 66 FIELD("vh", ID_AA64MMFR1_EL1_VH_SHIFT, mmfr1_vh_filter), 67 FIELD("hafdbs", ID_AA64MMFR1_EL1_HAFDBS_SHIFT, NULL), 68 {} 69 }, 70 }; 71 72 73 static bool __init mmfr2_varange_filter(u64 val) 74 { 75 int __maybe_unused feat; 76 77 if (val) 78 return false; 79 80 #ifdef CONFIG_ARM64_LPA2 81 feat = cpuid_feature_extract_signed_field(read_sysreg(id_aa64mmfr0_el1), 82 ID_AA64MMFR0_EL1_TGRAN_SHIFT); 83 if (feat >= ID_AA64MMFR0_EL1_TGRAN_LPA2) { 84 id_aa64mmfr0_override.val |= 85 (ID_AA64MMFR0_EL1_TGRAN_LPA2 - 1) << ID_AA64MMFR0_EL1_TGRAN_SHIFT; 86 id_aa64mmfr0_override.mask |= 0xfU << ID_AA64MMFR0_EL1_TGRAN_SHIFT; 87 88 /* 89 * Override PARange to 48 bits - the override will just be 90 * ignored if the actual PARange is smaller, but this is 91 * unlikely to be the case for LPA2 capable silicon. 92 */ 93 id_aa64mmfr0_override.val |= 94 ID_AA64MMFR0_EL1_PARANGE_48 << ID_AA64MMFR0_EL1_PARANGE_SHIFT; 95 id_aa64mmfr0_override.mask |= 0xfU << ID_AA64MMFR0_EL1_PARANGE_SHIFT; 96 } 97 #endif 98 return true; 99 } 100 101 static const struct ftr_set_desc mmfr2 __prel64_initconst = { 102 .name = "id_aa64mmfr2", 103 .override = &id_aa64mmfr2_override, 104 .fields = { 105 FIELD("varange", ID_AA64MMFR2_EL1_VARange_SHIFT, mmfr2_varange_filter), 106 {} 107 }, 108 }; 109 110 static const struct ftr_set_desc mmfr4 __prel64_initconst = { 111 .name = "id_aa64mmfr4", 112 .override = &id_aa64mmfr4_override, 113 .fields = { 114 FIELD("nv_frac", ID_AA64MMFR4_EL1_NV_frac_SHIFT, NULL), 115 {} 116 }, 117 }; 118 119 static bool __init pfr0_sve_filter(u64 val) 120 { 121 /* 122 * Disabling SVE also means disabling all the features that 123 * are associated with it. The easiest way to do it is just to 124 * override id_aa64zfr0_el1 to be 0. 125 */ 126 if (!val) { 127 id_aa64zfr0_override.val = 0; 128 id_aa64zfr0_override.mask = GENMASK(63, 0); 129 } 130 131 return true; 132 } 133 134 static const struct ftr_set_desc pfr0 __prel64_initconst = { 135 .name = "id_aa64pfr0", 136 .override = &id_aa64pfr0_override, 137 .fields = { 138 FIELD("sve", ID_AA64PFR0_EL1_SVE_SHIFT, pfr0_sve_filter), 139 FIELD("el0", ID_AA64PFR0_EL1_EL0_SHIFT, NULL), 140 FIELD("mpam", ID_AA64PFR0_EL1_MPAM_SHIFT, NULL), 141 {} 142 }, 143 }; 144 145 static bool __init pfr1_sme_filter(u64 val) 146 { 147 /* 148 * Similarly to SVE, disabling SME also means disabling all 149 * the features that are associated with it. Just set 150 * id_aa64smfr0_el1 to 0 and don't look back. 151 */ 152 if (!val) { 153 id_aa64smfr0_override.val = 0; 154 id_aa64smfr0_override.mask = GENMASK(63, 0); 155 } 156 157 return true; 158 } 159 160 static const struct ftr_set_desc pfr1 __prel64_initconst = { 161 .name = "id_aa64pfr1", 162 .override = &id_aa64pfr1_override, 163 .fields = { 164 FIELD("bt", ID_AA64PFR1_EL1_BT_SHIFT, NULL ), 165 FIELD("gcs", ID_AA64PFR1_EL1_GCS_SHIFT, NULL), 166 FIELD("mte", ID_AA64PFR1_EL1_MTE_SHIFT, NULL), 167 FIELD("sme", ID_AA64PFR1_EL1_SME_SHIFT, pfr1_sme_filter), 168 FIELD("mpam_frac", ID_AA64PFR1_EL1_MPAM_frac_SHIFT, NULL), 169 {} 170 }, 171 }; 172 173 static const struct ftr_set_desc isar1 __prel64_initconst = { 174 .name = "id_aa64isar1", 175 .override = &id_aa64isar1_override, 176 .fields = { 177 FIELD("gpi", ID_AA64ISAR1_EL1_GPI_SHIFT, NULL), 178 FIELD("gpa", ID_AA64ISAR1_EL1_GPA_SHIFT, NULL), 179 FIELD("api", ID_AA64ISAR1_EL1_API_SHIFT, NULL), 180 FIELD("apa", ID_AA64ISAR1_EL1_APA_SHIFT, NULL), 181 {} 182 }, 183 }; 184 185 static const struct ftr_set_desc isar2 __prel64_initconst = { 186 .name = "id_aa64isar2", 187 .override = &id_aa64isar2_override, 188 .fields = { 189 FIELD("gpa3", ID_AA64ISAR2_EL1_GPA3_SHIFT, NULL), 190 FIELD("apa3", ID_AA64ISAR2_EL1_APA3_SHIFT, NULL), 191 FIELD("mops", ID_AA64ISAR2_EL1_MOPS_SHIFT, NULL), 192 {} 193 }, 194 }; 195 196 static const struct ftr_set_desc smfr0 __prel64_initconst = { 197 .name = "id_aa64smfr0", 198 .override = &id_aa64smfr0_override, 199 .fields = { 200 FIELD("smever", ID_AA64SMFR0_EL1_SMEver_SHIFT, NULL), 201 /* FA64 is a one bit field... :-/ */ 202 { "fa64", ID_AA64SMFR0_EL1_FA64_SHIFT, 1, }, 203 {} 204 }, 205 }; 206 207 static bool __init hvhe_filter(u64 val) 208 { 209 u64 mmfr1 = read_sysreg(id_aa64mmfr1_el1); 210 211 return (val == 1 && 212 lower_32_bits(__boot_status) == BOOT_CPU_MODE_EL2 && 213 cpuid_feature_extract_unsigned_field(mmfr1, 214 ID_AA64MMFR1_EL1_VH_SHIFT)); 215 } 216 217 static const struct ftr_set_desc sw_features __prel64_initconst = { 218 .name = "arm64_sw", 219 .override = &arm64_sw_feature_override, 220 .fields = { 221 FIELD("nokaslr", ARM64_SW_FEATURE_OVERRIDE_NOKASLR, NULL), 222 FIELD("hvhe", ARM64_SW_FEATURE_OVERRIDE_HVHE, hvhe_filter), 223 FIELD("rodataoff", ARM64_SW_FEATURE_OVERRIDE_RODATA_OFF, NULL), 224 {} 225 }, 226 }; 227 228 static const 229 PREL64(const struct ftr_set_desc, reg) regs[] __prel64_initconst = { 230 { &mmfr0 }, 231 { &mmfr1 }, 232 { &mmfr2 }, 233 { &mmfr4 }, 234 { &pfr0 }, 235 { &pfr1 }, 236 { &isar1 }, 237 { &isar2 }, 238 { &smfr0 }, 239 { &sw_features }, 240 }; 241 242 static const struct { 243 char alias[FTR_ALIAS_NAME_LEN]; 244 char feature[FTR_ALIAS_OPTION_LEN]; 245 } aliases[] __initconst = { 246 { "kvm_arm.mode=nvhe", "arm64_sw.hvhe=0 id_aa64mmfr1.vh=0" }, 247 { "kvm_arm.mode=protected", "arm64_sw.hvhe=1" }, 248 { "arm64.nosve", "id_aa64pfr0.sve=0" }, 249 { "arm64.nosme", "id_aa64pfr1.sme=0" }, 250 { "arm64.nobti", "id_aa64pfr1.bt=0" }, 251 { "arm64.nogcs", "id_aa64pfr1.gcs=0" }, 252 { "arm64.nopauth", 253 "id_aa64isar1.gpi=0 id_aa64isar1.gpa=0 " 254 "id_aa64isar1.api=0 id_aa64isar1.apa=0 " 255 "id_aa64isar2.gpa3=0 id_aa64isar2.apa3=0" }, 256 { "arm64.nomops", "id_aa64isar2.mops=0" }, 257 { "arm64.nomte", "id_aa64pfr1.mte=0" }, 258 { "nokaslr", "arm64_sw.nokaslr=1" }, 259 { "rodata=off", "arm64_sw.rodataoff=1" }, 260 { "arm64.nohaft", "id_aa64mmfr1.hafdbs=2" }, 261 { "arm64.nolva", "id_aa64mmfr2.varange=0" }, 262 { "arm64.no32bit_el0", "id_aa64pfr0.el0=1" }, 263 { "arm64.nompam", "id_aa64pfr0.mpam=0 id_aa64pfr1.mpam_frac=0" }, 264 }; 265 266 static int __init parse_hexdigit(const char *p, u64 *v) 267 { 268 // skip "0x" if it comes next 269 if (p[0] == '0' && tolower(p[1]) == 'x') 270 p += 2; 271 272 // check whether the RHS is a single hex digit 273 if (!isxdigit(p[0]) || (p[1] && !isspace(p[1]))) 274 return -EINVAL; 275 276 *v = tolower(*p) - (isdigit(*p) ? '0' : 'a' - 10); 277 return 0; 278 } 279 280 static int __init find_field(const char *cmdline, char *opt, int len, 281 const struct ftr_set_desc *reg, int f, u64 *v) 282 { 283 int flen = strlen(reg->fields[f].name); 284 285 // append '<fieldname>=' to obtain '<name>.<fieldname>=' 286 memcpy(opt + len, reg->fields[f].name, flen); 287 len += flen; 288 opt[len++] = '='; 289 290 if (memcmp(cmdline, opt, len)) 291 return -1; 292 293 return parse_hexdigit(cmdline + len, v); 294 } 295 296 static void __init match_options(const char *cmdline) 297 { 298 char opt[FTR_DESC_NAME_LEN + FTR_DESC_FIELD_LEN + 2]; 299 int i; 300 301 for (i = 0; i < ARRAY_SIZE(regs); i++) { 302 const struct ftr_set_desc *reg = prel64_pointer(regs[i].reg); 303 struct arm64_ftr_override *override; 304 int len = strlen(reg->name); 305 int f; 306 307 override = prel64_pointer(reg->override); 308 309 // set opt[] to '<name>.' 310 memcpy(opt, reg->name, len); 311 opt[len++] = '.'; 312 313 for (f = 0; reg->fields[f].name[0] != '\0'; f++) { 314 u64 shift = reg->fields[f].shift; 315 u64 width = reg->fields[f].width ?: 4; 316 u64 mask = GENMASK_ULL(shift + width - 1, shift); 317 bool (*filter)(u64 val); 318 u64 v; 319 320 if (find_field(cmdline, opt, len, reg, f, &v)) 321 continue; 322 323 /* 324 * If an override gets filtered out, advertise 325 * it by setting the value to the all-ones while 326 * clearing the mask... Yes, this is fragile. 327 */ 328 filter = prel64_pointer(reg->fields[f].filter); 329 if (filter && !filter(v)) { 330 override->val |= mask; 331 override->mask &= ~mask; 332 continue; 333 } 334 335 override->val &= ~mask; 336 override->val |= (v << shift) & mask; 337 override->mask |= mask; 338 339 return; 340 } 341 } 342 } 343 344 static __init void __parse_cmdline(const char *cmdline, bool parse_aliases) 345 { 346 do { 347 char buf[256]; 348 size_t len; 349 int i; 350 351 cmdline = skip_spaces(cmdline); 352 353 /* terminate on "--" appearing on the command line by itself */ 354 if (cmdline[0] == '-' && cmdline[1] == '-' && isspace(cmdline[2])) 355 return; 356 357 for (len = 0; cmdline[len] && !isspace(cmdline[len]); len++) { 358 if (len >= sizeof(buf) - 1) 359 break; 360 if (cmdline[len] == '-') 361 buf[len] = '_'; 362 else 363 buf[len] = cmdline[len]; 364 } 365 if (!len) 366 return; 367 368 buf[len] = 0; 369 370 cmdline += len; 371 372 match_options(buf); 373 374 for (i = 0; parse_aliases && i < ARRAY_SIZE(aliases); i++) 375 if (!memcmp(buf, aliases[i].alias, len + 1)) 376 __parse_cmdline(aliases[i].feature, false); 377 } while (1); 378 } 379 380 static __init const u8 *get_bootargs_cmdline(const void *fdt, int node) 381 { 382 static char const bootargs[] __initconst = "bootargs"; 383 const u8 *prop; 384 385 if (node < 0) 386 return NULL; 387 388 prop = fdt_getprop(fdt, node, bootargs, NULL); 389 if (!prop) 390 return NULL; 391 392 return strlen(prop) ? prop : NULL; 393 } 394 395 static __init void parse_cmdline(const void *fdt, int chosen) 396 { 397 static char const cmdline[] __initconst = CONFIG_CMDLINE; 398 const u8 *prop = get_bootargs_cmdline(fdt, chosen); 399 400 if (IS_ENABLED(CONFIG_CMDLINE_FORCE) || !prop) 401 __parse_cmdline(cmdline, true); 402 403 if (!IS_ENABLED(CONFIG_CMDLINE_FORCE) && prop) 404 __parse_cmdline(prop, true); 405 } 406 407 void __init init_feature_override(u64 boot_status, const void *fdt, 408 int chosen) 409 { 410 struct arm64_ftr_override *override; 411 const struct ftr_set_desc *reg; 412 int i; 413 414 for (i = 0; i < ARRAY_SIZE(regs); i++) { 415 reg = prel64_pointer(regs[i].reg); 416 override = prel64_pointer(reg->override); 417 418 override->val = 0; 419 override->mask = 0; 420 } 421 422 __boot_status = boot_status; 423 424 parse_cmdline(fdt, chosen); 425 426 for (i = 0; i < ARRAY_SIZE(regs); i++) { 427 reg = prel64_pointer(regs[i].reg); 428 override = prel64_pointer(reg->override); 429 dcache_clean_inval_poc((unsigned long)override, 430 (unsigned long)(override + 1)); 431 } 432 } 433 434 char * __init skip_spaces(const char *str) 435 { 436 while (isspace(*str)) 437 ++str; 438 return (char *)str; 439 } 440