1 // SPDX-License-Identifier: GPL-2.0-only 2 #include <linux/kernel.h> 3 #include <linux/mm.h> 4 #include <linux/smp.h> 5 #include <linux/spinlock.h> 6 #include <linux/stop_machine.h> 7 #include <linux/uaccess.h> 8 9 #include <asm/cacheflush.h> 10 #include <asm/fixmap.h> 11 #include <asm/insn.h> 12 #include <asm/kprobes.h> 13 #include <asm/text-patching.h> 14 #include <asm/sections.h> 15 16 static DEFINE_RAW_SPINLOCK(patch_lock); 17 18 static bool is_exit_text(unsigned long addr) 19 { 20 /* discarded with init text/data */ 21 return system_state < SYSTEM_RUNNING && 22 addr >= (unsigned long)__exittext_begin && 23 addr < (unsigned long)__exittext_end; 24 } 25 26 static bool is_image_text(unsigned long addr) 27 { 28 return core_kernel_text(addr) || is_exit_text(addr); 29 } 30 31 static void __kprobes *patch_map(void *addr, int fixmap) 32 { 33 phys_addr_t phys; 34 35 if (is_image_text((unsigned long)addr)) { 36 phys = __pa_symbol(addr); 37 } else { 38 struct page *page = vmalloc_to_page(addr); 39 BUG_ON(!page); 40 phys = page_to_phys(page) + offset_in_page(addr); 41 } 42 43 return (void *)set_fixmap_offset(fixmap, phys); 44 } 45 46 static void __kprobes patch_unmap(int fixmap) 47 { 48 clear_fixmap(fixmap); 49 } 50 /* 51 * In ARMv8-A, A64 instructions have a fixed length of 32 bits and are always 52 * little-endian. 53 */ 54 int __kprobes aarch64_insn_read(void *addr, u32 *insnp) 55 { 56 int ret; 57 __le32 val; 58 59 ret = copy_from_kernel_nofault(&val, addr, AARCH64_INSN_SIZE); 60 if (!ret) 61 *insnp = le32_to_cpu(val); 62 63 return ret; 64 } 65 66 static int __kprobes __aarch64_insn_write(void *addr, __le32 insn) 67 { 68 void *waddr = addr; 69 unsigned long flags = 0; 70 int ret; 71 72 raw_spin_lock_irqsave(&patch_lock, flags); 73 waddr = patch_map(addr, FIX_TEXT_POKE0); 74 75 ret = copy_to_kernel_nofault(waddr, &insn, AARCH64_INSN_SIZE); 76 77 patch_unmap(FIX_TEXT_POKE0); 78 raw_spin_unlock_irqrestore(&patch_lock, flags); 79 80 return ret; 81 } 82 83 int __kprobes aarch64_insn_write(void *addr, u32 insn) 84 { 85 return __aarch64_insn_write(addr, cpu_to_le32(insn)); 86 } 87 88 noinstr int aarch64_insn_write_literal_u64(void *addr, u64 val) 89 { 90 u64 *waddr; 91 unsigned long flags; 92 int ret; 93 94 raw_spin_lock_irqsave(&patch_lock, flags); 95 waddr = patch_map(addr, FIX_TEXT_POKE0); 96 97 ret = copy_to_kernel_nofault(waddr, &val, sizeof(val)); 98 99 patch_unmap(FIX_TEXT_POKE0); 100 raw_spin_unlock_irqrestore(&patch_lock, flags); 101 102 return ret; 103 } 104 105 typedef void text_poke_f(void *dst, void *src, size_t patched, size_t len); 106 107 static void *__text_poke(text_poke_f func, void *addr, void *src, size_t len) 108 { 109 unsigned long flags; 110 size_t patched = 0; 111 size_t size; 112 void *waddr; 113 void *ptr; 114 115 raw_spin_lock_irqsave(&patch_lock, flags); 116 117 while (patched < len) { 118 ptr = addr + patched; 119 size = min(PAGE_SIZE - offset_in_page(ptr), len - patched); 120 121 waddr = patch_map(ptr, FIX_TEXT_POKE0); 122 func(waddr, src, patched, size); 123 patch_unmap(FIX_TEXT_POKE0); 124 125 patched += size; 126 } 127 raw_spin_unlock_irqrestore(&patch_lock, flags); 128 129 flush_icache_range((uintptr_t)addr, (uintptr_t)addr + len); 130 131 return addr; 132 } 133 134 static void text_poke_memcpy(void *dst, void *src, size_t patched, size_t len) 135 { 136 copy_to_kernel_nofault(dst, src + patched, len); 137 } 138 139 static void text_poke_memset(void *dst, void *src, size_t patched, size_t len) 140 { 141 u32 c = *(u32 *)src; 142 143 memset32(dst, c, len / 4); 144 } 145 146 /** 147 * aarch64_insn_copy - Copy instructions into (an unused part of) RX memory 148 * @dst: address to modify 149 * @src: source of the copy 150 * @len: length to copy 151 * 152 * Useful for JITs to dump new code blocks into unused regions of RX memory. 153 */ 154 noinstr void *aarch64_insn_copy(void *dst, void *src, size_t len) 155 { 156 /* A64 instructions must be word aligned */ 157 if ((uintptr_t)dst & 0x3) 158 return NULL; 159 160 return __text_poke(text_poke_memcpy, dst, src, len); 161 } 162 163 /** 164 * aarch64_insn_set - memset for RX memory regions. 165 * @dst: address to modify 166 * @insn: value to set 167 * @len: length of memory region. 168 * 169 * Useful for JITs to fill regions of RX memory with illegal instructions. 170 */ 171 noinstr void *aarch64_insn_set(void *dst, u32 insn, size_t len) 172 { 173 if ((uintptr_t)dst & 0x3) 174 return NULL; 175 176 return __text_poke(text_poke_memset, dst, &insn, len); 177 } 178 179 int __kprobes aarch64_insn_patch_text_nosync(void *addr, u32 insn) 180 { 181 u32 *tp = addr; 182 int ret; 183 184 /* A64 instructions must be word aligned */ 185 if ((uintptr_t)tp & 0x3) 186 return -EINVAL; 187 188 ret = aarch64_insn_write(tp, insn); 189 if (ret == 0) 190 caches_clean_inval_pou((uintptr_t)tp, 191 (uintptr_t)tp + AARCH64_INSN_SIZE); 192 193 return ret; 194 } 195 196 struct aarch64_insn_patch { 197 void **text_addrs; 198 u32 *new_insns; 199 int insn_cnt; 200 atomic_t cpu_count; 201 }; 202 203 static int __kprobes aarch64_insn_patch_text_cb(void *arg) 204 { 205 int i, ret = 0; 206 struct aarch64_insn_patch *pp = arg; 207 208 /* The last CPU becomes master */ 209 if (atomic_inc_return(&pp->cpu_count) == num_online_cpus()) { 210 for (i = 0; ret == 0 && i < pp->insn_cnt; i++) 211 ret = aarch64_insn_patch_text_nosync(pp->text_addrs[i], 212 pp->new_insns[i]); 213 /* Notify other processors with an additional increment. */ 214 atomic_inc(&pp->cpu_count); 215 } else { 216 while (atomic_read(&pp->cpu_count) <= num_online_cpus()) 217 cpu_relax(); 218 isb(); 219 } 220 221 return ret; 222 } 223 224 int __kprobes aarch64_insn_patch_text(void *addrs[], u32 insns[], int cnt) 225 { 226 struct aarch64_insn_patch patch = { 227 .text_addrs = addrs, 228 .new_insns = insns, 229 .insn_cnt = cnt, 230 .cpu_count = ATOMIC_INIT(0), 231 }; 232 233 if (cnt <= 0) 234 return -EINVAL; 235 236 return stop_machine_cpuslocked(aarch64_insn_patch_text_cb, &patch, 237 cpu_online_mask); 238 } 239